2 * SPDX-License-Identifier: BSD-4-Clause
4 * Copyright (c) 1991 Regents of the University of California.
6 * Copyright (c) 1994 John S. Dyson
8 * Copyright (c) 1994 David Greenman
10 * Copyright (c) 2003 Peter Wemm
11 * All rights reserved.
12 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
13 * All rights reserved.
15 * This code is derived from software contributed to Berkeley by
16 * the Systems Programming Group of the University of Utah Computer
17 * Science Department and William Jolitz of UUNET Technologies Inc.
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions
22 * 1. Redistributions of source code must retain the above copyright
23 * notice, this list of conditions and the following disclaimer.
24 * 2. Redistributions in binary form must reproduce the above copyright
25 * notice, this list of conditions and the following disclaimer in the
26 * documentation and/or other materials provided with the distribution.
27 * 3. All advertising materials mentioning features or use of this software
28 * must display the following acknowledgement:
29 * This product includes software developed by the University of
30 * California, Berkeley and its contributors.
31 * 4. Neither the name of the University nor the names of its contributors
32 * may be used to endorse or promote products derived from this software
33 * without specific prior written permission.
35 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
36 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
37 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
38 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
39 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
40 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
41 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
42 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
43 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
44 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
47 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
50 * Copyright (c) 2003 Networks Associates Technology, Inc.
51 * Copyright (c) 2014-2020 The FreeBSD Foundation
52 * All rights reserved.
54 * This software was developed for the FreeBSD Project by Jake Burkholder,
55 * Safeport Network Services, and Network Associates Laboratories, the
56 * Security Research Division of Network Associates, Inc. under
57 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
58 * CHATS research program.
60 * Portions of this software were developed by
61 * Konstantin Belousov <kib@FreeBSD.org> under sponsorship from
62 * the FreeBSD Foundation.
64 * Redistribution and use in source and binary forms, with or without
65 * modification, are permitted provided that the following conditions
67 * 1. Redistributions of source code must retain the above copyright
68 * notice, this list of conditions and the following disclaimer.
69 * 2. Redistributions in binary form must reproduce the above copyright
70 * notice, this list of conditions and the following disclaimer in the
71 * documentation and/or other materials provided with the distribution.
73 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
74 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
77 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
78 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
79 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
80 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
81 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
82 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
86 #define AMD64_NPT_AWARE
88 #include <sys/cdefs.h>
89 __FBSDID("$FreeBSD$");
92 * Manages physical address maps.
94 * Since the information managed by this module is
95 * also stored by the logical address mapping module,
96 * this module may throw away valid virtual-to-physical
97 * mappings at almost any time. However, invalidations
98 * of virtual-to-physical mappings must be done as
101 * In order to cope with hardware architectures which
102 * make virtual-to-physical map invalidates expensive,
103 * this module may delay invalidate or reduced protection
104 * operations until such time as they are actually
105 * necessary. This module is given full information as
106 * to which processors are currently using which maps,
107 * and to when physical maps must be made correct.
111 #include "opt_pmap.h"
114 #include <sys/param.h>
115 #include <sys/bitstring.h>
117 #include <sys/systm.h>
118 #include <sys/kernel.h>
120 #include <sys/lock.h>
121 #include <sys/malloc.h>
122 #include <sys/mman.h>
123 #include <sys/mutex.h>
124 #include <sys/proc.h>
125 #include <sys/rangeset.h>
126 #include <sys/rwlock.h>
127 #include <sys/sbuf.h>
129 #include <sys/turnstile.h>
130 #include <sys/vmem.h>
131 #include <sys/vmmeter.h>
132 #include <sys/sched.h>
133 #include <sys/sysctl.h>
141 #include <vm/vm_param.h>
142 #include <vm/vm_kern.h>
143 #include <vm/vm_page.h>
144 #include <vm/vm_map.h>
145 #include <vm/vm_object.h>
146 #include <vm/vm_extern.h>
147 #include <vm/vm_pageout.h>
148 #include <vm/vm_pager.h>
149 #include <vm/vm_phys.h>
150 #include <vm/vm_radix.h>
151 #include <vm/vm_reserv.h>
152 #include <vm/vm_dumpset.h>
155 #include <machine/intr_machdep.h>
156 #include <x86/apicvar.h>
157 #include <x86/ifunc.h>
158 #include <machine/cpu.h>
159 #include <machine/cputypes.h>
160 #include <machine/md_var.h>
161 #include <machine/pcb.h>
162 #include <machine/specialreg.h>
164 #include <machine/smp.h>
166 #include <machine/sysarch.h>
167 #include <machine/tss.h>
170 #define PMAP_MEMDOM MAXMEMDOM
172 #define PMAP_MEMDOM 1
175 static __inline boolean_t
176 pmap_type_guest(pmap_t pmap)
179 return ((pmap->pm_type == PT_EPT) || (pmap->pm_type == PT_RVI));
182 static __inline boolean_t
183 pmap_emulate_ad_bits(pmap_t pmap)
186 return ((pmap->pm_flags & PMAP_EMULATE_AD_BITS) != 0);
189 static __inline pt_entry_t
190 pmap_valid_bit(pmap_t pmap)
194 switch (pmap->pm_type) {
200 if (pmap_emulate_ad_bits(pmap))
201 mask = EPT_PG_EMUL_V;
206 panic("pmap_valid_bit: invalid pm_type %d", pmap->pm_type);
212 static __inline pt_entry_t
213 pmap_rw_bit(pmap_t pmap)
217 switch (pmap->pm_type) {
223 if (pmap_emulate_ad_bits(pmap))
224 mask = EPT_PG_EMUL_RW;
229 panic("pmap_rw_bit: invalid pm_type %d", pmap->pm_type);
235 static pt_entry_t pg_g;
237 static __inline pt_entry_t
238 pmap_global_bit(pmap_t pmap)
242 switch (pmap->pm_type) {
251 panic("pmap_global_bit: invalid pm_type %d", pmap->pm_type);
257 static __inline pt_entry_t
258 pmap_accessed_bit(pmap_t pmap)
262 switch (pmap->pm_type) {
268 if (pmap_emulate_ad_bits(pmap))
274 panic("pmap_accessed_bit: invalid pm_type %d", pmap->pm_type);
280 static __inline pt_entry_t
281 pmap_modified_bit(pmap_t pmap)
285 switch (pmap->pm_type) {
291 if (pmap_emulate_ad_bits(pmap))
297 panic("pmap_modified_bit: invalid pm_type %d", pmap->pm_type);
303 static __inline pt_entry_t
304 pmap_pku_mask_bit(pmap_t pmap)
307 return (pmap->pm_type == PT_X86 ? X86_PG_PKU_MASK : 0);
310 #if !defined(DIAGNOSTIC)
311 #ifdef __GNUC_GNU_INLINE__
312 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
314 #define PMAP_INLINE extern inline
321 #define PV_STAT(x) do { x ; } while (0)
323 #define PV_STAT(x) do { } while (0)
328 #define pa_index(pa) ({ \
329 KASSERT((pa) <= vm_phys_segs[vm_phys_nsegs - 1].end, \
330 ("address %lx beyond the last segment", (pa))); \
333 #define pa_to_pmdp(pa) (&pv_table[pa_index(pa)])
334 #define pa_to_pvh(pa) (&(pa_to_pmdp(pa)->pv_page))
335 #define PHYS_TO_PV_LIST_LOCK(pa) ({ \
336 struct rwlock *_lock; \
337 if (__predict_false((pa) > pmap_last_pa)) \
338 _lock = &pv_dummy_large.pv_lock; \
340 _lock = &(pa_to_pmdp(pa)->pv_lock); \
344 #define pa_index(pa) ((pa) >> PDRSHIFT)
345 #define pa_to_pvh(pa) (&pv_table[pa_index(pa)])
347 #define NPV_LIST_LOCKS MAXCPU
349 #define PHYS_TO_PV_LIST_LOCK(pa) \
350 (&pv_list_locks[pa_index(pa) % NPV_LIST_LOCKS])
353 #define CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa) do { \
354 struct rwlock **_lockp = (lockp); \
355 struct rwlock *_new_lock; \
357 _new_lock = PHYS_TO_PV_LIST_LOCK(pa); \
358 if (_new_lock != *_lockp) { \
359 if (*_lockp != NULL) \
360 rw_wunlock(*_lockp); \
361 *_lockp = _new_lock; \
366 #define CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m) \
367 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, VM_PAGE_TO_PHYS(m))
369 #define RELEASE_PV_LIST_LOCK(lockp) do { \
370 struct rwlock **_lockp = (lockp); \
372 if (*_lockp != NULL) { \
373 rw_wunlock(*_lockp); \
378 #define VM_PAGE_TO_PV_LIST_LOCK(m) \
379 PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m))
381 struct pmap kernel_pmap_store;
383 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
384 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
387 SYSCTL_INT(_machdep, OID_AUTO, nkpt, CTLFLAG_RD, &nkpt, 0,
388 "Number of kernel page table pages allocated on bootup");
391 vm_paddr_t dmaplimit;
392 vm_offset_t kernel_vm_end = VM_MIN_KERNEL_ADDRESS;
395 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
396 "VM/pmap parameters");
398 static int pg_ps_enabled = 1;
399 SYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
400 &pg_ps_enabled, 0, "Are large page mappings enabled?");
402 int __read_frequently la57 = 0;
403 SYSCTL_INT(_vm_pmap, OID_AUTO, la57, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
405 "5-level paging for host is enabled");
408 pmap_is_la57(pmap_t pmap)
410 if (pmap->pm_type == PT_X86)
412 return (false); /* XXXKIB handle EPT */
415 #define PAT_INDEX_SIZE 8
416 static int pat_index[PAT_INDEX_SIZE]; /* cache mode to PAT index conversion */
418 static u_int64_t KPTphys; /* phys addr of kernel level 1 */
419 static u_int64_t KPDphys; /* phys addr of kernel level 2 */
420 u_int64_t KPDPphys; /* phys addr of kernel level 3 */
421 u_int64_t KPML4phys; /* phys addr of kernel level 4 */
422 u_int64_t KPML5phys; /* phys addr of kernel level 5,
425 static pml4_entry_t *kernel_pml4;
426 static u_int64_t DMPDphys; /* phys addr of direct mapped level 2 */
427 static u_int64_t DMPDPphys; /* phys addr of direct mapped level 3 */
428 static int ndmpdpphys; /* number of DMPDPphys pages */
430 static vm_paddr_t KERNend; /* phys addr of end of bootstrap data */
433 * pmap_mapdev support pre initialization (i.e. console)
435 #define PMAP_PREINIT_MAPPING_COUNT 8
436 static struct pmap_preinit_mapping {
441 } pmap_preinit_mapping[PMAP_PREINIT_MAPPING_COUNT];
442 static int pmap_initialized;
445 * Data for the pv entry allocation mechanism.
446 * Updates to pv_invl_gen are protected by the pv list lock but reads are not.
450 pc_to_domain(struct pv_chunk *pc)
453 return (_vm_phys_domain(DMAP_TO_PHYS((vm_offset_t)pc)));
457 pc_to_domain(struct pv_chunk *pc __unused)
464 struct pv_chunks_list {
466 TAILQ_HEAD(pch, pv_chunk) pvc_list;
468 } __aligned(CACHE_LINE_SIZE);
470 struct pv_chunks_list __exclusive_cache_line pv_chunks[PMAP_MEMDOM];
473 struct pmap_large_md_page {
474 struct rwlock pv_lock;
475 struct md_page pv_page;
478 __exclusive_cache_line static struct pmap_large_md_page pv_dummy_large;
479 #define pv_dummy pv_dummy_large.pv_page
480 __read_mostly static struct pmap_large_md_page *pv_table;
481 __read_mostly vm_paddr_t pmap_last_pa;
483 static struct rwlock __exclusive_cache_line pv_list_locks[NPV_LIST_LOCKS];
484 static u_long pv_invl_gen[NPV_LIST_LOCKS];
485 static struct md_page *pv_table;
486 static struct md_page pv_dummy;
490 * All those kernel PT submaps that BSD is so fond of
492 pt_entry_t *CMAP1 = NULL;
494 static vm_offset_t qframe = 0;
495 static struct mtx qframe_mtx;
497 static int pmap_flags = PMAP_PDE_SUPERPAGE; /* flags for x86 pmaps */
499 static vmem_t *large_vmem;
500 static u_int lm_ents;
501 #define PMAP_ADDRESS_IN_LARGEMAP(va) ((va) >= LARGEMAP_MIN_ADDRESS && \
502 (va) < LARGEMAP_MIN_ADDRESS + NBPML4 * (u_long)lm_ents)
504 int pmap_pcid_enabled = 1;
505 SYSCTL_INT(_vm_pmap, OID_AUTO, pcid_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
506 &pmap_pcid_enabled, 0, "Is TLB Context ID enabled ?");
507 int invpcid_works = 0;
508 SYSCTL_INT(_vm_pmap, OID_AUTO, invpcid_works, CTLFLAG_RD, &invpcid_works, 0,
509 "Is the invpcid instruction available ?");
511 int __read_frequently pti = 0;
512 SYSCTL_INT(_vm_pmap, OID_AUTO, pti, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
514 "Page Table Isolation enabled");
515 static vm_object_t pti_obj;
516 static pml4_entry_t *pti_pml4;
517 static vm_pindex_t pti_pg_idx;
518 static bool pti_finalized;
520 struct pmap_pkru_range {
521 struct rs_el pkru_rs_el;
526 static uma_zone_t pmap_pkru_ranges_zone;
527 static bool pmap_pkru_same(pmap_t pmap, vm_offset_t sva, vm_offset_t eva);
528 static pt_entry_t pmap_pkru_get(pmap_t pmap, vm_offset_t va);
529 static void pmap_pkru_on_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva);
530 static void *pkru_dup_range(void *ctx, void *data);
531 static void pkru_free_range(void *ctx, void *node);
532 static int pmap_pkru_copy(pmap_t dst_pmap, pmap_t src_pmap);
533 static int pmap_pkru_deassign(pmap_t pmap, vm_offset_t sva, vm_offset_t eva);
534 static void pmap_pkru_deassign_all(pmap_t pmap);
537 pmap_pcid_save_cnt_proc(SYSCTL_HANDLER_ARGS)
544 res += cpuid_to_pcpu[i]->pc_pm_save_cnt;
546 return (sysctl_handle_64(oidp, &res, 0, req));
548 SYSCTL_PROC(_vm_pmap, OID_AUTO, pcid_save_cnt, CTLTYPE_U64 | CTLFLAG_RD |
549 CTLFLAG_MPSAFE, NULL, 0, pmap_pcid_save_cnt_proc, "QU",
550 "Count of saved TLB context on switch");
552 static LIST_HEAD(, pmap_invl_gen) pmap_invl_gen_tracker =
553 LIST_HEAD_INITIALIZER(&pmap_invl_gen_tracker);
554 static struct mtx invl_gen_mtx;
555 /* Fake lock object to satisfy turnstiles interface. */
556 static struct lock_object invl_gen_ts = {
559 static struct pmap_invl_gen pmap_invl_gen_head = {
563 static u_long pmap_invl_gen = 1;
564 static int pmap_invl_waiters;
565 static struct callout pmap_invl_callout;
566 static bool pmap_invl_callout_inited;
568 #define PMAP_ASSERT_NOT_IN_DI() \
569 KASSERT(pmap_not_in_di(), ("DI already started"))
576 if ((cpu_feature2 & CPUID2_CX16) == 0)
579 TUNABLE_INT_FETCH("vm.pmap.di_locked", &tun);
584 sysctl_pmap_di_locked(SYSCTL_HANDLER_ARGS)
588 locked = pmap_di_locked();
589 return (sysctl_handle_int(oidp, &locked, 0, req));
591 SYSCTL_PROC(_vm_pmap, OID_AUTO, di_locked, CTLTYPE_INT | CTLFLAG_RDTUN |
592 CTLFLAG_MPSAFE, 0, 0, sysctl_pmap_di_locked, "",
593 "Locked delayed invalidation");
595 static bool pmap_not_in_di_l(void);
596 static bool pmap_not_in_di_u(void);
597 DEFINE_IFUNC(, bool, pmap_not_in_di, (void))
600 return (pmap_di_locked() ? pmap_not_in_di_l : pmap_not_in_di_u);
604 pmap_not_in_di_l(void)
606 struct pmap_invl_gen *invl_gen;
608 invl_gen = &curthread->td_md.md_invl_gen;
609 return (invl_gen->gen == 0);
613 pmap_thread_init_invl_gen_l(struct thread *td)
615 struct pmap_invl_gen *invl_gen;
617 invl_gen = &td->td_md.md_invl_gen;
622 pmap_delayed_invl_wait_block(u_long *m_gen, u_long *invl_gen)
624 struct turnstile *ts;
626 ts = turnstile_trywait(&invl_gen_ts);
627 if (*m_gen > atomic_load_long(invl_gen))
628 turnstile_wait(ts, NULL, TS_SHARED_QUEUE);
630 turnstile_cancel(ts);
634 pmap_delayed_invl_finish_unblock(u_long new_gen)
636 struct turnstile *ts;
638 turnstile_chain_lock(&invl_gen_ts);
639 ts = turnstile_lookup(&invl_gen_ts);
641 pmap_invl_gen = new_gen;
643 turnstile_broadcast(ts, TS_SHARED_QUEUE);
644 turnstile_unpend(ts);
646 turnstile_chain_unlock(&invl_gen_ts);
650 * Start a new Delayed Invalidation (DI) block of code, executed by
651 * the current thread. Within a DI block, the current thread may
652 * destroy both the page table and PV list entries for a mapping and
653 * then release the corresponding PV list lock before ensuring that
654 * the mapping is flushed from the TLBs of any processors with the
658 pmap_delayed_invl_start_l(void)
660 struct pmap_invl_gen *invl_gen;
663 invl_gen = &curthread->td_md.md_invl_gen;
664 PMAP_ASSERT_NOT_IN_DI();
665 mtx_lock(&invl_gen_mtx);
666 if (LIST_EMPTY(&pmap_invl_gen_tracker))
667 currgen = pmap_invl_gen;
669 currgen = LIST_FIRST(&pmap_invl_gen_tracker)->gen;
670 invl_gen->gen = currgen + 1;
671 LIST_INSERT_HEAD(&pmap_invl_gen_tracker, invl_gen, link);
672 mtx_unlock(&invl_gen_mtx);
676 * Finish the DI block, previously started by the current thread. All
677 * required TLB flushes for the pages marked by
678 * pmap_delayed_invl_page() must be finished before this function is
681 * This function works by bumping the global DI generation number to
682 * the generation number of the current thread's DI, unless there is a
683 * pending DI that started earlier. In the latter case, bumping the
684 * global DI generation number would incorrectly signal that the
685 * earlier DI had finished. Instead, this function bumps the earlier
686 * DI's generation number to match the generation number of the
687 * current thread's DI.
690 pmap_delayed_invl_finish_l(void)
692 struct pmap_invl_gen *invl_gen, *next;
694 invl_gen = &curthread->td_md.md_invl_gen;
695 KASSERT(invl_gen->gen != 0, ("missed invl_start"));
696 mtx_lock(&invl_gen_mtx);
697 next = LIST_NEXT(invl_gen, link);
699 pmap_delayed_invl_finish_unblock(invl_gen->gen);
701 next->gen = invl_gen->gen;
702 LIST_REMOVE(invl_gen, link);
703 mtx_unlock(&invl_gen_mtx);
708 pmap_not_in_di_u(void)
710 struct pmap_invl_gen *invl_gen;
712 invl_gen = &curthread->td_md.md_invl_gen;
713 return (((uintptr_t)invl_gen->next & PMAP_INVL_GEN_NEXT_INVALID) != 0);
717 pmap_thread_init_invl_gen_u(struct thread *td)
719 struct pmap_invl_gen *invl_gen;
721 invl_gen = &td->td_md.md_invl_gen;
723 invl_gen->next = (void *)PMAP_INVL_GEN_NEXT_INVALID;
727 pmap_di_load_invl(struct pmap_invl_gen *ptr, struct pmap_invl_gen *out)
729 uint64_t new_high, new_low, old_high, old_low;
732 old_low = new_low = 0;
733 old_high = new_high = (uintptr_t)0;
735 __asm volatile("lock;cmpxchg16b\t%1"
736 : "=@cce" (res), "+m" (*ptr), "+a" (old_low), "+d" (old_high)
737 : "b"(new_low), "c" (new_high)
740 if ((old_high & PMAP_INVL_GEN_NEXT_INVALID) != 0)
743 out->next = (void *)old_high;
746 out->next = (void *)new_high;
752 pmap_di_store_invl(struct pmap_invl_gen *ptr, struct pmap_invl_gen *old_val,
753 struct pmap_invl_gen *new_val)
755 uint64_t new_high, new_low, old_high, old_low;
758 new_low = new_val->gen;
759 new_high = (uintptr_t)new_val->next;
760 old_low = old_val->gen;
761 old_high = (uintptr_t)old_val->next;
763 __asm volatile("lock;cmpxchg16b\t%1"
764 : "=@cce" (res), "+m" (*ptr), "+a" (old_low), "+d" (old_high)
765 : "b"(new_low), "c" (new_high)
771 static long invl_start_restart;
772 SYSCTL_LONG(_vm_pmap, OID_AUTO, invl_start_restart, CTLFLAG_RD,
773 &invl_start_restart, 0,
775 static long invl_finish_restart;
776 SYSCTL_LONG(_vm_pmap, OID_AUTO, invl_finish_restart, CTLFLAG_RD,
777 &invl_finish_restart, 0,
779 static int invl_max_qlen;
780 SYSCTL_INT(_vm_pmap, OID_AUTO, invl_max_qlen, CTLFLAG_RD,
785 #define di_delay locks_delay
788 pmap_delayed_invl_start_u(void)
790 struct pmap_invl_gen *invl_gen, *p, prev, new_prev;
792 struct lock_delay_arg lda;
800 invl_gen = &td->td_md.md_invl_gen;
801 PMAP_ASSERT_NOT_IN_DI();
802 lock_delay_arg_init(&lda, &di_delay);
803 invl_gen->saved_pri = 0;
804 pri = td->td_base_pri;
807 pri = td->td_base_pri;
809 invl_gen->saved_pri = pri;
816 for (p = &pmap_invl_gen_head;; p = prev.next) {
818 prevl = (uintptr_t)atomic_load_ptr(&p->next);
819 if ((prevl & PMAP_INVL_GEN_NEXT_INVALID) != 0) {
820 PV_STAT(atomic_add_long(&invl_start_restart, 1));
826 prev.next = (void *)prevl;
829 if ((ii = invl_max_qlen) < i)
830 atomic_cmpset_int(&invl_max_qlen, ii, i);
833 if (!pmap_di_load_invl(p, &prev) || prev.next != NULL) {
834 PV_STAT(atomic_add_long(&invl_start_restart, 1));
839 new_prev.gen = prev.gen;
840 new_prev.next = invl_gen;
841 invl_gen->gen = prev.gen + 1;
843 /* Formal fence between store to invl->gen and updating *p. */
844 atomic_thread_fence_rel();
847 * After inserting an invl_gen element with invalid bit set,
848 * this thread blocks any other thread trying to enter the
849 * delayed invalidation block. Do not allow to remove us from
850 * the CPU, because it causes starvation for other threads.
855 * ABA for *p is not possible there, since p->gen can only
856 * increase. So if the *p thread finished its di, then
857 * started a new one and got inserted into the list at the
858 * same place, its gen will appear greater than the previously
861 if (!pmap_di_store_invl(p, &prev, &new_prev)) {
863 PV_STAT(atomic_add_long(&invl_start_restart, 1));
869 * There we clear PMAP_INVL_GEN_NEXT_INVALID in
870 * invl_gen->next, allowing other threads to iterate past us.
871 * pmap_di_store_invl() provides fence between the generation
872 * write and the update of next.
874 invl_gen->next = NULL;
879 pmap_delayed_invl_finish_u_crit(struct pmap_invl_gen *invl_gen,
880 struct pmap_invl_gen *p)
882 struct pmap_invl_gen prev, new_prev;
886 * Load invl_gen->gen after setting invl_gen->next
887 * PMAP_INVL_GEN_NEXT_INVALID. This prevents larger
888 * generations to propagate to our invl_gen->gen. Lock prefix
889 * in atomic_set_ptr() worked as seq_cst fence.
891 mygen = atomic_load_long(&invl_gen->gen);
893 if (!pmap_di_load_invl(p, &prev) || prev.next != invl_gen)
896 KASSERT(prev.gen < mygen,
897 ("invalid di gen sequence %lu %lu", prev.gen, mygen));
898 new_prev.gen = mygen;
899 new_prev.next = (void *)((uintptr_t)invl_gen->next &
900 ~PMAP_INVL_GEN_NEXT_INVALID);
902 /* Formal fence between load of prev and storing update to it. */
903 atomic_thread_fence_rel();
905 return (pmap_di_store_invl(p, &prev, &new_prev));
909 pmap_delayed_invl_finish_u(void)
911 struct pmap_invl_gen *invl_gen, *p;
913 struct lock_delay_arg lda;
917 invl_gen = &td->td_md.md_invl_gen;
918 KASSERT(invl_gen->gen != 0, ("missed invl_start: gen 0"));
919 KASSERT(((uintptr_t)invl_gen->next & PMAP_INVL_GEN_NEXT_INVALID) == 0,
920 ("missed invl_start: INVALID"));
921 lock_delay_arg_init(&lda, &di_delay);
924 for (p = &pmap_invl_gen_head; p != NULL; p = (void *)prevl) {
925 prevl = (uintptr_t)atomic_load_ptr(&p->next);
926 if ((prevl & PMAP_INVL_GEN_NEXT_INVALID) != 0) {
927 PV_STAT(atomic_add_long(&invl_finish_restart, 1));
931 if ((void *)prevl == invl_gen)
936 * It is legitimate to not find ourself on the list if a
937 * thread before us finished its DI and started it again.
939 if (__predict_false(p == NULL)) {
940 PV_STAT(atomic_add_long(&invl_finish_restart, 1));
946 atomic_set_ptr((uintptr_t *)&invl_gen->next,
947 PMAP_INVL_GEN_NEXT_INVALID);
948 if (!pmap_delayed_invl_finish_u_crit(invl_gen, p)) {
949 atomic_clear_ptr((uintptr_t *)&invl_gen->next,
950 PMAP_INVL_GEN_NEXT_INVALID);
952 PV_STAT(atomic_add_long(&invl_finish_restart, 1));
957 if (atomic_load_int(&pmap_invl_waiters) > 0)
958 pmap_delayed_invl_finish_unblock(0);
959 if (invl_gen->saved_pri != 0) {
961 sched_prio(td, invl_gen->saved_pri);
967 DB_SHOW_COMMAND(di_queue, pmap_di_queue)
969 struct pmap_invl_gen *p, *pn;
974 for (p = &pmap_invl_gen_head, first = true; p != NULL; p = pn,
976 nextl = (uintptr_t)atomic_load_ptr(&p->next);
977 pn = (void *)(nextl & ~PMAP_INVL_GEN_NEXT_INVALID);
978 td = first ? NULL : __containerof(p, struct thread,
980 db_printf("gen %lu inv %d td %p tid %d\n", p->gen,
981 (nextl & PMAP_INVL_GEN_NEXT_INVALID) != 0, td,
982 td != NULL ? td->td_tid : -1);
988 static long invl_wait;
989 SYSCTL_LONG(_vm_pmap, OID_AUTO, invl_wait, CTLFLAG_RD, &invl_wait, 0,
990 "Number of times DI invalidation blocked pmap_remove_all/write");
991 static long invl_wait_slow;
992 SYSCTL_LONG(_vm_pmap, OID_AUTO, invl_wait_slow, CTLFLAG_RD, &invl_wait_slow, 0,
993 "Number of slow invalidation waits for lockless DI");
998 pmap_delayed_invl_genp(vm_page_t m)
1003 pa = VM_PAGE_TO_PHYS(m);
1004 if (__predict_false((pa) > pmap_last_pa))
1005 gen = &pv_dummy_large.pv_invl_gen;
1007 gen = &(pa_to_pmdp(pa)->pv_invl_gen);
1013 pmap_delayed_invl_genp(vm_page_t m)
1016 return (&pv_invl_gen[pa_index(VM_PAGE_TO_PHYS(m)) % NPV_LIST_LOCKS]);
1021 pmap_delayed_invl_callout_func(void *arg __unused)
1024 if (atomic_load_int(&pmap_invl_waiters) == 0)
1026 pmap_delayed_invl_finish_unblock(0);
1030 pmap_delayed_invl_callout_init(void *arg __unused)
1033 if (pmap_di_locked())
1035 callout_init(&pmap_invl_callout, 1);
1036 pmap_invl_callout_inited = true;
1038 SYSINIT(pmap_di_callout, SI_SUB_CPU + 1, SI_ORDER_ANY,
1039 pmap_delayed_invl_callout_init, NULL);
1042 * Ensure that all currently executing DI blocks, that need to flush
1043 * TLB for the given page m, actually flushed the TLB at the time the
1044 * function returned. If the page m has an empty PV list and we call
1045 * pmap_delayed_invl_wait(), upon its return we know that no CPU has a
1046 * valid mapping for the page m in either its page table or TLB.
1048 * This function works by blocking until the global DI generation
1049 * number catches up with the generation number associated with the
1050 * given page m and its PV list. Since this function's callers
1051 * typically own an object lock and sometimes own a page lock, it
1052 * cannot sleep. Instead, it blocks on a turnstile to relinquish the
1056 pmap_delayed_invl_wait_l(vm_page_t m)
1060 bool accounted = false;
1063 m_gen = pmap_delayed_invl_genp(m);
1064 while (*m_gen > pmap_invl_gen) {
1067 atomic_add_long(&invl_wait, 1);
1071 pmap_delayed_invl_wait_block(m_gen, &pmap_invl_gen);
1076 pmap_delayed_invl_wait_u(vm_page_t m)
1079 struct lock_delay_arg lda;
1083 m_gen = pmap_delayed_invl_genp(m);
1084 lock_delay_arg_init(&lda, &di_delay);
1085 while (*m_gen > atomic_load_long(&pmap_invl_gen_head.gen)) {
1086 if (fast || !pmap_invl_callout_inited) {
1087 PV_STAT(atomic_add_long(&invl_wait, 1));
1092 * The page's invalidation generation number
1093 * is still below the current thread's number.
1094 * Prepare to block so that we do not waste
1095 * CPU cycles or worse, suffer livelock.
1097 * Since it is impossible to block without
1098 * racing with pmap_delayed_invl_finish_u(),
1099 * prepare for the race by incrementing
1100 * pmap_invl_waiters and arming a 1-tick
1101 * callout which will unblock us if we lose
1104 atomic_add_int(&pmap_invl_waiters, 1);
1107 * Re-check the current thread's invalidation
1108 * generation after incrementing
1109 * pmap_invl_waiters, so that there is no race
1110 * with pmap_delayed_invl_finish_u() setting
1111 * the page generation and checking
1112 * pmap_invl_waiters. The only race allowed
1113 * is for a missed unblock, which is handled
1117 atomic_load_long(&pmap_invl_gen_head.gen)) {
1118 callout_reset(&pmap_invl_callout, 1,
1119 pmap_delayed_invl_callout_func, NULL);
1120 PV_STAT(atomic_add_long(&invl_wait_slow, 1));
1121 pmap_delayed_invl_wait_block(m_gen,
1122 &pmap_invl_gen_head.gen);
1124 atomic_add_int(&pmap_invl_waiters, -1);
1129 DEFINE_IFUNC(, void, pmap_thread_init_invl_gen, (struct thread *))
1132 return (pmap_di_locked() ? pmap_thread_init_invl_gen_l :
1133 pmap_thread_init_invl_gen_u);
1136 DEFINE_IFUNC(static, void, pmap_delayed_invl_start, (void))
1139 return (pmap_di_locked() ? pmap_delayed_invl_start_l :
1140 pmap_delayed_invl_start_u);
1143 DEFINE_IFUNC(static, void, pmap_delayed_invl_finish, (void))
1146 return (pmap_di_locked() ? pmap_delayed_invl_finish_l :
1147 pmap_delayed_invl_finish_u);
1150 DEFINE_IFUNC(static, void, pmap_delayed_invl_wait, (vm_page_t))
1153 return (pmap_di_locked() ? pmap_delayed_invl_wait_l :
1154 pmap_delayed_invl_wait_u);
1158 * Mark the page m's PV list as participating in the current thread's
1159 * DI block. Any threads concurrently using m's PV list to remove or
1160 * restrict all mappings to m will wait for the current thread's DI
1161 * block to complete before proceeding.
1163 * The function works by setting the DI generation number for m's PV
1164 * list to at least the DI generation number of the current thread.
1165 * This forces a caller of pmap_delayed_invl_wait() to block until
1166 * current thread calls pmap_delayed_invl_finish().
1169 pmap_delayed_invl_page(vm_page_t m)
1173 rw_assert(VM_PAGE_TO_PV_LIST_LOCK(m), RA_WLOCKED);
1174 gen = curthread->td_md.md_invl_gen.gen;
1177 m_gen = pmap_delayed_invl_genp(m);
1185 static caddr_t crashdumpmap;
1188 * Internal flags for pmap_enter()'s helper functions.
1190 #define PMAP_ENTER_NORECLAIM 0x1000000 /* Don't reclaim PV entries. */
1191 #define PMAP_ENTER_NOREPLACE 0x2000000 /* Don't replace mappings. */
1194 * Internal flags for pmap_mapdev_internal() and
1195 * pmap_change_props_locked().
1197 #define MAPDEV_FLUSHCACHE 0x00000001 /* Flush cache after mapping. */
1198 #define MAPDEV_SETATTR 0x00000002 /* Modify existing attrs. */
1199 #define MAPDEV_ASSERTVALID 0x00000004 /* Assert mapping validity. */
1201 TAILQ_HEAD(pv_chunklist, pv_chunk);
1203 static void free_pv_chunk(struct pv_chunk *pc);
1204 static void free_pv_chunk_batch(struct pv_chunklist *batch);
1205 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
1206 static pv_entry_t get_pv_entry(pmap_t pmap, struct rwlock **lockp);
1207 static int popcnt_pc_map_pq(uint64_t *map);
1208 static vm_page_t reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp);
1209 static void reserve_pv_entries(pmap_t pmap, int needed,
1210 struct rwlock **lockp);
1211 static void pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
1212 struct rwlock **lockp);
1213 static bool pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, pd_entry_t pde,
1214 u_int flags, struct rwlock **lockp);
1215 #if VM_NRESERVLEVEL > 0
1216 static void pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
1217 struct rwlock **lockp);
1219 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
1220 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
1223 static void pmap_abort_ptp(pmap_t pmap, vm_offset_t va, vm_page_t mpte);
1224 static int pmap_change_props_locked(vm_offset_t va, vm_size_t size,
1225 vm_prot_t prot, int mode, int flags);
1226 static boolean_t pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
1227 static boolean_t pmap_demote_pde_locked(pmap_t pmap, pd_entry_t *pde,
1228 vm_offset_t va, struct rwlock **lockp);
1229 static boolean_t pmap_demote_pdpe(pmap_t pmap, pdp_entry_t *pdpe,
1231 static bool pmap_enter_2mpage(pmap_t pmap, vm_offset_t va, vm_page_t m,
1232 vm_prot_t prot, struct rwlock **lockp);
1233 static int pmap_enter_pde(pmap_t pmap, vm_offset_t va, pd_entry_t newpde,
1234 u_int flags, vm_page_t m, struct rwlock **lockp);
1235 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
1236 vm_page_t m, vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp);
1237 static void pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte);
1238 static int pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte, bool promoted);
1239 static void pmap_invalidate_cache_range_selfsnoop(vm_offset_t sva,
1241 static void pmap_invalidate_cache_range_all(vm_offset_t sva,
1243 static void pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va,
1245 static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode);
1246 static vm_page_t pmap_large_map_getptp_unlocked(void);
1247 static vm_paddr_t pmap_large_map_kextract(vm_offset_t va);
1248 #if VM_NRESERVLEVEL > 0
1249 static void pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
1250 struct rwlock **lockp);
1252 static boolean_t pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva,
1254 static void pmap_pte_props(pt_entry_t *pte, u_long bits, u_long mask);
1255 static void pmap_pti_add_kva_locked(vm_offset_t sva, vm_offset_t eva,
1257 static pdp_entry_t *pmap_pti_pdpe(vm_offset_t va);
1258 static pd_entry_t *pmap_pti_pde(vm_offset_t va);
1259 static void pmap_pti_wire_pte(void *pte);
1260 static int pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
1261 struct spglist *free, struct rwlock **lockp);
1262 static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva,
1263 pd_entry_t ptepde, struct spglist *free, struct rwlock **lockp);
1264 static vm_page_t pmap_remove_pt_page(pmap_t pmap, vm_offset_t va);
1265 static void pmap_remove_page(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
1266 struct spglist *free);
1267 static bool pmap_remove_ptes(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
1268 pd_entry_t *pde, struct spglist *free,
1269 struct rwlock **lockp);
1270 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
1271 vm_page_t m, struct rwlock **lockp);
1272 static void pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
1274 static void pmap_update_pde_invalidate(pmap_t, vm_offset_t va, pd_entry_t pde);
1276 static vm_page_t _pmap_allocpte(pmap_t pmap, vm_pindex_t ptepindex,
1277 struct rwlock **lockp, vm_offset_t va);
1278 static pd_entry_t *pmap_alloc_pde(pmap_t pmap, vm_offset_t va, vm_page_t *pdpgp,
1279 struct rwlock **lockp);
1280 static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va,
1281 struct rwlock **lockp);
1283 static void _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m,
1284 struct spglist *free);
1285 static int pmap_unuse_pt(pmap_t, vm_offset_t, pd_entry_t, struct spglist *);
1287 /********************/
1288 /* Inline functions */
1289 /********************/
1292 * Return a non-clipped indexes for a given VA, which are page table
1293 * pages indexes at the corresponding level.
1295 static __inline vm_pindex_t
1296 pmap_pde_pindex(vm_offset_t va)
1298 return (va >> PDRSHIFT);
1301 static __inline vm_pindex_t
1302 pmap_pdpe_pindex(vm_offset_t va)
1304 return (NUPDE + (va >> PDPSHIFT));
1307 static __inline vm_pindex_t
1308 pmap_pml4e_pindex(vm_offset_t va)
1310 return (NUPDE + NUPDPE + (va >> PML4SHIFT));
1313 static __inline vm_pindex_t
1314 pmap_pml5e_pindex(vm_offset_t va)
1316 return (NUPDE + NUPDPE + NUPML4E + (va >> PML5SHIFT));
1319 static __inline pml4_entry_t *
1320 pmap_pml5e(pmap_t pmap, vm_offset_t va)
1323 MPASS(pmap_is_la57(pmap));
1324 return (&pmap->pm_pmltop[pmap_pml5e_index(va)]);
1327 static __inline pml4_entry_t *
1328 pmap_pml5e_u(pmap_t pmap, vm_offset_t va)
1331 MPASS(pmap_is_la57(pmap));
1332 return (&pmap->pm_pmltopu[pmap_pml5e_index(va)]);
1335 static __inline pml4_entry_t *
1336 pmap_pml5e_to_pml4e(pml5_entry_t *pml5e, vm_offset_t va)
1338 pml4_entry_t *pml4e;
1340 /* XXX MPASS(pmap_is_la57(pmap); */
1341 pml4e = (pml4_entry_t *)PHYS_TO_DMAP(*pml5e & PG_FRAME);
1342 return (&pml4e[pmap_pml4e_index(va)]);
1345 /* Return a pointer to the PML4 slot that corresponds to a VA */
1346 static __inline pml4_entry_t *
1347 pmap_pml4e(pmap_t pmap, vm_offset_t va)
1349 pml5_entry_t *pml5e;
1350 pml4_entry_t *pml4e;
1353 if (pmap_is_la57(pmap)) {
1354 pml5e = pmap_pml5e(pmap, va);
1355 PG_V = pmap_valid_bit(pmap);
1356 if ((*pml5e & PG_V) == 0)
1358 pml4e = (pml4_entry_t *)PHYS_TO_DMAP(*pml5e & PG_FRAME);
1360 pml4e = pmap->pm_pmltop;
1362 return (&pml4e[pmap_pml4e_index(va)]);
1365 static __inline pml4_entry_t *
1366 pmap_pml4e_u(pmap_t pmap, vm_offset_t va)
1368 MPASS(!pmap_is_la57(pmap));
1369 return (&pmap->pm_pmltopu[pmap_pml4e_index(va)]);
1372 /* Return a pointer to the PDP slot that corresponds to a VA */
1373 static __inline pdp_entry_t *
1374 pmap_pml4e_to_pdpe(pml4_entry_t *pml4e, vm_offset_t va)
1378 pdpe = (pdp_entry_t *)PHYS_TO_DMAP(*pml4e & PG_FRAME);
1379 return (&pdpe[pmap_pdpe_index(va)]);
1382 /* Return a pointer to the PDP slot that corresponds to a VA */
1383 static __inline pdp_entry_t *
1384 pmap_pdpe(pmap_t pmap, vm_offset_t va)
1386 pml4_entry_t *pml4e;
1389 PG_V = pmap_valid_bit(pmap);
1390 pml4e = pmap_pml4e(pmap, va);
1391 if (pml4e == NULL || (*pml4e & PG_V) == 0)
1393 return (pmap_pml4e_to_pdpe(pml4e, va));
1396 /* Return a pointer to the PD slot that corresponds to a VA */
1397 static __inline pd_entry_t *
1398 pmap_pdpe_to_pde(pdp_entry_t *pdpe, vm_offset_t va)
1402 KASSERT((*pdpe & PG_PS) == 0,
1403 ("%s: pdpe %#lx is a leaf", __func__, *pdpe));
1404 pde = (pd_entry_t *)PHYS_TO_DMAP(*pdpe & PG_FRAME);
1405 return (&pde[pmap_pde_index(va)]);
1408 /* Return a pointer to the PD slot that corresponds to a VA */
1409 static __inline pd_entry_t *
1410 pmap_pde(pmap_t pmap, vm_offset_t va)
1415 PG_V = pmap_valid_bit(pmap);
1416 pdpe = pmap_pdpe(pmap, va);
1417 if (pdpe == NULL || (*pdpe & PG_V) == 0)
1419 KASSERT((*pdpe & PG_PS) == 0,
1420 ("pmap_pde for 1G page, pmap %p va %#lx", pmap, va));
1421 return (pmap_pdpe_to_pde(pdpe, va));
1424 /* Return a pointer to the PT slot that corresponds to a VA */
1425 static __inline pt_entry_t *
1426 pmap_pde_to_pte(pd_entry_t *pde, vm_offset_t va)
1430 KASSERT((*pde & PG_PS) == 0,
1431 ("%s: pde %#lx is a leaf", __func__, *pde));
1432 pte = (pt_entry_t *)PHYS_TO_DMAP(*pde & PG_FRAME);
1433 return (&pte[pmap_pte_index(va)]);
1436 /* Return a pointer to the PT slot that corresponds to a VA */
1437 static __inline pt_entry_t *
1438 pmap_pte(pmap_t pmap, vm_offset_t va)
1443 PG_V = pmap_valid_bit(pmap);
1444 pde = pmap_pde(pmap, va);
1445 if (pde == NULL || (*pde & PG_V) == 0)
1447 if ((*pde & PG_PS) != 0) /* compat with i386 pmap_pte() */
1448 return ((pt_entry_t *)pde);
1449 return (pmap_pde_to_pte(pde, va));
1452 static __inline void
1453 pmap_resident_count_inc(pmap_t pmap, int count)
1456 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1457 pmap->pm_stats.resident_count += count;
1460 static __inline void
1461 pmap_resident_count_dec(pmap_t pmap, int count)
1464 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1465 KASSERT(pmap->pm_stats.resident_count >= count,
1466 ("pmap %p resident count underflow %ld %d", pmap,
1467 pmap->pm_stats.resident_count, count));
1468 pmap->pm_stats.resident_count -= count;
1471 PMAP_INLINE pt_entry_t *
1472 vtopte(vm_offset_t va)
1476 KASSERT(va >= VM_MAXUSER_ADDRESS, ("vtopte on a uva/gpa 0x%0lx", va));
1479 mask = ((1ul << (NPTEPGSHIFT + NPDEPGSHIFT + NPDPEPGSHIFT +
1480 NPML4EPGSHIFT + NPML5EPGSHIFT)) - 1);
1481 return (P5Tmap + ((va >> PAGE_SHIFT) & mask));
1483 mask = ((1ul << (NPTEPGSHIFT + NPDEPGSHIFT + NPDPEPGSHIFT +
1484 NPML4EPGSHIFT)) - 1);
1485 return (P4Tmap + ((va >> PAGE_SHIFT) & mask));
1489 static __inline pd_entry_t *
1490 vtopde(vm_offset_t va)
1494 KASSERT(va >= VM_MAXUSER_ADDRESS, ("vtopde on a uva/gpa 0x%0lx", va));
1497 mask = ((1ul << (NPDEPGSHIFT + NPDPEPGSHIFT +
1498 NPML4EPGSHIFT + NPML5EPGSHIFT)) - 1);
1499 return (P5Dmap + ((va >> PDRSHIFT) & mask));
1501 mask = ((1ul << (NPDEPGSHIFT + NPDPEPGSHIFT +
1502 NPML4EPGSHIFT)) - 1);
1503 return (P4Dmap + ((va >> PDRSHIFT) & mask));
1508 allocpages(vm_paddr_t *firstaddr, int n)
1513 bzero((void *)ret, n * PAGE_SIZE);
1514 *firstaddr += n * PAGE_SIZE;
1518 CTASSERT(powerof2(NDMPML4E));
1520 /* number of kernel PDP slots */
1521 #define NKPDPE(ptpgs) howmany(ptpgs, NPDEPG)
1524 nkpt_init(vm_paddr_t addr)
1531 pt_pages = howmany(addr, 1 << PDRSHIFT);
1532 pt_pages += NKPDPE(pt_pages);
1535 * Add some slop beyond the bare minimum required for bootstrapping
1538 * This is quite important when allocating KVA for kernel modules.
1539 * The modules are required to be linked in the negative 2GB of
1540 * the address space. If we run out of KVA in this region then
1541 * pmap_growkernel() will need to allocate page table pages to map
1542 * the entire 512GB of KVA space which is an unnecessary tax on
1545 * Secondly, device memory mapped as part of setting up the low-
1546 * level console(s) is taken from KVA, starting at virtual_avail.
1547 * This is because cninit() is called after pmap_bootstrap() but
1548 * before vm_init() and pmap_init(). 20MB for a frame buffer is
1551 pt_pages += 32; /* 64MB additional slop. */
1557 * Returns the proper write/execute permission for a physical page that is
1558 * part of the initial boot allocations.
1560 * If the page has kernel text, it is marked as read-only. If the page has
1561 * kernel read-only data, it is marked as read-only/not-executable. If the
1562 * page has only read-write data, it is marked as read-write/not-executable.
1563 * If the page is below/above the kernel range, it is marked as read-write.
1565 * This function operates on 2M pages, since we map the kernel space that
1568 static inline pt_entry_t
1569 bootaddr_rwx(vm_paddr_t pa)
1573 * The kernel is loaded at a 2MB-aligned address, and memory below that
1574 * need not be executable. The .bss section is padded to a 2MB
1575 * boundary, so memory following the kernel need not be executable
1576 * either. Preloaded kernel modules have their mapping permissions
1577 * fixed up by the linker.
1579 if (pa < trunc_2mpage(btext - KERNBASE) ||
1580 pa >= trunc_2mpage(_end - KERNBASE))
1581 return (X86_PG_RW | pg_nx);
1584 * The linker should ensure that the read-only and read-write
1585 * portions don't share the same 2M page, so this shouldn't
1586 * impact read-only data. However, in any case, any page with
1587 * read-write data needs to be read-write.
1589 if (pa >= trunc_2mpage(brwsection - KERNBASE))
1590 return (X86_PG_RW | pg_nx);
1593 * Mark any 2M page containing kernel text as read-only. Mark
1594 * other pages with read-only data as read-only and not executable.
1595 * (It is likely a small portion of the read-only data section will
1596 * be marked as read-only, but executable. This should be acceptable
1597 * since the read-only protection will keep the data from changing.)
1598 * Note that fixups to the .text section will still work until we
1601 if (pa < round_2mpage(etext - KERNBASE))
1607 create_pagetables(vm_paddr_t *firstaddr)
1609 int i, j, ndm1g, nkpdpe, nkdmpde;
1613 uint64_t DMPDkernphys;
1615 /* Allocate page table pages for the direct map */
1616 ndmpdp = howmany(ptoa(Maxmem), NBPDP);
1617 if (ndmpdp < 4) /* Minimum 4GB of dirmap */
1619 ndmpdpphys = howmany(ndmpdp, NPDPEPG);
1620 if (ndmpdpphys > NDMPML4E) {
1622 * Each NDMPML4E allows 512 GB, so limit to that,
1623 * and then readjust ndmpdp and ndmpdpphys.
1625 printf("NDMPML4E limits system to %d GB\n", NDMPML4E * 512);
1626 Maxmem = atop(NDMPML4E * NBPML4);
1627 ndmpdpphys = NDMPML4E;
1628 ndmpdp = NDMPML4E * NPDEPG;
1630 DMPDPphys = allocpages(firstaddr, ndmpdpphys);
1632 if ((amd_feature & AMDID_PAGE1GB) != 0) {
1634 * Calculate the number of 1G pages that will fully fit in
1637 ndm1g = ptoa(Maxmem) >> PDPSHIFT;
1640 * Allocate 2M pages for the kernel. These will be used in
1641 * place of the first one or more 1G pages from ndm1g.
1643 nkdmpde = howmany((vm_offset_t)(brwsection - KERNBASE), NBPDP);
1644 DMPDkernphys = allocpages(firstaddr, nkdmpde);
1647 DMPDphys = allocpages(firstaddr, ndmpdp - ndm1g);
1648 dmaplimit = (vm_paddr_t)ndmpdp << PDPSHIFT;
1650 /* Allocate pages */
1651 KPML4phys = allocpages(firstaddr, 1);
1652 KPDPphys = allocpages(firstaddr, NKPML4E);
1655 * Allocate the initial number of kernel page table pages required to
1656 * bootstrap. We defer this until after all memory-size dependent
1657 * allocations are done (e.g. direct map), so that we don't have to
1658 * build in too much slop in our estimate.
1660 * Note that when NKPML4E > 1, we have an empty page underneath
1661 * all but the KPML4I'th one, so we need NKPML4E-1 extra (zeroed)
1662 * pages. (pmap_enter requires a PD page to exist for each KPML4E.)
1664 nkpt_init(*firstaddr);
1665 nkpdpe = NKPDPE(nkpt);
1667 KPTphys = allocpages(firstaddr, nkpt);
1668 KPDphys = allocpages(firstaddr, nkpdpe);
1671 * Connect the zero-filled PT pages to their PD entries. This
1672 * implicitly maps the PT pages at their correct locations within
1675 pd_p = (pd_entry_t *)KPDphys;
1676 for (i = 0; i < nkpt; i++)
1677 pd_p[i] = (KPTphys + ptoa(i)) | X86_PG_RW | X86_PG_V;
1680 * Map from physical address zero to the end of loader preallocated
1681 * memory using 2MB pages. This replaces some of the PD entries
1684 for (i = 0; (i << PDRSHIFT) < KERNend; i++)
1685 /* Preset PG_M and PG_A because demotion expects it. */
1686 pd_p[i] = (i << PDRSHIFT) | X86_PG_V | PG_PS | pg_g |
1687 X86_PG_M | X86_PG_A | bootaddr_rwx(i << PDRSHIFT);
1690 * Because we map the physical blocks in 2M pages, adjust firstaddr
1691 * to record the physical blocks we've actually mapped into kernel
1692 * virtual address space.
1694 if (*firstaddr < round_2mpage(KERNend))
1695 *firstaddr = round_2mpage(KERNend);
1697 /* And connect up the PD to the PDP (leaving room for L4 pages) */
1698 pdp_p = (pdp_entry_t *)(KPDPphys + ptoa(KPML4I - KPML4BASE));
1699 for (i = 0; i < nkpdpe; i++)
1700 pdp_p[i + KPDPI] = (KPDphys + ptoa(i)) | X86_PG_RW | X86_PG_V;
1703 * Now, set up the direct map region using 2MB and/or 1GB pages. If
1704 * the end of physical memory is not aligned to a 1GB page boundary,
1705 * then the residual physical memory is mapped with 2MB pages. Later,
1706 * if pmap_mapdev{_attr}() uses the direct map for non-write-back
1707 * memory, pmap_change_attr() will demote any 2MB or 1GB page mappings
1708 * that are partially used.
1710 pd_p = (pd_entry_t *)DMPDphys;
1711 for (i = NPDEPG * ndm1g, j = 0; i < NPDEPG * ndmpdp; i++, j++) {
1712 pd_p[j] = (vm_paddr_t)i << PDRSHIFT;
1713 /* Preset PG_M and PG_A because demotion expects it. */
1714 pd_p[j] |= X86_PG_RW | X86_PG_V | PG_PS | pg_g |
1715 X86_PG_M | X86_PG_A | pg_nx;
1717 pdp_p = (pdp_entry_t *)DMPDPphys;
1718 for (i = 0; i < ndm1g; i++) {
1719 pdp_p[i] = (vm_paddr_t)i << PDPSHIFT;
1720 /* Preset PG_M and PG_A because demotion expects it. */
1721 pdp_p[i] |= X86_PG_RW | X86_PG_V | PG_PS | pg_g |
1722 X86_PG_M | X86_PG_A | pg_nx;
1724 for (j = 0; i < ndmpdp; i++, j++) {
1725 pdp_p[i] = DMPDphys + ptoa(j);
1726 pdp_p[i] |= X86_PG_RW | X86_PG_V | pg_nx;
1730 * Instead of using a 1G page for the memory containing the kernel,
1731 * use 2M pages with read-only and no-execute permissions. (If using 1G
1732 * pages, this will partially overwrite the PDPEs above.)
1735 pd_p = (pd_entry_t *)DMPDkernphys;
1736 for (i = 0; i < (NPDEPG * nkdmpde); i++)
1737 pd_p[i] = (i << PDRSHIFT) | X86_PG_V | PG_PS | pg_g |
1738 X86_PG_M | X86_PG_A | pg_nx |
1739 bootaddr_rwx(i << PDRSHIFT);
1740 for (i = 0; i < nkdmpde; i++)
1741 pdp_p[i] = (DMPDkernphys + ptoa(i)) | X86_PG_RW |
1745 /* And recursively map PML4 to itself in order to get PTmap */
1746 p4_p = (pml4_entry_t *)KPML4phys;
1747 p4_p[PML4PML4I] = KPML4phys;
1748 p4_p[PML4PML4I] |= X86_PG_RW | X86_PG_V | pg_nx;
1750 /* Connect the Direct Map slot(s) up to the PML4. */
1751 for (i = 0; i < ndmpdpphys; i++) {
1752 p4_p[DMPML4I + i] = DMPDPphys + ptoa(i);
1753 p4_p[DMPML4I + i] |= X86_PG_RW | X86_PG_V | pg_nx;
1756 /* Connect the KVA slots up to the PML4 */
1757 for (i = 0; i < NKPML4E; i++) {
1758 p4_p[KPML4BASE + i] = KPDPphys + ptoa(i);
1759 p4_p[KPML4BASE + i] |= X86_PG_RW | X86_PG_V;
1762 kernel_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(KPML4phys);
1766 * Bootstrap the system enough to run with virtual memory.
1768 * On amd64 this is called after mapping has already been enabled
1769 * and just syncs the pmap module with what has already been done.
1770 * [We can't call it easily with mapping off since the kernel is not
1771 * mapped with PA == VA, hence we would have to relocate every address
1772 * from the linked base (virtual) address "KERNBASE" to the actual
1773 * (physical) address starting relative to 0]
1776 pmap_bootstrap(vm_paddr_t *firstaddr)
1779 pt_entry_t *pte, *pcpu_pte;
1780 struct region_descriptor r_gdt;
1781 uint64_t cr4, pcpu_phys;
1785 KERNend = *firstaddr;
1786 res = atop(KERNend - (vm_paddr_t)kernphys);
1792 * Create an initial set of page tables to run the kernel in.
1794 create_pagetables(firstaddr);
1796 pcpu_phys = allocpages(firstaddr, MAXCPU);
1799 * Add a physical memory segment (vm_phys_seg) corresponding to the
1800 * preallocated kernel page table pages so that vm_page structures
1801 * representing these pages will be created. The vm_page structures
1802 * are required for promotion of the corresponding kernel virtual
1803 * addresses to superpage mappings.
1805 vm_phys_early_add_seg(KPTphys, KPTphys + ptoa(nkpt));
1808 * Account for the virtual addresses mapped by create_pagetables().
1810 virtual_avail = (vm_offset_t)KERNBASE + round_2mpage(KERNend);
1811 virtual_end = VM_MAX_KERNEL_ADDRESS;
1814 * Enable PG_G global pages, then switch to the kernel page
1815 * table from the bootstrap page table. After the switch, it
1816 * is possible to enable SMEP and SMAP since PG_U bits are
1822 load_cr3(KPML4phys);
1823 if (cpu_stdext_feature & CPUID_STDEXT_SMEP)
1825 if (cpu_stdext_feature & CPUID_STDEXT_SMAP)
1830 * Initialize the kernel pmap (which is statically allocated).
1831 * Count bootstrap data as being resident in case any of this data is
1832 * later unmapped (using pmap_remove()) and freed.
1834 PMAP_LOCK_INIT(kernel_pmap);
1835 kernel_pmap->pm_pmltop = kernel_pml4;
1836 kernel_pmap->pm_cr3 = KPML4phys;
1837 kernel_pmap->pm_ucr3 = PMAP_NO_CR3;
1838 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */
1839 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
1840 kernel_pmap->pm_stats.resident_count = res;
1841 kernel_pmap->pm_flags = pmap_flags;
1844 * Initialize the TLB invalidations generation number lock.
1846 mtx_init(&invl_gen_mtx, "invlgn", NULL, MTX_DEF);
1849 * Reserve some special page table entries/VA space for temporary
1852 #define SYSMAP(c, p, v, n) \
1853 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n);
1859 * Crashdump maps. The first page is reused as CMAP1 for the
1862 SYSMAP(caddr_t, CMAP1, crashdumpmap, MAXDUMPPGS)
1863 CADDR1 = crashdumpmap;
1865 SYSMAP(struct pcpu *, pcpu_pte, __pcpu, MAXCPU);
1868 for (i = 0; i < MAXCPU; i++) {
1869 pcpu_pte[i] = (pcpu_phys + ptoa(i)) | X86_PG_V | X86_PG_RW |
1870 pg_g | pg_nx | X86_PG_M | X86_PG_A;
1874 * Re-initialize PCPU area for BSP after switching.
1875 * Make hardware use gdt and common_tss from the new PCPU.
1877 STAILQ_INIT(&cpuhead);
1878 wrmsr(MSR_GSBASE, (uint64_t)&__pcpu[0]);
1879 pcpu_init(&__pcpu[0], 0, sizeof(struct pcpu));
1880 amd64_bsp_pcpu_init1(&__pcpu[0]);
1881 amd64_bsp_ist_init(&__pcpu[0]);
1882 __pcpu[0].pc_common_tss.tss_iobase = sizeof(struct amd64tss) +
1884 memcpy(__pcpu[0].pc_gdt, temp_bsp_pcpu.pc_gdt, NGDT *
1885 sizeof(struct user_segment_descriptor));
1886 gdt_segs[GPROC0_SEL].ssd_base = (uintptr_t)&__pcpu[0].pc_common_tss;
1887 ssdtosyssd(&gdt_segs[GPROC0_SEL],
1888 (struct system_segment_descriptor *)&__pcpu[0].pc_gdt[GPROC0_SEL]);
1889 r_gdt.rd_limit = NGDT * sizeof(struct user_segment_descriptor) - 1;
1890 r_gdt.rd_base = (long)__pcpu[0].pc_gdt;
1892 wrmsr(MSR_GSBASE, (uint64_t)&__pcpu[0]);
1893 ltr(GSEL(GPROC0_SEL, SEL_KPL));
1894 __pcpu[0].pc_dynamic = temp_bsp_pcpu.pc_dynamic;
1895 __pcpu[0].pc_acpi_id = temp_bsp_pcpu.pc_acpi_id;
1898 * Initialize the PAT MSR.
1899 * pmap_init_pat() clears and sets CR4_PGE, which, as a
1900 * side-effect, invalidates stale PG_G TLB entries that might
1901 * have been created in our pre-boot environment.
1905 /* Initialize TLB Context Id. */
1906 if (pmap_pcid_enabled) {
1907 for (i = 0; i < MAXCPU; i++) {
1908 kernel_pmap->pm_pcids[i].pm_pcid = PMAP_PCID_KERN;
1909 kernel_pmap->pm_pcids[i].pm_gen = 1;
1913 * PMAP_PCID_KERN + 1 is used for initialization of
1914 * proc0 pmap. The pmap' pcid state might be used by
1915 * EFIRT entry before first context switch, so it
1916 * needs to be valid.
1918 PCPU_SET(pcid_next, PMAP_PCID_KERN + 2);
1919 PCPU_SET(pcid_gen, 1);
1922 * pcpu area for APs is zeroed during AP startup.
1923 * pc_pcid_next and pc_pcid_gen are initialized by AP
1924 * during pcpu setup.
1926 load_cr4(rcr4() | CR4_PCIDE);
1931 * Setup the PAT MSR.
1940 /* Bail if this CPU doesn't implement PAT. */
1941 if ((cpu_feature & CPUID_PAT) == 0)
1944 /* Set default PAT index table. */
1945 for (i = 0; i < PAT_INDEX_SIZE; i++)
1947 pat_index[PAT_WRITE_BACK] = 0;
1948 pat_index[PAT_WRITE_THROUGH] = 1;
1949 pat_index[PAT_UNCACHEABLE] = 3;
1950 pat_index[PAT_WRITE_COMBINING] = 6;
1951 pat_index[PAT_WRITE_PROTECTED] = 5;
1952 pat_index[PAT_UNCACHED] = 2;
1955 * Initialize default PAT entries.
1956 * Leave the indices 0-3 at the default of WB, WT, UC-, and UC.
1957 * Program 5 and 6 as WP and WC.
1959 * Leave 4 and 7 as WB and UC. Note that a recursive page table
1960 * mapping for a 2M page uses a PAT value with the bit 3 set due
1961 * to its overload with PG_PS.
1963 pat_msr = PAT_VALUE(0, PAT_WRITE_BACK) |
1964 PAT_VALUE(1, PAT_WRITE_THROUGH) |
1965 PAT_VALUE(2, PAT_UNCACHED) |
1966 PAT_VALUE(3, PAT_UNCACHEABLE) |
1967 PAT_VALUE(4, PAT_WRITE_BACK) |
1968 PAT_VALUE(5, PAT_WRITE_PROTECTED) |
1969 PAT_VALUE(6, PAT_WRITE_COMBINING) |
1970 PAT_VALUE(7, PAT_UNCACHEABLE);
1974 load_cr4(cr4 & ~CR4_PGE);
1976 /* Disable caches (CD = 1, NW = 0). */
1978 load_cr0((cr0 & ~CR0_NW) | CR0_CD);
1980 /* Flushes caches and TLBs. */
1984 /* Update PAT and index table. */
1985 wrmsr(MSR_PAT, pat_msr);
1987 /* Flush caches and TLBs again. */
1991 /* Restore caches and PGE. */
1996 extern const char la57_trampoline[], la57_trampoline_gdt_desc[],
1997 la57_trampoline_gdt[], la57_trampoline_end[];
2000 pmap_bootstrap_la57(void *arg __unused)
2003 pml5_entry_t *v_pml5;
2004 pml4_entry_t *v_pml4;
2008 vm_page_t m_code, m_pml4, m_pdp, m_pd, m_pt, m_pml5;
2009 void (*la57_tramp)(uint64_t pml5);
2010 struct region_descriptor r_gdt;
2012 if ((cpu_stdext_feature2 & CPUID_STDEXT2_LA57) == 0)
2014 if (!TUNABLE_INT_FETCH("vm.pmap.la57", &la57))
2019 r_gdt.rd_limit = NGDT * sizeof(struct user_segment_descriptor) - 1;
2020 r_gdt.rd_base = (long)__pcpu[0].pc_gdt;
2022 m_code = vm_page_alloc_contig(NULL, 0,
2023 VM_ALLOC_NORMAL | VM_ALLOC_NOBUSY | VM_ALLOC_ZERO | VM_ALLOC_NOOBJ,
2024 1, 0, (1ULL << 32), PAGE_SIZE, 0, VM_MEMATTR_DEFAULT);
2025 if ((m_code->flags & PG_ZERO) == 0)
2026 pmap_zero_page(m_code);
2027 v_code = (char *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m_code));
2028 m_pml5 = vm_page_alloc_contig(NULL, 0,
2029 VM_ALLOC_NORMAL | VM_ALLOC_NOBUSY | VM_ALLOC_ZERO | VM_ALLOC_NOOBJ,
2030 1, 0, (1ULL << 32), PAGE_SIZE, 0, VM_MEMATTR_DEFAULT);
2031 if ((m_pml5->flags & PG_ZERO) == 0)
2032 pmap_zero_page(m_pml5);
2033 KPML5phys = VM_PAGE_TO_PHYS(m_pml5);
2034 v_pml5 = (pml5_entry_t *)PHYS_TO_DMAP(KPML5phys);
2035 m_pml4 = vm_page_alloc_contig(NULL, 0,
2036 VM_ALLOC_NORMAL | VM_ALLOC_NOBUSY | VM_ALLOC_ZERO | VM_ALLOC_NOOBJ,
2037 1, 0, (1ULL << 32), PAGE_SIZE, 0, VM_MEMATTR_DEFAULT);
2038 if ((m_pml4->flags & PG_ZERO) == 0)
2039 pmap_zero_page(m_pml4);
2040 v_pml4 = (pdp_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m_pml4));
2041 m_pdp = vm_page_alloc_contig(NULL, 0,
2042 VM_ALLOC_NORMAL | VM_ALLOC_NOBUSY | VM_ALLOC_ZERO | VM_ALLOC_NOOBJ,
2043 1, 0, (1ULL << 32), PAGE_SIZE, 0, VM_MEMATTR_DEFAULT);
2044 if ((m_pdp->flags & PG_ZERO) == 0)
2045 pmap_zero_page(m_pdp);
2046 v_pdp = (pdp_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m_pdp));
2047 m_pd = vm_page_alloc_contig(NULL, 0,
2048 VM_ALLOC_NORMAL | VM_ALLOC_NOBUSY | VM_ALLOC_ZERO | VM_ALLOC_NOOBJ,
2049 1, 0, (1ULL << 32), PAGE_SIZE, 0, VM_MEMATTR_DEFAULT);
2050 if ((m_pd->flags & PG_ZERO) == 0)
2051 pmap_zero_page(m_pd);
2052 v_pd = (pdp_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m_pd));
2053 m_pt = vm_page_alloc_contig(NULL, 0,
2054 VM_ALLOC_NORMAL | VM_ALLOC_NOBUSY | VM_ALLOC_ZERO | VM_ALLOC_NOOBJ,
2055 1, 0, (1ULL << 32), PAGE_SIZE, 0, VM_MEMATTR_DEFAULT);
2056 if ((m_pt->flags & PG_ZERO) == 0)
2057 pmap_zero_page(m_pt);
2058 v_pt = (pt_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m_pt));
2061 * Map m_code 1:1, it appears below 4G in KVA due to physical
2062 * address being below 4G. Since kernel KVA is in upper half,
2063 * the pml4e should be zero and free for temporary use.
2065 kernel_pmap->pm_pmltop[pmap_pml4e_index(VM_PAGE_TO_PHYS(m_code))] =
2066 VM_PAGE_TO_PHYS(m_pdp) | X86_PG_V | X86_PG_RW | X86_PG_A |
2068 v_pdp[pmap_pdpe_index(VM_PAGE_TO_PHYS(m_code))] =
2069 VM_PAGE_TO_PHYS(m_pd) | X86_PG_V | X86_PG_RW | X86_PG_A |
2071 v_pd[pmap_pde_index(VM_PAGE_TO_PHYS(m_code))] =
2072 VM_PAGE_TO_PHYS(m_pt) | X86_PG_V | X86_PG_RW | X86_PG_A |
2074 v_pt[pmap_pte_index(VM_PAGE_TO_PHYS(m_code))] =
2075 VM_PAGE_TO_PHYS(m_code) | X86_PG_V | X86_PG_RW | X86_PG_A |
2079 * Add pml5 entry at top of KVA pointing to existing pml4 table,
2080 * entering all existing kernel mappings into level 5 table.
2082 v_pml5[pmap_pml5e_index(UPT_MAX_ADDRESS)] = KPML4phys | X86_PG_V |
2083 X86_PG_RW | X86_PG_A | X86_PG_M | pg_g;
2086 * Add pml5 entry for 1:1 trampoline mapping after LA57 is turned on.
2088 v_pml5[pmap_pml5e_index(VM_PAGE_TO_PHYS(m_code))] =
2089 VM_PAGE_TO_PHYS(m_pml4) | X86_PG_V | X86_PG_RW | X86_PG_A |
2091 v_pml4[pmap_pml4e_index(VM_PAGE_TO_PHYS(m_code))] =
2092 VM_PAGE_TO_PHYS(m_pdp) | X86_PG_V | X86_PG_RW | X86_PG_A |
2096 * Copy and call the 48->57 trampoline, hope we return there, alive.
2098 bcopy(la57_trampoline, v_code, la57_trampoline_end - la57_trampoline);
2099 *(u_long *)(v_code + 2 + (la57_trampoline_gdt_desc - la57_trampoline)) =
2100 la57_trampoline_gdt - la57_trampoline + VM_PAGE_TO_PHYS(m_code);
2101 la57_tramp = (void (*)(uint64_t))VM_PAGE_TO_PHYS(m_code);
2102 la57_tramp(KPML5phys);
2105 * gdt was necessary reset, switch back to our gdt.
2108 wrmsr(MSR_GSBASE, (uint64_t)&__pcpu[0]);
2112 ssdtosyssd(&gdt_segs[GPROC0_SEL],
2113 (struct system_segment_descriptor *)&__pcpu[0].pc_gdt[GPROC0_SEL]);
2114 ltr(GSEL(GPROC0_SEL, SEL_KPL));
2117 * Now unmap the trampoline, and free the pages.
2118 * Clear pml5 entry used for 1:1 trampoline mapping.
2120 pte_clear(&v_pml5[pmap_pml5e_index(VM_PAGE_TO_PHYS(m_code))]);
2121 invlpg((vm_offset_t)v_code);
2122 vm_page_free(m_code);
2123 vm_page_free(m_pdp);
2128 * Recursively map PML5 to itself in order to get PTmap and
2131 v_pml5[PML5PML5I] = KPML5phys | X86_PG_RW | X86_PG_V | pg_nx;
2133 kernel_pmap->pm_cr3 = KPML5phys;
2134 kernel_pmap->pm_pmltop = v_pml5;
2136 SYSINIT(la57, SI_SUB_KMEM, SI_ORDER_ANY, pmap_bootstrap_la57, NULL);
2139 * Initialize a vm_page's machine-dependent fields.
2142 pmap_page_init(vm_page_t m)
2145 TAILQ_INIT(&m->md.pv_list);
2146 m->md.pat_mode = PAT_WRITE_BACK;
2149 static int pmap_allow_2m_x_ept;
2150 SYSCTL_INT(_vm_pmap, OID_AUTO, allow_2m_x_ept, CTLFLAG_RWTUN | CTLFLAG_NOFETCH,
2151 &pmap_allow_2m_x_ept, 0,
2152 "Allow executable superpage mappings in EPT");
2155 pmap_allow_2m_x_ept_recalculate(void)
2158 * SKL002, SKL012S. Since the EPT format is only used by
2159 * Intel CPUs, the vendor check is merely a formality.
2161 if (!(cpu_vendor_id != CPU_VENDOR_INTEL ||
2162 (cpu_ia32_arch_caps & IA32_ARCH_CAP_IF_PSCHANGE_MC_NO) != 0 ||
2163 (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
2164 (CPUID_TO_MODEL(cpu_id) == 0x26 || /* Atoms */
2165 CPUID_TO_MODEL(cpu_id) == 0x27 ||
2166 CPUID_TO_MODEL(cpu_id) == 0x35 ||
2167 CPUID_TO_MODEL(cpu_id) == 0x36 ||
2168 CPUID_TO_MODEL(cpu_id) == 0x37 ||
2169 CPUID_TO_MODEL(cpu_id) == 0x86 ||
2170 CPUID_TO_MODEL(cpu_id) == 0x1c ||
2171 CPUID_TO_MODEL(cpu_id) == 0x4a ||
2172 CPUID_TO_MODEL(cpu_id) == 0x4c ||
2173 CPUID_TO_MODEL(cpu_id) == 0x4d ||
2174 CPUID_TO_MODEL(cpu_id) == 0x5a ||
2175 CPUID_TO_MODEL(cpu_id) == 0x5c ||
2176 CPUID_TO_MODEL(cpu_id) == 0x5d ||
2177 CPUID_TO_MODEL(cpu_id) == 0x5f ||
2178 CPUID_TO_MODEL(cpu_id) == 0x6e ||
2179 CPUID_TO_MODEL(cpu_id) == 0x7a ||
2180 CPUID_TO_MODEL(cpu_id) == 0x57 || /* Knights */
2181 CPUID_TO_MODEL(cpu_id) == 0x85))))
2182 pmap_allow_2m_x_ept = 1;
2183 TUNABLE_INT_FETCH("hw.allow_2m_x_ept", &pmap_allow_2m_x_ept);
2187 pmap_allow_2m_x_page(pmap_t pmap, bool executable)
2190 return (pmap->pm_type != PT_EPT || !executable ||
2191 !pmap_allow_2m_x_ept);
2196 pmap_init_pv_table(void)
2198 struct pmap_large_md_page *pvd;
2200 long start, end, highest, pv_npg;
2201 int domain, i, j, pages;
2204 * We strongly depend on the size being a power of two, so the assert
2205 * is overzealous. However, should the struct be resized to a
2206 * different power of two, the code below needs to be revisited.
2208 CTASSERT((sizeof(*pvd) == 64));
2211 * Calculate the size of the array.
2213 pmap_last_pa = vm_phys_segs[vm_phys_nsegs - 1].end;
2214 pv_npg = howmany(pmap_last_pa, NBPDR);
2215 s = (vm_size_t)pv_npg * sizeof(struct pmap_large_md_page);
2217 pv_table = (struct pmap_large_md_page *)kva_alloc(s);
2218 if (pv_table == NULL)
2219 panic("%s: kva_alloc failed\n", __func__);
2222 * Iterate physical segments to allocate space for respective pages.
2226 for (i = 0; i < vm_phys_nsegs; i++) {
2227 end = vm_phys_segs[i].end / NBPDR;
2228 domain = vm_phys_segs[i].domain;
2233 start = highest + 1;
2234 pvd = &pv_table[start];
2236 pages = end - start + 1;
2237 s = round_page(pages * sizeof(*pvd));
2238 highest = start + (s / sizeof(*pvd)) - 1;
2240 for (j = 0; j < s; j += PAGE_SIZE) {
2241 vm_page_t m = vm_page_alloc_domain(NULL, 0,
2242 domain, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ);
2244 panic("vm_page_alloc_domain failed for %lx\n", (vm_offset_t)pvd + j);
2245 pmap_qenter((vm_offset_t)pvd + j, &m, 1);
2248 for (j = 0; j < s / sizeof(*pvd); j++) {
2249 rw_init_flags(&pvd->pv_lock, "pmap pv list", RW_NEW);
2250 TAILQ_INIT(&pvd->pv_page.pv_list);
2251 pvd->pv_page.pv_gen = 0;
2252 pvd->pv_page.pat_mode = 0;
2253 pvd->pv_invl_gen = 0;
2257 pvd = &pv_dummy_large;
2258 rw_init_flags(&pvd->pv_lock, "pmap pv list dummy", RW_NEW);
2259 TAILQ_INIT(&pvd->pv_page.pv_list);
2260 pvd->pv_page.pv_gen = 0;
2261 pvd->pv_page.pat_mode = 0;
2262 pvd->pv_invl_gen = 0;
2266 pmap_init_pv_table(void)
2272 * Initialize the pool of pv list locks.
2274 for (i = 0; i < NPV_LIST_LOCKS; i++)
2275 rw_init(&pv_list_locks[i], "pmap pv list");
2278 * Calculate the size of the pv head table for superpages.
2280 pv_npg = howmany(vm_phys_segs[vm_phys_nsegs - 1].end, NBPDR);
2283 * Allocate memory for the pv head table for superpages.
2285 s = (vm_size_t)pv_npg * sizeof(struct md_page);
2287 pv_table = (struct md_page *)kmem_malloc(s, M_WAITOK | M_ZERO);
2288 for (i = 0; i < pv_npg; i++)
2289 TAILQ_INIT(&pv_table[i].pv_list);
2290 TAILQ_INIT(&pv_dummy.pv_list);
2295 * Initialize the pmap module.
2296 * Called by vm_init, to initialize any structures that the pmap
2297 * system needs to map virtual memory.
2302 struct pmap_preinit_mapping *ppim;
2304 int error, i, ret, skz63;
2306 /* L1TF, reserve page @0 unconditionally */
2307 vm_page_blacklist_add(0, bootverbose);
2309 /* Detect bare-metal Skylake Server and Skylake-X. */
2310 if (vm_guest == VM_GUEST_NO && cpu_vendor_id == CPU_VENDOR_INTEL &&
2311 CPUID_TO_FAMILY(cpu_id) == 0x6 && CPUID_TO_MODEL(cpu_id) == 0x55) {
2313 * Skylake-X errata SKZ63. Processor May Hang When
2314 * Executing Code In an HLE Transaction Region between
2315 * 40000000H and 403FFFFFH.
2317 * Mark the pages in the range as preallocated. It
2318 * seems to be impossible to distinguish between
2319 * Skylake Server and Skylake X.
2322 TUNABLE_INT_FETCH("hw.skz63_enable", &skz63);
2325 printf("SKZ63: skipping 4M RAM starting "
2326 "at physical 1G\n");
2327 for (i = 0; i < atop(0x400000); i++) {
2328 ret = vm_page_blacklist_add(0x40000000 +
2330 if (!ret && bootverbose)
2331 printf("page at %#lx already used\n",
2332 0x40000000 + ptoa(i));
2338 pmap_allow_2m_x_ept_recalculate();
2341 * Initialize the vm page array entries for the kernel pmap's
2344 PMAP_LOCK(kernel_pmap);
2345 for (i = 0; i < nkpt; i++) {
2346 mpte = PHYS_TO_VM_PAGE(KPTphys + (i << PAGE_SHIFT));
2347 KASSERT(mpte >= vm_page_array &&
2348 mpte < &vm_page_array[vm_page_array_size],
2349 ("pmap_init: page table page is out of range"));
2350 mpte->pindex = pmap_pde_pindex(KERNBASE) + i;
2351 mpte->phys_addr = KPTphys + (i << PAGE_SHIFT);
2352 mpte->ref_count = 1;
2355 * Collect the page table pages that were replaced by a 2MB
2356 * page in create_pagetables(). They are zero filled.
2358 if ((vm_paddr_t)i << PDRSHIFT < KERNend &&
2359 pmap_insert_pt_page(kernel_pmap, mpte, false))
2360 panic("pmap_init: pmap_insert_pt_page failed");
2362 PMAP_UNLOCK(kernel_pmap);
2366 * If the kernel is running on a virtual machine, then it must assume
2367 * that MCA is enabled by the hypervisor. Moreover, the kernel must
2368 * be prepared for the hypervisor changing the vendor and family that
2369 * are reported by CPUID. Consequently, the workaround for AMD Family
2370 * 10h Erratum 383 is enabled if the processor's feature set does not
2371 * include at least one feature that is only supported by older Intel
2372 * or newer AMD processors.
2374 if (vm_guest != VM_GUEST_NO && (cpu_feature & CPUID_SS) == 0 &&
2375 (cpu_feature2 & (CPUID2_SSSE3 | CPUID2_SSE41 | CPUID2_AESNI |
2376 CPUID2_AVX | CPUID2_XSAVE)) == 0 && (amd_feature2 & (AMDID2_XOP |
2378 workaround_erratum383 = 1;
2381 * Are large page mappings enabled?
2383 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled);
2384 if (pg_ps_enabled) {
2385 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
2386 ("pmap_init: can't assign to pagesizes[1]"));
2387 pagesizes[1] = NBPDR;
2388 if ((amd_feature & AMDID_PAGE1GB) != 0) {
2389 KASSERT(MAXPAGESIZES > 2 && pagesizes[2] == 0,
2390 ("pmap_init: can't assign to pagesizes[2]"));
2391 pagesizes[2] = NBPDP;
2396 * Initialize pv chunk lists.
2398 for (i = 0; i < PMAP_MEMDOM; i++) {
2399 mtx_init(&pv_chunks[i].pvc_lock, "pmap pv chunk list", NULL, MTX_DEF);
2400 TAILQ_INIT(&pv_chunks[i].pvc_list);
2402 pmap_init_pv_table();
2404 pmap_initialized = 1;
2405 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
2406 ppim = pmap_preinit_mapping + i;
2409 /* Make the direct map consistent */
2410 if (ppim->pa < dmaplimit && ppim->pa + ppim->sz <= dmaplimit) {
2411 (void)pmap_change_attr(PHYS_TO_DMAP(ppim->pa),
2412 ppim->sz, ppim->mode);
2416 printf("PPIM %u: PA=%#lx, VA=%#lx, size=%#lx, mode=%#x\n", i,
2417 ppim->pa, ppim->va, ppim->sz, ppim->mode);
2420 mtx_init(&qframe_mtx, "qfrmlk", NULL, MTX_SPIN);
2421 error = vmem_alloc(kernel_arena, PAGE_SIZE, M_BESTFIT | M_WAITOK,
2422 (vmem_addr_t *)&qframe);
2424 panic("qframe allocation failed");
2427 TUNABLE_INT_FETCH("vm.pmap.large_map_pml4_entries", &lm_ents);
2428 if (lm_ents > LMEPML4I - LMSPML4I + 1)
2429 lm_ents = LMEPML4I - LMSPML4I + 1;
2431 printf("pmap: large map %u PML4 slots (%lu GB)\n",
2432 lm_ents, (u_long)lm_ents * (NBPML4 / 1024 / 1024 / 1024));
2434 large_vmem = vmem_create("large", LARGEMAP_MIN_ADDRESS,
2435 (vmem_size_t)lm_ents * NBPML4, PAGE_SIZE, 0, M_WAITOK);
2436 if (large_vmem == NULL) {
2437 printf("pmap: cannot create large map\n");
2440 for (i = 0; i < lm_ents; i++) {
2441 m = pmap_large_map_getptp_unlocked();
2443 kernel_pml4[LMSPML4I + i] = X86_PG_V |
2444 X86_PG_RW | X86_PG_A | X86_PG_M | pg_nx |
2450 SYSCTL_UINT(_vm_pmap, OID_AUTO, large_map_pml4_entries,
2451 CTLFLAG_RDTUN | CTLFLAG_NOFETCH, &lm_ents, 0,
2452 "Maximum number of PML4 entries for use by large map (tunable). "
2453 "Each entry corresponds to 512GB of address space.");
2455 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
2456 "2MB page mapping counters");
2458 static u_long pmap_pde_demotions;
2459 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, demotions, CTLFLAG_RD,
2460 &pmap_pde_demotions, 0, "2MB page demotions");
2462 static u_long pmap_pde_mappings;
2463 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD,
2464 &pmap_pde_mappings, 0, "2MB page mappings");
2466 static u_long pmap_pde_p_failures;
2467 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, p_failures, CTLFLAG_RD,
2468 &pmap_pde_p_failures, 0, "2MB page promotion failures");
2470 static u_long pmap_pde_promotions;
2471 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, promotions, CTLFLAG_RD,
2472 &pmap_pde_promotions, 0, "2MB page promotions");
2474 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pdpe, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
2475 "1GB page mapping counters");
2477 static u_long pmap_pdpe_demotions;
2478 SYSCTL_ULONG(_vm_pmap_pdpe, OID_AUTO, demotions, CTLFLAG_RD,
2479 &pmap_pdpe_demotions, 0, "1GB page demotions");
2481 /***************************************************
2482 * Low level helper routines.....
2483 ***************************************************/
2486 pmap_swap_pat(pmap_t pmap, pt_entry_t entry)
2488 int x86_pat_bits = X86_PG_PTE_PAT | X86_PG_PDE_PAT;
2490 switch (pmap->pm_type) {
2493 /* Verify that both PAT bits are not set at the same time */
2494 KASSERT((entry & x86_pat_bits) != x86_pat_bits,
2495 ("Invalid PAT bits in entry %#lx", entry));
2497 /* Swap the PAT bits if one of them is set */
2498 if ((entry & x86_pat_bits) != 0)
2499 entry ^= x86_pat_bits;
2503 * Nothing to do - the memory attributes are represented
2504 * the same way for regular pages and superpages.
2508 panic("pmap_switch_pat_bits: bad pm_type %d", pmap->pm_type);
2515 pmap_is_valid_memattr(pmap_t pmap __unused, vm_memattr_t mode)
2518 return (mode >= 0 && mode < PAT_INDEX_SIZE &&
2519 pat_index[(int)mode] >= 0);
2523 * Determine the appropriate bits to set in a PTE or PDE for a specified
2527 pmap_cache_bits(pmap_t pmap, int mode, boolean_t is_pde)
2529 int cache_bits, pat_flag, pat_idx;
2531 if (!pmap_is_valid_memattr(pmap, mode))
2532 panic("Unknown caching mode %d\n", mode);
2534 switch (pmap->pm_type) {
2537 /* The PAT bit is different for PTE's and PDE's. */
2538 pat_flag = is_pde ? X86_PG_PDE_PAT : X86_PG_PTE_PAT;
2540 /* Map the caching mode to a PAT index. */
2541 pat_idx = pat_index[mode];
2543 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */
2546 cache_bits |= pat_flag;
2548 cache_bits |= PG_NC_PCD;
2550 cache_bits |= PG_NC_PWT;
2554 cache_bits = EPT_PG_IGNORE_PAT | EPT_PG_MEMORY_TYPE(mode);
2558 panic("unsupported pmap type %d", pmap->pm_type);
2561 return (cache_bits);
2565 pmap_cache_mask(pmap_t pmap, boolean_t is_pde)
2569 switch (pmap->pm_type) {
2572 mask = is_pde ? X86_PG_PDE_CACHE : X86_PG_PTE_CACHE;
2575 mask = EPT_PG_IGNORE_PAT | EPT_PG_MEMORY_TYPE(0x7);
2578 panic("pmap_cache_mask: invalid pm_type %d", pmap->pm_type);
2585 pmap_pat_index(pmap_t pmap, pt_entry_t pte, bool is_pde)
2587 int pat_flag, pat_idx;
2590 switch (pmap->pm_type) {
2593 /* The PAT bit is different for PTE's and PDE's. */
2594 pat_flag = is_pde ? X86_PG_PDE_PAT : X86_PG_PTE_PAT;
2596 if ((pte & pat_flag) != 0)
2598 if ((pte & PG_NC_PCD) != 0)
2600 if ((pte & PG_NC_PWT) != 0)
2604 if ((pte & EPT_PG_IGNORE_PAT) != 0)
2605 panic("EPT PTE %#lx has no PAT memory type", pte);
2606 pat_idx = (pte & EPT_PG_MEMORY_TYPE(0x7)) >> 3;
2610 /* See pmap_init_pat(). */
2620 pmap_ps_enabled(pmap_t pmap)
2623 return (pg_ps_enabled && (pmap->pm_flags & PMAP_PDE_SUPERPAGE) != 0);
2627 pmap_update_pde_store(pmap_t pmap, pd_entry_t *pde, pd_entry_t newpde)
2630 switch (pmap->pm_type) {
2637 * This is a little bogus since the generation number is
2638 * supposed to be bumped up when a region of the address
2639 * space is invalidated in the page tables.
2641 * In this case the old PDE entry is valid but yet we want
2642 * to make sure that any mappings using the old entry are
2643 * invalidated in the TLB.
2645 * The reason this works as expected is because we rendezvous
2646 * "all" host cpus and force any vcpu context to exit as a
2649 atomic_add_acq_long(&pmap->pm_eptgen, 1);
2652 panic("pmap_update_pde_store: bad pm_type %d", pmap->pm_type);
2654 pde_store(pde, newpde);
2658 * After changing the page size for the specified virtual address in the page
2659 * table, flush the corresponding entries from the processor's TLB. Only the
2660 * calling processor's TLB is affected.
2662 * The calling thread must be pinned to a processor.
2665 pmap_update_pde_invalidate(pmap_t pmap, vm_offset_t va, pd_entry_t newpde)
2669 if (pmap_type_guest(pmap))
2672 KASSERT(pmap->pm_type == PT_X86,
2673 ("pmap_update_pde_invalidate: invalid type %d", pmap->pm_type));
2675 PG_G = pmap_global_bit(pmap);
2677 if ((newpde & PG_PS) == 0)
2678 /* Demotion: flush a specific 2MB page mapping. */
2680 else if ((newpde & PG_G) == 0)
2682 * Promotion: flush every 4KB page mapping from the TLB
2683 * because there are too many to flush individually.
2688 * Promotion: flush every 4KB page mapping from the TLB,
2689 * including any global (PG_G) mappings.
2697 * For SMP, these functions have to use the IPI mechanism for coherence.
2699 * N.B.: Before calling any of the following TLB invalidation functions,
2700 * the calling processor must ensure that all stores updating a non-
2701 * kernel page table are globally performed. Otherwise, another
2702 * processor could cache an old, pre-update entry without being
2703 * invalidated. This can happen one of two ways: (1) The pmap becomes
2704 * active on another processor after its pm_active field is checked by
2705 * one of the following functions but before a store updating the page
2706 * table is globally performed. (2) The pmap becomes active on another
2707 * processor before its pm_active field is checked but due to
2708 * speculative loads one of the following functions stills reads the
2709 * pmap as inactive on the other processor.
2711 * The kernel page table is exempt because its pm_active field is
2712 * immutable. The kernel page table is always active on every
2717 * Interrupt the cpus that are executing in the guest context.
2718 * This will force the vcpu to exit and the cached EPT mappings
2719 * will be invalidated by the host before the next vmresume.
2721 static __inline void
2722 pmap_invalidate_ept(pmap_t pmap)
2727 KASSERT(!CPU_ISSET(curcpu, &pmap->pm_active),
2728 ("pmap_invalidate_ept: absurd pm_active"));
2731 * The TLB mappings associated with a vcpu context are not
2732 * flushed each time a different vcpu is chosen to execute.
2734 * This is in contrast with a process's vtop mappings that
2735 * are flushed from the TLB on each context switch.
2737 * Therefore we need to do more than just a TLB shootdown on
2738 * the active cpus in 'pmap->pm_active'. To do this we keep
2739 * track of the number of invalidations performed on this pmap.
2741 * Each vcpu keeps a cache of this counter and compares it
2742 * just before a vmresume. If the counter is out-of-date an
2743 * invept will be done to flush stale mappings from the TLB.
2745 atomic_add_acq_long(&pmap->pm_eptgen, 1);
2748 * Force the vcpu to exit and trap back into the hypervisor.
2750 ipinum = pmap->pm_flags & PMAP_NESTED_IPIMASK;
2751 ipi_selected(pmap->pm_active, ipinum);
2756 pmap_invalidate_cpu_mask(pmap_t pmap)
2759 return (pmap == kernel_pmap ? all_cpus : pmap->pm_active);
2763 pmap_invalidate_page_pcid(pmap_t pmap, vm_offset_t va,
2764 const bool invpcid_works1)
2766 struct invpcid_descr d;
2767 uint64_t kcr3, ucr3;
2771 cpuid = PCPU_GET(cpuid);
2772 if (pmap == PCPU_GET(curpmap)) {
2773 if (pmap->pm_ucr3 != PMAP_NO_CR3 &&
2775 * If we context-switched right after
2776 * PCPU_GET(ucr3_load_mask), we could read the
2777 * ~CR3_PCID_SAVE mask, which causes us to skip
2778 * the code below to invalidate user pages. This
2779 * is handled in pmap_activate_sw_pcid_pti() by
2780 * clearing pm_gen if ucr3_load_mask is ~CR3_PCID_SAVE.
2782 PCPU_GET(ucr3_load_mask) == PMAP_UCR3_NOMASK) {
2784 * Because pm_pcid is recalculated on a
2785 * context switch, we must disable switching.
2786 * Otherwise, we might use a stale value
2790 pcid = pmap->pm_pcids[cpuid].pm_pcid;
2791 if (invpcid_works1) {
2792 d.pcid = pcid | PMAP_PCID_USER_PT;
2795 invpcid(&d, INVPCID_ADDR);
2797 kcr3 = pmap->pm_cr3 | pcid | CR3_PCID_SAVE;
2798 ucr3 = pmap->pm_ucr3 | pcid |
2799 PMAP_PCID_USER_PT | CR3_PCID_SAVE;
2800 pmap_pti_pcid_invlpg(ucr3, kcr3, va);
2805 pmap->pm_pcids[cpuid].pm_gen = 0;
2809 pmap->pm_pcids[i].pm_gen = 0;
2813 * The fence is between stores to pm_gen and the read of the
2814 * pm_active mask. We need to ensure that it is impossible
2815 * for us to miss the bit update in pm_active and
2816 * simultaneously observe a non-zero pm_gen in
2817 * pmap_activate_sw(), otherwise TLB update is missed.
2818 * Without the fence, IA32 allows such an outcome. Note that
2819 * pm_active is updated by a locked operation, which provides
2820 * the reciprocal fence.
2822 atomic_thread_fence_seq_cst();
2826 pmap_invalidate_page_pcid_invpcid(pmap_t pmap, vm_offset_t va)
2829 pmap_invalidate_page_pcid(pmap, va, true);
2833 pmap_invalidate_page_pcid_noinvpcid(pmap_t pmap, vm_offset_t va)
2836 pmap_invalidate_page_pcid(pmap, va, false);
2840 pmap_invalidate_page_nopcid(pmap_t pmap, vm_offset_t va)
2844 DEFINE_IFUNC(static, void, pmap_invalidate_page_mode, (pmap_t, vm_offset_t))
2847 if (pmap_pcid_enabled)
2848 return (invpcid_works ? pmap_invalidate_page_pcid_invpcid :
2849 pmap_invalidate_page_pcid_noinvpcid);
2850 return (pmap_invalidate_page_nopcid);
2854 pmap_invalidate_page_curcpu_cb(pmap_t pmap, vm_offset_t va,
2855 vm_offset_t addr2 __unused)
2858 if (pmap == kernel_pmap) {
2861 if (pmap == PCPU_GET(curpmap))
2863 pmap_invalidate_page_mode(pmap, va);
2868 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
2871 if (pmap_type_guest(pmap)) {
2872 pmap_invalidate_ept(pmap);
2876 KASSERT(pmap->pm_type == PT_X86,
2877 ("pmap_invalidate_page: invalid type %d", pmap->pm_type));
2879 smp_masked_invlpg(pmap_invalidate_cpu_mask(pmap), va, pmap,
2880 pmap_invalidate_page_curcpu_cb);
2883 /* 4k PTEs -- Chosen to exceed the total size of Broadwell L2 TLB */
2884 #define PMAP_INVLPG_THRESHOLD (4 * 1024 * PAGE_SIZE)
2887 pmap_invalidate_range_pcid(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
2888 const bool invpcid_works1)
2890 struct invpcid_descr d;
2891 uint64_t kcr3, ucr3;
2895 cpuid = PCPU_GET(cpuid);
2896 if (pmap == PCPU_GET(curpmap)) {
2897 if (pmap->pm_ucr3 != PMAP_NO_CR3 &&
2898 PCPU_GET(ucr3_load_mask) == PMAP_UCR3_NOMASK) {
2900 pcid = pmap->pm_pcids[cpuid].pm_pcid;
2901 if (invpcid_works1) {
2902 d.pcid = pcid | PMAP_PCID_USER_PT;
2905 for (; d.addr < eva; d.addr += PAGE_SIZE)
2906 invpcid(&d, INVPCID_ADDR);
2908 kcr3 = pmap->pm_cr3 | pcid | CR3_PCID_SAVE;
2909 ucr3 = pmap->pm_ucr3 | pcid |
2910 PMAP_PCID_USER_PT | CR3_PCID_SAVE;
2911 pmap_pti_pcid_invlrng(ucr3, kcr3, sva, eva);
2916 pmap->pm_pcids[cpuid].pm_gen = 0;
2920 pmap->pm_pcids[i].pm_gen = 0;
2922 /* See the comment in pmap_invalidate_page_pcid(). */
2923 atomic_thread_fence_seq_cst();
2927 pmap_invalidate_range_pcid_invpcid(pmap_t pmap, vm_offset_t sva,
2931 pmap_invalidate_range_pcid(pmap, sva, eva, true);
2935 pmap_invalidate_range_pcid_noinvpcid(pmap_t pmap, vm_offset_t sva,
2939 pmap_invalidate_range_pcid(pmap, sva, eva, false);
2943 pmap_invalidate_range_nopcid(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2947 DEFINE_IFUNC(static, void, pmap_invalidate_range_mode, (pmap_t, vm_offset_t,
2951 if (pmap_pcid_enabled)
2952 return (invpcid_works ? pmap_invalidate_range_pcid_invpcid :
2953 pmap_invalidate_range_pcid_noinvpcid);
2954 return (pmap_invalidate_range_nopcid);
2958 pmap_invalidate_range_curcpu_cb(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2962 if (pmap == kernel_pmap) {
2963 for (addr = sva; addr < eva; addr += PAGE_SIZE)
2966 if (pmap == PCPU_GET(curpmap)) {
2967 for (addr = sva; addr < eva; addr += PAGE_SIZE)
2970 pmap_invalidate_range_mode(pmap, sva, eva);
2975 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2978 if (eva - sva >= PMAP_INVLPG_THRESHOLD) {
2979 pmap_invalidate_all(pmap);
2983 if (pmap_type_guest(pmap)) {
2984 pmap_invalidate_ept(pmap);
2988 KASSERT(pmap->pm_type == PT_X86,
2989 ("pmap_invalidate_range: invalid type %d", pmap->pm_type));
2991 smp_masked_invlpg_range(pmap_invalidate_cpu_mask(pmap), sva, eva, pmap,
2992 pmap_invalidate_range_curcpu_cb);
2996 pmap_invalidate_all_pcid(pmap_t pmap, bool invpcid_works1)
2998 struct invpcid_descr d;
3003 if (pmap == kernel_pmap) {
3004 if (invpcid_works1) {
3005 bzero(&d, sizeof(d));
3006 invpcid(&d, INVPCID_CTXGLOB);
3011 cpuid = PCPU_GET(cpuid);
3012 if (pmap == PCPU_GET(curpmap)) {
3014 pcid = pmap->pm_pcids[cpuid].pm_pcid;
3015 if (invpcid_works1) {
3019 invpcid(&d, INVPCID_CTX);
3021 kcr3 = pmap->pm_cr3 | pcid;
3024 if (pmap->pm_ucr3 != PMAP_NO_CR3)
3025 PCPU_SET(ucr3_load_mask, ~CR3_PCID_SAVE);
3028 pmap->pm_pcids[cpuid].pm_gen = 0;
3031 pmap->pm_pcids[i].pm_gen = 0;
3034 /* See the comment in pmap_invalidate_page_pcid(). */
3035 atomic_thread_fence_seq_cst();
3039 pmap_invalidate_all_pcid_invpcid(pmap_t pmap)
3042 pmap_invalidate_all_pcid(pmap, true);
3046 pmap_invalidate_all_pcid_noinvpcid(pmap_t pmap)
3049 pmap_invalidate_all_pcid(pmap, false);
3053 pmap_invalidate_all_nopcid(pmap_t pmap)
3056 if (pmap == kernel_pmap)
3058 else if (pmap == PCPU_GET(curpmap))
3062 DEFINE_IFUNC(static, void, pmap_invalidate_all_mode, (pmap_t))
3065 if (pmap_pcid_enabled)
3066 return (invpcid_works ? pmap_invalidate_all_pcid_invpcid :
3067 pmap_invalidate_all_pcid_noinvpcid);
3068 return (pmap_invalidate_all_nopcid);
3072 pmap_invalidate_all_curcpu_cb(pmap_t pmap, vm_offset_t addr1 __unused,
3073 vm_offset_t addr2 __unused)
3076 pmap_invalidate_all_mode(pmap);
3080 pmap_invalidate_all(pmap_t pmap)
3083 if (pmap_type_guest(pmap)) {
3084 pmap_invalidate_ept(pmap);
3088 KASSERT(pmap->pm_type == PT_X86,
3089 ("pmap_invalidate_all: invalid type %d", pmap->pm_type));
3091 smp_masked_invltlb(pmap_invalidate_cpu_mask(pmap), pmap,
3092 pmap_invalidate_all_curcpu_cb);
3096 pmap_invalidate_cache_curcpu_cb(pmap_t pmap __unused, vm_offset_t va __unused,
3097 vm_offset_t addr2 __unused)
3104 pmap_invalidate_cache(void)
3107 smp_cache_flush(pmap_invalidate_cache_curcpu_cb);
3111 cpuset_t invalidate; /* processors that invalidate their TLB */
3116 u_int store; /* processor that updates the PDE */
3120 pmap_update_pde_action(void *arg)
3122 struct pde_action *act = arg;
3124 if (act->store == PCPU_GET(cpuid))
3125 pmap_update_pde_store(act->pmap, act->pde, act->newpde);
3129 pmap_update_pde_teardown(void *arg)
3131 struct pde_action *act = arg;
3133 if (CPU_ISSET(PCPU_GET(cpuid), &act->invalidate))
3134 pmap_update_pde_invalidate(act->pmap, act->va, act->newpde);
3138 * Change the page size for the specified virtual address in a way that
3139 * prevents any possibility of the TLB ever having two entries that map the
3140 * same virtual address using different page sizes. This is the recommended
3141 * workaround for Erratum 383 on AMD Family 10h processors. It prevents a
3142 * machine check exception for a TLB state that is improperly diagnosed as a
3146 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
3148 struct pde_action act;
3149 cpuset_t active, other_cpus;
3153 cpuid = PCPU_GET(cpuid);
3154 other_cpus = all_cpus;
3155 CPU_CLR(cpuid, &other_cpus);
3156 if (pmap == kernel_pmap || pmap_type_guest(pmap))
3159 active = pmap->pm_active;
3161 if (CPU_OVERLAP(&active, &other_cpus)) {
3163 act.invalidate = active;
3167 act.newpde = newpde;
3168 CPU_SET(cpuid, &active);
3169 smp_rendezvous_cpus(active,
3170 smp_no_rendezvous_barrier, pmap_update_pde_action,
3171 pmap_update_pde_teardown, &act);
3173 pmap_update_pde_store(pmap, pde, newpde);
3174 if (CPU_ISSET(cpuid, &active))
3175 pmap_update_pde_invalidate(pmap, va, newpde);
3181 * Normal, non-SMP, invalidation functions.
3184 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
3186 struct invpcid_descr d;
3187 uint64_t kcr3, ucr3;
3190 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
3194 KASSERT(pmap->pm_type == PT_X86,
3195 ("pmap_invalidate_range: unknown type %d", pmap->pm_type));
3197 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap)) {
3199 if (pmap == PCPU_GET(curpmap) && pmap_pcid_enabled &&
3200 pmap->pm_ucr3 != PMAP_NO_CR3) {
3202 pcid = pmap->pm_pcids[0].pm_pcid;
3203 if (invpcid_works) {
3204 d.pcid = pcid | PMAP_PCID_USER_PT;
3207 invpcid(&d, INVPCID_ADDR);
3209 kcr3 = pmap->pm_cr3 | pcid | CR3_PCID_SAVE;
3210 ucr3 = pmap->pm_ucr3 | pcid |
3211 PMAP_PCID_USER_PT | CR3_PCID_SAVE;
3212 pmap_pti_pcid_invlpg(ucr3, kcr3, va);
3216 } else if (pmap_pcid_enabled)
3217 pmap->pm_pcids[0].pm_gen = 0;
3221 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
3223 struct invpcid_descr d;
3225 uint64_t kcr3, ucr3;
3227 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
3231 KASSERT(pmap->pm_type == PT_X86,
3232 ("pmap_invalidate_range: unknown type %d", pmap->pm_type));
3234 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap)) {
3235 for (addr = sva; addr < eva; addr += PAGE_SIZE)
3237 if (pmap == PCPU_GET(curpmap) && pmap_pcid_enabled &&
3238 pmap->pm_ucr3 != PMAP_NO_CR3) {
3240 if (invpcid_works) {
3241 d.pcid = pmap->pm_pcids[0].pm_pcid |
3245 for (; d.addr < eva; d.addr += PAGE_SIZE)
3246 invpcid(&d, INVPCID_ADDR);
3248 kcr3 = pmap->pm_cr3 | pmap->pm_pcids[0].
3249 pm_pcid | CR3_PCID_SAVE;
3250 ucr3 = pmap->pm_ucr3 | pmap->pm_pcids[0].
3251 pm_pcid | PMAP_PCID_USER_PT | CR3_PCID_SAVE;
3252 pmap_pti_pcid_invlrng(ucr3, kcr3, sva, eva);
3256 } else if (pmap_pcid_enabled) {
3257 pmap->pm_pcids[0].pm_gen = 0;
3262 pmap_invalidate_all(pmap_t pmap)
3264 struct invpcid_descr d;
3265 uint64_t kcr3, ucr3;
3267 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
3271 KASSERT(pmap->pm_type == PT_X86,
3272 ("pmap_invalidate_all: unknown type %d", pmap->pm_type));
3274 if (pmap == kernel_pmap) {
3275 if (pmap_pcid_enabled && invpcid_works) {
3276 bzero(&d, sizeof(d));
3277 invpcid(&d, INVPCID_CTXGLOB);
3281 } else if (pmap == PCPU_GET(curpmap)) {
3282 if (pmap_pcid_enabled) {
3284 if (invpcid_works) {
3285 d.pcid = pmap->pm_pcids[0].pm_pcid;
3288 invpcid(&d, INVPCID_CTX);
3289 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
3290 d.pcid |= PMAP_PCID_USER_PT;
3291 invpcid(&d, INVPCID_CTX);
3294 kcr3 = pmap->pm_cr3 | pmap->pm_pcids[0].pm_pcid;
3295 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
3296 ucr3 = pmap->pm_ucr3 | pmap->pm_pcids[
3297 0].pm_pcid | PMAP_PCID_USER_PT;
3298 pmap_pti_pcid_invalidate(ucr3, kcr3);
3306 } else if (pmap_pcid_enabled) {
3307 pmap->pm_pcids[0].pm_gen = 0;
3312 pmap_invalidate_cache(void)
3319 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
3322 pmap_update_pde_store(pmap, pde, newpde);
3323 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap))
3324 pmap_update_pde_invalidate(pmap, va, newpde);
3326 pmap->pm_pcids[0].pm_gen = 0;
3331 pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va, pd_entry_t pde)
3335 * When the PDE has PG_PROMOTED set, the 2MB page mapping was created
3336 * by a promotion that did not invalidate the 512 4KB page mappings
3337 * that might exist in the TLB. Consequently, at this point, the TLB
3338 * may hold both 4KB and 2MB page mappings for the address range [va,
3339 * va + NBPDR). Therefore, the entire range must be invalidated here.
3340 * In contrast, when PG_PROMOTED is clear, the TLB will not hold any
3341 * 4KB page mappings for the address range [va, va + NBPDR), and so a
3342 * single INVLPG suffices to invalidate the 2MB page mapping from the
3345 if ((pde & PG_PROMOTED) != 0)
3346 pmap_invalidate_range(pmap, va, va + NBPDR - 1);
3348 pmap_invalidate_page(pmap, va);
3351 DEFINE_IFUNC(, void, pmap_invalidate_cache_range,
3352 (vm_offset_t sva, vm_offset_t eva))
3355 if ((cpu_feature & CPUID_SS) != 0)
3356 return (pmap_invalidate_cache_range_selfsnoop);
3357 if ((cpu_feature & CPUID_CLFSH) != 0)
3358 return (pmap_force_invalidate_cache_range);
3359 return (pmap_invalidate_cache_range_all);
3362 #define PMAP_CLFLUSH_THRESHOLD (2 * 1024 * 1024)
3365 pmap_invalidate_cache_range_check_align(vm_offset_t sva, vm_offset_t eva)
3368 KASSERT((sva & PAGE_MASK) == 0,
3369 ("pmap_invalidate_cache_range: sva not page-aligned"));
3370 KASSERT((eva & PAGE_MASK) == 0,
3371 ("pmap_invalidate_cache_range: eva not page-aligned"));
3375 pmap_invalidate_cache_range_selfsnoop(vm_offset_t sva, vm_offset_t eva)
3378 pmap_invalidate_cache_range_check_align(sva, eva);
3382 pmap_force_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva)
3385 sva &= ~(vm_offset_t)(cpu_clflush_line_size - 1);
3388 * XXX: Some CPUs fault, hang, or trash the local APIC
3389 * registers if we use CLFLUSH on the local APIC range. The
3390 * local APIC is always uncached, so we don't need to flush
3391 * for that range anyway.
3393 if (pmap_kextract(sva) == lapic_paddr)
3396 if ((cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0) {
3398 * Do per-cache line flush. Use a locked
3399 * instruction to insure that previous stores are
3400 * included in the write-back. The processor
3401 * propagates flush to other processors in the cache
3404 atomic_thread_fence_seq_cst();
3405 for (; sva < eva; sva += cpu_clflush_line_size)
3407 atomic_thread_fence_seq_cst();
3410 * Writes are ordered by CLFLUSH on Intel CPUs.
3412 if (cpu_vendor_id != CPU_VENDOR_INTEL)
3414 for (; sva < eva; sva += cpu_clflush_line_size)
3416 if (cpu_vendor_id != CPU_VENDOR_INTEL)
3422 pmap_invalidate_cache_range_all(vm_offset_t sva, vm_offset_t eva)
3425 pmap_invalidate_cache_range_check_align(sva, eva);
3426 pmap_invalidate_cache();
3430 * Remove the specified set of pages from the data and instruction caches.
3432 * In contrast to pmap_invalidate_cache_range(), this function does not
3433 * rely on the CPU's self-snoop feature, because it is intended for use
3434 * when moving pages into a different cache domain.
3437 pmap_invalidate_cache_pages(vm_page_t *pages, int count)
3439 vm_offset_t daddr, eva;
3443 useclflushopt = (cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0;
3444 if (count >= PMAP_CLFLUSH_THRESHOLD / PAGE_SIZE ||
3445 ((cpu_feature & CPUID_CLFSH) == 0 && !useclflushopt))
3446 pmap_invalidate_cache();
3449 atomic_thread_fence_seq_cst();
3450 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
3452 for (i = 0; i < count; i++) {
3453 daddr = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pages[i]));
3454 eva = daddr + PAGE_SIZE;
3455 for (; daddr < eva; daddr += cpu_clflush_line_size) {
3463 atomic_thread_fence_seq_cst();
3464 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
3470 pmap_flush_cache_range(vm_offset_t sva, vm_offset_t eva)
3473 pmap_invalidate_cache_range_check_align(sva, eva);
3475 if ((cpu_stdext_feature & CPUID_STDEXT_CLWB) == 0) {
3476 pmap_force_invalidate_cache_range(sva, eva);
3480 /* See comment in pmap_force_invalidate_cache_range(). */
3481 if (pmap_kextract(sva) == lapic_paddr)
3484 atomic_thread_fence_seq_cst();
3485 for (; sva < eva; sva += cpu_clflush_line_size)
3487 atomic_thread_fence_seq_cst();
3491 pmap_flush_cache_phys_range(vm_paddr_t spa, vm_paddr_t epa, vm_memattr_t mattr)
3495 int error, pte_bits;
3497 KASSERT((spa & PAGE_MASK) == 0,
3498 ("pmap_flush_cache_phys_range: spa not page-aligned"));
3499 KASSERT((epa & PAGE_MASK) == 0,
3500 ("pmap_flush_cache_phys_range: epa not page-aligned"));
3502 if (spa < dmaplimit) {
3503 pmap_flush_cache_range(PHYS_TO_DMAP(spa), PHYS_TO_DMAP(MIN(
3505 if (dmaplimit >= epa)
3510 pte_bits = pmap_cache_bits(kernel_pmap, mattr, 0) | X86_PG_RW |
3512 error = vmem_alloc(kernel_arena, PAGE_SIZE, M_BESTFIT | M_WAITOK,
3514 KASSERT(error == 0, ("vmem_alloc failed: %d", error));
3515 pte = vtopte(vaddr);
3516 for (; spa < epa; spa += PAGE_SIZE) {
3518 pte_store(pte, spa | pte_bits);
3520 /* XXXKIB atomic inside flush_cache_range are excessive */
3521 pmap_flush_cache_range(vaddr, vaddr + PAGE_SIZE);
3524 vmem_free(kernel_arena, vaddr, PAGE_SIZE);
3528 * Routine: pmap_extract
3530 * Extract the physical page address associated
3531 * with the given map/virtual_address pair.
3534 pmap_extract(pmap_t pmap, vm_offset_t va)
3538 pt_entry_t *pte, PG_V;
3542 PG_V = pmap_valid_bit(pmap);
3544 pdpe = pmap_pdpe(pmap, va);
3545 if (pdpe != NULL && (*pdpe & PG_V) != 0) {
3546 if ((*pdpe & PG_PS) != 0)
3547 pa = (*pdpe & PG_PS_FRAME) | (va & PDPMASK);
3549 pde = pmap_pdpe_to_pde(pdpe, va);
3550 if ((*pde & PG_V) != 0) {
3551 if ((*pde & PG_PS) != 0) {
3552 pa = (*pde & PG_PS_FRAME) |
3555 pte = pmap_pde_to_pte(pde, va);
3556 pa = (*pte & PG_FRAME) |
3567 * Routine: pmap_extract_and_hold
3569 * Atomically extract and hold the physical page
3570 * with the given pmap and virtual address pair
3571 * if that mapping permits the given protection.
3574 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
3576 pdp_entry_t pdpe, *pdpep;
3577 pd_entry_t pde, *pdep;
3578 pt_entry_t pte, PG_RW, PG_V;
3582 PG_RW = pmap_rw_bit(pmap);
3583 PG_V = pmap_valid_bit(pmap);
3586 pdpep = pmap_pdpe(pmap, va);
3587 if (pdpep == NULL || ((pdpe = *pdpep) & PG_V) == 0)
3589 if ((pdpe & PG_PS) != 0) {
3590 if ((pdpe & PG_RW) == 0 && (prot & VM_PROT_WRITE) != 0)
3592 m = PHYS_TO_VM_PAGE((pdpe & PG_PS_FRAME) | (va & PDPMASK));
3596 pdep = pmap_pdpe_to_pde(pdpep, va);
3597 if (pdep == NULL || ((pde = *pdep) & PG_V) == 0)
3599 if ((pde & PG_PS) != 0) {
3600 if ((pde & PG_RW) == 0 && (prot & VM_PROT_WRITE) != 0)
3602 m = PHYS_TO_VM_PAGE((pde & PG_PS_FRAME) | (va & PDRMASK));
3606 pte = *pmap_pde_to_pte(pdep, va);
3607 if ((pte & PG_V) == 0 ||
3608 ((pte & PG_RW) == 0 && (prot & VM_PROT_WRITE) != 0))
3610 m = PHYS_TO_VM_PAGE(pte & PG_FRAME);
3613 if (m != NULL && !vm_page_wire_mapped(m))
3621 pmap_kextract(vm_offset_t va)
3626 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS) {
3627 pa = DMAP_TO_PHYS(va);
3628 } else if (PMAP_ADDRESS_IN_LARGEMAP(va)) {
3629 pa = pmap_large_map_kextract(va);
3633 pa = (pde & PG_PS_FRAME) | (va & PDRMASK);
3636 * Beware of a concurrent promotion that changes the
3637 * PDE at this point! For example, vtopte() must not
3638 * be used to access the PTE because it would use the
3639 * new PDE. It is, however, safe to use the old PDE
3640 * because the page table page is preserved by the
3643 pa = *pmap_pde_to_pte(&pde, va);
3644 pa = (pa & PG_FRAME) | (va & PAGE_MASK);
3650 /***************************************************
3651 * Low level mapping routines.....
3652 ***************************************************/
3655 * Add a wired page to the kva.
3656 * Note: not SMP coherent.
3659 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
3664 pte_store(pte, pa | X86_PG_RW | X86_PG_V | pg_g | pg_nx);
3667 static __inline void
3668 pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode)
3674 cache_bits = pmap_cache_bits(kernel_pmap, mode, 0);
3675 pte_store(pte, pa | X86_PG_RW | X86_PG_V | pg_g | pg_nx | cache_bits);
3679 * Remove a page from the kernel pagetables.
3680 * Note: not SMP coherent.
3683 pmap_kremove(vm_offset_t va)
3692 * Used to map a range of physical addresses into kernel
3693 * virtual address space.
3695 * The value passed in '*virt' is a suggested virtual address for
3696 * the mapping. Architectures which can support a direct-mapped
3697 * physical to virtual region can return the appropriate address
3698 * within that region, leaving '*virt' unchanged. Other
3699 * architectures should map the pages starting at '*virt' and
3700 * update '*virt' with the first usable address after the mapped
3704 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
3706 return PHYS_TO_DMAP(start);
3710 * Add a list of wired pages to the kva
3711 * this routine is only used for temporary
3712 * kernel mappings that do not need to have
3713 * page modification or references recorded.
3714 * Note that old mappings are simply written
3715 * over. The page *must* be wired.
3716 * Note: SMP coherent. Uses a ranged shootdown IPI.
3719 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
3721 pt_entry_t *endpte, oldpte, pa, *pte;
3727 endpte = pte + count;
3728 while (pte < endpte) {
3730 cache_bits = pmap_cache_bits(kernel_pmap, m->md.pat_mode, 0);
3731 pa = VM_PAGE_TO_PHYS(m) | cache_bits;
3732 if ((*pte & (PG_FRAME | X86_PG_PTE_CACHE)) != pa) {
3734 pte_store(pte, pa | pg_g | pg_nx | X86_PG_RW | X86_PG_V);
3738 if (__predict_false((oldpte & X86_PG_V) != 0))
3739 pmap_invalidate_range(kernel_pmap, sva, sva + count *
3744 * This routine tears out page mappings from the
3745 * kernel -- it is meant only for temporary mappings.
3746 * Note: SMP coherent. Uses a ranged shootdown IPI.
3749 pmap_qremove(vm_offset_t sva, int count)
3754 while (count-- > 0) {
3755 KASSERT(va >= VM_MIN_KERNEL_ADDRESS, ("usermode va %lx", va));
3759 pmap_invalidate_range(kernel_pmap, sva, va);
3762 /***************************************************
3763 * Page table page management routines.....
3764 ***************************************************/
3766 * Schedule the specified unused page table page to be freed. Specifically,
3767 * add the page to the specified list of pages that will be released to the
3768 * physical memory manager after the TLB has been updated.
3770 static __inline void
3771 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
3772 boolean_t set_PG_ZERO)
3776 m->flags |= PG_ZERO;
3778 m->flags &= ~PG_ZERO;
3779 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
3783 * Inserts the specified page table page into the specified pmap's collection
3784 * of idle page table pages. Each of a pmap's page table pages is responsible
3785 * for mapping a distinct range of virtual addresses. The pmap's collection is
3786 * ordered by this virtual address range.
3788 * If "promoted" is false, then the page table page "mpte" must be zero filled.
3791 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte, bool promoted)
3794 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3795 mpte->valid = promoted ? VM_PAGE_BITS_ALL : 0;
3796 return (vm_radix_insert(&pmap->pm_root, mpte));
3800 * Removes the page table page mapping the specified virtual address from the
3801 * specified pmap's collection of idle page table pages, and returns it.
3802 * Otherwise, returns NULL if there is no page table page corresponding to the
3803 * specified virtual address.
3805 static __inline vm_page_t
3806 pmap_remove_pt_page(pmap_t pmap, vm_offset_t va)
3809 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3810 return (vm_radix_remove(&pmap->pm_root, pmap_pde_pindex(va)));
3814 * Decrements a page table page's reference count, which is used to record the
3815 * number of valid page table entries within the page. If the reference count
3816 * drops to zero, then the page table page is unmapped. Returns TRUE if the
3817 * page table page was unmapped and FALSE otherwise.
3819 static inline boolean_t
3820 pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
3824 if (m->ref_count == 0) {
3825 _pmap_unwire_ptp(pmap, va, m, free);
3832 _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
3838 vm_page_t pdpg, pdppg, pml4pg;
3840 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3843 * unmap the page table page
3845 if (m->pindex >= NUPDE + NUPDPE + NUPML4E) {
3847 MPASS(pmap_is_la57(pmap));
3848 pml5 = pmap_pml5e(pmap, va);
3850 if (pmap->pm_pmltopu != NULL && va <= VM_MAXUSER_ADDRESS) {
3851 pml5 = pmap_pml5e_u(pmap, va);
3854 } else if (m->pindex >= NUPDE + NUPDPE) {
3856 pml4 = pmap_pml4e(pmap, va);
3858 if (!pmap_is_la57(pmap) && pmap->pm_pmltopu != NULL &&
3859 va <= VM_MAXUSER_ADDRESS) {
3860 pml4 = pmap_pml4e_u(pmap, va);
3863 } else if (m->pindex >= NUPDE) {
3865 pdp = pmap_pdpe(pmap, va);
3869 pd = pmap_pde(pmap, va);
3872 pmap_resident_count_dec(pmap, 1);
3873 if (m->pindex < NUPDE) {
3874 /* We just released a PT, unhold the matching PD */
3875 pdpg = PHYS_TO_VM_PAGE(*pmap_pdpe(pmap, va) & PG_FRAME);
3876 pmap_unwire_ptp(pmap, va, pdpg, free);
3877 } else if (m->pindex < NUPDE + NUPDPE) {
3878 /* We just released a PD, unhold the matching PDP */
3879 pdppg = PHYS_TO_VM_PAGE(*pmap_pml4e(pmap, va) & PG_FRAME);
3880 pmap_unwire_ptp(pmap, va, pdppg, free);
3881 } else if (m->pindex < NUPDE + NUPDPE + NUPML4E && pmap_is_la57(pmap)) {
3882 /* We just released a PDP, unhold the matching PML4 */
3883 pml4pg = PHYS_TO_VM_PAGE(*pmap_pml5e(pmap, va) & PG_FRAME);
3884 pmap_unwire_ptp(pmap, va, pml4pg, free);
3888 * Put page on a list so that it is released after
3889 * *ALL* TLB shootdown is done
3891 pmap_add_delayed_free_list(m, free, TRUE);
3895 * After removing a page table entry, this routine is used to
3896 * conditionally free the page, and manage the reference count.
3899 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, pd_entry_t ptepde,
3900 struct spglist *free)
3904 if (va >= VM_MAXUSER_ADDRESS)
3906 KASSERT(ptepde != 0, ("pmap_unuse_pt: ptepde != 0"));
3907 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME);
3908 return (pmap_unwire_ptp(pmap, va, mpte, free));
3912 * Release a page table page reference after a failed attempt to create a
3916 pmap_abort_ptp(pmap_t pmap, vm_offset_t va, vm_page_t mpte)
3918 struct spglist free;
3921 if (pmap_unwire_ptp(pmap, va, mpte, &free)) {
3923 * Although "va" was never mapped, paging-structure caches
3924 * could nonetheless have entries that refer to the freed
3925 * page table pages. Invalidate those entries.
3927 pmap_invalidate_page(pmap, va);
3928 vm_page_free_pages_toq(&free, true);
3933 pmap_pinit0(pmap_t pmap)
3939 PMAP_LOCK_INIT(pmap);
3940 pmap->pm_pmltop = kernel_pmap->pm_pmltop;
3941 pmap->pm_pmltopu = NULL;
3942 pmap->pm_cr3 = kernel_pmap->pm_cr3;
3943 /* hack to keep pmap_pti_pcid_invalidate() alive */
3944 pmap->pm_ucr3 = PMAP_NO_CR3;
3945 pmap->pm_root.rt_root = 0;
3946 CPU_ZERO(&pmap->pm_active);
3947 TAILQ_INIT(&pmap->pm_pvchunk);
3948 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
3949 pmap->pm_flags = pmap_flags;
3951 pmap->pm_pcids[i].pm_pcid = PMAP_PCID_KERN + 1;
3952 pmap->pm_pcids[i].pm_gen = 1;
3954 pmap_activate_boot(pmap);
3959 p->p_md.md_flags |= P_MD_KPTI;
3962 pmap_thread_init_invl_gen(td);
3964 if ((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0) {
3965 pmap_pkru_ranges_zone = uma_zcreate("pkru ranges",
3966 sizeof(struct pmap_pkru_range), NULL, NULL, NULL, NULL,
3972 pmap_pinit_pml4(vm_page_t pml4pg)
3974 pml4_entry_t *pm_pml4;
3977 pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4pg));
3979 /* Wire in kernel global address entries. */
3980 for (i = 0; i < NKPML4E; i++) {
3981 pm_pml4[KPML4BASE + i] = (KPDPphys + ptoa(i)) | X86_PG_RW |
3984 for (i = 0; i < ndmpdpphys; i++) {
3985 pm_pml4[DMPML4I + i] = (DMPDPphys + ptoa(i)) | X86_PG_RW |
3989 /* install self-referential address mapping entry(s) */
3990 pm_pml4[PML4PML4I] = VM_PAGE_TO_PHYS(pml4pg) | X86_PG_V | X86_PG_RW |
3991 X86_PG_A | X86_PG_M;
3993 /* install large map entries if configured */
3994 for (i = 0; i < lm_ents; i++)
3995 pm_pml4[LMSPML4I + i] = kernel_pmap->pm_pmltop[LMSPML4I + i];
3999 pmap_pinit_pml5(vm_page_t pml5pg)
4001 pml5_entry_t *pm_pml5;
4003 pm_pml5 = (pml5_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml5pg));
4006 * Add pml5 entry at top of KVA pointing to existing pml4 table,
4007 * entering all existing kernel mappings into level 5 table.
4009 pm_pml5[pmap_pml5e_index(UPT_MAX_ADDRESS)] = KPML4phys | X86_PG_V |
4010 X86_PG_RW | X86_PG_A | X86_PG_M | pg_g |
4011 pmap_cache_bits(kernel_pmap, VM_MEMATTR_DEFAULT, FALSE);
4014 * Install self-referential address mapping entry.
4016 pm_pml5[PML5PML5I] = VM_PAGE_TO_PHYS(pml5pg) |
4017 X86_PG_RW | X86_PG_V | X86_PG_M | X86_PG_A |
4018 pmap_cache_bits(kernel_pmap, VM_MEMATTR_DEFAULT, FALSE);
4022 pmap_pinit_pml4_pti(vm_page_t pml4pgu)
4024 pml4_entry_t *pm_pml4u;
4027 pm_pml4u = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4pgu));
4028 for (i = 0; i < NPML4EPG; i++)
4029 pm_pml4u[i] = pti_pml4[i];
4033 pmap_pinit_pml5_pti(vm_page_t pml5pgu)
4035 pml5_entry_t *pm_pml5u;
4037 pm_pml5u = (pml5_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml5pgu));
4040 * Add pml5 entry at top of KVA pointing to existing pml4 pti
4041 * table, entering all kernel mappings needed for usermode
4042 * into level 5 table.
4044 pm_pml5u[pmap_pml5e_index(UPT_MAX_ADDRESS)] =
4045 pmap_kextract((vm_offset_t)pti_pml4) |
4046 X86_PG_V | X86_PG_RW | X86_PG_A | X86_PG_M | pg_g |
4047 pmap_cache_bits(kernel_pmap, VM_MEMATTR_DEFAULT, FALSE);
4051 * Initialize a preallocated and zeroed pmap structure,
4052 * such as one in a vmspace structure.
4055 pmap_pinit_type(pmap_t pmap, enum pmap_type pm_type, int flags)
4057 vm_page_t pmltop_pg, pmltop_pgu;
4058 vm_paddr_t pmltop_phys;
4062 * allocate the page directory page
4064 pmltop_pg = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
4065 VM_ALLOC_WIRED | VM_ALLOC_ZERO | VM_ALLOC_WAITOK);
4067 pmltop_phys = VM_PAGE_TO_PHYS(pmltop_pg);
4068 pmap->pm_pmltop = (pml5_entry_t *)PHYS_TO_DMAP(pmltop_phys);
4071 pmap->pm_pcids[i].pm_pcid = PMAP_PCID_NONE;
4072 pmap->pm_pcids[i].pm_gen = 0;
4074 pmap->pm_cr3 = PMAP_NO_CR3; /* initialize to an invalid value */
4075 pmap->pm_ucr3 = PMAP_NO_CR3;
4076 pmap->pm_pmltopu = NULL;
4078 pmap->pm_type = pm_type;
4079 if ((pmltop_pg->flags & PG_ZERO) == 0)
4080 pagezero(pmap->pm_pmltop);
4083 * Do not install the host kernel mappings in the nested page
4084 * tables. These mappings are meaningless in the guest physical
4086 * Install minimal kernel mappings in PTI case.
4088 if (pm_type == PT_X86) {
4089 pmap->pm_cr3 = pmltop_phys;
4090 if (pmap_is_la57(pmap))
4091 pmap_pinit_pml5(pmltop_pg);
4093 pmap_pinit_pml4(pmltop_pg);
4094 if ((curproc->p_md.md_flags & P_MD_KPTI) != 0) {
4095 pmltop_pgu = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
4096 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | VM_ALLOC_WAITOK);
4097 pmap->pm_pmltopu = (pml4_entry_t *)PHYS_TO_DMAP(
4098 VM_PAGE_TO_PHYS(pmltop_pgu));
4099 if (pmap_is_la57(pmap))
4100 pmap_pinit_pml5_pti(pmltop_pgu);
4102 pmap_pinit_pml4_pti(pmltop_pgu);
4103 pmap->pm_ucr3 = VM_PAGE_TO_PHYS(pmltop_pgu);
4105 if ((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0) {
4106 rangeset_init(&pmap->pm_pkru, pkru_dup_range,
4107 pkru_free_range, pmap, M_NOWAIT);
4111 pmap->pm_root.rt_root = 0;
4112 CPU_ZERO(&pmap->pm_active);
4113 TAILQ_INIT(&pmap->pm_pvchunk);
4114 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
4115 pmap->pm_flags = flags;
4116 pmap->pm_eptgen = 0;
4122 pmap_pinit(pmap_t pmap)
4125 return (pmap_pinit_type(pmap, PT_X86, pmap_flags));
4129 pmap_allocpte_free_unref(pmap_t pmap, vm_offset_t va, pt_entry_t *pte)
4132 struct spglist free;
4134 mpg = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
4135 if (mpg->ref_count != 0)
4138 _pmap_unwire_ptp(pmap, va, mpg, &free);
4139 pmap_invalidate_page(pmap, va);
4140 vm_page_free_pages_toq(&free, true);
4143 static pml4_entry_t *
4144 pmap_allocpte_getpml4(pmap_t pmap, struct rwlock **lockp, vm_offset_t va,
4147 vm_pindex_t pml5index;
4154 if (!pmap_is_la57(pmap))
4155 return (&pmap->pm_pmltop[pmap_pml4e_index(va)]);
4157 PG_V = pmap_valid_bit(pmap);
4158 pml5index = pmap_pml5e_index(va);
4159 pml5 = &pmap->pm_pmltop[pml5index];
4160 if ((*pml5 & PG_V) == 0) {
4161 if (_pmap_allocpte(pmap, pmap_pml5e_pindex(va), lockp, va) ==
4168 pml4 = (pml4_entry_t *)PHYS_TO_DMAP(*pml5 & PG_FRAME);
4169 pml4 = &pml4[pmap_pml4e_index(va)];
4170 if ((*pml4 & PG_V) == 0) {
4171 pml4pg = PHYS_TO_VM_PAGE(*pml5 & PG_FRAME);
4172 if (allocated && !addref)
4173 pml4pg->ref_count--;
4174 else if (!allocated && addref)
4175 pml4pg->ref_count++;
4180 static pdp_entry_t *
4181 pmap_allocpte_getpdp(pmap_t pmap, struct rwlock **lockp, vm_offset_t va,
4190 PG_V = pmap_valid_bit(pmap);
4192 pml4 = pmap_allocpte_getpml4(pmap, lockp, va, false);
4196 if ((*pml4 & PG_V) == 0) {
4197 /* Have to allocate a new pdp, recurse */
4198 if (_pmap_allocpte(pmap, pmap_pml4e_pindex(va), lockp, va) ==
4200 if (pmap_is_la57(pmap))
4201 pmap_allocpte_free_unref(pmap, va,
4202 pmap_pml5e(pmap, va));
4209 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
4210 pdp = &pdp[pmap_pdpe_index(va)];
4211 if ((*pdp & PG_V) == 0) {
4212 pdppg = PHYS_TO_VM_PAGE(*pml4 & PG_FRAME);
4213 if (allocated && !addref)
4215 else if (!allocated && addref)
4222 * This routine is called if the desired page table page does not exist.
4224 * If page table page allocation fails, this routine may sleep before
4225 * returning NULL. It sleeps only if a lock pointer was given.
4227 * Note: If a page allocation fails at page table level two, three, or four,
4228 * up to three pages may be held during the wait, only to be released
4229 * afterwards. This conservative approach is easily argued to avoid
4232 * The ptepindexes, i.e. page indices, of the page table pages encountered
4233 * while translating virtual address va are defined as follows:
4234 * - for the page table page (last level),
4235 * ptepindex = pmap_pde_pindex(va) = va >> PDRSHIFT,
4236 * in other words, it is just the index of the PDE that maps the page
4238 * - for the page directory page,
4239 * ptepindex = NUPDE (number of userland PD entries) +
4240 * (pmap_pde_index(va) >> NPDEPGSHIFT)
4241 * i.e. index of PDPE is put after the last index of PDE,
4242 * - for the page directory pointer page,
4243 * ptepindex = NUPDE + NUPDPE + (pmap_pde_index(va) >> (NPDEPGSHIFT +
4245 * i.e. index of pml4e is put after the last index of PDPE,
4246 * - for the PML4 page (if LA57 mode is enabled),
4247 * ptepindex = NUPDE + NUPDPE + NUPML4E + (pmap_pde_index(va) >>
4248 * (NPDEPGSHIFT + NPML4EPGSHIFT + NPML5EPGSHIFT),
4249 * i.e. index of pml5e is put after the last index of PML4E.
4251 * Define an order on the paging entries, where all entries of the
4252 * same height are put together, then heights are put from deepest to
4253 * root. Then ptexpindex is the sequential number of the
4254 * corresponding paging entry in this order.
4256 * The values of NUPDE, NUPDPE, and NUPML4E are determined by the size of
4257 * LA57 paging structures even in LA48 paging mode. Moreover, the
4258 * ptepindexes are calculated as if the paging structures were 5-level
4259 * regardless of the actual mode of operation.
4261 * The root page at PML4/PML5 does not participate in this indexing scheme,
4262 * since it is statically allocated by pmap_pinit() and not by _pmap_allocpte().
4265 _pmap_allocpte(pmap_t pmap, vm_pindex_t ptepindex, struct rwlock **lockp,
4266 vm_offset_t va __unused)
4268 vm_pindex_t pml5index, pml4index;
4269 pml5_entry_t *pml5, *pml5u;
4270 pml4_entry_t *pml4, *pml4u;
4274 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
4276 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4278 PG_A = pmap_accessed_bit(pmap);
4279 PG_M = pmap_modified_bit(pmap);
4280 PG_V = pmap_valid_bit(pmap);
4281 PG_RW = pmap_rw_bit(pmap);
4284 * Allocate a page table page.
4286 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
4287 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
4288 if (lockp != NULL) {
4289 RELEASE_PV_LIST_LOCK(lockp);
4291 PMAP_ASSERT_NOT_IN_DI();
4297 * Indicate the need to retry. While waiting, the page table
4298 * page may have been allocated.
4302 if ((m->flags & PG_ZERO) == 0)
4306 * Map the pagetable page into the process address space, if
4307 * it isn't already there.
4309 if (ptepindex >= NUPDE + NUPDPE + NUPML4E) {
4310 MPASS(pmap_is_la57(pmap));
4312 pml5index = pmap_pml5e_index(va);
4313 pml5 = &pmap->pm_pmltop[pml5index];
4314 KASSERT((*pml5 & PG_V) == 0,
4315 ("pmap %p va %#lx pml5 %#lx", pmap, va, *pml5));
4316 *pml5 = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
4318 if (pmap->pm_pmltopu != NULL && pml5index < NUPML5E) {
4319 if (pmap->pm_ucr3 != PMAP_NO_CR3)
4322 pml5u = &pmap->pm_pmltopu[pml5index];
4323 *pml5u = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V |
4326 } else if (ptepindex >= NUPDE + NUPDPE) {
4327 pml4index = pmap_pml4e_index(va);
4328 /* Wire up a new PDPE page */
4329 pml4 = pmap_allocpte_getpml4(pmap, lockp, va, true);
4331 vm_page_unwire_noq(m);
4332 vm_page_free_zero(m);
4335 KASSERT((*pml4 & PG_V) == 0,
4336 ("pmap %p va %#lx pml4 %#lx", pmap, va, *pml4));
4337 *pml4 = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
4339 if (!pmap_is_la57(pmap) && pmap->pm_pmltopu != NULL &&
4340 pml4index < NUPML4E) {
4342 * PTI: Make all user-space mappings in the
4343 * kernel-mode page table no-execute so that
4344 * we detect any programming errors that leave
4345 * the kernel-mode page table active on return
4348 if (pmap->pm_ucr3 != PMAP_NO_CR3)
4351 pml4u = &pmap->pm_pmltopu[pml4index];
4352 *pml4u = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V |
4355 } else if (ptepindex >= NUPDE) {
4356 /* Wire up a new PDE page */
4357 pdp = pmap_allocpte_getpdp(pmap, lockp, va, true);
4359 vm_page_unwire_noq(m);
4360 vm_page_free_zero(m);
4363 KASSERT((*pdp & PG_V) == 0,
4364 ("pmap %p va %#lx pdp %#lx", pmap, va, *pdp));
4365 *pdp = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
4367 /* Wire up a new PTE page */
4368 pdp = pmap_allocpte_getpdp(pmap, lockp, va, false);
4370 vm_page_unwire_noq(m);
4371 vm_page_free_zero(m);
4374 if ((*pdp & PG_V) == 0) {
4375 /* Have to allocate a new pd, recurse */
4376 if (_pmap_allocpte(pmap, pmap_pdpe_pindex(va),
4377 lockp, va) == NULL) {
4378 pmap_allocpte_free_unref(pmap, va,
4379 pmap_pml4e(pmap, va));
4380 vm_page_unwire_noq(m);
4381 vm_page_free_zero(m);
4385 /* Add reference to the pd page */
4386 pdpg = PHYS_TO_VM_PAGE(*pdp & PG_FRAME);
4389 pd = (pd_entry_t *)PHYS_TO_DMAP(*pdp & PG_FRAME);
4391 /* Now we know where the page directory page is */
4392 pd = &pd[pmap_pde_index(va)];
4393 KASSERT((*pd & PG_V) == 0,
4394 ("pmap %p va %#lx pd %#lx", pmap, va, *pd));
4395 *pd = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
4398 pmap_resident_count_inc(pmap, 1);
4404 pmap_alloc_pde(pmap_t pmap, vm_offset_t va, vm_page_t *pdpgp,
4405 struct rwlock **lockp)
4407 pdp_entry_t *pdpe, PG_V;
4410 vm_pindex_t pdpindex;
4412 PG_V = pmap_valid_bit(pmap);
4415 pdpe = pmap_pdpe(pmap, va);
4416 if (pdpe != NULL && (*pdpe & PG_V) != 0) {
4417 pde = pmap_pdpe_to_pde(pdpe, va);
4418 if (va < VM_MAXUSER_ADDRESS) {
4419 /* Add a reference to the pd page. */
4420 pdpg = PHYS_TO_VM_PAGE(*pdpe & PG_FRAME);
4424 } else if (va < VM_MAXUSER_ADDRESS) {
4425 /* Allocate a pd page. */
4426 pdpindex = pmap_pde_pindex(va) >> NPDPEPGSHIFT;
4427 pdpg = _pmap_allocpte(pmap, NUPDE + pdpindex, lockp, va);
4434 pde = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pdpg));
4435 pde = &pde[pmap_pde_index(va)];
4437 panic("pmap_alloc_pde: missing page table page for va %#lx",
4444 pmap_allocpte(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
4446 vm_pindex_t ptepindex;
4447 pd_entry_t *pd, PG_V;
4450 PG_V = pmap_valid_bit(pmap);
4453 * Calculate pagetable page index
4455 ptepindex = pmap_pde_pindex(va);
4458 * Get the page directory entry
4460 pd = pmap_pde(pmap, va);
4463 * This supports switching from a 2MB page to a
4466 if (pd != NULL && (*pd & (PG_PS | PG_V)) == (PG_PS | PG_V)) {
4467 if (!pmap_demote_pde_locked(pmap, pd, va, lockp)) {
4469 * Invalidation of the 2MB page mapping may have caused
4470 * the deallocation of the underlying PD page.
4477 * If the page table page is mapped, we just increment the
4478 * hold count, and activate it.
4480 if (pd != NULL && (*pd & PG_V) != 0) {
4481 m = PHYS_TO_VM_PAGE(*pd & PG_FRAME);
4485 * Here if the pte page isn't mapped, or if it has been
4488 m = _pmap_allocpte(pmap, ptepindex, lockp, va);
4489 if (m == NULL && lockp != NULL)
4495 /***************************************************
4496 * Pmap allocation/deallocation routines.
4497 ***************************************************/
4500 * Release any resources held by the given physical map.
4501 * Called when a pmap initialized by pmap_pinit is being released.
4502 * Should only be called if the map contains no valid mappings.
4505 pmap_release(pmap_t pmap)
4510 KASSERT(pmap->pm_stats.resident_count == 0,
4511 ("pmap_release: pmap %p resident count %ld != 0",
4512 pmap, pmap->pm_stats.resident_count));
4513 KASSERT(vm_radix_is_empty(&pmap->pm_root),
4514 ("pmap_release: pmap %p has reserved page table page(s)",
4516 KASSERT(CPU_EMPTY(&pmap->pm_active),
4517 ("releasing active pmap %p", pmap));
4519 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pmap->pm_pmltop));
4521 if (pmap_is_la57(pmap)) {
4522 pmap->pm_pmltop[pmap_pml5e_index(UPT_MAX_ADDRESS)] = 0;
4523 pmap->pm_pmltop[PML5PML5I] = 0;
4525 for (i = 0; i < NKPML4E; i++) /* KVA */
4526 pmap->pm_pmltop[KPML4BASE + i] = 0;
4527 for (i = 0; i < ndmpdpphys; i++)/* Direct Map */
4528 pmap->pm_pmltop[DMPML4I + i] = 0;
4529 pmap->pm_pmltop[PML4PML4I] = 0; /* Recursive Mapping */
4530 for (i = 0; i < lm_ents; i++) /* Large Map */
4531 pmap->pm_pmltop[LMSPML4I + i] = 0;
4534 vm_page_unwire_noq(m);
4535 vm_page_free_zero(m);
4537 if (pmap->pm_pmltopu != NULL) {
4538 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pmap->
4540 vm_page_unwire_noq(m);
4543 if (pmap->pm_type == PT_X86 &&
4544 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0)
4545 rangeset_fini(&pmap->pm_pkru);
4549 kvm_size(SYSCTL_HANDLER_ARGS)
4551 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS;
4553 return sysctl_handle_long(oidp, &ksize, 0, req);
4555 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG | CTLFLAG_RD | CTLFLAG_MPSAFE,
4556 0, 0, kvm_size, "LU",
4560 kvm_free(SYSCTL_HANDLER_ARGS)
4562 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
4564 return sysctl_handle_long(oidp, &kfree, 0, req);
4566 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG | CTLFLAG_RD | CTLFLAG_MPSAFE,
4567 0, 0, kvm_free, "LU",
4568 "Amount of KVM free");
4571 * Allocate physical memory for the vm_page array and map it into KVA,
4572 * attempting to back the vm_pages with domain-local memory.
4575 pmap_page_array_startup(long pages)
4578 pd_entry_t *pde, newpdir;
4579 vm_offset_t va, start, end;
4584 vm_page_array_size = pages;
4586 start = VM_MIN_KERNEL_ADDRESS;
4587 end = start + pages * sizeof(struct vm_page);
4588 for (va = start; va < end; va += NBPDR) {
4589 pfn = first_page + (va - start) / sizeof(struct vm_page);
4590 domain = _vm_phys_domain(ptoa(pfn));
4591 pdpe = pmap_pdpe(kernel_pmap, va);
4592 if ((*pdpe & X86_PG_V) == 0) {
4593 pa = vm_phys_early_alloc(domain, PAGE_SIZE);
4595 pagezero((void *)PHYS_TO_DMAP(pa));
4596 *pdpe = (pdp_entry_t)(pa | X86_PG_V | X86_PG_RW |
4597 X86_PG_A | X86_PG_M);
4599 pde = pmap_pdpe_to_pde(pdpe, va);
4600 if ((*pde & X86_PG_V) != 0)
4601 panic("Unexpected pde");
4602 pa = vm_phys_early_alloc(domain, NBPDR);
4603 for (i = 0; i < NPDEPG; i++)
4604 dump_add_page(pa + i * PAGE_SIZE);
4605 newpdir = (pd_entry_t)(pa | X86_PG_V | X86_PG_RW | X86_PG_A |
4606 X86_PG_M | PG_PS | pg_g | pg_nx);
4607 pde_store(pde, newpdir);
4609 vm_page_array = (vm_page_t)start;
4613 * grow the number of kernel page table entries, if needed
4616 pmap_growkernel(vm_offset_t addr)
4620 pd_entry_t *pde, newpdir;
4623 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
4626 * Return if "addr" is within the range of kernel page table pages
4627 * that were preallocated during pmap bootstrap. Moreover, leave
4628 * "kernel_vm_end" and the kernel page table as they were.
4630 * The correctness of this action is based on the following
4631 * argument: vm_map_insert() allocates contiguous ranges of the
4632 * kernel virtual address space. It calls this function if a range
4633 * ends after "kernel_vm_end". If the kernel is mapped between
4634 * "kernel_vm_end" and "addr", then the range cannot begin at
4635 * "kernel_vm_end". In fact, its beginning address cannot be less
4636 * than the kernel. Thus, there is no immediate need to allocate
4637 * any new kernel page table pages between "kernel_vm_end" and
4640 if (KERNBASE < addr && addr <= KERNBASE + nkpt * NBPDR)
4643 addr = roundup2(addr, NBPDR);
4644 if (addr - 1 >= vm_map_max(kernel_map))
4645 addr = vm_map_max(kernel_map);
4646 while (kernel_vm_end < addr) {
4647 pdpe = pmap_pdpe(kernel_pmap, kernel_vm_end);
4648 if ((*pdpe & X86_PG_V) == 0) {
4649 /* We need a new PDP entry */
4650 nkpg = vm_page_alloc(NULL, kernel_vm_end >> PDPSHIFT,
4651 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ |
4652 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
4654 panic("pmap_growkernel: no memory to grow kernel");
4655 if ((nkpg->flags & PG_ZERO) == 0)
4656 pmap_zero_page(nkpg);
4657 paddr = VM_PAGE_TO_PHYS(nkpg);
4658 *pdpe = (pdp_entry_t)(paddr | X86_PG_V | X86_PG_RW |
4659 X86_PG_A | X86_PG_M);
4660 continue; /* try again */
4662 pde = pmap_pdpe_to_pde(pdpe, kernel_vm_end);
4663 if ((*pde & X86_PG_V) != 0) {
4664 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
4665 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
4666 kernel_vm_end = vm_map_max(kernel_map);
4672 nkpg = vm_page_alloc(NULL, pmap_pde_pindex(kernel_vm_end),
4673 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
4676 panic("pmap_growkernel: no memory to grow kernel");
4677 if ((nkpg->flags & PG_ZERO) == 0)
4678 pmap_zero_page(nkpg);
4679 paddr = VM_PAGE_TO_PHYS(nkpg);
4680 newpdir = paddr | X86_PG_V | X86_PG_RW | X86_PG_A | X86_PG_M;
4681 pde_store(pde, newpdir);
4683 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
4684 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
4685 kernel_vm_end = vm_map_max(kernel_map);
4691 /***************************************************
4692 * page management routines.
4693 ***************************************************/
4695 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
4696 CTASSERT(_NPCM == 3);
4697 CTASSERT(_NPCPV == 168);
4699 static __inline struct pv_chunk *
4700 pv_to_chunk(pv_entry_t pv)
4703 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
4706 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
4708 #define PC_FREE0 0xfffffffffffffffful
4709 #define PC_FREE1 0xfffffffffffffffful
4710 #define PC_FREE2 0x000000fffffffffful
4712 static const uint64_t pc_freemask[_NPCM] = { PC_FREE0, PC_FREE1, PC_FREE2 };
4715 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
4717 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
4718 "Current number of pv entry chunks");
4719 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
4720 "Current number of pv entry chunks allocated");
4721 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
4722 "Current number of pv entry chunks frees");
4723 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
4724 "Number of times tried to get a chunk page but failed.");
4726 static long pv_entry_frees, pv_entry_allocs, pv_entry_count;
4727 static int pv_entry_spare;
4729 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
4730 "Current number of pv entry frees");
4731 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
4732 "Current number of pv entry allocs");
4733 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
4734 "Current number of pv entries");
4735 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
4736 "Current number of spare pv entries");
4740 reclaim_pv_chunk_leave_pmap(pmap_t pmap, pmap_t locked_pmap, bool start_di)
4745 pmap_invalidate_all(pmap);
4746 if (pmap != locked_pmap)
4749 pmap_delayed_invl_finish();
4753 * We are in a serious low memory condition. Resort to
4754 * drastic measures to free some pages so we can allocate
4755 * another pv entry chunk.
4757 * Returns NULL if PV entries were reclaimed from the specified pmap.
4759 * We do not, however, unmap 2mpages because subsequent accesses will
4760 * allocate per-page pv entries until repromotion occurs, thereby
4761 * exacerbating the shortage of free pv entries.
4764 reclaim_pv_chunk_domain(pmap_t locked_pmap, struct rwlock **lockp, int domain)
4766 struct pv_chunks_list *pvc;
4767 struct pv_chunk *pc, *pc_marker, *pc_marker_end;
4768 struct pv_chunk_header pc_marker_b, pc_marker_end_b;
4769 struct md_page *pvh;
4771 pmap_t next_pmap, pmap;
4772 pt_entry_t *pte, tpte;
4773 pt_entry_t PG_G, PG_A, PG_M, PG_RW;
4777 struct spglist free;
4779 int bit, field, freed;
4780 bool start_di, restart;
4782 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
4783 KASSERT(lockp != NULL, ("reclaim_pv_chunk: lockp is NULL"));
4786 PG_G = PG_A = PG_M = PG_RW = 0;
4788 bzero(&pc_marker_b, sizeof(pc_marker_b));
4789 bzero(&pc_marker_end_b, sizeof(pc_marker_end_b));
4790 pc_marker = (struct pv_chunk *)&pc_marker_b;
4791 pc_marker_end = (struct pv_chunk *)&pc_marker_end_b;
4794 * A delayed invalidation block should already be active if
4795 * pmap_advise() or pmap_remove() called this function by way
4796 * of pmap_demote_pde_locked().
4798 start_di = pmap_not_in_di();
4800 pvc = &pv_chunks[domain];
4801 mtx_lock(&pvc->pvc_lock);
4802 pvc->active_reclaims++;
4803 TAILQ_INSERT_HEAD(&pvc->pvc_list, pc_marker, pc_lru);
4804 TAILQ_INSERT_TAIL(&pvc->pvc_list, pc_marker_end, pc_lru);
4805 while ((pc = TAILQ_NEXT(pc_marker, pc_lru)) != pc_marker_end &&
4806 SLIST_EMPTY(&free)) {
4807 next_pmap = pc->pc_pmap;
4808 if (next_pmap == NULL) {
4810 * The next chunk is a marker. However, it is
4811 * not our marker, so active_reclaims must be
4812 * > 1. Consequently, the next_chunk code
4813 * will not rotate the pv_chunks list.
4817 mtx_unlock(&pvc->pvc_lock);
4820 * A pv_chunk can only be removed from the pc_lru list
4821 * when both pc_chunks_mutex is owned and the
4822 * corresponding pmap is locked.
4824 if (pmap != next_pmap) {
4826 reclaim_pv_chunk_leave_pmap(pmap, locked_pmap,
4829 /* Avoid deadlock and lock recursion. */
4830 if (pmap > locked_pmap) {
4831 RELEASE_PV_LIST_LOCK(lockp);
4834 pmap_delayed_invl_start();
4835 mtx_lock(&pvc->pvc_lock);
4837 } else if (pmap != locked_pmap) {
4838 if (PMAP_TRYLOCK(pmap)) {
4840 pmap_delayed_invl_start();
4841 mtx_lock(&pvc->pvc_lock);
4844 pmap = NULL; /* pmap is not locked */
4845 mtx_lock(&pvc->pvc_lock);
4846 pc = TAILQ_NEXT(pc_marker, pc_lru);
4848 pc->pc_pmap != next_pmap)
4852 } else if (start_di)
4853 pmap_delayed_invl_start();
4854 PG_G = pmap_global_bit(pmap);
4855 PG_A = pmap_accessed_bit(pmap);
4856 PG_M = pmap_modified_bit(pmap);
4857 PG_RW = pmap_rw_bit(pmap);
4863 * Destroy every non-wired, 4 KB page mapping in the chunk.
4866 for (field = 0; field < _NPCM; field++) {
4867 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
4868 inuse != 0; inuse &= ~(1UL << bit)) {
4870 pv = &pc->pc_pventry[field * 64 + bit];
4872 pde = pmap_pde(pmap, va);
4873 if ((*pde & PG_PS) != 0)
4875 pte = pmap_pde_to_pte(pde, va);
4876 if ((*pte & PG_W) != 0)
4878 tpte = pte_load_clear(pte);
4879 if ((tpte & PG_G) != 0)
4880 pmap_invalidate_page(pmap, va);
4881 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
4882 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
4884 if ((tpte & PG_A) != 0)
4885 vm_page_aflag_set(m, PGA_REFERENCED);
4886 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
4887 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4889 if (TAILQ_EMPTY(&m->md.pv_list) &&
4890 (m->flags & PG_FICTITIOUS) == 0) {
4891 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4892 if (TAILQ_EMPTY(&pvh->pv_list)) {
4893 vm_page_aflag_clear(m,
4897 pmap_delayed_invl_page(m);
4898 pc->pc_map[field] |= 1UL << bit;
4899 pmap_unuse_pt(pmap, va, *pde, &free);
4904 mtx_lock(&pvc->pvc_lock);
4907 /* Every freed mapping is for a 4 KB page. */
4908 pmap_resident_count_dec(pmap, freed);
4909 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
4910 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
4911 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
4912 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4913 if (pc->pc_map[0] == PC_FREE0 && pc->pc_map[1] == PC_FREE1 &&
4914 pc->pc_map[2] == PC_FREE2) {
4915 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
4916 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
4917 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
4918 /* Entire chunk is free; return it. */
4919 m_pc = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
4920 dump_drop_page(m_pc->phys_addr);
4921 mtx_lock(&pvc->pvc_lock);
4922 TAILQ_REMOVE(&pvc->pvc_list, pc, pc_lru);
4925 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
4926 mtx_lock(&pvc->pvc_lock);
4927 /* One freed pv entry in locked_pmap is sufficient. */
4928 if (pmap == locked_pmap)
4931 TAILQ_REMOVE(&pvc->pvc_list, pc_marker, pc_lru);
4932 TAILQ_INSERT_AFTER(&pvc->pvc_list, pc, pc_marker, pc_lru);
4933 if (pvc->active_reclaims == 1 && pmap != NULL) {
4935 * Rotate the pv chunks list so that we do not
4936 * scan the same pv chunks that could not be
4937 * freed (because they contained a wired
4938 * and/or superpage mapping) on every
4939 * invocation of reclaim_pv_chunk().
4941 while ((pc = TAILQ_FIRST(&pvc->pvc_list)) != pc_marker) {
4942 MPASS(pc->pc_pmap != NULL);
4943 TAILQ_REMOVE(&pvc->pvc_list, pc, pc_lru);
4944 TAILQ_INSERT_TAIL(&pvc->pvc_list, pc, pc_lru);
4948 TAILQ_REMOVE(&pvc->pvc_list, pc_marker, pc_lru);
4949 TAILQ_REMOVE(&pvc->pvc_list, pc_marker_end, pc_lru);
4950 pvc->active_reclaims--;
4951 mtx_unlock(&pvc->pvc_lock);
4952 reclaim_pv_chunk_leave_pmap(pmap, locked_pmap, start_di);
4953 if (m_pc == NULL && !SLIST_EMPTY(&free)) {
4954 m_pc = SLIST_FIRST(&free);
4955 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
4956 /* Recycle a freed page table page. */
4957 m_pc->ref_count = 1;
4959 vm_page_free_pages_toq(&free, true);
4964 reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp)
4969 domain = PCPU_GET(domain);
4970 for (i = 0; i < vm_ndomains; i++) {
4971 m = reclaim_pv_chunk_domain(locked_pmap, lockp, domain);
4974 domain = (domain + 1) % vm_ndomains;
4981 * free the pv_entry back to the free list
4984 free_pv_entry(pmap_t pmap, pv_entry_t pv)
4986 struct pv_chunk *pc;
4987 int idx, field, bit;
4989 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4990 PV_STAT(atomic_add_long(&pv_entry_frees, 1));
4991 PV_STAT(atomic_add_int(&pv_entry_spare, 1));
4992 PV_STAT(atomic_subtract_long(&pv_entry_count, 1));
4993 pc = pv_to_chunk(pv);
4994 idx = pv - &pc->pc_pventry[0];
4997 pc->pc_map[field] |= 1ul << bit;
4998 if (pc->pc_map[0] != PC_FREE0 || pc->pc_map[1] != PC_FREE1 ||
4999 pc->pc_map[2] != PC_FREE2) {
5000 /* 98% of the time, pc is already at the head of the list. */
5001 if (__predict_false(pc != TAILQ_FIRST(&pmap->pm_pvchunk))) {
5002 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
5003 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
5007 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
5012 free_pv_chunk_dequeued(struct pv_chunk *pc)
5016 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
5017 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
5018 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
5019 /* entire chunk is free, return it */
5020 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
5021 dump_drop_page(m->phys_addr);
5022 vm_page_unwire_noq(m);
5027 free_pv_chunk(struct pv_chunk *pc)
5029 struct pv_chunks_list *pvc;
5031 pvc = &pv_chunks[pc_to_domain(pc)];
5032 mtx_lock(&pvc->pvc_lock);
5033 TAILQ_REMOVE(&pvc->pvc_list, pc, pc_lru);
5034 mtx_unlock(&pvc->pvc_lock);
5035 free_pv_chunk_dequeued(pc);
5039 free_pv_chunk_batch(struct pv_chunklist *batch)
5041 struct pv_chunks_list *pvc;
5042 struct pv_chunk *pc, *npc;
5045 for (i = 0; i < vm_ndomains; i++) {
5046 if (TAILQ_EMPTY(&batch[i]))
5048 pvc = &pv_chunks[i];
5049 mtx_lock(&pvc->pvc_lock);
5050 TAILQ_FOREACH(pc, &batch[i], pc_list) {
5051 TAILQ_REMOVE(&pvc->pvc_list, pc, pc_lru);
5053 mtx_unlock(&pvc->pvc_lock);
5056 for (i = 0; i < vm_ndomains; i++) {
5057 TAILQ_FOREACH_SAFE(pc, &batch[i], pc_list, npc) {
5058 free_pv_chunk_dequeued(pc);
5064 * Returns a new PV entry, allocating a new PV chunk from the system when
5065 * needed. If this PV chunk allocation fails and a PV list lock pointer was
5066 * given, a PV chunk is reclaimed from an arbitrary pmap. Otherwise, NULL is
5069 * The given PV list lock may be released.
5072 get_pv_entry(pmap_t pmap, struct rwlock **lockp)
5074 struct pv_chunks_list *pvc;
5077 struct pv_chunk *pc;
5080 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5081 PV_STAT(atomic_add_long(&pv_entry_allocs, 1));
5083 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
5085 for (field = 0; field < _NPCM; field++) {
5086 if (pc->pc_map[field]) {
5087 bit = bsfq(pc->pc_map[field]);
5091 if (field < _NPCM) {
5092 pv = &pc->pc_pventry[field * 64 + bit];
5093 pc->pc_map[field] &= ~(1ul << bit);
5094 /* If this was the last item, move it to tail */
5095 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 &&
5096 pc->pc_map[2] == 0) {
5097 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
5098 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc,
5101 PV_STAT(atomic_add_long(&pv_entry_count, 1));
5102 PV_STAT(atomic_subtract_int(&pv_entry_spare, 1));
5106 /* No free items, allocate another chunk */
5107 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
5110 if (lockp == NULL) {
5111 PV_STAT(pc_chunk_tryfail++);
5114 m = reclaim_pv_chunk(pmap, lockp);
5118 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
5119 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
5120 dump_add_page(m->phys_addr);
5121 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
5123 pc->pc_map[0] = PC_FREE0 & ~1ul; /* preallocated bit 0 */
5124 pc->pc_map[1] = PC_FREE1;
5125 pc->pc_map[2] = PC_FREE2;
5126 pvc = &pv_chunks[_vm_phys_domain(m->phys_addr)];
5127 mtx_lock(&pvc->pvc_lock);
5128 TAILQ_INSERT_TAIL(&pvc->pvc_list, pc, pc_lru);
5129 mtx_unlock(&pvc->pvc_lock);
5130 pv = &pc->pc_pventry[0];
5131 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
5132 PV_STAT(atomic_add_long(&pv_entry_count, 1));
5133 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV - 1));
5138 * Returns the number of one bits within the given PV chunk map.
5140 * The erratas for Intel processors state that "POPCNT Instruction May
5141 * Take Longer to Execute Than Expected". It is believed that the
5142 * issue is the spurious dependency on the destination register.
5143 * Provide a hint to the register rename logic that the destination
5144 * value is overwritten, by clearing it, as suggested in the
5145 * optimization manual. It should be cheap for unaffected processors
5148 * Reference numbers for erratas are
5149 * 4th Gen Core: HSD146
5150 * 5th Gen Core: BDM85
5151 * 6th Gen Core: SKL029
5154 popcnt_pc_map_pq(uint64_t *map)
5158 __asm __volatile("xorl %k0,%k0;popcntq %2,%0;"
5159 "xorl %k1,%k1;popcntq %3,%1;addl %k1,%k0;"
5160 "xorl %k1,%k1;popcntq %4,%1;addl %k1,%k0"
5161 : "=&r" (result), "=&r" (tmp)
5162 : "m" (map[0]), "m" (map[1]), "m" (map[2]));
5167 * Ensure that the number of spare PV entries in the specified pmap meets or
5168 * exceeds the given count, "needed".
5170 * The given PV list lock may be released.
5173 reserve_pv_entries(pmap_t pmap, int needed, struct rwlock **lockp)
5175 struct pv_chunks_list *pvc;
5176 struct pch new_tail[PMAP_MEMDOM];
5177 struct pv_chunk *pc;
5182 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5183 KASSERT(lockp != NULL, ("reserve_pv_entries: lockp is NULL"));
5186 * Newly allocated PV chunks must be stored in a private list until
5187 * the required number of PV chunks have been allocated. Otherwise,
5188 * reclaim_pv_chunk() could recycle one of these chunks. In
5189 * contrast, these chunks must be added to the pmap upon allocation.
5191 for (i = 0; i < PMAP_MEMDOM; i++)
5192 TAILQ_INIT(&new_tail[i]);
5195 TAILQ_FOREACH(pc, &pmap->pm_pvchunk, pc_list) {
5197 if ((cpu_feature2 & CPUID2_POPCNT) == 0)
5198 bit_count((bitstr_t *)pc->pc_map, 0,
5199 sizeof(pc->pc_map) * NBBY, &free);
5202 free = popcnt_pc_map_pq(pc->pc_map);
5206 if (avail >= needed)
5209 for (reclaimed = false; avail < needed; avail += _NPCPV) {
5210 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
5213 m = reclaim_pv_chunk(pmap, lockp);
5218 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
5219 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
5220 dump_add_page(m->phys_addr);
5221 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
5223 pc->pc_map[0] = PC_FREE0;
5224 pc->pc_map[1] = PC_FREE1;
5225 pc->pc_map[2] = PC_FREE2;
5226 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
5227 TAILQ_INSERT_TAIL(&new_tail[pc_to_domain(pc)], pc, pc_lru);
5228 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV));
5231 * The reclaim might have freed a chunk from the current pmap.
5232 * If that chunk contained available entries, we need to
5233 * re-count the number of available entries.
5238 for (i = 0; i < vm_ndomains; i++) {
5239 if (TAILQ_EMPTY(&new_tail[i]))
5241 pvc = &pv_chunks[i];
5242 mtx_lock(&pvc->pvc_lock);
5243 TAILQ_CONCAT(&pvc->pvc_list, &new_tail[i], pc_lru);
5244 mtx_unlock(&pvc->pvc_lock);
5249 * First find and then remove the pv entry for the specified pmap and virtual
5250 * address from the specified pv list. Returns the pv entry if found and NULL
5251 * otherwise. This operation can be performed on pv lists for either 4KB or
5252 * 2MB page mappings.
5254 static __inline pv_entry_t
5255 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
5259 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5260 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
5261 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
5270 * After demotion from a 2MB page mapping to 512 4KB page mappings,
5271 * destroy the pv entry for the 2MB page mapping and reinstantiate the pv
5272 * entries for each of the 4KB page mappings.
5275 pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
5276 struct rwlock **lockp)
5278 struct md_page *pvh;
5279 struct pv_chunk *pc;
5281 vm_offset_t va_last;
5285 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5286 KASSERT((pa & PDRMASK) == 0,
5287 ("pmap_pv_demote_pde: pa is not 2mpage aligned"));
5288 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
5291 * Transfer the 2mpage's pv entry for this mapping to the first
5292 * page's pv list. Once this transfer begins, the pv list lock
5293 * must not be released until the last pv entry is reinstantiated.
5295 pvh = pa_to_pvh(pa);
5296 va = trunc_2mpage(va);
5297 pv = pmap_pvh_remove(pvh, pmap, va);
5298 KASSERT(pv != NULL, ("pmap_pv_demote_pde: pv not found"));
5299 m = PHYS_TO_VM_PAGE(pa);
5300 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
5302 /* Instantiate the remaining NPTEPG - 1 pv entries. */
5303 PV_STAT(atomic_add_long(&pv_entry_allocs, NPTEPG - 1));
5304 va_last = va + NBPDR - PAGE_SIZE;
5306 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
5307 KASSERT(pc->pc_map[0] != 0 || pc->pc_map[1] != 0 ||
5308 pc->pc_map[2] != 0, ("pmap_pv_demote_pde: missing spare"));
5309 for (field = 0; field < _NPCM; field++) {
5310 while (pc->pc_map[field]) {
5311 bit = bsfq(pc->pc_map[field]);
5312 pc->pc_map[field] &= ~(1ul << bit);
5313 pv = &pc->pc_pventry[field * 64 + bit];
5317 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5318 ("pmap_pv_demote_pde: page %p is not managed", m));
5319 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
5325 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
5326 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
5329 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 && pc->pc_map[2] == 0) {
5330 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
5331 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
5333 PV_STAT(atomic_add_long(&pv_entry_count, NPTEPG - 1));
5334 PV_STAT(atomic_subtract_int(&pv_entry_spare, NPTEPG - 1));
5337 #if VM_NRESERVLEVEL > 0
5339 * After promotion from 512 4KB page mappings to a single 2MB page mapping,
5340 * replace the many pv entries for the 4KB page mappings by a single pv entry
5341 * for the 2MB page mapping.
5344 pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
5345 struct rwlock **lockp)
5347 struct md_page *pvh;
5349 vm_offset_t va_last;
5352 KASSERT((pa & PDRMASK) == 0,
5353 ("pmap_pv_promote_pde: pa is not 2mpage aligned"));
5354 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
5357 * Transfer the first page's pv entry for this mapping to the 2mpage's
5358 * pv list. Aside from avoiding the cost of a call to get_pv_entry(),
5359 * a transfer avoids the possibility that get_pv_entry() calls
5360 * reclaim_pv_chunk() and that reclaim_pv_chunk() removes one of the
5361 * mappings that is being promoted.
5363 m = PHYS_TO_VM_PAGE(pa);
5364 va = trunc_2mpage(va);
5365 pv = pmap_pvh_remove(&m->md, pmap, va);
5366 KASSERT(pv != NULL, ("pmap_pv_promote_pde: pv not found"));
5367 pvh = pa_to_pvh(pa);
5368 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
5370 /* Free the remaining NPTEPG - 1 pv entries. */
5371 va_last = va + NBPDR - PAGE_SIZE;
5375 pmap_pvh_free(&m->md, pmap, va);
5376 } while (va < va_last);
5378 #endif /* VM_NRESERVLEVEL > 0 */
5381 * First find and then destroy the pv entry for the specified pmap and virtual
5382 * address. This operation can be performed on pv lists for either 4KB or 2MB
5386 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
5390 pv = pmap_pvh_remove(pvh, pmap, va);
5391 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
5392 free_pv_entry(pmap, pv);
5396 * Conditionally create the PV entry for a 4KB page mapping if the required
5397 * memory can be allocated without resorting to reclamation.
5400 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m,
5401 struct rwlock **lockp)
5405 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5406 /* Pass NULL instead of the lock pointer to disable reclamation. */
5407 if ((pv = get_pv_entry(pmap, NULL)) != NULL) {
5409 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
5410 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
5418 * Create the PV entry for a 2MB page mapping. Always returns true unless the
5419 * flag PMAP_ENTER_NORECLAIM is specified. If that flag is specified, returns
5420 * false if the PV entry cannot be allocated without resorting to reclamation.
5423 pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, pd_entry_t pde, u_int flags,
5424 struct rwlock **lockp)
5426 struct md_page *pvh;
5430 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5431 /* Pass NULL instead of the lock pointer to disable reclamation. */
5432 if ((pv = get_pv_entry(pmap, (flags & PMAP_ENTER_NORECLAIM) != 0 ?
5433 NULL : lockp)) == NULL)
5436 pa = pde & PG_PS_FRAME;
5437 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
5438 pvh = pa_to_pvh(pa);
5439 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
5445 * Fills a page table page with mappings to consecutive physical pages.
5448 pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte)
5452 for (pte = firstpte; pte < firstpte + NPTEPG; pte++) {
5454 newpte += PAGE_SIZE;
5459 * Tries to demote a 2MB page mapping. If demotion fails, the 2MB page
5460 * mapping is invalidated.
5463 pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
5465 struct rwlock *lock;
5469 rv = pmap_demote_pde_locked(pmap, pde, va, &lock);
5476 pmap_demote_pde_check(pt_entry_t *firstpte __unused, pt_entry_t newpte __unused)
5480 pt_entry_t *xpte, *ypte;
5482 for (xpte = firstpte; xpte < firstpte + NPTEPG;
5483 xpte++, newpte += PAGE_SIZE) {
5484 if ((*xpte & PG_FRAME) != (newpte & PG_FRAME)) {
5485 printf("pmap_demote_pde: xpte %zd and newpte map "
5486 "different pages: found %#lx, expected %#lx\n",
5487 xpte - firstpte, *xpte, newpte);
5488 printf("page table dump\n");
5489 for (ypte = firstpte; ypte < firstpte + NPTEPG; ypte++)
5490 printf("%zd %#lx\n", ypte - firstpte, *ypte);
5495 KASSERT((*firstpte & PG_FRAME) == (newpte & PG_FRAME),
5496 ("pmap_demote_pde: firstpte and newpte map different physical"
5503 pmap_demote_pde_abort(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
5504 pd_entry_t oldpde, struct rwlock **lockp)
5506 struct spglist free;
5510 sva = trunc_2mpage(va);
5511 pmap_remove_pde(pmap, pde, sva, &free, lockp);
5512 if ((oldpde & pmap_global_bit(pmap)) == 0)
5513 pmap_invalidate_pde_page(pmap, sva, oldpde);
5514 vm_page_free_pages_toq(&free, true);
5515 CTR2(KTR_PMAP, "pmap_demote_pde: failure for va %#lx in pmap %p",
5520 pmap_demote_pde_locked(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
5521 struct rwlock **lockp)
5523 pd_entry_t newpde, oldpde;
5524 pt_entry_t *firstpte, newpte;
5525 pt_entry_t PG_A, PG_G, PG_M, PG_PKU_MASK, PG_RW, PG_V;
5531 PG_A = pmap_accessed_bit(pmap);
5532 PG_G = pmap_global_bit(pmap);
5533 PG_M = pmap_modified_bit(pmap);
5534 PG_RW = pmap_rw_bit(pmap);
5535 PG_V = pmap_valid_bit(pmap);
5536 PG_PTE_CACHE = pmap_cache_mask(pmap, 0);
5537 PG_PKU_MASK = pmap_pku_mask_bit(pmap);
5539 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5540 in_kernel = va >= VM_MAXUSER_ADDRESS;
5542 KASSERT((oldpde & (PG_PS | PG_V)) == (PG_PS | PG_V),
5543 ("pmap_demote_pde: oldpde is missing PG_PS and/or PG_V"));
5546 * Invalidate the 2MB page mapping and return "failure" if the
5547 * mapping was never accessed.
5549 if ((oldpde & PG_A) == 0) {
5550 KASSERT((oldpde & PG_W) == 0,
5551 ("pmap_demote_pde: a wired mapping is missing PG_A"));
5552 pmap_demote_pde_abort(pmap, va, pde, oldpde, lockp);
5556 mpte = pmap_remove_pt_page(pmap, va);
5558 KASSERT((oldpde & PG_W) == 0,
5559 ("pmap_demote_pde: page table page for a wired mapping"
5563 * If the page table page is missing and the mapping
5564 * is for a kernel address, the mapping must belong to
5565 * the direct map. Page table pages are preallocated
5566 * for every other part of the kernel address space,
5567 * so the direct map region is the only part of the
5568 * kernel address space that must be handled here.
5570 KASSERT(!in_kernel || (va >= DMAP_MIN_ADDRESS &&
5571 va < DMAP_MAX_ADDRESS),
5572 ("pmap_demote_pde: No saved mpte for va %#lx", va));
5575 * If the 2MB page mapping belongs to the direct map
5576 * region of the kernel's address space, then the page
5577 * allocation request specifies the highest possible
5578 * priority (VM_ALLOC_INTERRUPT). Otherwise, the
5579 * priority is normal.
5581 mpte = vm_page_alloc(NULL, pmap_pde_pindex(va),
5582 (in_kernel ? VM_ALLOC_INTERRUPT : VM_ALLOC_NORMAL) |
5583 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED);
5586 * If the allocation of the new page table page fails,
5587 * invalidate the 2MB page mapping and return "failure".
5590 pmap_demote_pde_abort(pmap, va, pde, oldpde, lockp);
5595 mpte->ref_count = NPTEPG;
5596 pmap_resident_count_inc(pmap, 1);
5599 mptepa = VM_PAGE_TO_PHYS(mpte);
5600 firstpte = (pt_entry_t *)PHYS_TO_DMAP(mptepa);
5601 newpde = mptepa | PG_M | PG_A | (oldpde & PG_U) | PG_RW | PG_V;
5602 KASSERT((oldpde & (PG_M | PG_RW)) != PG_RW,
5603 ("pmap_demote_pde: oldpde is missing PG_M"));
5604 newpte = oldpde & ~PG_PS;
5605 newpte = pmap_swap_pat(pmap, newpte);
5608 * If the page table page is not leftover from an earlier promotion,
5611 if (mpte->valid == 0)
5612 pmap_fill_ptp(firstpte, newpte);
5614 pmap_demote_pde_check(firstpte, newpte);
5617 * If the mapping has changed attributes, update the page table
5620 if ((*firstpte & PG_PTE_PROMOTE) != (newpte & PG_PTE_PROMOTE))
5621 pmap_fill_ptp(firstpte, newpte);
5624 * The spare PV entries must be reserved prior to demoting the
5625 * mapping, that is, prior to changing the PDE. Otherwise, the state
5626 * of the PDE and the PV lists will be inconsistent, which can result
5627 * in reclaim_pv_chunk() attempting to remove a PV entry from the
5628 * wrong PV list and pmap_pv_demote_pde() failing to find the expected
5629 * PV entry for the 2MB page mapping that is being demoted.
5631 if ((oldpde & PG_MANAGED) != 0)
5632 reserve_pv_entries(pmap, NPTEPG - 1, lockp);
5635 * Demote the mapping. This pmap is locked. The old PDE has
5636 * PG_A set. If the old PDE has PG_RW set, it also has PG_M
5637 * set. Thus, there is no danger of a race with another
5638 * processor changing the setting of PG_A and/or PG_M between
5639 * the read above and the store below.
5641 if (workaround_erratum383)
5642 pmap_update_pde(pmap, va, pde, newpde);
5644 pde_store(pde, newpde);
5647 * Invalidate a stale recursive mapping of the page table page.
5650 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
5653 * Demote the PV entry.
5655 if ((oldpde & PG_MANAGED) != 0)
5656 pmap_pv_demote_pde(pmap, va, oldpde & PG_PS_FRAME, lockp);
5658 atomic_add_long(&pmap_pde_demotions, 1);
5659 CTR2(KTR_PMAP, "pmap_demote_pde: success for va %#lx in pmap %p",
5665 * pmap_remove_kernel_pde: Remove a kernel superpage mapping.
5668 pmap_remove_kernel_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
5674 KASSERT(pmap == kernel_pmap, ("pmap %p is not kernel_pmap", pmap));
5675 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5676 mpte = pmap_remove_pt_page(pmap, va);
5678 panic("pmap_remove_kernel_pde: Missing pt page.");
5680 mptepa = VM_PAGE_TO_PHYS(mpte);
5681 newpde = mptepa | X86_PG_M | X86_PG_A | X86_PG_RW | X86_PG_V;
5684 * If this page table page was unmapped by a promotion, then it
5685 * contains valid mappings. Zero it to invalidate those mappings.
5687 if (mpte->valid != 0)
5688 pagezero((void *)PHYS_TO_DMAP(mptepa));
5691 * Demote the mapping.
5693 if (workaround_erratum383)
5694 pmap_update_pde(pmap, va, pde, newpde);
5696 pde_store(pde, newpde);
5699 * Invalidate a stale recursive mapping of the page table page.
5701 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
5705 * pmap_remove_pde: do the things to unmap a superpage in a process
5708 pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
5709 struct spglist *free, struct rwlock **lockp)
5711 struct md_page *pvh;
5713 vm_offset_t eva, va;
5715 pt_entry_t PG_G, PG_A, PG_M, PG_RW;
5717 PG_G = pmap_global_bit(pmap);
5718 PG_A = pmap_accessed_bit(pmap);
5719 PG_M = pmap_modified_bit(pmap);
5720 PG_RW = pmap_rw_bit(pmap);
5722 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5723 KASSERT((sva & PDRMASK) == 0,
5724 ("pmap_remove_pde: sva is not 2mpage aligned"));
5725 oldpde = pte_load_clear(pdq);
5727 pmap->pm_stats.wired_count -= NBPDR / PAGE_SIZE;
5728 if ((oldpde & PG_G) != 0)
5729 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
5730 pmap_resident_count_dec(pmap, NBPDR / PAGE_SIZE);
5731 if (oldpde & PG_MANAGED) {
5732 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, oldpde & PG_PS_FRAME);
5733 pvh = pa_to_pvh(oldpde & PG_PS_FRAME);
5734 pmap_pvh_free(pvh, pmap, sva);
5736 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
5737 va < eva; va += PAGE_SIZE, m++) {
5738 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
5741 vm_page_aflag_set(m, PGA_REFERENCED);
5742 if (TAILQ_EMPTY(&m->md.pv_list) &&
5743 TAILQ_EMPTY(&pvh->pv_list))
5744 vm_page_aflag_clear(m, PGA_WRITEABLE);
5745 pmap_delayed_invl_page(m);
5748 if (pmap == kernel_pmap) {
5749 pmap_remove_kernel_pde(pmap, pdq, sva);
5751 mpte = pmap_remove_pt_page(pmap, sva);
5753 KASSERT(mpte->valid == VM_PAGE_BITS_ALL,
5754 ("pmap_remove_pde: pte page not promoted"));
5755 pmap_resident_count_dec(pmap, 1);
5756 KASSERT(mpte->ref_count == NPTEPG,
5757 ("pmap_remove_pde: pte page ref count error"));
5758 mpte->ref_count = 0;
5759 pmap_add_delayed_free_list(mpte, free, FALSE);
5762 return (pmap_unuse_pt(pmap, sva, *pmap_pdpe(pmap, sva), free));
5766 * pmap_remove_pte: do the things to unmap a page in a process
5769 pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va,
5770 pd_entry_t ptepde, struct spglist *free, struct rwlock **lockp)
5772 struct md_page *pvh;
5773 pt_entry_t oldpte, PG_A, PG_M, PG_RW;
5776 PG_A = pmap_accessed_bit(pmap);
5777 PG_M = pmap_modified_bit(pmap);
5778 PG_RW = pmap_rw_bit(pmap);
5780 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5781 oldpte = pte_load_clear(ptq);
5783 pmap->pm_stats.wired_count -= 1;
5784 pmap_resident_count_dec(pmap, 1);
5785 if (oldpte & PG_MANAGED) {
5786 m = PHYS_TO_VM_PAGE(oldpte & PG_FRAME);
5787 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
5790 vm_page_aflag_set(m, PGA_REFERENCED);
5791 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
5792 pmap_pvh_free(&m->md, pmap, va);
5793 if (TAILQ_EMPTY(&m->md.pv_list) &&
5794 (m->flags & PG_FICTITIOUS) == 0) {
5795 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5796 if (TAILQ_EMPTY(&pvh->pv_list))
5797 vm_page_aflag_clear(m, PGA_WRITEABLE);
5799 pmap_delayed_invl_page(m);
5801 return (pmap_unuse_pt(pmap, va, ptepde, free));
5805 * Remove a single page from a process address space
5808 pmap_remove_page(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
5809 struct spglist *free)
5811 struct rwlock *lock;
5812 pt_entry_t *pte, PG_V;
5814 PG_V = pmap_valid_bit(pmap);
5815 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5816 if ((*pde & PG_V) == 0)
5818 pte = pmap_pde_to_pte(pde, va);
5819 if ((*pte & PG_V) == 0)
5822 pmap_remove_pte(pmap, pte, va, *pde, free, &lock);
5825 pmap_invalidate_page(pmap, va);
5829 * Removes the specified range of addresses from the page table page.
5832 pmap_remove_ptes(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
5833 pd_entry_t *pde, struct spglist *free, struct rwlock **lockp)
5835 pt_entry_t PG_G, *pte;
5839 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5840 PG_G = pmap_global_bit(pmap);
5843 for (pte = pmap_pde_to_pte(pde, sva); sva != eva; pte++,
5847 pmap_invalidate_range(pmap, va, sva);
5852 if ((*pte & PG_G) == 0)
5856 if (pmap_remove_pte(pmap, pte, sva, *pde, free, lockp)) {
5862 pmap_invalidate_range(pmap, va, sva);
5867 * Remove the given range of addresses from the specified map.
5869 * It is assumed that the start and end are properly
5870 * rounded to the page size.
5873 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
5875 struct rwlock *lock;
5877 vm_offset_t va_next;
5878 pml5_entry_t *pml5e;
5879 pml4_entry_t *pml4e;
5881 pd_entry_t ptpaddr, *pde;
5882 pt_entry_t PG_G, PG_V;
5883 struct spglist free;
5886 PG_G = pmap_global_bit(pmap);
5887 PG_V = pmap_valid_bit(pmap);
5890 * Perform an unsynchronized read. This is, however, safe.
5892 if (pmap->pm_stats.resident_count == 0)
5898 pmap_delayed_invl_start();
5900 pmap_pkru_on_remove(pmap, sva, eva);
5903 * special handling of removing one page. a very
5904 * common operation and easy to short circuit some
5907 if (sva + PAGE_SIZE == eva) {
5908 pde = pmap_pde(pmap, sva);
5909 if (pde && (*pde & PG_PS) == 0) {
5910 pmap_remove_page(pmap, sva, pde, &free);
5916 for (; sva < eva; sva = va_next) {
5917 if (pmap->pm_stats.resident_count == 0)
5920 if (pmap_is_la57(pmap)) {
5921 pml5e = pmap_pml5e(pmap, sva);
5922 if ((*pml5e & PG_V) == 0) {
5923 va_next = (sva + NBPML5) & ~PML5MASK;
5928 pml4e = pmap_pml5e_to_pml4e(pml5e, sva);
5930 pml4e = pmap_pml4e(pmap, sva);
5932 if ((*pml4e & PG_V) == 0) {
5933 va_next = (sva + NBPML4) & ~PML4MASK;
5939 va_next = (sva + NBPDP) & ~PDPMASK;
5942 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
5943 if ((*pdpe & PG_V) == 0)
5945 if ((*pdpe & PG_PS) != 0) {
5946 KASSERT(va_next <= eva,
5947 ("partial update of non-transparent 1G mapping "
5948 "pdpe %#lx sva %#lx eva %#lx va_next %#lx",
5949 *pdpe, sva, eva, va_next));
5950 MPASS(pmap != kernel_pmap); /* XXXKIB */
5951 MPASS((*pdpe & (PG_MANAGED | PG_G)) == 0);
5954 pmap_resident_count_dec(pmap, NBPDP / PAGE_SIZE);
5955 mt = PHYS_TO_VM_PAGE(*pmap_pml4e(pmap, sva) & PG_FRAME);
5956 pmap_unwire_ptp(pmap, sva, mt, &free);
5961 * Calculate index for next page table.
5963 va_next = (sva + NBPDR) & ~PDRMASK;
5967 pde = pmap_pdpe_to_pde(pdpe, sva);
5971 * Weed out invalid mappings.
5977 * Check for large page.
5979 if ((ptpaddr & PG_PS) != 0) {
5981 * Are we removing the entire large page? If not,
5982 * demote the mapping and fall through.
5984 if (sva + NBPDR == va_next && eva >= va_next) {
5986 * The TLB entry for a PG_G mapping is
5987 * invalidated by pmap_remove_pde().
5989 if ((ptpaddr & PG_G) == 0)
5991 pmap_remove_pde(pmap, pde, sva, &free, &lock);
5993 } else if (!pmap_demote_pde_locked(pmap, pde, sva,
5995 /* The large page mapping was destroyed. */
6002 * Limit our scan to either the end of the va represented
6003 * by the current page table page, or to the end of the
6004 * range being removed.
6009 if (pmap_remove_ptes(pmap, sva, va_next, pde, &free, &lock))
6016 pmap_invalidate_all(pmap);
6018 pmap_delayed_invl_finish();
6019 vm_page_free_pages_toq(&free, true);
6023 * Routine: pmap_remove_all
6025 * Removes this physical page from
6026 * all physical maps in which it resides.
6027 * Reflects back modify bits to the pager.
6030 * Original versions of this routine were very
6031 * inefficient because they iteratively called
6032 * pmap_remove (slow...)
6036 pmap_remove_all(vm_page_t m)
6038 struct md_page *pvh;
6041 struct rwlock *lock;
6042 pt_entry_t *pte, tpte, PG_A, PG_M, PG_RW;
6045 struct spglist free;
6046 int pvh_gen, md_gen;
6048 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
6049 ("pmap_remove_all: page %p is not managed", m));
6051 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
6052 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
6053 pa_to_pvh(VM_PAGE_TO_PHYS(m));
6056 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
6058 if (!PMAP_TRYLOCK(pmap)) {
6059 pvh_gen = pvh->pv_gen;
6063 if (pvh_gen != pvh->pv_gen) {
6070 pde = pmap_pde(pmap, va);
6071 (void)pmap_demote_pde_locked(pmap, pde, va, &lock);
6074 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
6076 if (!PMAP_TRYLOCK(pmap)) {
6077 pvh_gen = pvh->pv_gen;
6078 md_gen = m->md.pv_gen;
6082 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
6088 PG_A = pmap_accessed_bit(pmap);
6089 PG_M = pmap_modified_bit(pmap);
6090 PG_RW = pmap_rw_bit(pmap);
6091 pmap_resident_count_dec(pmap, 1);
6092 pde = pmap_pde(pmap, pv->pv_va);
6093 KASSERT((*pde & PG_PS) == 0, ("pmap_remove_all: found"
6094 " a 2mpage in page %p's pv list", m));
6095 pte = pmap_pde_to_pte(pde, pv->pv_va);
6096 tpte = pte_load_clear(pte);
6098 pmap->pm_stats.wired_count--;
6100 vm_page_aflag_set(m, PGA_REFERENCED);
6103 * Update the vm_page_t clean and reference bits.
6105 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
6107 pmap_unuse_pt(pmap, pv->pv_va, *pde, &free);
6108 pmap_invalidate_page(pmap, pv->pv_va);
6109 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
6111 free_pv_entry(pmap, pv);
6114 vm_page_aflag_clear(m, PGA_WRITEABLE);
6116 pmap_delayed_invl_wait(m);
6117 vm_page_free_pages_toq(&free, true);
6121 * pmap_protect_pde: do the things to protect a 2mpage in a process
6124 pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, vm_prot_t prot)
6126 pd_entry_t newpde, oldpde;
6128 boolean_t anychanged;
6129 pt_entry_t PG_G, PG_M, PG_RW;
6131 PG_G = pmap_global_bit(pmap);
6132 PG_M = pmap_modified_bit(pmap);
6133 PG_RW = pmap_rw_bit(pmap);
6135 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6136 KASSERT((sva & PDRMASK) == 0,
6137 ("pmap_protect_pde: sva is not 2mpage aligned"));
6140 oldpde = newpde = *pde;
6141 if ((prot & VM_PROT_WRITE) == 0) {
6142 if ((oldpde & (PG_MANAGED | PG_M | PG_RW)) ==
6143 (PG_MANAGED | PG_M | PG_RW)) {
6144 m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
6145 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
6148 newpde &= ~(PG_RW | PG_M);
6150 if ((prot & VM_PROT_EXECUTE) == 0)
6152 if (newpde != oldpde) {
6154 * As an optimization to future operations on this PDE, clear
6155 * PG_PROMOTED. The impending invalidation will remove any
6156 * lingering 4KB page mappings from the TLB.
6158 if (!atomic_cmpset_long(pde, oldpde, newpde & ~PG_PROMOTED))
6160 if ((oldpde & PG_G) != 0)
6161 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
6165 return (anychanged);
6169 * Set the physical protection on the
6170 * specified range of this map as requested.
6173 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
6176 vm_offset_t va_next;
6177 pml4_entry_t *pml4e;
6179 pd_entry_t ptpaddr, *pde;
6180 pt_entry_t *pte, PG_G, PG_M, PG_RW, PG_V;
6181 pt_entry_t obits, pbits;
6182 boolean_t anychanged;
6184 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
6185 if (prot == VM_PROT_NONE) {
6186 pmap_remove(pmap, sva, eva);
6190 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) ==
6191 (VM_PROT_WRITE|VM_PROT_EXECUTE))
6194 PG_G = pmap_global_bit(pmap);
6195 PG_M = pmap_modified_bit(pmap);
6196 PG_V = pmap_valid_bit(pmap);
6197 PG_RW = pmap_rw_bit(pmap);
6201 * Although this function delays and batches the invalidation
6202 * of stale TLB entries, it does not need to call
6203 * pmap_delayed_invl_start() and
6204 * pmap_delayed_invl_finish(), because it does not
6205 * ordinarily destroy mappings. Stale TLB entries from
6206 * protection-only changes need only be invalidated before the
6207 * pmap lock is released, because protection-only changes do
6208 * not destroy PV entries. Even operations that iterate over
6209 * a physical page's PV list of mappings, like
6210 * pmap_remove_write(), acquire the pmap lock for each
6211 * mapping. Consequently, for protection-only changes, the
6212 * pmap lock suffices to synchronize both page table and TLB
6215 * This function only destroys a mapping if pmap_demote_pde()
6216 * fails. In that case, stale TLB entries are immediately
6221 for (; sva < eva; sva = va_next) {
6222 pml4e = pmap_pml4e(pmap, sva);
6223 if (pml4e == NULL || (*pml4e & PG_V) == 0) {
6224 va_next = (sva + NBPML4) & ~PML4MASK;
6230 va_next = (sva + NBPDP) & ~PDPMASK;
6233 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
6234 if ((*pdpe & PG_V) == 0)
6236 if ((*pdpe & PG_PS) != 0) {
6237 KASSERT(va_next <= eva,
6238 ("partial update of non-transparent 1G mapping "
6239 "pdpe %#lx sva %#lx eva %#lx va_next %#lx",
6240 *pdpe, sva, eva, va_next));
6242 obits = pbits = *pdpe;
6243 MPASS((pbits & (PG_MANAGED | PG_G)) == 0);
6244 MPASS(pmap != kernel_pmap); /* XXXKIB */
6245 if ((prot & VM_PROT_WRITE) == 0)
6246 pbits &= ~(PG_RW | PG_M);
6247 if ((prot & VM_PROT_EXECUTE) == 0)
6250 if (pbits != obits) {
6251 if (!atomic_cmpset_long(pdpe, obits, pbits))
6252 /* PG_PS cannot be cleared under us, */
6259 va_next = (sva + NBPDR) & ~PDRMASK;
6263 pde = pmap_pdpe_to_pde(pdpe, sva);
6267 * Weed out invalid mappings.
6273 * Check for large page.
6275 if ((ptpaddr & PG_PS) != 0) {
6277 * Are we protecting the entire large page? If not,
6278 * demote the mapping and fall through.
6280 if (sva + NBPDR == va_next && eva >= va_next) {
6282 * The TLB entry for a PG_G mapping is
6283 * invalidated by pmap_protect_pde().
6285 if (pmap_protect_pde(pmap, pde, sva, prot))
6288 } else if (!pmap_demote_pde(pmap, pde, sva)) {
6290 * The large page mapping was destroyed.
6299 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
6302 obits = pbits = *pte;
6303 if ((pbits & PG_V) == 0)
6306 if ((prot & VM_PROT_WRITE) == 0) {
6307 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) ==
6308 (PG_MANAGED | PG_M | PG_RW)) {
6309 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME);
6312 pbits &= ~(PG_RW | PG_M);
6314 if ((prot & VM_PROT_EXECUTE) == 0)
6317 if (pbits != obits) {
6318 if (!atomic_cmpset_long(pte, obits, pbits))
6321 pmap_invalidate_page(pmap, sva);
6328 pmap_invalidate_all(pmap);
6332 #if VM_NRESERVLEVEL > 0
6334 pmap_pde_ept_executable(pmap_t pmap, pd_entry_t pde)
6337 if (pmap->pm_type != PT_EPT)
6339 return ((pde & EPT_PG_EXECUTE) != 0);
6343 * Tries to promote the 512, contiguous 4KB page mappings that are within a
6344 * single page table page (PTP) to a single 2MB page mapping. For promotion
6345 * to occur, two conditions must be met: (1) the 4KB page mappings must map
6346 * aligned, contiguous physical memory and (2) the 4KB page mappings must have
6347 * identical characteristics.
6350 pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
6351 struct rwlock **lockp)
6354 pt_entry_t *firstpte, oldpte, pa, *pte;
6355 pt_entry_t PG_G, PG_A, PG_M, PG_RW, PG_V, PG_PKU_MASK;
6359 PG_A = pmap_accessed_bit(pmap);
6360 PG_G = pmap_global_bit(pmap);
6361 PG_M = pmap_modified_bit(pmap);
6362 PG_V = pmap_valid_bit(pmap);
6363 PG_RW = pmap_rw_bit(pmap);
6364 PG_PKU_MASK = pmap_pku_mask_bit(pmap);
6365 PG_PTE_CACHE = pmap_cache_mask(pmap, 0);
6367 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6370 * Examine the first PTE in the specified PTP. Abort if this PTE is
6371 * either invalid, unused, or does not map the first 4KB physical page
6372 * within a 2MB page.
6374 firstpte = (pt_entry_t *)PHYS_TO_DMAP(*pde & PG_FRAME);
6377 if ((newpde & ((PG_FRAME & PDRMASK) | PG_A | PG_V)) != (PG_A | PG_V) ||
6378 !pmap_allow_2m_x_page(pmap, pmap_pde_ept_executable(pmap,
6380 atomic_add_long(&pmap_pde_p_failures, 1);
6381 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
6382 " in pmap %p", va, pmap);
6385 if ((newpde & (PG_M | PG_RW)) == PG_RW) {
6387 * When PG_M is already clear, PG_RW can be cleared without
6388 * a TLB invalidation.
6390 if (!atomic_cmpset_long(firstpte, newpde, newpde & ~PG_RW))
6396 * Examine each of the other PTEs in the specified PTP. Abort if this
6397 * PTE maps an unexpected 4KB physical page or does not have identical
6398 * characteristics to the first PTE.
6400 pa = (newpde & (PG_PS_FRAME | PG_A | PG_V)) + NBPDR - PAGE_SIZE;
6401 for (pte = firstpte + NPTEPG - 1; pte > firstpte; pte--) {
6404 if ((oldpte & (PG_FRAME | PG_A | PG_V)) != pa) {
6405 atomic_add_long(&pmap_pde_p_failures, 1);
6406 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
6407 " in pmap %p", va, pmap);
6410 if ((oldpte & (PG_M | PG_RW)) == PG_RW) {
6412 * When PG_M is already clear, PG_RW can be cleared
6413 * without a TLB invalidation.
6415 if (!atomic_cmpset_long(pte, oldpte, oldpte & ~PG_RW))
6418 CTR2(KTR_PMAP, "pmap_promote_pde: protect for va %#lx"
6419 " in pmap %p", (oldpte & PG_FRAME & PDRMASK) |
6420 (va & ~PDRMASK), pmap);
6422 if ((oldpte & PG_PTE_PROMOTE) != (newpde & PG_PTE_PROMOTE)) {
6423 atomic_add_long(&pmap_pde_p_failures, 1);
6424 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
6425 " in pmap %p", va, pmap);
6432 * Save the page table page in its current state until the PDE
6433 * mapping the superpage is demoted by pmap_demote_pde() or
6434 * destroyed by pmap_remove_pde().
6436 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
6437 KASSERT(mpte >= vm_page_array &&
6438 mpte < &vm_page_array[vm_page_array_size],
6439 ("pmap_promote_pde: page table page is out of range"));
6440 KASSERT(mpte->pindex == pmap_pde_pindex(va),
6441 ("pmap_promote_pde: page table page's pindex is wrong"));
6442 if (pmap_insert_pt_page(pmap, mpte, true)) {
6443 atomic_add_long(&pmap_pde_p_failures, 1);
6445 "pmap_promote_pde: failure for va %#lx in pmap %p", va,
6451 * Promote the pv entries.
6453 if ((newpde & PG_MANAGED) != 0)
6454 pmap_pv_promote_pde(pmap, va, newpde & PG_PS_FRAME, lockp);
6457 * Propagate the PAT index to its proper position.
6459 newpde = pmap_swap_pat(pmap, newpde);
6462 * Map the superpage.
6464 if (workaround_erratum383)
6465 pmap_update_pde(pmap, va, pde, PG_PS | newpde);
6467 pde_store(pde, PG_PROMOTED | PG_PS | newpde);
6469 atomic_add_long(&pmap_pde_promotions, 1);
6470 CTR2(KTR_PMAP, "pmap_promote_pde: success for va %#lx"
6471 " in pmap %p", va, pmap);
6473 #endif /* VM_NRESERVLEVEL > 0 */
6476 pmap_enter_largepage(pmap_t pmap, vm_offset_t va, pt_entry_t newpte, int flags,
6480 pt_entry_t origpte, *pml4e, *pdpe, *pde, pten, PG_V;
6482 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6483 KASSERT(psind > 0 && psind < MAXPAGESIZES && pagesizes[psind] != 0,
6484 ("psind %d unexpected", psind));
6485 KASSERT(((newpte & PG_FRAME) & (pagesizes[psind] - 1)) == 0,
6486 ("unaligned phys address %#lx newpte %#lx psind %d",
6487 newpte & PG_FRAME, newpte, psind));
6488 KASSERT((va & (pagesizes[psind] - 1)) == 0,
6489 ("unaligned va %#lx psind %d", va, psind));
6490 KASSERT(va < VM_MAXUSER_ADDRESS,
6491 ("kernel mode non-transparent superpage")); /* XXXKIB */
6492 KASSERT(va + pagesizes[psind] < VM_MAXUSER_ADDRESS,
6493 ("overflowing user map va %#lx psind %d", va, psind)); /* XXXKIB */
6495 PG_V = pmap_valid_bit(pmap);
6498 if (!pmap_pkru_same(pmap, va, va + pagesizes[psind]))
6499 return (KERN_PROTECTION_FAILURE);
6501 if (va < VM_MAXUSER_ADDRESS && pmap->pm_type == PT_X86)
6502 pten |= pmap_pkru_get(pmap, va);
6504 if (psind == 2) { /* 1G */
6505 pml4e = pmap_pml4e(pmap, va);
6506 if (pml4e == NULL || (*pml4e & PG_V) == 0) {
6507 mp = _pmap_allocpte(pmap, pmap_pml4e_pindex(va),
6511 pdpe = (pdp_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mp));
6512 pdpe = &pdpe[pmap_pdpe_index(va)];
6514 MPASS(origpte == 0);
6516 pdpe = pmap_pml4e_to_pdpe(pml4e, va);
6517 KASSERT(pdpe != NULL, ("va %#lx lost pdpe", va));
6519 if ((origpte & PG_V) == 0) {
6520 mp = PHYS_TO_VM_PAGE(*pml4e & PG_FRAME);
6525 } else /* (psind == 1) */ { /* 2M */
6526 pde = pmap_pde(pmap, va);
6528 mp = _pmap_allocpte(pmap, pmap_pdpe_pindex(va),
6532 pde = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mp));
6533 pde = &pde[pmap_pde_index(va)];
6535 MPASS(origpte == 0);
6538 if ((origpte & PG_V) == 0) {
6539 pdpe = pmap_pdpe(pmap, va);
6540 MPASS(pdpe != NULL && (*pdpe & PG_V) != 0);
6541 mp = PHYS_TO_VM_PAGE(*pdpe & PG_FRAME);
6547 KASSERT((origpte & PG_V) == 0 || ((origpte & PG_PS) != 0 &&
6548 (origpte & PG_PS_FRAME) == (pten & PG_PS_FRAME)),
6549 ("va %#lx changing %s phys page origpte %#lx pten %#lx",
6550 va, psind == 2 ? "1G" : "2M", origpte, pten));
6551 if ((pten & PG_W) != 0 && (origpte & PG_W) == 0)
6552 pmap->pm_stats.wired_count += pagesizes[psind] / PAGE_SIZE;
6553 else if ((pten & PG_W) == 0 && (origpte & PG_W) != 0)
6554 pmap->pm_stats.wired_count -= pagesizes[psind] / PAGE_SIZE;
6555 if ((origpte & PG_V) == 0)
6556 pmap_resident_count_inc(pmap, pagesizes[psind] / PAGE_SIZE);
6558 return (KERN_SUCCESS);
6561 if ((flags & PMAP_ENTER_NOSLEEP) != 0)
6562 return (KERN_RESOURCE_SHORTAGE);
6570 * Insert the given physical page (p) at
6571 * the specified virtual address (v) in the
6572 * target physical map with the protection requested.
6574 * If specified, the page will be wired down, meaning
6575 * that the related pte can not be reclaimed.
6577 * NB: This is the only routine which MAY NOT lazy-evaluate
6578 * or lose information. That is, this routine must actually
6579 * insert this page into the given map NOW.
6581 * When destroying both a page table and PV entry, this function
6582 * performs the TLB invalidation before releasing the PV list
6583 * lock, so we do not need pmap_delayed_invl_page() calls here.
6586 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
6587 u_int flags, int8_t psind)
6589 struct rwlock *lock;
6591 pt_entry_t *pte, PG_G, PG_A, PG_M, PG_RW, PG_V;
6592 pt_entry_t newpte, origpte;
6599 PG_A = pmap_accessed_bit(pmap);
6600 PG_G = pmap_global_bit(pmap);
6601 PG_M = pmap_modified_bit(pmap);
6602 PG_V = pmap_valid_bit(pmap);
6603 PG_RW = pmap_rw_bit(pmap);
6605 va = trunc_page(va);
6606 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig"));
6607 KASSERT(va < UPT_MIN_ADDRESS || va >= UPT_MAX_ADDRESS,
6608 ("pmap_enter: invalid to pmap_enter page table pages (va: 0x%lx)",
6610 KASSERT((m->oflags & VPO_UNMANAGED) != 0 || va < kmi.clean_sva ||
6611 va >= kmi.clean_eva,
6612 ("pmap_enter: managed mapping within the clean submap"));
6613 if ((m->oflags & VPO_UNMANAGED) == 0)
6614 VM_PAGE_OBJECT_BUSY_ASSERT(m);
6615 KASSERT((flags & PMAP_ENTER_RESERVED) == 0,
6616 ("pmap_enter: flags %u has reserved bits set", flags));
6617 pa = VM_PAGE_TO_PHYS(m);
6618 newpte = (pt_entry_t)(pa | PG_A | PG_V);
6619 if ((flags & VM_PROT_WRITE) != 0)
6621 if ((prot & VM_PROT_WRITE) != 0)
6623 KASSERT((newpte & (PG_M | PG_RW)) != PG_M,
6624 ("pmap_enter: flags includes VM_PROT_WRITE but prot doesn't"));
6625 if ((prot & VM_PROT_EXECUTE) == 0)
6627 if ((flags & PMAP_ENTER_WIRED) != 0)
6629 if (va < VM_MAXUSER_ADDRESS)
6631 if (pmap == kernel_pmap)
6633 newpte |= pmap_cache_bits(pmap, m->md.pat_mode, psind > 0);
6636 * Set modified bit gratuitously for writeable mappings if
6637 * the page is unmanaged. We do not want to take a fault
6638 * to do the dirty bit accounting for these mappings.
6640 if ((m->oflags & VPO_UNMANAGED) != 0) {
6641 if ((newpte & PG_RW) != 0)
6644 newpte |= PG_MANAGED;
6648 if ((flags & PMAP_ENTER_LARGEPAGE) != 0) {
6649 KASSERT((m->oflags & VPO_UNMANAGED) != 0,
6650 ("managed largepage va %#lx flags %#x", va, flags));
6651 rv = pmap_enter_largepage(pmap, va, newpte | PG_PS, flags,
6656 /* Assert the required virtual and physical alignment. */
6657 KASSERT((va & PDRMASK) == 0, ("pmap_enter: va unaligned"));
6658 KASSERT(m->psind > 0, ("pmap_enter: m->psind < psind"));
6659 rv = pmap_enter_pde(pmap, va, newpte | PG_PS, flags, m, &lock);
6665 * In the case that a page table page is not
6666 * resident, we are creating it here.
6669 pde = pmap_pde(pmap, va);
6670 if (pde != NULL && (*pde & PG_V) != 0 && ((*pde & PG_PS) == 0 ||
6671 pmap_demote_pde_locked(pmap, pde, va, &lock))) {
6672 pte = pmap_pde_to_pte(pde, va);
6673 if (va < VM_MAXUSER_ADDRESS && mpte == NULL) {
6674 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
6677 } else if (va < VM_MAXUSER_ADDRESS) {
6679 * Here if the pte page isn't mapped, or if it has been
6682 nosleep = (flags & PMAP_ENTER_NOSLEEP) != 0;
6683 mpte = _pmap_allocpte(pmap, pmap_pde_pindex(va),
6684 nosleep ? NULL : &lock, va);
6685 if (mpte == NULL && nosleep) {
6686 rv = KERN_RESOURCE_SHORTAGE;
6691 panic("pmap_enter: invalid page directory va=%#lx", va);
6695 if (va < VM_MAXUSER_ADDRESS && pmap->pm_type == PT_X86)
6696 newpte |= pmap_pkru_get(pmap, va);
6699 * Is the specified virtual address already mapped?
6701 if ((origpte & PG_V) != 0) {
6703 * Wiring change, just update stats. We don't worry about
6704 * wiring PT pages as they remain resident as long as there
6705 * are valid mappings in them. Hence, if a user page is wired,
6706 * the PT page will be also.
6708 if ((newpte & PG_W) != 0 && (origpte & PG_W) == 0)
6709 pmap->pm_stats.wired_count++;
6710 else if ((newpte & PG_W) == 0 && (origpte & PG_W) != 0)
6711 pmap->pm_stats.wired_count--;
6714 * Remove the extra PT page reference.
6718 KASSERT(mpte->ref_count > 0,
6719 ("pmap_enter: missing reference to page table page,"
6724 * Has the physical page changed?
6726 opa = origpte & PG_FRAME;
6729 * No, might be a protection or wiring change.
6731 if ((origpte & PG_MANAGED) != 0 &&
6732 (newpte & PG_RW) != 0)
6733 vm_page_aflag_set(m, PGA_WRITEABLE);
6734 if (((origpte ^ newpte) & ~(PG_M | PG_A)) == 0)
6740 * The physical page has changed. Temporarily invalidate
6741 * the mapping. This ensures that all threads sharing the
6742 * pmap keep a consistent view of the mapping, which is
6743 * necessary for the correct handling of COW faults. It
6744 * also permits reuse of the old mapping's PV entry,
6745 * avoiding an allocation.
6747 * For consistency, handle unmanaged mappings the same way.
6749 origpte = pte_load_clear(pte);
6750 KASSERT((origpte & PG_FRAME) == opa,
6751 ("pmap_enter: unexpected pa update for %#lx", va));
6752 if ((origpte & PG_MANAGED) != 0) {
6753 om = PHYS_TO_VM_PAGE(opa);
6756 * The pmap lock is sufficient to synchronize with
6757 * concurrent calls to pmap_page_test_mappings() and
6758 * pmap_ts_referenced().
6760 if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
6762 if ((origpte & PG_A) != 0) {
6763 pmap_invalidate_page(pmap, va);
6764 vm_page_aflag_set(om, PGA_REFERENCED);
6766 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, opa);
6767 pv = pmap_pvh_remove(&om->md, pmap, va);
6769 ("pmap_enter: no PV entry for %#lx", va));
6770 if ((newpte & PG_MANAGED) == 0)
6771 free_pv_entry(pmap, pv);
6772 if ((om->a.flags & PGA_WRITEABLE) != 0 &&
6773 TAILQ_EMPTY(&om->md.pv_list) &&
6774 ((om->flags & PG_FICTITIOUS) != 0 ||
6775 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
6776 vm_page_aflag_clear(om, PGA_WRITEABLE);
6779 * Since this mapping is unmanaged, assume that PG_A
6782 pmap_invalidate_page(pmap, va);
6787 * Increment the counters.
6789 if ((newpte & PG_W) != 0)
6790 pmap->pm_stats.wired_count++;
6791 pmap_resident_count_inc(pmap, 1);
6795 * Enter on the PV list if part of our managed memory.
6797 if ((newpte & PG_MANAGED) != 0) {
6799 pv = get_pv_entry(pmap, &lock);
6802 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, pa);
6803 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
6805 if ((newpte & PG_RW) != 0)
6806 vm_page_aflag_set(m, PGA_WRITEABLE);
6812 if ((origpte & PG_V) != 0) {
6814 origpte = pte_load_store(pte, newpte);
6815 KASSERT((origpte & PG_FRAME) == pa,
6816 ("pmap_enter: unexpected pa update for %#lx", va));
6817 if ((newpte & PG_M) == 0 && (origpte & (PG_M | PG_RW)) ==
6819 if ((origpte & PG_MANAGED) != 0)
6823 * Although the PTE may still have PG_RW set, TLB
6824 * invalidation may nonetheless be required because
6825 * the PTE no longer has PG_M set.
6827 } else if ((origpte & PG_NX) != 0 || (newpte & PG_NX) == 0) {
6829 * This PTE change does not require TLB invalidation.
6833 if ((origpte & PG_A) != 0)
6834 pmap_invalidate_page(pmap, va);
6836 pte_store(pte, newpte);
6840 #if VM_NRESERVLEVEL > 0
6842 * If both the page table page and the reservation are fully
6843 * populated, then attempt promotion.
6845 if ((mpte == NULL || mpte->ref_count == NPTEPG) &&
6846 pmap_ps_enabled(pmap) &&
6847 (m->flags & PG_FICTITIOUS) == 0 &&
6848 vm_reserv_level_iffullpop(m) == 0)
6849 pmap_promote_pde(pmap, pde, va, &lock);
6861 * Tries to create a read- and/or execute-only 2MB page mapping. Returns true
6862 * if successful. Returns false if (1) a page table page cannot be allocated
6863 * without sleeping, (2) a mapping already exists at the specified virtual
6864 * address, or (3) a PV entry cannot be allocated without reclaiming another
6868 pmap_enter_2mpage(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
6869 struct rwlock **lockp)
6874 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6875 PG_V = pmap_valid_bit(pmap);
6876 newpde = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(pmap, m->md.pat_mode, 1) |
6878 if ((m->oflags & VPO_UNMANAGED) == 0)
6879 newpde |= PG_MANAGED;
6880 if ((prot & VM_PROT_EXECUTE) == 0)
6882 if (va < VM_MAXUSER_ADDRESS)
6884 return (pmap_enter_pde(pmap, va, newpde, PMAP_ENTER_NOSLEEP |
6885 PMAP_ENTER_NOREPLACE | PMAP_ENTER_NORECLAIM, NULL, lockp) ==
6890 * Returns true if every page table entry in the specified page table page is
6894 pmap_every_pte_zero(vm_paddr_t pa)
6896 pt_entry_t *pt_end, *pte;
6898 KASSERT((pa & PAGE_MASK) == 0, ("pa is misaligned"));
6899 pte = (pt_entry_t *)PHYS_TO_DMAP(pa);
6900 for (pt_end = pte + NPTEPG; pte < pt_end; pte++) {
6908 * Tries to create the specified 2MB page mapping. Returns KERN_SUCCESS if
6909 * the mapping was created, and either KERN_FAILURE or KERN_RESOURCE_SHORTAGE
6910 * otherwise. Returns KERN_FAILURE if PMAP_ENTER_NOREPLACE was specified and
6911 * a mapping already exists at the specified virtual address. Returns
6912 * KERN_RESOURCE_SHORTAGE if PMAP_ENTER_NOSLEEP was specified and a page table
6913 * page allocation failed. Returns KERN_RESOURCE_SHORTAGE if
6914 * PMAP_ENTER_NORECLAIM was specified and a PV entry allocation failed.
6916 * The parameter "m" is only used when creating a managed, writeable mapping.
6919 pmap_enter_pde(pmap_t pmap, vm_offset_t va, pd_entry_t newpde, u_int flags,
6920 vm_page_t m, struct rwlock **lockp)
6922 struct spglist free;
6923 pd_entry_t oldpde, *pde;
6924 pt_entry_t PG_G, PG_RW, PG_V;
6927 KASSERT(pmap == kernel_pmap || (newpde & PG_W) == 0,
6928 ("pmap_enter_pde: cannot create wired user mapping"));
6929 PG_G = pmap_global_bit(pmap);
6930 PG_RW = pmap_rw_bit(pmap);
6931 KASSERT((newpde & (pmap_modified_bit(pmap) | PG_RW)) != PG_RW,
6932 ("pmap_enter_pde: newpde is missing PG_M"));
6933 PG_V = pmap_valid_bit(pmap);
6934 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6936 if (!pmap_allow_2m_x_page(pmap, pmap_pde_ept_executable(pmap,
6938 CTR2(KTR_PMAP, "pmap_enter_pde: 2m x blocked for va %#lx"
6939 " in pmap %p", va, pmap);
6940 return (KERN_FAILURE);
6942 if ((pde = pmap_alloc_pde(pmap, va, &pdpg, (flags &
6943 PMAP_ENTER_NOSLEEP) != 0 ? NULL : lockp)) == NULL) {
6944 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
6945 " in pmap %p", va, pmap);
6946 return (KERN_RESOURCE_SHORTAGE);
6950 * If pkru is not same for the whole pde range, return failure
6951 * and let vm_fault() cope. Check after pde allocation, since
6954 if (!pmap_pkru_same(pmap, va, va + NBPDR)) {
6955 pmap_abort_ptp(pmap, va, pdpg);
6956 return (KERN_FAILURE);
6958 if (va < VM_MAXUSER_ADDRESS && pmap->pm_type == PT_X86) {
6959 newpde &= ~X86_PG_PKU_MASK;
6960 newpde |= pmap_pkru_get(pmap, va);
6964 * If there are existing mappings, either abort or remove them.
6967 if ((oldpde & PG_V) != 0) {
6968 KASSERT(pdpg == NULL || pdpg->ref_count > 1,
6969 ("pmap_enter_pde: pdpg's reference count is too low"));
6970 if ((flags & PMAP_ENTER_NOREPLACE) != 0 && (va <
6971 VM_MAXUSER_ADDRESS || (oldpde & PG_PS) != 0 ||
6972 !pmap_every_pte_zero(oldpde & PG_FRAME))) {
6975 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
6976 " in pmap %p", va, pmap);
6977 return (KERN_FAILURE);
6979 /* Break the existing mapping(s). */
6981 if ((oldpde & PG_PS) != 0) {
6983 * The reference to the PD page that was acquired by
6984 * pmap_alloc_pde() ensures that it won't be freed.
6985 * However, if the PDE resulted from a promotion, then
6986 * a reserved PT page could be freed.
6988 (void)pmap_remove_pde(pmap, pde, va, &free, lockp);
6989 if ((oldpde & PG_G) == 0)
6990 pmap_invalidate_pde_page(pmap, va, oldpde);
6992 pmap_delayed_invl_start();
6993 if (pmap_remove_ptes(pmap, va, va + NBPDR, pde, &free,
6995 pmap_invalidate_all(pmap);
6996 pmap_delayed_invl_finish();
6998 if (va < VM_MAXUSER_ADDRESS) {
6999 vm_page_free_pages_toq(&free, true);
7000 KASSERT(*pde == 0, ("pmap_enter_pde: non-zero pde %p",
7003 KASSERT(SLIST_EMPTY(&free),
7004 ("pmap_enter_pde: freed kernel page table page"));
7007 * Both pmap_remove_pde() and pmap_remove_ptes() will
7008 * leave the kernel page table page zero filled.
7010 mt = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
7011 if (pmap_insert_pt_page(pmap, mt, false))
7012 panic("pmap_enter_pde: trie insert failed");
7016 if ((newpde & PG_MANAGED) != 0) {
7018 * Abort this mapping if its PV entry could not be created.
7020 if (!pmap_pv_insert_pde(pmap, va, newpde, flags, lockp)) {
7022 pmap_abort_ptp(pmap, va, pdpg);
7023 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
7024 " in pmap %p", va, pmap);
7025 return (KERN_RESOURCE_SHORTAGE);
7027 if ((newpde & PG_RW) != 0) {
7028 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
7029 vm_page_aflag_set(mt, PGA_WRITEABLE);
7034 * Increment counters.
7036 if ((newpde & PG_W) != 0)
7037 pmap->pm_stats.wired_count += NBPDR / PAGE_SIZE;
7038 pmap_resident_count_inc(pmap, NBPDR / PAGE_SIZE);
7041 * Map the superpage. (This is not a promoted mapping; there will not
7042 * be any lingering 4KB page mappings in the TLB.)
7044 pde_store(pde, newpde);
7046 atomic_add_long(&pmap_pde_mappings, 1);
7047 CTR2(KTR_PMAP, "pmap_enter_pde: success for va %#lx in pmap %p",
7049 return (KERN_SUCCESS);
7053 * Maps a sequence of resident pages belonging to the same object.
7054 * The sequence begins with the given page m_start. This page is
7055 * mapped at the given virtual address start. Each subsequent page is
7056 * mapped at a virtual address that is offset from start by the same
7057 * amount as the page is offset from m_start within the object. The
7058 * last page in the sequence is the page with the largest offset from
7059 * m_start that can be mapped at a virtual address less than the given
7060 * virtual address end. Not every virtual page between start and end
7061 * is mapped; only those for which a resident page exists with the
7062 * corresponding offset from m_start are mapped.
7065 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
7066 vm_page_t m_start, vm_prot_t prot)
7068 struct rwlock *lock;
7071 vm_pindex_t diff, psize;
7073 VM_OBJECT_ASSERT_LOCKED(m_start->object);
7075 psize = atop(end - start);
7080 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
7081 va = start + ptoa(diff);
7082 if ((va & PDRMASK) == 0 && va + NBPDR <= end &&
7083 m->psind == 1 && pmap_ps_enabled(pmap) &&
7084 pmap_allow_2m_x_page(pmap, (prot & VM_PROT_EXECUTE) != 0) &&
7085 pmap_enter_2mpage(pmap, va, m, prot, &lock))
7086 m = &m[NBPDR / PAGE_SIZE - 1];
7088 mpte = pmap_enter_quick_locked(pmap, va, m, prot,
7090 m = TAILQ_NEXT(m, listq);
7098 * this code makes some *MAJOR* assumptions:
7099 * 1. Current pmap & pmap exists.
7102 * 4. No page table pages.
7103 * but is *MUCH* faster than pmap_enter...
7107 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
7109 struct rwlock *lock;
7113 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL, &lock);
7120 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
7121 vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp)
7123 pt_entry_t newpte, *pte, PG_V;
7125 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
7126 (m->oflags & VPO_UNMANAGED) != 0,
7127 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
7128 PG_V = pmap_valid_bit(pmap);
7129 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
7132 * In the case that a page table page is not
7133 * resident, we are creating it here.
7135 if (va < VM_MAXUSER_ADDRESS) {
7136 vm_pindex_t ptepindex;
7140 * Calculate pagetable page index
7142 ptepindex = pmap_pde_pindex(va);
7143 if (mpte && (mpte->pindex == ptepindex)) {
7147 * Get the page directory entry
7149 ptepa = pmap_pde(pmap, va);
7152 * If the page table page is mapped, we just increment
7153 * the hold count, and activate it. Otherwise, we
7154 * attempt to allocate a page table page. If this
7155 * attempt fails, we don't retry. Instead, we give up.
7157 if (ptepa && (*ptepa & PG_V) != 0) {
7160 mpte = PHYS_TO_VM_PAGE(*ptepa & PG_FRAME);
7164 * Pass NULL instead of the PV list lock
7165 * pointer, because we don't intend to sleep.
7167 mpte = _pmap_allocpte(pmap, ptepindex, NULL,
7173 pte = (pt_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpte));
7174 pte = &pte[pmap_pte_index(va)];
7186 * Enter on the PV list if part of our managed memory.
7188 if ((m->oflags & VPO_UNMANAGED) == 0 &&
7189 !pmap_try_insert_pv_entry(pmap, va, m, lockp)) {
7191 pmap_abort_ptp(pmap, va, mpte);
7196 * Increment counters
7198 pmap_resident_count_inc(pmap, 1);
7200 newpte = VM_PAGE_TO_PHYS(m) | PG_V |
7201 pmap_cache_bits(pmap, m->md.pat_mode, 0);
7202 if ((m->oflags & VPO_UNMANAGED) == 0)
7203 newpte |= PG_MANAGED;
7204 if ((prot & VM_PROT_EXECUTE) == 0)
7206 if (va < VM_MAXUSER_ADDRESS)
7207 newpte |= PG_U | pmap_pkru_get(pmap, va);
7208 pte_store(pte, newpte);
7213 * Make a temporary mapping for a physical address. This is only intended
7214 * to be used for panic dumps.
7217 pmap_kenter_temporary(vm_paddr_t pa, int i)
7221 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
7222 pmap_kenter(va, pa);
7224 return ((void *)crashdumpmap);
7228 * This code maps large physical mmap regions into the
7229 * processor address space. Note that some shortcuts
7230 * are taken, but the code works.
7233 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
7234 vm_pindex_t pindex, vm_size_t size)
7237 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
7238 vm_paddr_t pa, ptepa;
7242 PG_A = pmap_accessed_bit(pmap);
7243 PG_M = pmap_modified_bit(pmap);
7244 PG_V = pmap_valid_bit(pmap);
7245 PG_RW = pmap_rw_bit(pmap);
7247 VM_OBJECT_ASSERT_WLOCKED(object);
7248 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
7249 ("pmap_object_init_pt: non-device object"));
7250 if ((addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) {
7251 if (!pmap_ps_enabled(pmap))
7253 if (!vm_object_populate(object, pindex, pindex + atop(size)))
7255 p = vm_page_lookup(object, pindex);
7256 KASSERT(p->valid == VM_PAGE_BITS_ALL,
7257 ("pmap_object_init_pt: invalid page %p", p));
7258 pat_mode = p->md.pat_mode;
7261 * Abort the mapping if the first page is not physically
7262 * aligned to a 2MB page boundary.
7264 ptepa = VM_PAGE_TO_PHYS(p);
7265 if (ptepa & (NBPDR - 1))
7269 * Skip the first page. Abort the mapping if the rest of
7270 * the pages are not physically contiguous or have differing
7271 * memory attributes.
7273 p = TAILQ_NEXT(p, listq);
7274 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size;
7276 KASSERT(p->valid == VM_PAGE_BITS_ALL,
7277 ("pmap_object_init_pt: invalid page %p", p));
7278 if (pa != VM_PAGE_TO_PHYS(p) ||
7279 pat_mode != p->md.pat_mode)
7281 p = TAILQ_NEXT(p, listq);
7285 * Map using 2MB pages. Since "ptepa" is 2M aligned and
7286 * "size" is a multiple of 2M, adding the PAT setting to "pa"
7287 * will not affect the termination of this loop.
7290 for (pa = ptepa | pmap_cache_bits(pmap, pat_mode, 1);
7291 pa < ptepa + size; pa += NBPDR) {
7292 pde = pmap_alloc_pde(pmap, addr, &pdpg, NULL);
7295 * The creation of mappings below is only an
7296 * optimization. If a page directory page
7297 * cannot be allocated without blocking,
7298 * continue on to the next mapping rather than
7304 if ((*pde & PG_V) == 0) {
7305 pde_store(pde, pa | PG_PS | PG_M | PG_A |
7306 PG_U | PG_RW | PG_V);
7307 pmap_resident_count_inc(pmap, NBPDR / PAGE_SIZE);
7308 atomic_add_long(&pmap_pde_mappings, 1);
7310 /* Continue on if the PDE is already valid. */
7312 KASSERT(pdpg->ref_count > 0,
7313 ("pmap_object_init_pt: missing reference "
7314 "to page directory page, va: 0x%lx", addr));
7323 * Clear the wired attribute from the mappings for the specified range of
7324 * addresses in the given pmap. Every valid mapping within that range
7325 * must have the wired attribute set. In contrast, invalid mappings
7326 * cannot have the wired attribute set, so they are ignored.
7328 * The wired attribute of the page table entry is not a hardware
7329 * feature, so there is no need to invalidate any TLB entries.
7330 * Since pmap_demote_pde() for the wired entry must never fail,
7331 * pmap_delayed_invl_start()/finish() calls around the
7332 * function are not needed.
7335 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
7337 vm_offset_t va_next;
7338 pml4_entry_t *pml4e;
7341 pt_entry_t *pte, PG_V, PG_G;
7343 PG_V = pmap_valid_bit(pmap);
7344 PG_G = pmap_global_bit(pmap);
7346 for (; sva < eva; sva = va_next) {
7347 pml4e = pmap_pml4e(pmap, sva);
7348 if (pml4e == NULL || (*pml4e & PG_V) == 0) {
7349 va_next = (sva + NBPML4) & ~PML4MASK;
7355 va_next = (sva + NBPDP) & ~PDPMASK;
7358 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
7359 if ((*pdpe & PG_V) == 0)
7361 if ((*pdpe & PG_PS) != 0) {
7362 KASSERT(va_next <= eva,
7363 ("partial update of non-transparent 1G mapping "
7364 "pdpe %#lx sva %#lx eva %#lx va_next %#lx",
7365 *pdpe, sva, eva, va_next));
7366 MPASS(pmap != kernel_pmap); /* XXXKIB */
7367 MPASS((*pdpe & (PG_MANAGED | PG_G)) == 0);
7368 atomic_clear_long(pdpe, PG_W);
7369 pmap->pm_stats.wired_count -= NBPDP / PAGE_SIZE;
7373 va_next = (sva + NBPDR) & ~PDRMASK;
7376 pde = pmap_pdpe_to_pde(pdpe, sva);
7377 if ((*pde & PG_V) == 0)
7379 if ((*pde & PG_PS) != 0) {
7380 if ((*pde & PG_W) == 0)
7381 panic("pmap_unwire: pde %#jx is missing PG_W",
7385 * Are we unwiring the entire large page? If not,
7386 * demote the mapping and fall through.
7388 if (sva + NBPDR == va_next && eva >= va_next) {
7389 atomic_clear_long(pde, PG_W);
7390 pmap->pm_stats.wired_count -= NBPDR /
7393 } else if (!pmap_demote_pde(pmap, pde, sva))
7394 panic("pmap_unwire: demotion failed");
7398 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
7400 if ((*pte & PG_V) == 0)
7402 if ((*pte & PG_W) == 0)
7403 panic("pmap_unwire: pte %#jx is missing PG_W",
7407 * PG_W must be cleared atomically. Although the pmap
7408 * lock synchronizes access to PG_W, another processor
7409 * could be setting PG_M and/or PG_A concurrently.
7411 atomic_clear_long(pte, PG_W);
7412 pmap->pm_stats.wired_count--;
7419 * Copy the range specified by src_addr/len
7420 * from the source map to the range dst_addr/len
7421 * in the destination map.
7423 * This routine is only advisory and need not do anything.
7426 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
7427 vm_offset_t src_addr)
7429 struct rwlock *lock;
7430 pml4_entry_t *pml4e;
7432 pd_entry_t *pde, srcptepaddr;
7433 pt_entry_t *dst_pte, PG_A, PG_M, PG_V, ptetemp, *src_pte;
7434 vm_offset_t addr, end_addr, va_next;
7435 vm_page_t dst_pdpg, dstmpte, srcmpte;
7437 if (dst_addr != src_addr)
7440 if (dst_pmap->pm_type != src_pmap->pm_type)
7444 * EPT page table entries that require emulation of A/D bits are
7445 * sensitive to clearing the PG_A bit (aka EPT_PG_READ). Although
7446 * we clear PG_M (aka EPT_PG_WRITE) concomitantly, the PG_U bit
7447 * (aka EPT_PG_EXECUTE) could still be set. Since some EPT
7448 * implementations flag an EPT misconfiguration for exec-only
7449 * mappings we skip this function entirely for emulated pmaps.
7451 if (pmap_emulate_ad_bits(dst_pmap))
7454 end_addr = src_addr + len;
7456 if (dst_pmap < src_pmap) {
7457 PMAP_LOCK(dst_pmap);
7458 PMAP_LOCK(src_pmap);
7460 PMAP_LOCK(src_pmap);
7461 PMAP_LOCK(dst_pmap);
7464 PG_A = pmap_accessed_bit(dst_pmap);
7465 PG_M = pmap_modified_bit(dst_pmap);
7466 PG_V = pmap_valid_bit(dst_pmap);
7468 for (addr = src_addr; addr < end_addr; addr = va_next) {
7469 KASSERT(addr < UPT_MIN_ADDRESS,
7470 ("pmap_copy: invalid to pmap_copy page tables"));
7472 pml4e = pmap_pml4e(src_pmap, addr);
7473 if (pml4e == NULL || (*pml4e & PG_V) == 0) {
7474 va_next = (addr + NBPML4) & ~PML4MASK;
7480 va_next = (addr + NBPDP) & ~PDPMASK;
7483 pdpe = pmap_pml4e_to_pdpe(pml4e, addr);
7484 if ((*pdpe & PG_V) == 0)
7486 if ((*pdpe & PG_PS) != 0) {
7487 KASSERT(va_next <= end_addr,
7488 ("partial update of non-transparent 1G mapping "
7489 "pdpe %#lx sva %#lx eva %#lx va_next %#lx",
7490 *pdpe, addr, end_addr, va_next));
7491 MPASS((addr & PDPMASK) == 0);
7492 MPASS((*pdpe & PG_MANAGED) == 0);
7493 srcptepaddr = *pdpe;
7494 pdpe = pmap_pdpe(dst_pmap, addr);
7496 if (_pmap_allocpte(dst_pmap,
7497 pmap_pml4e_pindex(addr), NULL, addr) ==
7500 pdpe = pmap_pdpe(dst_pmap, addr);
7502 pml4e = pmap_pml4e(dst_pmap, addr);
7503 dst_pdpg = PHYS_TO_VM_PAGE(*pml4e & PG_FRAME);
7504 dst_pdpg->ref_count++;
7507 ("1G mapping present in dst pmap "
7508 "pdpe %#lx sva %#lx eva %#lx va_next %#lx",
7509 *pdpe, addr, end_addr, va_next));
7510 *pdpe = srcptepaddr & ~PG_W;
7511 pmap_resident_count_inc(dst_pmap, NBPDP / PAGE_SIZE);
7515 va_next = (addr + NBPDR) & ~PDRMASK;
7519 pde = pmap_pdpe_to_pde(pdpe, addr);
7521 if (srcptepaddr == 0)
7524 if (srcptepaddr & PG_PS) {
7525 if ((addr & PDRMASK) != 0 || addr + NBPDR > end_addr)
7527 pde = pmap_alloc_pde(dst_pmap, addr, &dst_pdpg, NULL);
7530 if (*pde == 0 && ((srcptepaddr & PG_MANAGED) == 0 ||
7531 pmap_pv_insert_pde(dst_pmap, addr, srcptepaddr,
7532 PMAP_ENTER_NORECLAIM, &lock))) {
7533 *pde = srcptepaddr & ~PG_W;
7534 pmap_resident_count_inc(dst_pmap, NBPDR /
7536 atomic_add_long(&pmap_pde_mappings, 1);
7538 pmap_abort_ptp(dst_pmap, addr, dst_pdpg);
7542 srcptepaddr &= PG_FRAME;
7543 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr);
7544 KASSERT(srcmpte->ref_count > 0,
7545 ("pmap_copy: source page table page is unused"));
7547 if (va_next > end_addr)
7550 src_pte = (pt_entry_t *)PHYS_TO_DMAP(srcptepaddr);
7551 src_pte = &src_pte[pmap_pte_index(addr)];
7553 for (; addr < va_next; addr += PAGE_SIZE, src_pte++) {
7557 * We only virtual copy managed pages.
7559 if ((ptetemp & PG_MANAGED) == 0)
7562 if (dstmpte != NULL) {
7563 KASSERT(dstmpte->pindex ==
7564 pmap_pde_pindex(addr),
7565 ("dstmpte pindex/addr mismatch"));
7566 dstmpte->ref_count++;
7567 } else if ((dstmpte = pmap_allocpte(dst_pmap, addr,
7570 dst_pte = (pt_entry_t *)
7571 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dstmpte));
7572 dst_pte = &dst_pte[pmap_pte_index(addr)];
7573 if (*dst_pte == 0 &&
7574 pmap_try_insert_pv_entry(dst_pmap, addr,
7575 PHYS_TO_VM_PAGE(ptetemp & PG_FRAME), &lock)) {
7577 * Clear the wired, modified, and accessed
7578 * (referenced) bits during the copy.
7580 *dst_pte = ptetemp & ~(PG_W | PG_M | PG_A);
7581 pmap_resident_count_inc(dst_pmap, 1);
7583 pmap_abort_ptp(dst_pmap, addr, dstmpte);
7586 /* Have we copied all of the valid mappings? */
7587 if (dstmpte->ref_count >= srcmpte->ref_count)
7594 PMAP_UNLOCK(src_pmap);
7595 PMAP_UNLOCK(dst_pmap);
7599 pmap_vmspace_copy(pmap_t dst_pmap, pmap_t src_pmap)
7603 if (dst_pmap->pm_type != src_pmap->pm_type ||
7604 dst_pmap->pm_type != PT_X86 ||
7605 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0)
7608 if (dst_pmap < src_pmap) {
7609 PMAP_LOCK(dst_pmap);
7610 PMAP_LOCK(src_pmap);
7612 PMAP_LOCK(src_pmap);
7613 PMAP_LOCK(dst_pmap);
7615 error = pmap_pkru_copy(dst_pmap, src_pmap);
7616 /* Clean up partial copy on failure due to no memory. */
7617 if (error == ENOMEM)
7618 pmap_pkru_deassign_all(dst_pmap);
7619 PMAP_UNLOCK(src_pmap);
7620 PMAP_UNLOCK(dst_pmap);
7621 if (error != ENOMEM)
7629 * Zero the specified hardware page.
7632 pmap_zero_page(vm_page_t m)
7634 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
7636 pagezero((void *)va);
7640 * Zero an an area within a single hardware page. off and size must not
7641 * cover an area beyond a single hardware page.
7644 pmap_zero_page_area(vm_page_t m, int off, int size)
7646 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
7648 if (off == 0 && size == PAGE_SIZE)
7649 pagezero((void *)va);
7651 bzero((char *)va + off, size);
7655 * Copy 1 specified hardware page to another.
7658 pmap_copy_page(vm_page_t msrc, vm_page_t mdst)
7660 vm_offset_t src = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(msrc));
7661 vm_offset_t dst = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mdst));
7663 pagecopy((void *)src, (void *)dst);
7666 int unmapped_buf_allowed = 1;
7669 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
7670 vm_offset_t b_offset, int xfersize)
7674 vm_offset_t vaddr[2], a_pg_offset, b_pg_offset;
7678 while (xfersize > 0) {
7679 a_pg_offset = a_offset & PAGE_MASK;
7680 pages[0] = ma[a_offset >> PAGE_SHIFT];
7681 b_pg_offset = b_offset & PAGE_MASK;
7682 pages[1] = mb[b_offset >> PAGE_SHIFT];
7683 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
7684 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
7685 mapped = pmap_map_io_transient(pages, vaddr, 2, FALSE);
7686 a_cp = (char *)vaddr[0] + a_pg_offset;
7687 b_cp = (char *)vaddr[1] + b_pg_offset;
7688 bcopy(a_cp, b_cp, cnt);
7689 if (__predict_false(mapped))
7690 pmap_unmap_io_transient(pages, vaddr, 2, FALSE);
7698 * Returns true if the pmap's pv is one of the first
7699 * 16 pvs linked to from this page. This count may
7700 * be changed upwards or downwards in the future; it
7701 * is only necessary that true be returned for a small
7702 * subset of pmaps for proper page aging.
7705 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
7707 struct md_page *pvh;
7708 struct rwlock *lock;
7713 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
7714 ("pmap_page_exists_quick: page %p is not managed", m));
7716 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
7718 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
7719 if (PV_PMAP(pv) == pmap) {
7727 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
7728 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
7729 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
7730 if (PV_PMAP(pv) == pmap) {
7744 * pmap_page_wired_mappings:
7746 * Return the number of managed mappings to the given physical page
7750 pmap_page_wired_mappings(vm_page_t m)
7752 struct rwlock *lock;
7753 struct md_page *pvh;
7757 int count, md_gen, pvh_gen;
7759 if ((m->oflags & VPO_UNMANAGED) != 0)
7761 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
7765 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
7767 if (!PMAP_TRYLOCK(pmap)) {
7768 md_gen = m->md.pv_gen;
7772 if (md_gen != m->md.pv_gen) {
7777 pte = pmap_pte(pmap, pv->pv_va);
7778 if ((*pte & PG_W) != 0)
7782 if ((m->flags & PG_FICTITIOUS) == 0) {
7783 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
7784 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
7786 if (!PMAP_TRYLOCK(pmap)) {
7787 md_gen = m->md.pv_gen;
7788 pvh_gen = pvh->pv_gen;
7792 if (md_gen != m->md.pv_gen ||
7793 pvh_gen != pvh->pv_gen) {
7798 pte = pmap_pde(pmap, pv->pv_va);
7799 if ((*pte & PG_W) != 0)
7809 * Returns TRUE if the given page is mapped individually or as part of
7810 * a 2mpage. Otherwise, returns FALSE.
7813 pmap_page_is_mapped(vm_page_t m)
7815 struct rwlock *lock;
7818 if ((m->oflags & VPO_UNMANAGED) != 0)
7820 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
7822 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
7823 ((m->flags & PG_FICTITIOUS) == 0 &&
7824 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
7830 * Destroy all managed, non-wired mappings in the given user-space
7831 * pmap. This pmap cannot be active on any processor besides the
7834 * This function cannot be applied to the kernel pmap. Moreover, it
7835 * is not intended for general use. It is only to be used during
7836 * process termination. Consequently, it can be implemented in ways
7837 * that make it faster than pmap_remove(). First, it can more quickly
7838 * destroy mappings by iterating over the pmap's collection of PV
7839 * entries, rather than searching the page table. Second, it doesn't
7840 * have to test and clear the page table entries atomically, because
7841 * no processor is currently accessing the user address space. In
7842 * particular, a page table entry's dirty bit won't change state once
7843 * this function starts.
7845 * Although this function destroys all of the pmap's managed,
7846 * non-wired mappings, it can delay and batch the invalidation of TLB
7847 * entries without calling pmap_delayed_invl_start() and
7848 * pmap_delayed_invl_finish(). Because the pmap is not active on
7849 * any other processor, none of these TLB entries will ever be used
7850 * before their eventual invalidation. Consequently, there is no need
7851 * for either pmap_remove_all() or pmap_remove_write() to wait for
7852 * that eventual TLB invalidation.
7855 pmap_remove_pages(pmap_t pmap)
7858 pt_entry_t *pte, tpte;
7859 pt_entry_t PG_M, PG_RW, PG_V;
7860 struct spglist free;
7861 struct pv_chunklist free_chunks[PMAP_MEMDOM];
7862 vm_page_t m, mpte, mt;
7864 struct md_page *pvh;
7865 struct pv_chunk *pc, *npc;
7866 struct rwlock *lock;
7868 uint64_t inuse, bitmask;
7869 int allfree, field, freed, i, idx;
7870 boolean_t superpage;
7874 * Assert that the given pmap is only active on the current
7875 * CPU. Unfortunately, we cannot block another CPU from
7876 * activating the pmap while this function is executing.
7878 KASSERT(pmap == PCPU_GET(curpmap), ("non-current pmap %p", pmap));
7881 cpuset_t other_cpus;
7883 other_cpus = all_cpus;
7885 CPU_CLR(PCPU_GET(cpuid), &other_cpus);
7886 CPU_AND(&other_cpus, &pmap->pm_active);
7888 KASSERT(CPU_EMPTY(&other_cpus), ("pmap active %p", pmap));
7893 PG_M = pmap_modified_bit(pmap);
7894 PG_V = pmap_valid_bit(pmap);
7895 PG_RW = pmap_rw_bit(pmap);
7897 for (i = 0; i < PMAP_MEMDOM; i++)
7898 TAILQ_INIT(&free_chunks[i]);
7901 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
7904 for (field = 0; field < _NPCM; field++) {
7905 inuse = ~pc->pc_map[field] & pc_freemask[field];
7906 while (inuse != 0) {
7908 bitmask = 1UL << bit;
7909 idx = field * 64 + bit;
7910 pv = &pc->pc_pventry[idx];
7913 pte = pmap_pdpe(pmap, pv->pv_va);
7915 pte = pmap_pdpe_to_pde(pte, pv->pv_va);
7917 if ((tpte & (PG_PS | PG_V)) == PG_V) {
7920 pte = (pt_entry_t *)PHYS_TO_DMAP(tpte &
7922 pte = &pte[pmap_pte_index(pv->pv_va)];
7926 * Keep track whether 'tpte' is a
7927 * superpage explicitly instead of
7928 * relying on PG_PS being set.
7930 * This is because PG_PS is numerically
7931 * identical to PG_PTE_PAT and thus a
7932 * regular page could be mistaken for
7938 if ((tpte & PG_V) == 0) {
7939 panic("bad pte va %lx pte %lx",
7944 * We cannot remove wired pages from a process' mapping at this time
7952 pa = tpte & PG_PS_FRAME;
7954 pa = tpte & PG_FRAME;
7956 m = PHYS_TO_VM_PAGE(pa);
7957 KASSERT(m->phys_addr == pa,
7958 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
7959 m, (uintmax_t)m->phys_addr,
7962 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
7963 m < &vm_page_array[vm_page_array_size],
7964 ("pmap_remove_pages: bad tpte %#jx",
7970 * Update the vm_page_t clean/reference bits.
7972 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
7974 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
7980 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(&lock, m);
7983 pc->pc_map[field] |= bitmask;
7985 pmap_resident_count_dec(pmap, NBPDR / PAGE_SIZE);
7986 pvh = pa_to_pvh(tpte & PG_PS_FRAME);
7987 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
7989 if (TAILQ_EMPTY(&pvh->pv_list)) {
7990 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
7991 if ((mt->a.flags & PGA_WRITEABLE) != 0 &&
7992 TAILQ_EMPTY(&mt->md.pv_list))
7993 vm_page_aflag_clear(mt, PGA_WRITEABLE);
7995 mpte = pmap_remove_pt_page(pmap, pv->pv_va);
7997 KASSERT(mpte->valid == VM_PAGE_BITS_ALL,
7998 ("pmap_remove_pages: pte page not promoted"));
7999 pmap_resident_count_dec(pmap, 1);
8000 KASSERT(mpte->ref_count == NPTEPG,
8001 ("pmap_remove_pages: pte page reference count error"));
8002 mpte->ref_count = 0;
8003 pmap_add_delayed_free_list(mpte, &free, FALSE);
8006 pmap_resident_count_dec(pmap, 1);
8007 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
8009 if ((m->a.flags & PGA_WRITEABLE) != 0 &&
8010 TAILQ_EMPTY(&m->md.pv_list) &&
8011 (m->flags & PG_FICTITIOUS) == 0) {
8012 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
8013 if (TAILQ_EMPTY(&pvh->pv_list))
8014 vm_page_aflag_clear(m, PGA_WRITEABLE);
8017 pmap_unuse_pt(pmap, pv->pv_va, ptepde, &free);
8021 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
8022 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
8023 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
8025 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
8026 TAILQ_INSERT_TAIL(&free_chunks[pc_to_domain(pc)], pc, pc_list);
8031 pmap_invalidate_all(pmap);
8032 pmap_pkru_deassign_all(pmap);
8033 free_pv_chunk_batch((struct pv_chunklist *)&free_chunks);
8035 vm_page_free_pages_toq(&free, true);
8039 pmap_page_test_mappings(vm_page_t m, boolean_t accessed, boolean_t modified)
8041 struct rwlock *lock;
8043 struct md_page *pvh;
8044 pt_entry_t *pte, mask;
8045 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
8047 int md_gen, pvh_gen;
8051 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
8054 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
8056 if (!PMAP_TRYLOCK(pmap)) {
8057 md_gen = m->md.pv_gen;
8061 if (md_gen != m->md.pv_gen) {
8066 pte = pmap_pte(pmap, pv->pv_va);
8069 PG_M = pmap_modified_bit(pmap);
8070 PG_RW = pmap_rw_bit(pmap);
8071 mask |= PG_RW | PG_M;
8074 PG_A = pmap_accessed_bit(pmap);
8075 PG_V = pmap_valid_bit(pmap);
8076 mask |= PG_V | PG_A;
8078 rv = (*pte & mask) == mask;
8083 if ((m->flags & PG_FICTITIOUS) == 0) {
8084 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
8085 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
8087 if (!PMAP_TRYLOCK(pmap)) {
8088 md_gen = m->md.pv_gen;
8089 pvh_gen = pvh->pv_gen;
8093 if (md_gen != m->md.pv_gen ||
8094 pvh_gen != pvh->pv_gen) {
8099 pte = pmap_pde(pmap, pv->pv_va);
8102 PG_M = pmap_modified_bit(pmap);
8103 PG_RW = pmap_rw_bit(pmap);
8104 mask |= PG_RW | PG_M;
8107 PG_A = pmap_accessed_bit(pmap);
8108 PG_V = pmap_valid_bit(pmap);
8109 mask |= PG_V | PG_A;
8111 rv = (*pte & mask) == mask;
8125 * Return whether or not the specified physical page was modified
8126 * in any physical maps.
8129 pmap_is_modified(vm_page_t m)
8132 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
8133 ("pmap_is_modified: page %p is not managed", m));
8136 * If the page is not busied then this check is racy.
8138 if (!pmap_page_is_write_mapped(m))
8140 return (pmap_page_test_mappings(m, FALSE, TRUE));
8144 * pmap_is_prefaultable:
8146 * Return whether or not the specified virtual address is eligible
8150 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
8153 pt_entry_t *pte, PG_V;
8156 PG_V = pmap_valid_bit(pmap);
8159 pde = pmap_pde(pmap, addr);
8160 if (pde != NULL && (*pde & (PG_PS | PG_V)) == PG_V) {
8161 pte = pmap_pde_to_pte(pde, addr);
8162 rv = (*pte & PG_V) == 0;
8169 * pmap_is_referenced:
8171 * Return whether or not the specified physical page was referenced
8172 * in any physical maps.
8175 pmap_is_referenced(vm_page_t m)
8178 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
8179 ("pmap_is_referenced: page %p is not managed", m));
8180 return (pmap_page_test_mappings(m, TRUE, FALSE));
8184 * Clear the write and modified bits in each of the given page's mappings.
8187 pmap_remove_write(vm_page_t m)
8189 struct md_page *pvh;
8191 struct rwlock *lock;
8192 pv_entry_t next_pv, pv;
8194 pt_entry_t oldpte, *pte, PG_M, PG_RW;
8196 int pvh_gen, md_gen;
8198 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
8199 ("pmap_remove_write: page %p is not managed", m));
8201 vm_page_assert_busied(m);
8202 if (!pmap_page_is_write_mapped(m))
8205 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
8206 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
8207 pa_to_pvh(VM_PAGE_TO_PHYS(m));
8210 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
8212 if (!PMAP_TRYLOCK(pmap)) {
8213 pvh_gen = pvh->pv_gen;
8217 if (pvh_gen != pvh->pv_gen) {
8223 PG_RW = pmap_rw_bit(pmap);
8225 pde = pmap_pde(pmap, va);
8226 if ((*pde & PG_RW) != 0)
8227 (void)pmap_demote_pde_locked(pmap, pde, va, &lock);
8228 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
8229 ("inconsistent pv lock %p %p for page %p",
8230 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
8233 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
8235 if (!PMAP_TRYLOCK(pmap)) {
8236 pvh_gen = pvh->pv_gen;
8237 md_gen = m->md.pv_gen;
8241 if (pvh_gen != pvh->pv_gen ||
8242 md_gen != m->md.pv_gen) {
8248 PG_M = pmap_modified_bit(pmap);
8249 PG_RW = pmap_rw_bit(pmap);
8250 pde = pmap_pde(pmap, pv->pv_va);
8251 KASSERT((*pde & PG_PS) == 0,
8252 ("pmap_remove_write: found a 2mpage in page %p's pv list",
8254 pte = pmap_pde_to_pte(pde, pv->pv_va);
8257 if (oldpte & PG_RW) {
8258 if (!atomic_cmpset_long(pte, oldpte, oldpte &
8261 if ((oldpte & PG_M) != 0)
8263 pmap_invalidate_page(pmap, pv->pv_va);
8268 vm_page_aflag_clear(m, PGA_WRITEABLE);
8269 pmap_delayed_invl_wait(m);
8272 static __inline boolean_t
8273 safe_to_clear_referenced(pmap_t pmap, pt_entry_t pte)
8276 if (!pmap_emulate_ad_bits(pmap))
8279 KASSERT(pmap->pm_type == PT_EPT, ("invalid pm_type %d", pmap->pm_type));
8282 * XWR = 010 or 110 will cause an unconditional EPT misconfiguration
8283 * so we don't let the referenced (aka EPT_PG_READ) bit to be cleared
8284 * if the EPT_PG_WRITE bit is set.
8286 if ((pte & EPT_PG_WRITE) != 0)
8290 * XWR = 100 is allowed only if the PMAP_SUPPORTS_EXEC_ONLY is set.
8292 if ((pte & EPT_PG_EXECUTE) == 0 ||
8293 ((pmap->pm_flags & PMAP_SUPPORTS_EXEC_ONLY) != 0))
8300 * pmap_ts_referenced:
8302 * Return a count of reference bits for a page, clearing those bits.
8303 * It is not necessary for every reference bit to be cleared, but it
8304 * is necessary that 0 only be returned when there are truly no
8305 * reference bits set.
8307 * As an optimization, update the page's dirty field if a modified bit is
8308 * found while counting reference bits. This opportunistic update can be
8309 * performed at low cost and can eliminate the need for some future calls
8310 * to pmap_is_modified(). However, since this function stops after
8311 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
8312 * dirty pages. Those dirty pages will only be detected by a future call
8313 * to pmap_is_modified().
8315 * A DI block is not needed within this function, because
8316 * invalidations are performed before the PV list lock is
8320 pmap_ts_referenced(vm_page_t m)
8322 struct md_page *pvh;
8325 struct rwlock *lock;
8326 pd_entry_t oldpde, *pde;
8327 pt_entry_t *pte, PG_A, PG_M, PG_RW;
8330 int cleared, md_gen, not_cleared, pvh_gen;
8331 struct spglist free;
8334 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
8335 ("pmap_ts_referenced: page %p is not managed", m));
8338 pa = VM_PAGE_TO_PHYS(m);
8339 lock = PHYS_TO_PV_LIST_LOCK(pa);
8340 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : pa_to_pvh(pa);
8344 if ((pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
8345 goto small_mappings;
8351 if (!PMAP_TRYLOCK(pmap)) {
8352 pvh_gen = pvh->pv_gen;
8356 if (pvh_gen != pvh->pv_gen) {
8361 PG_A = pmap_accessed_bit(pmap);
8362 PG_M = pmap_modified_bit(pmap);
8363 PG_RW = pmap_rw_bit(pmap);
8365 pde = pmap_pde(pmap, pv->pv_va);
8367 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
8369 * Although "oldpde" is mapping a 2MB page, because
8370 * this function is called at a 4KB page granularity,
8371 * we only update the 4KB page under test.
8375 if ((oldpde & PG_A) != 0) {
8377 * Since this reference bit is shared by 512 4KB
8378 * pages, it should not be cleared every time it is
8379 * tested. Apply a simple "hash" function on the
8380 * physical page number, the virtual superpage number,
8381 * and the pmap address to select one 4KB page out of
8382 * the 512 on which testing the reference bit will
8383 * result in clearing that reference bit. This
8384 * function is designed to avoid the selection of the
8385 * same 4KB page for every 2MB page mapping.
8387 * On demotion, a mapping that hasn't been referenced
8388 * is simply destroyed. To avoid the possibility of a
8389 * subsequent page fault on a demoted wired mapping,
8390 * always leave its reference bit set. Moreover,
8391 * since the superpage is wired, the current state of
8392 * its reference bit won't affect page replacement.
8394 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> PDRSHIFT) ^
8395 (uintptr_t)pmap) & (NPTEPG - 1)) == 0 &&
8396 (oldpde & PG_W) == 0) {
8397 if (safe_to_clear_referenced(pmap, oldpde)) {
8398 atomic_clear_long(pde, PG_A);
8399 pmap_invalidate_page(pmap, pv->pv_va);
8401 } else if (pmap_demote_pde_locked(pmap, pde,
8402 pv->pv_va, &lock)) {
8404 * Remove the mapping to a single page
8405 * so that a subsequent access may
8406 * repromote. Since the underlying
8407 * page table page is fully populated,
8408 * this removal never frees a page
8412 va += VM_PAGE_TO_PHYS(m) - (oldpde &
8414 pte = pmap_pde_to_pte(pde, va);
8415 pmap_remove_pte(pmap, pte, va, *pde,
8417 pmap_invalidate_page(pmap, va);
8423 * The superpage mapping was removed
8424 * entirely and therefore 'pv' is no
8432 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
8433 ("inconsistent pv lock %p %p for page %p",
8434 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
8439 /* Rotate the PV list if it has more than one entry. */
8440 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
8441 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
8442 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
8445 if (cleared + not_cleared >= PMAP_TS_REFERENCED_MAX)
8447 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
8449 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
8456 if (!PMAP_TRYLOCK(pmap)) {
8457 pvh_gen = pvh->pv_gen;
8458 md_gen = m->md.pv_gen;
8462 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
8467 PG_A = pmap_accessed_bit(pmap);
8468 PG_M = pmap_modified_bit(pmap);
8469 PG_RW = pmap_rw_bit(pmap);
8470 pde = pmap_pde(pmap, pv->pv_va);
8471 KASSERT((*pde & PG_PS) == 0,
8472 ("pmap_ts_referenced: found a 2mpage in page %p's pv list",
8474 pte = pmap_pde_to_pte(pde, pv->pv_va);
8475 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
8477 if ((*pte & PG_A) != 0) {
8478 if (safe_to_clear_referenced(pmap, *pte)) {
8479 atomic_clear_long(pte, PG_A);
8480 pmap_invalidate_page(pmap, pv->pv_va);
8482 } else if ((*pte & PG_W) == 0) {
8484 * Wired pages cannot be paged out so
8485 * doing accessed bit emulation for
8486 * them is wasted effort. We do the
8487 * hard work for unwired pages only.
8489 pmap_remove_pte(pmap, pte, pv->pv_va,
8490 *pde, &free, &lock);
8491 pmap_invalidate_page(pmap, pv->pv_va);
8496 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
8497 ("inconsistent pv lock %p %p for page %p",
8498 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
8503 /* Rotate the PV list if it has more than one entry. */
8504 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
8505 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
8506 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
8509 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && cleared +
8510 not_cleared < PMAP_TS_REFERENCED_MAX);
8513 vm_page_free_pages_toq(&free, true);
8514 return (cleared + not_cleared);
8518 * Apply the given advice to the specified range of addresses within the
8519 * given pmap. Depending on the advice, clear the referenced and/or
8520 * modified flags in each mapping and set the mapped page's dirty field.
8523 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
8525 struct rwlock *lock;
8526 pml4_entry_t *pml4e;
8528 pd_entry_t oldpde, *pde;
8529 pt_entry_t *pte, PG_A, PG_G, PG_M, PG_RW, PG_V;
8530 vm_offset_t va, va_next;
8534 if (advice != MADV_DONTNEED && advice != MADV_FREE)
8538 * A/D bit emulation requires an alternate code path when clearing
8539 * the modified and accessed bits below. Since this function is
8540 * advisory in nature we skip it entirely for pmaps that require
8541 * A/D bit emulation.
8543 if (pmap_emulate_ad_bits(pmap))
8546 PG_A = pmap_accessed_bit(pmap);
8547 PG_G = pmap_global_bit(pmap);
8548 PG_M = pmap_modified_bit(pmap);
8549 PG_V = pmap_valid_bit(pmap);
8550 PG_RW = pmap_rw_bit(pmap);
8552 pmap_delayed_invl_start();
8554 for (; sva < eva; sva = va_next) {
8555 pml4e = pmap_pml4e(pmap, sva);
8556 if (pml4e == NULL || (*pml4e & PG_V) == 0) {
8557 va_next = (sva + NBPML4) & ~PML4MASK;
8563 va_next = (sva + NBPDP) & ~PDPMASK;
8566 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
8567 if ((*pdpe & PG_V) == 0)
8569 if ((*pdpe & PG_PS) != 0) {
8570 KASSERT(va_next <= eva,
8571 ("partial update of non-transparent 1G mapping "
8572 "pdpe %#lx sva %#lx eva %#lx va_next %#lx",
8573 *pdpe, sva, eva, va_next));
8577 va_next = (sva + NBPDR) & ~PDRMASK;
8580 pde = pmap_pdpe_to_pde(pdpe, sva);
8582 if ((oldpde & PG_V) == 0)
8584 else if ((oldpde & PG_PS) != 0) {
8585 if ((oldpde & PG_MANAGED) == 0)
8588 if (!pmap_demote_pde_locked(pmap, pde, sva, &lock)) {
8593 * The large page mapping was destroyed.
8599 * Unless the page mappings are wired, remove the
8600 * mapping to a single page so that a subsequent
8601 * access may repromote. Choosing the last page
8602 * within the address range [sva, min(va_next, eva))
8603 * generally results in more repromotions. Since the
8604 * underlying page table page is fully populated, this
8605 * removal never frees a page table page.
8607 if ((oldpde & PG_W) == 0) {
8613 ("pmap_advise: no address gap"));
8614 pte = pmap_pde_to_pte(pde, va);
8615 KASSERT((*pte & PG_V) != 0,
8616 ("pmap_advise: invalid PTE"));
8617 pmap_remove_pte(pmap, pte, va, *pde, NULL,
8627 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
8629 if ((*pte & (PG_MANAGED | PG_V)) != (PG_MANAGED | PG_V))
8631 else if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
8632 if (advice == MADV_DONTNEED) {
8634 * Future calls to pmap_is_modified()
8635 * can be avoided by making the page
8638 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
8641 atomic_clear_long(pte, PG_M | PG_A);
8642 } else if ((*pte & PG_A) != 0)
8643 atomic_clear_long(pte, PG_A);
8647 if ((*pte & PG_G) != 0) {
8654 if (va != va_next) {
8655 pmap_invalidate_range(pmap, va, sva);
8660 pmap_invalidate_range(pmap, va, sva);
8663 pmap_invalidate_all(pmap);
8665 pmap_delayed_invl_finish();
8669 * Clear the modify bits on the specified physical page.
8672 pmap_clear_modify(vm_page_t m)
8674 struct md_page *pvh;
8676 pv_entry_t next_pv, pv;
8677 pd_entry_t oldpde, *pde;
8678 pt_entry_t *pte, PG_M, PG_RW;
8679 struct rwlock *lock;
8681 int md_gen, pvh_gen;
8683 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
8684 ("pmap_clear_modify: page %p is not managed", m));
8685 vm_page_assert_busied(m);
8687 if (!pmap_page_is_write_mapped(m))
8689 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
8690 pa_to_pvh(VM_PAGE_TO_PHYS(m));
8691 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
8694 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
8696 if (!PMAP_TRYLOCK(pmap)) {
8697 pvh_gen = pvh->pv_gen;
8701 if (pvh_gen != pvh->pv_gen) {
8706 PG_M = pmap_modified_bit(pmap);
8707 PG_RW = pmap_rw_bit(pmap);
8709 pde = pmap_pde(pmap, va);
8711 /* If oldpde has PG_RW set, then it also has PG_M set. */
8712 if ((oldpde & PG_RW) != 0 &&
8713 pmap_demote_pde_locked(pmap, pde, va, &lock) &&
8714 (oldpde & PG_W) == 0) {
8716 * Write protect the mapping to a single page so that
8717 * a subsequent write access may repromote.
8719 va += VM_PAGE_TO_PHYS(m) - (oldpde & PG_PS_FRAME);
8720 pte = pmap_pde_to_pte(pde, va);
8721 atomic_clear_long(pte, PG_M | PG_RW);
8723 pmap_invalidate_page(pmap, va);
8727 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
8729 if (!PMAP_TRYLOCK(pmap)) {
8730 md_gen = m->md.pv_gen;
8731 pvh_gen = pvh->pv_gen;
8735 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
8740 PG_M = pmap_modified_bit(pmap);
8741 PG_RW = pmap_rw_bit(pmap);
8742 pde = pmap_pde(pmap, pv->pv_va);
8743 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_modify: found"
8744 " a 2mpage in page %p's pv list", m));
8745 pte = pmap_pde_to_pte(pde, pv->pv_va);
8746 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
8747 atomic_clear_long(pte, PG_M);
8748 pmap_invalidate_page(pmap, pv->pv_va);
8756 * Miscellaneous support routines follow
8759 /* Adjust the properties for a leaf page table entry. */
8760 static __inline void
8761 pmap_pte_props(pt_entry_t *pte, u_long bits, u_long mask)
8765 opte = *(u_long *)pte;
8767 npte = opte & ~mask;
8769 } while (npte != opte && !atomic_fcmpset_long((u_long *)pte, &opte,
8774 * Map a set of physical memory pages into the kernel virtual
8775 * address space. Return a pointer to where it is mapped. This
8776 * routine is intended to be used for mapping device memory,
8780 pmap_mapdev_internal(vm_paddr_t pa, vm_size_t size, int mode, int flags)
8782 struct pmap_preinit_mapping *ppim;
8783 vm_offset_t va, offset;
8787 offset = pa & PAGE_MASK;
8788 size = round_page(offset + size);
8789 pa = trunc_page(pa);
8791 if (!pmap_initialized) {
8793 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
8794 ppim = pmap_preinit_mapping + i;
8795 if (ppim->va == 0) {
8799 ppim->va = virtual_avail;
8800 virtual_avail += size;
8806 panic("%s: too many preinit mappings", __func__);
8809 * If we have a preinit mapping, re-use it.
8811 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
8812 ppim = pmap_preinit_mapping + i;
8813 if (ppim->pa == pa && ppim->sz == size &&
8814 (ppim->mode == mode ||
8815 (flags & MAPDEV_SETATTR) == 0))
8816 return ((void *)(ppim->va + offset));
8819 * If the specified range of physical addresses fits within
8820 * the direct map window, use the direct map.
8822 if (pa < dmaplimit && pa + size <= dmaplimit) {
8823 va = PHYS_TO_DMAP(pa);
8824 if ((flags & MAPDEV_SETATTR) != 0) {
8825 PMAP_LOCK(kernel_pmap);
8826 i = pmap_change_props_locked(va, size,
8827 PROT_NONE, mode, flags);
8828 PMAP_UNLOCK(kernel_pmap);
8832 return ((void *)(va + offset));
8834 va = kva_alloc(size);
8836 panic("%s: Couldn't allocate KVA", __func__);
8838 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
8839 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode);
8840 pmap_invalidate_range(kernel_pmap, va, va + tmpsize);
8841 if ((flags & MAPDEV_FLUSHCACHE) != 0)
8842 pmap_invalidate_cache_range(va, va + tmpsize);
8843 return ((void *)(va + offset));
8847 pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode)
8850 return (pmap_mapdev_internal(pa, size, mode, MAPDEV_FLUSHCACHE |
8855 pmap_mapdev(vm_paddr_t pa, vm_size_t size)
8858 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE));
8862 pmap_mapdev_pciecfg(vm_paddr_t pa, vm_size_t size)
8865 return (pmap_mapdev_internal(pa, size, PAT_UNCACHEABLE,
8870 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
8873 return (pmap_mapdev_internal(pa, size, PAT_WRITE_BACK,
8874 MAPDEV_FLUSHCACHE));
8878 pmap_unmapdev(vm_offset_t va, vm_size_t size)
8880 struct pmap_preinit_mapping *ppim;
8884 /* If we gave a direct map region in pmap_mapdev, do nothing */
8885 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS)
8887 offset = va & PAGE_MASK;
8888 size = round_page(offset + size);
8889 va = trunc_page(va);
8890 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
8891 ppim = pmap_preinit_mapping + i;
8892 if (ppim->va == va && ppim->sz == size) {
8893 if (pmap_initialized)
8899 if (va + size == virtual_avail)
8904 if (pmap_initialized) {
8905 pmap_qremove(va, atop(size));
8911 * Tries to demote a 1GB page mapping.
8914 pmap_demote_pdpe(pmap_t pmap, pdp_entry_t *pdpe, vm_offset_t va)
8916 pdp_entry_t newpdpe, oldpdpe;
8917 pd_entry_t *firstpde, newpde, *pde;
8918 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
8922 PG_A = pmap_accessed_bit(pmap);
8923 PG_M = pmap_modified_bit(pmap);
8924 PG_V = pmap_valid_bit(pmap);
8925 PG_RW = pmap_rw_bit(pmap);
8927 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
8929 KASSERT((oldpdpe & (PG_PS | PG_V)) == (PG_PS | PG_V),
8930 ("pmap_demote_pdpe: oldpdpe is missing PG_PS and/or PG_V"));
8931 if ((pdpg = vm_page_alloc(NULL, va >> PDPSHIFT, VM_ALLOC_INTERRUPT |
8932 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
8933 CTR2(KTR_PMAP, "pmap_demote_pdpe: failure for va %#lx"
8934 " in pmap %p", va, pmap);
8937 pdpgpa = VM_PAGE_TO_PHYS(pdpg);
8938 firstpde = (pd_entry_t *)PHYS_TO_DMAP(pdpgpa);
8939 newpdpe = pdpgpa | PG_M | PG_A | (oldpdpe & PG_U) | PG_RW | PG_V;
8940 KASSERT((oldpdpe & PG_A) != 0,
8941 ("pmap_demote_pdpe: oldpdpe is missing PG_A"));
8942 KASSERT((oldpdpe & (PG_M | PG_RW)) != PG_RW,
8943 ("pmap_demote_pdpe: oldpdpe is missing PG_M"));
8947 * Initialize the page directory page.
8949 for (pde = firstpde; pde < firstpde + NPDEPG; pde++) {
8955 * Demote the mapping.
8960 * Invalidate a stale recursive mapping of the page directory page.
8962 pmap_invalidate_page(pmap, (vm_offset_t)vtopde(va));
8964 pmap_pdpe_demotions++;
8965 CTR2(KTR_PMAP, "pmap_demote_pdpe: success for va %#lx"
8966 " in pmap %p", va, pmap);
8971 * Sets the memory attribute for the specified page.
8974 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
8977 m->md.pat_mode = ma;
8980 * If "m" is a normal page, update its direct mapping. This update
8981 * can be relied upon to perform any cache operations that are
8982 * required for data coherence.
8984 if ((m->flags & PG_FICTITIOUS) == 0 &&
8985 pmap_change_attr(PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)), PAGE_SIZE,
8987 panic("memory attribute change on the direct map failed");
8991 * Changes the specified virtual address range's memory type to that given by
8992 * the parameter "mode". The specified virtual address range must be
8993 * completely contained within either the direct map or the kernel map. If
8994 * the virtual address range is contained within the kernel map, then the
8995 * memory type for each of the corresponding ranges of the direct map is also
8996 * changed. (The corresponding ranges of the direct map are those ranges that
8997 * map the same physical pages as the specified virtual address range.) These
8998 * changes to the direct map are necessary because Intel describes the
8999 * behavior of their processors as "undefined" if two or more mappings to the
9000 * same physical page have different memory types.
9002 * Returns zero if the change completed successfully, and either EINVAL or
9003 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
9004 * of the virtual address range was not mapped, and ENOMEM is returned if
9005 * there was insufficient memory available to complete the change. In the
9006 * latter case, the memory type may have been changed on some part of the
9007 * virtual address range or the direct map.
9010 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
9014 PMAP_LOCK(kernel_pmap);
9015 error = pmap_change_props_locked(va, size, PROT_NONE, mode,
9017 PMAP_UNLOCK(kernel_pmap);
9022 * Changes the specified virtual address range's protections to those
9023 * specified by "prot". Like pmap_change_attr(), protections for aliases
9024 * in the direct map are updated as well. Protections on aliasing mappings may
9025 * be a subset of the requested protections; for example, mappings in the direct
9026 * map are never executable.
9029 pmap_change_prot(vm_offset_t va, vm_size_t size, vm_prot_t prot)
9033 /* Only supported within the kernel map. */
9034 if (va < VM_MIN_KERNEL_ADDRESS)
9037 PMAP_LOCK(kernel_pmap);
9038 error = pmap_change_props_locked(va, size, prot, -1,
9039 MAPDEV_ASSERTVALID);
9040 PMAP_UNLOCK(kernel_pmap);
9045 pmap_change_props_locked(vm_offset_t va, vm_size_t size, vm_prot_t prot,
9046 int mode, int flags)
9048 vm_offset_t base, offset, tmpva;
9049 vm_paddr_t pa_start, pa_end, pa_end1;
9051 pd_entry_t *pde, pde_bits, pde_mask;
9052 pt_entry_t *pte, pte_bits, pte_mask;
9056 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
9057 base = trunc_page(va);
9058 offset = va & PAGE_MASK;
9059 size = round_page(offset + size);
9062 * Only supported on kernel virtual addresses, including the direct
9063 * map but excluding the recursive map.
9065 if (base < DMAP_MIN_ADDRESS)
9069 * Construct our flag sets and masks. "bits" is the subset of
9070 * "mask" that will be set in each modified PTE.
9072 * Mappings in the direct map are never allowed to be executable.
9074 pde_bits = pte_bits = 0;
9075 pde_mask = pte_mask = 0;
9077 pde_bits |= pmap_cache_bits(kernel_pmap, mode, true);
9078 pde_mask |= X86_PG_PDE_CACHE;
9079 pte_bits |= pmap_cache_bits(kernel_pmap, mode, false);
9080 pte_mask |= X86_PG_PTE_CACHE;
9082 if (prot != VM_PROT_NONE) {
9083 if ((prot & VM_PROT_WRITE) != 0) {
9084 pde_bits |= X86_PG_RW;
9085 pte_bits |= X86_PG_RW;
9087 if ((prot & VM_PROT_EXECUTE) == 0 ||
9088 va < VM_MIN_KERNEL_ADDRESS) {
9092 pde_mask |= X86_PG_RW | pg_nx;
9093 pte_mask |= X86_PG_RW | pg_nx;
9097 * Pages that aren't mapped aren't supported. Also break down 2MB pages
9098 * into 4KB pages if required.
9100 for (tmpva = base; tmpva < base + size; ) {
9101 pdpe = pmap_pdpe(kernel_pmap, tmpva);
9102 if (pdpe == NULL || *pdpe == 0) {
9103 KASSERT((flags & MAPDEV_ASSERTVALID) == 0,
9104 ("%s: addr %#lx is not mapped", __func__, tmpva));
9107 if (*pdpe & PG_PS) {
9109 * If the current 1GB page already has the required
9110 * properties, then we need not demote this page. Just
9111 * increment tmpva to the next 1GB page frame.
9113 if ((*pdpe & pde_mask) == pde_bits) {
9114 tmpva = trunc_1gpage(tmpva) + NBPDP;
9119 * If the current offset aligns with a 1GB page frame
9120 * and there is at least 1GB left within the range, then
9121 * we need not break down this page into 2MB pages.
9123 if ((tmpva & PDPMASK) == 0 &&
9124 tmpva + PDPMASK < base + size) {
9128 if (!pmap_demote_pdpe(kernel_pmap, pdpe, tmpva))
9131 pde = pmap_pdpe_to_pde(pdpe, tmpva);
9133 KASSERT((flags & MAPDEV_ASSERTVALID) == 0,
9134 ("%s: addr %#lx is not mapped", __func__, tmpva));
9139 * If the current 2MB page already has the required
9140 * properties, then we need not demote this page. Just
9141 * increment tmpva to the next 2MB page frame.
9143 if ((*pde & pde_mask) == pde_bits) {
9144 tmpva = trunc_2mpage(tmpva) + NBPDR;
9149 * If the current offset aligns with a 2MB page frame
9150 * and there is at least 2MB left within the range, then
9151 * we need not break down this page into 4KB pages.
9153 if ((tmpva & PDRMASK) == 0 &&
9154 tmpva + PDRMASK < base + size) {
9158 if (!pmap_demote_pde(kernel_pmap, pde, tmpva))
9161 pte = pmap_pde_to_pte(pde, tmpva);
9163 KASSERT((flags & MAPDEV_ASSERTVALID) == 0,
9164 ("%s: addr %#lx is not mapped", __func__, tmpva));
9172 * Ok, all the pages exist, so run through them updating their
9173 * properties if required.
9176 pa_start = pa_end = 0;
9177 for (tmpva = base; tmpva < base + size; ) {
9178 pdpe = pmap_pdpe(kernel_pmap, tmpva);
9179 if (*pdpe & PG_PS) {
9180 if ((*pdpe & pde_mask) != pde_bits) {
9181 pmap_pte_props(pdpe, pde_bits, pde_mask);
9184 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
9185 (*pdpe & PG_PS_FRAME) < dmaplimit) {
9186 if (pa_start == pa_end) {
9187 /* Start physical address run. */
9188 pa_start = *pdpe & PG_PS_FRAME;
9189 pa_end = pa_start + NBPDP;
9190 } else if (pa_end == (*pdpe & PG_PS_FRAME))
9193 /* Run ended, update direct map. */
9194 error = pmap_change_props_locked(
9195 PHYS_TO_DMAP(pa_start),
9196 pa_end - pa_start, prot, mode,
9200 /* Start physical address run. */
9201 pa_start = *pdpe & PG_PS_FRAME;
9202 pa_end = pa_start + NBPDP;
9205 tmpva = trunc_1gpage(tmpva) + NBPDP;
9208 pde = pmap_pdpe_to_pde(pdpe, tmpva);
9210 if ((*pde & pde_mask) != pde_bits) {
9211 pmap_pte_props(pde, pde_bits, pde_mask);
9214 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
9215 (*pde & PG_PS_FRAME) < dmaplimit) {
9216 if (pa_start == pa_end) {
9217 /* Start physical address run. */
9218 pa_start = *pde & PG_PS_FRAME;
9219 pa_end = pa_start + NBPDR;
9220 } else if (pa_end == (*pde & PG_PS_FRAME))
9223 /* Run ended, update direct map. */
9224 error = pmap_change_props_locked(
9225 PHYS_TO_DMAP(pa_start),
9226 pa_end - pa_start, prot, mode,
9230 /* Start physical address run. */
9231 pa_start = *pde & PG_PS_FRAME;
9232 pa_end = pa_start + NBPDR;
9235 tmpva = trunc_2mpage(tmpva) + NBPDR;
9237 pte = pmap_pde_to_pte(pde, tmpva);
9238 if ((*pte & pte_mask) != pte_bits) {
9239 pmap_pte_props(pte, pte_bits, pte_mask);
9242 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
9243 (*pte & PG_FRAME) < dmaplimit) {
9244 if (pa_start == pa_end) {
9245 /* Start physical address run. */
9246 pa_start = *pte & PG_FRAME;
9247 pa_end = pa_start + PAGE_SIZE;
9248 } else if (pa_end == (*pte & PG_FRAME))
9249 pa_end += PAGE_SIZE;
9251 /* Run ended, update direct map. */
9252 error = pmap_change_props_locked(
9253 PHYS_TO_DMAP(pa_start),
9254 pa_end - pa_start, prot, mode,
9258 /* Start physical address run. */
9259 pa_start = *pte & PG_FRAME;
9260 pa_end = pa_start + PAGE_SIZE;
9266 if (error == 0 && pa_start != pa_end && pa_start < dmaplimit) {
9267 pa_end1 = MIN(pa_end, dmaplimit);
9268 if (pa_start != pa_end1)
9269 error = pmap_change_props_locked(PHYS_TO_DMAP(pa_start),
9270 pa_end1 - pa_start, prot, mode, flags);
9274 * Flush CPU caches if required to make sure any data isn't cached that
9275 * shouldn't be, etc.
9278 pmap_invalidate_range(kernel_pmap, base, tmpva);
9279 if ((flags & MAPDEV_FLUSHCACHE) != 0)
9280 pmap_invalidate_cache_range(base, tmpva);
9286 * Demotes any mapping within the direct map region that covers more than the
9287 * specified range of physical addresses. This range's size must be a power
9288 * of two and its starting address must be a multiple of its size. Since the
9289 * demotion does not change any attributes of the mapping, a TLB invalidation
9290 * is not mandatory. The caller may, however, request a TLB invalidation.
9293 pmap_demote_DMAP(vm_paddr_t base, vm_size_t len, boolean_t invalidate)
9302 KASSERT(powerof2(len), ("pmap_demote_DMAP: len is not a power of 2"));
9303 KASSERT((base & (len - 1)) == 0,
9304 ("pmap_demote_DMAP: base is not a multiple of len"));
9305 if (len < NBPDP && base < dmaplimit) {
9306 va = PHYS_TO_DMAP(base);
9308 PMAP_LOCK(kernel_pmap);
9309 pdpe = pmap_pdpe(kernel_pmap, va);
9310 if ((*pdpe & X86_PG_V) == 0)
9311 panic("pmap_demote_DMAP: invalid PDPE");
9312 if ((*pdpe & PG_PS) != 0) {
9313 if (!pmap_demote_pdpe(kernel_pmap, pdpe, va))
9314 panic("pmap_demote_DMAP: PDPE failed");
9318 pde = pmap_pdpe_to_pde(pdpe, va);
9319 if ((*pde & X86_PG_V) == 0)
9320 panic("pmap_demote_DMAP: invalid PDE");
9321 if ((*pde & PG_PS) != 0) {
9322 if (!pmap_demote_pde(kernel_pmap, pde, va))
9323 panic("pmap_demote_DMAP: PDE failed");
9327 if (changed && invalidate)
9328 pmap_invalidate_page(kernel_pmap, va);
9329 PMAP_UNLOCK(kernel_pmap);
9334 * Perform the pmap work for mincore(2). If the page is not both referenced and
9335 * modified by this pmap, returns its physical address so that the caller can
9336 * find other mappings.
9339 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *pap)
9343 pt_entry_t pte, PG_A, PG_M, PG_RW, PG_V;
9347 PG_A = pmap_accessed_bit(pmap);
9348 PG_M = pmap_modified_bit(pmap);
9349 PG_V = pmap_valid_bit(pmap);
9350 PG_RW = pmap_rw_bit(pmap);
9356 pdpe = pmap_pdpe(pmap, addr);
9357 if ((*pdpe & PG_V) != 0) {
9358 if ((*pdpe & PG_PS) != 0) {
9360 pa = ((pte & PG_PS_PDP_FRAME) | (addr & PDPMASK)) &
9362 val = MINCORE_PSIND(2);
9364 pdep = pmap_pde(pmap, addr);
9365 if (pdep != NULL && (*pdep & PG_V) != 0) {
9366 if ((*pdep & PG_PS) != 0) {
9368 /* Compute the physical address of the 4KB page. */
9369 pa = ((pte & PG_PS_FRAME) | (addr &
9370 PDRMASK)) & PG_FRAME;
9371 val = MINCORE_PSIND(1);
9373 pte = *pmap_pde_to_pte(pdep, addr);
9374 pa = pte & PG_FRAME;
9380 if ((pte & PG_V) != 0) {
9381 val |= MINCORE_INCORE;
9382 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
9383 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
9384 if ((pte & PG_A) != 0)
9385 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
9387 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
9388 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) &&
9389 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) {
9397 pmap_pcid_alloc(pmap_t pmap, u_int cpuid)
9399 uint32_t gen, new_gen, pcid_next;
9401 CRITICAL_ASSERT(curthread);
9402 gen = PCPU_GET(pcid_gen);
9403 if (pmap->pm_pcids[cpuid].pm_pcid == PMAP_PCID_KERN)
9404 return (pti ? 0 : CR3_PCID_SAVE);
9405 if (pmap->pm_pcids[cpuid].pm_gen == gen)
9406 return (CR3_PCID_SAVE);
9407 pcid_next = PCPU_GET(pcid_next);
9408 KASSERT((!pti && pcid_next <= PMAP_PCID_OVERMAX) ||
9409 (pti && pcid_next <= PMAP_PCID_OVERMAX_KERN),
9410 ("cpu %d pcid_next %#x", cpuid, pcid_next));
9411 if ((!pti && pcid_next == PMAP_PCID_OVERMAX) ||
9412 (pti && pcid_next == PMAP_PCID_OVERMAX_KERN)) {
9416 PCPU_SET(pcid_gen, new_gen);
9417 pcid_next = PMAP_PCID_KERN + 1;
9421 pmap->pm_pcids[cpuid].pm_pcid = pcid_next;
9422 pmap->pm_pcids[cpuid].pm_gen = new_gen;
9423 PCPU_SET(pcid_next, pcid_next + 1);
9428 pmap_pcid_alloc_checked(pmap_t pmap, u_int cpuid)
9432 cached = pmap_pcid_alloc(pmap, cpuid);
9433 KASSERT(pmap->pm_pcids[cpuid].pm_pcid < PMAP_PCID_OVERMAX,
9434 ("pmap %p cpu %d pcid %#x", pmap, cpuid,
9435 pmap->pm_pcids[cpuid].pm_pcid));
9436 KASSERT(pmap->pm_pcids[cpuid].pm_pcid != PMAP_PCID_KERN ||
9437 pmap == kernel_pmap,
9438 ("non-kernel pmap pmap %p cpu %d pcid %#x",
9439 pmap, cpuid, pmap->pm_pcids[cpuid].pm_pcid));
9444 pmap_activate_sw_pti_post(struct thread *td, pmap_t pmap)
9447 PCPU_GET(tssp)->tss_rsp0 = pmap->pm_ucr3 != PMAP_NO_CR3 ?
9448 PCPU_GET(pti_rsp0) : (uintptr_t)td->td_md.md_stack_base;
9452 pmap_activate_sw_pcid_pti(struct thread *td, pmap_t pmap, u_int cpuid)
9455 uint64_t cached, cr3, kcr3, ucr3;
9457 KASSERT((read_rflags() & PSL_I) == 0,
9458 ("PCID needs interrupts disabled in pmap_activate_sw()"));
9460 /* See the comment in pmap_invalidate_page_pcid(). */
9461 if (PCPU_GET(ucr3_load_mask) != PMAP_UCR3_NOMASK) {
9462 PCPU_SET(ucr3_load_mask, PMAP_UCR3_NOMASK);
9463 old_pmap = PCPU_GET(curpmap);
9464 MPASS(old_pmap->pm_ucr3 != PMAP_NO_CR3);
9465 old_pmap->pm_pcids[cpuid].pm_gen = 0;
9468 cached = pmap_pcid_alloc_checked(pmap, cpuid);
9470 if ((cr3 & ~CR3_PCID_MASK) != pmap->pm_cr3)
9471 load_cr3(pmap->pm_cr3 | pmap->pm_pcids[cpuid].pm_pcid);
9472 PCPU_SET(curpmap, pmap);
9473 kcr3 = pmap->pm_cr3 | pmap->pm_pcids[cpuid].pm_pcid;
9474 ucr3 = pmap->pm_ucr3 | pmap->pm_pcids[cpuid].pm_pcid |
9477 if (!cached && pmap->pm_ucr3 != PMAP_NO_CR3)
9478 PCPU_SET(ucr3_load_mask, ~CR3_PCID_SAVE);
9480 PCPU_SET(kcr3, kcr3 | CR3_PCID_SAVE);
9481 PCPU_SET(ucr3, ucr3 | CR3_PCID_SAVE);
9483 PCPU_INC(pm_save_cnt);
9485 pmap_activate_sw_pti_post(td, pmap);
9489 pmap_activate_sw_pcid_nopti(struct thread *td __unused, pmap_t pmap,
9492 uint64_t cached, cr3;
9494 KASSERT((read_rflags() & PSL_I) == 0,
9495 ("PCID needs interrupts disabled in pmap_activate_sw()"));
9497 cached = pmap_pcid_alloc_checked(pmap, cpuid);
9499 if (!cached || (cr3 & ~CR3_PCID_MASK) != pmap->pm_cr3)
9500 load_cr3(pmap->pm_cr3 | pmap->pm_pcids[cpuid].pm_pcid |
9502 PCPU_SET(curpmap, pmap);
9504 PCPU_INC(pm_save_cnt);
9508 pmap_activate_sw_nopcid_nopti(struct thread *td __unused, pmap_t pmap,
9509 u_int cpuid __unused)
9512 load_cr3(pmap->pm_cr3);
9513 PCPU_SET(curpmap, pmap);
9517 pmap_activate_sw_nopcid_pti(struct thread *td, pmap_t pmap,
9518 u_int cpuid __unused)
9521 pmap_activate_sw_nopcid_nopti(td, pmap, cpuid);
9522 PCPU_SET(kcr3, pmap->pm_cr3);
9523 PCPU_SET(ucr3, pmap->pm_ucr3);
9524 pmap_activate_sw_pti_post(td, pmap);
9527 DEFINE_IFUNC(static, void, pmap_activate_sw_mode, (struct thread *, pmap_t,
9531 if (pmap_pcid_enabled && pti)
9532 return (pmap_activate_sw_pcid_pti);
9533 else if (pmap_pcid_enabled && !pti)
9534 return (pmap_activate_sw_pcid_nopti);
9535 else if (!pmap_pcid_enabled && pti)
9536 return (pmap_activate_sw_nopcid_pti);
9537 else /* if (!pmap_pcid_enabled && !pti) */
9538 return (pmap_activate_sw_nopcid_nopti);
9542 pmap_activate_sw(struct thread *td)
9544 pmap_t oldpmap, pmap;
9547 oldpmap = PCPU_GET(curpmap);
9548 pmap = vmspace_pmap(td->td_proc->p_vmspace);
9549 if (oldpmap == pmap) {
9550 if (cpu_vendor_id != CPU_VENDOR_INTEL)
9554 cpuid = PCPU_GET(cpuid);
9556 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
9558 CPU_SET(cpuid, &pmap->pm_active);
9560 pmap_activate_sw_mode(td, pmap, cpuid);
9562 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
9564 CPU_CLR(cpuid, &oldpmap->pm_active);
9569 pmap_activate(struct thread *td)
9572 * invltlb_{invpcid,}_pcid_handler() is used to handle an
9573 * invalidate_all IPI, which checks for curpmap ==
9574 * smp_tlb_pmap. The below sequence of operations has a
9575 * window where %CR3 is loaded with the new pmap's PML4
9576 * address, but the curpmap value has not yet been updated.
9577 * This causes the invltlb IPI handler, which is called
9578 * between the updates, to execute as a NOP, which leaves
9579 * stale TLB entries.
9581 * Note that the most common use of pmap_activate_sw(), from
9582 * a context switch, is immune to this race, because
9583 * interrupts are disabled (while the thread lock is owned),
9584 * so the IPI is delayed until after curpmap is updated. Protect
9585 * other callers in a similar way, by disabling interrupts
9586 * around the %cr3 register reload and curpmap assignment.
9589 pmap_activate_sw(td);
9594 pmap_activate_boot(pmap_t pmap)
9600 * kernel_pmap must be never deactivated, and we ensure that
9601 * by never activating it at all.
9603 MPASS(pmap != kernel_pmap);
9605 cpuid = PCPU_GET(cpuid);
9607 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
9609 CPU_SET(cpuid, &pmap->pm_active);
9611 PCPU_SET(curpmap, pmap);
9613 kcr3 = pmap->pm_cr3;
9614 if (pmap_pcid_enabled)
9615 kcr3 |= pmap->pm_pcids[cpuid].pm_pcid | CR3_PCID_SAVE;
9619 PCPU_SET(kcr3, kcr3);
9620 PCPU_SET(ucr3, PMAP_NO_CR3);
9624 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
9629 * Increase the starting virtual address of the given mapping if a
9630 * different alignment might result in more superpage mappings.
9633 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
9634 vm_offset_t *addr, vm_size_t size)
9636 vm_offset_t superpage_offset;
9640 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
9641 offset += ptoa(object->pg_color);
9642 superpage_offset = offset & PDRMASK;
9643 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR ||
9644 (*addr & PDRMASK) == superpage_offset)
9646 if ((*addr & PDRMASK) < superpage_offset)
9647 *addr = (*addr & ~PDRMASK) + superpage_offset;
9649 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset;
9653 static unsigned long num_dirty_emulations;
9654 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_dirty_emulations, CTLFLAG_RW,
9655 &num_dirty_emulations, 0, NULL);
9657 static unsigned long num_accessed_emulations;
9658 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_accessed_emulations, CTLFLAG_RW,
9659 &num_accessed_emulations, 0, NULL);
9661 static unsigned long num_superpage_accessed_emulations;
9662 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_superpage_accessed_emulations, CTLFLAG_RW,
9663 &num_superpage_accessed_emulations, 0, NULL);
9665 static unsigned long ad_emulation_superpage_promotions;
9666 SYSCTL_ULONG(_vm_pmap, OID_AUTO, ad_emulation_superpage_promotions, CTLFLAG_RW,
9667 &ad_emulation_superpage_promotions, 0, NULL);
9668 #endif /* INVARIANTS */
9671 pmap_emulate_accessed_dirty(pmap_t pmap, vm_offset_t va, int ftype)
9674 struct rwlock *lock;
9675 #if VM_NRESERVLEVEL > 0
9679 pt_entry_t *pte, PG_A, PG_M, PG_RW, PG_V;
9681 KASSERT(ftype == VM_PROT_READ || ftype == VM_PROT_WRITE,
9682 ("pmap_emulate_accessed_dirty: invalid fault type %d", ftype));
9684 if (!pmap_emulate_ad_bits(pmap))
9687 PG_A = pmap_accessed_bit(pmap);
9688 PG_M = pmap_modified_bit(pmap);
9689 PG_V = pmap_valid_bit(pmap);
9690 PG_RW = pmap_rw_bit(pmap);
9696 pde = pmap_pde(pmap, va);
9697 if (pde == NULL || (*pde & PG_V) == 0)
9700 if ((*pde & PG_PS) != 0) {
9701 if (ftype == VM_PROT_READ) {
9703 atomic_add_long(&num_superpage_accessed_emulations, 1);
9711 pte = pmap_pde_to_pte(pde, va);
9712 if ((*pte & PG_V) == 0)
9715 if (ftype == VM_PROT_WRITE) {
9716 if ((*pte & PG_RW) == 0)
9719 * Set the modified and accessed bits simultaneously.
9721 * Intel EPT PTEs that do software emulation of A/D bits map
9722 * PG_A and PG_M to EPT_PG_READ and EPT_PG_WRITE respectively.
9723 * An EPT misconfiguration is triggered if the PTE is writable
9724 * but not readable (WR=10). This is avoided by setting PG_A
9725 * and PG_M simultaneously.
9727 *pte |= PG_M | PG_A;
9732 #if VM_NRESERVLEVEL > 0
9733 /* try to promote the mapping */
9734 if (va < VM_MAXUSER_ADDRESS)
9735 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
9739 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
9741 if ((mpte == NULL || mpte->ref_count == NPTEPG) &&
9742 pmap_ps_enabled(pmap) &&
9743 (m->flags & PG_FICTITIOUS) == 0 &&
9744 vm_reserv_level_iffullpop(m) == 0) {
9745 pmap_promote_pde(pmap, pde, va, &lock);
9747 atomic_add_long(&ad_emulation_superpage_promotions, 1);
9753 if (ftype == VM_PROT_WRITE)
9754 atomic_add_long(&num_dirty_emulations, 1);
9756 atomic_add_long(&num_accessed_emulations, 1);
9758 rv = 0; /* success */
9767 pmap_get_mapping(pmap_t pmap, vm_offset_t va, uint64_t *ptr, int *num)
9772 pt_entry_t *pte, PG_V;
9776 PG_V = pmap_valid_bit(pmap);
9779 pml4 = pmap_pml4e(pmap, va);
9783 if ((*pml4 & PG_V) == 0)
9786 pdp = pmap_pml4e_to_pdpe(pml4, va);
9788 if ((*pdp & PG_V) == 0 || (*pdp & PG_PS) != 0)
9791 pde = pmap_pdpe_to_pde(pdp, va);
9793 if ((*pde & PG_V) == 0 || (*pde & PG_PS) != 0)
9796 pte = pmap_pde_to_pte(pde, va);
9805 * Get the kernel virtual address of a set of physical pages. If there are
9806 * physical addresses not covered by the DMAP perform a transient mapping
9807 * that will be removed when calling pmap_unmap_io_transient.
9809 * \param page The pages the caller wishes to obtain the virtual
9810 * address on the kernel memory map.
9811 * \param vaddr On return contains the kernel virtual memory address
9812 * of the pages passed in the page parameter.
9813 * \param count Number of pages passed in.
9814 * \param can_fault TRUE if the thread using the mapped pages can take
9815 * page faults, FALSE otherwise.
9817 * \returns TRUE if the caller must call pmap_unmap_io_transient when
9818 * finished or FALSE otherwise.
9822 pmap_map_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
9823 boolean_t can_fault)
9826 boolean_t needs_mapping;
9828 int cache_bits, error __unused, i;
9831 * Allocate any KVA space that we need, this is done in a separate
9832 * loop to prevent calling vmem_alloc while pinned.
9834 needs_mapping = FALSE;
9835 for (i = 0; i < count; i++) {
9836 paddr = VM_PAGE_TO_PHYS(page[i]);
9837 if (__predict_false(paddr >= dmaplimit)) {
9838 error = vmem_alloc(kernel_arena, PAGE_SIZE,
9839 M_BESTFIT | M_WAITOK, &vaddr[i]);
9840 KASSERT(error == 0, ("vmem_alloc failed: %d", error));
9841 needs_mapping = TRUE;
9843 vaddr[i] = PHYS_TO_DMAP(paddr);
9847 /* Exit early if everything is covered by the DMAP */
9852 * NB: The sequence of updating a page table followed by accesses
9853 * to the corresponding pages used in the !DMAP case is subject to
9854 * the situation described in the "AMD64 Architecture Programmer's
9855 * Manual Volume 2: System Programming" rev. 3.23, "7.3.1 Special
9856 * Coherency Considerations". Therefore, issuing the INVLPG right
9857 * after modifying the PTE bits is crucial.
9861 for (i = 0; i < count; i++) {
9862 paddr = VM_PAGE_TO_PHYS(page[i]);
9863 if (paddr >= dmaplimit) {
9866 * Slow path, since we can get page faults
9867 * while mappings are active don't pin the
9868 * thread to the CPU and instead add a global
9869 * mapping visible to all CPUs.
9871 pmap_qenter(vaddr[i], &page[i], 1);
9873 pte = vtopte(vaddr[i]);
9874 cache_bits = pmap_cache_bits(kernel_pmap,
9875 page[i]->md.pat_mode, 0);
9876 pte_store(pte, paddr | X86_PG_RW | X86_PG_V |
9883 return (needs_mapping);
9887 pmap_unmap_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
9888 boolean_t can_fault)
9895 for (i = 0; i < count; i++) {
9896 paddr = VM_PAGE_TO_PHYS(page[i]);
9897 if (paddr >= dmaplimit) {
9899 pmap_qremove(vaddr[i], 1);
9900 vmem_free(kernel_arena, vaddr[i], PAGE_SIZE);
9906 pmap_quick_enter_page(vm_page_t m)
9910 paddr = VM_PAGE_TO_PHYS(m);
9911 if (paddr < dmaplimit)
9912 return (PHYS_TO_DMAP(paddr));
9913 mtx_lock_spin(&qframe_mtx);
9914 KASSERT(*vtopte(qframe) == 0, ("qframe busy"));
9915 pte_store(vtopte(qframe), paddr | X86_PG_RW | X86_PG_V | X86_PG_A |
9916 X86_PG_M | pmap_cache_bits(kernel_pmap, m->md.pat_mode, 0));
9921 pmap_quick_remove_page(vm_offset_t addr)
9926 pte_store(vtopte(qframe), 0);
9928 mtx_unlock_spin(&qframe_mtx);
9932 * Pdp pages from the large map are managed differently from either
9933 * kernel or user page table pages. They are permanently allocated at
9934 * initialization time, and their reference count is permanently set to
9935 * zero. The pml4 entries pointing to those pages are copied into
9936 * each allocated pmap.
9938 * In contrast, pd and pt pages are managed like user page table
9939 * pages. They are dynamically allocated, and their reference count
9940 * represents the number of valid entries within the page.
9943 pmap_large_map_getptp_unlocked(void)
9947 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
9949 if (m != NULL && (m->flags & PG_ZERO) == 0)
9955 pmap_large_map_getptp(void)
9959 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
9960 m = pmap_large_map_getptp_unlocked();
9962 PMAP_UNLOCK(kernel_pmap);
9964 PMAP_LOCK(kernel_pmap);
9965 /* Callers retry. */
9970 static pdp_entry_t *
9971 pmap_large_map_pdpe(vm_offset_t va)
9973 vm_pindex_t pml4_idx;
9976 pml4_idx = pmap_pml4e_index(va);
9977 KASSERT(LMSPML4I <= pml4_idx && pml4_idx < LMSPML4I + lm_ents,
9978 ("pmap_large_map_pdpe: va %#jx out of range idx %#jx LMSPML4I "
9980 (uintmax_t)va, (uintmax_t)pml4_idx, LMSPML4I, lm_ents));
9981 KASSERT((kernel_pml4[pml4_idx] & X86_PG_V) != 0,
9982 ("pmap_large_map_pdpe: invalid pml4 for va %#jx idx %#jx "
9983 "LMSPML4I %#jx lm_ents %d",
9984 (uintmax_t)va, (uintmax_t)pml4_idx, LMSPML4I, lm_ents));
9985 mphys = kernel_pml4[pml4_idx] & PG_FRAME;
9986 return ((pdp_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pdpe_index(va));
9990 pmap_large_map_pde(vm_offset_t va)
9997 pdpe = pmap_large_map_pdpe(va);
9999 m = pmap_large_map_getptp();
10002 mphys = VM_PAGE_TO_PHYS(m);
10003 *pdpe = mphys | X86_PG_A | X86_PG_RW | X86_PG_V | pg_nx;
10005 MPASS((*pdpe & X86_PG_PS) == 0);
10006 mphys = *pdpe & PG_FRAME;
10008 return ((pd_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pde_index(va));
10011 static pt_entry_t *
10012 pmap_large_map_pte(vm_offset_t va)
10019 pde = pmap_large_map_pde(va);
10021 m = pmap_large_map_getptp();
10024 mphys = VM_PAGE_TO_PHYS(m);
10025 *pde = mphys | X86_PG_A | X86_PG_RW | X86_PG_V | pg_nx;
10026 PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pde))->ref_count++;
10028 MPASS((*pde & X86_PG_PS) == 0);
10029 mphys = *pde & PG_FRAME;
10031 return ((pt_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pte_index(va));
10035 pmap_large_map_kextract(vm_offset_t va)
10037 pdp_entry_t *pdpe, pdp;
10038 pd_entry_t *pde, pd;
10039 pt_entry_t *pte, pt;
10041 KASSERT(PMAP_ADDRESS_IN_LARGEMAP(va),
10042 ("not largemap range %#lx", (u_long)va));
10043 pdpe = pmap_large_map_pdpe(va);
10045 KASSERT((pdp & X86_PG_V) != 0,
10046 ("invalid pdp va %#lx pdpe %#lx pdp %#lx", va,
10047 (u_long)pdpe, pdp));
10048 if ((pdp & X86_PG_PS) != 0) {
10049 KASSERT((amd_feature & AMDID_PAGE1GB) != 0,
10050 ("no 1G pages, va %#lx pdpe %#lx pdp %#lx", va,
10051 (u_long)pdpe, pdp));
10052 return ((pdp & PG_PS_PDP_FRAME) | (va & PDPMASK));
10054 pde = pmap_pdpe_to_pde(pdpe, va);
10056 KASSERT((pd & X86_PG_V) != 0,
10057 ("invalid pd va %#lx pde %#lx pd %#lx", va, (u_long)pde, pd));
10058 if ((pd & X86_PG_PS) != 0)
10059 return ((pd & PG_PS_FRAME) | (va & PDRMASK));
10060 pte = pmap_pde_to_pte(pde, va);
10062 KASSERT((pt & X86_PG_V) != 0,
10063 ("invalid pte va %#lx pte %#lx pt %#lx", va, (u_long)pte, pt));
10064 return ((pt & PG_FRAME) | (va & PAGE_MASK));
10068 pmap_large_map_getva(vm_size_t len, vm_offset_t align, vm_offset_t phase,
10069 vmem_addr_t *vmem_res)
10073 * Large mappings are all but static. Consequently, there
10074 * is no point in waiting for an earlier allocation to be
10077 return (vmem_xalloc(large_vmem, len, align, phase, 0, VMEM_ADDR_MIN,
10078 VMEM_ADDR_MAX, M_NOWAIT | M_BESTFIT, vmem_res));
10082 pmap_large_map(vm_paddr_t spa, vm_size_t len, void **addr,
10083 vm_memattr_t mattr)
10088 vm_offset_t va, inc;
10089 vmem_addr_t vmem_res;
10093 if (len == 0 || spa + len < spa)
10096 /* See if DMAP can serve. */
10097 if (spa + len <= dmaplimit) {
10098 va = PHYS_TO_DMAP(spa);
10099 *addr = (void *)va;
10100 return (pmap_change_attr(va, len, mattr));
10104 * No, allocate KVA. Fit the address with best possible
10105 * alignment for superpages. Fall back to worse align if
10109 if ((amd_feature & AMDID_PAGE1GB) != 0 && rounddown2(spa + len,
10110 NBPDP) >= roundup2(spa, NBPDP) + NBPDP)
10111 error = pmap_large_map_getva(len, NBPDP, spa & PDPMASK,
10113 if (error != 0 && rounddown2(spa + len, NBPDR) >= roundup2(spa,
10115 error = pmap_large_map_getva(len, NBPDR, spa & PDRMASK,
10118 error = pmap_large_map_getva(len, PAGE_SIZE, 0, &vmem_res);
10123 * Fill pagetable. PG_M is not pre-set, we scan modified bits
10124 * in the pagetable to minimize flushing. No need to
10125 * invalidate TLB, since we only update invalid entries.
10127 PMAP_LOCK(kernel_pmap);
10128 for (pa = spa, va = vmem_res; len > 0; pa += inc, va += inc,
10130 if ((amd_feature & AMDID_PAGE1GB) != 0 && len >= NBPDP &&
10131 (pa & PDPMASK) == 0 && (va & PDPMASK) == 0) {
10132 pdpe = pmap_large_map_pdpe(va);
10134 *pdpe = pa | pg_g | X86_PG_PS | X86_PG_RW |
10135 X86_PG_V | X86_PG_A | pg_nx |
10136 pmap_cache_bits(kernel_pmap, mattr, TRUE);
10138 } else if (len >= NBPDR && (pa & PDRMASK) == 0 &&
10139 (va & PDRMASK) == 0) {
10140 pde = pmap_large_map_pde(va);
10142 *pde = pa | pg_g | X86_PG_PS | X86_PG_RW |
10143 X86_PG_V | X86_PG_A | pg_nx |
10144 pmap_cache_bits(kernel_pmap, mattr, TRUE);
10145 PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pde))->
10149 pte = pmap_large_map_pte(va);
10151 *pte = pa | pg_g | X86_PG_RW | X86_PG_V |
10152 X86_PG_A | pg_nx | pmap_cache_bits(kernel_pmap,
10154 PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pte))->
10159 PMAP_UNLOCK(kernel_pmap);
10162 *addr = (void *)vmem_res;
10167 pmap_large_unmap(void *svaa, vm_size_t len)
10169 vm_offset_t sva, va;
10171 pdp_entry_t *pdpe, pdp;
10172 pd_entry_t *pde, pd;
10175 struct spglist spgf;
10177 sva = (vm_offset_t)svaa;
10178 if (len == 0 || sva + len < sva || (sva >= DMAP_MIN_ADDRESS &&
10179 sva + len <= DMAP_MIN_ADDRESS + dmaplimit))
10183 KASSERT(PMAP_ADDRESS_IN_LARGEMAP(sva) &&
10184 PMAP_ADDRESS_IN_LARGEMAP(sva + len - 1),
10185 ("not largemap range %#lx %#lx", (u_long)svaa, (u_long)svaa + len));
10186 PMAP_LOCK(kernel_pmap);
10187 for (va = sva; va < sva + len; va += inc) {
10188 pdpe = pmap_large_map_pdpe(va);
10190 KASSERT((pdp & X86_PG_V) != 0,
10191 ("invalid pdp va %#lx pdpe %#lx pdp %#lx", va,
10192 (u_long)pdpe, pdp));
10193 if ((pdp & X86_PG_PS) != 0) {
10194 KASSERT((amd_feature & AMDID_PAGE1GB) != 0,
10195 ("no 1G pages, va %#lx pdpe %#lx pdp %#lx", va,
10196 (u_long)pdpe, pdp));
10197 KASSERT((va & PDPMASK) == 0,
10198 ("PDPMASK bit set, va %#lx pdpe %#lx pdp %#lx", va,
10199 (u_long)pdpe, pdp));
10200 KASSERT(va + NBPDP <= sva + len,
10201 ("unmap covers partial 1GB page, sva %#lx va %#lx "
10202 "pdpe %#lx pdp %#lx len %#lx", sva, va,
10203 (u_long)pdpe, pdp, len));
10208 pde = pmap_pdpe_to_pde(pdpe, va);
10210 KASSERT((pd & X86_PG_V) != 0,
10211 ("invalid pd va %#lx pde %#lx pd %#lx", va,
10213 if ((pd & X86_PG_PS) != 0) {
10214 KASSERT((va & PDRMASK) == 0,
10215 ("PDRMASK bit set, va %#lx pde %#lx pd %#lx", va,
10217 KASSERT(va + NBPDR <= sva + len,
10218 ("unmap covers partial 2MB page, sva %#lx va %#lx "
10219 "pde %#lx pd %#lx len %#lx", sva, va, (u_long)pde,
10223 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pde));
10225 if (m->ref_count == 0) {
10227 SLIST_INSERT_HEAD(&spgf, m, plinks.s.ss);
10231 pte = pmap_pde_to_pte(pde, va);
10232 KASSERT((*pte & X86_PG_V) != 0,
10233 ("invalid pte va %#lx pte %#lx pt %#lx", va,
10234 (u_long)pte, *pte));
10237 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pte));
10239 if (m->ref_count == 0) {
10241 SLIST_INSERT_HEAD(&spgf, m, plinks.s.ss);
10242 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pde));
10244 if (m->ref_count == 0) {
10246 SLIST_INSERT_HEAD(&spgf, m, plinks.s.ss);
10250 pmap_invalidate_range(kernel_pmap, sva, sva + len);
10251 PMAP_UNLOCK(kernel_pmap);
10252 vm_page_free_pages_toq(&spgf, false);
10253 vmem_free(large_vmem, sva, len);
10257 pmap_large_map_wb_fence_mfence(void)
10264 pmap_large_map_wb_fence_atomic(void)
10267 atomic_thread_fence_seq_cst();
10271 pmap_large_map_wb_fence_nop(void)
10275 DEFINE_IFUNC(static, void, pmap_large_map_wb_fence, (void))
10278 if (cpu_vendor_id != CPU_VENDOR_INTEL)
10279 return (pmap_large_map_wb_fence_mfence);
10280 else if ((cpu_stdext_feature & (CPUID_STDEXT_CLWB |
10281 CPUID_STDEXT_CLFLUSHOPT)) == 0)
10282 return (pmap_large_map_wb_fence_atomic);
10284 /* clflush is strongly enough ordered */
10285 return (pmap_large_map_wb_fence_nop);
10289 pmap_large_map_flush_range_clwb(vm_offset_t va, vm_size_t len)
10292 for (; len > 0; len -= cpu_clflush_line_size,
10293 va += cpu_clflush_line_size)
10298 pmap_large_map_flush_range_clflushopt(vm_offset_t va, vm_size_t len)
10301 for (; len > 0; len -= cpu_clflush_line_size,
10302 va += cpu_clflush_line_size)
10307 pmap_large_map_flush_range_clflush(vm_offset_t va, vm_size_t len)
10310 for (; len > 0; len -= cpu_clflush_line_size,
10311 va += cpu_clflush_line_size)
10316 pmap_large_map_flush_range_nop(vm_offset_t sva __unused, vm_size_t len __unused)
10320 DEFINE_IFUNC(static, void, pmap_large_map_flush_range, (vm_offset_t, vm_size_t))
10323 if ((cpu_stdext_feature & CPUID_STDEXT_CLWB) != 0)
10324 return (pmap_large_map_flush_range_clwb);
10325 else if ((cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0)
10326 return (pmap_large_map_flush_range_clflushopt);
10327 else if ((cpu_feature & CPUID_CLFSH) != 0)
10328 return (pmap_large_map_flush_range_clflush);
10330 return (pmap_large_map_flush_range_nop);
10334 pmap_large_map_wb_large(vm_offset_t sva, vm_offset_t eva)
10336 volatile u_long *pe;
10342 for (va = sva; va < eva; va += inc) {
10344 if ((amd_feature & AMDID_PAGE1GB) != 0) {
10345 pe = (volatile u_long *)pmap_large_map_pdpe(va);
10347 if ((p & X86_PG_PS) != 0)
10351 pe = (volatile u_long *)pmap_large_map_pde(va);
10353 if ((p & X86_PG_PS) != 0)
10357 pe = (volatile u_long *)pmap_large_map_pte(va);
10361 seen_other = false;
10363 if ((p & X86_PG_AVAIL1) != 0) {
10365 * Spin-wait for the end of a parallel
10372 * If we saw other write-back
10373 * occuring, we cannot rely on PG_M to
10374 * indicate state of the cache. The
10375 * PG_M bit is cleared before the
10376 * flush to avoid ignoring new writes,
10377 * and writes which are relevant for
10378 * us might happen after.
10384 if ((p & X86_PG_M) != 0 || seen_other) {
10385 if (!atomic_fcmpset_long(pe, &p,
10386 (p & ~X86_PG_M) | X86_PG_AVAIL1))
10388 * If we saw PG_M without
10389 * PG_AVAIL1, and then on the
10390 * next attempt we do not
10391 * observe either PG_M or
10392 * PG_AVAIL1, the other
10393 * write-back started after us
10394 * and finished before us. We
10395 * can rely on it doing our
10399 pmap_large_map_flush_range(va, inc);
10400 atomic_clear_long(pe, X86_PG_AVAIL1);
10409 * Write-back cache lines for the given address range.
10411 * Must be called only on the range or sub-range returned from
10412 * pmap_large_map(). Must not be called on the coalesced ranges.
10414 * Does nothing on CPUs without CLWB, CLFLUSHOPT, or CLFLUSH
10415 * instructions support.
10418 pmap_large_map_wb(void *svap, vm_size_t len)
10420 vm_offset_t eva, sva;
10422 sva = (vm_offset_t)svap;
10424 pmap_large_map_wb_fence();
10425 if (sva >= DMAP_MIN_ADDRESS && eva <= DMAP_MIN_ADDRESS + dmaplimit) {
10426 pmap_large_map_flush_range(sva, len);
10428 KASSERT(sva >= LARGEMAP_MIN_ADDRESS &&
10429 eva <= LARGEMAP_MIN_ADDRESS + lm_ents * NBPML4,
10430 ("pmap_large_map_wb: not largemap %#lx %#lx", sva, len));
10431 pmap_large_map_wb_large(sva, eva);
10433 pmap_large_map_wb_fence();
10437 pmap_pti_alloc_page(void)
10441 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
10442 m = vm_page_grab(pti_obj, pti_pg_idx++, VM_ALLOC_NOBUSY |
10443 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
10448 pmap_pti_free_page(vm_page_t m)
10451 KASSERT(m->ref_count > 0, ("page %p not referenced", m));
10452 if (!vm_page_unwire_noq(m))
10454 vm_page_free_zero(m);
10459 pmap_pti_init(void)
10468 pti_obj = vm_pager_allocate(OBJT_PHYS, NULL, 0, VM_PROT_ALL, 0, NULL);
10469 VM_OBJECT_WLOCK(pti_obj);
10470 pml4_pg = pmap_pti_alloc_page();
10471 pti_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4_pg));
10472 for (va = VM_MIN_KERNEL_ADDRESS; va <= VM_MAX_KERNEL_ADDRESS &&
10473 va >= VM_MIN_KERNEL_ADDRESS && va > NBPML4; va += NBPML4) {
10474 pdpe = pmap_pti_pdpe(va);
10475 pmap_pti_wire_pte(pdpe);
10477 pmap_pti_add_kva_locked((vm_offset_t)&__pcpu[0],
10478 (vm_offset_t)&__pcpu[0] + sizeof(__pcpu[0]) * MAXCPU, false);
10479 pmap_pti_add_kva_locked((vm_offset_t)idt, (vm_offset_t)idt +
10480 sizeof(struct gate_descriptor) * NIDT, false);
10482 /* Doublefault stack IST 1 */
10483 va = __pcpu[i].pc_common_tss.tss_ist1 + sizeof(struct nmi_pcpu);
10484 pmap_pti_add_kva_locked(va - PAGE_SIZE, va, false);
10485 /* NMI stack IST 2 */
10486 va = __pcpu[i].pc_common_tss.tss_ist2 + sizeof(struct nmi_pcpu);
10487 pmap_pti_add_kva_locked(va - PAGE_SIZE, va, false);
10488 /* MC# stack IST 3 */
10489 va = __pcpu[i].pc_common_tss.tss_ist3 +
10490 sizeof(struct nmi_pcpu);
10491 pmap_pti_add_kva_locked(va - PAGE_SIZE, va, false);
10492 /* DB# stack IST 4 */
10493 va = __pcpu[i].pc_common_tss.tss_ist4 + sizeof(struct nmi_pcpu);
10494 pmap_pti_add_kva_locked(va - PAGE_SIZE, va, false);
10496 pmap_pti_add_kva_locked((vm_offset_t)kernphys + KERNBASE,
10497 (vm_offset_t)etext, true);
10498 pti_finalized = true;
10499 VM_OBJECT_WUNLOCK(pti_obj);
10501 SYSINIT(pmap_pti, SI_SUB_CPU + 1, SI_ORDER_ANY, pmap_pti_init, NULL);
10503 static pdp_entry_t *
10504 pmap_pti_pdpe(vm_offset_t va)
10506 pml4_entry_t *pml4e;
10509 vm_pindex_t pml4_idx;
10512 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
10514 pml4_idx = pmap_pml4e_index(va);
10515 pml4e = &pti_pml4[pml4_idx];
10519 panic("pml4 alloc after finalization\n");
10520 m = pmap_pti_alloc_page();
10522 pmap_pti_free_page(m);
10523 mphys = *pml4e & ~PAGE_MASK;
10525 mphys = VM_PAGE_TO_PHYS(m);
10526 *pml4e = mphys | X86_PG_RW | X86_PG_V;
10529 mphys = *pml4e & ~PAGE_MASK;
10531 pdpe = (pdp_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pdpe_index(va);
10536 pmap_pti_wire_pte(void *pte)
10540 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
10541 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pte));
10546 pmap_pti_unwire_pde(void *pde, bool only_ref)
10550 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
10551 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pde));
10552 MPASS(m->ref_count > 0);
10553 MPASS(only_ref || m->ref_count > 1);
10554 pmap_pti_free_page(m);
10558 pmap_pti_unwire_pte(void *pte, vm_offset_t va)
10563 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
10564 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pte));
10565 MPASS(m->ref_count > 0);
10566 if (pmap_pti_free_page(m)) {
10567 pde = pmap_pti_pde(va);
10568 MPASS((*pde & (X86_PG_PS | X86_PG_V)) == X86_PG_V);
10570 pmap_pti_unwire_pde(pde, false);
10574 static pd_entry_t *
10575 pmap_pti_pde(vm_offset_t va)
10580 vm_pindex_t pd_idx;
10583 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
10585 pdpe = pmap_pti_pdpe(va);
10587 m = pmap_pti_alloc_page();
10589 pmap_pti_free_page(m);
10590 MPASS((*pdpe & X86_PG_PS) == 0);
10591 mphys = *pdpe & ~PAGE_MASK;
10593 mphys = VM_PAGE_TO_PHYS(m);
10594 *pdpe = mphys | X86_PG_RW | X86_PG_V;
10597 MPASS((*pdpe & X86_PG_PS) == 0);
10598 mphys = *pdpe & ~PAGE_MASK;
10601 pde = (pd_entry_t *)PHYS_TO_DMAP(mphys);
10602 pd_idx = pmap_pde_index(va);
10607 static pt_entry_t *
10608 pmap_pti_pte(vm_offset_t va, bool *unwire_pde)
10615 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
10617 pde = pmap_pti_pde(va);
10618 if (unwire_pde != NULL) {
10619 *unwire_pde = true;
10620 pmap_pti_wire_pte(pde);
10623 m = pmap_pti_alloc_page();
10625 pmap_pti_free_page(m);
10626 MPASS((*pde & X86_PG_PS) == 0);
10627 mphys = *pde & ~(PAGE_MASK | pg_nx);
10629 mphys = VM_PAGE_TO_PHYS(m);
10630 *pde = mphys | X86_PG_RW | X86_PG_V;
10631 if (unwire_pde != NULL)
10632 *unwire_pde = false;
10635 MPASS((*pde & X86_PG_PS) == 0);
10636 mphys = *pde & ~(PAGE_MASK | pg_nx);
10639 pte = (pt_entry_t *)PHYS_TO_DMAP(mphys);
10640 pte += pmap_pte_index(va);
10646 pmap_pti_add_kva_locked(vm_offset_t sva, vm_offset_t eva, bool exec)
10650 pt_entry_t *pte, ptev;
10653 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
10655 sva = trunc_page(sva);
10656 MPASS(sva > VM_MAXUSER_ADDRESS);
10657 eva = round_page(eva);
10659 for (; sva < eva; sva += PAGE_SIZE) {
10660 pte = pmap_pti_pte(sva, &unwire_pde);
10661 pa = pmap_kextract(sva);
10662 ptev = pa | X86_PG_RW | X86_PG_V | X86_PG_A | X86_PG_G |
10663 (exec ? 0 : pg_nx) | pmap_cache_bits(kernel_pmap,
10664 VM_MEMATTR_DEFAULT, FALSE);
10666 pte_store(pte, ptev);
10667 pmap_pti_wire_pte(pte);
10669 KASSERT(!pti_finalized,
10670 ("pti overlap after fin %#lx %#lx %#lx",
10672 KASSERT(*pte == ptev,
10673 ("pti non-identical pte after fin %#lx %#lx %#lx",
10677 pde = pmap_pti_pde(sva);
10678 pmap_pti_unwire_pde(pde, true);
10684 pmap_pti_add_kva(vm_offset_t sva, vm_offset_t eva, bool exec)
10689 VM_OBJECT_WLOCK(pti_obj);
10690 pmap_pti_add_kva_locked(sva, eva, exec);
10691 VM_OBJECT_WUNLOCK(pti_obj);
10695 pmap_pti_remove_kva(vm_offset_t sva, vm_offset_t eva)
10702 sva = rounddown2(sva, PAGE_SIZE);
10703 MPASS(sva > VM_MAXUSER_ADDRESS);
10704 eva = roundup2(eva, PAGE_SIZE);
10706 VM_OBJECT_WLOCK(pti_obj);
10707 for (va = sva; va < eva; va += PAGE_SIZE) {
10708 pte = pmap_pti_pte(va, NULL);
10709 KASSERT((*pte & X86_PG_V) != 0,
10710 ("invalid pte va %#lx pte %#lx pt %#lx", va,
10711 (u_long)pte, *pte));
10713 pmap_pti_unwire_pte(pte, va);
10715 pmap_invalidate_range(kernel_pmap, sva, eva);
10716 VM_OBJECT_WUNLOCK(pti_obj);
10720 pkru_dup_range(void *ctx __unused, void *data)
10722 struct pmap_pkru_range *node, *new_node;
10724 new_node = uma_zalloc(pmap_pkru_ranges_zone, M_NOWAIT);
10725 if (new_node == NULL)
10728 memcpy(new_node, node, sizeof(*node));
10733 pkru_free_range(void *ctx __unused, void *node)
10736 uma_zfree(pmap_pkru_ranges_zone, node);
10740 pmap_pkru_assign(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, u_int keyidx,
10743 struct pmap_pkru_range *ppr;
10746 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
10747 MPASS(pmap->pm_type == PT_X86);
10748 MPASS((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0);
10749 if ((flags & AMD64_PKRU_EXCL) != 0 &&
10750 !rangeset_check_empty(&pmap->pm_pkru, sva, eva))
10752 ppr = uma_zalloc(pmap_pkru_ranges_zone, M_NOWAIT);
10755 ppr->pkru_keyidx = keyidx;
10756 ppr->pkru_flags = flags & AMD64_PKRU_PERSIST;
10757 error = rangeset_insert(&pmap->pm_pkru, sva, eva, ppr);
10759 uma_zfree(pmap_pkru_ranges_zone, ppr);
10764 pmap_pkru_deassign(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
10767 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
10768 MPASS(pmap->pm_type == PT_X86);
10769 MPASS((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0);
10770 return (rangeset_remove(&pmap->pm_pkru, sva, eva));
10774 pmap_pkru_deassign_all(pmap_t pmap)
10777 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
10778 if (pmap->pm_type == PT_X86 &&
10779 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0)
10780 rangeset_remove_all(&pmap->pm_pkru);
10784 pmap_pkru_same(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
10786 struct pmap_pkru_range *ppr, *prev_ppr;
10789 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
10790 if (pmap->pm_type != PT_X86 ||
10791 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0 ||
10792 sva >= VM_MAXUSER_ADDRESS)
10794 MPASS(eva <= VM_MAXUSER_ADDRESS);
10795 for (va = sva; va < eva; prev_ppr = ppr) {
10796 ppr = rangeset_lookup(&pmap->pm_pkru, va);
10799 else if ((ppr == NULL) ^ (prev_ppr == NULL))
10805 if (prev_ppr->pkru_keyidx != ppr->pkru_keyidx)
10807 va = ppr->pkru_rs_el.re_end;
10813 pmap_pkru_get(pmap_t pmap, vm_offset_t va)
10815 struct pmap_pkru_range *ppr;
10817 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
10818 if (pmap->pm_type != PT_X86 ||
10819 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0 ||
10820 va >= VM_MAXUSER_ADDRESS)
10822 ppr = rangeset_lookup(&pmap->pm_pkru, va);
10824 return (X86_PG_PKU(ppr->pkru_keyidx));
10829 pred_pkru_on_remove(void *ctx __unused, void *r)
10831 struct pmap_pkru_range *ppr;
10834 return ((ppr->pkru_flags & AMD64_PKRU_PERSIST) == 0);
10838 pmap_pkru_on_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
10841 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
10842 if (pmap->pm_type == PT_X86 &&
10843 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0) {
10844 rangeset_remove_pred(&pmap->pm_pkru, sva, eva,
10845 pred_pkru_on_remove);
10850 pmap_pkru_copy(pmap_t dst_pmap, pmap_t src_pmap)
10853 PMAP_LOCK_ASSERT(dst_pmap, MA_OWNED);
10854 PMAP_LOCK_ASSERT(src_pmap, MA_OWNED);
10855 MPASS(dst_pmap->pm_type == PT_X86);
10856 MPASS(src_pmap->pm_type == PT_X86);
10857 MPASS((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0);
10858 if (src_pmap->pm_pkru.rs_data_ctx == NULL)
10860 return (rangeset_copy(&dst_pmap->pm_pkru, &src_pmap->pm_pkru));
10864 pmap_pkru_update_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
10867 pml4_entry_t *pml4e;
10869 pd_entry_t newpde, ptpaddr, *pde;
10870 pt_entry_t newpte, *ptep, pte;
10871 vm_offset_t va, va_next;
10874 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
10875 MPASS(pmap->pm_type == PT_X86);
10876 MPASS(keyidx <= PMAP_MAX_PKRU_IDX);
10878 for (changed = false, va = sva; va < eva; va = va_next) {
10879 pml4e = pmap_pml4e(pmap, va);
10880 if (pml4e == NULL || (*pml4e & X86_PG_V) == 0) {
10881 va_next = (va + NBPML4) & ~PML4MASK;
10887 pdpe = pmap_pml4e_to_pdpe(pml4e, va);
10888 if ((*pdpe & X86_PG_V) == 0) {
10889 va_next = (va + NBPDP) & ~PDPMASK;
10895 va_next = (va + NBPDR) & ~PDRMASK;
10899 pde = pmap_pdpe_to_pde(pdpe, va);
10904 MPASS((ptpaddr & X86_PG_V) != 0);
10905 if ((ptpaddr & PG_PS) != 0) {
10906 if (va + NBPDR == va_next && eva >= va_next) {
10907 newpde = (ptpaddr & ~X86_PG_PKU_MASK) |
10908 X86_PG_PKU(keyidx);
10909 if (newpde != ptpaddr) {
10914 } else if (!pmap_demote_pde(pmap, pde, va)) {
10922 for (ptep = pmap_pde_to_pte(pde, va); va != va_next;
10923 ptep++, va += PAGE_SIZE) {
10925 if ((pte & X86_PG_V) == 0)
10927 newpte = (pte & ~X86_PG_PKU_MASK) | X86_PG_PKU(keyidx);
10928 if (newpte != pte) {
10935 pmap_invalidate_range(pmap, sva, eva);
10939 pmap_pkru_check_uargs(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
10940 u_int keyidx, int flags)
10943 if (pmap->pm_type != PT_X86 || keyidx > PMAP_MAX_PKRU_IDX ||
10944 (flags & ~(AMD64_PKRU_PERSIST | AMD64_PKRU_EXCL)) != 0)
10946 if (eva <= sva || eva > VM_MAXUSER_ADDRESS)
10948 if ((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0)
10954 pmap_pkru_set(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, u_int keyidx,
10959 sva = trunc_page(sva);
10960 eva = round_page(eva);
10961 error = pmap_pkru_check_uargs(pmap, sva, eva, keyidx, flags);
10966 error = pmap_pkru_assign(pmap, sva, eva, keyidx, flags);
10968 pmap_pkru_update_range(pmap, sva, eva, keyidx);
10970 if (error != ENOMEM)
10978 pmap_pkru_clear(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
10982 sva = trunc_page(sva);
10983 eva = round_page(eva);
10984 error = pmap_pkru_check_uargs(pmap, sva, eva, 0, 0);
10989 error = pmap_pkru_deassign(pmap, sva, eva);
10991 pmap_pkru_update_range(pmap, sva, eva, 0);
10993 if (error != ENOMEM)
11001 * Track a range of the kernel's virtual address space that is contiguous
11002 * in various mapping attributes.
11004 struct pmap_kernel_map_range {
11013 sysctl_kmaps_dump(struct sbuf *sb, struct pmap_kernel_map_range *range,
11019 if (eva <= range->sva)
11022 pat_idx = pmap_pat_index(kernel_pmap, range->attrs, true);
11023 for (i = 0; i < PAT_INDEX_SIZE; i++)
11024 if (pat_index[i] == pat_idx)
11028 case PAT_WRITE_BACK:
11031 case PAT_WRITE_THROUGH:
11034 case PAT_UNCACHEABLE:
11040 case PAT_WRITE_PROTECTED:
11043 case PAT_WRITE_COMBINING:
11047 printf("%s: unknown PAT mode %#x for range 0x%016lx-0x%016lx\n",
11048 __func__, pat_idx, range->sva, eva);
11053 sbuf_printf(sb, "0x%016lx-0x%016lx r%c%c%c%c %s %d %d %d\n",
11055 (range->attrs & X86_PG_RW) != 0 ? 'w' : '-',
11056 (range->attrs & pg_nx) != 0 ? '-' : 'x',
11057 (range->attrs & X86_PG_U) != 0 ? 'u' : 's',
11058 (range->attrs & X86_PG_G) != 0 ? 'g' : '-',
11059 mode, range->pdpes, range->pdes, range->ptes);
11061 /* Reset to sentinel value. */
11062 range->sva = la57 ? KV5ADDR(NPML5EPG - 1, NPML4EPG - 1, NPDPEPG - 1,
11063 NPDEPG - 1, NPTEPG - 1) : KV4ADDR(NPML4EPG - 1, NPDPEPG - 1,
11064 NPDEPG - 1, NPTEPG - 1);
11068 * Determine whether the attributes specified by a page table entry match those
11069 * being tracked by the current range. This is not quite as simple as a direct
11070 * flag comparison since some PAT modes have multiple representations.
11073 sysctl_kmaps_match(struct pmap_kernel_map_range *range, pt_entry_t attrs)
11075 pt_entry_t diff, mask;
11077 mask = X86_PG_G | X86_PG_RW | X86_PG_U | X86_PG_PDE_CACHE | pg_nx;
11078 diff = (range->attrs ^ attrs) & mask;
11081 if ((diff & ~X86_PG_PDE_PAT) == 0 &&
11082 pmap_pat_index(kernel_pmap, range->attrs, true) ==
11083 pmap_pat_index(kernel_pmap, attrs, true))
11089 sysctl_kmaps_reinit(struct pmap_kernel_map_range *range, vm_offset_t va,
11093 memset(range, 0, sizeof(*range));
11095 range->attrs = attrs;
11099 * Given a leaf PTE, derive the mapping's attributes. If they do not match
11100 * those of the current run, dump the address range and its attributes, and
11104 sysctl_kmaps_check(struct sbuf *sb, struct pmap_kernel_map_range *range,
11105 vm_offset_t va, pml4_entry_t pml4e, pdp_entry_t pdpe, pd_entry_t pde,
11110 attrs = pml4e & (X86_PG_RW | X86_PG_U | pg_nx);
11112 attrs |= pdpe & pg_nx;
11113 attrs &= pg_nx | (pdpe & (X86_PG_RW | X86_PG_U));
11114 if ((pdpe & PG_PS) != 0) {
11115 attrs |= pdpe & (X86_PG_G | X86_PG_PDE_CACHE);
11116 } else if (pde != 0) {
11117 attrs |= pde & pg_nx;
11118 attrs &= pg_nx | (pde & (X86_PG_RW | X86_PG_U));
11120 if ((pde & PG_PS) != 0) {
11121 attrs |= pde & (X86_PG_G | X86_PG_PDE_CACHE);
11122 } else if (pte != 0) {
11123 attrs |= pte & pg_nx;
11124 attrs &= pg_nx | (pte & (X86_PG_RW | X86_PG_U));
11125 attrs |= pte & (X86_PG_G | X86_PG_PTE_CACHE);
11127 /* Canonicalize by always using the PDE PAT bit. */
11128 if ((attrs & X86_PG_PTE_PAT) != 0)
11129 attrs ^= X86_PG_PDE_PAT | X86_PG_PTE_PAT;
11132 if (range->sva > va || !sysctl_kmaps_match(range, attrs)) {
11133 sysctl_kmaps_dump(sb, range, va);
11134 sysctl_kmaps_reinit(range, va, attrs);
11139 sysctl_kmaps(SYSCTL_HANDLER_ARGS)
11141 struct pmap_kernel_map_range range;
11142 struct sbuf sbuf, *sb;
11143 pml4_entry_t pml4e;
11144 pdp_entry_t *pdp, pdpe;
11145 pd_entry_t *pd, pde;
11146 pt_entry_t *pt, pte;
11149 int error, i, j, k, l;
11151 error = sysctl_wire_old_buffer(req, 0);
11155 sbuf_new_for_sysctl(sb, NULL, PAGE_SIZE, req);
11157 /* Sentinel value. */
11158 range.sva = la57 ? KV5ADDR(NPML5EPG - 1, NPML4EPG - 1, NPDPEPG - 1,
11159 NPDEPG - 1, NPTEPG - 1) : KV4ADDR(NPML4EPG - 1, NPDPEPG - 1,
11160 NPDEPG - 1, NPTEPG - 1);
11163 * Iterate over the kernel page tables without holding the kernel pmap
11164 * lock. Outside of the large map, kernel page table pages are never
11165 * freed, so at worst we will observe inconsistencies in the output.
11166 * Within the large map, ensure that PDP and PD page addresses are
11167 * valid before descending.
11169 for (sva = 0, i = pmap_pml4e_index(sva); i < NPML4EPG; i++) {
11172 sbuf_printf(sb, "\nRecursive map:\n");
11175 sbuf_printf(sb, "\nDirect map:\n");
11178 sbuf_printf(sb, "\nKernel map:\n");
11181 sbuf_printf(sb, "\nLarge map:\n");
11185 /* Convert to canonical form. */
11186 if (sva == 1ul << 47)
11190 pml4e = kernel_pml4[i];
11191 if ((pml4e & X86_PG_V) == 0) {
11192 sva = rounddown2(sva, NBPML4);
11193 sysctl_kmaps_dump(sb, &range, sva);
11197 pa = pml4e & PG_FRAME;
11198 pdp = (pdp_entry_t *)PHYS_TO_DMAP(pa);
11200 for (j = pmap_pdpe_index(sva); j < NPDPEPG; j++) {
11202 if ((pdpe & X86_PG_V) == 0) {
11203 sva = rounddown2(sva, NBPDP);
11204 sysctl_kmaps_dump(sb, &range, sva);
11208 pa = pdpe & PG_FRAME;
11209 if (PMAP_ADDRESS_IN_LARGEMAP(sva) &&
11210 vm_phys_paddr_to_vm_page(pa) == NULL)
11212 if ((pdpe & PG_PS) != 0) {
11213 sva = rounddown2(sva, NBPDP);
11214 sysctl_kmaps_check(sb, &range, sva, pml4e, pdpe,
11220 pd = (pd_entry_t *)PHYS_TO_DMAP(pa);
11222 for (k = pmap_pde_index(sva); k < NPDEPG; k++) {
11224 if ((pde & X86_PG_V) == 0) {
11225 sva = rounddown2(sva, NBPDR);
11226 sysctl_kmaps_dump(sb, &range, sva);
11230 pa = pde & PG_FRAME;
11231 if (PMAP_ADDRESS_IN_LARGEMAP(sva) &&
11232 vm_phys_paddr_to_vm_page(pa) == NULL)
11234 if ((pde & PG_PS) != 0) {
11235 sva = rounddown2(sva, NBPDR);
11236 sysctl_kmaps_check(sb, &range, sva,
11237 pml4e, pdpe, pde, 0);
11242 pt = (pt_entry_t *)PHYS_TO_DMAP(pa);
11244 for (l = pmap_pte_index(sva); l < NPTEPG; l++,
11245 sva += PAGE_SIZE) {
11247 if ((pte & X86_PG_V) == 0) {
11248 sysctl_kmaps_dump(sb, &range,
11252 sysctl_kmaps_check(sb, &range, sva,
11253 pml4e, pdpe, pde, pte);
11260 error = sbuf_finish(sb);
11264 SYSCTL_OID(_vm_pmap, OID_AUTO, kernel_maps,
11265 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE,
11266 NULL, 0, sysctl_kmaps, "A",
11267 "Dump kernel address layout");
11270 DB_SHOW_COMMAND(pte, pmap_print_pte)
11273 pml5_entry_t *pml5;
11274 pml4_entry_t *pml4;
11277 pt_entry_t *pte, PG_V;
11281 db_printf("show pte addr\n");
11284 va = (vm_offset_t)addr;
11286 if (kdb_thread != NULL)
11287 pmap = vmspace_pmap(kdb_thread->td_proc->p_vmspace);
11289 pmap = PCPU_GET(curpmap);
11291 PG_V = pmap_valid_bit(pmap);
11292 db_printf("VA 0x%016lx", va);
11294 if (pmap_is_la57(pmap)) {
11295 pml5 = pmap_pml5e(pmap, va);
11296 db_printf(" pml5e 0x%016lx", *pml5);
11297 if ((*pml5 & PG_V) == 0) {
11301 pml4 = pmap_pml5e_to_pml4e(pml5, va);
11303 pml4 = pmap_pml4e(pmap, va);
11305 db_printf(" pml4e 0x%016lx", *pml4);
11306 if ((*pml4 & PG_V) == 0) {
11310 pdp = pmap_pml4e_to_pdpe(pml4, va);
11311 db_printf(" pdpe 0x%016lx", *pdp);
11312 if ((*pdp & PG_V) == 0 || (*pdp & PG_PS) != 0) {
11316 pde = pmap_pdpe_to_pde(pdp, va);
11317 db_printf(" pde 0x%016lx", *pde);
11318 if ((*pde & PG_V) == 0 || (*pde & PG_PS) != 0) {
11322 pte = pmap_pde_to_pte(pde, va);
11323 db_printf(" pte 0x%016lx\n", *pte);
11326 DB_SHOW_COMMAND(phys2dmap, pmap_phys2dmap)
11331 a = (vm_paddr_t)addr;
11332 db_printf("0x%jx\n", (uintmax_t)PHYS_TO_DMAP(a));
11334 db_printf("show phys2dmap addr\n");
11339 ptpages_show_page(int level, int idx, vm_page_t pg)
11341 db_printf("l %d i %d pg %p phys %#lx ref %x\n",
11342 level, idx, pg, VM_PAGE_TO_PHYS(pg), pg->ref_count);
11346 ptpages_show_complain(int level, int idx, uint64_t pte)
11348 db_printf("l %d i %d pte %#lx\n", level, idx, pte);
11352 ptpages_show_pml4(vm_page_t pg4, int num_entries, uint64_t PG_V)
11354 vm_page_t pg3, pg2, pg1;
11355 pml4_entry_t *pml4;
11360 pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pg4));
11361 for (i4 = 0; i4 < num_entries; i4++) {
11362 if ((pml4[i4] & PG_V) == 0)
11364 pg3 = PHYS_TO_VM_PAGE(pml4[i4] & PG_FRAME);
11366 ptpages_show_complain(3, i4, pml4[i4]);
11369 ptpages_show_page(3, i4, pg3);
11370 pdp = (pdp_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pg3));
11371 for (i3 = 0; i3 < NPDPEPG; i3++) {
11372 if ((pdp[i3] & PG_V) == 0)
11374 pg2 = PHYS_TO_VM_PAGE(pdp[i3] & PG_FRAME);
11376 ptpages_show_complain(2, i3, pdp[i3]);
11379 ptpages_show_page(2, i3, pg2);
11380 pd = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pg2));
11381 for (i2 = 0; i2 < NPDEPG; i2++) {
11382 if ((pd[i2] & PG_V) == 0)
11384 pg1 = PHYS_TO_VM_PAGE(pd[i2] & PG_FRAME);
11386 ptpages_show_complain(1, i2, pd[i2]);
11389 ptpages_show_page(1, i2, pg1);
11395 DB_SHOW_COMMAND(ptpages, pmap_ptpages)
11399 pml5_entry_t *pml5;
11404 pmap = (pmap_t)addr;
11406 pmap = PCPU_GET(curpmap);
11408 PG_V = pmap_valid_bit(pmap);
11410 if (pmap_is_la57(pmap)) {
11411 pml5 = pmap->pm_pmltop;
11412 for (i5 = 0; i5 < NUPML5E; i5++) {
11413 if ((pml5[i5] & PG_V) == 0)
11415 pg = PHYS_TO_VM_PAGE(pml5[i5] & PG_FRAME);
11417 ptpages_show_complain(4, i5, pml5[i5]);
11420 ptpages_show_page(4, i5, pg);
11421 ptpages_show_pml4(pg, NPML4EPG, PG_V);
11424 ptpages_show_pml4(PHYS_TO_VM_PAGE(DMAP_TO_PHYS(
11425 (vm_offset_t)pmap->pm_pmltop)), NUP4ML4E, PG_V);