2 * SPDX-License-Identifier: BSD-4-Clause
4 * Copyright (c) 1991 Regents of the University of California.
6 * Copyright (c) 1994 John S. Dyson
8 * Copyright (c) 1994 David Greenman
10 * Copyright (c) 2003 Peter Wemm
11 * All rights reserved.
12 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
13 * All rights reserved.
15 * This code is derived from software contributed to Berkeley by
16 * the Systems Programming Group of the University of Utah Computer
17 * Science Department and William Jolitz of UUNET Technologies Inc.
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions
22 * 1. Redistributions of source code must retain the above copyright
23 * notice, this list of conditions and the following disclaimer.
24 * 2. Redistributions in binary form must reproduce the above copyright
25 * notice, this list of conditions and the following disclaimer in the
26 * documentation and/or other materials provided with the distribution.
27 * 3. All advertising materials mentioning features or use of this software
28 * must display the following acknowledgement:
29 * This product includes software developed by the University of
30 * California, Berkeley and its contributors.
31 * 4. Neither the name of the University nor the names of its contributors
32 * may be used to endorse or promote products derived from this software
33 * without specific prior written permission.
35 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
36 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
37 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
38 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
39 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
40 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
41 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
42 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
43 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
44 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
47 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
50 * Copyright (c) 2003 Networks Associates Technology, Inc.
51 * Copyright (c) 2014-2019 The FreeBSD Foundation
52 * All rights reserved.
54 * This software was developed for the FreeBSD Project by Jake Burkholder,
55 * Safeport Network Services, and Network Associates Laboratories, the
56 * Security Research Division of Network Associates, Inc. under
57 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
58 * CHATS research program.
60 * Portions of this software were developed by
61 * Konstantin Belousov <kib@FreeBSD.org> under sponsorship from
62 * the FreeBSD Foundation.
64 * Redistribution and use in source and binary forms, with or without
65 * modification, are permitted provided that the following conditions
67 * 1. Redistributions of source code must retain the above copyright
68 * notice, this list of conditions and the following disclaimer.
69 * 2. Redistributions in binary form must reproduce the above copyright
70 * notice, this list of conditions and the following disclaimer in the
71 * documentation and/or other materials provided with the distribution.
73 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
74 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
77 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
78 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
79 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
80 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
81 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
82 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
86 #define AMD64_NPT_AWARE
88 #include <sys/cdefs.h>
89 __FBSDID("$FreeBSD$");
92 * Manages physical address maps.
94 * Since the information managed by this module is
95 * also stored by the logical address mapping module,
96 * this module may throw away valid virtual-to-physical
97 * mappings at almost any time. However, invalidations
98 * of virtual-to-physical mappings must be done as
101 * In order to cope with hardware architectures which
102 * make virtual-to-physical map invalidates expensive,
103 * this module may delay invalidate or reduced protection
104 * operations until such time as they are actually
105 * necessary. This module is given full information as
106 * to which processors are currently using which maps,
107 * and to when physical maps must be made correct.
111 #include "opt_pmap.h"
114 #include <sys/param.h>
115 #include <sys/bitstring.h>
117 #include <sys/systm.h>
118 #include <sys/kernel.h>
120 #include <sys/lock.h>
121 #include <sys/malloc.h>
122 #include <sys/mman.h>
123 #include <sys/mutex.h>
124 #include <sys/proc.h>
125 #include <sys/rangeset.h>
126 #include <sys/rwlock.h>
127 #include <sys/sbuf.h>
129 #include <sys/turnstile.h>
130 #include <sys/vmem.h>
131 #include <sys/vmmeter.h>
132 #include <sys/sched.h>
133 #include <sys/sysctl.h>
141 #include <vm/vm_param.h>
142 #include <vm/vm_kern.h>
143 #include <vm/vm_page.h>
144 #include <vm/vm_map.h>
145 #include <vm/vm_object.h>
146 #include <vm/vm_extern.h>
147 #include <vm/vm_pageout.h>
148 #include <vm/vm_pager.h>
149 #include <vm/vm_phys.h>
150 #include <vm/vm_radix.h>
151 #include <vm/vm_reserv.h>
154 #include <machine/intr_machdep.h>
155 #include <x86/apicvar.h>
156 #include <x86/ifunc.h>
157 #include <machine/cpu.h>
158 #include <machine/cputypes.h>
159 #include <machine/md_var.h>
160 #include <machine/pcb.h>
161 #include <machine/specialreg.h>
163 #include <machine/smp.h>
165 #include <machine/sysarch.h>
166 #include <machine/tss.h>
169 #define PMAP_MEMDOM MAXMEMDOM
171 #define PMAP_MEMDOM 1
174 static __inline boolean_t
175 pmap_type_guest(pmap_t pmap)
178 return ((pmap->pm_type == PT_EPT) || (pmap->pm_type == PT_RVI));
181 static __inline boolean_t
182 pmap_emulate_ad_bits(pmap_t pmap)
185 return ((pmap->pm_flags & PMAP_EMULATE_AD_BITS) != 0);
188 static __inline pt_entry_t
189 pmap_valid_bit(pmap_t pmap)
193 switch (pmap->pm_type) {
199 if (pmap_emulate_ad_bits(pmap))
200 mask = EPT_PG_EMUL_V;
205 panic("pmap_valid_bit: invalid pm_type %d", pmap->pm_type);
211 static __inline pt_entry_t
212 pmap_rw_bit(pmap_t pmap)
216 switch (pmap->pm_type) {
222 if (pmap_emulate_ad_bits(pmap))
223 mask = EPT_PG_EMUL_RW;
228 panic("pmap_rw_bit: invalid pm_type %d", pmap->pm_type);
234 static pt_entry_t pg_g;
236 static __inline pt_entry_t
237 pmap_global_bit(pmap_t pmap)
241 switch (pmap->pm_type) {
250 panic("pmap_global_bit: invalid pm_type %d", pmap->pm_type);
256 static __inline pt_entry_t
257 pmap_accessed_bit(pmap_t pmap)
261 switch (pmap->pm_type) {
267 if (pmap_emulate_ad_bits(pmap))
273 panic("pmap_accessed_bit: invalid pm_type %d", pmap->pm_type);
279 static __inline pt_entry_t
280 pmap_modified_bit(pmap_t pmap)
284 switch (pmap->pm_type) {
290 if (pmap_emulate_ad_bits(pmap))
296 panic("pmap_modified_bit: invalid pm_type %d", pmap->pm_type);
302 static __inline pt_entry_t
303 pmap_pku_mask_bit(pmap_t pmap)
306 return (pmap->pm_type == PT_X86 ? X86_PG_PKU_MASK : 0);
309 #if !defined(DIAGNOSTIC)
310 #ifdef __GNUC_GNU_INLINE__
311 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
313 #define PMAP_INLINE extern inline
320 #define PV_STAT(x) do { x ; } while (0)
322 #define PV_STAT(x) do { } while (0)
327 #define pa_index(pa) ({ \
328 KASSERT((pa) <= vm_phys_segs[vm_phys_nsegs - 1].end, \
329 ("address %lx beyond the last segment", (pa))); \
332 #define pa_to_pmdp(pa) (&pv_table[pa_index(pa)])
333 #define pa_to_pvh(pa) (&(pa_to_pmdp(pa)->pv_page))
334 #define PHYS_TO_PV_LIST_LOCK(pa) ({ \
335 struct rwlock *_lock; \
336 if (__predict_false((pa) > pmap_last_pa)) \
337 _lock = &pv_dummy_large.pv_lock; \
339 _lock = &(pa_to_pmdp(pa)->pv_lock); \
343 #define pa_index(pa) ((pa) >> PDRSHIFT)
344 #define pa_to_pvh(pa) (&pv_table[pa_index(pa)])
346 #define NPV_LIST_LOCKS MAXCPU
348 #define PHYS_TO_PV_LIST_LOCK(pa) \
349 (&pv_list_locks[pa_index(pa) % NPV_LIST_LOCKS])
352 #define CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa) do { \
353 struct rwlock **_lockp = (lockp); \
354 struct rwlock *_new_lock; \
356 _new_lock = PHYS_TO_PV_LIST_LOCK(pa); \
357 if (_new_lock != *_lockp) { \
358 if (*_lockp != NULL) \
359 rw_wunlock(*_lockp); \
360 *_lockp = _new_lock; \
365 #define CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m) \
366 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, VM_PAGE_TO_PHYS(m))
368 #define RELEASE_PV_LIST_LOCK(lockp) do { \
369 struct rwlock **_lockp = (lockp); \
371 if (*_lockp != NULL) { \
372 rw_wunlock(*_lockp); \
377 #define VM_PAGE_TO_PV_LIST_LOCK(m) \
378 PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m))
380 struct pmap kernel_pmap_store;
382 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
383 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
386 SYSCTL_INT(_machdep, OID_AUTO, nkpt, CTLFLAG_RD, &nkpt, 0,
387 "Number of kernel page table pages allocated on bootup");
390 vm_paddr_t dmaplimit;
391 vm_offset_t kernel_vm_end = VM_MIN_KERNEL_ADDRESS;
394 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
395 "VM/pmap parameters");
397 static int pg_ps_enabled = 1;
398 SYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
399 &pg_ps_enabled, 0, "Are large page mappings enabled?");
401 #define PAT_INDEX_SIZE 8
402 static int pat_index[PAT_INDEX_SIZE]; /* cache mode to PAT index conversion */
404 static u_int64_t KPTphys; /* phys addr of kernel level 1 */
405 static u_int64_t KPDphys; /* phys addr of kernel level 2 */
406 u_int64_t KPDPphys; /* phys addr of kernel level 3 */
407 u_int64_t KPML4phys; /* phys addr of kernel level 4 */
409 static u_int64_t DMPDphys; /* phys addr of direct mapped level 2 */
410 static u_int64_t DMPDPphys; /* phys addr of direct mapped level 3 */
411 static int ndmpdpphys; /* number of DMPDPphys pages */
413 static vm_paddr_t KERNend; /* phys addr of end of bootstrap data */
416 * pmap_mapdev support pre initialization (i.e. console)
418 #define PMAP_PREINIT_MAPPING_COUNT 8
419 static struct pmap_preinit_mapping {
424 } pmap_preinit_mapping[PMAP_PREINIT_MAPPING_COUNT];
425 static int pmap_initialized;
428 * Data for the pv entry allocation mechanism.
429 * Updates to pv_invl_gen are protected by the pv list lock but reads are not.
433 pc_to_domain(struct pv_chunk *pc)
436 return (_vm_phys_domain(DMAP_TO_PHYS((vm_offset_t)pc)));
440 pc_to_domain(struct pv_chunk *pc __unused)
447 struct pv_chunks_list {
449 TAILQ_HEAD(pch, pv_chunk) pvc_list;
451 } __aligned(CACHE_LINE_SIZE);
453 struct pv_chunks_list __exclusive_cache_line pv_chunks[PMAP_MEMDOM];
456 struct pmap_large_md_page {
457 struct rwlock pv_lock;
458 struct md_page pv_page;
461 __exclusive_cache_line static struct pmap_large_md_page pv_dummy_large;
462 #define pv_dummy pv_dummy_large.pv_page
463 __read_mostly static struct pmap_large_md_page *pv_table;
464 __read_mostly vm_paddr_t pmap_last_pa;
466 static struct rwlock __exclusive_cache_line pv_list_locks[NPV_LIST_LOCKS];
467 static u_long pv_invl_gen[NPV_LIST_LOCKS];
468 static struct md_page *pv_table;
469 static struct md_page pv_dummy;
473 * All those kernel PT submaps that BSD is so fond of
475 pt_entry_t *CMAP1 = NULL;
477 static vm_offset_t qframe = 0;
478 static struct mtx qframe_mtx;
480 static int pmap_flags = PMAP_PDE_SUPERPAGE; /* flags for x86 pmaps */
482 static vmem_t *large_vmem;
483 static u_int lm_ents;
484 #define PMAP_ADDRESS_IN_LARGEMAP(va) ((va) >= LARGEMAP_MIN_ADDRESS && \
485 (va) < LARGEMAP_MIN_ADDRESS + NBPML4 * (u_long)lm_ents)
487 int pmap_pcid_enabled = 1;
488 SYSCTL_INT(_vm_pmap, OID_AUTO, pcid_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
489 &pmap_pcid_enabled, 0, "Is TLB Context ID enabled ?");
490 int invpcid_works = 0;
491 SYSCTL_INT(_vm_pmap, OID_AUTO, invpcid_works, CTLFLAG_RD, &invpcid_works, 0,
492 "Is the invpcid instruction available ?");
494 int __read_frequently pti = 0;
495 SYSCTL_INT(_vm_pmap, OID_AUTO, pti, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
497 "Page Table Isolation enabled");
498 static vm_object_t pti_obj;
499 static pml4_entry_t *pti_pml4;
500 static vm_pindex_t pti_pg_idx;
501 static bool pti_finalized;
503 struct pmap_pkru_range {
504 struct rs_el pkru_rs_el;
509 static uma_zone_t pmap_pkru_ranges_zone;
510 static bool pmap_pkru_same(pmap_t pmap, vm_offset_t sva, vm_offset_t eva);
511 static pt_entry_t pmap_pkru_get(pmap_t pmap, vm_offset_t va);
512 static void pmap_pkru_on_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva);
513 static void *pkru_dup_range(void *ctx, void *data);
514 static void pkru_free_range(void *ctx, void *node);
515 static int pmap_pkru_copy(pmap_t dst_pmap, pmap_t src_pmap);
516 static int pmap_pkru_deassign(pmap_t pmap, vm_offset_t sva, vm_offset_t eva);
517 static void pmap_pkru_deassign_all(pmap_t pmap);
520 pmap_pcid_save_cnt_proc(SYSCTL_HANDLER_ARGS)
527 res += cpuid_to_pcpu[i]->pc_pm_save_cnt;
529 return (sysctl_handle_64(oidp, &res, 0, req));
531 SYSCTL_PROC(_vm_pmap, OID_AUTO, pcid_save_cnt, CTLTYPE_U64 | CTLFLAG_RD |
532 CTLFLAG_MPSAFE, NULL, 0, pmap_pcid_save_cnt_proc, "QU",
533 "Count of saved TLB context on switch");
535 static LIST_HEAD(, pmap_invl_gen) pmap_invl_gen_tracker =
536 LIST_HEAD_INITIALIZER(&pmap_invl_gen_tracker);
537 static struct mtx invl_gen_mtx;
538 /* Fake lock object to satisfy turnstiles interface. */
539 static struct lock_object invl_gen_ts = {
542 static struct pmap_invl_gen pmap_invl_gen_head = {
546 static u_long pmap_invl_gen = 1;
547 static int pmap_invl_waiters;
548 static struct callout pmap_invl_callout;
549 static bool pmap_invl_callout_inited;
551 #define PMAP_ASSERT_NOT_IN_DI() \
552 KASSERT(pmap_not_in_di(), ("DI already started"))
559 if ((cpu_feature2 & CPUID2_CX16) == 0)
562 TUNABLE_INT_FETCH("vm.pmap.di_locked", &tun);
567 sysctl_pmap_di_locked(SYSCTL_HANDLER_ARGS)
571 locked = pmap_di_locked();
572 return (sysctl_handle_int(oidp, &locked, 0, req));
574 SYSCTL_PROC(_vm_pmap, OID_AUTO, di_locked, CTLTYPE_INT | CTLFLAG_RDTUN |
575 CTLFLAG_MPSAFE, 0, 0, sysctl_pmap_di_locked, "",
576 "Locked delayed invalidation");
578 static bool pmap_not_in_di_l(void);
579 static bool pmap_not_in_di_u(void);
580 DEFINE_IFUNC(, bool, pmap_not_in_di, (void))
583 return (pmap_di_locked() ? pmap_not_in_di_l : pmap_not_in_di_u);
587 pmap_not_in_di_l(void)
589 struct pmap_invl_gen *invl_gen;
591 invl_gen = &curthread->td_md.md_invl_gen;
592 return (invl_gen->gen == 0);
596 pmap_thread_init_invl_gen_l(struct thread *td)
598 struct pmap_invl_gen *invl_gen;
600 invl_gen = &td->td_md.md_invl_gen;
605 pmap_delayed_invl_wait_block(u_long *m_gen, u_long *invl_gen)
607 struct turnstile *ts;
609 ts = turnstile_trywait(&invl_gen_ts);
610 if (*m_gen > atomic_load_long(invl_gen))
611 turnstile_wait(ts, NULL, TS_SHARED_QUEUE);
613 turnstile_cancel(ts);
617 pmap_delayed_invl_finish_unblock(u_long new_gen)
619 struct turnstile *ts;
621 turnstile_chain_lock(&invl_gen_ts);
622 ts = turnstile_lookup(&invl_gen_ts);
624 pmap_invl_gen = new_gen;
626 turnstile_broadcast(ts, TS_SHARED_QUEUE);
627 turnstile_unpend(ts);
629 turnstile_chain_unlock(&invl_gen_ts);
633 * Start a new Delayed Invalidation (DI) block of code, executed by
634 * the current thread. Within a DI block, the current thread may
635 * destroy both the page table and PV list entries for a mapping and
636 * then release the corresponding PV list lock before ensuring that
637 * the mapping is flushed from the TLBs of any processors with the
641 pmap_delayed_invl_start_l(void)
643 struct pmap_invl_gen *invl_gen;
646 invl_gen = &curthread->td_md.md_invl_gen;
647 PMAP_ASSERT_NOT_IN_DI();
648 mtx_lock(&invl_gen_mtx);
649 if (LIST_EMPTY(&pmap_invl_gen_tracker))
650 currgen = pmap_invl_gen;
652 currgen = LIST_FIRST(&pmap_invl_gen_tracker)->gen;
653 invl_gen->gen = currgen + 1;
654 LIST_INSERT_HEAD(&pmap_invl_gen_tracker, invl_gen, link);
655 mtx_unlock(&invl_gen_mtx);
659 * Finish the DI block, previously started by the current thread. All
660 * required TLB flushes for the pages marked by
661 * pmap_delayed_invl_page() must be finished before this function is
664 * This function works by bumping the global DI generation number to
665 * the generation number of the current thread's DI, unless there is a
666 * pending DI that started earlier. In the latter case, bumping the
667 * global DI generation number would incorrectly signal that the
668 * earlier DI had finished. Instead, this function bumps the earlier
669 * DI's generation number to match the generation number of the
670 * current thread's DI.
673 pmap_delayed_invl_finish_l(void)
675 struct pmap_invl_gen *invl_gen, *next;
677 invl_gen = &curthread->td_md.md_invl_gen;
678 KASSERT(invl_gen->gen != 0, ("missed invl_start"));
679 mtx_lock(&invl_gen_mtx);
680 next = LIST_NEXT(invl_gen, link);
682 pmap_delayed_invl_finish_unblock(invl_gen->gen);
684 next->gen = invl_gen->gen;
685 LIST_REMOVE(invl_gen, link);
686 mtx_unlock(&invl_gen_mtx);
691 pmap_not_in_di_u(void)
693 struct pmap_invl_gen *invl_gen;
695 invl_gen = &curthread->td_md.md_invl_gen;
696 return (((uintptr_t)invl_gen->next & PMAP_INVL_GEN_NEXT_INVALID) != 0);
700 pmap_thread_init_invl_gen_u(struct thread *td)
702 struct pmap_invl_gen *invl_gen;
704 invl_gen = &td->td_md.md_invl_gen;
706 invl_gen->next = (void *)PMAP_INVL_GEN_NEXT_INVALID;
710 pmap_di_load_invl(struct pmap_invl_gen *ptr, struct pmap_invl_gen *out)
712 uint64_t new_high, new_low, old_high, old_low;
715 old_low = new_low = 0;
716 old_high = new_high = (uintptr_t)0;
718 __asm volatile("lock;cmpxchg16b\t%1"
719 : "=@cce" (res), "+m" (*ptr), "+a" (old_low), "+d" (old_high)
720 : "b"(new_low), "c" (new_high)
723 if ((old_high & PMAP_INVL_GEN_NEXT_INVALID) != 0)
726 out->next = (void *)old_high;
729 out->next = (void *)new_high;
735 pmap_di_store_invl(struct pmap_invl_gen *ptr, struct pmap_invl_gen *old_val,
736 struct pmap_invl_gen *new_val)
738 uint64_t new_high, new_low, old_high, old_low;
741 new_low = new_val->gen;
742 new_high = (uintptr_t)new_val->next;
743 old_low = old_val->gen;
744 old_high = (uintptr_t)old_val->next;
746 __asm volatile("lock;cmpxchg16b\t%1"
747 : "=@cce" (res), "+m" (*ptr), "+a" (old_low), "+d" (old_high)
748 : "b"(new_low), "c" (new_high)
754 static long invl_start_restart;
755 SYSCTL_LONG(_vm_pmap, OID_AUTO, invl_start_restart, CTLFLAG_RD,
756 &invl_start_restart, 0,
758 static long invl_finish_restart;
759 SYSCTL_LONG(_vm_pmap, OID_AUTO, invl_finish_restart, CTLFLAG_RD,
760 &invl_finish_restart, 0,
762 static int invl_max_qlen;
763 SYSCTL_INT(_vm_pmap, OID_AUTO, invl_max_qlen, CTLFLAG_RD,
768 #define di_delay locks_delay
771 pmap_delayed_invl_start_u(void)
773 struct pmap_invl_gen *invl_gen, *p, prev, new_prev;
775 struct lock_delay_arg lda;
783 invl_gen = &td->td_md.md_invl_gen;
784 PMAP_ASSERT_NOT_IN_DI();
785 lock_delay_arg_init(&lda, &di_delay);
786 invl_gen->saved_pri = 0;
787 pri = td->td_base_pri;
790 pri = td->td_base_pri;
792 invl_gen->saved_pri = pri;
799 for (p = &pmap_invl_gen_head;; p = prev.next) {
801 prevl = (uintptr_t)atomic_load_ptr(&p->next);
802 if ((prevl & PMAP_INVL_GEN_NEXT_INVALID) != 0) {
803 PV_STAT(atomic_add_long(&invl_start_restart, 1));
809 prev.next = (void *)prevl;
812 if ((ii = invl_max_qlen) < i)
813 atomic_cmpset_int(&invl_max_qlen, ii, i);
816 if (!pmap_di_load_invl(p, &prev) || prev.next != NULL) {
817 PV_STAT(atomic_add_long(&invl_start_restart, 1));
822 new_prev.gen = prev.gen;
823 new_prev.next = invl_gen;
824 invl_gen->gen = prev.gen + 1;
826 /* Formal fence between store to invl->gen and updating *p. */
827 atomic_thread_fence_rel();
830 * After inserting an invl_gen element with invalid bit set,
831 * this thread blocks any other thread trying to enter the
832 * delayed invalidation block. Do not allow to remove us from
833 * the CPU, because it causes starvation for other threads.
838 * ABA for *p is not possible there, since p->gen can only
839 * increase. So if the *p thread finished its di, then
840 * started a new one and got inserted into the list at the
841 * same place, its gen will appear greater than the previously
844 if (!pmap_di_store_invl(p, &prev, &new_prev)) {
846 PV_STAT(atomic_add_long(&invl_start_restart, 1));
852 * There we clear PMAP_INVL_GEN_NEXT_INVALID in
853 * invl_gen->next, allowing other threads to iterate past us.
854 * pmap_di_store_invl() provides fence between the generation
855 * write and the update of next.
857 invl_gen->next = NULL;
862 pmap_delayed_invl_finish_u_crit(struct pmap_invl_gen *invl_gen,
863 struct pmap_invl_gen *p)
865 struct pmap_invl_gen prev, new_prev;
869 * Load invl_gen->gen after setting invl_gen->next
870 * PMAP_INVL_GEN_NEXT_INVALID. This prevents larger
871 * generations to propagate to our invl_gen->gen. Lock prefix
872 * in atomic_set_ptr() worked as seq_cst fence.
874 mygen = atomic_load_long(&invl_gen->gen);
876 if (!pmap_di_load_invl(p, &prev) || prev.next != invl_gen)
879 KASSERT(prev.gen < mygen,
880 ("invalid di gen sequence %lu %lu", prev.gen, mygen));
881 new_prev.gen = mygen;
882 new_prev.next = (void *)((uintptr_t)invl_gen->next &
883 ~PMAP_INVL_GEN_NEXT_INVALID);
885 /* Formal fence between load of prev and storing update to it. */
886 atomic_thread_fence_rel();
888 return (pmap_di_store_invl(p, &prev, &new_prev));
892 pmap_delayed_invl_finish_u(void)
894 struct pmap_invl_gen *invl_gen, *p;
896 struct lock_delay_arg lda;
900 invl_gen = &td->td_md.md_invl_gen;
901 KASSERT(invl_gen->gen != 0, ("missed invl_start: gen 0"));
902 KASSERT(((uintptr_t)invl_gen->next & PMAP_INVL_GEN_NEXT_INVALID) == 0,
903 ("missed invl_start: INVALID"));
904 lock_delay_arg_init(&lda, &di_delay);
907 for (p = &pmap_invl_gen_head; p != NULL; p = (void *)prevl) {
908 prevl = (uintptr_t)atomic_load_ptr(&p->next);
909 if ((prevl & PMAP_INVL_GEN_NEXT_INVALID) != 0) {
910 PV_STAT(atomic_add_long(&invl_finish_restart, 1));
914 if ((void *)prevl == invl_gen)
919 * It is legitimate to not find ourself on the list if a
920 * thread before us finished its DI and started it again.
922 if (__predict_false(p == NULL)) {
923 PV_STAT(atomic_add_long(&invl_finish_restart, 1));
929 atomic_set_ptr((uintptr_t *)&invl_gen->next,
930 PMAP_INVL_GEN_NEXT_INVALID);
931 if (!pmap_delayed_invl_finish_u_crit(invl_gen, p)) {
932 atomic_clear_ptr((uintptr_t *)&invl_gen->next,
933 PMAP_INVL_GEN_NEXT_INVALID);
935 PV_STAT(atomic_add_long(&invl_finish_restart, 1));
940 if (atomic_load_int(&pmap_invl_waiters) > 0)
941 pmap_delayed_invl_finish_unblock(0);
942 if (invl_gen->saved_pri != 0) {
944 sched_prio(td, invl_gen->saved_pri);
950 DB_SHOW_COMMAND(di_queue, pmap_di_queue)
952 struct pmap_invl_gen *p, *pn;
957 for (p = &pmap_invl_gen_head, first = true; p != NULL; p = pn,
959 nextl = (uintptr_t)atomic_load_ptr(&p->next);
960 pn = (void *)(nextl & ~PMAP_INVL_GEN_NEXT_INVALID);
961 td = first ? NULL : __containerof(p, struct thread,
963 db_printf("gen %lu inv %d td %p tid %d\n", p->gen,
964 (nextl & PMAP_INVL_GEN_NEXT_INVALID) != 0, td,
965 td != NULL ? td->td_tid : -1);
971 static long invl_wait;
972 SYSCTL_LONG(_vm_pmap, OID_AUTO, invl_wait, CTLFLAG_RD, &invl_wait, 0,
973 "Number of times DI invalidation blocked pmap_remove_all/write");
974 static long invl_wait_slow;
975 SYSCTL_LONG(_vm_pmap, OID_AUTO, invl_wait_slow, CTLFLAG_RD, &invl_wait_slow, 0,
976 "Number of slow invalidation waits for lockless DI");
981 pmap_delayed_invl_genp(vm_page_t m)
986 pa = VM_PAGE_TO_PHYS(m);
987 if (__predict_false((pa) > pmap_last_pa))
988 gen = &pv_dummy_large.pv_invl_gen;
990 gen = &(pa_to_pmdp(pa)->pv_invl_gen);
996 pmap_delayed_invl_genp(vm_page_t m)
999 return (&pv_invl_gen[pa_index(VM_PAGE_TO_PHYS(m)) % NPV_LIST_LOCKS]);
1004 pmap_delayed_invl_callout_func(void *arg __unused)
1007 if (atomic_load_int(&pmap_invl_waiters) == 0)
1009 pmap_delayed_invl_finish_unblock(0);
1013 pmap_delayed_invl_callout_init(void *arg __unused)
1016 if (pmap_di_locked())
1018 callout_init(&pmap_invl_callout, 1);
1019 pmap_invl_callout_inited = true;
1021 SYSINIT(pmap_di_callout, SI_SUB_CPU + 1, SI_ORDER_ANY,
1022 pmap_delayed_invl_callout_init, NULL);
1025 * Ensure that all currently executing DI blocks, that need to flush
1026 * TLB for the given page m, actually flushed the TLB at the time the
1027 * function returned. If the page m has an empty PV list and we call
1028 * pmap_delayed_invl_wait(), upon its return we know that no CPU has a
1029 * valid mapping for the page m in either its page table or TLB.
1031 * This function works by blocking until the global DI generation
1032 * number catches up with the generation number associated with the
1033 * given page m and its PV list. Since this function's callers
1034 * typically own an object lock and sometimes own a page lock, it
1035 * cannot sleep. Instead, it blocks on a turnstile to relinquish the
1039 pmap_delayed_invl_wait_l(vm_page_t m)
1043 bool accounted = false;
1046 m_gen = pmap_delayed_invl_genp(m);
1047 while (*m_gen > pmap_invl_gen) {
1050 atomic_add_long(&invl_wait, 1);
1054 pmap_delayed_invl_wait_block(m_gen, &pmap_invl_gen);
1059 pmap_delayed_invl_wait_u(vm_page_t m)
1062 struct lock_delay_arg lda;
1066 m_gen = pmap_delayed_invl_genp(m);
1067 lock_delay_arg_init(&lda, &di_delay);
1068 while (*m_gen > atomic_load_long(&pmap_invl_gen_head.gen)) {
1069 if (fast || !pmap_invl_callout_inited) {
1070 PV_STAT(atomic_add_long(&invl_wait, 1));
1075 * The page's invalidation generation number
1076 * is still below the current thread's number.
1077 * Prepare to block so that we do not waste
1078 * CPU cycles or worse, suffer livelock.
1080 * Since it is impossible to block without
1081 * racing with pmap_delayed_invl_finish_u(),
1082 * prepare for the race by incrementing
1083 * pmap_invl_waiters and arming a 1-tick
1084 * callout which will unblock us if we lose
1087 atomic_add_int(&pmap_invl_waiters, 1);
1090 * Re-check the current thread's invalidation
1091 * generation after incrementing
1092 * pmap_invl_waiters, so that there is no race
1093 * with pmap_delayed_invl_finish_u() setting
1094 * the page generation and checking
1095 * pmap_invl_waiters. The only race allowed
1096 * is for a missed unblock, which is handled
1100 atomic_load_long(&pmap_invl_gen_head.gen)) {
1101 callout_reset(&pmap_invl_callout, 1,
1102 pmap_delayed_invl_callout_func, NULL);
1103 PV_STAT(atomic_add_long(&invl_wait_slow, 1));
1104 pmap_delayed_invl_wait_block(m_gen,
1105 &pmap_invl_gen_head.gen);
1107 atomic_add_int(&pmap_invl_waiters, -1);
1112 DEFINE_IFUNC(, void, pmap_thread_init_invl_gen, (struct thread *))
1115 return (pmap_di_locked() ? pmap_thread_init_invl_gen_l :
1116 pmap_thread_init_invl_gen_u);
1119 DEFINE_IFUNC(static, void, pmap_delayed_invl_start, (void))
1122 return (pmap_di_locked() ? pmap_delayed_invl_start_l :
1123 pmap_delayed_invl_start_u);
1126 DEFINE_IFUNC(static, void, pmap_delayed_invl_finish, (void))
1129 return (pmap_di_locked() ? pmap_delayed_invl_finish_l :
1130 pmap_delayed_invl_finish_u);
1133 DEFINE_IFUNC(static, void, pmap_delayed_invl_wait, (vm_page_t))
1136 return (pmap_di_locked() ? pmap_delayed_invl_wait_l :
1137 pmap_delayed_invl_wait_u);
1141 * Mark the page m's PV list as participating in the current thread's
1142 * DI block. Any threads concurrently using m's PV list to remove or
1143 * restrict all mappings to m will wait for the current thread's DI
1144 * block to complete before proceeding.
1146 * The function works by setting the DI generation number for m's PV
1147 * list to at least the DI generation number of the current thread.
1148 * This forces a caller of pmap_delayed_invl_wait() to block until
1149 * current thread calls pmap_delayed_invl_finish().
1152 pmap_delayed_invl_page(vm_page_t m)
1156 rw_assert(VM_PAGE_TO_PV_LIST_LOCK(m), RA_WLOCKED);
1157 gen = curthread->td_md.md_invl_gen.gen;
1160 m_gen = pmap_delayed_invl_genp(m);
1168 static caddr_t crashdumpmap;
1171 * Internal flags for pmap_enter()'s helper functions.
1173 #define PMAP_ENTER_NORECLAIM 0x1000000 /* Don't reclaim PV entries. */
1174 #define PMAP_ENTER_NOREPLACE 0x2000000 /* Don't replace mappings. */
1177 * Internal flags for pmap_mapdev_internal() and
1178 * pmap_change_props_locked().
1180 #define MAPDEV_FLUSHCACHE 0x00000001 /* Flush cache after mapping. */
1181 #define MAPDEV_SETATTR 0x00000002 /* Modify existing attrs. */
1182 #define MAPDEV_ASSERTVALID 0x00000004 /* Assert mapping validity. */
1184 TAILQ_HEAD(pv_chunklist, pv_chunk);
1186 static void free_pv_chunk(struct pv_chunk *pc);
1187 static void free_pv_chunk_batch(struct pv_chunklist *batch);
1188 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
1189 static pv_entry_t get_pv_entry(pmap_t pmap, struct rwlock **lockp);
1190 static int popcnt_pc_map_pq(uint64_t *map);
1191 static vm_page_t reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp);
1192 static void reserve_pv_entries(pmap_t pmap, int needed,
1193 struct rwlock **lockp);
1194 static void pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
1195 struct rwlock **lockp);
1196 static bool pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, pd_entry_t pde,
1197 u_int flags, struct rwlock **lockp);
1198 #if VM_NRESERVLEVEL > 0
1199 static void pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
1200 struct rwlock **lockp);
1202 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
1203 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
1206 static void pmap_abort_ptp(pmap_t pmap, vm_offset_t va, vm_page_t mpte);
1207 static int pmap_change_props_locked(vm_offset_t va, vm_size_t size,
1208 vm_prot_t prot, int mode, int flags);
1209 static boolean_t pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
1210 static boolean_t pmap_demote_pde_locked(pmap_t pmap, pd_entry_t *pde,
1211 vm_offset_t va, struct rwlock **lockp);
1212 static boolean_t pmap_demote_pdpe(pmap_t pmap, pdp_entry_t *pdpe,
1214 static bool pmap_enter_2mpage(pmap_t pmap, vm_offset_t va, vm_page_t m,
1215 vm_prot_t prot, struct rwlock **lockp);
1216 static int pmap_enter_pde(pmap_t pmap, vm_offset_t va, pd_entry_t newpde,
1217 u_int flags, vm_page_t m, struct rwlock **lockp);
1218 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
1219 vm_page_t m, vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp);
1220 static void pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte);
1221 static int pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte, bool promoted);
1222 static void pmap_invalidate_cache_range_selfsnoop(vm_offset_t sva,
1224 static void pmap_invalidate_cache_range_all(vm_offset_t sva,
1226 static void pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va,
1228 static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode);
1229 static vm_page_t pmap_large_map_getptp_unlocked(void);
1230 static vm_paddr_t pmap_large_map_kextract(vm_offset_t va);
1231 #if VM_NRESERVLEVEL > 0
1232 static void pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
1233 struct rwlock **lockp);
1235 static boolean_t pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva,
1237 static void pmap_pte_props(pt_entry_t *pte, u_long bits, u_long mask);
1238 static void pmap_pti_add_kva_locked(vm_offset_t sva, vm_offset_t eva,
1240 static pdp_entry_t *pmap_pti_pdpe(vm_offset_t va);
1241 static pd_entry_t *pmap_pti_pde(vm_offset_t va);
1242 static void pmap_pti_wire_pte(void *pte);
1243 static int pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
1244 struct spglist *free, struct rwlock **lockp);
1245 static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva,
1246 pd_entry_t ptepde, struct spglist *free, struct rwlock **lockp);
1247 static vm_page_t pmap_remove_pt_page(pmap_t pmap, vm_offset_t va);
1248 static void pmap_remove_page(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
1249 struct spglist *free);
1250 static bool pmap_remove_ptes(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
1251 pd_entry_t *pde, struct spglist *free,
1252 struct rwlock **lockp);
1253 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
1254 vm_page_t m, struct rwlock **lockp);
1255 static void pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
1257 static void pmap_update_pde_invalidate(pmap_t, vm_offset_t va, pd_entry_t pde);
1259 static vm_page_t _pmap_allocpte(pmap_t pmap, vm_pindex_t ptepindex,
1260 struct rwlock **lockp);
1261 static pd_entry_t *pmap_alloc_pde(pmap_t pmap, vm_offset_t va, vm_page_t *pdpgp,
1262 struct rwlock **lockp);
1263 static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va,
1264 struct rwlock **lockp);
1266 static void _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m,
1267 struct spglist *free);
1268 static int pmap_unuse_pt(pmap_t, vm_offset_t, pd_entry_t, struct spglist *);
1270 /********************/
1271 /* Inline functions */
1272 /********************/
1274 /* Return a non-clipped PD index for a given VA */
1275 static __inline vm_pindex_t
1276 pmap_pde_pindex(vm_offset_t va)
1278 return (va >> PDRSHIFT);
1282 /* Return a pointer to the PML4 slot that corresponds to a VA */
1283 static __inline pml4_entry_t *
1284 pmap_pml4e(pmap_t pmap, vm_offset_t va)
1287 return (&pmap->pm_pml4[pmap_pml4e_index(va)]);
1290 /* Return a pointer to the PDP slot that corresponds to a VA */
1291 static __inline pdp_entry_t *
1292 pmap_pml4e_to_pdpe(pml4_entry_t *pml4e, vm_offset_t va)
1296 pdpe = (pdp_entry_t *)PHYS_TO_DMAP(*pml4e & PG_FRAME);
1297 return (&pdpe[pmap_pdpe_index(va)]);
1300 /* Return a pointer to the PDP slot that corresponds to a VA */
1301 static __inline pdp_entry_t *
1302 pmap_pdpe(pmap_t pmap, vm_offset_t va)
1304 pml4_entry_t *pml4e;
1307 PG_V = pmap_valid_bit(pmap);
1308 pml4e = pmap_pml4e(pmap, va);
1309 if ((*pml4e & PG_V) == 0)
1311 return (pmap_pml4e_to_pdpe(pml4e, va));
1314 /* Return a pointer to the PD slot that corresponds to a VA */
1315 static __inline pd_entry_t *
1316 pmap_pdpe_to_pde(pdp_entry_t *pdpe, vm_offset_t va)
1320 KASSERT((*pdpe & PG_PS) == 0,
1321 ("%s: pdpe %#lx is a leaf", __func__, *pdpe));
1322 pde = (pd_entry_t *)PHYS_TO_DMAP(*pdpe & PG_FRAME);
1323 return (&pde[pmap_pde_index(va)]);
1326 /* Return a pointer to the PD slot that corresponds to a VA */
1327 static __inline pd_entry_t *
1328 pmap_pde(pmap_t pmap, vm_offset_t va)
1333 PG_V = pmap_valid_bit(pmap);
1334 pdpe = pmap_pdpe(pmap, va);
1335 if (pdpe == NULL || (*pdpe & PG_V) == 0)
1337 return (pmap_pdpe_to_pde(pdpe, va));
1340 /* Return a pointer to the PT slot that corresponds to a VA */
1341 static __inline pt_entry_t *
1342 pmap_pde_to_pte(pd_entry_t *pde, vm_offset_t va)
1346 KASSERT((*pde & PG_PS) == 0,
1347 ("%s: pde %#lx is a leaf", __func__, *pde));
1348 pte = (pt_entry_t *)PHYS_TO_DMAP(*pde & PG_FRAME);
1349 return (&pte[pmap_pte_index(va)]);
1352 /* Return a pointer to the PT slot that corresponds to a VA */
1353 static __inline pt_entry_t *
1354 pmap_pte(pmap_t pmap, vm_offset_t va)
1359 PG_V = pmap_valid_bit(pmap);
1360 pde = pmap_pde(pmap, va);
1361 if (pde == NULL || (*pde & PG_V) == 0)
1363 if ((*pde & PG_PS) != 0) /* compat with i386 pmap_pte() */
1364 return ((pt_entry_t *)pde);
1365 return (pmap_pde_to_pte(pde, va));
1368 static __inline void
1369 pmap_resident_count_inc(pmap_t pmap, int count)
1372 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1373 pmap->pm_stats.resident_count += count;
1376 static __inline void
1377 pmap_resident_count_dec(pmap_t pmap, int count)
1380 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1381 KASSERT(pmap->pm_stats.resident_count >= count,
1382 ("pmap %p resident count underflow %ld %d", pmap,
1383 pmap->pm_stats.resident_count, count));
1384 pmap->pm_stats.resident_count -= count;
1387 PMAP_INLINE pt_entry_t *
1388 vtopte(vm_offset_t va)
1390 u_int64_t mask = ((1ul << (NPTEPGSHIFT + NPDEPGSHIFT + NPDPEPGSHIFT + NPML4EPGSHIFT)) - 1);
1392 KASSERT(va >= VM_MAXUSER_ADDRESS, ("vtopte on a uva/gpa 0x%0lx", va));
1394 return (PTmap + ((va >> PAGE_SHIFT) & mask));
1397 static __inline pd_entry_t *
1398 vtopde(vm_offset_t va)
1400 u_int64_t mask = ((1ul << (NPDEPGSHIFT + NPDPEPGSHIFT + NPML4EPGSHIFT)) - 1);
1402 KASSERT(va >= VM_MAXUSER_ADDRESS, ("vtopde on a uva/gpa 0x%0lx", va));
1404 return (PDmap + ((va >> PDRSHIFT) & mask));
1408 allocpages(vm_paddr_t *firstaddr, int n)
1413 bzero((void *)ret, n * PAGE_SIZE);
1414 *firstaddr += n * PAGE_SIZE;
1418 CTASSERT(powerof2(NDMPML4E));
1420 /* number of kernel PDP slots */
1421 #define NKPDPE(ptpgs) howmany(ptpgs, NPDEPG)
1424 nkpt_init(vm_paddr_t addr)
1431 pt_pages = howmany(addr, 1 << PDRSHIFT);
1432 pt_pages += NKPDPE(pt_pages);
1435 * Add some slop beyond the bare minimum required for bootstrapping
1438 * This is quite important when allocating KVA for kernel modules.
1439 * The modules are required to be linked in the negative 2GB of
1440 * the address space. If we run out of KVA in this region then
1441 * pmap_growkernel() will need to allocate page table pages to map
1442 * the entire 512GB of KVA space which is an unnecessary tax on
1445 * Secondly, device memory mapped as part of setting up the low-
1446 * level console(s) is taken from KVA, starting at virtual_avail.
1447 * This is because cninit() is called after pmap_bootstrap() but
1448 * before vm_init() and pmap_init(). 20MB for a frame buffer is
1451 pt_pages += 32; /* 64MB additional slop. */
1457 * Returns the proper write/execute permission for a physical page that is
1458 * part of the initial boot allocations.
1460 * If the page has kernel text, it is marked as read-only. If the page has
1461 * kernel read-only data, it is marked as read-only/not-executable. If the
1462 * page has only read-write data, it is marked as read-write/not-executable.
1463 * If the page is below/above the kernel range, it is marked as read-write.
1465 * This function operates on 2M pages, since we map the kernel space that
1468 static inline pt_entry_t
1469 bootaddr_rwx(vm_paddr_t pa)
1473 * The kernel is loaded at a 2MB-aligned address, and memory below that
1474 * need not be executable. The .bss section is padded to a 2MB
1475 * boundary, so memory following the kernel need not be executable
1476 * either. Preloaded kernel modules have their mapping permissions
1477 * fixed up by the linker.
1479 if (pa < trunc_2mpage(btext - KERNBASE) ||
1480 pa >= trunc_2mpage(_end - KERNBASE))
1481 return (X86_PG_RW | pg_nx);
1484 * The linker should ensure that the read-only and read-write
1485 * portions don't share the same 2M page, so this shouldn't
1486 * impact read-only data. However, in any case, any page with
1487 * read-write data needs to be read-write.
1489 if (pa >= trunc_2mpage(brwsection - KERNBASE))
1490 return (X86_PG_RW | pg_nx);
1493 * Mark any 2M page containing kernel text as read-only. Mark
1494 * other pages with read-only data as read-only and not executable.
1495 * (It is likely a small portion of the read-only data section will
1496 * be marked as read-only, but executable. This should be acceptable
1497 * since the read-only protection will keep the data from changing.)
1498 * Note that fixups to the .text section will still work until we
1501 if (pa < round_2mpage(etext - KERNBASE))
1507 create_pagetables(vm_paddr_t *firstaddr)
1509 int i, j, ndm1g, nkpdpe, nkdmpde;
1513 uint64_t DMPDkernphys;
1515 /* Allocate page table pages for the direct map */
1516 ndmpdp = howmany(ptoa(Maxmem), NBPDP);
1517 if (ndmpdp < 4) /* Minimum 4GB of dirmap */
1519 ndmpdpphys = howmany(ndmpdp, NPDPEPG);
1520 if (ndmpdpphys > NDMPML4E) {
1522 * Each NDMPML4E allows 512 GB, so limit to that,
1523 * and then readjust ndmpdp and ndmpdpphys.
1525 printf("NDMPML4E limits system to %d GB\n", NDMPML4E * 512);
1526 Maxmem = atop(NDMPML4E * NBPML4);
1527 ndmpdpphys = NDMPML4E;
1528 ndmpdp = NDMPML4E * NPDEPG;
1530 DMPDPphys = allocpages(firstaddr, ndmpdpphys);
1532 if ((amd_feature & AMDID_PAGE1GB) != 0) {
1534 * Calculate the number of 1G pages that will fully fit in
1537 ndm1g = ptoa(Maxmem) >> PDPSHIFT;
1540 * Allocate 2M pages for the kernel. These will be used in
1541 * place of the first one or more 1G pages from ndm1g.
1543 nkdmpde = howmany((vm_offset_t)(brwsection - KERNBASE), NBPDP);
1544 DMPDkernphys = allocpages(firstaddr, nkdmpde);
1547 DMPDphys = allocpages(firstaddr, ndmpdp - ndm1g);
1548 dmaplimit = (vm_paddr_t)ndmpdp << PDPSHIFT;
1550 /* Allocate pages */
1551 KPML4phys = allocpages(firstaddr, 1);
1552 KPDPphys = allocpages(firstaddr, NKPML4E);
1555 * Allocate the initial number of kernel page table pages required to
1556 * bootstrap. We defer this until after all memory-size dependent
1557 * allocations are done (e.g. direct map), so that we don't have to
1558 * build in too much slop in our estimate.
1560 * Note that when NKPML4E > 1, we have an empty page underneath
1561 * all but the KPML4I'th one, so we need NKPML4E-1 extra (zeroed)
1562 * pages. (pmap_enter requires a PD page to exist for each KPML4E.)
1564 nkpt_init(*firstaddr);
1565 nkpdpe = NKPDPE(nkpt);
1567 KPTphys = allocpages(firstaddr, nkpt);
1568 KPDphys = allocpages(firstaddr, nkpdpe);
1571 * Connect the zero-filled PT pages to their PD entries. This
1572 * implicitly maps the PT pages at their correct locations within
1575 pd_p = (pd_entry_t *)KPDphys;
1576 for (i = 0; i < nkpt; i++)
1577 pd_p[i] = (KPTphys + ptoa(i)) | X86_PG_RW | X86_PG_V;
1580 * Map from physical address zero to the end of loader preallocated
1581 * memory using 2MB pages. This replaces some of the PD entries
1584 for (i = 0; (i << PDRSHIFT) < KERNend; i++)
1585 /* Preset PG_M and PG_A because demotion expects it. */
1586 pd_p[i] = (i << PDRSHIFT) | X86_PG_V | PG_PS | pg_g |
1587 X86_PG_M | X86_PG_A | bootaddr_rwx(i << PDRSHIFT);
1590 * Because we map the physical blocks in 2M pages, adjust firstaddr
1591 * to record the physical blocks we've actually mapped into kernel
1592 * virtual address space.
1594 if (*firstaddr < round_2mpage(KERNend))
1595 *firstaddr = round_2mpage(KERNend);
1597 /* And connect up the PD to the PDP (leaving room for L4 pages) */
1598 pdp_p = (pdp_entry_t *)(KPDPphys + ptoa(KPML4I - KPML4BASE));
1599 for (i = 0; i < nkpdpe; i++)
1600 pdp_p[i + KPDPI] = (KPDphys + ptoa(i)) | X86_PG_RW | X86_PG_V;
1603 * Now, set up the direct map region using 2MB and/or 1GB pages. If
1604 * the end of physical memory is not aligned to a 1GB page boundary,
1605 * then the residual physical memory is mapped with 2MB pages. Later,
1606 * if pmap_mapdev{_attr}() uses the direct map for non-write-back
1607 * memory, pmap_change_attr() will demote any 2MB or 1GB page mappings
1608 * that are partially used.
1610 pd_p = (pd_entry_t *)DMPDphys;
1611 for (i = NPDEPG * ndm1g, j = 0; i < NPDEPG * ndmpdp; i++, j++) {
1612 pd_p[j] = (vm_paddr_t)i << PDRSHIFT;
1613 /* Preset PG_M and PG_A because demotion expects it. */
1614 pd_p[j] |= X86_PG_RW | X86_PG_V | PG_PS | pg_g |
1615 X86_PG_M | X86_PG_A | pg_nx;
1617 pdp_p = (pdp_entry_t *)DMPDPphys;
1618 for (i = 0; i < ndm1g; i++) {
1619 pdp_p[i] = (vm_paddr_t)i << PDPSHIFT;
1620 /* Preset PG_M and PG_A because demotion expects it. */
1621 pdp_p[i] |= X86_PG_RW | X86_PG_V | PG_PS | pg_g |
1622 X86_PG_M | X86_PG_A | pg_nx;
1624 for (j = 0; i < ndmpdp; i++, j++) {
1625 pdp_p[i] = DMPDphys + ptoa(j);
1626 pdp_p[i] |= X86_PG_RW | X86_PG_V | pg_nx;
1630 * Instead of using a 1G page for the memory containing the kernel,
1631 * use 2M pages with read-only and no-execute permissions. (If using 1G
1632 * pages, this will partially overwrite the PDPEs above.)
1635 pd_p = (pd_entry_t *)DMPDkernphys;
1636 for (i = 0; i < (NPDEPG * nkdmpde); i++)
1637 pd_p[i] = (i << PDRSHIFT) | X86_PG_V | PG_PS | pg_g |
1638 X86_PG_M | X86_PG_A | pg_nx |
1639 bootaddr_rwx(i << PDRSHIFT);
1640 for (i = 0; i < nkdmpde; i++)
1641 pdp_p[i] = (DMPDkernphys + ptoa(i)) | X86_PG_RW |
1645 /* And recursively map PML4 to itself in order to get PTmap */
1646 p4_p = (pml4_entry_t *)KPML4phys;
1647 p4_p[PML4PML4I] = KPML4phys;
1648 p4_p[PML4PML4I] |= X86_PG_RW | X86_PG_V | pg_nx;
1650 /* Connect the Direct Map slot(s) up to the PML4. */
1651 for (i = 0; i < ndmpdpphys; i++) {
1652 p4_p[DMPML4I + i] = DMPDPphys + ptoa(i);
1653 p4_p[DMPML4I + i] |= X86_PG_RW | X86_PG_V | pg_nx;
1656 /* Connect the KVA slots up to the PML4 */
1657 for (i = 0; i < NKPML4E; i++) {
1658 p4_p[KPML4BASE + i] = KPDPphys + ptoa(i);
1659 p4_p[KPML4BASE + i] |= X86_PG_RW | X86_PG_V;
1664 * Bootstrap the system enough to run with virtual memory.
1666 * On amd64 this is called after mapping has already been enabled
1667 * and just syncs the pmap module with what has already been done.
1668 * [We can't call it easily with mapping off since the kernel is not
1669 * mapped with PA == VA, hence we would have to relocate every address
1670 * from the linked base (virtual) address "KERNBASE" to the actual
1671 * (physical) address starting relative to 0]
1674 pmap_bootstrap(vm_paddr_t *firstaddr)
1677 pt_entry_t *pte, *pcpu_pte;
1678 struct region_descriptor r_gdt;
1679 uint64_t cr4, pcpu_phys;
1683 KERNend = *firstaddr;
1684 res = atop(KERNend - (vm_paddr_t)kernphys);
1690 * Create an initial set of page tables to run the kernel in.
1692 create_pagetables(firstaddr);
1694 pcpu_phys = allocpages(firstaddr, MAXCPU);
1697 * Add a physical memory segment (vm_phys_seg) corresponding to the
1698 * preallocated kernel page table pages so that vm_page structures
1699 * representing these pages will be created. The vm_page structures
1700 * are required for promotion of the corresponding kernel virtual
1701 * addresses to superpage mappings.
1703 vm_phys_early_add_seg(KPTphys, KPTphys + ptoa(nkpt));
1706 * Account for the virtual addresses mapped by create_pagetables().
1708 virtual_avail = (vm_offset_t)KERNBASE + round_2mpage(KERNend);
1709 virtual_end = VM_MAX_KERNEL_ADDRESS;
1712 * Enable PG_G global pages, then switch to the kernel page
1713 * table from the bootstrap page table. After the switch, it
1714 * is possible to enable SMEP and SMAP since PG_U bits are
1720 load_cr3(KPML4phys);
1721 if (cpu_stdext_feature & CPUID_STDEXT_SMEP)
1723 if (cpu_stdext_feature & CPUID_STDEXT_SMAP)
1728 * Initialize the kernel pmap (which is statically allocated).
1729 * Count bootstrap data as being resident in case any of this data is
1730 * later unmapped (using pmap_remove()) and freed.
1732 PMAP_LOCK_INIT(kernel_pmap);
1733 kernel_pmap->pm_pml4 = (pdp_entry_t *)PHYS_TO_DMAP(KPML4phys);
1734 kernel_pmap->pm_cr3 = KPML4phys;
1735 kernel_pmap->pm_ucr3 = PMAP_NO_CR3;
1736 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */
1737 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
1738 kernel_pmap->pm_stats.resident_count = res;
1739 kernel_pmap->pm_flags = pmap_flags;
1742 * Initialize the TLB invalidations generation number lock.
1744 mtx_init(&invl_gen_mtx, "invlgn", NULL, MTX_DEF);
1747 * Reserve some special page table entries/VA space for temporary
1750 #define SYSMAP(c, p, v, n) \
1751 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n);
1757 * Crashdump maps. The first page is reused as CMAP1 for the
1760 SYSMAP(caddr_t, CMAP1, crashdumpmap, MAXDUMPPGS)
1761 CADDR1 = crashdumpmap;
1763 SYSMAP(struct pcpu *, pcpu_pte, __pcpu, MAXCPU);
1766 for (i = 0; i < MAXCPU; i++) {
1767 pcpu_pte[i] = (pcpu_phys + ptoa(i)) | X86_PG_V | X86_PG_RW |
1768 pg_g | pg_nx | X86_PG_M | X86_PG_A;
1772 * Re-initialize PCPU area for BSP after switching.
1773 * Make hardware use gdt and common_tss from the new PCPU.
1775 STAILQ_INIT(&cpuhead);
1776 wrmsr(MSR_GSBASE, (uint64_t)&__pcpu[0]);
1777 pcpu_init(&__pcpu[0], 0, sizeof(struct pcpu));
1778 amd64_bsp_pcpu_init1(&__pcpu[0]);
1779 amd64_bsp_ist_init(&__pcpu[0]);
1780 __pcpu[0].pc_common_tss.tss_iobase = sizeof(struct amd64tss) +
1782 memcpy(__pcpu[0].pc_gdt, temp_bsp_pcpu.pc_gdt, NGDT *
1783 sizeof(struct user_segment_descriptor));
1784 gdt_segs[GPROC0_SEL].ssd_base = (uintptr_t)&__pcpu[0].pc_common_tss;
1785 ssdtosyssd(&gdt_segs[GPROC0_SEL],
1786 (struct system_segment_descriptor *)&__pcpu[0].pc_gdt[GPROC0_SEL]);
1787 r_gdt.rd_limit = NGDT * sizeof(struct user_segment_descriptor) - 1;
1788 r_gdt.rd_base = (long)__pcpu[0].pc_gdt;
1790 wrmsr(MSR_GSBASE, (uint64_t)&__pcpu[0]);
1791 ltr(GSEL(GPROC0_SEL, SEL_KPL));
1792 __pcpu[0].pc_dynamic = temp_bsp_pcpu.pc_dynamic;
1793 __pcpu[0].pc_acpi_id = temp_bsp_pcpu.pc_acpi_id;
1796 * Initialize the PAT MSR.
1797 * pmap_init_pat() clears and sets CR4_PGE, which, as a
1798 * side-effect, invalidates stale PG_G TLB entries that might
1799 * have been created in our pre-boot environment.
1803 /* Initialize TLB Context Id. */
1804 if (pmap_pcid_enabled) {
1805 for (i = 0; i < MAXCPU; i++) {
1806 kernel_pmap->pm_pcids[i].pm_pcid = PMAP_PCID_KERN;
1807 kernel_pmap->pm_pcids[i].pm_gen = 1;
1811 * PMAP_PCID_KERN + 1 is used for initialization of
1812 * proc0 pmap. The pmap' pcid state might be used by
1813 * EFIRT entry before first context switch, so it
1814 * needs to be valid.
1816 PCPU_SET(pcid_next, PMAP_PCID_KERN + 2);
1817 PCPU_SET(pcid_gen, 1);
1820 * pcpu area for APs is zeroed during AP startup.
1821 * pc_pcid_next and pc_pcid_gen are initialized by AP
1822 * during pcpu setup.
1824 load_cr4(rcr4() | CR4_PCIDE);
1829 * Setup the PAT MSR.
1838 /* Bail if this CPU doesn't implement PAT. */
1839 if ((cpu_feature & CPUID_PAT) == 0)
1842 /* Set default PAT index table. */
1843 for (i = 0; i < PAT_INDEX_SIZE; i++)
1845 pat_index[PAT_WRITE_BACK] = 0;
1846 pat_index[PAT_WRITE_THROUGH] = 1;
1847 pat_index[PAT_UNCACHEABLE] = 3;
1848 pat_index[PAT_WRITE_COMBINING] = 6;
1849 pat_index[PAT_WRITE_PROTECTED] = 5;
1850 pat_index[PAT_UNCACHED] = 2;
1853 * Initialize default PAT entries.
1854 * Leave the indices 0-3 at the default of WB, WT, UC-, and UC.
1855 * Program 5 and 6 as WP and WC.
1857 * Leave 4 and 7 as WB and UC. Note that a recursive page table
1858 * mapping for a 2M page uses a PAT value with the bit 3 set due
1859 * to its overload with PG_PS.
1861 pat_msr = PAT_VALUE(0, PAT_WRITE_BACK) |
1862 PAT_VALUE(1, PAT_WRITE_THROUGH) |
1863 PAT_VALUE(2, PAT_UNCACHED) |
1864 PAT_VALUE(3, PAT_UNCACHEABLE) |
1865 PAT_VALUE(4, PAT_WRITE_BACK) |
1866 PAT_VALUE(5, PAT_WRITE_PROTECTED) |
1867 PAT_VALUE(6, PAT_WRITE_COMBINING) |
1868 PAT_VALUE(7, PAT_UNCACHEABLE);
1872 load_cr4(cr4 & ~CR4_PGE);
1874 /* Disable caches (CD = 1, NW = 0). */
1876 load_cr0((cr0 & ~CR0_NW) | CR0_CD);
1878 /* Flushes caches and TLBs. */
1882 /* Update PAT and index table. */
1883 wrmsr(MSR_PAT, pat_msr);
1885 /* Flush caches and TLBs again. */
1889 /* Restore caches and PGE. */
1895 * Initialize a vm_page's machine-dependent fields.
1898 pmap_page_init(vm_page_t m)
1901 TAILQ_INIT(&m->md.pv_list);
1902 m->md.pat_mode = PAT_WRITE_BACK;
1905 static int pmap_allow_2m_x_ept;
1906 SYSCTL_INT(_vm_pmap, OID_AUTO, allow_2m_x_ept, CTLFLAG_RWTUN | CTLFLAG_NOFETCH,
1907 &pmap_allow_2m_x_ept, 0,
1908 "Allow executable superpage mappings in EPT");
1911 pmap_allow_2m_x_ept_recalculate(void)
1914 * SKL002, SKL012S. Since the EPT format is only used by
1915 * Intel CPUs, the vendor check is merely a formality.
1917 if (!(cpu_vendor_id != CPU_VENDOR_INTEL ||
1918 (cpu_ia32_arch_caps & IA32_ARCH_CAP_IF_PSCHANGE_MC_NO) != 0 ||
1919 (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
1920 (CPUID_TO_MODEL(cpu_id) == 0x26 || /* Atoms */
1921 CPUID_TO_MODEL(cpu_id) == 0x27 ||
1922 CPUID_TO_MODEL(cpu_id) == 0x35 ||
1923 CPUID_TO_MODEL(cpu_id) == 0x36 ||
1924 CPUID_TO_MODEL(cpu_id) == 0x37 ||
1925 CPUID_TO_MODEL(cpu_id) == 0x86 ||
1926 CPUID_TO_MODEL(cpu_id) == 0x1c ||
1927 CPUID_TO_MODEL(cpu_id) == 0x4a ||
1928 CPUID_TO_MODEL(cpu_id) == 0x4c ||
1929 CPUID_TO_MODEL(cpu_id) == 0x4d ||
1930 CPUID_TO_MODEL(cpu_id) == 0x5a ||
1931 CPUID_TO_MODEL(cpu_id) == 0x5c ||
1932 CPUID_TO_MODEL(cpu_id) == 0x5d ||
1933 CPUID_TO_MODEL(cpu_id) == 0x5f ||
1934 CPUID_TO_MODEL(cpu_id) == 0x6e ||
1935 CPUID_TO_MODEL(cpu_id) == 0x7a ||
1936 CPUID_TO_MODEL(cpu_id) == 0x57 || /* Knights */
1937 CPUID_TO_MODEL(cpu_id) == 0x85))))
1938 pmap_allow_2m_x_ept = 1;
1939 TUNABLE_INT_FETCH("hw.allow_2m_x_ept", &pmap_allow_2m_x_ept);
1943 pmap_allow_2m_x_page(pmap_t pmap, bool executable)
1946 return (pmap->pm_type != PT_EPT || !executable ||
1947 !pmap_allow_2m_x_ept);
1952 pmap_init_pv_table(void)
1954 struct pmap_large_md_page *pvd;
1956 long start, end, highest, pv_npg;
1957 int domain, i, j, pages;
1960 * We strongly depend on the size being a power of two, so the assert
1961 * is overzealous. However, should the struct be resized to a
1962 * different power of two, the code below needs to be revisited.
1964 CTASSERT((sizeof(*pvd) == 64));
1967 * Calculate the size of the array.
1969 pmap_last_pa = vm_phys_segs[vm_phys_nsegs - 1].end;
1970 pv_npg = howmany(pmap_last_pa, NBPDR);
1971 s = (vm_size_t)pv_npg * sizeof(struct pmap_large_md_page);
1973 pv_table = (struct pmap_large_md_page *)kva_alloc(s);
1974 if (pv_table == NULL)
1975 panic("%s: kva_alloc failed\n", __func__);
1978 * Iterate physical segments to allocate space for respective pages.
1982 for (i = 0; i < vm_phys_nsegs; i++) {
1983 end = vm_phys_segs[i].end / NBPDR;
1984 domain = vm_phys_segs[i].domain;
1989 start = highest + 1;
1990 pvd = &pv_table[start];
1992 pages = end - start + 1;
1993 s = round_page(pages * sizeof(*pvd));
1994 highest = start + (s / sizeof(*pvd)) - 1;
1996 for (j = 0; j < s; j += PAGE_SIZE) {
1997 vm_page_t m = vm_page_alloc_domain(NULL, 0,
1998 domain, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ);
2000 panic("vm_page_alloc_domain failed for %lx\n", (vm_offset_t)pvd + j);
2001 pmap_qenter((vm_offset_t)pvd + j, &m, 1);
2004 for (j = 0; j < s / sizeof(*pvd); j++) {
2005 rw_init_flags(&pvd->pv_lock, "pmap pv list", RW_NEW);
2006 TAILQ_INIT(&pvd->pv_page.pv_list);
2007 pvd->pv_page.pv_gen = 0;
2008 pvd->pv_page.pat_mode = 0;
2009 pvd->pv_invl_gen = 0;
2013 pvd = &pv_dummy_large;
2014 rw_init_flags(&pvd->pv_lock, "pmap pv list dummy", RW_NEW);
2015 TAILQ_INIT(&pvd->pv_page.pv_list);
2016 pvd->pv_page.pv_gen = 0;
2017 pvd->pv_page.pat_mode = 0;
2018 pvd->pv_invl_gen = 0;
2022 pmap_init_pv_table(void)
2028 * Initialize the pool of pv list locks.
2030 for (i = 0; i < NPV_LIST_LOCKS; i++)
2031 rw_init(&pv_list_locks[i], "pmap pv list");
2034 * Calculate the size of the pv head table for superpages.
2036 pv_npg = howmany(vm_phys_segs[vm_phys_nsegs - 1].end, NBPDR);
2039 * Allocate memory for the pv head table for superpages.
2041 s = (vm_size_t)pv_npg * sizeof(struct md_page);
2043 pv_table = (struct md_page *)kmem_malloc(s, M_WAITOK | M_ZERO);
2044 for (i = 0; i < pv_npg; i++)
2045 TAILQ_INIT(&pv_table[i].pv_list);
2046 TAILQ_INIT(&pv_dummy.pv_list);
2051 * Initialize the pmap module.
2052 * Called by vm_init, to initialize any structures that the pmap
2053 * system needs to map virtual memory.
2058 struct pmap_preinit_mapping *ppim;
2060 int error, i, ret, skz63;
2062 /* L1TF, reserve page @0 unconditionally */
2063 vm_page_blacklist_add(0, bootverbose);
2065 /* Detect bare-metal Skylake Server and Skylake-X. */
2066 if (vm_guest == VM_GUEST_NO && cpu_vendor_id == CPU_VENDOR_INTEL &&
2067 CPUID_TO_FAMILY(cpu_id) == 0x6 && CPUID_TO_MODEL(cpu_id) == 0x55) {
2069 * Skylake-X errata SKZ63. Processor May Hang When
2070 * Executing Code In an HLE Transaction Region between
2071 * 40000000H and 403FFFFFH.
2073 * Mark the pages in the range as preallocated. It
2074 * seems to be impossible to distinguish between
2075 * Skylake Server and Skylake X.
2078 TUNABLE_INT_FETCH("hw.skz63_enable", &skz63);
2081 printf("SKZ63: skipping 4M RAM starting "
2082 "at physical 1G\n");
2083 for (i = 0; i < atop(0x400000); i++) {
2084 ret = vm_page_blacklist_add(0x40000000 +
2086 if (!ret && bootverbose)
2087 printf("page at %#lx already used\n",
2088 0x40000000 + ptoa(i));
2094 pmap_allow_2m_x_ept_recalculate();
2097 * Initialize the vm page array entries for the kernel pmap's
2100 PMAP_LOCK(kernel_pmap);
2101 for (i = 0; i < nkpt; i++) {
2102 mpte = PHYS_TO_VM_PAGE(KPTphys + (i << PAGE_SHIFT));
2103 KASSERT(mpte >= vm_page_array &&
2104 mpte < &vm_page_array[vm_page_array_size],
2105 ("pmap_init: page table page is out of range"));
2106 mpte->pindex = pmap_pde_pindex(KERNBASE) + i;
2107 mpte->phys_addr = KPTphys + (i << PAGE_SHIFT);
2108 mpte->ref_count = 1;
2111 * Collect the page table pages that were replaced by a 2MB
2112 * page in create_pagetables(). They are zero filled.
2114 if (i << PDRSHIFT < KERNend &&
2115 pmap_insert_pt_page(kernel_pmap, mpte, false))
2116 panic("pmap_init: pmap_insert_pt_page failed");
2118 PMAP_UNLOCK(kernel_pmap);
2122 * If the kernel is running on a virtual machine, then it must assume
2123 * that MCA is enabled by the hypervisor. Moreover, the kernel must
2124 * be prepared for the hypervisor changing the vendor and family that
2125 * are reported by CPUID. Consequently, the workaround for AMD Family
2126 * 10h Erratum 383 is enabled if the processor's feature set does not
2127 * include at least one feature that is only supported by older Intel
2128 * or newer AMD processors.
2130 if (vm_guest != VM_GUEST_NO && (cpu_feature & CPUID_SS) == 0 &&
2131 (cpu_feature2 & (CPUID2_SSSE3 | CPUID2_SSE41 | CPUID2_AESNI |
2132 CPUID2_AVX | CPUID2_XSAVE)) == 0 && (amd_feature2 & (AMDID2_XOP |
2134 workaround_erratum383 = 1;
2137 * Are large page mappings enabled?
2139 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled);
2140 if (pg_ps_enabled) {
2141 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
2142 ("pmap_init: can't assign to pagesizes[1]"));
2143 pagesizes[1] = NBPDR;
2147 * Initialize pv chunk lists.
2149 for (i = 0; i < PMAP_MEMDOM; i++) {
2150 mtx_init(&pv_chunks[i].pvc_lock, "pmap pv chunk list", NULL, MTX_DEF);
2151 TAILQ_INIT(&pv_chunks[i].pvc_list);
2153 pmap_init_pv_table();
2155 pmap_initialized = 1;
2156 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
2157 ppim = pmap_preinit_mapping + i;
2160 /* Make the direct map consistent */
2161 if (ppim->pa < dmaplimit && ppim->pa + ppim->sz <= dmaplimit) {
2162 (void)pmap_change_attr(PHYS_TO_DMAP(ppim->pa),
2163 ppim->sz, ppim->mode);
2167 printf("PPIM %u: PA=%#lx, VA=%#lx, size=%#lx, mode=%#x\n", i,
2168 ppim->pa, ppim->va, ppim->sz, ppim->mode);
2171 mtx_init(&qframe_mtx, "qfrmlk", NULL, MTX_SPIN);
2172 error = vmem_alloc(kernel_arena, PAGE_SIZE, M_BESTFIT | M_WAITOK,
2173 (vmem_addr_t *)&qframe);
2175 panic("qframe allocation failed");
2178 TUNABLE_INT_FETCH("vm.pmap.large_map_pml4_entries", &lm_ents);
2179 if (lm_ents > LMEPML4I - LMSPML4I + 1)
2180 lm_ents = LMEPML4I - LMSPML4I + 1;
2182 printf("pmap: large map %u PML4 slots (%lu GB)\n",
2183 lm_ents, (u_long)lm_ents * (NBPML4 / 1024 / 1024 / 1024));
2185 large_vmem = vmem_create("large", LARGEMAP_MIN_ADDRESS,
2186 (vmem_size_t)lm_ents * NBPML4, PAGE_SIZE, 0, M_WAITOK);
2187 if (large_vmem == NULL) {
2188 printf("pmap: cannot create large map\n");
2191 for (i = 0; i < lm_ents; i++) {
2192 m = pmap_large_map_getptp_unlocked();
2193 kernel_pmap->pm_pml4[LMSPML4I + i] = X86_PG_V |
2194 X86_PG_RW | X86_PG_A | X86_PG_M | pg_nx |
2200 SYSCTL_UINT(_vm_pmap, OID_AUTO, large_map_pml4_entries,
2201 CTLFLAG_RDTUN | CTLFLAG_NOFETCH, &lm_ents, 0,
2202 "Maximum number of PML4 entries for use by large map (tunable). "
2203 "Each entry corresponds to 512GB of address space.");
2205 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
2206 "2MB page mapping counters");
2208 static u_long pmap_pde_demotions;
2209 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, demotions, CTLFLAG_RD,
2210 &pmap_pde_demotions, 0, "2MB page demotions");
2212 static u_long pmap_pde_mappings;
2213 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD,
2214 &pmap_pde_mappings, 0, "2MB page mappings");
2216 static u_long pmap_pde_p_failures;
2217 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, p_failures, CTLFLAG_RD,
2218 &pmap_pde_p_failures, 0, "2MB page promotion failures");
2220 static u_long pmap_pde_promotions;
2221 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, promotions, CTLFLAG_RD,
2222 &pmap_pde_promotions, 0, "2MB page promotions");
2224 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pdpe, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
2225 "1GB page mapping counters");
2227 static u_long pmap_pdpe_demotions;
2228 SYSCTL_ULONG(_vm_pmap_pdpe, OID_AUTO, demotions, CTLFLAG_RD,
2229 &pmap_pdpe_demotions, 0, "1GB page demotions");
2231 /***************************************************
2232 * Low level helper routines.....
2233 ***************************************************/
2236 pmap_swap_pat(pmap_t pmap, pt_entry_t entry)
2238 int x86_pat_bits = X86_PG_PTE_PAT | X86_PG_PDE_PAT;
2240 switch (pmap->pm_type) {
2243 /* Verify that both PAT bits are not set at the same time */
2244 KASSERT((entry & x86_pat_bits) != x86_pat_bits,
2245 ("Invalid PAT bits in entry %#lx", entry));
2247 /* Swap the PAT bits if one of them is set */
2248 if ((entry & x86_pat_bits) != 0)
2249 entry ^= x86_pat_bits;
2253 * Nothing to do - the memory attributes are represented
2254 * the same way for regular pages and superpages.
2258 panic("pmap_switch_pat_bits: bad pm_type %d", pmap->pm_type);
2265 pmap_is_valid_memattr(pmap_t pmap __unused, vm_memattr_t mode)
2268 return (mode >= 0 && mode < PAT_INDEX_SIZE &&
2269 pat_index[(int)mode] >= 0);
2273 * Determine the appropriate bits to set in a PTE or PDE for a specified
2277 pmap_cache_bits(pmap_t pmap, int mode, boolean_t is_pde)
2279 int cache_bits, pat_flag, pat_idx;
2281 if (!pmap_is_valid_memattr(pmap, mode))
2282 panic("Unknown caching mode %d\n", mode);
2284 switch (pmap->pm_type) {
2287 /* The PAT bit is different for PTE's and PDE's. */
2288 pat_flag = is_pde ? X86_PG_PDE_PAT : X86_PG_PTE_PAT;
2290 /* Map the caching mode to a PAT index. */
2291 pat_idx = pat_index[mode];
2293 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */
2296 cache_bits |= pat_flag;
2298 cache_bits |= PG_NC_PCD;
2300 cache_bits |= PG_NC_PWT;
2304 cache_bits = EPT_PG_IGNORE_PAT | EPT_PG_MEMORY_TYPE(mode);
2308 panic("unsupported pmap type %d", pmap->pm_type);
2311 return (cache_bits);
2315 pmap_cache_mask(pmap_t pmap, boolean_t is_pde)
2319 switch (pmap->pm_type) {
2322 mask = is_pde ? X86_PG_PDE_CACHE : X86_PG_PTE_CACHE;
2325 mask = EPT_PG_IGNORE_PAT | EPT_PG_MEMORY_TYPE(0x7);
2328 panic("pmap_cache_mask: invalid pm_type %d", pmap->pm_type);
2335 pmap_pat_index(pmap_t pmap, pt_entry_t pte, bool is_pde)
2337 int pat_flag, pat_idx;
2340 switch (pmap->pm_type) {
2343 /* The PAT bit is different for PTE's and PDE's. */
2344 pat_flag = is_pde ? X86_PG_PDE_PAT : X86_PG_PTE_PAT;
2346 if ((pte & pat_flag) != 0)
2348 if ((pte & PG_NC_PCD) != 0)
2350 if ((pte & PG_NC_PWT) != 0)
2354 if ((pte & EPT_PG_IGNORE_PAT) != 0)
2355 panic("EPT PTE %#lx has no PAT memory type", pte);
2356 pat_idx = (pte & EPT_PG_MEMORY_TYPE(0x7)) >> 3;
2360 /* See pmap_init_pat(). */
2370 pmap_ps_enabled(pmap_t pmap)
2373 return (pg_ps_enabled && (pmap->pm_flags & PMAP_PDE_SUPERPAGE) != 0);
2377 pmap_update_pde_store(pmap_t pmap, pd_entry_t *pde, pd_entry_t newpde)
2380 switch (pmap->pm_type) {
2387 * This is a little bogus since the generation number is
2388 * supposed to be bumped up when a region of the address
2389 * space is invalidated in the page tables.
2391 * In this case the old PDE entry is valid but yet we want
2392 * to make sure that any mappings using the old entry are
2393 * invalidated in the TLB.
2395 * The reason this works as expected is because we rendezvous
2396 * "all" host cpus and force any vcpu context to exit as a
2399 atomic_add_acq_long(&pmap->pm_eptgen, 1);
2402 panic("pmap_update_pde_store: bad pm_type %d", pmap->pm_type);
2404 pde_store(pde, newpde);
2408 * After changing the page size for the specified virtual address in the page
2409 * table, flush the corresponding entries from the processor's TLB. Only the
2410 * calling processor's TLB is affected.
2412 * The calling thread must be pinned to a processor.
2415 pmap_update_pde_invalidate(pmap_t pmap, vm_offset_t va, pd_entry_t newpde)
2419 if (pmap_type_guest(pmap))
2422 KASSERT(pmap->pm_type == PT_X86,
2423 ("pmap_update_pde_invalidate: invalid type %d", pmap->pm_type));
2425 PG_G = pmap_global_bit(pmap);
2427 if ((newpde & PG_PS) == 0)
2428 /* Demotion: flush a specific 2MB page mapping. */
2430 else if ((newpde & PG_G) == 0)
2432 * Promotion: flush every 4KB page mapping from the TLB
2433 * because there are too many to flush individually.
2438 * Promotion: flush every 4KB page mapping from the TLB,
2439 * including any global (PG_G) mappings.
2447 * For SMP, these functions have to use the IPI mechanism for coherence.
2449 * N.B.: Before calling any of the following TLB invalidation functions,
2450 * the calling processor must ensure that all stores updating a non-
2451 * kernel page table are globally performed. Otherwise, another
2452 * processor could cache an old, pre-update entry without being
2453 * invalidated. This can happen one of two ways: (1) The pmap becomes
2454 * active on another processor after its pm_active field is checked by
2455 * one of the following functions but before a store updating the page
2456 * table is globally performed. (2) The pmap becomes active on another
2457 * processor before its pm_active field is checked but due to
2458 * speculative loads one of the following functions stills reads the
2459 * pmap as inactive on the other processor.
2461 * The kernel page table is exempt because its pm_active field is
2462 * immutable. The kernel page table is always active on every
2467 * Interrupt the cpus that are executing in the guest context.
2468 * This will force the vcpu to exit and the cached EPT mappings
2469 * will be invalidated by the host before the next vmresume.
2471 static __inline void
2472 pmap_invalidate_ept(pmap_t pmap)
2477 KASSERT(!CPU_ISSET(curcpu, &pmap->pm_active),
2478 ("pmap_invalidate_ept: absurd pm_active"));
2481 * The TLB mappings associated with a vcpu context are not
2482 * flushed each time a different vcpu is chosen to execute.
2484 * This is in contrast with a process's vtop mappings that
2485 * are flushed from the TLB on each context switch.
2487 * Therefore we need to do more than just a TLB shootdown on
2488 * the active cpus in 'pmap->pm_active'. To do this we keep
2489 * track of the number of invalidations performed on this pmap.
2491 * Each vcpu keeps a cache of this counter and compares it
2492 * just before a vmresume. If the counter is out-of-date an
2493 * invept will be done to flush stale mappings from the TLB.
2495 atomic_add_acq_long(&pmap->pm_eptgen, 1);
2498 * Force the vcpu to exit and trap back into the hypervisor.
2500 ipinum = pmap->pm_flags & PMAP_NESTED_IPIMASK;
2501 ipi_selected(pmap->pm_active, ipinum);
2506 pmap_invalidate_cpu_mask(pmap_t pmap)
2509 return (pmap == kernel_pmap ? all_cpus : pmap->pm_active);
2513 pmap_invalidate_page_pcid(pmap_t pmap, vm_offset_t va,
2514 const bool invpcid_works1)
2516 struct invpcid_descr d;
2517 uint64_t kcr3, ucr3;
2521 cpuid = PCPU_GET(cpuid);
2522 if (pmap == PCPU_GET(curpmap)) {
2523 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
2525 * Because pm_pcid is recalculated on a
2526 * context switch, we must disable switching.
2527 * Otherwise, we might use a stale value
2531 pcid = pmap->pm_pcids[cpuid].pm_pcid;
2532 if (invpcid_works1) {
2533 d.pcid = pcid | PMAP_PCID_USER_PT;
2536 invpcid(&d, INVPCID_ADDR);
2538 kcr3 = pmap->pm_cr3 | pcid | CR3_PCID_SAVE;
2539 ucr3 = pmap->pm_ucr3 | pcid |
2540 PMAP_PCID_USER_PT | CR3_PCID_SAVE;
2541 pmap_pti_pcid_invlpg(ucr3, kcr3, va);
2546 pmap->pm_pcids[cpuid].pm_gen = 0;
2550 pmap->pm_pcids[i].pm_gen = 0;
2554 * The fence is between stores to pm_gen and the read of the
2555 * pm_active mask. We need to ensure that it is impossible
2556 * for us to miss the bit update in pm_active and
2557 * simultaneously observe a non-zero pm_gen in
2558 * pmap_activate_sw(), otherwise TLB update is missed.
2559 * Without the fence, IA32 allows such an outcome. Note that
2560 * pm_active is updated by a locked operation, which provides
2561 * the reciprocal fence.
2563 atomic_thread_fence_seq_cst();
2567 pmap_invalidate_page_pcid_invpcid(pmap_t pmap, vm_offset_t va)
2570 pmap_invalidate_page_pcid(pmap, va, true);
2574 pmap_invalidate_page_pcid_noinvpcid(pmap_t pmap, vm_offset_t va)
2577 pmap_invalidate_page_pcid(pmap, va, false);
2581 pmap_invalidate_page_nopcid(pmap_t pmap, vm_offset_t va)
2585 DEFINE_IFUNC(static, void, pmap_invalidate_page_mode, (pmap_t, vm_offset_t))
2588 if (pmap_pcid_enabled)
2589 return (invpcid_works ? pmap_invalidate_page_pcid_invpcid :
2590 pmap_invalidate_page_pcid_noinvpcid);
2591 return (pmap_invalidate_page_nopcid);
2595 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
2598 if (pmap_type_guest(pmap)) {
2599 pmap_invalidate_ept(pmap);
2603 KASSERT(pmap->pm_type == PT_X86,
2604 ("pmap_invalidate_page: invalid type %d", pmap->pm_type));
2607 if (pmap == kernel_pmap) {
2610 if (pmap == PCPU_GET(curpmap))
2612 pmap_invalidate_page_mode(pmap, va);
2614 smp_masked_invlpg(pmap_invalidate_cpu_mask(pmap), va, pmap);
2618 /* 4k PTEs -- Chosen to exceed the total size of Broadwell L2 TLB */
2619 #define PMAP_INVLPG_THRESHOLD (4 * 1024 * PAGE_SIZE)
2622 pmap_invalidate_range_pcid(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
2623 const bool invpcid_works1)
2625 struct invpcid_descr d;
2626 uint64_t kcr3, ucr3;
2630 cpuid = PCPU_GET(cpuid);
2631 if (pmap == PCPU_GET(curpmap)) {
2632 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
2634 pcid = pmap->pm_pcids[cpuid].pm_pcid;
2635 if (invpcid_works1) {
2636 d.pcid = pcid | PMAP_PCID_USER_PT;
2639 for (; d.addr < eva; d.addr += PAGE_SIZE)
2640 invpcid(&d, INVPCID_ADDR);
2642 kcr3 = pmap->pm_cr3 | pcid | CR3_PCID_SAVE;
2643 ucr3 = pmap->pm_ucr3 | pcid |
2644 PMAP_PCID_USER_PT | CR3_PCID_SAVE;
2645 pmap_pti_pcid_invlrng(ucr3, kcr3, sva, eva);
2650 pmap->pm_pcids[cpuid].pm_gen = 0;
2654 pmap->pm_pcids[i].pm_gen = 0;
2656 /* See the comment in pmap_invalidate_page_pcid(). */
2657 atomic_thread_fence_seq_cst();
2661 pmap_invalidate_range_pcid_invpcid(pmap_t pmap, vm_offset_t sva,
2665 pmap_invalidate_range_pcid(pmap, sva, eva, true);
2669 pmap_invalidate_range_pcid_noinvpcid(pmap_t pmap, vm_offset_t sva,
2673 pmap_invalidate_range_pcid(pmap, sva, eva, false);
2677 pmap_invalidate_range_nopcid(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2681 DEFINE_IFUNC(static, void, pmap_invalidate_range_mode, (pmap_t, vm_offset_t,
2685 if (pmap_pcid_enabled)
2686 return (invpcid_works ? pmap_invalidate_range_pcid_invpcid :
2687 pmap_invalidate_range_pcid_noinvpcid);
2688 return (pmap_invalidate_range_nopcid);
2692 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2696 if (eva - sva >= PMAP_INVLPG_THRESHOLD) {
2697 pmap_invalidate_all(pmap);
2701 if (pmap_type_guest(pmap)) {
2702 pmap_invalidate_ept(pmap);
2706 KASSERT(pmap->pm_type == PT_X86,
2707 ("pmap_invalidate_range: invalid type %d", pmap->pm_type));
2710 if (pmap == kernel_pmap) {
2711 for (addr = sva; addr < eva; addr += PAGE_SIZE)
2714 if (pmap == PCPU_GET(curpmap)) {
2715 for (addr = sva; addr < eva; addr += PAGE_SIZE)
2718 pmap_invalidate_range_mode(pmap, sva, eva);
2720 smp_masked_invlpg_range(pmap_invalidate_cpu_mask(pmap), sva, eva, pmap);
2725 pmap_invalidate_all_pcid(pmap_t pmap, bool invpcid_works1)
2727 struct invpcid_descr d;
2728 uint64_t kcr3, ucr3;
2732 if (pmap == kernel_pmap) {
2733 if (invpcid_works1) {
2734 bzero(&d, sizeof(d));
2735 invpcid(&d, INVPCID_CTXGLOB);
2740 cpuid = PCPU_GET(cpuid);
2741 if (pmap == PCPU_GET(curpmap)) {
2743 pcid = pmap->pm_pcids[cpuid].pm_pcid;
2744 if (invpcid_works1) {
2748 invpcid(&d, INVPCID_CTX);
2749 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
2750 d.pcid |= PMAP_PCID_USER_PT;
2751 invpcid(&d, INVPCID_CTX);
2754 kcr3 = pmap->pm_cr3 | pcid;
2755 ucr3 = pmap->pm_ucr3;
2756 if (ucr3 != PMAP_NO_CR3) {
2757 ucr3 |= pcid | PMAP_PCID_USER_PT;
2758 pmap_pti_pcid_invalidate(ucr3, kcr3);
2765 pmap->pm_pcids[cpuid].pm_gen = 0;
2768 pmap->pm_pcids[i].pm_gen = 0;
2771 /* See the comment in pmap_invalidate_page_pcid(). */
2772 atomic_thread_fence_seq_cst();
2776 pmap_invalidate_all_pcid_invpcid(pmap_t pmap)
2779 pmap_invalidate_all_pcid(pmap, true);
2783 pmap_invalidate_all_pcid_noinvpcid(pmap_t pmap)
2786 pmap_invalidate_all_pcid(pmap, false);
2790 pmap_invalidate_all_nopcid(pmap_t pmap)
2793 if (pmap == kernel_pmap)
2795 else if (pmap == PCPU_GET(curpmap))
2799 DEFINE_IFUNC(static, void, pmap_invalidate_all_mode, (pmap_t))
2802 if (pmap_pcid_enabled)
2803 return (invpcid_works ? pmap_invalidate_all_pcid_invpcid :
2804 pmap_invalidate_all_pcid_noinvpcid);
2805 return (pmap_invalidate_all_nopcid);
2809 pmap_invalidate_all(pmap_t pmap)
2812 if (pmap_type_guest(pmap)) {
2813 pmap_invalidate_ept(pmap);
2817 KASSERT(pmap->pm_type == PT_X86,
2818 ("pmap_invalidate_all: invalid type %d", pmap->pm_type));
2821 pmap_invalidate_all_mode(pmap);
2822 smp_masked_invltlb(pmap_invalidate_cpu_mask(pmap), pmap);
2827 pmap_invalidate_cache(void)
2837 cpuset_t invalidate; /* processors that invalidate their TLB */
2842 u_int store; /* processor that updates the PDE */
2846 pmap_update_pde_action(void *arg)
2848 struct pde_action *act = arg;
2850 if (act->store == PCPU_GET(cpuid))
2851 pmap_update_pde_store(act->pmap, act->pde, act->newpde);
2855 pmap_update_pde_teardown(void *arg)
2857 struct pde_action *act = arg;
2859 if (CPU_ISSET(PCPU_GET(cpuid), &act->invalidate))
2860 pmap_update_pde_invalidate(act->pmap, act->va, act->newpde);
2864 * Change the page size for the specified virtual address in a way that
2865 * prevents any possibility of the TLB ever having two entries that map the
2866 * same virtual address using different page sizes. This is the recommended
2867 * workaround for Erratum 383 on AMD Family 10h processors. It prevents a
2868 * machine check exception for a TLB state that is improperly diagnosed as a
2872 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
2874 struct pde_action act;
2875 cpuset_t active, other_cpus;
2879 cpuid = PCPU_GET(cpuid);
2880 other_cpus = all_cpus;
2881 CPU_CLR(cpuid, &other_cpus);
2882 if (pmap == kernel_pmap || pmap_type_guest(pmap))
2885 active = pmap->pm_active;
2887 if (CPU_OVERLAP(&active, &other_cpus)) {
2889 act.invalidate = active;
2893 act.newpde = newpde;
2894 CPU_SET(cpuid, &active);
2895 smp_rendezvous_cpus(active,
2896 smp_no_rendezvous_barrier, pmap_update_pde_action,
2897 pmap_update_pde_teardown, &act);
2899 pmap_update_pde_store(pmap, pde, newpde);
2900 if (CPU_ISSET(cpuid, &active))
2901 pmap_update_pde_invalidate(pmap, va, newpde);
2907 * Normal, non-SMP, invalidation functions.
2910 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
2912 struct invpcid_descr d;
2913 uint64_t kcr3, ucr3;
2916 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
2920 KASSERT(pmap->pm_type == PT_X86,
2921 ("pmap_invalidate_range: unknown type %d", pmap->pm_type));
2923 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap)) {
2925 if (pmap == PCPU_GET(curpmap) && pmap_pcid_enabled &&
2926 pmap->pm_ucr3 != PMAP_NO_CR3) {
2928 pcid = pmap->pm_pcids[0].pm_pcid;
2929 if (invpcid_works) {
2930 d.pcid = pcid | PMAP_PCID_USER_PT;
2933 invpcid(&d, INVPCID_ADDR);
2935 kcr3 = pmap->pm_cr3 | pcid | CR3_PCID_SAVE;
2936 ucr3 = pmap->pm_ucr3 | pcid |
2937 PMAP_PCID_USER_PT | CR3_PCID_SAVE;
2938 pmap_pti_pcid_invlpg(ucr3, kcr3, va);
2942 } else if (pmap_pcid_enabled)
2943 pmap->pm_pcids[0].pm_gen = 0;
2947 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2949 struct invpcid_descr d;
2951 uint64_t kcr3, ucr3;
2953 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
2957 KASSERT(pmap->pm_type == PT_X86,
2958 ("pmap_invalidate_range: unknown type %d", pmap->pm_type));
2960 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap)) {
2961 for (addr = sva; addr < eva; addr += PAGE_SIZE)
2963 if (pmap == PCPU_GET(curpmap) && pmap_pcid_enabled &&
2964 pmap->pm_ucr3 != PMAP_NO_CR3) {
2966 if (invpcid_works) {
2967 d.pcid = pmap->pm_pcids[0].pm_pcid |
2971 for (; d.addr < eva; d.addr += PAGE_SIZE)
2972 invpcid(&d, INVPCID_ADDR);
2974 kcr3 = pmap->pm_cr3 | pmap->pm_pcids[0].
2975 pm_pcid | CR3_PCID_SAVE;
2976 ucr3 = pmap->pm_ucr3 | pmap->pm_pcids[0].
2977 pm_pcid | PMAP_PCID_USER_PT | CR3_PCID_SAVE;
2978 pmap_pti_pcid_invlrng(ucr3, kcr3, sva, eva);
2982 } else if (pmap_pcid_enabled) {
2983 pmap->pm_pcids[0].pm_gen = 0;
2988 pmap_invalidate_all(pmap_t pmap)
2990 struct invpcid_descr d;
2991 uint64_t kcr3, ucr3;
2993 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
2997 KASSERT(pmap->pm_type == PT_X86,
2998 ("pmap_invalidate_all: unknown type %d", pmap->pm_type));
3000 if (pmap == kernel_pmap) {
3001 if (pmap_pcid_enabled && invpcid_works) {
3002 bzero(&d, sizeof(d));
3003 invpcid(&d, INVPCID_CTXGLOB);
3007 } else if (pmap == PCPU_GET(curpmap)) {
3008 if (pmap_pcid_enabled) {
3010 if (invpcid_works) {
3011 d.pcid = pmap->pm_pcids[0].pm_pcid;
3014 invpcid(&d, INVPCID_CTX);
3015 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
3016 d.pcid |= PMAP_PCID_USER_PT;
3017 invpcid(&d, INVPCID_CTX);
3020 kcr3 = pmap->pm_cr3 | pmap->pm_pcids[0].pm_pcid;
3021 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
3022 ucr3 = pmap->pm_ucr3 | pmap->pm_pcids[
3023 0].pm_pcid | PMAP_PCID_USER_PT;
3024 pmap_pti_pcid_invalidate(ucr3, kcr3);
3032 } else if (pmap_pcid_enabled) {
3033 pmap->pm_pcids[0].pm_gen = 0;
3038 pmap_invalidate_cache(void)
3045 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
3048 pmap_update_pde_store(pmap, pde, newpde);
3049 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap))
3050 pmap_update_pde_invalidate(pmap, va, newpde);
3052 pmap->pm_pcids[0].pm_gen = 0;
3057 pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va, pd_entry_t pde)
3061 * When the PDE has PG_PROMOTED set, the 2MB page mapping was created
3062 * by a promotion that did not invalidate the 512 4KB page mappings
3063 * that might exist in the TLB. Consequently, at this point, the TLB
3064 * may hold both 4KB and 2MB page mappings for the address range [va,
3065 * va + NBPDR). Therefore, the entire range must be invalidated here.
3066 * In contrast, when PG_PROMOTED is clear, the TLB will not hold any
3067 * 4KB page mappings for the address range [va, va + NBPDR), and so a
3068 * single INVLPG suffices to invalidate the 2MB page mapping from the
3071 if ((pde & PG_PROMOTED) != 0)
3072 pmap_invalidate_range(pmap, va, va + NBPDR - 1);
3074 pmap_invalidate_page(pmap, va);
3077 DEFINE_IFUNC(, void, pmap_invalidate_cache_range,
3078 (vm_offset_t sva, vm_offset_t eva))
3081 if ((cpu_feature & CPUID_SS) != 0)
3082 return (pmap_invalidate_cache_range_selfsnoop);
3083 if ((cpu_feature & CPUID_CLFSH) != 0)
3084 return (pmap_force_invalidate_cache_range);
3085 return (pmap_invalidate_cache_range_all);
3088 #define PMAP_CLFLUSH_THRESHOLD (2 * 1024 * 1024)
3091 pmap_invalidate_cache_range_check_align(vm_offset_t sva, vm_offset_t eva)
3094 KASSERT((sva & PAGE_MASK) == 0,
3095 ("pmap_invalidate_cache_range: sva not page-aligned"));
3096 KASSERT((eva & PAGE_MASK) == 0,
3097 ("pmap_invalidate_cache_range: eva not page-aligned"));
3101 pmap_invalidate_cache_range_selfsnoop(vm_offset_t sva, vm_offset_t eva)
3104 pmap_invalidate_cache_range_check_align(sva, eva);
3108 pmap_force_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva)
3111 sva &= ~(vm_offset_t)(cpu_clflush_line_size - 1);
3114 * XXX: Some CPUs fault, hang, or trash the local APIC
3115 * registers if we use CLFLUSH on the local APIC range. The
3116 * local APIC is always uncached, so we don't need to flush
3117 * for that range anyway.
3119 if (pmap_kextract(sva) == lapic_paddr)
3122 if ((cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0) {
3124 * Do per-cache line flush. Use a locked
3125 * instruction to insure that previous stores are
3126 * included in the write-back. The processor
3127 * propagates flush to other processors in the cache
3130 atomic_thread_fence_seq_cst();
3131 for (; sva < eva; sva += cpu_clflush_line_size)
3133 atomic_thread_fence_seq_cst();
3136 * Writes are ordered by CLFLUSH on Intel CPUs.
3138 if (cpu_vendor_id != CPU_VENDOR_INTEL)
3140 for (; sva < eva; sva += cpu_clflush_line_size)
3142 if (cpu_vendor_id != CPU_VENDOR_INTEL)
3148 pmap_invalidate_cache_range_all(vm_offset_t sva, vm_offset_t eva)
3151 pmap_invalidate_cache_range_check_align(sva, eva);
3152 pmap_invalidate_cache();
3156 * Remove the specified set of pages from the data and instruction caches.
3158 * In contrast to pmap_invalidate_cache_range(), this function does not
3159 * rely on the CPU's self-snoop feature, because it is intended for use
3160 * when moving pages into a different cache domain.
3163 pmap_invalidate_cache_pages(vm_page_t *pages, int count)
3165 vm_offset_t daddr, eva;
3169 useclflushopt = (cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0;
3170 if (count >= PMAP_CLFLUSH_THRESHOLD / PAGE_SIZE ||
3171 ((cpu_feature & CPUID_CLFSH) == 0 && !useclflushopt))
3172 pmap_invalidate_cache();
3175 atomic_thread_fence_seq_cst();
3176 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
3178 for (i = 0; i < count; i++) {
3179 daddr = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pages[i]));
3180 eva = daddr + PAGE_SIZE;
3181 for (; daddr < eva; daddr += cpu_clflush_line_size) {
3189 atomic_thread_fence_seq_cst();
3190 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
3196 pmap_flush_cache_range(vm_offset_t sva, vm_offset_t eva)
3199 pmap_invalidate_cache_range_check_align(sva, eva);
3201 if ((cpu_stdext_feature & CPUID_STDEXT_CLWB) == 0) {
3202 pmap_force_invalidate_cache_range(sva, eva);
3206 /* See comment in pmap_force_invalidate_cache_range(). */
3207 if (pmap_kextract(sva) == lapic_paddr)
3210 atomic_thread_fence_seq_cst();
3211 for (; sva < eva; sva += cpu_clflush_line_size)
3213 atomic_thread_fence_seq_cst();
3217 pmap_flush_cache_phys_range(vm_paddr_t spa, vm_paddr_t epa, vm_memattr_t mattr)
3221 int error, pte_bits;
3223 KASSERT((spa & PAGE_MASK) == 0,
3224 ("pmap_flush_cache_phys_range: spa not page-aligned"));
3225 KASSERT((epa & PAGE_MASK) == 0,
3226 ("pmap_flush_cache_phys_range: epa not page-aligned"));
3228 if (spa < dmaplimit) {
3229 pmap_flush_cache_range(PHYS_TO_DMAP(spa), PHYS_TO_DMAP(MIN(
3231 if (dmaplimit >= epa)
3236 pte_bits = pmap_cache_bits(kernel_pmap, mattr, 0) | X86_PG_RW |
3238 error = vmem_alloc(kernel_arena, PAGE_SIZE, M_BESTFIT | M_WAITOK,
3240 KASSERT(error == 0, ("vmem_alloc failed: %d", error));
3241 pte = vtopte(vaddr);
3242 for (; spa < epa; spa += PAGE_SIZE) {
3244 pte_store(pte, spa | pte_bits);
3246 /* XXXKIB atomic inside flush_cache_range are excessive */
3247 pmap_flush_cache_range(vaddr, vaddr + PAGE_SIZE);
3250 vmem_free(kernel_arena, vaddr, PAGE_SIZE);
3254 * Routine: pmap_extract
3256 * Extract the physical page address associated
3257 * with the given map/virtual_address pair.
3260 pmap_extract(pmap_t pmap, vm_offset_t va)
3264 pt_entry_t *pte, PG_V;
3268 PG_V = pmap_valid_bit(pmap);
3270 pdpe = pmap_pdpe(pmap, va);
3271 if (pdpe != NULL && (*pdpe & PG_V) != 0) {
3272 if ((*pdpe & PG_PS) != 0)
3273 pa = (*pdpe & PG_PS_FRAME) | (va & PDPMASK);
3275 pde = pmap_pdpe_to_pde(pdpe, va);
3276 if ((*pde & PG_V) != 0) {
3277 if ((*pde & PG_PS) != 0) {
3278 pa = (*pde & PG_PS_FRAME) |
3281 pte = pmap_pde_to_pte(pde, va);
3282 pa = (*pte & PG_FRAME) |
3293 * Routine: pmap_extract_and_hold
3295 * Atomically extract and hold the physical page
3296 * with the given pmap and virtual address pair
3297 * if that mapping permits the given protection.
3300 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
3302 pd_entry_t pde, *pdep;
3303 pt_entry_t pte, PG_RW, PG_V;
3307 PG_RW = pmap_rw_bit(pmap);
3308 PG_V = pmap_valid_bit(pmap);
3311 pdep = pmap_pde(pmap, va);
3312 if (pdep != NULL && (pde = *pdep)) {
3314 if ((pde & PG_RW) != 0 || (prot & VM_PROT_WRITE) == 0)
3315 m = PHYS_TO_VM_PAGE((pde & PG_PS_FRAME) |
3318 pte = *pmap_pde_to_pte(pdep, va);
3319 if ((pte & PG_V) != 0 &&
3320 ((pte & PG_RW) != 0 || (prot & VM_PROT_WRITE) == 0))
3321 m = PHYS_TO_VM_PAGE(pte & PG_FRAME);
3323 if (m != NULL && !vm_page_wire_mapped(m))
3331 pmap_kextract(vm_offset_t va)
3336 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS) {
3337 pa = DMAP_TO_PHYS(va);
3338 } else if (PMAP_ADDRESS_IN_LARGEMAP(va)) {
3339 pa = pmap_large_map_kextract(va);
3343 pa = (pde & PG_PS_FRAME) | (va & PDRMASK);
3346 * Beware of a concurrent promotion that changes the
3347 * PDE at this point! For example, vtopte() must not
3348 * be used to access the PTE because it would use the
3349 * new PDE. It is, however, safe to use the old PDE
3350 * because the page table page is preserved by the
3353 pa = *pmap_pde_to_pte(&pde, va);
3354 pa = (pa & PG_FRAME) | (va & PAGE_MASK);
3360 /***************************************************
3361 * Low level mapping routines.....
3362 ***************************************************/
3365 * Add a wired page to the kva.
3366 * Note: not SMP coherent.
3369 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
3374 pte_store(pte, pa | X86_PG_RW | X86_PG_V | pg_g | pg_nx);
3377 static __inline void
3378 pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode)
3384 cache_bits = pmap_cache_bits(kernel_pmap, mode, 0);
3385 pte_store(pte, pa | X86_PG_RW | X86_PG_V | pg_g | pg_nx | cache_bits);
3389 * Remove a page from the kernel pagetables.
3390 * Note: not SMP coherent.
3393 pmap_kremove(vm_offset_t va)
3402 * Used to map a range of physical addresses into kernel
3403 * virtual address space.
3405 * The value passed in '*virt' is a suggested virtual address for
3406 * the mapping. Architectures which can support a direct-mapped
3407 * physical to virtual region can return the appropriate address
3408 * within that region, leaving '*virt' unchanged. Other
3409 * architectures should map the pages starting at '*virt' and
3410 * update '*virt' with the first usable address after the mapped
3414 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
3416 return PHYS_TO_DMAP(start);
3421 * Add a list of wired pages to the kva
3422 * this routine is only used for temporary
3423 * kernel mappings that do not need to have
3424 * page modification or references recorded.
3425 * Note that old mappings are simply written
3426 * over. The page *must* be wired.
3427 * Note: SMP coherent. Uses a ranged shootdown IPI.
3430 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
3432 pt_entry_t *endpte, oldpte, pa, *pte;
3438 endpte = pte + count;
3439 while (pte < endpte) {
3441 cache_bits = pmap_cache_bits(kernel_pmap, m->md.pat_mode, 0);
3442 pa = VM_PAGE_TO_PHYS(m) | cache_bits;
3443 if ((*pte & (PG_FRAME | X86_PG_PTE_CACHE)) != pa) {
3445 pte_store(pte, pa | pg_g | pg_nx | X86_PG_RW | X86_PG_V);
3449 if (__predict_false((oldpte & X86_PG_V) != 0))
3450 pmap_invalidate_range(kernel_pmap, sva, sva + count *
3455 * This routine tears out page mappings from the
3456 * kernel -- it is meant only for temporary mappings.
3457 * Note: SMP coherent. Uses a ranged shootdown IPI.
3460 pmap_qremove(vm_offset_t sva, int count)
3465 while (count-- > 0) {
3466 KASSERT(va >= VM_MIN_KERNEL_ADDRESS, ("usermode va %lx", va));
3470 pmap_invalidate_range(kernel_pmap, sva, va);
3473 /***************************************************
3474 * Page table page management routines.....
3475 ***************************************************/
3477 * Schedule the specified unused page table page to be freed. Specifically,
3478 * add the page to the specified list of pages that will be released to the
3479 * physical memory manager after the TLB has been updated.
3481 static __inline void
3482 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
3483 boolean_t set_PG_ZERO)
3487 m->flags |= PG_ZERO;
3489 m->flags &= ~PG_ZERO;
3490 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
3494 * Inserts the specified page table page into the specified pmap's collection
3495 * of idle page table pages. Each of a pmap's page table pages is responsible
3496 * for mapping a distinct range of virtual addresses. The pmap's collection is
3497 * ordered by this virtual address range.
3499 * If "promoted" is false, then the page table page "mpte" must be zero filled.
3502 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte, bool promoted)
3505 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3506 mpte->valid = promoted ? VM_PAGE_BITS_ALL : 0;
3507 return (vm_radix_insert(&pmap->pm_root, mpte));
3511 * Removes the page table page mapping the specified virtual address from the
3512 * specified pmap's collection of idle page table pages, and returns it.
3513 * Otherwise, returns NULL if there is no page table page corresponding to the
3514 * specified virtual address.
3516 static __inline vm_page_t
3517 pmap_remove_pt_page(pmap_t pmap, vm_offset_t va)
3520 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3521 return (vm_radix_remove(&pmap->pm_root, pmap_pde_pindex(va)));
3525 * Decrements a page table page's reference count, which is used to record the
3526 * number of valid page table entries within the page. If the reference count
3527 * drops to zero, then the page table page is unmapped. Returns TRUE if the
3528 * page table page was unmapped and FALSE otherwise.
3530 static inline boolean_t
3531 pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
3535 if (m->ref_count == 0) {
3536 _pmap_unwire_ptp(pmap, va, m, free);
3543 _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
3546 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3548 * unmap the page table page
3550 if (m->pindex >= NUPDE + NUPDPE) {
3553 pml4 = pmap_pml4e(pmap, va);
3555 if (pmap->pm_pml4u != NULL && va <= VM_MAXUSER_ADDRESS) {
3556 pml4 = &pmap->pm_pml4u[pmap_pml4e_index(va)];
3559 } else if (m->pindex >= NUPDE) {
3562 pdp = pmap_pdpe(pmap, va);
3567 pd = pmap_pde(pmap, va);
3570 pmap_resident_count_dec(pmap, 1);
3571 if (m->pindex < NUPDE) {
3572 /* We just released a PT, unhold the matching PD */
3575 pdpg = PHYS_TO_VM_PAGE(*pmap_pdpe(pmap, va) & PG_FRAME);
3576 pmap_unwire_ptp(pmap, va, pdpg, free);
3577 } else if (m->pindex < NUPDE + NUPDPE) {
3578 /* We just released a PD, unhold the matching PDP */
3581 pdppg = PHYS_TO_VM_PAGE(*pmap_pml4e(pmap, va) & PG_FRAME);
3582 pmap_unwire_ptp(pmap, va, pdppg, free);
3586 * Put page on a list so that it is released after
3587 * *ALL* TLB shootdown is done
3589 pmap_add_delayed_free_list(m, free, TRUE);
3593 * After removing a page table entry, this routine is used to
3594 * conditionally free the page, and manage the reference count.
3597 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, pd_entry_t ptepde,
3598 struct spglist *free)
3602 if (va >= VM_MAXUSER_ADDRESS)
3604 KASSERT(ptepde != 0, ("pmap_unuse_pt: ptepde != 0"));
3605 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME);
3606 return (pmap_unwire_ptp(pmap, va, mpte, free));
3610 * Release a page table page reference after a failed attempt to create a
3614 pmap_abort_ptp(pmap_t pmap, vm_offset_t va, vm_page_t mpte)
3616 struct spglist free;
3619 if (pmap_unwire_ptp(pmap, va, mpte, &free)) {
3621 * Although "va" was never mapped, paging-structure caches
3622 * could nonetheless have entries that refer to the freed
3623 * page table pages. Invalidate those entries.
3625 pmap_invalidate_page(pmap, va);
3626 vm_page_free_pages_toq(&free, true);
3631 pmap_pinit0(pmap_t pmap)
3637 PMAP_LOCK_INIT(pmap);
3638 pmap->pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(KPML4phys);
3639 pmap->pm_pml4u = NULL;
3640 pmap->pm_cr3 = KPML4phys;
3641 /* hack to keep pmap_pti_pcid_invalidate() alive */
3642 pmap->pm_ucr3 = PMAP_NO_CR3;
3643 pmap->pm_root.rt_root = 0;
3644 CPU_ZERO(&pmap->pm_active);
3645 TAILQ_INIT(&pmap->pm_pvchunk);
3646 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
3647 pmap->pm_flags = pmap_flags;
3649 pmap->pm_pcids[i].pm_pcid = PMAP_PCID_KERN + 1;
3650 pmap->pm_pcids[i].pm_gen = 1;
3652 pmap_activate_boot(pmap);
3657 p->p_md.md_flags |= P_MD_KPTI;
3660 pmap_thread_init_invl_gen(td);
3662 if ((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0) {
3663 pmap_pkru_ranges_zone = uma_zcreate("pkru ranges",
3664 sizeof(struct pmap_pkru_range), NULL, NULL, NULL, NULL,
3670 pmap_pinit_pml4(vm_page_t pml4pg)
3672 pml4_entry_t *pm_pml4;
3675 pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4pg));
3677 /* Wire in kernel global address entries. */
3678 for (i = 0; i < NKPML4E; i++) {
3679 pm_pml4[KPML4BASE + i] = (KPDPphys + ptoa(i)) | X86_PG_RW |
3682 for (i = 0; i < ndmpdpphys; i++) {
3683 pm_pml4[DMPML4I + i] = (DMPDPphys + ptoa(i)) | X86_PG_RW |
3687 /* install self-referential address mapping entry(s) */
3688 pm_pml4[PML4PML4I] = VM_PAGE_TO_PHYS(pml4pg) | X86_PG_V | X86_PG_RW |
3689 X86_PG_A | X86_PG_M;
3691 /* install large map entries if configured */
3692 for (i = 0; i < lm_ents; i++)
3693 pm_pml4[LMSPML4I + i] = kernel_pmap->pm_pml4[LMSPML4I + i];
3697 pmap_pinit_pml4_pti(vm_page_t pml4pg)
3699 pml4_entry_t *pm_pml4;
3702 pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4pg));
3703 for (i = 0; i < NPML4EPG; i++)
3704 pm_pml4[i] = pti_pml4[i];
3708 * Initialize a preallocated and zeroed pmap structure,
3709 * such as one in a vmspace structure.
3712 pmap_pinit_type(pmap_t pmap, enum pmap_type pm_type, int flags)
3714 vm_page_t pml4pg, pml4pgu;
3715 vm_paddr_t pml4phys;
3719 * allocate the page directory page
3721 pml4pg = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
3722 VM_ALLOC_WIRED | VM_ALLOC_ZERO | VM_ALLOC_WAITOK);
3724 pml4phys = VM_PAGE_TO_PHYS(pml4pg);
3725 pmap->pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(pml4phys);
3727 pmap->pm_pcids[i].pm_pcid = PMAP_PCID_NONE;
3728 pmap->pm_pcids[i].pm_gen = 0;
3730 pmap->pm_cr3 = PMAP_NO_CR3; /* initialize to an invalid value */
3731 pmap->pm_ucr3 = PMAP_NO_CR3;
3732 pmap->pm_pml4u = NULL;
3734 pmap->pm_type = pm_type;
3735 if ((pml4pg->flags & PG_ZERO) == 0)
3736 pagezero(pmap->pm_pml4);
3739 * Do not install the host kernel mappings in the nested page
3740 * tables. These mappings are meaningless in the guest physical
3742 * Install minimal kernel mappings in PTI case.
3744 if (pm_type == PT_X86) {
3745 pmap->pm_cr3 = pml4phys;
3746 pmap_pinit_pml4(pml4pg);
3747 if ((curproc->p_md.md_flags & P_MD_KPTI) != 0) {
3748 pml4pgu = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
3749 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | VM_ALLOC_WAITOK);
3750 pmap->pm_pml4u = (pml4_entry_t *)PHYS_TO_DMAP(
3751 VM_PAGE_TO_PHYS(pml4pgu));
3752 pmap_pinit_pml4_pti(pml4pgu);
3753 pmap->pm_ucr3 = VM_PAGE_TO_PHYS(pml4pgu);
3755 if ((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0) {
3756 rangeset_init(&pmap->pm_pkru, pkru_dup_range,
3757 pkru_free_range, pmap, M_NOWAIT);
3761 pmap->pm_root.rt_root = 0;
3762 CPU_ZERO(&pmap->pm_active);
3763 TAILQ_INIT(&pmap->pm_pvchunk);
3764 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
3765 pmap->pm_flags = flags;
3766 pmap->pm_eptgen = 0;
3772 pmap_pinit(pmap_t pmap)
3775 return (pmap_pinit_type(pmap, PT_X86, pmap_flags));
3779 * This routine is called if the desired page table page does not exist.
3781 * If page table page allocation fails, this routine may sleep before
3782 * returning NULL. It sleeps only if a lock pointer was given.
3784 * Note: If a page allocation fails at page table level two or three,
3785 * one or two pages may be held during the wait, only to be released
3786 * afterwards. This conservative approach is easily argued to avoid
3790 _pmap_allocpte(pmap_t pmap, vm_pindex_t ptepindex, struct rwlock **lockp)
3792 vm_page_t m, pdppg, pdpg;
3793 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
3795 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3797 PG_A = pmap_accessed_bit(pmap);
3798 PG_M = pmap_modified_bit(pmap);
3799 PG_V = pmap_valid_bit(pmap);
3800 PG_RW = pmap_rw_bit(pmap);
3803 * Allocate a page table page.
3805 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
3806 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
3807 if (lockp != NULL) {
3808 RELEASE_PV_LIST_LOCK(lockp);
3810 PMAP_ASSERT_NOT_IN_DI();
3816 * Indicate the need to retry. While waiting, the page table
3817 * page may have been allocated.
3821 if ((m->flags & PG_ZERO) == 0)
3825 * Map the pagetable page into the process address space, if
3826 * it isn't already there.
3829 if (ptepindex >= (NUPDE + NUPDPE)) {
3830 pml4_entry_t *pml4, *pml4u;
3831 vm_pindex_t pml4index;
3833 /* Wire up a new PDPE page */
3834 pml4index = ptepindex - (NUPDE + NUPDPE);
3835 pml4 = &pmap->pm_pml4[pml4index];
3836 *pml4 = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
3837 if (pmap->pm_pml4u != NULL && pml4index < NUPML4E) {
3839 * PTI: Make all user-space mappings in the
3840 * kernel-mode page table no-execute so that
3841 * we detect any programming errors that leave
3842 * the kernel-mode page table active on return
3845 if (pmap->pm_ucr3 != PMAP_NO_CR3)
3848 pml4u = &pmap->pm_pml4u[pml4index];
3849 *pml4u = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V |
3853 } else if (ptepindex >= NUPDE) {
3854 vm_pindex_t pml4index;
3855 vm_pindex_t pdpindex;
3859 /* Wire up a new PDE page */
3860 pdpindex = ptepindex - NUPDE;
3861 pml4index = pdpindex >> NPML4EPGSHIFT;
3863 pml4 = &pmap->pm_pml4[pml4index];
3864 if ((*pml4 & PG_V) == 0) {
3865 /* Have to allocate a new pdp, recurse */
3866 if (_pmap_allocpte(pmap, NUPDE + NUPDPE + pml4index,
3868 vm_page_unwire_noq(m);
3869 vm_page_free_zero(m);
3873 /* Add reference to pdp page */
3874 pdppg = PHYS_TO_VM_PAGE(*pml4 & PG_FRAME);
3877 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
3879 /* Now find the pdp page */
3880 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)];
3881 *pdp = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
3884 vm_pindex_t pml4index;
3885 vm_pindex_t pdpindex;
3890 /* Wire up a new PTE page */
3891 pdpindex = ptepindex >> NPDPEPGSHIFT;
3892 pml4index = pdpindex >> NPML4EPGSHIFT;
3894 /* First, find the pdp and check that its valid. */
3895 pml4 = &pmap->pm_pml4[pml4index];
3896 if ((*pml4 & PG_V) == 0) {
3897 /* Have to allocate a new pd, recurse */
3898 if (_pmap_allocpte(pmap, NUPDE + pdpindex,
3900 vm_page_unwire_noq(m);
3901 vm_page_free_zero(m);
3904 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
3905 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)];
3907 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
3908 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)];
3909 if ((*pdp & PG_V) == 0) {
3910 /* Have to allocate a new pd, recurse */
3911 if (_pmap_allocpte(pmap, NUPDE + pdpindex,
3913 vm_page_unwire_noq(m);
3914 vm_page_free_zero(m);
3918 /* Add reference to the pd page */
3919 pdpg = PHYS_TO_VM_PAGE(*pdp & PG_FRAME);
3923 pd = (pd_entry_t *)PHYS_TO_DMAP(*pdp & PG_FRAME);
3925 /* Now we know where the page directory page is */
3926 pd = &pd[ptepindex & ((1ul << NPDEPGSHIFT) - 1)];
3927 *pd = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
3930 pmap_resident_count_inc(pmap, 1);
3936 pmap_alloc_pde(pmap_t pmap, vm_offset_t va, vm_page_t *pdpgp,
3937 struct rwlock **lockp)
3939 pdp_entry_t *pdpe, PG_V;
3942 vm_pindex_t pdpindex;
3944 PG_V = pmap_valid_bit(pmap);
3947 pdpe = pmap_pdpe(pmap, va);
3948 if (pdpe != NULL && (*pdpe & PG_V) != 0) {
3949 pde = pmap_pdpe_to_pde(pdpe, va);
3950 if (va < VM_MAXUSER_ADDRESS) {
3951 /* Add a reference to the pd page. */
3952 pdpg = PHYS_TO_VM_PAGE(*pdpe & PG_FRAME);
3956 } else if (va < VM_MAXUSER_ADDRESS) {
3957 /* Allocate a pd page. */
3958 pdpindex = pmap_pde_pindex(va) >> NPDPEPGSHIFT;
3959 pdpg = _pmap_allocpte(pmap, NUPDE + pdpindex, lockp);
3966 pde = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pdpg));
3967 pde = &pde[pmap_pde_index(va)];
3969 panic("pmap_alloc_pde: missing page table page for va %#lx",
3976 pmap_allocpte(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
3978 vm_pindex_t ptepindex;
3979 pd_entry_t *pd, PG_V;
3982 PG_V = pmap_valid_bit(pmap);
3985 * Calculate pagetable page index
3987 ptepindex = pmap_pde_pindex(va);
3990 * Get the page directory entry
3992 pd = pmap_pde(pmap, va);
3995 * This supports switching from a 2MB page to a
3998 if (pd != NULL && (*pd & (PG_PS | PG_V)) == (PG_PS | PG_V)) {
3999 if (!pmap_demote_pde_locked(pmap, pd, va, lockp)) {
4001 * Invalidation of the 2MB page mapping may have caused
4002 * the deallocation of the underlying PD page.
4009 * If the page table page is mapped, we just increment the
4010 * hold count, and activate it.
4012 if (pd != NULL && (*pd & PG_V) != 0) {
4013 m = PHYS_TO_VM_PAGE(*pd & PG_FRAME);
4017 * Here if the pte page isn't mapped, or if it has been
4020 m = _pmap_allocpte(pmap, ptepindex, lockp);
4021 if (m == NULL && lockp != NULL)
4028 /***************************************************
4029 * Pmap allocation/deallocation routines.
4030 ***************************************************/
4033 * Release any resources held by the given physical map.
4034 * Called when a pmap initialized by pmap_pinit is being released.
4035 * Should only be called if the map contains no valid mappings.
4038 pmap_release(pmap_t pmap)
4043 KASSERT(pmap->pm_stats.resident_count == 0,
4044 ("pmap_release: pmap resident count %ld != 0",
4045 pmap->pm_stats.resident_count));
4046 KASSERT(vm_radix_is_empty(&pmap->pm_root),
4047 ("pmap_release: pmap has reserved page table page(s)"));
4048 KASSERT(CPU_EMPTY(&pmap->pm_active),
4049 ("releasing active pmap %p", pmap));
4051 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pmap->pm_pml4));
4053 for (i = 0; i < NKPML4E; i++) /* KVA */
4054 pmap->pm_pml4[KPML4BASE + i] = 0;
4055 for (i = 0; i < ndmpdpphys; i++)/* Direct Map */
4056 pmap->pm_pml4[DMPML4I + i] = 0;
4057 pmap->pm_pml4[PML4PML4I] = 0; /* Recursive Mapping */
4058 for (i = 0; i < lm_ents; i++) /* Large Map */
4059 pmap->pm_pml4[LMSPML4I + i] = 0;
4061 vm_page_unwire_noq(m);
4062 vm_page_free_zero(m);
4064 if (pmap->pm_pml4u != NULL) {
4065 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pmap->pm_pml4u));
4066 vm_page_unwire_noq(m);
4069 if (pmap->pm_type == PT_X86 &&
4070 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0)
4071 rangeset_fini(&pmap->pm_pkru);
4075 kvm_size(SYSCTL_HANDLER_ARGS)
4077 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS;
4079 return sysctl_handle_long(oidp, &ksize, 0, req);
4081 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG | CTLFLAG_RD | CTLFLAG_MPSAFE,
4082 0, 0, kvm_size, "LU",
4086 kvm_free(SYSCTL_HANDLER_ARGS)
4088 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
4090 return sysctl_handle_long(oidp, &kfree, 0, req);
4092 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG | CTLFLAG_RD | CTLFLAG_MPSAFE,
4093 0, 0, kvm_free, "LU",
4094 "Amount of KVM free");
4097 * Allocate physical memory for the vm_page array and map it into KVA,
4098 * attempting to back the vm_pages with domain-local memory.
4101 pmap_page_array_startup(long pages)
4104 pd_entry_t *pde, newpdir;
4105 vm_offset_t va, start, end;
4110 vm_page_array_size = pages;
4112 start = VM_MIN_KERNEL_ADDRESS;
4113 end = start + pages * sizeof(struct vm_page);
4114 for (va = start; va < end; va += NBPDR) {
4115 pfn = first_page + (va - start) / sizeof(struct vm_page);
4116 domain = _vm_phys_domain(ptoa(pfn));
4117 pdpe = pmap_pdpe(kernel_pmap, va);
4118 if ((*pdpe & X86_PG_V) == 0) {
4119 pa = vm_phys_early_alloc(domain, PAGE_SIZE);
4121 pagezero((void *)PHYS_TO_DMAP(pa));
4122 *pdpe = (pdp_entry_t)(pa | X86_PG_V | X86_PG_RW |
4123 X86_PG_A | X86_PG_M);
4125 pde = pmap_pdpe_to_pde(pdpe, va);
4126 if ((*pde & X86_PG_V) != 0)
4127 panic("Unexpected pde");
4128 pa = vm_phys_early_alloc(domain, NBPDR);
4129 for (i = 0; i < NPDEPG; i++)
4130 dump_add_page(pa + i * PAGE_SIZE);
4131 newpdir = (pd_entry_t)(pa | X86_PG_V | X86_PG_RW | X86_PG_A |
4132 X86_PG_M | PG_PS | pg_g | pg_nx);
4133 pde_store(pde, newpdir);
4135 vm_page_array = (vm_page_t)start;
4139 * grow the number of kernel page table entries, if needed
4142 pmap_growkernel(vm_offset_t addr)
4146 pd_entry_t *pde, newpdir;
4149 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
4152 * Return if "addr" is within the range of kernel page table pages
4153 * that were preallocated during pmap bootstrap. Moreover, leave
4154 * "kernel_vm_end" and the kernel page table as they were.
4156 * The correctness of this action is based on the following
4157 * argument: vm_map_insert() allocates contiguous ranges of the
4158 * kernel virtual address space. It calls this function if a range
4159 * ends after "kernel_vm_end". If the kernel is mapped between
4160 * "kernel_vm_end" and "addr", then the range cannot begin at
4161 * "kernel_vm_end". In fact, its beginning address cannot be less
4162 * than the kernel. Thus, there is no immediate need to allocate
4163 * any new kernel page table pages between "kernel_vm_end" and
4166 if (KERNBASE < addr && addr <= KERNBASE + nkpt * NBPDR)
4169 addr = roundup2(addr, NBPDR);
4170 if (addr - 1 >= vm_map_max(kernel_map))
4171 addr = vm_map_max(kernel_map);
4172 while (kernel_vm_end < addr) {
4173 pdpe = pmap_pdpe(kernel_pmap, kernel_vm_end);
4174 if ((*pdpe & X86_PG_V) == 0) {
4175 /* We need a new PDP entry */
4176 nkpg = vm_page_alloc(NULL, kernel_vm_end >> PDPSHIFT,
4177 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ |
4178 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
4180 panic("pmap_growkernel: no memory to grow kernel");
4181 if ((nkpg->flags & PG_ZERO) == 0)
4182 pmap_zero_page(nkpg);
4183 paddr = VM_PAGE_TO_PHYS(nkpg);
4184 *pdpe = (pdp_entry_t)(paddr | X86_PG_V | X86_PG_RW |
4185 X86_PG_A | X86_PG_M);
4186 continue; /* try again */
4188 pde = pmap_pdpe_to_pde(pdpe, kernel_vm_end);
4189 if ((*pde & X86_PG_V) != 0) {
4190 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
4191 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
4192 kernel_vm_end = vm_map_max(kernel_map);
4198 nkpg = vm_page_alloc(NULL, pmap_pde_pindex(kernel_vm_end),
4199 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
4202 panic("pmap_growkernel: no memory to grow kernel");
4203 if ((nkpg->flags & PG_ZERO) == 0)
4204 pmap_zero_page(nkpg);
4205 paddr = VM_PAGE_TO_PHYS(nkpg);
4206 newpdir = paddr | X86_PG_V | X86_PG_RW | X86_PG_A | X86_PG_M;
4207 pde_store(pde, newpdir);
4209 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
4210 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
4211 kernel_vm_end = vm_map_max(kernel_map);
4218 /***************************************************
4219 * page management routines.
4220 ***************************************************/
4222 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
4223 CTASSERT(_NPCM == 3);
4224 CTASSERT(_NPCPV == 168);
4226 static __inline struct pv_chunk *
4227 pv_to_chunk(pv_entry_t pv)
4230 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
4233 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
4235 #define PC_FREE0 0xfffffffffffffffful
4236 #define PC_FREE1 0xfffffffffffffffful
4237 #define PC_FREE2 0x000000fffffffffful
4239 static const uint64_t pc_freemask[_NPCM] = { PC_FREE0, PC_FREE1, PC_FREE2 };
4242 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
4244 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
4245 "Current number of pv entry chunks");
4246 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
4247 "Current number of pv entry chunks allocated");
4248 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
4249 "Current number of pv entry chunks frees");
4250 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
4251 "Number of times tried to get a chunk page but failed.");
4253 static long pv_entry_frees, pv_entry_allocs, pv_entry_count;
4254 static int pv_entry_spare;
4256 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
4257 "Current number of pv entry frees");
4258 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
4259 "Current number of pv entry allocs");
4260 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
4261 "Current number of pv entries");
4262 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
4263 "Current number of spare pv entries");
4267 reclaim_pv_chunk_leave_pmap(pmap_t pmap, pmap_t locked_pmap, bool start_di)
4272 pmap_invalidate_all(pmap);
4273 if (pmap != locked_pmap)
4276 pmap_delayed_invl_finish();
4280 * We are in a serious low memory condition. Resort to
4281 * drastic measures to free some pages so we can allocate
4282 * another pv entry chunk.
4284 * Returns NULL if PV entries were reclaimed from the specified pmap.
4286 * We do not, however, unmap 2mpages because subsequent accesses will
4287 * allocate per-page pv entries until repromotion occurs, thereby
4288 * exacerbating the shortage of free pv entries.
4291 reclaim_pv_chunk_domain(pmap_t locked_pmap, struct rwlock **lockp, int domain)
4293 struct pv_chunks_list *pvc;
4294 struct pv_chunk *pc, *pc_marker, *pc_marker_end;
4295 struct pv_chunk_header pc_marker_b, pc_marker_end_b;
4296 struct md_page *pvh;
4298 pmap_t next_pmap, pmap;
4299 pt_entry_t *pte, tpte;
4300 pt_entry_t PG_G, PG_A, PG_M, PG_RW;
4304 struct spglist free;
4306 int bit, field, freed;
4307 bool start_di, restart;
4309 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
4310 KASSERT(lockp != NULL, ("reclaim_pv_chunk: lockp is NULL"));
4313 PG_G = PG_A = PG_M = PG_RW = 0;
4315 bzero(&pc_marker_b, sizeof(pc_marker_b));
4316 bzero(&pc_marker_end_b, sizeof(pc_marker_end_b));
4317 pc_marker = (struct pv_chunk *)&pc_marker_b;
4318 pc_marker_end = (struct pv_chunk *)&pc_marker_end_b;
4321 * A delayed invalidation block should already be active if
4322 * pmap_advise() or pmap_remove() called this function by way
4323 * of pmap_demote_pde_locked().
4325 start_di = pmap_not_in_di();
4327 pvc = &pv_chunks[domain];
4328 mtx_lock(&pvc->pvc_lock);
4329 pvc->active_reclaims++;
4330 TAILQ_INSERT_HEAD(&pvc->pvc_list, pc_marker, pc_lru);
4331 TAILQ_INSERT_TAIL(&pvc->pvc_list, pc_marker_end, pc_lru);
4332 while ((pc = TAILQ_NEXT(pc_marker, pc_lru)) != pc_marker_end &&
4333 SLIST_EMPTY(&free)) {
4334 next_pmap = pc->pc_pmap;
4335 if (next_pmap == NULL) {
4337 * The next chunk is a marker. However, it is
4338 * not our marker, so active_reclaims must be
4339 * > 1. Consequently, the next_chunk code
4340 * will not rotate the pv_chunks list.
4344 mtx_unlock(&pvc->pvc_lock);
4347 * A pv_chunk can only be removed from the pc_lru list
4348 * when both pc_chunks_mutex is owned and the
4349 * corresponding pmap is locked.
4351 if (pmap != next_pmap) {
4353 reclaim_pv_chunk_leave_pmap(pmap, locked_pmap,
4356 /* Avoid deadlock and lock recursion. */
4357 if (pmap > locked_pmap) {
4358 RELEASE_PV_LIST_LOCK(lockp);
4361 pmap_delayed_invl_start();
4362 mtx_lock(&pvc->pvc_lock);
4364 } else if (pmap != locked_pmap) {
4365 if (PMAP_TRYLOCK(pmap)) {
4367 pmap_delayed_invl_start();
4368 mtx_lock(&pvc->pvc_lock);
4371 pmap = NULL; /* pmap is not locked */
4372 mtx_lock(&pvc->pvc_lock);
4373 pc = TAILQ_NEXT(pc_marker, pc_lru);
4375 pc->pc_pmap != next_pmap)
4379 } else if (start_di)
4380 pmap_delayed_invl_start();
4381 PG_G = pmap_global_bit(pmap);
4382 PG_A = pmap_accessed_bit(pmap);
4383 PG_M = pmap_modified_bit(pmap);
4384 PG_RW = pmap_rw_bit(pmap);
4390 * Destroy every non-wired, 4 KB page mapping in the chunk.
4393 for (field = 0; field < _NPCM; field++) {
4394 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
4395 inuse != 0; inuse &= ~(1UL << bit)) {
4397 pv = &pc->pc_pventry[field * 64 + bit];
4399 pde = pmap_pde(pmap, va);
4400 if ((*pde & PG_PS) != 0)
4402 pte = pmap_pde_to_pte(pde, va);
4403 if ((*pte & PG_W) != 0)
4405 tpte = pte_load_clear(pte);
4406 if ((tpte & PG_G) != 0)
4407 pmap_invalidate_page(pmap, va);
4408 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
4409 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
4411 if ((tpte & PG_A) != 0)
4412 vm_page_aflag_set(m, PGA_REFERENCED);
4413 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
4414 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4416 if (TAILQ_EMPTY(&m->md.pv_list) &&
4417 (m->flags & PG_FICTITIOUS) == 0) {
4418 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4419 if (TAILQ_EMPTY(&pvh->pv_list)) {
4420 vm_page_aflag_clear(m,
4424 pmap_delayed_invl_page(m);
4425 pc->pc_map[field] |= 1UL << bit;
4426 pmap_unuse_pt(pmap, va, *pde, &free);
4431 mtx_lock(&pvc->pvc_lock);
4434 /* Every freed mapping is for a 4 KB page. */
4435 pmap_resident_count_dec(pmap, freed);
4436 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
4437 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
4438 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
4439 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4440 if (pc->pc_map[0] == PC_FREE0 && pc->pc_map[1] == PC_FREE1 &&
4441 pc->pc_map[2] == PC_FREE2) {
4442 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
4443 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
4444 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
4445 /* Entire chunk is free; return it. */
4446 m_pc = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
4447 dump_drop_page(m_pc->phys_addr);
4448 mtx_lock(&pvc->pvc_lock);
4449 TAILQ_REMOVE(&pvc->pvc_list, pc, pc_lru);
4452 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
4453 mtx_lock(&pvc->pvc_lock);
4454 /* One freed pv entry in locked_pmap is sufficient. */
4455 if (pmap == locked_pmap)
4458 TAILQ_REMOVE(&pvc->pvc_list, pc_marker, pc_lru);
4459 TAILQ_INSERT_AFTER(&pvc->pvc_list, pc, pc_marker, pc_lru);
4460 if (pvc->active_reclaims == 1 && pmap != NULL) {
4462 * Rotate the pv chunks list so that we do not
4463 * scan the same pv chunks that could not be
4464 * freed (because they contained a wired
4465 * and/or superpage mapping) on every
4466 * invocation of reclaim_pv_chunk().
4468 while ((pc = TAILQ_FIRST(&pvc->pvc_list)) != pc_marker) {
4469 MPASS(pc->pc_pmap != NULL);
4470 TAILQ_REMOVE(&pvc->pvc_list, pc, pc_lru);
4471 TAILQ_INSERT_TAIL(&pvc->pvc_list, pc, pc_lru);
4475 TAILQ_REMOVE(&pvc->pvc_list, pc_marker, pc_lru);
4476 TAILQ_REMOVE(&pvc->pvc_list, pc_marker_end, pc_lru);
4477 pvc->active_reclaims--;
4478 mtx_unlock(&pvc->pvc_lock);
4479 reclaim_pv_chunk_leave_pmap(pmap, locked_pmap, start_di);
4480 if (m_pc == NULL && !SLIST_EMPTY(&free)) {
4481 m_pc = SLIST_FIRST(&free);
4482 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
4483 /* Recycle a freed page table page. */
4484 m_pc->ref_count = 1;
4486 vm_page_free_pages_toq(&free, true);
4491 reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp)
4496 domain = PCPU_GET(domain);
4497 for (i = 0; i < vm_ndomains; i++) {
4498 m = reclaim_pv_chunk_domain(locked_pmap, lockp, domain);
4501 domain = (domain + 1) % vm_ndomains;
4508 * free the pv_entry back to the free list
4511 free_pv_entry(pmap_t pmap, pv_entry_t pv)
4513 struct pv_chunk *pc;
4514 int idx, field, bit;
4516 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4517 PV_STAT(atomic_add_long(&pv_entry_frees, 1));
4518 PV_STAT(atomic_add_int(&pv_entry_spare, 1));
4519 PV_STAT(atomic_subtract_long(&pv_entry_count, 1));
4520 pc = pv_to_chunk(pv);
4521 idx = pv - &pc->pc_pventry[0];
4524 pc->pc_map[field] |= 1ul << bit;
4525 if (pc->pc_map[0] != PC_FREE0 || pc->pc_map[1] != PC_FREE1 ||
4526 pc->pc_map[2] != PC_FREE2) {
4527 /* 98% of the time, pc is already at the head of the list. */
4528 if (__predict_false(pc != TAILQ_FIRST(&pmap->pm_pvchunk))) {
4529 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4530 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
4534 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4539 free_pv_chunk_dequeued(struct pv_chunk *pc)
4543 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
4544 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
4545 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
4546 /* entire chunk is free, return it */
4547 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
4548 dump_drop_page(m->phys_addr);
4549 vm_page_unwire_noq(m);
4554 free_pv_chunk(struct pv_chunk *pc)
4556 struct pv_chunks_list *pvc;
4558 pvc = &pv_chunks[pc_to_domain(pc)];
4559 mtx_lock(&pvc->pvc_lock);
4560 TAILQ_REMOVE(&pvc->pvc_list, pc, pc_lru);
4561 mtx_unlock(&pvc->pvc_lock);
4562 free_pv_chunk_dequeued(pc);
4566 free_pv_chunk_batch(struct pv_chunklist *batch)
4568 struct pv_chunks_list *pvc;
4569 struct pv_chunk *pc, *npc;
4572 for (i = 0; i < vm_ndomains; i++) {
4573 if (TAILQ_EMPTY(&batch[i]))
4575 pvc = &pv_chunks[i];
4576 mtx_lock(&pvc->pvc_lock);
4577 TAILQ_FOREACH(pc, &batch[i], pc_list) {
4578 TAILQ_REMOVE(&pvc->pvc_list, pc, pc_lru);
4580 mtx_unlock(&pvc->pvc_lock);
4583 for (i = 0; i < vm_ndomains; i++) {
4584 TAILQ_FOREACH_SAFE(pc, &batch[i], pc_list, npc) {
4585 free_pv_chunk_dequeued(pc);
4591 * Returns a new PV entry, allocating a new PV chunk from the system when
4592 * needed. If this PV chunk allocation fails and a PV list lock pointer was
4593 * given, a PV chunk is reclaimed from an arbitrary pmap. Otherwise, NULL is
4596 * The given PV list lock may be released.
4599 get_pv_entry(pmap_t pmap, struct rwlock **lockp)
4601 struct pv_chunks_list *pvc;
4604 struct pv_chunk *pc;
4607 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4608 PV_STAT(atomic_add_long(&pv_entry_allocs, 1));
4610 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
4612 for (field = 0; field < _NPCM; field++) {
4613 if (pc->pc_map[field]) {
4614 bit = bsfq(pc->pc_map[field]);
4618 if (field < _NPCM) {
4619 pv = &pc->pc_pventry[field * 64 + bit];
4620 pc->pc_map[field] &= ~(1ul << bit);
4621 /* If this was the last item, move it to tail */
4622 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 &&
4623 pc->pc_map[2] == 0) {
4624 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4625 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc,
4628 PV_STAT(atomic_add_long(&pv_entry_count, 1));
4629 PV_STAT(atomic_subtract_int(&pv_entry_spare, 1));
4633 /* No free items, allocate another chunk */
4634 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
4637 if (lockp == NULL) {
4638 PV_STAT(pc_chunk_tryfail++);
4641 m = reclaim_pv_chunk(pmap, lockp);
4645 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
4646 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
4647 dump_add_page(m->phys_addr);
4648 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
4650 pc->pc_map[0] = PC_FREE0 & ~1ul; /* preallocated bit 0 */
4651 pc->pc_map[1] = PC_FREE1;
4652 pc->pc_map[2] = PC_FREE2;
4653 pvc = &pv_chunks[_vm_phys_domain(m->phys_addr)];
4654 mtx_lock(&pvc->pvc_lock);
4655 TAILQ_INSERT_TAIL(&pvc->pvc_list, pc, pc_lru);
4656 mtx_unlock(&pvc->pvc_lock);
4657 pv = &pc->pc_pventry[0];
4658 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
4659 PV_STAT(atomic_add_long(&pv_entry_count, 1));
4660 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV - 1));
4665 * Returns the number of one bits within the given PV chunk map.
4667 * The erratas for Intel processors state that "POPCNT Instruction May
4668 * Take Longer to Execute Than Expected". It is believed that the
4669 * issue is the spurious dependency on the destination register.
4670 * Provide a hint to the register rename logic that the destination
4671 * value is overwritten, by clearing it, as suggested in the
4672 * optimization manual. It should be cheap for unaffected processors
4675 * Reference numbers for erratas are
4676 * 4th Gen Core: HSD146
4677 * 5th Gen Core: BDM85
4678 * 6th Gen Core: SKL029
4681 popcnt_pc_map_pq(uint64_t *map)
4685 __asm __volatile("xorl %k0,%k0;popcntq %2,%0;"
4686 "xorl %k1,%k1;popcntq %3,%1;addl %k1,%k0;"
4687 "xorl %k1,%k1;popcntq %4,%1;addl %k1,%k0"
4688 : "=&r" (result), "=&r" (tmp)
4689 : "m" (map[0]), "m" (map[1]), "m" (map[2]));
4694 * Ensure that the number of spare PV entries in the specified pmap meets or
4695 * exceeds the given count, "needed".
4697 * The given PV list lock may be released.
4700 reserve_pv_entries(pmap_t pmap, int needed, struct rwlock **lockp)
4702 struct pv_chunks_list *pvc;
4703 struct pch new_tail[PMAP_MEMDOM];
4704 struct pv_chunk *pc;
4709 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4710 KASSERT(lockp != NULL, ("reserve_pv_entries: lockp is NULL"));
4713 * Newly allocated PV chunks must be stored in a private list until
4714 * the required number of PV chunks have been allocated. Otherwise,
4715 * reclaim_pv_chunk() could recycle one of these chunks. In
4716 * contrast, these chunks must be added to the pmap upon allocation.
4718 for (i = 0; i < PMAP_MEMDOM; i++)
4719 TAILQ_INIT(&new_tail[i]);
4722 TAILQ_FOREACH(pc, &pmap->pm_pvchunk, pc_list) {
4724 if ((cpu_feature2 & CPUID2_POPCNT) == 0)
4725 bit_count((bitstr_t *)pc->pc_map, 0,
4726 sizeof(pc->pc_map) * NBBY, &free);
4729 free = popcnt_pc_map_pq(pc->pc_map);
4733 if (avail >= needed)
4736 for (reclaimed = false; avail < needed; avail += _NPCPV) {
4737 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
4740 m = reclaim_pv_chunk(pmap, lockp);
4745 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
4746 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
4747 dump_add_page(m->phys_addr);
4748 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
4750 pc->pc_map[0] = PC_FREE0;
4751 pc->pc_map[1] = PC_FREE1;
4752 pc->pc_map[2] = PC_FREE2;
4753 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
4754 TAILQ_INSERT_TAIL(&new_tail[pc_to_domain(pc)], pc, pc_lru);
4755 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV));
4758 * The reclaim might have freed a chunk from the current pmap.
4759 * If that chunk contained available entries, we need to
4760 * re-count the number of available entries.
4765 for (i = 0; i < vm_ndomains; i++) {
4766 if (TAILQ_EMPTY(&new_tail[i]))
4768 pvc = &pv_chunks[i];
4769 mtx_lock(&pvc->pvc_lock);
4770 TAILQ_CONCAT(&pvc->pvc_list, &new_tail[i], pc_lru);
4771 mtx_unlock(&pvc->pvc_lock);
4776 * First find and then remove the pv entry for the specified pmap and virtual
4777 * address from the specified pv list. Returns the pv entry if found and NULL
4778 * otherwise. This operation can be performed on pv lists for either 4KB or
4779 * 2MB page mappings.
4781 static __inline pv_entry_t
4782 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
4786 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4787 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
4788 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
4797 * After demotion from a 2MB page mapping to 512 4KB page mappings,
4798 * destroy the pv entry for the 2MB page mapping and reinstantiate the pv
4799 * entries for each of the 4KB page mappings.
4802 pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
4803 struct rwlock **lockp)
4805 struct md_page *pvh;
4806 struct pv_chunk *pc;
4808 vm_offset_t va_last;
4812 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4813 KASSERT((pa & PDRMASK) == 0,
4814 ("pmap_pv_demote_pde: pa is not 2mpage aligned"));
4815 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
4818 * Transfer the 2mpage's pv entry for this mapping to the first
4819 * page's pv list. Once this transfer begins, the pv list lock
4820 * must not be released until the last pv entry is reinstantiated.
4822 pvh = pa_to_pvh(pa);
4823 va = trunc_2mpage(va);
4824 pv = pmap_pvh_remove(pvh, pmap, va);
4825 KASSERT(pv != NULL, ("pmap_pv_demote_pde: pv not found"));
4826 m = PHYS_TO_VM_PAGE(pa);
4827 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4829 /* Instantiate the remaining NPTEPG - 1 pv entries. */
4830 PV_STAT(atomic_add_long(&pv_entry_allocs, NPTEPG - 1));
4831 va_last = va + NBPDR - PAGE_SIZE;
4833 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
4834 KASSERT(pc->pc_map[0] != 0 || pc->pc_map[1] != 0 ||
4835 pc->pc_map[2] != 0, ("pmap_pv_demote_pde: missing spare"));
4836 for (field = 0; field < _NPCM; field++) {
4837 while (pc->pc_map[field]) {
4838 bit = bsfq(pc->pc_map[field]);
4839 pc->pc_map[field] &= ~(1ul << bit);
4840 pv = &pc->pc_pventry[field * 64 + bit];
4844 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4845 ("pmap_pv_demote_pde: page %p is not managed", m));
4846 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4852 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4853 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
4856 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 && pc->pc_map[2] == 0) {
4857 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4858 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
4860 PV_STAT(atomic_add_long(&pv_entry_count, NPTEPG - 1));
4861 PV_STAT(atomic_subtract_int(&pv_entry_spare, NPTEPG - 1));
4864 #if VM_NRESERVLEVEL > 0
4866 * After promotion from 512 4KB page mappings to a single 2MB page mapping,
4867 * replace the many pv entries for the 4KB page mappings by a single pv entry
4868 * for the 2MB page mapping.
4871 pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
4872 struct rwlock **lockp)
4874 struct md_page *pvh;
4876 vm_offset_t va_last;
4879 KASSERT((pa & PDRMASK) == 0,
4880 ("pmap_pv_promote_pde: pa is not 2mpage aligned"));
4881 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
4884 * Transfer the first page's pv entry for this mapping to the 2mpage's
4885 * pv list. Aside from avoiding the cost of a call to get_pv_entry(),
4886 * a transfer avoids the possibility that get_pv_entry() calls
4887 * reclaim_pv_chunk() and that reclaim_pv_chunk() removes one of the
4888 * mappings that is being promoted.
4890 m = PHYS_TO_VM_PAGE(pa);
4891 va = trunc_2mpage(va);
4892 pv = pmap_pvh_remove(&m->md, pmap, va);
4893 KASSERT(pv != NULL, ("pmap_pv_promote_pde: pv not found"));
4894 pvh = pa_to_pvh(pa);
4895 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
4897 /* Free the remaining NPTEPG - 1 pv entries. */
4898 va_last = va + NBPDR - PAGE_SIZE;
4902 pmap_pvh_free(&m->md, pmap, va);
4903 } while (va < va_last);
4905 #endif /* VM_NRESERVLEVEL > 0 */
4908 * First find and then destroy the pv entry for the specified pmap and virtual
4909 * address. This operation can be performed on pv lists for either 4KB or 2MB
4913 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
4917 pv = pmap_pvh_remove(pvh, pmap, va);
4918 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
4919 free_pv_entry(pmap, pv);
4923 * Conditionally create the PV entry for a 4KB page mapping if the required
4924 * memory can be allocated without resorting to reclamation.
4927 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m,
4928 struct rwlock **lockp)
4932 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4933 /* Pass NULL instead of the lock pointer to disable reclamation. */
4934 if ((pv = get_pv_entry(pmap, NULL)) != NULL) {
4936 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
4937 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4945 * Create the PV entry for a 2MB page mapping. Always returns true unless the
4946 * flag PMAP_ENTER_NORECLAIM is specified. If that flag is specified, returns
4947 * false if the PV entry cannot be allocated without resorting to reclamation.
4950 pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, pd_entry_t pde, u_int flags,
4951 struct rwlock **lockp)
4953 struct md_page *pvh;
4957 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4958 /* Pass NULL instead of the lock pointer to disable reclamation. */
4959 if ((pv = get_pv_entry(pmap, (flags & PMAP_ENTER_NORECLAIM) != 0 ?
4960 NULL : lockp)) == NULL)
4963 pa = pde & PG_PS_FRAME;
4964 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
4965 pvh = pa_to_pvh(pa);
4966 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
4972 * Fills a page table page with mappings to consecutive physical pages.
4975 pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte)
4979 for (pte = firstpte; pte < firstpte + NPTEPG; pte++) {
4981 newpte += PAGE_SIZE;
4986 * Tries to demote a 2MB page mapping. If demotion fails, the 2MB page
4987 * mapping is invalidated.
4990 pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
4992 struct rwlock *lock;
4996 rv = pmap_demote_pde_locked(pmap, pde, va, &lock);
5003 pmap_demote_pde_check(pt_entry_t *firstpte __unused, pt_entry_t newpte __unused)
5007 pt_entry_t *xpte, *ypte;
5009 for (xpte = firstpte; xpte < firstpte + NPTEPG;
5010 xpte++, newpte += PAGE_SIZE) {
5011 if ((*xpte & PG_FRAME) != (newpte & PG_FRAME)) {
5012 printf("pmap_demote_pde: xpte %zd and newpte map "
5013 "different pages: found %#lx, expected %#lx\n",
5014 xpte - firstpte, *xpte, newpte);
5015 printf("page table dump\n");
5016 for (ypte = firstpte; ypte < firstpte + NPTEPG; ypte++)
5017 printf("%zd %#lx\n", ypte - firstpte, *ypte);
5022 KASSERT((*firstpte & PG_FRAME) == (newpte & PG_FRAME),
5023 ("pmap_demote_pde: firstpte and newpte map different physical"
5030 pmap_demote_pde_abort(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
5031 pd_entry_t oldpde, struct rwlock **lockp)
5033 struct spglist free;
5037 sva = trunc_2mpage(va);
5038 pmap_remove_pde(pmap, pde, sva, &free, lockp);
5039 if ((oldpde & pmap_global_bit(pmap)) == 0)
5040 pmap_invalidate_pde_page(pmap, sva, oldpde);
5041 vm_page_free_pages_toq(&free, true);
5042 CTR2(KTR_PMAP, "pmap_demote_pde: failure for va %#lx in pmap %p",
5047 pmap_demote_pde_locked(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
5048 struct rwlock **lockp)
5050 pd_entry_t newpde, oldpde;
5051 pt_entry_t *firstpte, newpte;
5052 pt_entry_t PG_A, PG_G, PG_M, PG_PKU_MASK, PG_RW, PG_V;
5058 PG_A = pmap_accessed_bit(pmap);
5059 PG_G = pmap_global_bit(pmap);
5060 PG_M = pmap_modified_bit(pmap);
5061 PG_RW = pmap_rw_bit(pmap);
5062 PG_V = pmap_valid_bit(pmap);
5063 PG_PTE_CACHE = pmap_cache_mask(pmap, 0);
5064 PG_PKU_MASK = pmap_pku_mask_bit(pmap);
5066 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5067 in_kernel = va >= VM_MAXUSER_ADDRESS;
5069 KASSERT((oldpde & (PG_PS | PG_V)) == (PG_PS | PG_V),
5070 ("pmap_demote_pde: oldpde is missing PG_PS and/or PG_V"));
5073 * Invalidate the 2MB page mapping and return "failure" if the
5074 * mapping was never accessed.
5076 if ((oldpde & PG_A) == 0) {
5077 KASSERT((oldpde & PG_W) == 0,
5078 ("pmap_demote_pde: a wired mapping is missing PG_A"));
5079 pmap_demote_pde_abort(pmap, va, pde, oldpde, lockp);
5083 mpte = pmap_remove_pt_page(pmap, va);
5085 KASSERT((oldpde & PG_W) == 0,
5086 ("pmap_demote_pde: page table page for a wired mapping"
5090 * If the page table page is missing and the mapping
5091 * is for a kernel address, the mapping must belong to
5092 * the direct map. Page table pages are preallocated
5093 * for every other part of the kernel address space,
5094 * so the direct map region is the only part of the
5095 * kernel address space that must be handled here.
5097 KASSERT(!in_kernel || (va >= DMAP_MIN_ADDRESS &&
5098 va < DMAP_MAX_ADDRESS),
5099 ("pmap_demote_pde: No saved mpte for va %#lx", va));
5102 * If the 2MB page mapping belongs to the direct map
5103 * region of the kernel's address space, then the page
5104 * allocation request specifies the highest possible
5105 * priority (VM_ALLOC_INTERRUPT). Otherwise, the
5106 * priority is normal.
5108 mpte = vm_page_alloc(NULL, pmap_pde_pindex(va),
5109 (in_kernel ? VM_ALLOC_INTERRUPT : VM_ALLOC_NORMAL) |
5110 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED);
5113 * If the allocation of the new page table page fails,
5114 * invalidate the 2MB page mapping and return "failure".
5117 pmap_demote_pde_abort(pmap, va, pde, oldpde, lockp);
5122 mpte->ref_count = NPTEPG;
5123 pmap_resident_count_inc(pmap, 1);
5126 mptepa = VM_PAGE_TO_PHYS(mpte);
5127 firstpte = (pt_entry_t *)PHYS_TO_DMAP(mptepa);
5128 newpde = mptepa | PG_M | PG_A | (oldpde & PG_U) | PG_RW | PG_V;
5129 KASSERT((oldpde & (PG_M | PG_RW)) != PG_RW,
5130 ("pmap_demote_pde: oldpde is missing PG_M"));
5131 newpte = oldpde & ~PG_PS;
5132 newpte = pmap_swap_pat(pmap, newpte);
5135 * If the page table page is not leftover from an earlier promotion,
5138 if (mpte->valid == 0)
5139 pmap_fill_ptp(firstpte, newpte);
5141 pmap_demote_pde_check(firstpte, newpte);
5144 * If the mapping has changed attributes, update the page table
5147 if ((*firstpte & PG_PTE_PROMOTE) != (newpte & PG_PTE_PROMOTE))
5148 pmap_fill_ptp(firstpte, newpte);
5151 * The spare PV entries must be reserved prior to demoting the
5152 * mapping, that is, prior to changing the PDE. Otherwise, the state
5153 * of the PDE and the PV lists will be inconsistent, which can result
5154 * in reclaim_pv_chunk() attempting to remove a PV entry from the
5155 * wrong PV list and pmap_pv_demote_pde() failing to find the expected
5156 * PV entry for the 2MB page mapping that is being demoted.
5158 if ((oldpde & PG_MANAGED) != 0)
5159 reserve_pv_entries(pmap, NPTEPG - 1, lockp);
5162 * Demote the mapping. This pmap is locked. The old PDE has
5163 * PG_A set. If the old PDE has PG_RW set, it also has PG_M
5164 * set. Thus, there is no danger of a race with another
5165 * processor changing the setting of PG_A and/or PG_M between
5166 * the read above and the store below.
5168 if (workaround_erratum383)
5169 pmap_update_pde(pmap, va, pde, newpde);
5171 pde_store(pde, newpde);
5174 * Invalidate a stale recursive mapping of the page table page.
5177 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
5180 * Demote the PV entry.
5182 if ((oldpde & PG_MANAGED) != 0)
5183 pmap_pv_demote_pde(pmap, va, oldpde & PG_PS_FRAME, lockp);
5185 atomic_add_long(&pmap_pde_demotions, 1);
5186 CTR2(KTR_PMAP, "pmap_demote_pde: success for va %#lx in pmap %p",
5192 * pmap_remove_kernel_pde: Remove a kernel superpage mapping.
5195 pmap_remove_kernel_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
5201 KASSERT(pmap == kernel_pmap, ("pmap %p is not kernel_pmap", pmap));
5202 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5203 mpte = pmap_remove_pt_page(pmap, va);
5205 panic("pmap_remove_kernel_pde: Missing pt page.");
5207 mptepa = VM_PAGE_TO_PHYS(mpte);
5208 newpde = mptepa | X86_PG_M | X86_PG_A | X86_PG_RW | X86_PG_V;
5211 * If this page table page was unmapped by a promotion, then it
5212 * contains valid mappings. Zero it to invalidate those mappings.
5214 if (mpte->valid != 0)
5215 pagezero((void *)PHYS_TO_DMAP(mptepa));
5218 * Demote the mapping.
5220 if (workaround_erratum383)
5221 pmap_update_pde(pmap, va, pde, newpde);
5223 pde_store(pde, newpde);
5226 * Invalidate a stale recursive mapping of the page table page.
5228 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
5232 * pmap_remove_pde: do the things to unmap a superpage in a process
5235 pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
5236 struct spglist *free, struct rwlock **lockp)
5238 struct md_page *pvh;
5240 vm_offset_t eva, va;
5242 pt_entry_t PG_G, PG_A, PG_M, PG_RW;
5244 PG_G = pmap_global_bit(pmap);
5245 PG_A = pmap_accessed_bit(pmap);
5246 PG_M = pmap_modified_bit(pmap);
5247 PG_RW = pmap_rw_bit(pmap);
5249 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5250 KASSERT((sva & PDRMASK) == 0,
5251 ("pmap_remove_pde: sva is not 2mpage aligned"));
5252 oldpde = pte_load_clear(pdq);
5254 pmap->pm_stats.wired_count -= NBPDR / PAGE_SIZE;
5255 if ((oldpde & PG_G) != 0)
5256 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
5257 pmap_resident_count_dec(pmap, NBPDR / PAGE_SIZE);
5258 if (oldpde & PG_MANAGED) {
5259 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, oldpde & PG_PS_FRAME);
5260 pvh = pa_to_pvh(oldpde & PG_PS_FRAME);
5261 pmap_pvh_free(pvh, pmap, sva);
5263 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
5264 va < eva; va += PAGE_SIZE, m++) {
5265 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
5268 vm_page_aflag_set(m, PGA_REFERENCED);
5269 if (TAILQ_EMPTY(&m->md.pv_list) &&
5270 TAILQ_EMPTY(&pvh->pv_list))
5271 vm_page_aflag_clear(m, PGA_WRITEABLE);
5272 pmap_delayed_invl_page(m);
5275 if (pmap == kernel_pmap) {
5276 pmap_remove_kernel_pde(pmap, pdq, sva);
5278 mpte = pmap_remove_pt_page(pmap, sva);
5280 KASSERT(mpte->valid == VM_PAGE_BITS_ALL,
5281 ("pmap_remove_pde: pte page not promoted"));
5282 pmap_resident_count_dec(pmap, 1);
5283 KASSERT(mpte->ref_count == NPTEPG,
5284 ("pmap_remove_pde: pte page ref count error"));
5285 mpte->ref_count = 0;
5286 pmap_add_delayed_free_list(mpte, free, FALSE);
5289 return (pmap_unuse_pt(pmap, sva, *pmap_pdpe(pmap, sva), free));
5293 * pmap_remove_pte: do the things to unmap a page in a process
5296 pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va,
5297 pd_entry_t ptepde, struct spglist *free, struct rwlock **lockp)
5299 struct md_page *pvh;
5300 pt_entry_t oldpte, PG_A, PG_M, PG_RW;
5303 PG_A = pmap_accessed_bit(pmap);
5304 PG_M = pmap_modified_bit(pmap);
5305 PG_RW = pmap_rw_bit(pmap);
5307 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5308 oldpte = pte_load_clear(ptq);
5310 pmap->pm_stats.wired_count -= 1;
5311 pmap_resident_count_dec(pmap, 1);
5312 if (oldpte & PG_MANAGED) {
5313 m = PHYS_TO_VM_PAGE(oldpte & PG_FRAME);
5314 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
5317 vm_page_aflag_set(m, PGA_REFERENCED);
5318 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
5319 pmap_pvh_free(&m->md, pmap, va);
5320 if (TAILQ_EMPTY(&m->md.pv_list) &&
5321 (m->flags & PG_FICTITIOUS) == 0) {
5322 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5323 if (TAILQ_EMPTY(&pvh->pv_list))
5324 vm_page_aflag_clear(m, PGA_WRITEABLE);
5326 pmap_delayed_invl_page(m);
5328 return (pmap_unuse_pt(pmap, va, ptepde, free));
5332 * Remove a single page from a process address space
5335 pmap_remove_page(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
5336 struct spglist *free)
5338 struct rwlock *lock;
5339 pt_entry_t *pte, PG_V;
5341 PG_V = pmap_valid_bit(pmap);
5342 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5343 if ((*pde & PG_V) == 0)
5345 pte = pmap_pde_to_pte(pde, va);
5346 if ((*pte & PG_V) == 0)
5349 pmap_remove_pte(pmap, pte, va, *pde, free, &lock);
5352 pmap_invalidate_page(pmap, va);
5356 * Removes the specified range of addresses from the page table page.
5359 pmap_remove_ptes(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
5360 pd_entry_t *pde, struct spglist *free, struct rwlock **lockp)
5362 pt_entry_t PG_G, *pte;
5366 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5367 PG_G = pmap_global_bit(pmap);
5370 for (pte = pmap_pde_to_pte(pde, sva); sva != eva; pte++,
5374 pmap_invalidate_range(pmap, va, sva);
5379 if ((*pte & PG_G) == 0)
5383 if (pmap_remove_pte(pmap, pte, sva, *pde, free, lockp)) {
5389 pmap_invalidate_range(pmap, va, sva);
5394 * Remove the given range of addresses from the specified map.
5396 * It is assumed that the start and end are properly
5397 * rounded to the page size.
5400 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
5402 struct rwlock *lock;
5403 vm_offset_t va_next;
5404 pml4_entry_t *pml4e;
5406 pd_entry_t ptpaddr, *pde;
5407 pt_entry_t PG_G, PG_V;
5408 struct spglist free;
5411 PG_G = pmap_global_bit(pmap);
5412 PG_V = pmap_valid_bit(pmap);
5415 * Perform an unsynchronized read. This is, however, safe.
5417 if (pmap->pm_stats.resident_count == 0)
5423 pmap_delayed_invl_start();
5425 pmap_pkru_on_remove(pmap, sva, eva);
5428 * special handling of removing one page. a very
5429 * common operation and easy to short circuit some
5432 if (sva + PAGE_SIZE == eva) {
5433 pde = pmap_pde(pmap, sva);
5434 if (pde && (*pde & PG_PS) == 0) {
5435 pmap_remove_page(pmap, sva, pde, &free);
5441 for (; sva < eva; sva = va_next) {
5443 if (pmap->pm_stats.resident_count == 0)
5446 pml4e = pmap_pml4e(pmap, sva);
5447 if ((*pml4e & PG_V) == 0) {
5448 va_next = (sva + NBPML4) & ~PML4MASK;
5454 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
5455 if ((*pdpe & PG_V) == 0) {
5456 va_next = (sva + NBPDP) & ~PDPMASK;
5463 * Calculate index for next page table.
5465 va_next = (sva + NBPDR) & ~PDRMASK;
5469 pde = pmap_pdpe_to_pde(pdpe, sva);
5473 * Weed out invalid mappings.
5479 * Check for large page.
5481 if ((ptpaddr & PG_PS) != 0) {
5483 * Are we removing the entire large page? If not,
5484 * demote the mapping and fall through.
5486 if (sva + NBPDR == va_next && eva >= va_next) {
5488 * The TLB entry for a PG_G mapping is
5489 * invalidated by pmap_remove_pde().
5491 if ((ptpaddr & PG_G) == 0)
5493 pmap_remove_pde(pmap, pde, sva, &free, &lock);
5495 } else if (!pmap_demote_pde_locked(pmap, pde, sva,
5497 /* The large page mapping was destroyed. */
5504 * Limit our scan to either the end of the va represented
5505 * by the current page table page, or to the end of the
5506 * range being removed.
5511 if (pmap_remove_ptes(pmap, sva, va_next, pde, &free, &lock))
5518 pmap_invalidate_all(pmap);
5520 pmap_delayed_invl_finish();
5521 vm_page_free_pages_toq(&free, true);
5525 * Routine: pmap_remove_all
5527 * Removes this physical page from
5528 * all physical maps in which it resides.
5529 * Reflects back modify bits to the pager.
5532 * Original versions of this routine were very
5533 * inefficient because they iteratively called
5534 * pmap_remove (slow...)
5538 pmap_remove_all(vm_page_t m)
5540 struct md_page *pvh;
5543 struct rwlock *lock;
5544 pt_entry_t *pte, tpte, PG_A, PG_M, PG_RW;
5547 struct spglist free;
5548 int pvh_gen, md_gen;
5550 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5551 ("pmap_remove_all: page %p is not managed", m));
5553 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5554 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
5555 pa_to_pvh(VM_PAGE_TO_PHYS(m));
5558 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
5560 if (!PMAP_TRYLOCK(pmap)) {
5561 pvh_gen = pvh->pv_gen;
5565 if (pvh_gen != pvh->pv_gen) {
5572 pde = pmap_pde(pmap, va);
5573 (void)pmap_demote_pde_locked(pmap, pde, va, &lock);
5576 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
5578 if (!PMAP_TRYLOCK(pmap)) {
5579 pvh_gen = pvh->pv_gen;
5580 md_gen = m->md.pv_gen;
5584 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
5590 PG_A = pmap_accessed_bit(pmap);
5591 PG_M = pmap_modified_bit(pmap);
5592 PG_RW = pmap_rw_bit(pmap);
5593 pmap_resident_count_dec(pmap, 1);
5594 pde = pmap_pde(pmap, pv->pv_va);
5595 KASSERT((*pde & PG_PS) == 0, ("pmap_remove_all: found"
5596 " a 2mpage in page %p's pv list", m));
5597 pte = pmap_pde_to_pte(pde, pv->pv_va);
5598 tpte = pte_load_clear(pte);
5600 pmap->pm_stats.wired_count--;
5602 vm_page_aflag_set(m, PGA_REFERENCED);
5605 * Update the vm_page_t clean and reference bits.
5607 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
5609 pmap_unuse_pt(pmap, pv->pv_va, *pde, &free);
5610 pmap_invalidate_page(pmap, pv->pv_va);
5611 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
5613 free_pv_entry(pmap, pv);
5616 vm_page_aflag_clear(m, PGA_WRITEABLE);
5618 pmap_delayed_invl_wait(m);
5619 vm_page_free_pages_toq(&free, true);
5623 * pmap_protect_pde: do the things to protect a 2mpage in a process
5626 pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, vm_prot_t prot)
5628 pd_entry_t newpde, oldpde;
5630 boolean_t anychanged;
5631 pt_entry_t PG_G, PG_M, PG_RW;
5633 PG_G = pmap_global_bit(pmap);
5634 PG_M = pmap_modified_bit(pmap);
5635 PG_RW = pmap_rw_bit(pmap);
5637 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5638 KASSERT((sva & PDRMASK) == 0,
5639 ("pmap_protect_pde: sva is not 2mpage aligned"));
5642 oldpde = newpde = *pde;
5643 if ((prot & VM_PROT_WRITE) == 0) {
5644 if ((oldpde & (PG_MANAGED | PG_M | PG_RW)) ==
5645 (PG_MANAGED | PG_M | PG_RW)) {
5646 m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
5647 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
5650 newpde &= ~(PG_RW | PG_M);
5652 if ((prot & VM_PROT_EXECUTE) == 0)
5654 if (newpde != oldpde) {
5656 * As an optimization to future operations on this PDE, clear
5657 * PG_PROMOTED. The impending invalidation will remove any
5658 * lingering 4KB page mappings from the TLB.
5660 if (!atomic_cmpset_long(pde, oldpde, newpde & ~PG_PROMOTED))
5662 if ((oldpde & PG_G) != 0)
5663 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
5667 return (anychanged);
5671 * Set the physical protection on the
5672 * specified range of this map as requested.
5675 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
5677 vm_offset_t va_next;
5678 pml4_entry_t *pml4e;
5680 pd_entry_t ptpaddr, *pde;
5681 pt_entry_t *pte, PG_G, PG_M, PG_RW, PG_V;
5682 boolean_t anychanged;
5684 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
5685 if (prot == VM_PROT_NONE) {
5686 pmap_remove(pmap, sva, eva);
5690 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) ==
5691 (VM_PROT_WRITE|VM_PROT_EXECUTE))
5694 PG_G = pmap_global_bit(pmap);
5695 PG_M = pmap_modified_bit(pmap);
5696 PG_V = pmap_valid_bit(pmap);
5697 PG_RW = pmap_rw_bit(pmap);
5701 * Although this function delays and batches the invalidation
5702 * of stale TLB entries, it does not need to call
5703 * pmap_delayed_invl_start() and
5704 * pmap_delayed_invl_finish(), because it does not
5705 * ordinarily destroy mappings. Stale TLB entries from
5706 * protection-only changes need only be invalidated before the
5707 * pmap lock is released, because protection-only changes do
5708 * not destroy PV entries. Even operations that iterate over
5709 * a physical page's PV list of mappings, like
5710 * pmap_remove_write(), acquire the pmap lock for each
5711 * mapping. Consequently, for protection-only changes, the
5712 * pmap lock suffices to synchronize both page table and TLB
5715 * This function only destroys a mapping if pmap_demote_pde()
5716 * fails. In that case, stale TLB entries are immediately
5721 for (; sva < eva; sva = va_next) {
5723 pml4e = pmap_pml4e(pmap, sva);
5724 if ((*pml4e & PG_V) == 0) {
5725 va_next = (sva + NBPML4) & ~PML4MASK;
5731 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
5732 if ((*pdpe & PG_V) == 0) {
5733 va_next = (sva + NBPDP) & ~PDPMASK;
5739 va_next = (sva + NBPDR) & ~PDRMASK;
5743 pde = pmap_pdpe_to_pde(pdpe, sva);
5747 * Weed out invalid mappings.
5753 * Check for large page.
5755 if ((ptpaddr & PG_PS) != 0) {
5757 * Are we protecting the entire large page? If not,
5758 * demote the mapping and fall through.
5760 if (sva + NBPDR == va_next && eva >= va_next) {
5762 * The TLB entry for a PG_G mapping is
5763 * invalidated by pmap_protect_pde().
5765 if (pmap_protect_pde(pmap, pde, sva, prot))
5768 } else if (!pmap_demote_pde(pmap, pde, sva)) {
5770 * The large page mapping was destroyed.
5779 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
5781 pt_entry_t obits, pbits;
5785 obits = pbits = *pte;
5786 if ((pbits & PG_V) == 0)
5789 if ((prot & VM_PROT_WRITE) == 0) {
5790 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) ==
5791 (PG_MANAGED | PG_M | PG_RW)) {
5792 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME);
5795 pbits &= ~(PG_RW | PG_M);
5797 if ((prot & VM_PROT_EXECUTE) == 0)
5800 if (pbits != obits) {
5801 if (!atomic_cmpset_long(pte, obits, pbits))
5804 pmap_invalidate_page(pmap, sva);
5811 pmap_invalidate_all(pmap);
5815 #if VM_NRESERVLEVEL > 0
5817 pmap_pde_ept_executable(pmap_t pmap, pd_entry_t pde)
5820 if (pmap->pm_type != PT_EPT)
5822 return ((pde & EPT_PG_EXECUTE) != 0);
5826 * Tries to promote the 512, contiguous 4KB page mappings that are within a
5827 * single page table page (PTP) to a single 2MB page mapping. For promotion
5828 * to occur, two conditions must be met: (1) the 4KB page mappings must map
5829 * aligned, contiguous physical memory and (2) the 4KB page mappings must have
5830 * identical characteristics.
5833 pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
5834 struct rwlock **lockp)
5837 pt_entry_t *firstpte, oldpte, pa, *pte;
5838 pt_entry_t PG_G, PG_A, PG_M, PG_RW, PG_V, PG_PKU_MASK;
5842 PG_A = pmap_accessed_bit(pmap);
5843 PG_G = pmap_global_bit(pmap);
5844 PG_M = pmap_modified_bit(pmap);
5845 PG_V = pmap_valid_bit(pmap);
5846 PG_RW = pmap_rw_bit(pmap);
5847 PG_PKU_MASK = pmap_pku_mask_bit(pmap);
5848 PG_PTE_CACHE = pmap_cache_mask(pmap, 0);
5850 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5853 * Examine the first PTE in the specified PTP. Abort if this PTE is
5854 * either invalid, unused, or does not map the first 4KB physical page
5855 * within a 2MB page.
5857 firstpte = (pt_entry_t *)PHYS_TO_DMAP(*pde & PG_FRAME);
5860 if ((newpde & ((PG_FRAME & PDRMASK) | PG_A | PG_V)) != (PG_A | PG_V) ||
5861 !pmap_allow_2m_x_page(pmap, pmap_pde_ept_executable(pmap,
5863 atomic_add_long(&pmap_pde_p_failures, 1);
5864 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
5865 " in pmap %p", va, pmap);
5868 if ((newpde & (PG_M | PG_RW)) == PG_RW) {
5870 * When PG_M is already clear, PG_RW can be cleared without
5871 * a TLB invalidation.
5873 if (!atomic_cmpset_long(firstpte, newpde, newpde & ~PG_RW))
5879 * Examine each of the other PTEs in the specified PTP. Abort if this
5880 * PTE maps an unexpected 4KB physical page or does not have identical
5881 * characteristics to the first PTE.
5883 pa = (newpde & (PG_PS_FRAME | PG_A | PG_V)) + NBPDR - PAGE_SIZE;
5884 for (pte = firstpte + NPTEPG - 1; pte > firstpte; pte--) {
5887 if ((oldpte & (PG_FRAME | PG_A | PG_V)) != pa) {
5888 atomic_add_long(&pmap_pde_p_failures, 1);
5889 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
5890 " in pmap %p", va, pmap);
5893 if ((oldpte & (PG_M | PG_RW)) == PG_RW) {
5895 * When PG_M is already clear, PG_RW can be cleared
5896 * without a TLB invalidation.
5898 if (!atomic_cmpset_long(pte, oldpte, oldpte & ~PG_RW))
5901 CTR2(KTR_PMAP, "pmap_promote_pde: protect for va %#lx"
5902 " in pmap %p", (oldpte & PG_FRAME & PDRMASK) |
5903 (va & ~PDRMASK), pmap);
5905 if ((oldpte & PG_PTE_PROMOTE) != (newpde & PG_PTE_PROMOTE)) {
5906 atomic_add_long(&pmap_pde_p_failures, 1);
5907 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
5908 " in pmap %p", va, pmap);
5915 * Save the page table page in its current state until the PDE
5916 * mapping the superpage is demoted by pmap_demote_pde() or
5917 * destroyed by pmap_remove_pde().
5919 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
5920 KASSERT(mpte >= vm_page_array &&
5921 mpte < &vm_page_array[vm_page_array_size],
5922 ("pmap_promote_pde: page table page is out of range"));
5923 KASSERT(mpte->pindex == pmap_pde_pindex(va),
5924 ("pmap_promote_pde: page table page's pindex is wrong"));
5925 if (pmap_insert_pt_page(pmap, mpte, true)) {
5926 atomic_add_long(&pmap_pde_p_failures, 1);
5928 "pmap_promote_pde: failure for va %#lx in pmap %p", va,
5934 * Promote the pv entries.
5936 if ((newpde & PG_MANAGED) != 0)
5937 pmap_pv_promote_pde(pmap, va, newpde & PG_PS_FRAME, lockp);
5940 * Propagate the PAT index to its proper position.
5942 newpde = pmap_swap_pat(pmap, newpde);
5945 * Map the superpage.
5947 if (workaround_erratum383)
5948 pmap_update_pde(pmap, va, pde, PG_PS | newpde);
5950 pde_store(pde, PG_PROMOTED | PG_PS | newpde);
5952 atomic_add_long(&pmap_pde_promotions, 1);
5953 CTR2(KTR_PMAP, "pmap_promote_pde: success for va %#lx"
5954 " in pmap %p", va, pmap);
5956 #endif /* VM_NRESERVLEVEL > 0 */
5959 * Insert the given physical page (p) at
5960 * the specified virtual address (v) in the
5961 * target physical map with the protection requested.
5963 * If specified, the page will be wired down, meaning
5964 * that the related pte can not be reclaimed.
5966 * NB: This is the only routine which MAY NOT lazy-evaluate
5967 * or lose information. That is, this routine must actually
5968 * insert this page into the given map NOW.
5970 * When destroying both a page table and PV entry, this function
5971 * performs the TLB invalidation before releasing the PV list
5972 * lock, so we do not need pmap_delayed_invl_page() calls here.
5975 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
5976 u_int flags, int8_t psind)
5978 struct rwlock *lock;
5980 pt_entry_t *pte, PG_G, PG_A, PG_M, PG_RW, PG_V;
5981 pt_entry_t newpte, origpte;
5988 PG_A = pmap_accessed_bit(pmap);
5989 PG_G = pmap_global_bit(pmap);
5990 PG_M = pmap_modified_bit(pmap);
5991 PG_V = pmap_valid_bit(pmap);
5992 PG_RW = pmap_rw_bit(pmap);
5994 va = trunc_page(va);
5995 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig"));
5996 KASSERT(va < UPT_MIN_ADDRESS || va >= UPT_MAX_ADDRESS,
5997 ("pmap_enter: invalid to pmap_enter page table pages (va: 0x%lx)",
5999 KASSERT((m->oflags & VPO_UNMANAGED) != 0 || va < kmi.clean_sva ||
6000 va >= kmi.clean_eva,
6001 ("pmap_enter: managed mapping within the clean submap"));
6002 if ((m->oflags & VPO_UNMANAGED) == 0)
6003 VM_PAGE_OBJECT_BUSY_ASSERT(m);
6004 KASSERT((flags & PMAP_ENTER_RESERVED) == 0,
6005 ("pmap_enter: flags %u has reserved bits set", flags));
6006 pa = VM_PAGE_TO_PHYS(m);
6007 newpte = (pt_entry_t)(pa | PG_A | PG_V);
6008 if ((flags & VM_PROT_WRITE) != 0)
6010 if ((prot & VM_PROT_WRITE) != 0)
6012 KASSERT((newpte & (PG_M | PG_RW)) != PG_M,
6013 ("pmap_enter: flags includes VM_PROT_WRITE but prot doesn't"));
6014 if ((prot & VM_PROT_EXECUTE) == 0)
6016 if ((flags & PMAP_ENTER_WIRED) != 0)
6018 if (va < VM_MAXUSER_ADDRESS)
6020 if (pmap == kernel_pmap)
6022 newpte |= pmap_cache_bits(pmap, m->md.pat_mode, psind > 0);
6025 * Set modified bit gratuitously for writeable mappings if
6026 * the page is unmanaged. We do not want to take a fault
6027 * to do the dirty bit accounting for these mappings.
6029 if ((m->oflags & VPO_UNMANAGED) != 0) {
6030 if ((newpte & PG_RW) != 0)
6033 newpte |= PG_MANAGED;
6038 /* Assert the required virtual and physical alignment. */
6039 KASSERT((va & PDRMASK) == 0, ("pmap_enter: va unaligned"));
6040 KASSERT(m->psind > 0, ("pmap_enter: m->psind < psind"));
6041 rv = pmap_enter_pde(pmap, va, newpte | PG_PS, flags, m, &lock);
6047 * In the case that a page table page is not
6048 * resident, we are creating it here.
6051 pde = pmap_pde(pmap, va);
6052 if (pde != NULL && (*pde & PG_V) != 0 && ((*pde & PG_PS) == 0 ||
6053 pmap_demote_pde_locked(pmap, pde, va, &lock))) {
6054 pte = pmap_pde_to_pte(pde, va);
6055 if (va < VM_MAXUSER_ADDRESS && mpte == NULL) {
6056 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
6059 } else if (va < VM_MAXUSER_ADDRESS) {
6061 * Here if the pte page isn't mapped, or if it has been
6064 nosleep = (flags & PMAP_ENTER_NOSLEEP) != 0;
6065 mpte = _pmap_allocpte(pmap, pmap_pde_pindex(va),
6066 nosleep ? NULL : &lock);
6067 if (mpte == NULL && nosleep) {
6068 rv = KERN_RESOURCE_SHORTAGE;
6073 panic("pmap_enter: invalid page directory va=%#lx", va);
6077 if (va < VM_MAXUSER_ADDRESS && pmap->pm_type == PT_X86)
6078 newpte |= pmap_pkru_get(pmap, va);
6081 * Is the specified virtual address already mapped?
6083 if ((origpte & PG_V) != 0) {
6085 * Wiring change, just update stats. We don't worry about
6086 * wiring PT pages as they remain resident as long as there
6087 * are valid mappings in them. Hence, if a user page is wired,
6088 * the PT page will be also.
6090 if ((newpte & PG_W) != 0 && (origpte & PG_W) == 0)
6091 pmap->pm_stats.wired_count++;
6092 else if ((newpte & PG_W) == 0 && (origpte & PG_W) != 0)
6093 pmap->pm_stats.wired_count--;
6096 * Remove the extra PT page reference.
6100 KASSERT(mpte->ref_count > 0,
6101 ("pmap_enter: missing reference to page table page,"
6106 * Has the physical page changed?
6108 opa = origpte & PG_FRAME;
6111 * No, might be a protection or wiring change.
6113 if ((origpte & PG_MANAGED) != 0 &&
6114 (newpte & PG_RW) != 0)
6115 vm_page_aflag_set(m, PGA_WRITEABLE);
6116 if (((origpte ^ newpte) & ~(PG_M | PG_A)) == 0)
6122 * The physical page has changed. Temporarily invalidate
6123 * the mapping. This ensures that all threads sharing the
6124 * pmap keep a consistent view of the mapping, which is
6125 * necessary for the correct handling of COW faults. It
6126 * also permits reuse of the old mapping's PV entry,
6127 * avoiding an allocation.
6129 * For consistency, handle unmanaged mappings the same way.
6131 origpte = pte_load_clear(pte);
6132 KASSERT((origpte & PG_FRAME) == opa,
6133 ("pmap_enter: unexpected pa update for %#lx", va));
6134 if ((origpte & PG_MANAGED) != 0) {
6135 om = PHYS_TO_VM_PAGE(opa);
6138 * The pmap lock is sufficient to synchronize with
6139 * concurrent calls to pmap_page_test_mappings() and
6140 * pmap_ts_referenced().
6142 if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
6144 if ((origpte & PG_A) != 0) {
6145 pmap_invalidate_page(pmap, va);
6146 vm_page_aflag_set(om, PGA_REFERENCED);
6148 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, opa);
6149 pv = pmap_pvh_remove(&om->md, pmap, va);
6151 ("pmap_enter: no PV entry for %#lx", va));
6152 if ((newpte & PG_MANAGED) == 0)
6153 free_pv_entry(pmap, pv);
6154 if ((om->a.flags & PGA_WRITEABLE) != 0 &&
6155 TAILQ_EMPTY(&om->md.pv_list) &&
6156 ((om->flags & PG_FICTITIOUS) != 0 ||
6157 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
6158 vm_page_aflag_clear(om, PGA_WRITEABLE);
6161 * Since this mapping is unmanaged, assume that PG_A
6164 pmap_invalidate_page(pmap, va);
6169 * Increment the counters.
6171 if ((newpte & PG_W) != 0)
6172 pmap->pm_stats.wired_count++;
6173 pmap_resident_count_inc(pmap, 1);
6177 * Enter on the PV list if part of our managed memory.
6179 if ((newpte & PG_MANAGED) != 0) {
6181 pv = get_pv_entry(pmap, &lock);
6184 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, pa);
6185 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
6187 if ((newpte & PG_RW) != 0)
6188 vm_page_aflag_set(m, PGA_WRITEABLE);
6194 if ((origpte & PG_V) != 0) {
6196 origpte = pte_load_store(pte, newpte);
6197 KASSERT((origpte & PG_FRAME) == pa,
6198 ("pmap_enter: unexpected pa update for %#lx", va));
6199 if ((newpte & PG_M) == 0 && (origpte & (PG_M | PG_RW)) ==
6201 if ((origpte & PG_MANAGED) != 0)
6205 * Although the PTE may still have PG_RW set, TLB
6206 * invalidation may nonetheless be required because
6207 * the PTE no longer has PG_M set.
6209 } else if ((origpte & PG_NX) != 0 || (newpte & PG_NX) == 0) {
6211 * This PTE change does not require TLB invalidation.
6215 if ((origpte & PG_A) != 0)
6216 pmap_invalidate_page(pmap, va);
6218 pte_store(pte, newpte);
6222 #if VM_NRESERVLEVEL > 0
6224 * If both the page table page and the reservation are fully
6225 * populated, then attempt promotion.
6227 if ((mpte == NULL || mpte->ref_count == NPTEPG) &&
6228 pmap_ps_enabled(pmap) &&
6229 (m->flags & PG_FICTITIOUS) == 0 &&
6230 vm_reserv_level_iffullpop(m) == 0)
6231 pmap_promote_pde(pmap, pde, va, &lock);
6243 * Tries to create a read- and/or execute-only 2MB page mapping. Returns true
6244 * if successful. Returns false if (1) a page table page cannot be allocated
6245 * without sleeping, (2) a mapping already exists at the specified virtual
6246 * address, or (3) a PV entry cannot be allocated without reclaiming another
6250 pmap_enter_2mpage(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
6251 struct rwlock **lockp)
6256 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6257 PG_V = pmap_valid_bit(pmap);
6258 newpde = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(pmap, m->md.pat_mode, 1) |
6260 if ((m->oflags & VPO_UNMANAGED) == 0)
6261 newpde |= PG_MANAGED;
6262 if ((prot & VM_PROT_EXECUTE) == 0)
6264 if (va < VM_MAXUSER_ADDRESS)
6266 return (pmap_enter_pde(pmap, va, newpde, PMAP_ENTER_NOSLEEP |
6267 PMAP_ENTER_NOREPLACE | PMAP_ENTER_NORECLAIM, NULL, lockp) ==
6272 * Returns true if every page table entry in the specified page table page is
6276 pmap_every_pte_zero(vm_paddr_t pa)
6278 pt_entry_t *pt_end, *pte;
6280 KASSERT((pa & PAGE_MASK) == 0, ("pa is misaligned"));
6281 pte = (pt_entry_t *)PHYS_TO_DMAP(pa);
6282 for (pt_end = pte + NPTEPG; pte < pt_end; pte++) {
6290 * Tries to create the specified 2MB page mapping. Returns KERN_SUCCESS if
6291 * the mapping was created, and either KERN_FAILURE or KERN_RESOURCE_SHORTAGE
6292 * otherwise. Returns KERN_FAILURE if PMAP_ENTER_NOREPLACE was specified and
6293 * a mapping already exists at the specified virtual address. Returns
6294 * KERN_RESOURCE_SHORTAGE if PMAP_ENTER_NOSLEEP was specified and a page table
6295 * page allocation failed. Returns KERN_RESOURCE_SHORTAGE if
6296 * PMAP_ENTER_NORECLAIM was specified and a PV entry allocation failed.
6298 * The parameter "m" is only used when creating a managed, writeable mapping.
6301 pmap_enter_pde(pmap_t pmap, vm_offset_t va, pd_entry_t newpde, u_int flags,
6302 vm_page_t m, struct rwlock **lockp)
6304 struct spglist free;
6305 pd_entry_t oldpde, *pde;
6306 pt_entry_t PG_G, PG_RW, PG_V;
6309 KASSERT(pmap == kernel_pmap || (newpde & PG_W) == 0,
6310 ("pmap_enter_pde: cannot create wired user mapping"));
6311 PG_G = pmap_global_bit(pmap);
6312 PG_RW = pmap_rw_bit(pmap);
6313 KASSERT((newpde & (pmap_modified_bit(pmap) | PG_RW)) != PG_RW,
6314 ("pmap_enter_pde: newpde is missing PG_M"));
6315 PG_V = pmap_valid_bit(pmap);
6316 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6318 if (!pmap_allow_2m_x_page(pmap, pmap_pde_ept_executable(pmap,
6320 CTR2(KTR_PMAP, "pmap_enter_pde: 2m x blocked for va %#lx"
6321 " in pmap %p", va, pmap);
6322 return (KERN_FAILURE);
6324 if ((pde = pmap_alloc_pde(pmap, va, &pdpg, (flags &
6325 PMAP_ENTER_NOSLEEP) != 0 ? NULL : lockp)) == NULL) {
6326 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
6327 " in pmap %p", va, pmap);
6328 return (KERN_RESOURCE_SHORTAGE);
6332 * If pkru is not same for the whole pde range, return failure
6333 * and let vm_fault() cope. Check after pde allocation, since
6336 if (!pmap_pkru_same(pmap, va, va + NBPDR)) {
6337 pmap_abort_ptp(pmap, va, pdpg);
6338 return (KERN_FAILURE);
6340 if (va < VM_MAXUSER_ADDRESS && pmap->pm_type == PT_X86) {
6341 newpde &= ~X86_PG_PKU_MASK;
6342 newpde |= pmap_pkru_get(pmap, va);
6346 * If there are existing mappings, either abort or remove them.
6349 if ((oldpde & PG_V) != 0) {
6350 KASSERT(pdpg == NULL || pdpg->ref_count > 1,
6351 ("pmap_enter_pde: pdpg's reference count is too low"));
6352 if ((flags & PMAP_ENTER_NOREPLACE) != 0 && (va <
6353 VM_MAXUSER_ADDRESS || (oldpde & PG_PS) != 0 ||
6354 !pmap_every_pte_zero(oldpde & PG_FRAME))) {
6357 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
6358 " in pmap %p", va, pmap);
6359 return (KERN_FAILURE);
6361 /* Break the existing mapping(s). */
6363 if ((oldpde & PG_PS) != 0) {
6365 * The reference to the PD page that was acquired by
6366 * pmap_alloc_pde() ensures that it won't be freed.
6367 * However, if the PDE resulted from a promotion, then
6368 * a reserved PT page could be freed.
6370 (void)pmap_remove_pde(pmap, pde, va, &free, lockp);
6371 if ((oldpde & PG_G) == 0)
6372 pmap_invalidate_pde_page(pmap, va, oldpde);
6374 pmap_delayed_invl_start();
6375 if (pmap_remove_ptes(pmap, va, va + NBPDR, pde, &free,
6377 pmap_invalidate_all(pmap);
6378 pmap_delayed_invl_finish();
6380 if (va < VM_MAXUSER_ADDRESS) {
6381 vm_page_free_pages_toq(&free, true);
6382 KASSERT(*pde == 0, ("pmap_enter_pde: non-zero pde %p",
6385 KASSERT(SLIST_EMPTY(&free),
6386 ("pmap_enter_pde: freed kernel page table page"));
6389 * Both pmap_remove_pde() and pmap_remove_ptes() will
6390 * leave the kernel page table page zero filled.
6392 mt = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
6393 if (pmap_insert_pt_page(pmap, mt, false))
6394 panic("pmap_enter_pde: trie insert failed");
6398 if ((newpde & PG_MANAGED) != 0) {
6400 * Abort this mapping if its PV entry could not be created.
6402 if (!pmap_pv_insert_pde(pmap, va, newpde, flags, lockp)) {
6404 pmap_abort_ptp(pmap, va, pdpg);
6405 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
6406 " in pmap %p", va, pmap);
6407 return (KERN_RESOURCE_SHORTAGE);
6409 if ((newpde & PG_RW) != 0) {
6410 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
6411 vm_page_aflag_set(mt, PGA_WRITEABLE);
6416 * Increment counters.
6418 if ((newpde & PG_W) != 0)
6419 pmap->pm_stats.wired_count += NBPDR / PAGE_SIZE;
6420 pmap_resident_count_inc(pmap, NBPDR / PAGE_SIZE);
6423 * Map the superpage. (This is not a promoted mapping; there will not
6424 * be any lingering 4KB page mappings in the TLB.)
6426 pde_store(pde, newpde);
6428 atomic_add_long(&pmap_pde_mappings, 1);
6429 CTR2(KTR_PMAP, "pmap_enter_pde: success for va %#lx in pmap %p",
6431 return (KERN_SUCCESS);
6435 * Maps a sequence of resident pages belonging to the same object.
6436 * The sequence begins with the given page m_start. This page is
6437 * mapped at the given virtual address start. Each subsequent page is
6438 * mapped at a virtual address that is offset from start by the same
6439 * amount as the page is offset from m_start within the object. The
6440 * last page in the sequence is the page with the largest offset from
6441 * m_start that can be mapped at a virtual address less than the given
6442 * virtual address end. Not every virtual page between start and end
6443 * is mapped; only those for which a resident page exists with the
6444 * corresponding offset from m_start are mapped.
6447 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
6448 vm_page_t m_start, vm_prot_t prot)
6450 struct rwlock *lock;
6453 vm_pindex_t diff, psize;
6455 VM_OBJECT_ASSERT_LOCKED(m_start->object);
6457 psize = atop(end - start);
6462 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
6463 va = start + ptoa(diff);
6464 if ((va & PDRMASK) == 0 && va + NBPDR <= end &&
6465 m->psind == 1 && pmap_ps_enabled(pmap) &&
6466 pmap_allow_2m_x_page(pmap, (prot & VM_PROT_EXECUTE) != 0) &&
6467 pmap_enter_2mpage(pmap, va, m, prot, &lock))
6468 m = &m[NBPDR / PAGE_SIZE - 1];
6470 mpte = pmap_enter_quick_locked(pmap, va, m, prot,
6472 m = TAILQ_NEXT(m, listq);
6480 * this code makes some *MAJOR* assumptions:
6481 * 1. Current pmap & pmap exists.
6484 * 4. No page table pages.
6485 * but is *MUCH* faster than pmap_enter...
6489 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
6491 struct rwlock *lock;
6495 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL, &lock);
6502 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
6503 vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp)
6505 pt_entry_t newpte, *pte, PG_V;
6507 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
6508 (m->oflags & VPO_UNMANAGED) != 0,
6509 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
6510 PG_V = pmap_valid_bit(pmap);
6511 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6514 * In the case that a page table page is not
6515 * resident, we are creating it here.
6517 if (va < VM_MAXUSER_ADDRESS) {
6518 vm_pindex_t ptepindex;
6522 * Calculate pagetable page index
6524 ptepindex = pmap_pde_pindex(va);
6525 if (mpte && (mpte->pindex == ptepindex)) {
6529 * Get the page directory entry
6531 ptepa = pmap_pde(pmap, va);
6534 * If the page table page is mapped, we just increment
6535 * the hold count, and activate it. Otherwise, we
6536 * attempt to allocate a page table page. If this
6537 * attempt fails, we don't retry. Instead, we give up.
6539 if (ptepa && (*ptepa & PG_V) != 0) {
6542 mpte = PHYS_TO_VM_PAGE(*ptepa & PG_FRAME);
6546 * Pass NULL instead of the PV list lock
6547 * pointer, because we don't intend to sleep.
6549 mpte = _pmap_allocpte(pmap, ptepindex, NULL);
6554 pte = (pt_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpte));
6555 pte = &pte[pmap_pte_index(va)];
6567 * Enter on the PV list if part of our managed memory.
6569 if ((m->oflags & VPO_UNMANAGED) == 0 &&
6570 !pmap_try_insert_pv_entry(pmap, va, m, lockp)) {
6572 pmap_abort_ptp(pmap, va, mpte);
6577 * Increment counters
6579 pmap_resident_count_inc(pmap, 1);
6581 newpte = VM_PAGE_TO_PHYS(m) | PG_V |
6582 pmap_cache_bits(pmap, m->md.pat_mode, 0);
6583 if ((m->oflags & VPO_UNMANAGED) == 0)
6584 newpte |= PG_MANAGED;
6585 if ((prot & VM_PROT_EXECUTE) == 0)
6587 if (va < VM_MAXUSER_ADDRESS)
6588 newpte |= PG_U | pmap_pkru_get(pmap, va);
6589 pte_store(pte, newpte);
6594 * Make a temporary mapping for a physical address. This is only intended
6595 * to be used for panic dumps.
6598 pmap_kenter_temporary(vm_paddr_t pa, int i)
6602 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
6603 pmap_kenter(va, pa);
6605 return ((void *)crashdumpmap);
6609 * This code maps large physical mmap regions into the
6610 * processor address space. Note that some shortcuts
6611 * are taken, but the code works.
6614 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
6615 vm_pindex_t pindex, vm_size_t size)
6618 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
6619 vm_paddr_t pa, ptepa;
6623 PG_A = pmap_accessed_bit(pmap);
6624 PG_M = pmap_modified_bit(pmap);
6625 PG_V = pmap_valid_bit(pmap);
6626 PG_RW = pmap_rw_bit(pmap);
6628 VM_OBJECT_ASSERT_WLOCKED(object);
6629 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
6630 ("pmap_object_init_pt: non-device object"));
6631 if ((addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) {
6632 if (!pmap_ps_enabled(pmap))
6634 if (!vm_object_populate(object, pindex, pindex + atop(size)))
6636 p = vm_page_lookup(object, pindex);
6637 KASSERT(p->valid == VM_PAGE_BITS_ALL,
6638 ("pmap_object_init_pt: invalid page %p", p));
6639 pat_mode = p->md.pat_mode;
6642 * Abort the mapping if the first page is not physically
6643 * aligned to a 2MB page boundary.
6645 ptepa = VM_PAGE_TO_PHYS(p);
6646 if (ptepa & (NBPDR - 1))
6650 * Skip the first page. Abort the mapping if the rest of
6651 * the pages are not physically contiguous or have differing
6652 * memory attributes.
6654 p = TAILQ_NEXT(p, listq);
6655 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size;
6657 KASSERT(p->valid == VM_PAGE_BITS_ALL,
6658 ("pmap_object_init_pt: invalid page %p", p));
6659 if (pa != VM_PAGE_TO_PHYS(p) ||
6660 pat_mode != p->md.pat_mode)
6662 p = TAILQ_NEXT(p, listq);
6666 * Map using 2MB pages. Since "ptepa" is 2M aligned and
6667 * "size" is a multiple of 2M, adding the PAT setting to "pa"
6668 * will not affect the termination of this loop.
6671 for (pa = ptepa | pmap_cache_bits(pmap, pat_mode, 1);
6672 pa < ptepa + size; pa += NBPDR) {
6673 pde = pmap_alloc_pde(pmap, addr, &pdpg, NULL);
6676 * The creation of mappings below is only an
6677 * optimization. If a page directory page
6678 * cannot be allocated without blocking,
6679 * continue on to the next mapping rather than
6685 if ((*pde & PG_V) == 0) {
6686 pde_store(pde, pa | PG_PS | PG_M | PG_A |
6687 PG_U | PG_RW | PG_V);
6688 pmap_resident_count_inc(pmap, NBPDR / PAGE_SIZE);
6689 atomic_add_long(&pmap_pde_mappings, 1);
6691 /* Continue on if the PDE is already valid. */
6693 KASSERT(pdpg->ref_count > 0,
6694 ("pmap_object_init_pt: missing reference "
6695 "to page directory page, va: 0x%lx", addr));
6704 * Clear the wired attribute from the mappings for the specified range of
6705 * addresses in the given pmap. Every valid mapping within that range
6706 * must have the wired attribute set. In contrast, invalid mappings
6707 * cannot have the wired attribute set, so they are ignored.
6709 * The wired attribute of the page table entry is not a hardware
6710 * feature, so there is no need to invalidate any TLB entries.
6711 * Since pmap_demote_pde() for the wired entry must never fail,
6712 * pmap_delayed_invl_start()/finish() calls around the
6713 * function are not needed.
6716 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
6718 vm_offset_t va_next;
6719 pml4_entry_t *pml4e;
6722 pt_entry_t *pte, PG_V;
6724 PG_V = pmap_valid_bit(pmap);
6726 for (; sva < eva; sva = va_next) {
6727 pml4e = pmap_pml4e(pmap, sva);
6728 if ((*pml4e & PG_V) == 0) {
6729 va_next = (sva + NBPML4) & ~PML4MASK;
6734 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
6735 if ((*pdpe & PG_V) == 0) {
6736 va_next = (sva + NBPDP) & ~PDPMASK;
6741 va_next = (sva + NBPDR) & ~PDRMASK;
6744 pde = pmap_pdpe_to_pde(pdpe, sva);
6745 if ((*pde & PG_V) == 0)
6747 if ((*pde & PG_PS) != 0) {
6748 if ((*pde & PG_W) == 0)
6749 panic("pmap_unwire: pde %#jx is missing PG_W",
6753 * Are we unwiring the entire large page? If not,
6754 * demote the mapping and fall through.
6756 if (sva + NBPDR == va_next && eva >= va_next) {
6757 atomic_clear_long(pde, PG_W);
6758 pmap->pm_stats.wired_count -= NBPDR /
6761 } else if (!pmap_demote_pde(pmap, pde, sva))
6762 panic("pmap_unwire: demotion failed");
6766 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
6768 if ((*pte & PG_V) == 0)
6770 if ((*pte & PG_W) == 0)
6771 panic("pmap_unwire: pte %#jx is missing PG_W",
6775 * PG_W must be cleared atomically. Although the pmap
6776 * lock synchronizes access to PG_W, another processor
6777 * could be setting PG_M and/or PG_A concurrently.
6779 atomic_clear_long(pte, PG_W);
6780 pmap->pm_stats.wired_count--;
6787 * Copy the range specified by src_addr/len
6788 * from the source map to the range dst_addr/len
6789 * in the destination map.
6791 * This routine is only advisory and need not do anything.
6794 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
6795 vm_offset_t src_addr)
6797 struct rwlock *lock;
6798 pml4_entry_t *pml4e;
6800 pd_entry_t *pde, srcptepaddr;
6801 pt_entry_t *dst_pte, PG_A, PG_M, PG_V, ptetemp, *src_pte;
6802 vm_offset_t addr, end_addr, va_next;
6803 vm_page_t dst_pdpg, dstmpte, srcmpte;
6805 if (dst_addr != src_addr)
6808 if (dst_pmap->pm_type != src_pmap->pm_type)
6812 * EPT page table entries that require emulation of A/D bits are
6813 * sensitive to clearing the PG_A bit (aka EPT_PG_READ). Although
6814 * we clear PG_M (aka EPT_PG_WRITE) concomitantly, the PG_U bit
6815 * (aka EPT_PG_EXECUTE) could still be set. Since some EPT
6816 * implementations flag an EPT misconfiguration for exec-only
6817 * mappings we skip this function entirely for emulated pmaps.
6819 if (pmap_emulate_ad_bits(dst_pmap))
6822 end_addr = src_addr + len;
6824 if (dst_pmap < src_pmap) {
6825 PMAP_LOCK(dst_pmap);
6826 PMAP_LOCK(src_pmap);
6828 PMAP_LOCK(src_pmap);
6829 PMAP_LOCK(dst_pmap);
6832 PG_A = pmap_accessed_bit(dst_pmap);
6833 PG_M = pmap_modified_bit(dst_pmap);
6834 PG_V = pmap_valid_bit(dst_pmap);
6836 for (addr = src_addr; addr < end_addr; addr = va_next) {
6837 KASSERT(addr < UPT_MIN_ADDRESS,
6838 ("pmap_copy: invalid to pmap_copy page tables"));
6840 pml4e = pmap_pml4e(src_pmap, addr);
6841 if ((*pml4e & PG_V) == 0) {
6842 va_next = (addr + NBPML4) & ~PML4MASK;
6848 pdpe = pmap_pml4e_to_pdpe(pml4e, addr);
6849 if ((*pdpe & PG_V) == 0) {
6850 va_next = (addr + NBPDP) & ~PDPMASK;
6856 va_next = (addr + NBPDR) & ~PDRMASK;
6860 pde = pmap_pdpe_to_pde(pdpe, addr);
6862 if (srcptepaddr == 0)
6865 if (srcptepaddr & PG_PS) {
6866 if ((addr & PDRMASK) != 0 || addr + NBPDR > end_addr)
6868 pde = pmap_alloc_pde(dst_pmap, addr, &dst_pdpg, NULL);
6871 if (*pde == 0 && ((srcptepaddr & PG_MANAGED) == 0 ||
6872 pmap_pv_insert_pde(dst_pmap, addr, srcptepaddr,
6873 PMAP_ENTER_NORECLAIM, &lock))) {
6874 *pde = srcptepaddr & ~PG_W;
6875 pmap_resident_count_inc(dst_pmap, NBPDR /
6877 atomic_add_long(&pmap_pde_mappings, 1);
6879 pmap_abort_ptp(dst_pmap, addr, dst_pdpg);
6883 srcptepaddr &= PG_FRAME;
6884 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr);
6885 KASSERT(srcmpte->ref_count > 0,
6886 ("pmap_copy: source page table page is unused"));
6888 if (va_next > end_addr)
6891 src_pte = (pt_entry_t *)PHYS_TO_DMAP(srcptepaddr);
6892 src_pte = &src_pte[pmap_pte_index(addr)];
6894 for (; addr < va_next; addr += PAGE_SIZE, src_pte++) {
6898 * We only virtual copy managed pages.
6900 if ((ptetemp & PG_MANAGED) == 0)
6903 if (dstmpte != NULL) {
6904 KASSERT(dstmpte->pindex ==
6905 pmap_pde_pindex(addr),
6906 ("dstmpte pindex/addr mismatch"));
6907 dstmpte->ref_count++;
6908 } else if ((dstmpte = pmap_allocpte(dst_pmap, addr,
6911 dst_pte = (pt_entry_t *)
6912 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dstmpte));
6913 dst_pte = &dst_pte[pmap_pte_index(addr)];
6914 if (*dst_pte == 0 &&
6915 pmap_try_insert_pv_entry(dst_pmap, addr,
6916 PHYS_TO_VM_PAGE(ptetemp & PG_FRAME), &lock)) {
6918 * Clear the wired, modified, and accessed
6919 * (referenced) bits during the copy.
6921 *dst_pte = ptetemp & ~(PG_W | PG_M | PG_A);
6922 pmap_resident_count_inc(dst_pmap, 1);
6924 pmap_abort_ptp(dst_pmap, addr, dstmpte);
6927 /* Have we copied all of the valid mappings? */
6928 if (dstmpte->ref_count >= srcmpte->ref_count)
6935 PMAP_UNLOCK(src_pmap);
6936 PMAP_UNLOCK(dst_pmap);
6940 pmap_vmspace_copy(pmap_t dst_pmap, pmap_t src_pmap)
6944 if (dst_pmap->pm_type != src_pmap->pm_type ||
6945 dst_pmap->pm_type != PT_X86 ||
6946 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0)
6949 if (dst_pmap < src_pmap) {
6950 PMAP_LOCK(dst_pmap);
6951 PMAP_LOCK(src_pmap);
6953 PMAP_LOCK(src_pmap);
6954 PMAP_LOCK(dst_pmap);
6956 error = pmap_pkru_copy(dst_pmap, src_pmap);
6957 /* Clean up partial copy on failure due to no memory. */
6958 if (error == ENOMEM)
6959 pmap_pkru_deassign_all(dst_pmap);
6960 PMAP_UNLOCK(src_pmap);
6961 PMAP_UNLOCK(dst_pmap);
6962 if (error != ENOMEM)
6970 * Zero the specified hardware page.
6973 pmap_zero_page(vm_page_t m)
6975 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
6977 pagezero((void *)va);
6981 * Zero an an area within a single hardware page. off and size must not
6982 * cover an area beyond a single hardware page.
6985 pmap_zero_page_area(vm_page_t m, int off, int size)
6987 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
6989 if (off == 0 && size == PAGE_SIZE)
6990 pagezero((void *)va);
6992 bzero((char *)va + off, size);
6996 * Copy 1 specified hardware page to another.
6999 pmap_copy_page(vm_page_t msrc, vm_page_t mdst)
7001 vm_offset_t src = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(msrc));
7002 vm_offset_t dst = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mdst));
7004 pagecopy((void *)src, (void *)dst);
7007 int unmapped_buf_allowed = 1;
7010 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
7011 vm_offset_t b_offset, int xfersize)
7015 vm_offset_t vaddr[2], a_pg_offset, b_pg_offset;
7019 while (xfersize > 0) {
7020 a_pg_offset = a_offset & PAGE_MASK;
7021 pages[0] = ma[a_offset >> PAGE_SHIFT];
7022 b_pg_offset = b_offset & PAGE_MASK;
7023 pages[1] = mb[b_offset >> PAGE_SHIFT];
7024 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
7025 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
7026 mapped = pmap_map_io_transient(pages, vaddr, 2, FALSE);
7027 a_cp = (char *)vaddr[0] + a_pg_offset;
7028 b_cp = (char *)vaddr[1] + b_pg_offset;
7029 bcopy(a_cp, b_cp, cnt);
7030 if (__predict_false(mapped))
7031 pmap_unmap_io_transient(pages, vaddr, 2, FALSE);
7039 * Returns true if the pmap's pv is one of the first
7040 * 16 pvs linked to from this page. This count may
7041 * be changed upwards or downwards in the future; it
7042 * is only necessary that true be returned for a small
7043 * subset of pmaps for proper page aging.
7046 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
7048 struct md_page *pvh;
7049 struct rwlock *lock;
7054 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
7055 ("pmap_page_exists_quick: page %p is not managed", m));
7057 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
7059 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
7060 if (PV_PMAP(pv) == pmap) {
7068 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
7069 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
7070 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
7071 if (PV_PMAP(pv) == pmap) {
7085 * pmap_page_wired_mappings:
7087 * Return the number of managed mappings to the given physical page
7091 pmap_page_wired_mappings(vm_page_t m)
7093 struct rwlock *lock;
7094 struct md_page *pvh;
7098 int count, md_gen, pvh_gen;
7100 if ((m->oflags & VPO_UNMANAGED) != 0)
7102 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
7106 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
7108 if (!PMAP_TRYLOCK(pmap)) {
7109 md_gen = m->md.pv_gen;
7113 if (md_gen != m->md.pv_gen) {
7118 pte = pmap_pte(pmap, pv->pv_va);
7119 if ((*pte & PG_W) != 0)
7123 if ((m->flags & PG_FICTITIOUS) == 0) {
7124 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
7125 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
7127 if (!PMAP_TRYLOCK(pmap)) {
7128 md_gen = m->md.pv_gen;
7129 pvh_gen = pvh->pv_gen;
7133 if (md_gen != m->md.pv_gen ||
7134 pvh_gen != pvh->pv_gen) {
7139 pte = pmap_pde(pmap, pv->pv_va);
7140 if ((*pte & PG_W) != 0)
7150 * Returns TRUE if the given page is mapped individually or as part of
7151 * a 2mpage. Otherwise, returns FALSE.
7154 pmap_page_is_mapped(vm_page_t m)
7156 struct rwlock *lock;
7159 if ((m->oflags & VPO_UNMANAGED) != 0)
7161 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
7163 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
7164 ((m->flags & PG_FICTITIOUS) == 0 &&
7165 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
7171 * Destroy all managed, non-wired mappings in the given user-space
7172 * pmap. This pmap cannot be active on any processor besides the
7175 * This function cannot be applied to the kernel pmap. Moreover, it
7176 * is not intended for general use. It is only to be used during
7177 * process termination. Consequently, it can be implemented in ways
7178 * that make it faster than pmap_remove(). First, it can more quickly
7179 * destroy mappings by iterating over the pmap's collection of PV
7180 * entries, rather than searching the page table. Second, it doesn't
7181 * have to test and clear the page table entries atomically, because
7182 * no processor is currently accessing the user address space. In
7183 * particular, a page table entry's dirty bit won't change state once
7184 * this function starts.
7186 * Although this function destroys all of the pmap's managed,
7187 * non-wired mappings, it can delay and batch the invalidation of TLB
7188 * entries without calling pmap_delayed_invl_start() and
7189 * pmap_delayed_invl_finish(). Because the pmap is not active on
7190 * any other processor, none of these TLB entries will ever be used
7191 * before their eventual invalidation. Consequently, there is no need
7192 * for either pmap_remove_all() or pmap_remove_write() to wait for
7193 * that eventual TLB invalidation.
7196 pmap_remove_pages(pmap_t pmap)
7199 pt_entry_t *pte, tpte;
7200 pt_entry_t PG_M, PG_RW, PG_V;
7201 struct spglist free;
7202 struct pv_chunklist free_chunks[PMAP_MEMDOM];
7203 vm_page_t m, mpte, mt;
7205 struct md_page *pvh;
7206 struct pv_chunk *pc, *npc;
7207 struct rwlock *lock;
7209 uint64_t inuse, bitmask;
7210 int allfree, field, freed, i, idx;
7211 boolean_t superpage;
7215 * Assert that the given pmap is only active on the current
7216 * CPU. Unfortunately, we cannot block another CPU from
7217 * activating the pmap while this function is executing.
7219 KASSERT(pmap == PCPU_GET(curpmap), ("non-current pmap %p", pmap));
7222 cpuset_t other_cpus;
7224 other_cpus = all_cpus;
7226 CPU_CLR(PCPU_GET(cpuid), &other_cpus);
7227 CPU_AND(&other_cpus, &pmap->pm_active);
7229 KASSERT(CPU_EMPTY(&other_cpus), ("pmap active %p", pmap));
7234 PG_M = pmap_modified_bit(pmap);
7235 PG_V = pmap_valid_bit(pmap);
7236 PG_RW = pmap_rw_bit(pmap);
7238 for (i = 0; i < PMAP_MEMDOM; i++)
7239 TAILQ_INIT(&free_chunks[i]);
7242 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
7245 for (field = 0; field < _NPCM; field++) {
7246 inuse = ~pc->pc_map[field] & pc_freemask[field];
7247 while (inuse != 0) {
7249 bitmask = 1UL << bit;
7250 idx = field * 64 + bit;
7251 pv = &pc->pc_pventry[idx];
7254 pte = pmap_pdpe(pmap, pv->pv_va);
7256 pte = pmap_pdpe_to_pde(pte, pv->pv_va);
7258 if ((tpte & (PG_PS | PG_V)) == PG_V) {
7261 pte = (pt_entry_t *)PHYS_TO_DMAP(tpte &
7263 pte = &pte[pmap_pte_index(pv->pv_va)];
7267 * Keep track whether 'tpte' is a
7268 * superpage explicitly instead of
7269 * relying on PG_PS being set.
7271 * This is because PG_PS is numerically
7272 * identical to PG_PTE_PAT and thus a
7273 * regular page could be mistaken for
7279 if ((tpte & PG_V) == 0) {
7280 panic("bad pte va %lx pte %lx",
7285 * We cannot remove wired pages from a process' mapping at this time
7293 pa = tpte & PG_PS_FRAME;
7295 pa = tpte & PG_FRAME;
7297 m = PHYS_TO_VM_PAGE(pa);
7298 KASSERT(m->phys_addr == pa,
7299 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
7300 m, (uintmax_t)m->phys_addr,
7303 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
7304 m < &vm_page_array[vm_page_array_size],
7305 ("pmap_remove_pages: bad tpte %#jx",
7311 * Update the vm_page_t clean/reference bits.
7313 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
7315 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
7321 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(&lock, m);
7324 pc->pc_map[field] |= bitmask;
7326 pmap_resident_count_dec(pmap, NBPDR / PAGE_SIZE);
7327 pvh = pa_to_pvh(tpte & PG_PS_FRAME);
7328 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
7330 if (TAILQ_EMPTY(&pvh->pv_list)) {
7331 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
7332 if ((mt->a.flags & PGA_WRITEABLE) != 0 &&
7333 TAILQ_EMPTY(&mt->md.pv_list))
7334 vm_page_aflag_clear(mt, PGA_WRITEABLE);
7336 mpte = pmap_remove_pt_page(pmap, pv->pv_va);
7338 KASSERT(mpte->valid == VM_PAGE_BITS_ALL,
7339 ("pmap_remove_pages: pte page not promoted"));
7340 pmap_resident_count_dec(pmap, 1);
7341 KASSERT(mpte->ref_count == NPTEPG,
7342 ("pmap_remove_pages: pte page reference count error"));
7343 mpte->ref_count = 0;
7344 pmap_add_delayed_free_list(mpte, &free, FALSE);
7347 pmap_resident_count_dec(pmap, 1);
7348 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
7350 if ((m->a.flags & PGA_WRITEABLE) != 0 &&
7351 TAILQ_EMPTY(&m->md.pv_list) &&
7352 (m->flags & PG_FICTITIOUS) == 0) {
7353 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
7354 if (TAILQ_EMPTY(&pvh->pv_list))
7355 vm_page_aflag_clear(m, PGA_WRITEABLE);
7358 pmap_unuse_pt(pmap, pv->pv_va, ptepde, &free);
7362 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
7363 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
7364 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
7366 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
7367 TAILQ_INSERT_TAIL(&free_chunks[pc_to_domain(pc)], pc, pc_list);
7372 pmap_invalidate_all(pmap);
7373 pmap_pkru_deassign_all(pmap);
7374 free_pv_chunk_batch((struct pv_chunklist *)&free_chunks);
7376 vm_page_free_pages_toq(&free, true);
7380 pmap_page_test_mappings(vm_page_t m, boolean_t accessed, boolean_t modified)
7382 struct rwlock *lock;
7384 struct md_page *pvh;
7385 pt_entry_t *pte, mask;
7386 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
7388 int md_gen, pvh_gen;
7392 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
7395 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
7397 if (!PMAP_TRYLOCK(pmap)) {
7398 md_gen = m->md.pv_gen;
7402 if (md_gen != m->md.pv_gen) {
7407 pte = pmap_pte(pmap, pv->pv_va);
7410 PG_M = pmap_modified_bit(pmap);
7411 PG_RW = pmap_rw_bit(pmap);
7412 mask |= PG_RW | PG_M;
7415 PG_A = pmap_accessed_bit(pmap);
7416 PG_V = pmap_valid_bit(pmap);
7417 mask |= PG_V | PG_A;
7419 rv = (*pte & mask) == mask;
7424 if ((m->flags & PG_FICTITIOUS) == 0) {
7425 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
7426 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
7428 if (!PMAP_TRYLOCK(pmap)) {
7429 md_gen = m->md.pv_gen;
7430 pvh_gen = pvh->pv_gen;
7434 if (md_gen != m->md.pv_gen ||
7435 pvh_gen != pvh->pv_gen) {
7440 pte = pmap_pde(pmap, pv->pv_va);
7443 PG_M = pmap_modified_bit(pmap);
7444 PG_RW = pmap_rw_bit(pmap);
7445 mask |= PG_RW | PG_M;
7448 PG_A = pmap_accessed_bit(pmap);
7449 PG_V = pmap_valid_bit(pmap);
7450 mask |= PG_V | PG_A;
7452 rv = (*pte & mask) == mask;
7466 * Return whether or not the specified physical page was modified
7467 * in any physical maps.
7470 pmap_is_modified(vm_page_t m)
7473 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
7474 ("pmap_is_modified: page %p is not managed", m));
7477 * If the page is not busied then this check is racy.
7479 if (!pmap_page_is_write_mapped(m))
7481 return (pmap_page_test_mappings(m, FALSE, TRUE));
7485 * pmap_is_prefaultable:
7487 * Return whether or not the specified virtual address is eligible
7491 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
7494 pt_entry_t *pte, PG_V;
7497 PG_V = pmap_valid_bit(pmap);
7500 pde = pmap_pde(pmap, addr);
7501 if (pde != NULL && (*pde & (PG_PS | PG_V)) == PG_V) {
7502 pte = pmap_pde_to_pte(pde, addr);
7503 rv = (*pte & PG_V) == 0;
7510 * pmap_is_referenced:
7512 * Return whether or not the specified physical page was referenced
7513 * in any physical maps.
7516 pmap_is_referenced(vm_page_t m)
7519 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
7520 ("pmap_is_referenced: page %p is not managed", m));
7521 return (pmap_page_test_mappings(m, TRUE, FALSE));
7525 * Clear the write and modified bits in each of the given page's mappings.
7528 pmap_remove_write(vm_page_t m)
7530 struct md_page *pvh;
7532 struct rwlock *lock;
7533 pv_entry_t next_pv, pv;
7535 pt_entry_t oldpte, *pte, PG_M, PG_RW;
7537 int pvh_gen, md_gen;
7539 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
7540 ("pmap_remove_write: page %p is not managed", m));
7542 vm_page_assert_busied(m);
7543 if (!pmap_page_is_write_mapped(m))
7546 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
7547 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
7548 pa_to_pvh(VM_PAGE_TO_PHYS(m));
7551 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
7553 if (!PMAP_TRYLOCK(pmap)) {
7554 pvh_gen = pvh->pv_gen;
7558 if (pvh_gen != pvh->pv_gen) {
7564 PG_RW = pmap_rw_bit(pmap);
7566 pde = pmap_pde(pmap, va);
7567 if ((*pde & PG_RW) != 0)
7568 (void)pmap_demote_pde_locked(pmap, pde, va, &lock);
7569 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
7570 ("inconsistent pv lock %p %p for page %p",
7571 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
7574 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
7576 if (!PMAP_TRYLOCK(pmap)) {
7577 pvh_gen = pvh->pv_gen;
7578 md_gen = m->md.pv_gen;
7582 if (pvh_gen != pvh->pv_gen ||
7583 md_gen != m->md.pv_gen) {
7589 PG_M = pmap_modified_bit(pmap);
7590 PG_RW = pmap_rw_bit(pmap);
7591 pde = pmap_pde(pmap, pv->pv_va);
7592 KASSERT((*pde & PG_PS) == 0,
7593 ("pmap_remove_write: found a 2mpage in page %p's pv list",
7595 pte = pmap_pde_to_pte(pde, pv->pv_va);
7598 if (oldpte & PG_RW) {
7599 if (!atomic_cmpset_long(pte, oldpte, oldpte &
7602 if ((oldpte & PG_M) != 0)
7604 pmap_invalidate_page(pmap, pv->pv_va);
7609 vm_page_aflag_clear(m, PGA_WRITEABLE);
7610 pmap_delayed_invl_wait(m);
7613 static __inline boolean_t
7614 safe_to_clear_referenced(pmap_t pmap, pt_entry_t pte)
7617 if (!pmap_emulate_ad_bits(pmap))
7620 KASSERT(pmap->pm_type == PT_EPT, ("invalid pm_type %d", pmap->pm_type));
7623 * XWR = 010 or 110 will cause an unconditional EPT misconfiguration
7624 * so we don't let the referenced (aka EPT_PG_READ) bit to be cleared
7625 * if the EPT_PG_WRITE bit is set.
7627 if ((pte & EPT_PG_WRITE) != 0)
7631 * XWR = 100 is allowed only if the PMAP_SUPPORTS_EXEC_ONLY is set.
7633 if ((pte & EPT_PG_EXECUTE) == 0 ||
7634 ((pmap->pm_flags & PMAP_SUPPORTS_EXEC_ONLY) != 0))
7641 * pmap_ts_referenced:
7643 * Return a count of reference bits for a page, clearing those bits.
7644 * It is not necessary for every reference bit to be cleared, but it
7645 * is necessary that 0 only be returned when there are truly no
7646 * reference bits set.
7648 * As an optimization, update the page's dirty field if a modified bit is
7649 * found while counting reference bits. This opportunistic update can be
7650 * performed at low cost and can eliminate the need for some future calls
7651 * to pmap_is_modified(). However, since this function stops after
7652 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
7653 * dirty pages. Those dirty pages will only be detected by a future call
7654 * to pmap_is_modified().
7656 * A DI block is not needed within this function, because
7657 * invalidations are performed before the PV list lock is
7661 pmap_ts_referenced(vm_page_t m)
7663 struct md_page *pvh;
7666 struct rwlock *lock;
7667 pd_entry_t oldpde, *pde;
7668 pt_entry_t *pte, PG_A, PG_M, PG_RW;
7671 int cleared, md_gen, not_cleared, pvh_gen;
7672 struct spglist free;
7675 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
7676 ("pmap_ts_referenced: page %p is not managed", m));
7679 pa = VM_PAGE_TO_PHYS(m);
7680 lock = PHYS_TO_PV_LIST_LOCK(pa);
7681 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : pa_to_pvh(pa);
7685 if ((pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
7686 goto small_mappings;
7692 if (!PMAP_TRYLOCK(pmap)) {
7693 pvh_gen = pvh->pv_gen;
7697 if (pvh_gen != pvh->pv_gen) {
7702 PG_A = pmap_accessed_bit(pmap);
7703 PG_M = pmap_modified_bit(pmap);
7704 PG_RW = pmap_rw_bit(pmap);
7706 pde = pmap_pde(pmap, pv->pv_va);
7708 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
7710 * Although "oldpde" is mapping a 2MB page, because
7711 * this function is called at a 4KB page granularity,
7712 * we only update the 4KB page under test.
7716 if ((oldpde & PG_A) != 0) {
7718 * Since this reference bit is shared by 512 4KB
7719 * pages, it should not be cleared every time it is
7720 * tested. Apply a simple "hash" function on the
7721 * physical page number, the virtual superpage number,
7722 * and the pmap address to select one 4KB page out of
7723 * the 512 on which testing the reference bit will
7724 * result in clearing that reference bit. This
7725 * function is designed to avoid the selection of the
7726 * same 4KB page for every 2MB page mapping.
7728 * On demotion, a mapping that hasn't been referenced
7729 * is simply destroyed. To avoid the possibility of a
7730 * subsequent page fault on a demoted wired mapping,
7731 * always leave its reference bit set. Moreover,
7732 * since the superpage is wired, the current state of
7733 * its reference bit won't affect page replacement.
7735 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> PDRSHIFT) ^
7736 (uintptr_t)pmap) & (NPTEPG - 1)) == 0 &&
7737 (oldpde & PG_W) == 0) {
7738 if (safe_to_clear_referenced(pmap, oldpde)) {
7739 atomic_clear_long(pde, PG_A);
7740 pmap_invalidate_page(pmap, pv->pv_va);
7742 } else if (pmap_demote_pde_locked(pmap, pde,
7743 pv->pv_va, &lock)) {
7745 * Remove the mapping to a single page
7746 * so that a subsequent access may
7747 * repromote. Since the underlying
7748 * page table page is fully populated,
7749 * this removal never frees a page
7753 va += VM_PAGE_TO_PHYS(m) - (oldpde &
7755 pte = pmap_pde_to_pte(pde, va);
7756 pmap_remove_pte(pmap, pte, va, *pde,
7758 pmap_invalidate_page(pmap, va);
7764 * The superpage mapping was removed
7765 * entirely and therefore 'pv' is no
7773 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
7774 ("inconsistent pv lock %p %p for page %p",
7775 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
7780 /* Rotate the PV list if it has more than one entry. */
7781 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
7782 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
7783 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
7786 if (cleared + not_cleared >= PMAP_TS_REFERENCED_MAX)
7788 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
7790 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
7797 if (!PMAP_TRYLOCK(pmap)) {
7798 pvh_gen = pvh->pv_gen;
7799 md_gen = m->md.pv_gen;
7803 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
7808 PG_A = pmap_accessed_bit(pmap);
7809 PG_M = pmap_modified_bit(pmap);
7810 PG_RW = pmap_rw_bit(pmap);
7811 pde = pmap_pde(pmap, pv->pv_va);
7812 KASSERT((*pde & PG_PS) == 0,
7813 ("pmap_ts_referenced: found a 2mpage in page %p's pv list",
7815 pte = pmap_pde_to_pte(pde, pv->pv_va);
7816 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
7818 if ((*pte & PG_A) != 0) {
7819 if (safe_to_clear_referenced(pmap, *pte)) {
7820 atomic_clear_long(pte, PG_A);
7821 pmap_invalidate_page(pmap, pv->pv_va);
7823 } else if ((*pte & PG_W) == 0) {
7825 * Wired pages cannot be paged out so
7826 * doing accessed bit emulation for
7827 * them is wasted effort. We do the
7828 * hard work for unwired pages only.
7830 pmap_remove_pte(pmap, pte, pv->pv_va,
7831 *pde, &free, &lock);
7832 pmap_invalidate_page(pmap, pv->pv_va);
7837 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
7838 ("inconsistent pv lock %p %p for page %p",
7839 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
7844 /* Rotate the PV list if it has more than one entry. */
7845 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
7846 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
7847 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
7850 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && cleared +
7851 not_cleared < PMAP_TS_REFERENCED_MAX);
7854 vm_page_free_pages_toq(&free, true);
7855 return (cleared + not_cleared);
7859 * Apply the given advice to the specified range of addresses within the
7860 * given pmap. Depending on the advice, clear the referenced and/or
7861 * modified flags in each mapping and set the mapped page's dirty field.
7864 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
7866 struct rwlock *lock;
7867 pml4_entry_t *pml4e;
7869 pd_entry_t oldpde, *pde;
7870 pt_entry_t *pte, PG_A, PG_G, PG_M, PG_RW, PG_V;
7871 vm_offset_t va, va_next;
7875 if (advice != MADV_DONTNEED && advice != MADV_FREE)
7879 * A/D bit emulation requires an alternate code path when clearing
7880 * the modified and accessed bits below. Since this function is
7881 * advisory in nature we skip it entirely for pmaps that require
7882 * A/D bit emulation.
7884 if (pmap_emulate_ad_bits(pmap))
7887 PG_A = pmap_accessed_bit(pmap);
7888 PG_G = pmap_global_bit(pmap);
7889 PG_M = pmap_modified_bit(pmap);
7890 PG_V = pmap_valid_bit(pmap);
7891 PG_RW = pmap_rw_bit(pmap);
7893 pmap_delayed_invl_start();
7895 for (; sva < eva; sva = va_next) {
7896 pml4e = pmap_pml4e(pmap, sva);
7897 if ((*pml4e & PG_V) == 0) {
7898 va_next = (sva + NBPML4) & ~PML4MASK;
7903 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
7904 if ((*pdpe & PG_V) == 0) {
7905 va_next = (sva + NBPDP) & ~PDPMASK;
7910 va_next = (sva + NBPDR) & ~PDRMASK;
7913 pde = pmap_pdpe_to_pde(pdpe, sva);
7915 if ((oldpde & PG_V) == 0)
7917 else if ((oldpde & PG_PS) != 0) {
7918 if ((oldpde & PG_MANAGED) == 0)
7921 if (!pmap_demote_pde_locked(pmap, pde, sva, &lock)) {
7926 * The large page mapping was destroyed.
7932 * Unless the page mappings are wired, remove the
7933 * mapping to a single page so that a subsequent
7934 * access may repromote. Choosing the last page
7935 * within the address range [sva, min(va_next, eva))
7936 * generally results in more repromotions. Since the
7937 * underlying page table page is fully populated, this
7938 * removal never frees a page table page.
7940 if ((oldpde & PG_W) == 0) {
7946 ("pmap_advise: no address gap"));
7947 pte = pmap_pde_to_pte(pde, va);
7948 KASSERT((*pte & PG_V) != 0,
7949 ("pmap_advise: invalid PTE"));
7950 pmap_remove_pte(pmap, pte, va, *pde, NULL,
7960 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
7962 if ((*pte & (PG_MANAGED | PG_V)) != (PG_MANAGED | PG_V))
7964 else if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
7965 if (advice == MADV_DONTNEED) {
7967 * Future calls to pmap_is_modified()
7968 * can be avoided by making the page
7971 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
7974 atomic_clear_long(pte, PG_M | PG_A);
7975 } else if ((*pte & PG_A) != 0)
7976 atomic_clear_long(pte, PG_A);
7980 if ((*pte & PG_G) != 0) {
7987 if (va != va_next) {
7988 pmap_invalidate_range(pmap, va, sva);
7993 pmap_invalidate_range(pmap, va, sva);
7996 pmap_invalidate_all(pmap);
7998 pmap_delayed_invl_finish();
8002 * Clear the modify bits on the specified physical page.
8005 pmap_clear_modify(vm_page_t m)
8007 struct md_page *pvh;
8009 pv_entry_t next_pv, pv;
8010 pd_entry_t oldpde, *pde;
8011 pt_entry_t *pte, PG_M, PG_RW;
8012 struct rwlock *lock;
8014 int md_gen, pvh_gen;
8016 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
8017 ("pmap_clear_modify: page %p is not managed", m));
8018 vm_page_assert_busied(m);
8020 if (!pmap_page_is_write_mapped(m))
8022 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
8023 pa_to_pvh(VM_PAGE_TO_PHYS(m));
8024 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
8027 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
8029 if (!PMAP_TRYLOCK(pmap)) {
8030 pvh_gen = pvh->pv_gen;
8034 if (pvh_gen != pvh->pv_gen) {
8039 PG_M = pmap_modified_bit(pmap);
8040 PG_RW = pmap_rw_bit(pmap);
8042 pde = pmap_pde(pmap, va);
8044 /* If oldpde has PG_RW set, then it also has PG_M set. */
8045 if ((oldpde & PG_RW) != 0 &&
8046 pmap_demote_pde_locked(pmap, pde, va, &lock) &&
8047 (oldpde & PG_W) == 0) {
8049 * Write protect the mapping to a single page so that
8050 * a subsequent write access may repromote.
8052 va += VM_PAGE_TO_PHYS(m) - (oldpde & PG_PS_FRAME);
8053 pte = pmap_pde_to_pte(pde, va);
8054 atomic_clear_long(pte, PG_M | PG_RW);
8056 pmap_invalidate_page(pmap, va);
8060 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
8062 if (!PMAP_TRYLOCK(pmap)) {
8063 md_gen = m->md.pv_gen;
8064 pvh_gen = pvh->pv_gen;
8068 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
8073 PG_M = pmap_modified_bit(pmap);
8074 PG_RW = pmap_rw_bit(pmap);
8075 pde = pmap_pde(pmap, pv->pv_va);
8076 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_modify: found"
8077 " a 2mpage in page %p's pv list", m));
8078 pte = pmap_pde_to_pte(pde, pv->pv_va);
8079 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
8080 atomic_clear_long(pte, PG_M);
8081 pmap_invalidate_page(pmap, pv->pv_va);
8089 * Miscellaneous support routines follow
8092 /* Adjust the properties for a leaf page table entry. */
8093 static __inline void
8094 pmap_pte_props(pt_entry_t *pte, u_long bits, u_long mask)
8098 opte = *(u_long *)pte;
8100 npte = opte & ~mask;
8102 } while (npte != opte && !atomic_fcmpset_long((u_long *)pte, &opte,
8107 * Map a set of physical memory pages into the kernel virtual
8108 * address space. Return a pointer to where it is mapped. This
8109 * routine is intended to be used for mapping device memory,
8113 pmap_mapdev_internal(vm_paddr_t pa, vm_size_t size, int mode, int flags)
8115 struct pmap_preinit_mapping *ppim;
8116 vm_offset_t va, offset;
8120 offset = pa & PAGE_MASK;
8121 size = round_page(offset + size);
8122 pa = trunc_page(pa);
8124 if (!pmap_initialized) {
8126 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
8127 ppim = pmap_preinit_mapping + i;
8128 if (ppim->va == 0) {
8132 ppim->va = virtual_avail;
8133 virtual_avail += size;
8139 panic("%s: too many preinit mappings", __func__);
8142 * If we have a preinit mapping, re-use it.
8144 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
8145 ppim = pmap_preinit_mapping + i;
8146 if (ppim->pa == pa && ppim->sz == size &&
8147 (ppim->mode == mode ||
8148 (flags & MAPDEV_SETATTR) == 0))
8149 return ((void *)(ppim->va + offset));
8152 * If the specified range of physical addresses fits within
8153 * the direct map window, use the direct map.
8155 if (pa < dmaplimit && pa + size <= dmaplimit) {
8156 va = PHYS_TO_DMAP(pa);
8157 if ((flags & MAPDEV_SETATTR) != 0) {
8158 PMAP_LOCK(kernel_pmap);
8159 i = pmap_change_props_locked(va, size,
8160 PROT_NONE, mode, flags);
8161 PMAP_UNLOCK(kernel_pmap);
8165 return ((void *)(va + offset));
8167 va = kva_alloc(size);
8169 panic("%s: Couldn't allocate KVA", __func__);
8171 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
8172 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode);
8173 pmap_invalidate_range(kernel_pmap, va, va + tmpsize);
8174 if ((flags & MAPDEV_FLUSHCACHE) != 0)
8175 pmap_invalidate_cache_range(va, va + tmpsize);
8176 return ((void *)(va + offset));
8180 pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode)
8183 return (pmap_mapdev_internal(pa, size, mode, MAPDEV_FLUSHCACHE |
8188 pmap_mapdev(vm_paddr_t pa, vm_size_t size)
8191 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE));
8195 pmap_mapdev_pciecfg(vm_paddr_t pa, vm_size_t size)
8198 return (pmap_mapdev_internal(pa, size, PAT_UNCACHEABLE,
8203 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
8206 return (pmap_mapdev_internal(pa, size, PAT_WRITE_BACK,
8207 MAPDEV_FLUSHCACHE));
8211 pmap_unmapdev(vm_offset_t va, vm_size_t size)
8213 struct pmap_preinit_mapping *ppim;
8217 /* If we gave a direct map region in pmap_mapdev, do nothing */
8218 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS)
8220 offset = va & PAGE_MASK;
8221 size = round_page(offset + size);
8222 va = trunc_page(va);
8223 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
8224 ppim = pmap_preinit_mapping + i;
8225 if (ppim->va == va && ppim->sz == size) {
8226 if (pmap_initialized)
8232 if (va + size == virtual_avail)
8237 if (pmap_initialized)
8242 * Tries to demote a 1GB page mapping.
8245 pmap_demote_pdpe(pmap_t pmap, pdp_entry_t *pdpe, vm_offset_t va)
8247 pdp_entry_t newpdpe, oldpdpe;
8248 pd_entry_t *firstpde, newpde, *pde;
8249 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
8253 PG_A = pmap_accessed_bit(pmap);
8254 PG_M = pmap_modified_bit(pmap);
8255 PG_V = pmap_valid_bit(pmap);
8256 PG_RW = pmap_rw_bit(pmap);
8258 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
8260 KASSERT((oldpdpe & (PG_PS | PG_V)) == (PG_PS | PG_V),
8261 ("pmap_demote_pdpe: oldpdpe is missing PG_PS and/or PG_V"));
8262 if ((pdpg = vm_page_alloc(NULL, va >> PDPSHIFT, VM_ALLOC_INTERRUPT |
8263 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
8264 CTR2(KTR_PMAP, "pmap_demote_pdpe: failure for va %#lx"
8265 " in pmap %p", va, pmap);
8268 pdpgpa = VM_PAGE_TO_PHYS(pdpg);
8269 firstpde = (pd_entry_t *)PHYS_TO_DMAP(pdpgpa);
8270 newpdpe = pdpgpa | PG_M | PG_A | (oldpdpe & PG_U) | PG_RW | PG_V;
8271 KASSERT((oldpdpe & PG_A) != 0,
8272 ("pmap_demote_pdpe: oldpdpe is missing PG_A"));
8273 KASSERT((oldpdpe & (PG_M | PG_RW)) != PG_RW,
8274 ("pmap_demote_pdpe: oldpdpe is missing PG_M"));
8278 * Initialize the page directory page.
8280 for (pde = firstpde; pde < firstpde + NPDEPG; pde++) {
8286 * Demote the mapping.
8291 * Invalidate a stale recursive mapping of the page directory page.
8293 pmap_invalidate_page(pmap, (vm_offset_t)vtopde(va));
8295 pmap_pdpe_demotions++;
8296 CTR2(KTR_PMAP, "pmap_demote_pdpe: success for va %#lx"
8297 " in pmap %p", va, pmap);
8302 * Sets the memory attribute for the specified page.
8305 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
8308 m->md.pat_mode = ma;
8311 * If "m" is a normal page, update its direct mapping. This update
8312 * can be relied upon to perform any cache operations that are
8313 * required for data coherence.
8315 if ((m->flags & PG_FICTITIOUS) == 0 &&
8316 pmap_change_attr(PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)), PAGE_SIZE,
8318 panic("memory attribute change on the direct map failed");
8322 * Changes the specified virtual address range's memory type to that given by
8323 * the parameter "mode". The specified virtual address range must be
8324 * completely contained within either the direct map or the kernel map. If
8325 * the virtual address range is contained within the kernel map, then the
8326 * memory type for each of the corresponding ranges of the direct map is also
8327 * changed. (The corresponding ranges of the direct map are those ranges that
8328 * map the same physical pages as the specified virtual address range.) These
8329 * changes to the direct map are necessary because Intel describes the
8330 * behavior of their processors as "undefined" if two or more mappings to the
8331 * same physical page have different memory types.
8333 * Returns zero if the change completed successfully, and either EINVAL or
8334 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
8335 * of the virtual address range was not mapped, and ENOMEM is returned if
8336 * there was insufficient memory available to complete the change. In the
8337 * latter case, the memory type may have been changed on some part of the
8338 * virtual address range or the direct map.
8341 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
8345 PMAP_LOCK(kernel_pmap);
8346 error = pmap_change_props_locked(va, size, PROT_NONE, mode,
8348 PMAP_UNLOCK(kernel_pmap);
8353 * Changes the specified virtual address range's protections to those
8354 * specified by "prot". Like pmap_change_attr(), protections for aliases
8355 * in the direct map are updated as well. Protections on aliasing mappings may
8356 * be a subset of the requested protections; for example, mappings in the direct
8357 * map are never executable.
8360 pmap_change_prot(vm_offset_t va, vm_size_t size, vm_prot_t prot)
8364 /* Only supported within the kernel map. */
8365 if (va < VM_MIN_KERNEL_ADDRESS)
8368 PMAP_LOCK(kernel_pmap);
8369 error = pmap_change_props_locked(va, size, prot, -1,
8370 MAPDEV_ASSERTVALID);
8371 PMAP_UNLOCK(kernel_pmap);
8376 pmap_change_props_locked(vm_offset_t va, vm_size_t size, vm_prot_t prot,
8377 int mode, int flags)
8379 vm_offset_t base, offset, tmpva;
8380 vm_paddr_t pa_start, pa_end, pa_end1;
8382 pd_entry_t *pde, pde_bits, pde_mask;
8383 pt_entry_t *pte, pte_bits, pte_mask;
8387 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
8388 base = trunc_page(va);
8389 offset = va & PAGE_MASK;
8390 size = round_page(offset + size);
8393 * Only supported on kernel virtual addresses, including the direct
8394 * map but excluding the recursive map.
8396 if (base < DMAP_MIN_ADDRESS)
8400 * Construct our flag sets and masks. "bits" is the subset of
8401 * "mask" that will be set in each modified PTE.
8403 * Mappings in the direct map are never allowed to be executable.
8405 pde_bits = pte_bits = 0;
8406 pde_mask = pte_mask = 0;
8408 pde_bits |= pmap_cache_bits(kernel_pmap, mode, true);
8409 pde_mask |= X86_PG_PDE_CACHE;
8410 pte_bits |= pmap_cache_bits(kernel_pmap, mode, false);
8411 pte_mask |= X86_PG_PTE_CACHE;
8413 if (prot != VM_PROT_NONE) {
8414 if ((prot & VM_PROT_WRITE) != 0) {
8415 pde_bits |= X86_PG_RW;
8416 pte_bits |= X86_PG_RW;
8418 if ((prot & VM_PROT_EXECUTE) == 0 ||
8419 va < VM_MIN_KERNEL_ADDRESS) {
8423 pde_mask |= X86_PG_RW | pg_nx;
8424 pte_mask |= X86_PG_RW | pg_nx;
8428 * Pages that aren't mapped aren't supported. Also break down 2MB pages
8429 * into 4KB pages if required.
8431 for (tmpva = base; tmpva < base + size; ) {
8432 pdpe = pmap_pdpe(kernel_pmap, tmpva);
8433 if (pdpe == NULL || *pdpe == 0) {
8434 KASSERT((flags & MAPDEV_ASSERTVALID) == 0,
8435 ("%s: addr %#lx is not mapped", __func__, tmpva));
8438 if (*pdpe & PG_PS) {
8440 * If the current 1GB page already has the required
8441 * properties, then we need not demote this page. Just
8442 * increment tmpva to the next 1GB page frame.
8444 if ((*pdpe & pde_mask) == pde_bits) {
8445 tmpva = trunc_1gpage(tmpva) + NBPDP;
8450 * If the current offset aligns with a 1GB page frame
8451 * and there is at least 1GB left within the range, then
8452 * we need not break down this page into 2MB pages.
8454 if ((tmpva & PDPMASK) == 0 &&
8455 tmpva + PDPMASK < base + size) {
8459 if (!pmap_demote_pdpe(kernel_pmap, pdpe, tmpva))
8462 pde = pmap_pdpe_to_pde(pdpe, tmpva);
8464 KASSERT((flags & MAPDEV_ASSERTVALID) == 0,
8465 ("%s: addr %#lx is not mapped", __func__, tmpva));
8470 * If the current 2MB page already has the required
8471 * properties, then we need not demote this page. Just
8472 * increment tmpva to the next 2MB page frame.
8474 if ((*pde & pde_mask) == pde_bits) {
8475 tmpva = trunc_2mpage(tmpva) + NBPDR;
8480 * If the current offset aligns with a 2MB page frame
8481 * and there is at least 2MB left within the range, then
8482 * we need not break down this page into 4KB pages.
8484 if ((tmpva & PDRMASK) == 0 &&
8485 tmpva + PDRMASK < base + size) {
8489 if (!pmap_demote_pde(kernel_pmap, pde, tmpva))
8492 pte = pmap_pde_to_pte(pde, tmpva);
8494 KASSERT((flags & MAPDEV_ASSERTVALID) == 0,
8495 ("%s: addr %#lx is not mapped", __func__, tmpva));
8503 * Ok, all the pages exist, so run through them updating their
8504 * properties if required.
8507 pa_start = pa_end = 0;
8508 for (tmpva = base; tmpva < base + size; ) {
8509 pdpe = pmap_pdpe(kernel_pmap, tmpva);
8510 if (*pdpe & PG_PS) {
8511 if ((*pdpe & pde_mask) != pde_bits) {
8512 pmap_pte_props(pdpe, pde_bits, pde_mask);
8515 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
8516 (*pdpe & PG_PS_FRAME) < dmaplimit) {
8517 if (pa_start == pa_end) {
8518 /* Start physical address run. */
8519 pa_start = *pdpe & PG_PS_FRAME;
8520 pa_end = pa_start + NBPDP;
8521 } else if (pa_end == (*pdpe & PG_PS_FRAME))
8524 /* Run ended, update direct map. */
8525 error = pmap_change_props_locked(
8526 PHYS_TO_DMAP(pa_start),
8527 pa_end - pa_start, prot, mode,
8531 /* Start physical address run. */
8532 pa_start = *pdpe & PG_PS_FRAME;
8533 pa_end = pa_start + NBPDP;
8536 tmpva = trunc_1gpage(tmpva) + NBPDP;
8539 pde = pmap_pdpe_to_pde(pdpe, tmpva);
8541 if ((*pde & pde_mask) != pde_bits) {
8542 pmap_pte_props(pde, pde_bits, pde_mask);
8545 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
8546 (*pde & PG_PS_FRAME) < dmaplimit) {
8547 if (pa_start == pa_end) {
8548 /* Start physical address run. */
8549 pa_start = *pde & PG_PS_FRAME;
8550 pa_end = pa_start + NBPDR;
8551 } else if (pa_end == (*pde & PG_PS_FRAME))
8554 /* Run ended, update direct map. */
8555 error = pmap_change_props_locked(
8556 PHYS_TO_DMAP(pa_start),
8557 pa_end - pa_start, prot, mode,
8561 /* Start physical address run. */
8562 pa_start = *pde & PG_PS_FRAME;
8563 pa_end = pa_start + NBPDR;
8566 tmpva = trunc_2mpage(tmpva) + NBPDR;
8568 pte = pmap_pde_to_pte(pde, tmpva);
8569 if ((*pte & pte_mask) != pte_bits) {
8570 pmap_pte_props(pte, pte_bits, pte_mask);
8573 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
8574 (*pte & PG_FRAME) < dmaplimit) {
8575 if (pa_start == pa_end) {
8576 /* Start physical address run. */
8577 pa_start = *pte & PG_FRAME;
8578 pa_end = pa_start + PAGE_SIZE;
8579 } else if (pa_end == (*pte & PG_FRAME))
8580 pa_end += PAGE_SIZE;
8582 /* Run ended, update direct map. */
8583 error = pmap_change_props_locked(
8584 PHYS_TO_DMAP(pa_start),
8585 pa_end - pa_start, prot, mode,
8589 /* Start physical address run. */
8590 pa_start = *pte & PG_FRAME;
8591 pa_end = pa_start + PAGE_SIZE;
8597 if (error == 0 && pa_start != pa_end && pa_start < dmaplimit) {
8598 pa_end1 = MIN(pa_end, dmaplimit);
8599 if (pa_start != pa_end1)
8600 error = pmap_change_props_locked(PHYS_TO_DMAP(pa_start),
8601 pa_end1 - pa_start, prot, mode, flags);
8605 * Flush CPU caches if required to make sure any data isn't cached that
8606 * shouldn't be, etc.
8609 pmap_invalidate_range(kernel_pmap, base, tmpva);
8610 if ((flags & MAPDEV_FLUSHCACHE) != 0)
8611 pmap_invalidate_cache_range(base, tmpva);
8617 * Demotes any mapping within the direct map region that covers more than the
8618 * specified range of physical addresses. This range's size must be a power
8619 * of two and its starting address must be a multiple of its size. Since the
8620 * demotion does not change any attributes of the mapping, a TLB invalidation
8621 * is not mandatory. The caller may, however, request a TLB invalidation.
8624 pmap_demote_DMAP(vm_paddr_t base, vm_size_t len, boolean_t invalidate)
8633 KASSERT(powerof2(len), ("pmap_demote_DMAP: len is not a power of 2"));
8634 KASSERT((base & (len - 1)) == 0,
8635 ("pmap_demote_DMAP: base is not a multiple of len"));
8636 if (len < NBPDP && base < dmaplimit) {
8637 va = PHYS_TO_DMAP(base);
8639 PMAP_LOCK(kernel_pmap);
8640 pdpe = pmap_pdpe(kernel_pmap, va);
8641 if ((*pdpe & X86_PG_V) == 0)
8642 panic("pmap_demote_DMAP: invalid PDPE");
8643 if ((*pdpe & PG_PS) != 0) {
8644 if (!pmap_demote_pdpe(kernel_pmap, pdpe, va))
8645 panic("pmap_demote_DMAP: PDPE failed");
8649 pde = pmap_pdpe_to_pde(pdpe, va);
8650 if ((*pde & X86_PG_V) == 0)
8651 panic("pmap_demote_DMAP: invalid PDE");
8652 if ((*pde & PG_PS) != 0) {
8653 if (!pmap_demote_pde(kernel_pmap, pde, va))
8654 panic("pmap_demote_DMAP: PDE failed");
8658 if (changed && invalidate)
8659 pmap_invalidate_page(kernel_pmap, va);
8660 PMAP_UNLOCK(kernel_pmap);
8665 * Perform the pmap work for mincore(2). If the page is not both referenced and
8666 * modified by this pmap, returns its physical address so that the caller can
8667 * find other mappings.
8670 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *pap)
8673 pt_entry_t pte, PG_A, PG_M, PG_RW, PG_V;
8677 PG_A = pmap_accessed_bit(pmap);
8678 PG_M = pmap_modified_bit(pmap);
8679 PG_V = pmap_valid_bit(pmap);
8680 PG_RW = pmap_rw_bit(pmap);
8683 pdep = pmap_pde(pmap, addr);
8684 if (pdep != NULL && (*pdep & PG_V)) {
8685 if (*pdep & PG_PS) {
8687 /* Compute the physical address of the 4KB page. */
8688 pa = ((*pdep & PG_PS_FRAME) | (addr & PDRMASK)) &
8690 val = MINCORE_SUPER;
8692 pte = *pmap_pde_to_pte(pdep, addr);
8693 pa = pte & PG_FRAME;
8701 if ((pte & PG_V) != 0) {
8702 val |= MINCORE_INCORE;
8703 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
8704 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
8705 if ((pte & PG_A) != 0)
8706 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
8708 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
8709 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) &&
8710 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) {
8718 pmap_pcid_alloc(pmap_t pmap, u_int cpuid)
8720 uint32_t gen, new_gen, pcid_next;
8722 CRITICAL_ASSERT(curthread);
8723 gen = PCPU_GET(pcid_gen);
8724 if (pmap->pm_pcids[cpuid].pm_pcid == PMAP_PCID_KERN)
8725 return (pti ? 0 : CR3_PCID_SAVE);
8726 if (pmap->pm_pcids[cpuid].pm_gen == gen)
8727 return (CR3_PCID_SAVE);
8728 pcid_next = PCPU_GET(pcid_next);
8729 KASSERT((!pti && pcid_next <= PMAP_PCID_OVERMAX) ||
8730 (pti && pcid_next <= PMAP_PCID_OVERMAX_KERN),
8731 ("cpu %d pcid_next %#x", cpuid, pcid_next));
8732 if ((!pti && pcid_next == PMAP_PCID_OVERMAX) ||
8733 (pti && pcid_next == PMAP_PCID_OVERMAX_KERN)) {
8737 PCPU_SET(pcid_gen, new_gen);
8738 pcid_next = PMAP_PCID_KERN + 1;
8742 pmap->pm_pcids[cpuid].pm_pcid = pcid_next;
8743 pmap->pm_pcids[cpuid].pm_gen = new_gen;
8744 PCPU_SET(pcid_next, pcid_next + 1);
8749 pmap_pcid_alloc_checked(pmap_t pmap, u_int cpuid)
8753 cached = pmap_pcid_alloc(pmap, cpuid);
8754 KASSERT(pmap->pm_pcids[cpuid].pm_pcid < PMAP_PCID_OVERMAX,
8755 ("pmap %p cpu %d pcid %#x", pmap, cpuid,
8756 pmap->pm_pcids[cpuid].pm_pcid));
8757 KASSERT(pmap->pm_pcids[cpuid].pm_pcid != PMAP_PCID_KERN ||
8758 pmap == kernel_pmap,
8759 ("non-kernel pmap pmap %p cpu %d pcid %#x",
8760 pmap, cpuid, pmap->pm_pcids[cpuid].pm_pcid));
8765 pmap_activate_sw_pti_post(struct thread *td, pmap_t pmap)
8768 PCPU_GET(tssp)->tss_rsp0 = pmap->pm_ucr3 != PMAP_NO_CR3 ?
8769 PCPU_GET(pti_rsp0) : (uintptr_t)td->td_md.md_stack_base;
8773 pmap_activate_sw_pcid_pti(pmap_t pmap, u_int cpuid, const bool invpcid_works1)
8775 struct invpcid_descr d;
8776 uint64_t cached, cr3, kcr3, ucr3;
8778 cached = pmap_pcid_alloc_checked(pmap, cpuid);
8780 if ((cr3 & ~CR3_PCID_MASK) != pmap->pm_cr3)
8781 load_cr3(pmap->pm_cr3 | pmap->pm_pcids[cpuid].pm_pcid);
8782 PCPU_SET(curpmap, pmap);
8783 kcr3 = pmap->pm_cr3 | pmap->pm_pcids[cpuid].pm_pcid;
8784 ucr3 = pmap->pm_ucr3 | pmap->pm_pcids[cpuid].pm_pcid |
8787 if (!cached && pmap->pm_ucr3 != PMAP_NO_CR3) {
8789 * Explicitly invalidate translations cached from the
8790 * user page table. They are not automatically
8791 * flushed by reload of cr3 with the kernel page table
8794 * Note that the if() condition is resolved statically
8795 * by using the function argument instead of
8796 * runtime-evaluated invpcid_works value.
8798 if (invpcid_works1) {
8799 d.pcid = PMAP_PCID_USER_PT |
8800 pmap->pm_pcids[cpuid].pm_pcid;
8803 invpcid(&d, INVPCID_CTX);
8805 pmap_pti_pcid_invalidate(ucr3, kcr3);
8809 PCPU_SET(kcr3, kcr3 | CR3_PCID_SAVE);
8810 PCPU_SET(ucr3, ucr3 | CR3_PCID_SAVE);
8812 PCPU_INC(pm_save_cnt);
8816 pmap_activate_sw_pcid_invpcid_pti(struct thread *td, pmap_t pmap, u_int cpuid)
8819 pmap_activate_sw_pcid_pti(pmap, cpuid, true);
8820 pmap_activate_sw_pti_post(td, pmap);
8824 pmap_activate_sw_pcid_noinvpcid_pti(struct thread *td, pmap_t pmap,
8830 * If the INVPCID instruction is not available,
8831 * invltlb_pcid_handler() is used to handle an invalidate_all
8832 * IPI, which checks for curpmap == smp_tlb_pmap. The below
8833 * sequence of operations has a window where %CR3 is loaded
8834 * with the new pmap's PML4 address, but the curpmap value has
8835 * not yet been updated. This causes the invltlb IPI handler,
8836 * which is called between the updates, to execute as a NOP,
8837 * which leaves stale TLB entries.
8839 * Note that the most typical use of pmap_activate_sw(), from
8840 * the context switch, is immune to this race, because
8841 * interrupts are disabled (while the thread lock is owned),
8842 * and the IPI happens after curpmap is updated. Protect
8843 * other callers in a similar way, by disabling interrupts
8844 * around the %cr3 register reload and curpmap assignment.
8846 rflags = intr_disable();
8847 pmap_activate_sw_pcid_pti(pmap, cpuid, false);
8848 intr_restore(rflags);
8849 pmap_activate_sw_pti_post(td, pmap);
8853 pmap_activate_sw_pcid_nopti(struct thread *td __unused, pmap_t pmap,
8856 uint64_t cached, cr3;
8858 cached = pmap_pcid_alloc_checked(pmap, cpuid);
8860 if (!cached || (cr3 & ~CR3_PCID_MASK) != pmap->pm_cr3)
8861 load_cr3(pmap->pm_cr3 | pmap->pm_pcids[cpuid].pm_pcid |
8863 PCPU_SET(curpmap, pmap);
8865 PCPU_INC(pm_save_cnt);
8869 pmap_activate_sw_pcid_noinvpcid_nopti(struct thread *td __unused, pmap_t pmap,
8874 rflags = intr_disable();
8875 pmap_activate_sw_pcid_nopti(td, pmap, cpuid);
8876 intr_restore(rflags);
8880 pmap_activate_sw_nopcid_nopti(struct thread *td __unused, pmap_t pmap,
8881 u_int cpuid __unused)
8884 load_cr3(pmap->pm_cr3);
8885 PCPU_SET(curpmap, pmap);
8889 pmap_activate_sw_nopcid_pti(struct thread *td, pmap_t pmap,
8890 u_int cpuid __unused)
8893 pmap_activate_sw_nopcid_nopti(td, pmap, cpuid);
8894 PCPU_SET(kcr3, pmap->pm_cr3);
8895 PCPU_SET(ucr3, pmap->pm_ucr3);
8896 pmap_activate_sw_pti_post(td, pmap);
8899 DEFINE_IFUNC(static, void, pmap_activate_sw_mode, (struct thread *, pmap_t,
8903 if (pmap_pcid_enabled && pti && invpcid_works)
8904 return (pmap_activate_sw_pcid_invpcid_pti);
8905 else if (pmap_pcid_enabled && pti && !invpcid_works)
8906 return (pmap_activate_sw_pcid_noinvpcid_pti);
8907 else if (pmap_pcid_enabled && !pti && invpcid_works)
8908 return (pmap_activate_sw_pcid_nopti);
8909 else if (pmap_pcid_enabled && !pti && !invpcid_works)
8910 return (pmap_activate_sw_pcid_noinvpcid_nopti);
8911 else if (!pmap_pcid_enabled && pti)
8912 return (pmap_activate_sw_nopcid_pti);
8913 else /* if (!pmap_pcid_enabled && !pti) */
8914 return (pmap_activate_sw_nopcid_nopti);
8918 pmap_activate_sw(struct thread *td)
8920 pmap_t oldpmap, pmap;
8923 oldpmap = PCPU_GET(curpmap);
8924 pmap = vmspace_pmap(td->td_proc->p_vmspace);
8925 if (oldpmap == pmap) {
8926 if (cpu_vendor_id != CPU_VENDOR_INTEL)
8930 cpuid = PCPU_GET(cpuid);
8932 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
8934 CPU_SET(cpuid, &pmap->pm_active);
8936 pmap_activate_sw_mode(td, pmap, cpuid);
8938 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
8940 CPU_CLR(cpuid, &oldpmap->pm_active);
8945 pmap_activate(struct thread *td)
8949 pmap_activate_sw(td);
8954 pmap_activate_boot(pmap_t pmap)
8960 * kernel_pmap must be never deactivated, and we ensure that
8961 * by never activating it at all.
8963 MPASS(pmap != kernel_pmap);
8965 cpuid = PCPU_GET(cpuid);
8967 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
8969 CPU_SET(cpuid, &pmap->pm_active);
8971 PCPU_SET(curpmap, pmap);
8973 kcr3 = pmap->pm_cr3;
8974 if (pmap_pcid_enabled)
8975 kcr3 |= pmap->pm_pcids[cpuid].pm_pcid | CR3_PCID_SAVE;
8979 PCPU_SET(kcr3, kcr3);
8980 PCPU_SET(ucr3, PMAP_NO_CR3);
8984 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
8989 * Increase the starting virtual address of the given mapping if a
8990 * different alignment might result in more superpage mappings.
8993 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
8994 vm_offset_t *addr, vm_size_t size)
8996 vm_offset_t superpage_offset;
9000 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
9001 offset += ptoa(object->pg_color);
9002 superpage_offset = offset & PDRMASK;
9003 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR ||
9004 (*addr & PDRMASK) == superpage_offset)
9006 if ((*addr & PDRMASK) < superpage_offset)
9007 *addr = (*addr & ~PDRMASK) + superpage_offset;
9009 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset;
9013 static unsigned long num_dirty_emulations;
9014 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_dirty_emulations, CTLFLAG_RW,
9015 &num_dirty_emulations, 0, NULL);
9017 static unsigned long num_accessed_emulations;
9018 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_accessed_emulations, CTLFLAG_RW,
9019 &num_accessed_emulations, 0, NULL);
9021 static unsigned long num_superpage_accessed_emulations;
9022 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_superpage_accessed_emulations, CTLFLAG_RW,
9023 &num_superpage_accessed_emulations, 0, NULL);
9025 static unsigned long ad_emulation_superpage_promotions;
9026 SYSCTL_ULONG(_vm_pmap, OID_AUTO, ad_emulation_superpage_promotions, CTLFLAG_RW,
9027 &ad_emulation_superpage_promotions, 0, NULL);
9028 #endif /* INVARIANTS */
9031 pmap_emulate_accessed_dirty(pmap_t pmap, vm_offset_t va, int ftype)
9034 struct rwlock *lock;
9035 #if VM_NRESERVLEVEL > 0
9039 pt_entry_t *pte, PG_A, PG_M, PG_RW, PG_V;
9041 KASSERT(ftype == VM_PROT_READ || ftype == VM_PROT_WRITE,
9042 ("pmap_emulate_accessed_dirty: invalid fault type %d", ftype));
9044 if (!pmap_emulate_ad_bits(pmap))
9047 PG_A = pmap_accessed_bit(pmap);
9048 PG_M = pmap_modified_bit(pmap);
9049 PG_V = pmap_valid_bit(pmap);
9050 PG_RW = pmap_rw_bit(pmap);
9056 pde = pmap_pde(pmap, va);
9057 if (pde == NULL || (*pde & PG_V) == 0)
9060 if ((*pde & PG_PS) != 0) {
9061 if (ftype == VM_PROT_READ) {
9063 atomic_add_long(&num_superpage_accessed_emulations, 1);
9071 pte = pmap_pde_to_pte(pde, va);
9072 if ((*pte & PG_V) == 0)
9075 if (ftype == VM_PROT_WRITE) {
9076 if ((*pte & PG_RW) == 0)
9079 * Set the modified and accessed bits simultaneously.
9081 * Intel EPT PTEs that do software emulation of A/D bits map
9082 * PG_A and PG_M to EPT_PG_READ and EPT_PG_WRITE respectively.
9083 * An EPT misconfiguration is triggered if the PTE is writable
9084 * but not readable (WR=10). This is avoided by setting PG_A
9085 * and PG_M simultaneously.
9087 *pte |= PG_M | PG_A;
9092 #if VM_NRESERVLEVEL > 0
9093 /* try to promote the mapping */
9094 if (va < VM_MAXUSER_ADDRESS)
9095 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
9099 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
9101 if ((mpte == NULL || mpte->ref_count == NPTEPG) &&
9102 pmap_ps_enabled(pmap) &&
9103 (m->flags & PG_FICTITIOUS) == 0 &&
9104 vm_reserv_level_iffullpop(m) == 0) {
9105 pmap_promote_pde(pmap, pde, va, &lock);
9107 atomic_add_long(&ad_emulation_superpage_promotions, 1);
9113 if (ftype == VM_PROT_WRITE)
9114 atomic_add_long(&num_dirty_emulations, 1);
9116 atomic_add_long(&num_accessed_emulations, 1);
9118 rv = 0; /* success */
9127 pmap_get_mapping(pmap_t pmap, vm_offset_t va, uint64_t *ptr, int *num)
9132 pt_entry_t *pte, PG_V;
9136 PG_V = pmap_valid_bit(pmap);
9139 pml4 = pmap_pml4e(pmap, va);
9141 if ((*pml4 & PG_V) == 0)
9144 pdp = pmap_pml4e_to_pdpe(pml4, va);
9146 if ((*pdp & PG_V) == 0 || (*pdp & PG_PS) != 0)
9149 pde = pmap_pdpe_to_pde(pdp, va);
9151 if ((*pde & PG_V) == 0 || (*pde & PG_PS) != 0)
9154 pte = pmap_pde_to_pte(pde, va);
9163 * Get the kernel virtual address of a set of physical pages. If there are
9164 * physical addresses not covered by the DMAP perform a transient mapping
9165 * that will be removed when calling pmap_unmap_io_transient.
9167 * \param page The pages the caller wishes to obtain the virtual
9168 * address on the kernel memory map.
9169 * \param vaddr On return contains the kernel virtual memory address
9170 * of the pages passed in the page parameter.
9171 * \param count Number of pages passed in.
9172 * \param can_fault TRUE if the thread using the mapped pages can take
9173 * page faults, FALSE otherwise.
9175 * \returns TRUE if the caller must call pmap_unmap_io_transient when
9176 * finished or FALSE otherwise.
9180 pmap_map_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
9181 boolean_t can_fault)
9184 boolean_t needs_mapping;
9186 int cache_bits, error __unused, i;
9189 * Allocate any KVA space that we need, this is done in a separate
9190 * loop to prevent calling vmem_alloc while pinned.
9192 needs_mapping = FALSE;
9193 for (i = 0; i < count; i++) {
9194 paddr = VM_PAGE_TO_PHYS(page[i]);
9195 if (__predict_false(paddr >= dmaplimit)) {
9196 error = vmem_alloc(kernel_arena, PAGE_SIZE,
9197 M_BESTFIT | M_WAITOK, &vaddr[i]);
9198 KASSERT(error == 0, ("vmem_alloc failed: %d", error));
9199 needs_mapping = TRUE;
9201 vaddr[i] = PHYS_TO_DMAP(paddr);
9205 /* Exit early if everything is covered by the DMAP */
9210 * NB: The sequence of updating a page table followed by accesses
9211 * to the corresponding pages used in the !DMAP case is subject to
9212 * the situation described in the "AMD64 Architecture Programmer's
9213 * Manual Volume 2: System Programming" rev. 3.23, "7.3.1 Special
9214 * Coherency Considerations". Therefore, issuing the INVLPG right
9215 * after modifying the PTE bits is crucial.
9219 for (i = 0; i < count; i++) {
9220 paddr = VM_PAGE_TO_PHYS(page[i]);
9221 if (paddr >= dmaplimit) {
9224 * Slow path, since we can get page faults
9225 * while mappings are active don't pin the
9226 * thread to the CPU and instead add a global
9227 * mapping visible to all CPUs.
9229 pmap_qenter(vaddr[i], &page[i], 1);
9231 pte = vtopte(vaddr[i]);
9232 cache_bits = pmap_cache_bits(kernel_pmap,
9233 page[i]->md.pat_mode, 0);
9234 pte_store(pte, paddr | X86_PG_RW | X86_PG_V |
9241 return (needs_mapping);
9245 pmap_unmap_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
9246 boolean_t can_fault)
9253 for (i = 0; i < count; i++) {
9254 paddr = VM_PAGE_TO_PHYS(page[i]);
9255 if (paddr >= dmaplimit) {
9257 pmap_qremove(vaddr[i], 1);
9258 vmem_free(kernel_arena, vaddr[i], PAGE_SIZE);
9264 pmap_quick_enter_page(vm_page_t m)
9268 paddr = VM_PAGE_TO_PHYS(m);
9269 if (paddr < dmaplimit)
9270 return (PHYS_TO_DMAP(paddr));
9271 mtx_lock_spin(&qframe_mtx);
9272 KASSERT(*vtopte(qframe) == 0, ("qframe busy"));
9273 pte_store(vtopte(qframe), paddr | X86_PG_RW | X86_PG_V | X86_PG_A |
9274 X86_PG_M | pmap_cache_bits(kernel_pmap, m->md.pat_mode, 0));
9279 pmap_quick_remove_page(vm_offset_t addr)
9284 pte_store(vtopte(qframe), 0);
9286 mtx_unlock_spin(&qframe_mtx);
9290 * Pdp pages from the large map are managed differently from either
9291 * kernel or user page table pages. They are permanently allocated at
9292 * initialization time, and their reference count is permanently set to
9293 * zero. The pml4 entries pointing to those pages are copied into
9294 * each allocated pmap.
9296 * In contrast, pd and pt pages are managed like user page table
9297 * pages. They are dynamically allocated, and their reference count
9298 * represents the number of valid entries within the page.
9301 pmap_large_map_getptp_unlocked(void)
9305 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
9307 if (m != NULL && (m->flags & PG_ZERO) == 0)
9313 pmap_large_map_getptp(void)
9317 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
9318 m = pmap_large_map_getptp_unlocked();
9320 PMAP_UNLOCK(kernel_pmap);
9322 PMAP_LOCK(kernel_pmap);
9323 /* Callers retry. */
9328 static pdp_entry_t *
9329 pmap_large_map_pdpe(vm_offset_t va)
9331 vm_pindex_t pml4_idx;
9334 pml4_idx = pmap_pml4e_index(va);
9335 KASSERT(LMSPML4I <= pml4_idx && pml4_idx < LMSPML4I + lm_ents,
9336 ("pmap_large_map_pdpe: va %#jx out of range idx %#jx LMSPML4I "
9338 (uintmax_t)va, (uintmax_t)pml4_idx, LMSPML4I, lm_ents));
9339 KASSERT((kernel_pmap->pm_pml4[pml4_idx] & X86_PG_V) != 0,
9340 ("pmap_large_map_pdpe: invalid pml4 for va %#jx idx %#jx "
9341 "LMSPML4I %#jx lm_ents %d",
9342 (uintmax_t)va, (uintmax_t)pml4_idx, LMSPML4I, lm_ents));
9343 mphys = kernel_pmap->pm_pml4[pml4_idx] & PG_FRAME;
9344 return ((pdp_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pdpe_index(va));
9348 pmap_large_map_pde(vm_offset_t va)
9355 pdpe = pmap_large_map_pdpe(va);
9357 m = pmap_large_map_getptp();
9360 mphys = VM_PAGE_TO_PHYS(m);
9361 *pdpe = mphys | X86_PG_A | X86_PG_RW | X86_PG_V | pg_nx;
9363 MPASS((*pdpe & X86_PG_PS) == 0);
9364 mphys = *pdpe & PG_FRAME;
9366 return ((pd_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pde_index(va));
9370 pmap_large_map_pte(vm_offset_t va)
9377 pde = pmap_large_map_pde(va);
9379 m = pmap_large_map_getptp();
9382 mphys = VM_PAGE_TO_PHYS(m);
9383 *pde = mphys | X86_PG_A | X86_PG_RW | X86_PG_V | pg_nx;
9384 PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pde))->ref_count++;
9386 MPASS((*pde & X86_PG_PS) == 0);
9387 mphys = *pde & PG_FRAME;
9389 return ((pt_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pte_index(va));
9393 pmap_large_map_kextract(vm_offset_t va)
9395 pdp_entry_t *pdpe, pdp;
9396 pd_entry_t *pde, pd;
9397 pt_entry_t *pte, pt;
9399 KASSERT(PMAP_ADDRESS_IN_LARGEMAP(va),
9400 ("not largemap range %#lx", (u_long)va));
9401 pdpe = pmap_large_map_pdpe(va);
9403 KASSERT((pdp & X86_PG_V) != 0,
9404 ("invalid pdp va %#lx pdpe %#lx pdp %#lx", va,
9405 (u_long)pdpe, pdp));
9406 if ((pdp & X86_PG_PS) != 0) {
9407 KASSERT((amd_feature & AMDID_PAGE1GB) != 0,
9408 ("no 1G pages, va %#lx pdpe %#lx pdp %#lx", va,
9409 (u_long)pdpe, pdp));
9410 return ((pdp & PG_PS_PDP_FRAME) | (va & PDPMASK));
9412 pde = pmap_pdpe_to_pde(pdpe, va);
9414 KASSERT((pd & X86_PG_V) != 0,
9415 ("invalid pd va %#lx pde %#lx pd %#lx", va, (u_long)pde, pd));
9416 if ((pd & X86_PG_PS) != 0)
9417 return ((pd & PG_PS_FRAME) | (va & PDRMASK));
9418 pte = pmap_pde_to_pte(pde, va);
9420 KASSERT((pt & X86_PG_V) != 0,
9421 ("invalid pte va %#lx pte %#lx pt %#lx", va, (u_long)pte, pt));
9422 return ((pt & PG_FRAME) | (va & PAGE_MASK));
9426 pmap_large_map_getva(vm_size_t len, vm_offset_t align, vm_offset_t phase,
9427 vmem_addr_t *vmem_res)
9431 * Large mappings are all but static. Consequently, there
9432 * is no point in waiting for an earlier allocation to be
9435 return (vmem_xalloc(large_vmem, len, align, phase, 0, VMEM_ADDR_MIN,
9436 VMEM_ADDR_MAX, M_NOWAIT | M_BESTFIT, vmem_res));
9440 pmap_large_map(vm_paddr_t spa, vm_size_t len, void **addr,
9446 vm_offset_t va, inc;
9447 vmem_addr_t vmem_res;
9451 if (len == 0 || spa + len < spa)
9454 /* See if DMAP can serve. */
9455 if (spa + len <= dmaplimit) {
9456 va = PHYS_TO_DMAP(spa);
9458 return (pmap_change_attr(va, len, mattr));
9462 * No, allocate KVA. Fit the address with best possible
9463 * alignment for superpages. Fall back to worse align if
9467 if ((amd_feature & AMDID_PAGE1GB) != 0 && rounddown2(spa + len,
9468 NBPDP) >= roundup2(spa, NBPDP) + NBPDP)
9469 error = pmap_large_map_getva(len, NBPDP, spa & PDPMASK,
9471 if (error != 0 && rounddown2(spa + len, NBPDR) >= roundup2(spa,
9473 error = pmap_large_map_getva(len, NBPDR, spa & PDRMASK,
9476 error = pmap_large_map_getva(len, PAGE_SIZE, 0, &vmem_res);
9481 * Fill pagetable. PG_M is not pre-set, we scan modified bits
9482 * in the pagetable to minimize flushing. No need to
9483 * invalidate TLB, since we only update invalid entries.
9485 PMAP_LOCK(kernel_pmap);
9486 for (pa = spa, va = vmem_res; len > 0; pa += inc, va += inc,
9488 if ((amd_feature & AMDID_PAGE1GB) != 0 && len >= NBPDP &&
9489 (pa & PDPMASK) == 0 && (va & PDPMASK) == 0) {
9490 pdpe = pmap_large_map_pdpe(va);
9492 *pdpe = pa | pg_g | X86_PG_PS | X86_PG_RW |
9493 X86_PG_V | X86_PG_A | pg_nx |
9494 pmap_cache_bits(kernel_pmap, mattr, TRUE);
9496 } else if (len >= NBPDR && (pa & PDRMASK) == 0 &&
9497 (va & PDRMASK) == 0) {
9498 pde = pmap_large_map_pde(va);
9500 *pde = pa | pg_g | X86_PG_PS | X86_PG_RW |
9501 X86_PG_V | X86_PG_A | pg_nx |
9502 pmap_cache_bits(kernel_pmap, mattr, TRUE);
9503 PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pde))->
9507 pte = pmap_large_map_pte(va);
9509 *pte = pa | pg_g | X86_PG_RW | X86_PG_V |
9510 X86_PG_A | pg_nx | pmap_cache_bits(kernel_pmap,
9512 PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pte))->
9517 PMAP_UNLOCK(kernel_pmap);
9520 *addr = (void *)vmem_res;
9525 pmap_large_unmap(void *svaa, vm_size_t len)
9527 vm_offset_t sva, va;
9529 pdp_entry_t *pdpe, pdp;
9530 pd_entry_t *pde, pd;
9533 struct spglist spgf;
9535 sva = (vm_offset_t)svaa;
9536 if (len == 0 || sva + len < sva || (sva >= DMAP_MIN_ADDRESS &&
9537 sva + len <= DMAP_MIN_ADDRESS + dmaplimit))
9541 KASSERT(PMAP_ADDRESS_IN_LARGEMAP(sva) &&
9542 PMAP_ADDRESS_IN_LARGEMAP(sva + len - 1),
9543 ("not largemap range %#lx %#lx", (u_long)svaa, (u_long)svaa + len));
9544 PMAP_LOCK(kernel_pmap);
9545 for (va = sva; va < sva + len; va += inc) {
9546 pdpe = pmap_large_map_pdpe(va);
9548 KASSERT((pdp & X86_PG_V) != 0,
9549 ("invalid pdp va %#lx pdpe %#lx pdp %#lx", va,
9550 (u_long)pdpe, pdp));
9551 if ((pdp & X86_PG_PS) != 0) {
9552 KASSERT((amd_feature & AMDID_PAGE1GB) != 0,
9553 ("no 1G pages, va %#lx pdpe %#lx pdp %#lx", va,
9554 (u_long)pdpe, pdp));
9555 KASSERT((va & PDPMASK) == 0,
9556 ("PDPMASK bit set, va %#lx pdpe %#lx pdp %#lx", va,
9557 (u_long)pdpe, pdp));
9558 KASSERT(va + NBPDP <= sva + len,
9559 ("unmap covers partial 1GB page, sva %#lx va %#lx "
9560 "pdpe %#lx pdp %#lx len %#lx", sva, va,
9561 (u_long)pdpe, pdp, len));
9566 pde = pmap_pdpe_to_pde(pdpe, va);
9568 KASSERT((pd & X86_PG_V) != 0,
9569 ("invalid pd va %#lx pde %#lx pd %#lx", va,
9571 if ((pd & X86_PG_PS) != 0) {
9572 KASSERT((va & PDRMASK) == 0,
9573 ("PDRMASK bit set, va %#lx pde %#lx pd %#lx", va,
9575 KASSERT(va + NBPDR <= sva + len,
9576 ("unmap covers partial 2MB page, sva %#lx va %#lx "
9577 "pde %#lx pd %#lx len %#lx", sva, va, (u_long)pde,
9581 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pde));
9583 if (m->ref_count == 0) {
9585 SLIST_INSERT_HEAD(&spgf, m, plinks.s.ss);
9589 pte = pmap_pde_to_pte(pde, va);
9590 KASSERT((*pte & X86_PG_V) != 0,
9591 ("invalid pte va %#lx pte %#lx pt %#lx", va,
9592 (u_long)pte, *pte));
9595 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pte));
9597 if (m->ref_count == 0) {
9599 SLIST_INSERT_HEAD(&spgf, m, plinks.s.ss);
9600 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pde));
9602 if (m->ref_count == 0) {
9604 SLIST_INSERT_HEAD(&spgf, m, plinks.s.ss);
9608 pmap_invalidate_range(kernel_pmap, sva, sva + len);
9609 PMAP_UNLOCK(kernel_pmap);
9610 vm_page_free_pages_toq(&spgf, false);
9611 vmem_free(large_vmem, sva, len);
9615 pmap_large_map_wb_fence_mfence(void)
9622 pmap_large_map_wb_fence_atomic(void)
9625 atomic_thread_fence_seq_cst();
9629 pmap_large_map_wb_fence_nop(void)
9633 DEFINE_IFUNC(static, void, pmap_large_map_wb_fence, (void))
9636 if (cpu_vendor_id != CPU_VENDOR_INTEL)
9637 return (pmap_large_map_wb_fence_mfence);
9638 else if ((cpu_stdext_feature & (CPUID_STDEXT_CLWB |
9639 CPUID_STDEXT_CLFLUSHOPT)) == 0)
9640 return (pmap_large_map_wb_fence_atomic);
9642 /* clflush is strongly enough ordered */
9643 return (pmap_large_map_wb_fence_nop);
9647 pmap_large_map_flush_range_clwb(vm_offset_t va, vm_size_t len)
9650 for (; len > 0; len -= cpu_clflush_line_size,
9651 va += cpu_clflush_line_size)
9656 pmap_large_map_flush_range_clflushopt(vm_offset_t va, vm_size_t len)
9659 for (; len > 0; len -= cpu_clflush_line_size,
9660 va += cpu_clflush_line_size)
9665 pmap_large_map_flush_range_clflush(vm_offset_t va, vm_size_t len)
9668 for (; len > 0; len -= cpu_clflush_line_size,
9669 va += cpu_clflush_line_size)
9674 pmap_large_map_flush_range_nop(vm_offset_t sva __unused, vm_size_t len __unused)
9678 DEFINE_IFUNC(static, void, pmap_large_map_flush_range, (vm_offset_t, vm_size_t))
9681 if ((cpu_stdext_feature & CPUID_STDEXT_CLWB) != 0)
9682 return (pmap_large_map_flush_range_clwb);
9683 else if ((cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0)
9684 return (pmap_large_map_flush_range_clflushopt);
9685 else if ((cpu_feature & CPUID_CLFSH) != 0)
9686 return (pmap_large_map_flush_range_clflush);
9688 return (pmap_large_map_flush_range_nop);
9692 pmap_large_map_wb_large(vm_offset_t sva, vm_offset_t eva)
9694 volatile u_long *pe;
9700 for (va = sva; va < eva; va += inc) {
9702 if ((amd_feature & AMDID_PAGE1GB) != 0) {
9703 pe = (volatile u_long *)pmap_large_map_pdpe(va);
9705 if ((p & X86_PG_PS) != 0)
9709 pe = (volatile u_long *)pmap_large_map_pde(va);
9711 if ((p & X86_PG_PS) != 0)
9715 pe = (volatile u_long *)pmap_large_map_pte(va);
9721 if ((p & X86_PG_AVAIL1) != 0) {
9723 * Spin-wait for the end of a parallel
9730 * If we saw other write-back
9731 * occuring, we cannot rely on PG_M to
9732 * indicate state of the cache. The
9733 * PG_M bit is cleared before the
9734 * flush to avoid ignoring new writes,
9735 * and writes which are relevant for
9736 * us might happen after.
9742 if ((p & X86_PG_M) != 0 || seen_other) {
9743 if (!atomic_fcmpset_long(pe, &p,
9744 (p & ~X86_PG_M) | X86_PG_AVAIL1))
9746 * If we saw PG_M without
9747 * PG_AVAIL1, and then on the
9748 * next attempt we do not
9749 * observe either PG_M or
9750 * PG_AVAIL1, the other
9751 * write-back started after us
9752 * and finished before us. We
9753 * can rely on it doing our
9757 pmap_large_map_flush_range(va, inc);
9758 atomic_clear_long(pe, X86_PG_AVAIL1);
9767 * Write-back cache lines for the given address range.
9769 * Must be called only on the range or sub-range returned from
9770 * pmap_large_map(). Must not be called on the coalesced ranges.
9772 * Does nothing on CPUs without CLWB, CLFLUSHOPT, or CLFLUSH
9773 * instructions support.
9776 pmap_large_map_wb(void *svap, vm_size_t len)
9778 vm_offset_t eva, sva;
9780 sva = (vm_offset_t)svap;
9782 pmap_large_map_wb_fence();
9783 if (sva >= DMAP_MIN_ADDRESS && eva <= DMAP_MIN_ADDRESS + dmaplimit) {
9784 pmap_large_map_flush_range(sva, len);
9786 KASSERT(sva >= LARGEMAP_MIN_ADDRESS &&
9787 eva <= LARGEMAP_MIN_ADDRESS + lm_ents * NBPML4,
9788 ("pmap_large_map_wb: not largemap %#lx %#lx", sva, len));
9789 pmap_large_map_wb_large(sva, eva);
9791 pmap_large_map_wb_fence();
9795 pmap_pti_alloc_page(void)
9799 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
9800 m = vm_page_grab(pti_obj, pti_pg_idx++, VM_ALLOC_NOBUSY |
9801 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
9806 pmap_pti_free_page(vm_page_t m)
9809 KASSERT(m->ref_count > 0, ("page %p not referenced", m));
9810 if (!vm_page_unwire_noq(m))
9812 vm_page_free_zero(m);
9826 pti_obj = vm_pager_allocate(OBJT_PHYS, NULL, 0, VM_PROT_ALL, 0, NULL);
9827 VM_OBJECT_WLOCK(pti_obj);
9828 pml4_pg = pmap_pti_alloc_page();
9829 pti_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4_pg));
9830 for (va = VM_MIN_KERNEL_ADDRESS; va <= VM_MAX_KERNEL_ADDRESS &&
9831 va >= VM_MIN_KERNEL_ADDRESS && va > NBPML4; va += NBPML4) {
9832 pdpe = pmap_pti_pdpe(va);
9833 pmap_pti_wire_pte(pdpe);
9835 pmap_pti_add_kva_locked((vm_offset_t)&__pcpu[0],
9836 (vm_offset_t)&__pcpu[0] + sizeof(__pcpu[0]) * MAXCPU, false);
9837 pmap_pti_add_kva_locked((vm_offset_t)idt, (vm_offset_t)idt +
9838 sizeof(struct gate_descriptor) * NIDT, false);
9840 /* Doublefault stack IST 1 */
9841 va = __pcpu[i].pc_common_tss.tss_ist1;
9842 pmap_pti_add_kva_locked(va - PAGE_SIZE, va, false);
9843 /* NMI stack IST 2 */
9844 va = __pcpu[i].pc_common_tss.tss_ist2 + sizeof(struct nmi_pcpu);
9845 pmap_pti_add_kva_locked(va - PAGE_SIZE, va, false);
9846 /* MC# stack IST 3 */
9847 va = __pcpu[i].pc_common_tss.tss_ist3 +
9848 sizeof(struct nmi_pcpu);
9849 pmap_pti_add_kva_locked(va - PAGE_SIZE, va, false);
9850 /* DB# stack IST 4 */
9851 va = __pcpu[i].pc_common_tss.tss_ist4 + sizeof(struct nmi_pcpu);
9852 pmap_pti_add_kva_locked(va - PAGE_SIZE, va, false);
9854 pmap_pti_add_kva_locked((vm_offset_t)kernphys + KERNBASE,
9855 (vm_offset_t)etext, true);
9856 pti_finalized = true;
9857 VM_OBJECT_WUNLOCK(pti_obj);
9859 SYSINIT(pmap_pti, SI_SUB_CPU + 1, SI_ORDER_ANY, pmap_pti_init, NULL);
9861 static pdp_entry_t *
9862 pmap_pti_pdpe(vm_offset_t va)
9864 pml4_entry_t *pml4e;
9867 vm_pindex_t pml4_idx;
9870 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
9872 pml4_idx = pmap_pml4e_index(va);
9873 pml4e = &pti_pml4[pml4_idx];
9877 panic("pml4 alloc after finalization\n");
9878 m = pmap_pti_alloc_page();
9880 pmap_pti_free_page(m);
9881 mphys = *pml4e & ~PAGE_MASK;
9883 mphys = VM_PAGE_TO_PHYS(m);
9884 *pml4e = mphys | X86_PG_RW | X86_PG_V;
9887 mphys = *pml4e & ~PAGE_MASK;
9889 pdpe = (pdp_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pdpe_index(va);
9894 pmap_pti_wire_pte(void *pte)
9898 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
9899 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pte));
9904 pmap_pti_unwire_pde(void *pde, bool only_ref)
9908 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
9909 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pde));
9910 MPASS(m->ref_count > 0);
9911 MPASS(only_ref || m->ref_count > 1);
9912 pmap_pti_free_page(m);
9916 pmap_pti_unwire_pte(void *pte, vm_offset_t va)
9921 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
9922 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pte));
9923 MPASS(m->ref_count > 0);
9924 if (pmap_pti_free_page(m)) {
9925 pde = pmap_pti_pde(va);
9926 MPASS((*pde & (X86_PG_PS | X86_PG_V)) == X86_PG_V);
9928 pmap_pti_unwire_pde(pde, false);
9933 pmap_pti_pde(vm_offset_t va)
9941 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
9943 pdpe = pmap_pti_pdpe(va);
9945 m = pmap_pti_alloc_page();
9947 pmap_pti_free_page(m);
9948 MPASS((*pdpe & X86_PG_PS) == 0);
9949 mphys = *pdpe & ~PAGE_MASK;
9951 mphys = VM_PAGE_TO_PHYS(m);
9952 *pdpe = mphys | X86_PG_RW | X86_PG_V;
9955 MPASS((*pdpe & X86_PG_PS) == 0);
9956 mphys = *pdpe & ~PAGE_MASK;
9959 pde = (pd_entry_t *)PHYS_TO_DMAP(mphys);
9960 pd_idx = pmap_pde_index(va);
9966 pmap_pti_pte(vm_offset_t va, bool *unwire_pde)
9973 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
9975 pde = pmap_pti_pde(va);
9976 if (unwire_pde != NULL) {
9978 pmap_pti_wire_pte(pde);
9981 m = pmap_pti_alloc_page();
9983 pmap_pti_free_page(m);
9984 MPASS((*pde & X86_PG_PS) == 0);
9985 mphys = *pde & ~(PAGE_MASK | pg_nx);
9987 mphys = VM_PAGE_TO_PHYS(m);
9988 *pde = mphys | X86_PG_RW | X86_PG_V;
9989 if (unwire_pde != NULL)
9990 *unwire_pde = false;
9993 MPASS((*pde & X86_PG_PS) == 0);
9994 mphys = *pde & ~(PAGE_MASK | pg_nx);
9997 pte = (pt_entry_t *)PHYS_TO_DMAP(mphys);
9998 pte += pmap_pte_index(va);
10004 pmap_pti_add_kva_locked(vm_offset_t sva, vm_offset_t eva, bool exec)
10008 pt_entry_t *pte, ptev;
10011 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
10013 sva = trunc_page(sva);
10014 MPASS(sva > VM_MAXUSER_ADDRESS);
10015 eva = round_page(eva);
10017 for (; sva < eva; sva += PAGE_SIZE) {
10018 pte = pmap_pti_pte(sva, &unwire_pde);
10019 pa = pmap_kextract(sva);
10020 ptev = pa | X86_PG_RW | X86_PG_V | X86_PG_A | X86_PG_G |
10021 (exec ? 0 : pg_nx) | pmap_cache_bits(kernel_pmap,
10022 VM_MEMATTR_DEFAULT, FALSE);
10024 pte_store(pte, ptev);
10025 pmap_pti_wire_pte(pte);
10027 KASSERT(!pti_finalized,
10028 ("pti overlap after fin %#lx %#lx %#lx",
10030 KASSERT(*pte == ptev,
10031 ("pti non-identical pte after fin %#lx %#lx %#lx",
10035 pde = pmap_pti_pde(sva);
10036 pmap_pti_unwire_pde(pde, true);
10042 pmap_pti_add_kva(vm_offset_t sva, vm_offset_t eva, bool exec)
10047 VM_OBJECT_WLOCK(pti_obj);
10048 pmap_pti_add_kva_locked(sva, eva, exec);
10049 VM_OBJECT_WUNLOCK(pti_obj);
10053 pmap_pti_remove_kva(vm_offset_t sva, vm_offset_t eva)
10060 sva = rounddown2(sva, PAGE_SIZE);
10061 MPASS(sva > VM_MAXUSER_ADDRESS);
10062 eva = roundup2(eva, PAGE_SIZE);
10064 VM_OBJECT_WLOCK(pti_obj);
10065 for (va = sva; va < eva; va += PAGE_SIZE) {
10066 pte = pmap_pti_pte(va, NULL);
10067 KASSERT((*pte & X86_PG_V) != 0,
10068 ("invalid pte va %#lx pte %#lx pt %#lx", va,
10069 (u_long)pte, *pte));
10071 pmap_pti_unwire_pte(pte, va);
10073 pmap_invalidate_range(kernel_pmap, sva, eva);
10074 VM_OBJECT_WUNLOCK(pti_obj);
10078 pkru_dup_range(void *ctx __unused, void *data)
10080 struct pmap_pkru_range *node, *new_node;
10082 new_node = uma_zalloc(pmap_pkru_ranges_zone, M_NOWAIT);
10083 if (new_node == NULL)
10086 memcpy(new_node, node, sizeof(*node));
10091 pkru_free_range(void *ctx __unused, void *node)
10094 uma_zfree(pmap_pkru_ranges_zone, node);
10098 pmap_pkru_assign(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, u_int keyidx,
10101 struct pmap_pkru_range *ppr;
10104 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
10105 MPASS(pmap->pm_type == PT_X86);
10106 MPASS((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0);
10107 if ((flags & AMD64_PKRU_EXCL) != 0 &&
10108 !rangeset_check_empty(&pmap->pm_pkru, sva, eva))
10110 ppr = uma_zalloc(pmap_pkru_ranges_zone, M_NOWAIT);
10113 ppr->pkru_keyidx = keyidx;
10114 ppr->pkru_flags = flags & AMD64_PKRU_PERSIST;
10115 error = rangeset_insert(&pmap->pm_pkru, sva, eva, ppr);
10117 uma_zfree(pmap_pkru_ranges_zone, ppr);
10122 pmap_pkru_deassign(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
10125 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
10126 MPASS(pmap->pm_type == PT_X86);
10127 MPASS((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0);
10128 return (rangeset_remove(&pmap->pm_pkru, sva, eva));
10132 pmap_pkru_deassign_all(pmap_t pmap)
10135 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
10136 if (pmap->pm_type == PT_X86 &&
10137 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0)
10138 rangeset_remove_all(&pmap->pm_pkru);
10142 pmap_pkru_same(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
10144 struct pmap_pkru_range *ppr, *prev_ppr;
10147 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
10148 if (pmap->pm_type != PT_X86 ||
10149 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0 ||
10150 sva >= VM_MAXUSER_ADDRESS)
10152 MPASS(eva <= VM_MAXUSER_ADDRESS);
10153 for (va = sva, prev_ppr = NULL; va < eva;) {
10154 ppr = rangeset_lookup(&pmap->pm_pkru, va);
10155 if ((ppr == NULL) ^ (prev_ppr == NULL))
10161 if (prev_ppr->pkru_keyidx != ppr->pkru_keyidx)
10163 va = ppr->pkru_rs_el.re_end;
10169 pmap_pkru_get(pmap_t pmap, vm_offset_t va)
10171 struct pmap_pkru_range *ppr;
10173 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
10174 if (pmap->pm_type != PT_X86 ||
10175 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0 ||
10176 va >= VM_MAXUSER_ADDRESS)
10178 ppr = rangeset_lookup(&pmap->pm_pkru, va);
10180 return (X86_PG_PKU(ppr->pkru_keyidx));
10185 pred_pkru_on_remove(void *ctx __unused, void *r)
10187 struct pmap_pkru_range *ppr;
10190 return ((ppr->pkru_flags & AMD64_PKRU_PERSIST) == 0);
10194 pmap_pkru_on_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
10197 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
10198 if (pmap->pm_type == PT_X86 &&
10199 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0) {
10200 rangeset_remove_pred(&pmap->pm_pkru, sva, eva,
10201 pred_pkru_on_remove);
10206 pmap_pkru_copy(pmap_t dst_pmap, pmap_t src_pmap)
10209 PMAP_LOCK_ASSERT(dst_pmap, MA_OWNED);
10210 PMAP_LOCK_ASSERT(src_pmap, MA_OWNED);
10211 MPASS(dst_pmap->pm_type == PT_X86);
10212 MPASS(src_pmap->pm_type == PT_X86);
10213 MPASS((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0);
10214 if (src_pmap->pm_pkru.rs_data_ctx == NULL)
10216 return (rangeset_copy(&dst_pmap->pm_pkru, &src_pmap->pm_pkru));
10220 pmap_pkru_update_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
10223 pml4_entry_t *pml4e;
10225 pd_entry_t newpde, ptpaddr, *pde;
10226 pt_entry_t newpte, *ptep, pte;
10227 vm_offset_t va, va_next;
10230 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
10231 MPASS(pmap->pm_type == PT_X86);
10232 MPASS(keyidx <= PMAP_MAX_PKRU_IDX);
10234 for (changed = false, va = sva; va < eva; va = va_next) {
10235 pml4e = pmap_pml4e(pmap, va);
10236 if ((*pml4e & X86_PG_V) == 0) {
10237 va_next = (va + NBPML4) & ~PML4MASK;
10243 pdpe = pmap_pml4e_to_pdpe(pml4e, va);
10244 if ((*pdpe & X86_PG_V) == 0) {
10245 va_next = (va + NBPDP) & ~PDPMASK;
10251 va_next = (va + NBPDR) & ~PDRMASK;
10255 pde = pmap_pdpe_to_pde(pdpe, va);
10260 MPASS((ptpaddr & X86_PG_V) != 0);
10261 if ((ptpaddr & PG_PS) != 0) {
10262 if (va + NBPDR == va_next && eva >= va_next) {
10263 newpde = (ptpaddr & ~X86_PG_PKU_MASK) |
10264 X86_PG_PKU(keyidx);
10265 if (newpde != ptpaddr) {
10270 } else if (!pmap_demote_pde(pmap, pde, va)) {
10278 for (ptep = pmap_pde_to_pte(pde, va); va != va_next;
10279 ptep++, va += PAGE_SIZE) {
10281 if ((pte & X86_PG_V) == 0)
10283 newpte = (pte & ~X86_PG_PKU_MASK) | X86_PG_PKU(keyidx);
10284 if (newpte != pte) {
10291 pmap_invalidate_range(pmap, sva, eva);
10295 pmap_pkru_check_uargs(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
10296 u_int keyidx, int flags)
10299 if (pmap->pm_type != PT_X86 || keyidx > PMAP_MAX_PKRU_IDX ||
10300 (flags & ~(AMD64_PKRU_PERSIST | AMD64_PKRU_EXCL)) != 0)
10302 if (eva <= sva || eva > VM_MAXUSER_ADDRESS)
10304 if ((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0)
10310 pmap_pkru_set(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, u_int keyidx,
10315 sva = trunc_page(sva);
10316 eva = round_page(eva);
10317 error = pmap_pkru_check_uargs(pmap, sva, eva, keyidx, flags);
10322 error = pmap_pkru_assign(pmap, sva, eva, keyidx, flags);
10324 pmap_pkru_update_range(pmap, sva, eva, keyidx);
10326 if (error != ENOMEM)
10334 pmap_pkru_clear(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
10338 sva = trunc_page(sva);
10339 eva = round_page(eva);
10340 error = pmap_pkru_check_uargs(pmap, sva, eva, 0, 0);
10345 error = pmap_pkru_deassign(pmap, sva, eva);
10347 pmap_pkru_update_range(pmap, sva, eva, 0);
10349 if (error != ENOMEM)
10357 * Track a range of the kernel's virtual address space that is contiguous
10358 * in various mapping attributes.
10360 struct pmap_kernel_map_range {
10369 sysctl_kmaps_dump(struct sbuf *sb, struct pmap_kernel_map_range *range,
10375 if (eva <= range->sva)
10378 pat_idx = pmap_pat_index(kernel_pmap, range->attrs, true);
10379 for (i = 0; i < PAT_INDEX_SIZE; i++)
10380 if (pat_index[i] == pat_idx)
10384 case PAT_WRITE_BACK:
10387 case PAT_WRITE_THROUGH:
10390 case PAT_UNCACHEABLE:
10396 case PAT_WRITE_PROTECTED:
10399 case PAT_WRITE_COMBINING:
10403 printf("%s: unknown PAT mode %#x for range 0x%016lx-0x%016lx\n",
10404 __func__, pat_idx, range->sva, eva);
10409 sbuf_printf(sb, "0x%016lx-0x%016lx r%c%c%c%c %s %d %d %d\n",
10411 (range->attrs & X86_PG_RW) != 0 ? 'w' : '-',
10412 (range->attrs & pg_nx) != 0 ? '-' : 'x',
10413 (range->attrs & X86_PG_U) != 0 ? 'u' : 's',
10414 (range->attrs & X86_PG_G) != 0 ? 'g' : '-',
10415 mode, range->pdpes, range->pdes, range->ptes);
10417 /* Reset to sentinel value. */
10418 range->sva = KVADDR(NPML4EPG - 1, NPDPEPG - 1, NPDEPG - 1, NPTEPG - 1);
10422 * Determine whether the attributes specified by a page table entry match those
10423 * being tracked by the current range. This is not quite as simple as a direct
10424 * flag comparison since some PAT modes have multiple representations.
10427 sysctl_kmaps_match(struct pmap_kernel_map_range *range, pt_entry_t attrs)
10429 pt_entry_t diff, mask;
10431 mask = X86_PG_G | X86_PG_RW | X86_PG_U | X86_PG_PDE_CACHE | pg_nx;
10432 diff = (range->attrs ^ attrs) & mask;
10435 if ((diff & ~X86_PG_PDE_PAT) == 0 &&
10436 pmap_pat_index(kernel_pmap, range->attrs, true) ==
10437 pmap_pat_index(kernel_pmap, attrs, true))
10443 sysctl_kmaps_reinit(struct pmap_kernel_map_range *range, vm_offset_t va,
10447 memset(range, 0, sizeof(*range));
10449 range->attrs = attrs;
10453 * Given a leaf PTE, derive the mapping's attributes. If they do not match
10454 * those of the current run, dump the address range and its attributes, and
10458 sysctl_kmaps_check(struct sbuf *sb, struct pmap_kernel_map_range *range,
10459 vm_offset_t va, pml4_entry_t pml4e, pdp_entry_t pdpe, pd_entry_t pde,
10464 attrs = pml4e & (X86_PG_RW | X86_PG_U | pg_nx);
10466 attrs |= pdpe & pg_nx;
10467 attrs &= pg_nx | (pdpe & (X86_PG_RW | X86_PG_U));
10468 if ((pdpe & PG_PS) != 0) {
10469 attrs |= pdpe & (X86_PG_G | X86_PG_PDE_CACHE);
10470 } else if (pde != 0) {
10471 attrs |= pde & pg_nx;
10472 attrs &= pg_nx | (pde & (X86_PG_RW | X86_PG_U));
10474 if ((pde & PG_PS) != 0) {
10475 attrs |= pde & (X86_PG_G | X86_PG_PDE_CACHE);
10476 } else if (pte != 0) {
10477 attrs |= pte & pg_nx;
10478 attrs &= pg_nx | (pte & (X86_PG_RW | X86_PG_U));
10479 attrs |= pte & (X86_PG_G | X86_PG_PTE_CACHE);
10481 /* Canonicalize by always using the PDE PAT bit. */
10482 if ((attrs & X86_PG_PTE_PAT) != 0)
10483 attrs ^= X86_PG_PDE_PAT | X86_PG_PTE_PAT;
10486 if (range->sva > va || !sysctl_kmaps_match(range, attrs)) {
10487 sysctl_kmaps_dump(sb, range, va);
10488 sysctl_kmaps_reinit(range, va, attrs);
10493 sysctl_kmaps(SYSCTL_HANDLER_ARGS)
10495 struct pmap_kernel_map_range range;
10496 struct sbuf sbuf, *sb;
10497 pml4_entry_t pml4e;
10498 pdp_entry_t *pdp, pdpe;
10499 pd_entry_t *pd, pde;
10500 pt_entry_t *pt, pte;
10503 int error, i, j, k, l;
10505 error = sysctl_wire_old_buffer(req, 0);
10509 sbuf_new_for_sysctl(sb, NULL, PAGE_SIZE, req);
10511 /* Sentinel value. */
10512 range.sva = KVADDR(NPML4EPG - 1, NPDPEPG - 1, NPDEPG - 1, NPTEPG - 1);
10515 * Iterate over the kernel page tables without holding the kernel pmap
10516 * lock. Outside of the large map, kernel page table pages are never
10517 * freed, so at worst we will observe inconsistencies in the output.
10518 * Within the large map, ensure that PDP and PD page addresses are
10519 * valid before descending.
10521 for (sva = 0, i = pmap_pml4e_index(sva); i < NPML4EPG; i++) {
10524 sbuf_printf(sb, "\nRecursive map:\n");
10527 sbuf_printf(sb, "\nDirect map:\n");
10530 sbuf_printf(sb, "\nKernel map:\n");
10533 sbuf_printf(sb, "\nLarge map:\n");
10537 /* Convert to canonical form. */
10538 if (sva == 1ul << 47)
10542 pml4e = kernel_pmap->pm_pml4[i];
10543 if ((pml4e & X86_PG_V) == 0) {
10544 sva = rounddown2(sva, NBPML4);
10545 sysctl_kmaps_dump(sb, &range, sva);
10549 pa = pml4e & PG_FRAME;
10550 pdp = (pdp_entry_t *)PHYS_TO_DMAP(pa);
10552 for (j = pmap_pdpe_index(sva); j < NPDPEPG; j++) {
10554 if ((pdpe & X86_PG_V) == 0) {
10555 sva = rounddown2(sva, NBPDP);
10556 sysctl_kmaps_dump(sb, &range, sva);
10560 pa = pdpe & PG_FRAME;
10561 if (PMAP_ADDRESS_IN_LARGEMAP(sva) &&
10562 vm_phys_paddr_to_vm_page(pa) == NULL)
10564 if ((pdpe & PG_PS) != 0) {
10565 sva = rounddown2(sva, NBPDP);
10566 sysctl_kmaps_check(sb, &range, sva, pml4e, pdpe,
10572 pd = (pd_entry_t *)PHYS_TO_DMAP(pa);
10574 for (k = pmap_pde_index(sva); k < NPDEPG; k++) {
10576 if ((pde & X86_PG_V) == 0) {
10577 sva = rounddown2(sva, NBPDR);
10578 sysctl_kmaps_dump(sb, &range, sva);
10582 pa = pde & PG_FRAME;
10583 if (PMAP_ADDRESS_IN_LARGEMAP(sva) &&
10584 vm_phys_paddr_to_vm_page(pa) == NULL)
10586 if ((pde & PG_PS) != 0) {
10587 sva = rounddown2(sva, NBPDR);
10588 sysctl_kmaps_check(sb, &range, sva,
10589 pml4e, pdpe, pde, 0);
10594 pt = (pt_entry_t *)PHYS_TO_DMAP(pa);
10596 for (l = pmap_pte_index(sva); l < NPTEPG; l++,
10597 sva += PAGE_SIZE) {
10599 if ((pte & X86_PG_V) == 0) {
10600 sysctl_kmaps_dump(sb, &range,
10604 sysctl_kmaps_check(sb, &range, sva,
10605 pml4e, pdpe, pde, pte);
10612 error = sbuf_finish(sb);
10616 SYSCTL_OID(_vm_pmap, OID_AUTO, kernel_maps,
10617 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE,
10618 NULL, 0, sysctl_kmaps, "A",
10619 "Dump kernel address layout");
10622 DB_SHOW_COMMAND(pte, pmap_print_pte)
10625 pml4_entry_t *pml4;
10628 pt_entry_t *pte, PG_V;
10632 db_printf("show pte addr\n");
10635 va = (vm_offset_t)addr;
10637 if (kdb_thread != NULL)
10638 pmap = vmspace_pmap(kdb_thread->td_proc->p_vmspace);
10640 pmap = PCPU_GET(curpmap);
10642 PG_V = pmap_valid_bit(pmap);
10643 pml4 = pmap_pml4e(pmap, va);
10644 db_printf("VA 0x%016lx pml4e 0x%016lx", va, *pml4);
10645 if ((*pml4 & PG_V) == 0) {
10649 pdp = pmap_pml4e_to_pdpe(pml4, va);
10650 db_printf(" pdpe 0x%016lx", *pdp);
10651 if ((*pdp & PG_V) == 0 || (*pdp & PG_PS) != 0) {
10655 pde = pmap_pdpe_to_pde(pdp, va);
10656 db_printf(" pde 0x%016lx", *pde);
10657 if ((*pde & PG_V) == 0 || (*pde & PG_PS) != 0) {
10661 pte = pmap_pde_to_pte(pde, va);
10662 db_printf(" pte 0x%016lx\n", *pte);
10665 DB_SHOW_COMMAND(phys2dmap, pmap_phys2dmap)
10670 a = (vm_paddr_t)addr;
10671 db_printf("0x%jx\n", (uintmax_t)PHYS_TO_DMAP(a));
10673 db_printf("show phys2dmap addr\n");