2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2011 NetApp, Inc.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
34 #include <sys/param.h>
35 #include <sys/systm.h>
37 #include <sys/kernel.h>
38 #include <sys/malloc.h>
41 #include <sys/sysctl.h>
46 #include <machine/psl.h>
47 #include <machine/cpufunc.h>
48 #include <machine/md_var.h>
49 #include <machine/reg.h>
50 #include <machine/segments.h>
51 #include <machine/smp.h>
52 #include <machine/specialreg.h>
53 #include <machine/vmparam.h>
55 #include <machine/vmm.h>
56 #include <machine/vmm_dev.h>
57 #include <machine/vmm_instruction_emul.h>
58 #include "vmm_lapic.h"
60 #include "vmm_ioport.h"
65 #include "vlapic_priv.h"
68 #include "vmx_cpufunc.h"
72 #include "vmx_controls.h"
74 #define PINBASED_CTLS_ONE_SETTING \
75 (PINBASED_EXTINT_EXITING | \
76 PINBASED_NMI_EXITING | \
78 #define PINBASED_CTLS_ZERO_SETTING 0
80 #define PROCBASED_CTLS_WINDOW_SETTING \
81 (PROCBASED_INT_WINDOW_EXITING | \
82 PROCBASED_NMI_WINDOW_EXITING)
84 #define PROCBASED_CTLS_ONE_SETTING \
85 (PROCBASED_SECONDARY_CONTROLS | \
86 PROCBASED_MWAIT_EXITING | \
87 PROCBASED_MONITOR_EXITING | \
88 PROCBASED_IO_EXITING | \
89 PROCBASED_MSR_BITMAPS | \
90 PROCBASED_CTLS_WINDOW_SETTING | \
91 PROCBASED_CR8_LOAD_EXITING | \
92 PROCBASED_CR8_STORE_EXITING)
93 #define PROCBASED_CTLS_ZERO_SETTING \
94 (PROCBASED_CR3_LOAD_EXITING | \
95 PROCBASED_CR3_STORE_EXITING | \
98 #define PROCBASED_CTLS2_ONE_SETTING PROCBASED2_ENABLE_EPT
99 #define PROCBASED_CTLS2_ZERO_SETTING 0
101 #define VM_EXIT_CTLS_ONE_SETTING \
102 (VM_EXIT_SAVE_DEBUG_CONTROLS | \
104 VM_EXIT_SAVE_EFER | \
105 VM_EXIT_LOAD_EFER | \
106 VM_EXIT_ACKNOWLEDGE_INTERRUPT)
108 #define VM_EXIT_CTLS_ZERO_SETTING 0
110 #define VM_ENTRY_CTLS_ONE_SETTING \
111 (VM_ENTRY_LOAD_DEBUG_CONTROLS | \
114 #define VM_ENTRY_CTLS_ZERO_SETTING \
115 (VM_ENTRY_INTO_SMM | \
116 VM_ENTRY_DEACTIVATE_DUAL_MONITOR)
121 static MALLOC_DEFINE(M_VMX, "vmx", "vmx");
122 static MALLOC_DEFINE(M_VLAPIC, "vlapic", "vlapic");
124 SYSCTL_DECL(_hw_vmm);
125 SYSCTL_NODE(_hw_vmm, OID_AUTO, vmx, CTLFLAG_RW, NULL, NULL);
127 int vmxon_enabled[MAXCPU];
128 static char vmxon_region[MAXCPU][PAGE_SIZE] __aligned(PAGE_SIZE);
130 static uint32_t pinbased_ctls, procbased_ctls, procbased_ctls2;
131 static uint32_t exit_ctls, entry_ctls;
133 static uint64_t cr0_ones_mask, cr0_zeros_mask;
134 SYSCTL_ULONG(_hw_vmm_vmx, OID_AUTO, cr0_ones_mask, CTLFLAG_RD,
135 &cr0_ones_mask, 0, NULL);
136 SYSCTL_ULONG(_hw_vmm_vmx, OID_AUTO, cr0_zeros_mask, CTLFLAG_RD,
137 &cr0_zeros_mask, 0, NULL);
139 static uint64_t cr4_ones_mask, cr4_zeros_mask;
140 SYSCTL_ULONG(_hw_vmm_vmx, OID_AUTO, cr4_ones_mask, CTLFLAG_RD,
141 &cr4_ones_mask, 0, NULL);
142 SYSCTL_ULONG(_hw_vmm_vmx, OID_AUTO, cr4_zeros_mask, CTLFLAG_RD,
143 &cr4_zeros_mask, 0, NULL);
145 static int vmx_initialized;
146 SYSCTL_INT(_hw_vmm_vmx, OID_AUTO, initialized, CTLFLAG_RD,
147 &vmx_initialized, 0, "Intel VMX initialized");
150 * Optional capabilities
152 static SYSCTL_NODE(_hw_vmm_vmx, OID_AUTO, cap, CTLFLAG_RW, NULL, NULL);
154 static int cap_halt_exit;
155 SYSCTL_INT(_hw_vmm_vmx_cap, OID_AUTO, halt_exit, CTLFLAG_RD, &cap_halt_exit, 0,
156 "HLT triggers a VM-exit");
158 static int cap_pause_exit;
159 SYSCTL_INT(_hw_vmm_vmx_cap, OID_AUTO, pause_exit, CTLFLAG_RD, &cap_pause_exit,
160 0, "PAUSE triggers a VM-exit");
162 static int cap_unrestricted_guest;
163 SYSCTL_INT(_hw_vmm_vmx_cap, OID_AUTO, unrestricted_guest, CTLFLAG_RD,
164 &cap_unrestricted_guest, 0, "Unrestricted guests");
166 static int cap_monitor_trap;
167 SYSCTL_INT(_hw_vmm_vmx_cap, OID_AUTO, monitor_trap, CTLFLAG_RD,
168 &cap_monitor_trap, 0, "Monitor trap flag");
170 static int cap_invpcid;
171 SYSCTL_INT(_hw_vmm_vmx_cap, OID_AUTO, invpcid, CTLFLAG_RD, &cap_invpcid,
172 0, "Guests are allowed to use INVPCID");
174 static int virtual_interrupt_delivery;
175 SYSCTL_INT(_hw_vmm_vmx_cap, OID_AUTO, virtual_interrupt_delivery, CTLFLAG_RD,
176 &virtual_interrupt_delivery, 0, "APICv virtual interrupt delivery support");
178 static int posted_interrupts;
179 SYSCTL_INT(_hw_vmm_vmx_cap, OID_AUTO, posted_interrupts, CTLFLAG_RD,
180 &posted_interrupts, 0, "APICv posted interrupt support");
182 static int pirvec = -1;
183 SYSCTL_INT(_hw_vmm_vmx, OID_AUTO, posted_interrupt_vector, CTLFLAG_RD,
184 &pirvec, 0, "APICv posted interrupt vector");
186 static struct unrhdr *vpid_unr;
187 static u_int vpid_alloc_failed;
188 SYSCTL_UINT(_hw_vmm_vmx, OID_AUTO, vpid_alloc_failed, CTLFLAG_RD,
189 &vpid_alloc_failed, 0, NULL);
191 static int guest_l1d_flush;
192 SYSCTL_INT(_hw_vmm_vmx, OID_AUTO, l1d_flush, CTLFLAG_RD,
193 &guest_l1d_flush, 0, NULL);
194 static int guest_l1d_flush_sw;
195 SYSCTL_INT(_hw_vmm_vmx, OID_AUTO, l1d_flush_sw, CTLFLAG_RD,
196 &guest_l1d_flush_sw, 0, NULL);
198 static struct msr_entry msr_load_list[1] __aligned(16);
201 * The definitions of SDT probes for VMX.
204 SDT_PROBE_DEFINE3(vmm, vmx, exit, entry,
205 "struct vmx *", "int", "struct vm_exit *");
207 SDT_PROBE_DEFINE4(vmm, vmx, exit, taskswitch,
208 "struct vmx *", "int", "struct vm_exit *", "struct vm_task_switch *");
210 SDT_PROBE_DEFINE4(vmm, vmx, exit, craccess,
211 "struct vmx *", "int", "struct vm_exit *", "uint64_t");
213 SDT_PROBE_DEFINE4(vmm, vmx, exit, rdmsr,
214 "struct vmx *", "int", "struct vm_exit *", "uint32_t");
216 SDT_PROBE_DEFINE5(vmm, vmx, exit, wrmsr,
217 "struct vmx *", "int", "struct vm_exit *", "uint32_t", "uint64_t");
219 SDT_PROBE_DEFINE3(vmm, vmx, exit, halt,
220 "struct vmx *", "int", "struct vm_exit *");
222 SDT_PROBE_DEFINE3(vmm, vmx, exit, mtrap,
223 "struct vmx *", "int", "struct vm_exit *");
225 SDT_PROBE_DEFINE3(vmm, vmx, exit, pause,
226 "struct vmx *", "int", "struct vm_exit *");
228 SDT_PROBE_DEFINE3(vmm, vmx, exit, intrwindow,
229 "struct vmx *", "int", "struct vm_exit *");
231 SDT_PROBE_DEFINE4(vmm, vmx, exit, interrupt,
232 "struct vmx *", "int", "struct vm_exit *", "uint32_t");
234 SDT_PROBE_DEFINE3(vmm, vmx, exit, nmiwindow,
235 "struct vmx *", "int", "struct vm_exit *");
237 SDT_PROBE_DEFINE3(vmm, vmx, exit, inout,
238 "struct vmx *", "int", "struct vm_exit *");
240 SDT_PROBE_DEFINE3(vmm, vmx, exit, cpuid,
241 "struct vmx *", "int", "struct vm_exit *");
243 SDT_PROBE_DEFINE5(vmm, vmx, exit, exception,
244 "struct vmx *", "int", "struct vm_exit *", "uint32_t", "int");
246 SDT_PROBE_DEFINE5(vmm, vmx, exit, nestedfault,
247 "struct vmx *", "int", "struct vm_exit *", "uint64_t", "uint64_t");
249 SDT_PROBE_DEFINE4(vmm, vmx, exit, mmiofault,
250 "struct vmx *", "int", "struct vm_exit *", "uint64_t");
252 SDT_PROBE_DEFINE3(vmm, vmx, exit, eoi,
253 "struct vmx *", "int", "struct vm_exit *");
255 SDT_PROBE_DEFINE3(vmm, vmx, exit, apicaccess,
256 "struct vmx *", "int", "struct vm_exit *");
258 SDT_PROBE_DEFINE4(vmm, vmx, exit, apicwrite,
259 "struct vmx *", "int", "struct vm_exit *", "struct vlapic *");
261 SDT_PROBE_DEFINE3(vmm, vmx, exit, xsetbv,
262 "struct vmx *", "int", "struct vm_exit *");
264 SDT_PROBE_DEFINE3(vmm, vmx, exit, monitor,
265 "struct vmx *", "int", "struct vm_exit *");
267 SDT_PROBE_DEFINE3(vmm, vmx, exit, mwait,
268 "struct vmx *", "int", "struct vm_exit *");
270 SDT_PROBE_DEFINE4(vmm, vmx, exit, unknown,
271 "struct vmx *", "int", "struct vm_exit *", "uint32_t");
273 SDT_PROBE_DEFINE4(vmm, vmx, exit, return,
274 "struct vmx *", "int", "struct vm_exit *", "int");
277 * Use the last page below 4GB as the APIC access address. This address is
278 * occupied by the boot firmware so it is guaranteed that it will not conflict
279 * with a page in system memory.
281 #define APIC_ACCESS_ADDRESS 0xFFFFF000
283 static int vmx_getdesc(void *arg, int vcpu, int reg, struct seg_desc *desc);
284 static int vmx_getreg(void *arg, int vcpu, int reg, uint64_t *retval);
285 static int vmxctx_setreg(struct vmxctx *vmxctx, int reg, uint64_t val);
286 static void vmx_inject_pir(struct vlapic *vlapic);
290 exit_reason_to_str(int reason)
292 static char reasonbuf[32];
295 case EXIT_REASON_EXCEPTION:
297 case EXIT_REASON_EXT_INTR:
299 case EXIT_REASON_TRIPLE_FAULT:
300 return "triplefault";
301 case EXIT_REASON_INIT:
303 case EXIT_REASON_SIPI:
305 case EXIT_REASON_IO_SMI:
307 case EXIT_REASON_SMI:
309 case EXIT_REASON_INTR_WINDOW:
311 case EXIT_REASON_NMI_WINDOW:
313 case EXIT_REASON_TASK_SWITCH:
315 case EXIT_REASON_CPUID:
317 case EXIT_REASON_GETSEC:
319 case EXIT_REASON_HLT:
321 case EXIT_REASON_INVD:
323 case EXIT_REASON_INVLPG:
325 case EXIT_REASON_RDPMC:
327 case EXIT_REASON_RDTSC:
329 case EXIT_REASON_RSM:
331 case EXIT_REASON_VMCALL:
333 case EXIT_REASON_VMCLEAR:
335 case EXIT_REASON_VMLAUNCH:
337 case EXIT_REASON_VMPTRLD:
339 case EXIT_REASON_VMPTRST:
341 case EXIT_REASON_VMREAD:
343 case EXIT_REASON_VMRESUME:
345 case EXIT_REASON_VMWRITE:
347 case EXIT_REASON_VMXOFF:
349 case EXIT_REASON_VMXON:
351 case EXIT_REASON_CR_ACCESS:
353 case EXIT_REASON_DR_ACCESS:
355 case EXIT_REASON_INOUT:
357 case EXIT_REASON_RDMSR:
359 case EXIT_REASON_WRMSR:
361 case EXIT_REASON_INVAL_VMCS:
363 case EXIT_REASON_INVAL_MSR:
365 case EXIT_REASON_MWAIT:
367 case EXIT_REASON_MTF:
369 case EXIT_REASON_MONITOR:
371 case EXIT_REASON_PAUSE:
373 case EXIT_REASON_MCE_DURING_ENTRY:
374 return "mce-during-entry";
375 case EXIT_REASON_TPR:
377 case EXIT_REASON_APIC_ACCESS:
378 return "apic-access";
379 case EXIT_REASON_GDTR_IDTR:
381 case EXIT_REASON_LDTR_TR:
383 case EXIT_REASON_EPT_FAULT:
385 case EXIT_REASON_EPT_MISCONFIG:
386 return "eptmisconfig";
387 case EXIT_REASON_INVEPT:
389 case EXIT_REASON_RDTSCP:
391 case EXIT_REASON_VMX_PREEMPT:
393 case EXIT_REASON_INVVPID:
395 case EXIT_REASON_WBINVD:
397 case EXIT_REASON_XSETBV:
399 case EXIT_REASON_APIC_WRITE:
402 snprintf(reasonbuf, sizeof(reasonbuf), "%d", reason);
409 vmx_allow_x2apic_msrs(struct vmx *vmx)
416 * Allow readonly access to the following x2APIC MSRs from the guest.
418 error += guest_msr_ro(vmx, MSR_APIC_ID);
419 error += guest_msr_ro(vmx, MSR_APIC_VERSION);
420 error += guest_msr_ro(vmx, MSR_APIC_LDR);
421 error += guest_msr_ro(vmx, MSR_APIC_SVR);
423 for (i = 0; i < 8; i++)
424 error += guest_msr_ro(vmx, MSR_APIC_ISR0 + i);
426 for (i = 0; i < 8; i++)
427 error += guest_msr_ro(vmx, MSR_APIC_TMR0 + i);
429 for (i = 0; i < 8; i++)
430 error += guest_msr_ro(vmx, MSR_APIC_IRR0 + i);
432 error += guest_msr_ro(vmx, MSR_APIC_ESR);
433 error += guest_msr_ro(vmx, MSR_APIC_LVT_TIMER);
434 error += guest_msr_ro(vmx, MSR_APIC_LVT_THERMAL);
435 error += guest_msr_ro(vmx, MSR_APIC_LVT_PCINT);
436 error += guest_msr_ro(vmx, MSR_APIC_LVT_LINT0);
437 error += guest_msr_ro(vmx, MSR_APIC_LVT_LINT1);
438 error += guest_msr_ro(vmx, MSR_APIC_LVT_ERROR);
439 error += guest_msr_ro(vmx, MSR_APIC_ICR_TIMER);
440 error += guest_msr_ro(vmx, MSR_APIC_DCR_TIMER);
441 error += guest_msr_ro(vmx, MSR_APIC_ICR);
444 * Allow TPR, EOI and SELF_IPI MSRs to be read and written by the guest.
446 * These registers get special treatment described in the section
447 * "Virtualizing MSR-Based APIC Accesses".
449 error += guest_msr_rw(vmx, MSR_APIC_TPR);
450 error += guest_msr_rw(vmx, MSR_APIC_EOI);
451 error += guest_msr_rw(vmx, MSR_APIC_SELF_IPI);
457 vmx_fix_cr0(u_long cr0)
460 return ((cr0 | cr0_ones_mask) & ~cr0_zeros_mask);
464 vmx_fix_cr4(u_long cr4)
467 return ((cr4 | cr4_ones_mask) & ~cr4_zeros_mask);
473 if (vpid < 0 || vpid > 0xffff)
474 panic("vpid_free: invalid vpid %d", vpid);
477 * VPIDs [0,VM_MAXCPU] are special and are not allocated from
478 * the unit number allocator.
481 if (vpid > VM_MAXCPU)
482 free_unr(vpid_unr, vpid);
486 vpid_alloc(uint16_t *vpid, int num)
490 if (num <= 0 || num > VM_MAXCPU)
491 panic("invalid number of vpids requested: %d", num);
494 * If the "enable vpid" execution control is not enabled then the
495 * VPID is required to be 0 for all vcpus.
497 if ((procbased_ctls2 & PROCBASED2_ENABLE_VPID) == 0) {
498 for (i = 0; i < num; i++)
504 * Allocate a unique VPID for each vcpu from the unit number allocator.
506 for (i = 0; i < num; i++) {
507 x = alloc_unr(vpid_unr);
515 atomic_add_int(&vpid_alloc_failed, 1);
518 * If the unit number allocator does not have enough unique
519 * VPIDs then we need to allocate from the [1,VM_MAXCPU] range.
521 * These VPIDs are not be unique across VMs but this does not
522 * affect correctness because the combined mappings are also
523 * tagged with the EP4TA which is unique for each VM.
525 * It is still sub-optimal because the invvpid will invalidate
526 * combined mappings for a particular VPID across all EP4TAs.
531 for (i = 0; i < num; i++)
540 * VPID 0 is required when the "enable VPID" execution control is
543 * VPIDs [1,VM_MAXCPU] are used as the "overflow namespace" when the
544 * unit number allocator does not have sufficient unique VPIDs to
545 * satisfy the allocation.
547 * The remaining VPIDs are managed by the unit number allocator.
549 vpid_unr = new_unrhdr(VM_MAXCPU + 1, 0xffff, NULL);
553 vmx_disable(void *arg __unused)
555 struct invvpid_desc invvpid_desc = { 0 };
556 struct invept_desc invept_desc = { 0 };
558 if (vmxon_enabled[curcpu]) {
560 * See sections 25.3.3.3 and 25.3.3.4 in Intel Vol 3b.
562 * VMXON or VMXOFF are not required to invalidate any TLB
563 * caching structures. This prevents potential retention of
564 * cached information in the TLB between distinct VMX episodes.
566 invvpid(INVVPID_TYPE_ALL_CONTEXTS, invvpid_desc);
567 invept(INVEPT_TYPE_ALL_CONTEXTS, invept_desc);
570 load_cr4(rcr4() & ~CR4_VMXE);
578 lapic_ipi_free(pirvec);
580 if (vpid_unr != NULL) {
581 delete_unrhdr(vpid_unr);
585 if (nmi_flush_l1d_sw == 1)
586 nmi_flush_l1d_sw = 0;
588 smp_rendezvous(NULL, vmx_disable, NULL, NULL);
594 vmx_enable(void *arg __unused)
597 uint64_t feature_control;
599 feature_control = rdmsr(MSR_IA32_FEATURE_CONTROL);
600 if ((feature_control & IA32_FEATURE_CONTROL_LOCK) == 0 ||
601 (feature_control & IA32_FEATURE_CONTROL_VMX_EN) == 0) {
602 wrmsr(MSR_IA32_FEATURE_CONTROL,
603 feature_control | IA32_FEATURE_CONTROL_VMX_EN |
604 IA32_FEATURE_CONTROL_LOCK);
607 load_cr4(rcr4() | CR4_VMXE);
609 *(uint32_t *)vmxon_region[curcpu] = vmx_revision();
610 error = vmxon(vmxon_region[curcpu]);
612 vmxon_enabled[curcpu] = 1;
619 if (vmxon_enabled[curcpu])
620 vmxon(vmxon_region[curcpu]);
626 int error, use_tpr_shadow;
627 uint64_t basic, fixed0, fixed1, feature_control;
628 uint32_t tmp, procbased2_vid_bits;
630 /* CPUID.1:ECX[bit 5] must be 1 for processor to support VMX */
631 if (!(cpu_feature2 & CPUID2_VMX)) {
632 printf("vmx_init: processor does not support VMX operation\n");
637 * Verify that MSR_IA32_FEATURE_CONTROL lock and VMXON enable bits
638 * are set (bits 0 and 2 respectively).
640 feature_control = rdmsr(MSR_IA32_FEATURE_CONTROL);
641 if ((feature_control & IA32_FEATURE_CONTROL_LOCK) == 1 &&
642 (feature_control & IA32_FEATURE_CONTROL_VMX_EN) == 0) {
643 printf("vmx_init: VMX operation disabled by BIOS\n");
648 * Verify capabilities MSR_VMX_BASIC:
649 * - bit 54 indicates support for INS/OUTS decoding
651 basic = rdmsr(MSR_VMX_BASIC);
652 if ((basic & (1UL << 54)) == 0) {
653 printf("vmx_init: processor does not support desired basic "
658 /* Check support for primary processor-based VM-execution controls */
659 error = vmx_set_ctlreg(MSR_VMX_PROCBASED_CTLS,
660 MSR_VMX_TRUE_PROCBASED_CTLS,
661 PROCBASED_CTLS_ONE_SETTING,
662 PROCBASED_CTLS_ZERO_SETTING, &procbased_ctls);
664 printf("vmx_init: processor does not support desired primary "
665 "processor-based controls\n");
669 /* Clear the processor-based ctl bits that are set on demand */
670 procbased_ctls &= ~PROCBASED_CTLS_WINDOW_SETTING;
672 /* Check support for secondary processor-based VM-execution controls */
673 error = vmx_set_ctlreg(MSR_VMX_PROCBASED_CTLS2,
674 MSR_VMX_PROCBASED_CTLS2,
675 PROCBASED_CTLS2_ONE_SETTING,
676 PROCBASED_CTLS2_ZERO_SETTING, &procbased_ctls2);
678 printf("vmx_init: processor does not support desired secondary "
679 "processor-based controls\n");
683 /* Check support for VPID */
684 error = vmx_set_ctlreg(MSR_VMX_PROCBASED_CTLS2, MSR_VMX_PROCBASED_CTLS2,
685 PROCBASED2_ENABLE_VPID, 0, &tmp);
687 procbased_ctls2 |= PROCBASED2_ENABLE_VPID;
689 /* Check support for pin-based VM-execution controls */
690 error = vmx_set_ctlreg(MSR_VMX_PINBASED_CTLS,
691 MSR_VMX_TRUE_PINBASED_CTLS,
692 PINBASED_CTLS_ONE_SETTING,
693 PINBASED_CTLS_ZERO_SETTING, &pinbased_ctls);
695 printf("vmx_init: processor does not support desired "
696 "pin-based controls\n");
700 /* Check support for VM-exit controls */
701 error = vmx_set_ctlreg(MSR_VMX_EXIT_CTLS, MSR_VMX_TRUE_EXIT_CTLS,
702 VM_EXIT_CTLS_ONE_SETTING,
703 VM_EXIT_CTLS_ZERO_SETTING,
706 printf("vmx_init: processor does not support desired "
711 /* Check support for VM-entry controls */
712 error = vmx_set_ctlreg(MSR_VMX_ENTRY_CTLS, MSR_VMX_TRUE_ENTRY_CTLS,
713 VM_ENTRY_CTLS_ONE_SETTING, VM_ENTRY_CTLS_ZERO_SETTING,
716 printf("vmx_init: processor does not support desired "
722 * Check support for optional features by testing them
725 cap_halt_exit = (vmx_set_ctlreg(MSR_VMX_PROCBASED_CTLS,
726 MSR_VMX_TRUE_PROCBASED_CTLS,
727 PROCBASED_HLT_EXITING, 0,
730 cap_monitor_trap = (vmx_set_ctlreg(MSR_VMX_PROCBASED_CTLS,
731 MSR_VMX_PROCBASED_CTLS,
735 cap_pause_exit = (vmx_set_ctlreg(MSR_VMX_PROCBASED_CTLS,
736 MSR_VMX_TRUE_PROCBASED_CTLS,
737 PROCBASED_PAUSE_EXITING, 0,
740 cap_unrestricted_guest = (vmx_set_ctlreg(MSR_VMX_PROCBASED_CTLS2,
741 MSR_VMX_PROCBASED_CTLS2,
742 PROCBASED2_UNRESTRICTED_GUEST, 0,
745 cap_invpcid = (vmx_set_ctlreg(MSR_VMX_PROCBASED_CTLS2,
746 MSR_VMX_PROCBASED_CTLS2, PROCBASED2_ENABLE_INVPCID, 0,
750 * Check support for virtual interrupt delivery.
752 procbased2_vid_bits = (PROCBASED2_VIRTUALIZE_APIC_ACCESSES |
753 PROCBASED2_VIRTUALIZE_X2APIC_MODE |
754 PROCBASED2_APIC_REGISTER_VIRTUALIZATION |
755 PROCBASED2_VIRTUAL_INTERRUPT_DELIVERY);
757 use_tpr_shadow = (vmx_set_ctlreg(MSR_VMX_PROCBASED_CTLS,
758 MSR_VMX_TRUE_PROCBASED_CTLS, PROCBASED_USE_TPR_SHADOW, 0,
761 error = vmx_set_ctlreg(MSR_VMX_PROCBASED_CTLS2, MSR_VMX_PROCBASED_CTLS2,
762 procbased2_vid_bits, 0, &tmp);
763 if (error == 0 && use_tpr_shadow) {
764 virtual_interrupt_delivery = 1;
765 TUNABLE_INT_FETCH("hw.vmm.vmx.use_apic_vid",
766 &virtual_interrupt_delivery);
769 if (virtual_interrupt_delivery) {
770 procbased_ctls |= PROCBASED_USE_TPR_SHADOW;
771 procbased_ctls2 |= procbased2_vid_bits;
772 procbased_ctls2 &= ~PROCBASED2_VIRTUALIZE_X2APIC_MODE;
775 * No need to emulate accesses to %CR8 if virtual
776 * interrupt delivery is enabled.
778 procbased_ctls &= ~PROCBASED_CR8_LOAD_EXITING;
779 procbased_ctls &= ~PROCBASED_CR8_STORE_EXITING;
782 * Check for Posted Interrupts only if Virtual Interrupt
783 * Delivery is enabled.
785 error = vmx_set_ctlreg(MSR_VMX_PINBASED_CTLS,
786 MSR_VMX_TRUE_PINBASED_CTLS, PINBASED_POSTED_INTERRUPT, 0,
789 pirvec = lapic_ipi_alloc(pti ? &IDTVEC(justreturn1_pti) :
790 &IDTVEC(justreturn));
793 printf("vmx_init: unable to allocate "
794 "posted interrupt vector\n");
797 posted_interrupts = 1;
798 TUNABLE_INT_FETCH("hw.vmm.vmx.use_apic_pir",
804 if (posted_interrupts)
805 pinbased_ctls |= PINBASED_POSTED_INTERRUPT;
808 error = ept_init(ipinum);
810 printf("vmx_init: ept initialization failed (%d)\n", error);
814 guest_l1d_flush = (cpu_ia32_arch_caps & IA32_ARCH_CAP_RDCL_NO) == 0;
815 TUNABLE_INT_FETCH("hw.vmm.l1d_flush", &guest_l1d_flush);
818 * L1D cache flush is enabled. Use IA32_FLUSH_CMD MSR when
819 * available. Otherwise fall back to the software flush
820 * method which loads enough data from the kernel text to
821 * flush existing L1D content, both on VMX entry and on NMI
824 if (guest_l1d_flush) {
825 if ((cpu_stdext_feature3 & CPUID_STDEXT3_L1D_FLUSH) == 0) {
826 guest_l1d_flush_sw = 1;
827 TUNABLE_INT_FETCH("hw.vmm.l1d_flush_sw",
828 &guest_l1d_flush_sw);
830 if (guest_l1d_flush_sw) {
831 if (nmi_flush_l1d_sw <= 1)
832 nmi_flush_l1d_sw = 1;
834 msr_load_list[0].index = MSR_IA32_FLUSH_CMD;
835 msr_load_list[0].val = IA32_FLUSH_CMD_L1D;
840 * Stash the cr0 and cr4 bits that must be fixed to 0 or 1
842 fixed0 = rdmsr(MSR_VMX_CR0_FIXED0);
843 fixed1 = rdmsr(MSR_VMX_CR0_FIXED1);
844 cr0_ones_mask = fixed0 & fixed1;
845 cr0_zeros_mask = ~fixed0 & ~fixed1;
848 * CR0_PE and CR0_PG can be set to zero in VMX non-root operation
849 * if unrestricted guest execution is allowed.
851 if (cap_unrestricted_guest)
852 cr0_ones_mask &= ~(CR0_PG | CR0_PE);
855 * Do not allow the guest to set CR0_NW or CR0_CD.
857 cr0_zeros_mask |= (CR0_NW | CR0_CD);
859 fixed0 = rdmsr(MSR_VMX_CR4_FIXED0);
860 fixed1 = rdmsr(MSR_VMX_CR4_FIXED1);
861 cr4_ones_mask = fixed0 & fixed1;
862 cr4_zeros_mask = ~fixed0 & ~fixed1;
868 /* enable VMX operation */
869 smp_rendezvous(NULL, vmx_enable, NULL, NULL);
877 vmx_trigger_hostintr(int vector)
880 struct gate_descriptor *gd;
884 KASSERT(vector >= 32 && vector <= 255, ("vmx_trigger_hostintr: "
885 "invalid vector %d", vector));
886 KASSERT(gd->gd_p == 1, ("gate descriptor for vector %d not present",
888 KASSERT(gd->gd_type == SDT_SYSIGT, ("gate descriptor for vector %d "
889 "has invalid type %d", vector, gd->gd_type));
890 KASSERT(gd->gd_dpl == SEL_KPL, ("gate descriptor for vector %d "
891 "has invalid dpl %d", vector, gd->gd_dpl));
892 KASSERT(gd->gd_selector == GSEL(GCODE_SEL, SEL_KPL), ("gate descriptor "
893 "for vector %d has invalid selector %d", vector, gd->gd_selector));
894 KASSERT(gd->gd_ist == 0, ("gate descriptor for vector %d has invalid "
895 "IST %d", vector, gd->gd_ist));
897 func = ((long)gd->gd_hioffset << 16 | gd->gd_looffset);
902 vmx_setup_cr_shadow(int which, struct vmcs *vmcs, uint32_t initial)
904 int error, mask_ident, shadow_ident;
907 if (which != 0 && which != 4)
908 panic("vmx_setup_cr_shadow: unknown cr%d", which);
911 mask_ident = VMCS_CR0_MASK;
912 mask_value = cr0_ones_mask | cr0_zeros_mask;
913 shadow_ident = VMCS_CR0_SHADOW;
915 mask_ident = VMCS_CR4_MASK;
916 mask_value = cr4_ones_mask | cr4_zeros_mask;
917 shadow_ident = VMCS_CR4_SHADOW;
920 error = vmcs_setreg(vmcs, 0, VMCS_IDENT(mask_ident), mask_value);
924 error = vmcs_setreg(vmcs, 0, VMCS_IDENT(shadow_ident), initial);
930 #define vmx_setup_cr0_shadow(vmcs,init) vmx_setup_cr_shadow(0, (vmcs), (init))
931 #define vmx_setup_cr4_shadow(vmcs,init) vmx_setup_cr_shadow(4, (vmcs), (init))
934 vmx_vminit(struct vm *vm, pmap_t pmap)
936 uint16_t vpid[VM_MAXCPU];
942 vmx = malloc(sizeof(struct vmx), M_VMX, M_WAITOK | M_ZERO);
943 if ((uintptr_t)vmx & PAGE_MASK) {
944 panic("malloc of struct vmx not aligned on %d byte boundary",
949 vmx->eptp = eptp(vtophys((vm_offset_t)pmap->pm_pml4));
952 * Clean up EPTP-tagged guest physical and combined mappings
954 * VMX transitions are not required to invalidate any guest physical
955 * mappings. So, it may be possible for stale guest physical mappings
956 * to be present in the processor TLBs.
958 * Combined mappings for this EP4TA are also invalidated for all VPIDs.
960 ept_invalidate_mappings(vmx->eptp);
962 msr_bitmap_initialize(vmx->msr_bitmap);
965 * It is safe to allow direct access to MSR_GSBASE and MSR_FSBASE.
966 * The guest FSBASE and GSBASE are saved and restored during
967 * vm-exit and vm-entry respectively. The host FSBASE and GSBASE are
968 * always restored from the vmcs host state area on vm-exit.
970 * The SYSENTER_CS/ESP/EIP MSRs are identical to FS/GSBASE in
971 * how they are saved/restored so can be directly accessed by the
974 * MSR_EFER is saved and restored in the guest VMCS area on a
975 * VM exit and entry respectively. It is also restored from the
976 * host VMCS area on a VM exit.
978 * The TSC MSR is exposed read-only. Writes are disallowed as
979 * that will impact the host TSC. If the guest does a write
980 * the "use TSC offsetting" execution control is enabled and the
981 * difference between the host TSC and the guest TSC is written
982 * into the TSC offset in the VMCS.
984 if (guest_msr_rw(vmx, MSR_GSBASE) ||
985 guest_msr_rw(vmx, MSR_FSBASE) ||
986 guest_msr_rw(vmx, MSR_SYSENTER_CS_MSR) ||
987 guest_msr_rw(vmx, MSR_SYSENTER_ESP_MSR) ||
988 guest_msr_rw(vmx, MSR_SYSENTER_EIP_MSR) ||
989 guest_msr_rw(vmx, MSR_EFER) ||
990 guest_msr_ro(vmx, MSR_TSC))
991 panic("vmx_vminit: error setting guest msr access");
993 vpid_alloc(vpid, VM_MAXCPU);
995 if (virtual_interrupt_delivery) {
996 error = vm_map_mmio(vm, DEFAULT_APIC_BASE, PAGE_SIZE,
997 APIC_ACCESS_ADDRESS);
998 /* XXX this should really return an error to the caller */
999 KASSERT(error == 0, ("vm_map_mmio(apicbase) error %d", error));
1002 for (i = 0; i < VM_MAXCPU; i++) {
1003 vmcs = &vmx->vmcs[i];
1004 vmcs->identifier = vmx_revision();
1005 error = vmclear(vmcs);
1007 panic("vmx_vminit: vmclear error %d on vcpu %d\n",
1011 vmx_msr_guest_init(vmx, i);
1013 error = vmcs_init(vmcs);
1014 KASSERT(error == 0, ("vmcs_init error %d", error));
1018 error += vmwrite(VMCS_HOST_RSP, (u_long)&vmx->ctx[i]);
1019 error += vmwrite(VMCS_EPTP, vmx->eptp);
1020 error += vmwrite(VMCS_PIN_BASED_CTLS, pinbased_ctls);
1021 error += vmwrite(VMCS_PRI_PROC_BASED_CTLS, procbased_ctls);
1022 error += vmwrite(VMCS_SEC_PROC_BASED_CTLS, procbased_ctls2);
1023 error += vmwrite(VMCS_EXIT_CTLS, exit_ctls);
1024 error += vmwrite(VMCS_ENTRY_CTLS, entry_ctls);
1025 error += vmwrite(VMCS_MSR_BITMAP, vtophys(vmx->msr_bitmap));
1026 error += vmwrite(VMCS_VPID, vpid[i]);
1028 if (guest_l1d_flush && !guest_l1d_flush_sw) {
1029 vmcs_write(VMCS_ENTRY_MSR_LOAD, pmap_kextract(
1030 (vm_offset_t)&msr_load_list[0]));
1031 vmcs_write(VMCS_ENTRY_MSR_LOAD_COUNT,
1032 nitems(msr_load_list));
1033 vmcs_write(VMCS_EXIT_MSR_STORE, 0);
1034 vmcs_write(VMCS_EXIT_MSR_STORE_COUNT, 0);
1037 /* exception bitmap */
1038 if (vcpu_trace_exceptions(vm, i))
1039 exc_bitmap = 0xffffffff;
1041 exc_bitmap = 1 << IDT_MC;
1042 error += vmwrite(VMCS_EXCEPTION_BITMAP, exc_bitmap);
1044 vmx->ctx[i].guest_dr6 = DBREG_DR6_RESERVED1;
1045 error += vmwrite(VMCS_GUEST_DR7, DBREG_DR7_RESERVED1);
1047 if (virtual_interrupt_delivery) {
1048 error += vmwrite(VMCS_APIC_ACCESS, APIC_ACCESS_ADDRESS);
1049 error += vmwrite(VMCS_VIRTUAL_APIC,
1050 vtophys(&vmx->apic_page[i]));
1051 error += vmwrite(VMCS_EOI_EXIT0, 0);
1052 error += vmwrite(VMCS_EOI_EXIT1, 0);
1053 error += vmwrite(VMCS_EOI_EXIT2, 0);
1054 error += vmwrite(VMCS_EOI_EXIT3, 0);
1056 if (posted_interrupts) {
1057 error += vmwrite(VMCS_PIR_VECTOR, pirvec);
1058 error += vmwrite(VMCS_PIR_DESC,
1059 vtophys(&vmx->pir_desc[i]));
1062 KASSERT(error == 0, ("vmx_vminit: error customizing the vmcs"));
1064 vmx->cap[i].set = 0;
1065 vmx->cap[i].proc_ctls = procbased_ctls;
1066 vmx->cap[i].proc_ctls2 = procbased_ctls2;
1068 vmx->state[i].nextrip = ~0;
1069 vmx->state[i].lastcpu = NOCPU;
1070 vmx->state[i].vpid = vpid[i];
1073 * Set up the CR0/4 shadows, and init the read shadow
1074 * to the power-on register value from the Intel Sys Arch.
1078 error = vmx_setup_cr0_shadow(vmcs, 0x60000010);
1080 panic("vmx_setup_cr0_shadow %d", error);
1082 error = vmx_setup_cr4_shadow(vmcs, 0);
1084 panic("vmx_setup_cr4_shadow %d", error);
1086 vmx->ctx[i].pmap = pmap;
1093 vmx_handle_cpuid(struct vm *vm, int vcpu, struct vmxctx *vmxctx)
1097 func = vmxctx->guest_rax;
1099 handled = x86_emulate_cpuid(vm, vcpu,
1100 (uint32_t*)(&vmxctx->guest_rax),
1101 (uint32_t*)(&vmxctx->guest_rbx),
1102 (uint32_t*)(&vmxctx->guest_rcx),
1103 (uint32_t*)(&vmxctx->guest_rdx));
1107 static __inline void
1108 vmx_run_trace(struct vmx *vmx, int vcpu)
1111 VCPU_CTR1(vmx->vm, vcpu, "Resume execution at %#lx", vmcs_guest_rip());
1115 static __inline void
1116 vmx_exit_trace(struct vmx *vmx, int vcpu, uint64_t rip, uint32_t exit_reason,
1120 VCPU_CTR3(vmx->vm, vcpu, "%s %s vmexit at 0x%0lx",
1121 handled ? "handled" : "unhandled",
1122 exit_reason_to_str(exit_reason), rip);
1126 static __inline void
1127 vmx_astpending_trace(struct vmx *vmx, int vcpu, uint64_t rip)
1130 VCPU_CTR1(vmx->vm, vcpu, "astpending vmexit at 0x%0lx", rip);
1134 static VMM_STAT_INTEL(VCPU_INVVPID_SAVED, "Number of vpid invalidations saved");
1135 static VMM_STAT_INTEL(VCPU_INVVPID_DONE, "Number of vpid invalidations done");
1138 * Invalidate guest mappings identified by its vpid from the TLB.
1140 static __inline void
1141 vmx_invvpid(struct vmx *vmx, int vcpu, pmap_t pmap, int running)
1143 struct vmxstate *vmxstate;
1144 struct invvpid_desc invvpid_desc;
1146 vmxstate = &vmx->state[vcpu];
1147 if (vmxstate->vpid == 0)
1152 * Set the 'lastcpu' to an invalid host cpu.
1154 * This will invalidate TLB entries tagged with the vcpu's
1155 * vpid the next time it runs via vmx_set_pcpu_defaults().
1157 vmxstate->lastcpu = NOCPU;
1161 KASSERT(curthread->td_critnest > 0, ("%s: vcpu %d running outside "
1162 "critical section", __func__, vcpu));
1165 * Invalidate all mappings tagged with 'vpid'
1167 * We do this because this vcpu was executing on a different host
1168 * cpu when it last ran. We do not track whether it invalidated
1169 * mappings associated with its 'vpid' during that run. So we must
1170 * assume that the mappings associated with 'vpid' on 'curcpu' are
1171 * stale and invalidate them.
1173 * Note that we incur this penalty only when the scheduler chooses to
1174 * move the thread associated with this vcpu between host cpus.
1176 * Note also that this will invalidate mappings tagged with 'vpid'
1179 if (pmap->pm_eptgen == vmx->eptgen[curcpu]) {
1180 invvpid_desc._res1 = 0;
1181 invvpid_desc._res2 = 0;
1182 invvpid_desc.vpid = vmxstate->vpid;
1183 invvpid_desc.linear_addr = 0;
1184 invvpid(INVVPID_TYPE_SINGLE_CONTEXT, invvpid_desc);
1185 vmm_stat_incr(vmx->vm, vcpu, VCPU_INVVPID_DONE, 1);
1188 * The invvpid can be skipped if an invept is going to
1189 * be performed before entering the guest. The invept
1190 * will invalidate combined mappings tagged with
1191 * 'vmx->eptp' for all vpids.
1193 vmm_stat_incr(vmx->vm, vcpu, VCPU_INVVPID_SAVED, 1);
1198 vmx_set_pcpu_defaults(struct vmx *vmx, int vcpu, pmap_t pmap)
1200 struct vmxstate *vmxstate;
1202 vmxstate = &vmx->state[vcpu];
1203 if (vmxstate->lastcpu == curcpu)
1206 vmxstate->lastcpu = curcpu;
1208 vmm_stat_incr(vmx->vm, vcpu, VCPU_MIGRATIONS, 1);
1210 vmcs_write(VMCS_HOST_TR_BASE, vmm_get_host_trbase());
1211 vmcs_write(VMCS_HOST_GDTR_BASE, vmm_get_host_gdtrbase());
1212 vmcs_write(VMCS_HOST_GS_BASE, vmm_get_host_gsbase());
1213 vmx_invvpid(vmx, vcpu, pmap, 1);
1217 * We depend on 'procbased_ctls' to have the Interrupt Window Exiting bit set.
1219 CTASSERT((PROCBASED_CTLS_ONE_SETTING & PROCBASED_INT_WINDOW_EXITING) != 0);
1221 static void __inline
1222 vmx_set_int_window_exiting(struct vmx *vmx, int vcpu)
1225 if ((vmx->cap[vcpu].proc_ctls & PROCBASED_INT_WINDOW_EXITING) == 0) {
1226 vmx->cap[vcpu].proc_ctls |= PROCBASED_INT_WINDOW_EXITING;
1227 vmcs_write(VMCS_PRI_PROC_BASED_CTLS, vmx->cap[vcpu].proc_ctls);
1228 VCPU_CTR0(vmx->vm, vcpu, "Enabling interrupt window exiting");
1232 static void __inline
1233 vmx_clear_int_window_exiting(struct vmx *vmx, int vcpu)
1236 KASSERT((vmx->cap[vcpu].proc_ctls & PROCBASED_INT_WINDOW_EXITING) != 0,
1237 ("intr_window_exiting not set: %#x", vmx->cap[vcpu].proc_ctls));
1238 vmx->cap[vcpu].proc_ctls &= ~PROCBASED_INT_WINDOW_EXITING;
1239 vmcs_write(VMCS_PRI_PROC_BASED_CTLS, vmx->cap[vcpu].proc_ctls);
1240 VCPU_CTR0(vmx->vm, vcpu, "Disabling interrupt window exiting");
1243 static void __inline
1244 vmx_set_nmi_window_exiting(struct vmx *vmx, int vcpu)
1247 if ((vmx->cap[vcpu].proc_ctls & PROCBASED_NMI_WINDOW_EXITING) == 0) {
1248 vmx->cap[vcpu].proc_ctls |= PROCBASED_NMI_WINDOW_EXITING;
1249 vmcs_write(VMCS_PRI_PROC_BASED_CTLS, vmx->cap[vcpu].proc_ctls);
1250 VCPU_CTR0(vmx->vm, vcpu, "Enabling NMI window exiting");
1254 static void __inline
1255 vmx_clear_nmi_window_exiting(struct vmx *vmx, int vcpu)
1258 KASSERT((vmx->cap[vcpu].proc_ctls & PROCBASED_NMI_WINDOW_EXITING) != 0,
1259 ("nmi_window_exiting not set %#x", vmx->cap[vcpu].proc_ctls));
1260 vmx->cap[vcpu].proc_ctls &= ~PROCBASED_NMI_WINDOW_EXITING;
1261 vmcs_write(VMCS_PRI_PROC_BASED_CTLS, vmx->cap[vcpu].proc_ctls);
1262 VCPU_CTR0(vmx->vm, vcpu, "Disabling NMI window exiting");
1266 vmx_set_tsc_offset(struct vmx *vmx, int vcpu, uint64_t offset)
1270 if ((vmx->cap[vcpu].proc_ctls & PROCBASED_TSC_OFFSET) == 0) {
1271 vmx->cap[vcpu].proc_ctls |= PROCBASED_TSC_OFFSET;
1272 vmcs_write(VMCS_PRI_PROC_BASED_CTLS, vmx->cap[vcpu].proc_ctls);
1273 VCPU_CTR0(vmx->vm, vcpu, "Enabling TSC offsetting");
1276 error = vmwrite(VMCS_TSC_OFFSET, offset);
1281 #define NMI_BLOCKING (VMCS_INTERRUPTIBILITY_NMI_BLOCKING | \
1282 VMCS_INTERRUPTIBILITY_MOVSS_BLOCKING)
1283 #define HWINTR_BLOCKING (VMCS_INTERRUPTIBILITY_STI_BLOCKING | \
1284 VMCS_INTERRUPTIBILITY_MOVSS_BLOCKING)
1287 vmx_inject_nmi(struct vmx *vmx, int vcpu)
1291 gi = vmcs_read(VMCS_GUEST_INTERRUPTIBILITY);
1292 KASSERT((gi & NMI_BLOCKING) == 0, ("vmx_inject_nmi: invalid guest "
1293 "interruptibility-state %#x", gi));
1295 info = vmcs_read(VMCS_ENTRY_INTR_INFO);
1296 KASSERT((info & VMCS_INTR_VALID) == 0, ("vmx_inject_nmi: invalid "
1297 "VM-entry interruption information %#x", info));
1300 * Inject the virtual NMI. The vector must be the NMI IDT entry
1301 * or the VMCS entry check will fail.
1303 info = IDT_NMI | VMCS_INTR_T_NMI | VMCS_INTR_VALID;
1304 vmcs_write(VMCS_ENTRY_INTR_INFO, info);
1306 VCPU_CTR0(vmx->vm, vcpu, "Injecting vNMI");
1308 /* Clear the request */
1309 vm_nmi_clear(vmx->vm, vcpu);
1313 vmx_inject_interrupts(struct vmx *vmx, int vcpu, struct vlapic *vlapic,
1316 int vector, need_nmi_exiting, extint_pending;
1317 uint64_t rflags, entryinfo;
1320 if (vmx->state[vcpu].nextrip != guestrip) {
1321 gi = vmcs_read(VMCS_GUEST_INTERRUPTIBILITY);
1322 if (gi & HWINTR_BLOCKING) {
1323 VCPU_CTR2(vmx->vm, vcpu, "Guest interrupt blocking "
1324 "cleared due to rip change: %#lx/%#lx",
1325 vmx->state[vcpu].nextrip, guestrip);
1326 gi &= ~HWINTR_BLOCKING;
1327 vmcs_write(VMCS_GUEST_INTERRUPTIBILITY, gi);
1331 if (vm_entry_intinfo(vmx->vm, vcpu, &entryinfo)) {
1332 KASSERT((entryinfo & VMCS_INTR_VALID) != 0, ("%s: entry "
1333 "intinfo is not valid: %#lx", __func__, entryinfo));
1335 info = vmcs_read(VMCS_ENTRY_INTR_INFO);
1336 KASSERT((info & VMCS_INTR_VALID) == 0, ("%s: cannot inject "
1337 "pending exception: %#lx/%#x", __func__, entryinfo, info));
1340 vector = info & 0xff;
1341 if (vector == IDT_BP || vector == IDT_OF) {
1343 * VT-x requires #BP and #OF to be injected as software
1346 info &= ~VMCS_INTR_T_MASK;
1347 info |= VMCS_INTR_T_SWEXCEPTION;
1350 if (info & VMCS_INTR_DEL_ERRCODE)
1351 vmcs_write(VMCS_ENTRY_EXCEPTION_ERROR, entryinfo >> 32);
1353 vmcs_write(VMCS_ENTRY_INTR_INFO, info);
1356 if (vm_nmi_pending(vmx->vm, vcpu)) {
1358 * If there are no conditions blocking NMI injection then
1359 * inject it directly here otherwise enable "NMI window
1360 * exiting" to inject it as soon as we can.
1362 * We also check for STI_BLOCKING because some implementations
1363 * don't allow NMI injection in this case. If we are running
1364 * on a processor that doesn't have this restriction it will
1365 * immediately exit and the NMI will be injected in the
1366 * "NMI window exiting" handler.
1368 need_nmi_exiting = 1;
1369 gi = vmcs_read(VMCS_GUEST_INTERRUPTIBILITY);
1370 if ((gi & (HWINTR_BLOCKING | NMI_BLOCKING)) == 0) {
1371 info = vmcs_read(VMCS_ENTRY_INTR_INFO);
1372 if ((info & VMCS_INTR_VALID) == 0) {
1373 vmx_inject_nmi(vmx, vcpu);
1374 need_nmi_exiting = 0;
1376 VCPU_CTR1(vmx->vm, vcpu, "Cannot inject NMI "
1377 "due to VM-entry intr info %#x", info);
1380 VCPU_CTR1(vmx->vm, vcpu, "Cannot inject NMI due to "
1381 "Guest Interruptibility-state %#x", gi);
1384 if (need_nmi_exiting)
1385 vmx_set_nmi_window_exiting(vmx, vcpu);
1388 extint_pending = vm_extint_pending(vmx->vm, vcpu);
1390 if (!extint_pending && virtual_interrupt_delivery) {
1391 vmx_inject_pir(vlapic);
1396 * If interrupt-window exiting is already in effect then don't bother
1397 * checking for pending interrupts. This is just an optimization and
1398 * not needed for correctness.
1400 if ((vmx->cap[vcpu].proc_ctls & PROCBASED_INT_WINDOW_EXITING) != 0) {
1401 VCPU_CTR0(vmx->vm, vcpu, "Skip interrupt injection due to "
1402 "pending int_window_exiting");
1406 if (!extint_pending) {
1407 /* Ask the local apic for a vector to inject */
1408 if (!vlapic_pending_intr(vlapic, &vector))
1412 * From the Intel SDM, Volume 3, Section "Maskable
1413 * Hardware Interrupts":
1414 * - maskable interrupt vectors [16,255] can be delivered
1415 * through the local APIC.
1417 KASSERT(vector >= 16 && vector <= 255,
1418 ("invalid vector %d from local APIC", vector));
1420 /* Ask the legacy pic for a vector to inject */
1421 vatpic_pending_intr(vmx->vm, &vector);
1424 * From the Intel SDM, Volume 3, Section "Maskable
1425 * Hardware Interrupts":
1426 * - maskable interrupt vectors [0,255] can be delivered
1427 * through the INTR pin.
1429 KASSERT(vector >= 0 && vector <= 255,
1430 ("invalid vector %d from INTR", vector));
1433 /* Check RFLAGS.IF and the interruptibility state of the guest */
1434 rflags = vmcs_read(VMCS_GUEST_RFLAGS);
1435 if ((rflags & PSL_I) == 0) {
1436 VCPU_CTR2(vmx->vm, vcpu, "Cannot inject vector %d due to "
1437 "rflags %#lx", vector, rflags);
1441 gi = vmcs_read(VMCS_GUEST_INTERRUPTIBILITY);
1442 if (gi & HWINTR_BLOCKING) {
1443 VCPU_CTR2(vmx->vm, vcpu, "Cannot inject vector %d due to "
1444 "Guest Interruptibility-state %#x", vector, gi);
1448 info = vmcs_read(VMCS_ENTRY_INTR_INFO);
1449 if (info & VMCS_INTR_VALID) {
1451 * This is expected and could happen for multiple reasons:
1452 * - A vectoring VM-entry was aborted due to astpending
1453 * - A VM-exit happened during event injection.
1454 * - An exception was injected above.
1455 * - An NMI was injected above or after "NMI window exiting"
1457 VCPU_CTR2(vmx->vm, vcpu, "Cannot inject vector %d due to "
1458 "VM-entry intr info %#x", vector, info);
1462 /* Inject the interrupt */
1463 info = VMCS_INTR_T_HWINTR | VMCS_INTR_VALID;
1465 vmcs_write(VMCS_ENTRY_INTR_INFO, info);
1467 if (!extint_pending) {
1468 /* Update the Local APIC ISR */
1469 vlapic_intr_accepted(vlapic, vector);
1471 vm_extint_clear(vmx->vm, vcpu);
1472 vatpic_intr_accepted(vmx->vm, vector);
1475 * After we accepted the current ExtINT the PIC may
1476 * have posted another one. If that is the case, set
1477 * the Interrupt Window Exiting execution control so
1478 * we can inject that one too.
1480 * Also, interrupt window exiting allows us to inject any
1481 * pending APIC vector that was preempted by the ExtINT
1482 * as soon as possible. This applies both for the software
1483 * emulated vlapic and the hardware assisted virtual APIC.
1485 vmx_set_int_window_exiting(vmx, vcpu);
1488 VCPU_CTR1(vmx->vm, vcpu, "Injecting hwintr at vector %d", vector);
1494 * Set the Interrupt Window Exiting execution control so we can inject
1495 * the interrupt as soon as blocking condition goes away.
1497 vmx_set_int_window_exiting(vmx, vcpu);
1501 * If the Virtual NMIs execution control is '1' then the logical processor
1502 * tracks virtual-NMI blocking in the Guest Interruptibility-state field of
1503 * the VMCS. An IRET instruction in VMX non-root operation will remove any
1504 * virtual-NMI blocking.
1506 * This unblocking occurs even if the IRET causes a fault. In this case the
1507 * hypervisor needs to restore virtual-NMI blocking before resuming the guest.
1510 vmx_restore_nmi_blocking(struct vmx *vmx, int vcpuid)
1514 VCPU_CTR0(vmx->vm, vcpuid, "Restore Virtual-NMI blocking");
1515 gi = vmcs_read(VMCS_GUEST_INTERRUPTIBILITY);
1516 gi |= VMCS_INTERRUPTIBILITY_NMI_BLOCKING;
1517 vmcs_write(VMCS_GUEST_INTERRUPTIBILITY, gi);
1521 vmx_clear_nmi_blocking(struct vmx *vmx, int vcpuid)
1525 VCPU_CTR0(vmx->vm, vcpuid, "Clear Virtual-NMI blocking");
1526 gi = vmcs_read(VMCS_GUEST_INTERRUPTIBILITY);
1527 gi &= ~VMCS_INTERRUPTIBILITY_NMI_BLOCKING;
1528 vmcs_write(VMCS_GUEST_INTERRUPTIBILITY, gi);
1532 vmx_assert_nmi_blocking(struct vmx *vmx, int vcpuid)
1536 gi = vmcs_read(VMCS_GUEST_INTERRUPTIBILITY);
1537 KASSERT(gi & VMCS_INTERRUPTIBILITY_NMI_BLOCKING,
1538 ("NMI blocking is not in effect %#x", gi));
1542 vmx_emulate_xsetbv(struct vmx *vmx, int vcpu, struct vm_exit *vmexit)
1544 struct vmxctx *vmxctx;
1546 const struct xsave_limits *limits;
1548 vmxctx = &vmx->ctx[vcpu];
1549 limits = vmm_get_xsave_limits();
1552 * Note that the processor raises a GP# fault on its own if
1553 * xsetbv is executed for CPL != 0, so we do not have to
1554 * emulate that fault here.
1557 /* Only xcr0 is supported. */
1558 if (vmxctx->guest_rcx != 0) {
1559 vm_inject_gp(vmx->vm, vcpu);
1563 /* We only handle xcr0 if both the host and guest have XSAVE enabled. */
1564 if (!limits->xsave_enabled || !(vmcs_read(VMCS_GUEST_CR4) & CR4_XSAVE)) {
1565 vm_inject_ud(vmx->vm, vcpu);
1569 xcrval = vmxctx->guest_rdx << 32 | (vmxctx->guest_rax & 0xffffffff);
1570 if ((xcrval & ~limits->xcr0_allowed) != 0) {
1571 vm_inject_gp(vmx->vm, vcpu);
1575 if (!(xcrval & XFEATURE_ENABLED_X87)) {
1576 vm_inject_gp(vmx->vm, vcpu);
1580 /* AVX (YMM_Hi128) requires SSE. */
1581 if (xcrval & XFEATURE_ENABLED_AVX &&
1582 (xcrval & XFEATURE_AVX) != XFEATURE_AVX) {
1583 vm_inject_gp(vmx->vm, vcpu);
1588 * AVX512 requires base AVX (YMM_Hi128) as well as OpMask,
1589 * ZMM_Hi256, and Hi16_ZMM.
1591 if (xcrval & XFEATURE_AVX512 &&
1592 (xcrval & (XFEATURE_AVX512 | XFEATURE_AVX)) !=
1593 (XFEATURE_AVX512 | XFEATURE_AVX)) {
1594 vm_inject_gp(vmx->vm, vcpu);
1599 * Intel MPX requires both bound register state flags to be
1602 if (((xcrval & XFEATURE_ENABLED_BNDREGS) != 0) !=
1603 ((xcrval & XFEATURE_ENABLED_BNDCSR) != 0)) {
1604 vm_inject_gp(vmx->vm, vcpu);
1609 * This runs "inside" vmrun() with the guest's FPU state, so
1610 * modifying xcr0 directly modifies the guest's xcr0, not the
1613 load_xcr(0, xcrval);
1618 vmx_get_guest_reg(struct vmx *vmx, int vcpu, int ident)
1620 const struct vmxctx *vmxctx;
1622 vmxctx = &vmx->ctx[vcpu];
1626 return (vmxctx->guest_rax);
1628 return (vmxctx->guest_rcx);
1630 return (vmxctx->guest_rdx);
1632 return (vmxctx->guest_rbx);
1634 return (vmcs_read(VMCS_GUEST_RSP));
1636 return (vmxctx->guest_rbp);
1638 return (vmxctx->guest_rsi);
1640 return (vmxctx->guest_rdi);
1642 return (vmxctx->guest_r8);
1644 return (vmxctx->guest_r9);
1646 return (vmxctx->guest_r10);
1648 return (vmxctx->guest_r11);
1650 return (vmxctx->guest_r12);
1652 return (vmxctx->guest_r13);
1654 return (vmxctx->guest_r14);
1656 return (vmxctx->guest_r15);
1658 panic("invalid vmx register %d", ident);
1663 vmx_set_guest_reg(struct vmx *vmx, int vcpu, int ident, uint64_t regval)
1665 struct vmxctx *vmxctx;
1667 vmxctx = &vmx->ctx[vcpu];
1671 vmxctx->guest_rax = regval;
1674 vmxctx->guest_rcx = regval;
1677 vmxctx->guest_rdx = regval;
1680 vmxctx->guest_rbx = regval;
1683 vmcs_write(VMCS_GUEST_RSP, regval);
1686 vmxctx->guest_rbp = regval;
1689 vmxctx->guest_rsi = regval;
1692 vmxctx->guest_rdi = regval;
1695 vmxctx->guest_r8 = regval;
1698 vmxctx->guest_r9 = regval;
1701 vmxctx->guest_r10 = regval;
1704 vmxctx->guest_r11 = regval;
1707 vmxctx->guest_r12 = regval;
1710 vmxctx->guest_r13 = regval;
1713 vmxctx->guest_r14 = regval;
1716 vmxctx->guest_r15 = regval;
1719 panic("invalid vmx register %d", ident);
1724 vmx_emulate_cr0_access(struct vmx *vmx, int vcpu, uint64_t exitqual)
1726 uint64_t crval, regval;
1728 /* We only handle mov to %cr0 at this time */
1729 if ((exitqual & 0xf0) != 0x00)
1732 regval = vmx_get_guest_reg(vmx, vcpu, (exitqual >> 8) & 0xf);
1734 vmcs_write(VMCS_CR0_SHADOW, regval);
1736 crval = regval | cr0_ones_mask;
1737 crval &= ~cr0_zeros_mask;
1738 vmcs_write(VMCS_GUEST_CR0, crval);
1740 if (regval & CR0_PG) {
1741 uint64_t efer, entry_ctls;
1744 * If CR0.PG is 1 and EFER.LME is 1 then EFER.LMA and
1745 * the "IA-32e mode guest" bit in VM-entry control must be
1748 efer = vmcs_read(VMCS_GUEST_IA32_EFER);
1749 if (efer & EFER_LME) {
1751 vmcs_write(VMCS_GUEST_IA32_EFER, efer);
1752 entry_ctls = vmcs_read(VMCS_ENTRY_CTLS);
1753 entry_ctls |= VM_ENTRY_GUEST_LMA;
1754 vmcs_write(VMCS_ENTRY_CTLS, entry_ctls);
1762 vmx_emulate_cr4_access(struct vmx *vmx, int vcpu, uint64_t exitqual)
1764 uint64_t crval, regval;
1766 /* We only handle mov to %cr4 at this time */
1767 if ((exitqual & 0xf0) != 0x00)
1770 regval = vmx_get_guest_reg(vmx, vcpu, (exitqual >> 8) & 0xf);
1772 vmcs_write(VMCS_CR4_SHADOW, regval);
1774 crval = regval | cr4_ones_mask;
1775 crval &= ~cr4_zeros_mask;
1776 vmcs_write(VMCS_GUEST_CR4, crval);
1782 vmx_emulate_cr8_access(struct vmx *vmx, int vcpu, uint64_t exitqual)
1784 struct vlapic *vlapic;
1788 /* We only handle mov %cr8 to/from a register at this time. */
1789 if ((exitqual & 0xe0) != 0x00) {
1793 vlapic = vm_lapic(vmx->vm, vcpu);
1794 regnum = (exitqual >> 8) & 0xf;
1795 if (exitqual & 0x10) {
1796 cr8 = vlapic_get_cr8(vlapic);
1797 vmx_set_guest_reg(vmx, vcpu, regnum, cr8);
1799 cr8 = vmx_get_guest_reg(vmx, vcpu, regnum);
1800 vlapic_set_cr8(vlapic, cr8);
1807 * From section "Guest Register State" in the Intel SDM: CPL = SS.DPL
1814 ssar = vmcs_read(VMCS_GUEST_SS_ACCESS_RIGHTS);
1815 return ((ssar >> 5) & 0x3);
1818 static enum vm_cpu_mode
1823 if (vmcs_read(VMCS_GUEST_IA32_EFER) & EFER_LMA) {
1824 csar = vmcs_read(VMCS_GUEST_CS_ACCESS_RIGHTS);
1826 return (CPU_MODE_64BIT); /* CS.L = 1 */
1828 return (CPU_MODE_COMPATIBILITY);
1829 } else if (vmcs_read(VMCS_GUEST_CR0) & CR0_PE) {
1830 return (CPU_MODE_PROTECTED);
1832 return (CPU_MODE_REAL);
1836 static enum vm_paging_mode
1837 vmx_paging_mode(void)
1840 if (!(vmcs_read(VMCS_GUEST_CR0) & CR0_PG))
1841 return (PAGING_MODE_FLAT);
1842 if (!(vmcs_read(VMCS_GUEST_CR4) & CR4_PAE))
1843 return (PAGING_MODE_32);
1844 if (vmcs_read(VMCS_GUEST_IA32_EFER) & EFER_LME)
1845 return (PAGING_MODE_64);
1847 return (PAGING_MODE_PAE);
1851 inout_str_index(struct vmx *vmx, int vcpuid, int in)
1855 enum vm_reg_name reg;
1857 reg = in ? VM_REG_GUEST_RDI : VM_REG_GUEST_RSI;
1858 error = vmx_getreg(vmx, vcpuid, reg, &val);
1859 KASSERT(error == 0, ("%s: vmx_getreg error %d", __func__, error));
1864 inout_str_count(struct vmx *vmx, int vcpuid, int rep)
1870 error = vmx_getreg(vmx, vcpuid, VM_REG_GUEST_RCX, &val);
1871 KASSERT(!error, ("%s: vmx_getreg error %d", __func__, error));
1879 inout_str_addrsize(uint32_t inst_info)
1883 size = (inst_info >> 7) & 0x7;
1886 return (2); /* 16 bit */
1888 return (4); /* 32 bit */
1890 return (8); /* 64 bit */
1892 panic("%s: invalid size encoding %d", __func__, size);
1897 inout_str_seginfo(struct vmx *vmx, int vcpuid, uint32_t inst_info, int in,
1898 struct vm_inout_str *vis)
1903 vis->seg_name = VM_REG_GUEST_ES;
1905 s = (inst_info >> 15) & 0x7;
1906 vis->seg_name = vm_segment_name(s);
1909 error = vmx_getdesc(vmx, vcpuid, vis->seg_name, &vis->seg_desc);
1910 KASSERT(error == 0, ("%s: vmx_getdesc error %d", __func__, error));
1914 vmx_paging_info(struct vm_guest_paging *paging)
1916 paging->cr3 = vmcs_guest_cr3();
1917 paging->cpl = vmx_cpl();
1918 paging->cpu_mode = vmx_cpu_mode();
1919 paging->paging_mode = vmx_paging_mode();
1923 vmexit_inst_emul(struct vm_exit *vmexit, uint64_t gpa, uint64_t gla)
1925 struct vm_guest_paging *paging;
1928 paging = &vmexit->u.inst_emul.paging;
1930 vmexit->exitcode = VM_EXITCODE_INST_EMUL;
1931 vmexit->inst_length = 0;
1932 vmexit->u.inst_emul.gpa = gpa;
1933 vmexit->u.inst_emul.gla = gla;
1934 vmx_paging_info(paging);
1935 switch (paging->cpu_mode) {
1937 vmexit->u.inst_emul.cs_base = vmcs_read(VMCS_GUEST_CS_BASE);
1938 vmexit->u.inst_emul.cs_d = 0;
1940 case CPU_MODE_PROTECTED:
1941 case CPU_MODE_COMPATIBILITY:
1942 vmexit->u.inst_emul.cs_base = vmcs_read(VMCS_GUEST_CS_BASE);
1943 csar = vmcs_read(VMCS_GUEST_CS_ACCESS_RIGHTS);
1944 vmexit->u.inst_emul.cs_d = SEG_DESC_DEF32(csar);
1947 vmexit->u.inst_emul.cs_base = 0;
1948 vmexit->u.inst_emul.cs_d = 0;
1951 vie_init(&vmexit->u.inst_emul.vie, NULL, 0);
1955 ept_fault_type(uint64_t ept_qual)
1959 if (ept_qual & EPT_VIOLATION_DATA_WRITE)
1960 fault_type = VM_PROT_WRITE;
1961 else if (ept_qual & EPT_VIOLATION_INST_FETCH)
1962 fault_type = VM_PROT_EXECUTE;
1964 fault_type= VM_PROT_READ;
1966 return (fault_type);
1970 ept_emulation_fault(uint64_t ept_qual)
1974 /* EPT fault on an instruction fetch doesn't make sense here */
1975 if (ept_qual & EPT_VIOLATION_INST_FETCH)
1978 /* EPT fault must be a read fault or a write fault */
1979 read = ept_qual & EPT_VIOLATION_DATA_READ ? 1 : 0;
1980 write = ept_qual & EPT_VIOLATION_DATA_WRITE ? 1 : 0;
1981 if ((read | write) == 0)
1985 * The EPT violation must have been caused by accessing a
1986 * guest-physical address that is a translation of a guest-linear
1989 if ((ept_qual & EPT_VIOLATION_GLA_VALID) == 0 ||
1990 (ept_qual & EPT_VIOLATION_XLAT_VALID) == 0) {
1998 apic_access_virtualization(struct vmx *vmx, int vcpuid)
2000 uint32_t proc_ctls2;
2002 proc_ctls2 = vmx->cap[vcpuid].proc_ctls2;
2003 return ((proc_ctls2 & PROCBASED2_VIRTUALIZE_APIC_ACCESSES) ? 1 : 0);
2007 x2apic_virtualization(struct vmx *vmx, int vcpuid)
2009 uint32_t proc_ctls2;
2011 proc_ctls2 = vmx->cap[vcpuid].proc_ctls2;
2012 return ((proc_ctls2 & PROCBASED2_VIRTUALIZE_X2APIC_MODE) ? 1 : 0);
2016 vmx_handle_apic_write(struct vmx *vmx, int vcpuid, struct vlapic *vlapic,
2019 int error, handled, offset;
2020 uint32_t *apic_regs, vector;
2024 offset = APIC_WRITE_OFFSET(qual);
2026 if (!apic_access_virtualization(vmx, vcpuid)) {
2028 * In general there should not be any APIC write VM-exits
2029 * unless APIC-access virtualization is enabled.
2031 * However self-IPI virtualization can legitimately trigger
2032 * an APIC-write VM-exit so treat it specially.
2034 if (x2apic_virtualization(vmx, vcpuid) &&
2035 offset == APIC_OFFSET_SELF_IPI) {
2036 apic_regs = (uint32_t *)(vlapic->apic_page);
2037 vector = apic_regs[APIC_OFFSET_SELF_IPI / 4];
2038 vlapic_self_ipi_handler(vlapic, vector);
2045 case APIC_OFFSET_ID:
2046 vlapic_id_write_handler(vlapic);
2048 case APIC_OFFSET_LDR:
2049 vlapic_ldr_write_handler(vlapic);
2051 case APIC_OFFSET_DFR:
2052 vlapic_dfr_write_handler(vlapic);
2054 case APIC_OFFSET_SVR:
2055 vlapic_svr_write_handler(vlapic);
2057 case APIC_OFFSET_ESR:
2058 vlapic_esr_write_handler(vlapic);
2060 case APIC_OFFSET_ICR_LOW:
2062 error = vlapic_icrlo_write_handler(vlapic, &retu);
2063 if (error != 0 || retu)
2064 handled = UNHANDLED;
2066 case APIC_OFFSET_CMCI_LVT:
2067 case APIC_OFFSET_TIMER_LVT ... APIC_OFFSET_ERROR_LVT:
2068 vlapic_lvt_write_handler(vlapic, offset);
2070 case APIC_OFFSET_TIMER_ICR:
2071 vlapic_icrtmr_write_handler(vlapic);
2073 case APIC_OFFSET_TIMER_DCR:
2074 vlapic_dcr_write_handler(vlapic);
2077 handled = UNHANDLED;
2084 apic_access_fault(struct vmx *vmx, int vcpuid, uint64_t gpa)
2087 if (apic_access_virtualization(vmx, vcpuid) &&
2088 (gpa >= DEFAULT_APIC_BASE && gpa < DEFAULT_APIC_BASE + PAGE_SIZE))
2095 vmx_handle_apic_access(struct vmx *vmx, int vcpuid, struct vm_exit *vmexit)
2098 int access_type, offset, allowed;
2100 if (!apic_access_virtualization(vmx, vcpuid))
2103 qual = vmexit->u.vmx.exit_qualification;
2104 access_type = APIC_ACCESS_TYPE(qual);
2105 offset = APIC_ACCESS_OFFSET(qual);
2108 if (access_type == 0) {
2110 * Read data access to the following registers is expected.
2113 case APIC_OFFSET_APR:
2114 case APIC_OFFSET_PPR:
2115 case APIC_OFFSET_RRR:
2116 case APIC_OFFSET_CMCI_LVT:
2117 case APIC_OFFSET_TIMER_CCR:
2123 } else if (access_type == 1) {
2125 * Write data access to the following registers is expected.
2128 case APIC_OFFSET_VER:
2129 case APIC_OFFSET_APR:
2130 case APIC_OFFSET_PPR:
2131 case APIC_OFFSET_RRR:
2132 case APIC_OFFSET_ISR0 ... APIC_OFFSET_ISR7:
2133 case APIC_OFFSET_TMR0 ... APIC_OFFSET_TMR7:
2134 case APIC_OFFSET_IRR0 ... APIC_OFFSET_IRR7:
2135 case APIC_OFFSET_CMCI_LVT:
2136 case APIC_OFFSET_TIMER_CCR:
2145 vmexit_inst_emul(vmexit, DEFAULT_APIC_BASE + offset,
2150 * Regardless of whether the APIC-access is allowed this handler
2151 * always returns UNHANDLED:
2152 * - if the access is allowed then it is handled by emulating the
2153 * instruction that caused the VM-exit (outside the critical section)
2154 * - if the access is not allowed then it will be converted to an
2155 * exitcode of VM_EXITCODE_VMX and will be dealt with in userland.
2160 static enum task_switch_reason
2161 vmx_task_switch_reason(uint64_t qual)
2165 reason = (qual >> 30) & 0x3;
2174 return (TSR_IDT_GATE);
2176 panic("%s: invalid reason %d", __func__, reason);
2181 emulate_wrmsr(struct vmx *vmx, int vcpuid, u_int num, uint64_t val, bool *retu)
2186 error = lapic_wrmsr(vmx->vm, vcpuid, num, val, retu);
2188 error = vmx_wrmsr(vmx, vcpuid, num, val, retu);
2194 emulate_rdmsr(struct vmx *vmx, int vcpuid, u_int num, bool *retu)
2196 struct vmxctx *vmxctx;
2202 error = lapic_rdmsr(vmx->vm, vcpuid, num, &result, retu);
2204 error = vmx_rdmsr(vmx, vcpuid, num, &result, retu);
2208 vmxctx = &vmx->ctx[vcpuid];
2209 error = vmxctx_setreg(vmxctx, VM_REG_GUEST_RAX, eax);
2210 KASSERT(error == 0, ("vmxctx_setreg(rax) error %d", error));
2213 error = vmxctx_setreg(vmxctx, VM_REG_GUEST_RDX, edx);
2214 KASSERT(error == 0, ("vmxctx_setreg(rdx) error %d", error));
2221 vmx_exit_process(struct vmx *vmx, int vcpu, struct vm_exit *vmexit)
2223 int error, errcode, errcode_valid, handled, in;
2224 struct vmxctx *vmxctx;
2225 struct vlapic *vlapic;
2226 struct vm_inout_str *vis;
2227 struct vm_task_switch *ts;
2228 uint32_t eax, ecx, edx, idtvec_info, idtvec_err, intr_info, inst_info;
2229 uint32_t intr_type, intr_vec, reason;
2230 uint64_t exitintinfo, qual, gpa;
2233 CTASSERT((PINBASED_CTLS_ONE_SETTING & PINBASED_VIRTUAL_NMI) != 0);
2234 CTASSERT((PINBASED_CTLS_ONE_SETTING & PINBASED_NMI_EXITING) != 0);
2236 handled = UNHANDLED;
2237 vmxctx = &vmx->ctx[vcpu];
2239 qual = vmexit->u.vmx.exit_qualification;
2240 reason = vmexit->u.vmx.exit_reason;
2241 vmexit->exitcode = VM_EXITCODE_BOGUS;
2243 vmm_stat_incr(vmx->vm, vcpu, VMEXIT_COUNT, 1);
2244 SDT_PROBE3(vmm, vmx, exit, entry, vmx, vcpu, vmexit);
2247 * VM-entry failures during or after loading guest state.
2249 * These VM-exits are uncommon but must be handled specially
2250 * as most VM-exit fields are not populated as usual.
2252 if (__predict_false(reason == EXIT_REASON_MCE_DURING_ENTRY)) {
2253 VCPU_CTR0(vmx->vm, vcpu, "Handling MCE during VM-entry");
2254 __asm __volatile("int $18");
2259 * VM exits that can be triggered during event delivery need to
2260 * be handled specially by re-injecting the event if the IDT
2261 * vectoring information field's valid bit is set.
2263 * See "Information for VM Exits During Event Delivery" in Intel SDM
2266 idtvec_info = vmcs_idt_vectoring_info();
2267 if (idtvec_info & VMCS_IDT_VEC_VALID) {
2268 idtvec_info &= ~(1 << 12); /* clear undefined bit */
2269 exitintinfo = idtvec_info;
2270 if (idtvec_info & VMCS_IDT_VEC_ERRCODE_VALID) {
2271 idtvec_err = vmcs_idt_vectoring_err();
2272 exitintinfo |= (uint64_t)idtvec_err << 32;
2274 error = vm_exit_intinfo(vmx->vm, vcpu, exitintinfo);
2275 KASSERT(error == 0, ("%s: vm_set_intinfo error %d",
2279 * If 'virtual NMIs' are being used and the VM-exit
2280 * happened while injecting an NMI during the previous
2281 * VM-entry, then clear "blocking by NMI" in the
2282 * Guest Interruptibility-State so the NMI can be
2283 * reinjected on the subsequent VM-entry.
2285 * However, if the NMI was being delivered through a task
2286 * gate, then the new task must start execution with NMIs
2287 * blocked so don't clear NMI blocking in this case.
2289 intr_type = idtvec_info & VMCS_INTR_T_MASK;
2290 if (intr_type == VMCS_INTR_T_NMI) {
2291 if (reason != EXIT_REASON_TASK_SWITCH)
2292 vmx_clear_nmi_blocking(vmx, vcpu);
2294 vmx_assert_nmi_blocking(vmx, vcpu);
2298 * Update VM-entry instruction length if the event being
2299 * delivered was a software interrupt or software exception.
2301 if (intr_type == VMCS_INTR_T_SWINTR ||
2302 intr_type == VMCS_INTR_T_PRIV_SWEXCEPTION ||
2303 intr_type == VMCS_INTR_T_SWEXCEPTION) {
2304 vmcs_write(VMCS_ENTRY_INST_LENGTH, vmexit->inst_length);
2309 case EXIT_REASON_TASK_SWITCH:
2310 ts = &vmexit->u.task_switch;
2311 ts->tsssel = qual & 0xffff;
2312 ts->reason = vmx_task_switch_reason(qual);
2314 ts->errcode_valid = 0;
2315 vmx_paging_info(&ts->paging);
2317 * If the task switch was due to a CALL, JMP, IRET, software
2318 * interrupt (INT n) or software exception (INT3, INTO),
2319 * then the saved %rip references the instruction that caused
2320 * the task switch. The instruction length field in the VMCS
2321 * is valid in this case.
2323 * In all other cases (e.g., NMI, hardware exception) the
2324 * saved %rip is one that would have been saved in the old TSS
2325 * had the task switch completed normally so the instruction
2326 * length field is not needed in this case and is explicitly
2329 if (ts->reason == TSR_IDT_GATE) {
2330 KASSERT(idtvec_info & VMCS_IDT_VEC_VALID,
2331 ("invalid idtvec_info %#x for IDT task switch",
2333 intr_type = idtvec_info & VMCS_INTR_T_MASK;
2334 if (intr_type != VMCS_INTR_T_SWINTR &&
2335 intr_type != VMCS_INTR_T_SWEXCEPTION &&
2336 intr_type != VMCS_INTR_T_PRIV_SWEXCEPTION) {
2337 /* Task switch triggered by external event */
2339 vmexit->inst_length = 0;
2340 if (idtvec_info & VMCS_IDT_VEC_ERRCODE_VALID) {
2341 ts->errcode_valid = 1;
2342 ts->errcode = vmcs_idt_vectoring_err();
2346 vmexit->exitcode = VM_EXITCODE_TASK_SWITCH;
2347 SDT_PROBE4(vmm, vmx, exit, taskswitch, vmx, vcpu, vmexit, ts);
2348 VCPU_CTR4(vmx->vm, vcpu, "task switch reason %d, tss 0x%04x, "
2349 "%s errcode 0x%016lx", ts->reason, ts->tsssel,
2350 ts->ext ? "external" : "internal",
2351 ((uint64_t)ts->errcode << 32) | ts->errcode_valid);
2353 case EXIT_REASON_CR_ACCESS:
2354 vmm_stat_incr(vmx->vm, vcpu, VMEXIT_CR_ACCESS, 1);
2355 SDT_PROBE4(vmm, vmx, exit, craccess, vmx, vcpu, vmexit, qual);
2356 switch (qual & 0xf) {
2358 handled = vmx_emulate_cr0_access(vmx, vcpu, qual);
2361 handled = vmx_emulate_cr4_access(vmx, vcpu, qual);
2364 handled = vmx_emulate_cr8_access(vmx, vcpu, qual);
2368 case EXIT_REASON_RDMSR:
2369 vmm_stat_incr(vmx->vm, vcpu, VMEXIT_RDMSR, 1);
2371 ecx = vmxctx->guest_rcx;
2372 VCPU_CTR1(vmx->vm, vcpu, "rdmsr 0x%08x", ecx);
2373 SDT_PROBE4(vmm, vmx, exit, rdmsr, vmx, vcpu, vmexit, ecx);
2374 error = emulate_rdmsr(vmx, vcpu, ecx, &retu);
2376 vmexit->exitcode = VM_EXITCODE_RDMSR;
2377 vmexit->u.msr.code = ecx;
2381 /* Return to userspace with a valid exitcode */
2382 KASSERT(vmexit->exitcode != VM_EXITCODE_BOGUS,
2383 ("emulate_rdmsr retu with bogus exitcode"));
2386 case EXIT_REASON_WRMSR:
2387 vmm_stat_incr(vmx->vm, vcpu, VMEXIT_WRMSR, 1);
2389 eax = vmxctx->guest_rax;
2390 ecx = vmxctx->guest_rcx;
2391 edx = vmxctx->guest_rdx;
2392 VCPU_CTR2(vmx->vm, vcpu, "wrmsr 0x%08x value 0x%016lx",
2393 ecx, (uint64_t)edx << 32 | eax);
2394 SDT_PROBE5(vmm, vmx, exit, wrmsr, vmx, vmexit, vcpu, ecx,
2395 (uint64_t)edx << 32 | eax);
2396 error = emulate_wrmsr(vmx, vcpu, ecx,
2397 (uint64_t)edx << 32 | eax, &retu);
2399 vmexit->exitcode = VM_EXITCODE_WRMSR;
2400 vmexit->u.msr.code = ecx;
2401 vmexit->u.msr.wval = (uint64_t)edx << 32 | eax;
2405 /* Return to userspace with a valid exitcode */
2406 KASSERT(vmexit->exitcode != VM_EXITCODE_BOGUS,
2407 ("emulate_wrmsr retu with bogus exitcode"));
2410 case EXIT_REASON_HLT:
2411 vmm_stat_incr(vmx->vm, vcpu, VMEXIT_HLT, 1);
2412 SDT_PROBE3(vmm, vmx, exit, halt, vmx, vcpu, vmexit);
2413 vmexit->exitcode = VM_EXITCODE_HLT;
2414 vmexit->u.hlt.rflags = vmcs_read(VMCS_GUEST_RFLAGS);
2415 if (virtual_interrupt_delivery)
2416 vmexit->u.hlt.intr_status =
2417 vmcs_read(VMCS_GUEST_INTR_STATUS);
2419 vmexit->u.hlt.intr_status = 0;
2421 case EXIT_REASON_MTF:
2422 vmm_stat_incr(vmx->vm, vcpu, VMEXIT_MTRAP, 1);
2423 SDT_PROBE3(vmm, vmx, exit, mtrap, vmx, vcpu, vmexit);
2424 vmexit->exitcode = VM_EXITCODE_MTRAP;
2425 vmexit->inst_length = 0;
2427 case EXIT_REASON_PAUSE:
2428 vmm_stat_incr(vmx->vm, vcpu, VMEXIT_PAUSE, 1);
2429 SDT_PROBE3(vmm, vmx, exit, pause, vmx, vcpu, vmexit);
2430 vmexit->exitcode = VM_EXITCODE_PAUSE;
2432 case EXIT_REASON_INTR_WINDOW:
2433 vmm_stat_incr(vmx->vm, vcpu, VMEXIT_INTR_WINDOW, 1);
2434 SDT_PROBE3(vmm, vmx, exit, intrwindow, vmx, vcpu, vmexit);
2435 vmx_clear_int_window_exiting(vmx, vcpu);
2437 case EXIT_REASON_EXT_INTR:
2439 * External interrupts serve only to cause VM exits and allow
2440 * the host interrupt handler to run.
2442 * If this external interrupt triggers a virtual interrupt
2443 * to a VM, then that state will be recorded by the
2444 * host interrupt handler in the VM's softc. We will inject
2445 * this virtual interrupt during the subsequent VM enter.
2447 intr_info = vmcs_read(VMCS_EXIT_INTR_INFO);
2448 SDT_PROBE4(vmm, vmx, exit, interrupt,
2449 vmx, vcpu, vmexit, intr_info);
2452 * XXX: Ignore this exit if VMCS_INTR_VALID is not set.
2453 * This appears to be a bug in VMware Fusion?
2455 if (!(intr_info & VMCS_INTR_VALID))
2457 KASSERT((intr_info & VMCS_INTR_VALID) != 0 &&
2458 (intr_info & VMCS_INTR_T_MASK) == VMCS_INTR_T_HWINTR,
2459 ("VM exit interruption info invalid: %#x", intr_info));
2460 vmx_trigger_hostintr(intr_info & 0xff);
2463 * This is special. We want to treat this as an 'handled'
2464 * VM-exit but not increment the instruction pointer.
2466 vmm_stat_incr(vmx->vm, vcpu, VMEXIT_EXTINT, 1);
2468 case EXIT_REASON_NMI_WINDOW:
2469 SDT_PROBE3(vmm, vmx, exit, nmiwindow, vmx, vcpu, vmexit);
2470 /* Exit to allow the pending virtual NMI to be injected */
2471 if (vm_nmi_pending(vmx->vm, vcpu))
2472 vmx_inject_nmi(vmx, vcpu);
2473 vmx_clear_nmi_window_exiting(vmx, vcpu);
2474 vmm_stat_incr(vmx->vm, vcpu, VMEXIT_NMI_WINDOW, 1);
2476 case EXIT_REASON_INOUT:
2477 vmm_stat_incr(vmx->vm, vcpu, VMEXIT_INOUT, 1);
2478 vmexit->exitcode = VM_EXITCODE_INOUT;
2479 vmexit->u.inout.bytes = (qual & 0x7) + 1;
2480 vmexit->u.inout.in = in = (qual & 0x8) ? 1 : 0;
2481 vmexit->u.inout.string = (qual & 0x10) ? 1 : 0;
2482 vmexit->u.inout.rep = (qual & 0x20) ? 1 : 0;
2483 vmexit->u.inout.port = (uint16_t)(qual >> 16);
2484 vmexit->u.inout.eax = (uint32_t)(vmxctx->guest_rax);
2485 if (vmexit->u.inout.string) {
2486 inst_info = vmcs_read(VMCS_EXIT_INSTRUCTION_INFO);
2487 vmexit->exitcode = VM_EXITCODE_INOUT_STR;
2488 vis = &vmexit->u.inout_str;
2489 vmx_paging_info(&vis->paging);
2490 vis->rflags = vmcs_read(VMCS_GUEST_RFLAGS);
2491 vis->cr0 = vmcs_read(VMCS_GUEST_CR0);
2492 vis->index = inout_str_index(vmx, vcpu, in);
2493 vis->count = inout_str_count(vmx, vcpu, vis->inout.rep);
2494 vis->addrsize = inout_str_addrsize(inst_info);
2495 inout_str_seginfo(vmx, vcpu, inst_info, in, vis);
2497 SDT_PROBE3(vmm, vmx, exit, inout, vmx, vcpu, vmexit);
2499 case EXIT_REASON_CPUID:
2500 vmm_stat_incr(vmx->vm, vcpu, VMEXIT_CPUID, 1);
2501 SDT_PROBE3(vmm, vmx, exit, cpuid, vmx, vcpu, vmexit);
2502 handled = vmx_handle_cpuid(vmx->vm, vcpu, vmxctx);
2504 case EXIT_REASON_EXCEPTION:
2505 vmm_stat_incr(vmx->vm, vcpu, VMEXIT_EXCEPTION, 1);
2506 intr_info = vmcs_read(VMCS_EXIT_INTR_INFO);
2507 KASSERT((intr_info & VMCS_INTR_VALID) != 0,
2508 ("VM exit interruption info invalid: %#x", intr_info));
2510 intr_vec = intr_info & 0xff;
2511 intr_type = intr_info & VMCS_INTR_T_MASK;
2514 * If Virtual NMIs control is 1 and the VM-exit is due to a
2515 * fault encountered during the execution of IRET then we must
2516 * restore the state of "virtual-NMI blocking" before resuming
2519 * See "Resuming Guest Software after Handling an Exception".
2520 * See "Information for VM Exits Due to Vectored Events".
2522 if ((idtvec_info & VMCS_IDT_VEC_VALID) == 0 &&
2523 (intr_vec != IDT_DF) &&
2524 (intr_info & EXIT_QUAL_NMIUDTI) != 0)
2525 vmx_restore_nmi_blocking(vmx, vcpu);
2528 * The NMI has already been handled in vmx_exit_handle_nmi().
2530 if (intr_type == VMCS_INTR_T_NMI)
2534 * Call the machine check handler by hand. Also don't reflect
2535 * the machine check back into the guest.
2537 if (intr_vec == IDT_MC) {
2538 VCPU_CTR0(vmx->vm, vcpu, "Vectoring to MCE handler");
2539 __asm __volatile("int $18");
2543 if (intr_vec == IDT_PF) {
2544 error = vmxctx_setreg(vmxctx, VM_REG_GUEST_CR2, qual);
2545 KASSERT(error == 0, ("%s: vmxctx_setreg(cr2) error %d",
2550 * Software exceptions exhibit trap-like behavior. This in
2551 * turn requires populating the VM-entry instruction length
2552 * so that the %rip in the trap frame is past the INT3/INTO
2555 if (intr_type == VMCS_INTR_T_SWEXCEPTION)
2556 vmcs_write(VMCS_ENTRY_INST_LENGTH, vmexit->inst_length);
2558 /* Reflect all other exceptions back into the guest */
2559 errcode_valid = errcode = 0;
2560 if (intr_info & VMCS_INTR_DEL_ERRCODE) {
2562 errcode = vmcs_read(VMCS_EXIT_INTR_ERRCODE);
2564 VCPU_CTR2(vmx->vm, vcpu, "Reflecting exception %d/%#x into "
2565 "the guest", intr_vec, errcode);
2566 SDT_PROBE5(vmm, vmx, exit, exception,
2567 vmx, vcpu, vmexit, intr_vec, errcode);
2568 error = vm_inject_exception(vmx->vm, vcpu, intr_vec,
2569 errcode_valid, errcode, 0);
2570 KASSERT(error == 0, ("%s: vm_inject_exception error %d",
2574 case EXIT_REASON_EPT_FAULT:
2576 * If 'gpa' lies within the address space allocated to
2577 * memory then this must be a nested page fault otherwise
2578 * this must be an instruction that accesses MMIO space.
2581 if (vm_mem_allocated(vmx->vm, vcpu, gpa) ||
2582 apic_access_fault(vmx, vcpu, gpa)) {
2583 vmexit->exitcode = VM_EXITCODE_PAGING;
2584 vmexit->inst_length = 0;
2585 vmexit->u.paging.gpa = gpa;
2586 vmexit->u.paging.fault_type = ept_fault_type(qual);
2587 vmm_stat_incr(vmx->vm, vcpu, VMEXIT_NESTED_FAULT, 1);
2588 SDT_PROBE5(vmm, vmx, exit, nestedfault,
2589 vmx, vcpu, vmexit, gpa, qual);
2590 } else if (ept_emulation_fault(qual)) {
2591 vmexit_inst_emul(vmexit, gpa, vmcs_gla());
2592 vmm_stat_incr(vmx->vm, vcpu, VMEXIT_INST_EMUL, 1);
2593 SDT_PROBE4(vmm, vmx, exit, mmiofault,
2594 vmx, vcpu, vmexit, gpa);
2597 * If Virtual NMIs control is 1 and the VM-exit is due to an
2598 * EPT fault during the execution of IRET then we must restore
2599 * the state of "virtual-NMI blocking" before resuming.
2601 * See description of "NMI unblocking due to IRET" in
2602 * "Exit Qualification for EPT Violations".
2604 if ((idtvec_info & VMCS_IDT_VEC_VALID) == 0 &&
2605 (qual & EXIT_QUAL_NMIUDTI) != 0)
2606 vmx_restore_nmi_blocking(vmx, vcpu);
2608 case EXIT_REASON_VIRTUALIZED_EOI:
2609 vmexit->exitcode = VM_EXITCODE_IOAPIC_EOI;
2610 vmexit->u.ioapic_eoi.vector = qual & 0xFF;
2611 SDT_PROBE3(vmm, vmx, exit, eoi, vmx, vcpu, vmexit);
2612 vmexit->inst_length = 0; /* trap-like */
2614 case EXIT_REASON_APIC_ACCESS:
2615 SDT_PROBE3(vmm, vmx, exit, apicaccess, vmx, vcpu, vmexit);
2616 handled = vmx_handle_apic_access(vmx, vcpu, vmexit);
2618 case EXIT_REASON_APIC_WRITE:
2620 * APIC-write VM exit is trap-like so the %rip is already
2621 * pointing to the next instruction.
2623 vmexit->inst_length = 0;
2624 vlapic = vm_lapic(vmx->vm, vcpu);
2625 SDT_PROBE4(vmm, vmx, exit, apicwrite,
2626 vmx, vcpu, vmexit, vlapic);
2627 handled = vmx_handle_apic_write(vmx, vcpu, vlapic, qual);
2629 case EXIT_REASON_XSETBV:
2630 SDT_PROBE3(vmm, vmx, exit, xsetbv, vmx, vcpu, vmexit);
2631 handled = vmx_emulate_xsetbv(vmx, vcpu, vmexit);
2633 case EXIT_REASON_MONITOR:
2634 SDT_PROBE3(vmm, vmx, exit, monitor, vmx, vcpu, vmexit);
2635 vmexit->exitcode = VM_EXITCODE_MONITOR;
2637 case EXIT_REASON_MWAIT:
2638 SDT_PROBE3(vmm, vmx, exit, mwait, vmx, vcpu, vmexit);
2639 vmexit->exitcode = VM_EXITCODE_MWAIT;
2642 SDT_PROBE4(vmm, vmx, exit, unknown,
2643 vmx, vcpu, vmexit, reason);
2644 vmm_stat_incr(vmx->vm, vcpu, VMEXIT_UNKNOWN, 1);
2650 * It is possible that control is returned to userland
2651 * even though we were able to handle the VM exit in the
2654 * In such a case we want to make sure that the userland
2655 * restarts guest execution at the instruction *after*
2656 * the one we just processed. Therefore we update the
2657 * guest rip in the VMCS and in 'vmexit'.
2659 vmexit->rip += vmexit->inst_length;
2660 vmexit->inst_length = 0;
2661 vmcs_write(VMCS_GUEST_RIP, vmexit->rip);
2663 if (vmexit->exitcode == VM_EXITCODE_BOGUS) {
2665 * If this VM exit was not claimed by anybody then
2666 * treat it as a generic VMX exit.
2668 vmexit->exitcode = VM_EXITCODE_VMX;
2669 vmexit->u.vmx.status = VM_SUCCESS;
2670 vmexit->u.vmx.inst_type = 0;
2671 vmexit->u.vmx.inst_error = 0;
2674 * The exitcode and collateral have been populated.
2675 * The VM exit will be processed further in userland.
2680 SDT_PROBE4(vmm, vmx, exit, return,
2681 vmx, vcpu, vmexit, handled);
2685 static __inline void
2686 vmx_exit_inst_error(struct vmxctx *vmxctx, int rc, struct vm_exit *vmexit)
2689 KASSERT(vmxctx->inst_fail_status != VM_SUCCESS,
2690 ("vmx_exit_inst_error: invalid inst_fail_status %d",
2691 vmxctx->inst_fail_status));
2693 vmexit->inst_length = 0;
2694 vmexit->exitcode = VM_EXITCODE_VMX;
2695 vmexit->u.vmx.status = vmxctx->inst_fail_status;
2696 vmexit->u.vmx.inst_error = vmcs_instruction_error();
2697 vmexit->u.vmx.exit_reason = ~0;
2698 vmexit->u.vmx.exit_qualification = ~0;
2701 case VMX_VMRESUME_ERROR:
2702 case VMX_VMLAUNCH_ERROR:
2703 case VMX_INVEPT_ERROR:
2704 vmexit->u.vmx.inst_type = rc;
2707 panic("vm_exit_inst_error: vmx_enter_guest returned %d", rc);
2712 * If the NMI-exiting VM execution control is set to '1' then an NMI in
2713 * non-root operation causes a VM-exit. NMI blocking is in effect so it is
2714 * sufficient to simply vector to the NMI handler via a software interrupt.
2715 * However, this must be done before maskable interrupts are enabled
2716 * otherwise the "iret" issued by an interrupt handler will incorrectly
2717 * clear NMI blocking.
2719 static __inline void
2720 vmx_exit_handle_nmi(struct vmx *vmx, int vcpuid, struct vm_exit *vmexit)
2724 KASSERT((read_rflags() & PSL_I) == 0, ("interrupts enabled"));
2726 if (vmexit->u.vmx.exit_reason != EXIT_REASON_EXCEPTION)
2729 intr_info = vmcs_read(VMCS_EXIT_INTR_INFO);
2730 KASSERT((intr_info & VMCS_INTR_VALID) != 0,
2731 ("VM exit interruption info invalid: %#x", intr_info));
2733 if ((intr_info & VMCS_INTR_T_MASK) == VMCS_INTR_T_NMI) {
2734 KASSERT((intr_info & 0xff) == IDT_NMI, ("VM exit due "
2735 "to NMI has invalid vector: %#x", intr_info));
2736 VCPU_CTR0(vmx->vm, vcpuid, "Vectoring to NMI handler");
2737 __asm __volatile("int $2");
2741 static __inline void
2742 vmx_dr_enter_guest(struct vmxctx *vmxctx)
2746 /* Save host control debug registers. */
2747 vmxctx->host_dr7 = rdr7();
2748 vmxctx->host_debugctl = rdmsr(MSR_DEBUGCTLMSR);
2751 * Disable debugging in DR7 and DEBUGCTL to avoid triggering
2752 * exceptions in the host based on the guest DRx values. The
2753 * guest DR7 and DEBUGCTL are saved/restored in the VMCS.
2756 wrmsr(MSR_DEBUGCTLMSR, 0);
2759 * Disable single stepping the kernel to avoid corrupting the
2760 * guest DR6. A debugger might still be able to corrupt the
2761 * guest DR6 by setting a breakpoint after this point and then
2764 rflags = read_rflags();
2765 vmxctx->host_tf = rflags & PSL_T;
2766 write_rflags(rflags & ~PSL_T);
2768 /* Save host debug registers. */
2769 vmxctx->host_dr0 = rdr0();
2770 vmxctx->host_dr1 = rdr1();
2771 vmxctx->host_dr2 = rdr2();
2772 vmxctx->host_dr3 = rdr3();
2773 vmxctx->host_dr6 = rdr6();
2775 /* Restore guest debug registers. */
2776 load_dr0(vmxctx->guest_dr0);
2777 load_dr1(vmxctx->guest_dr1);
2778 load_dr2(vmxctx->guest_dr2);
2779 load_dr3(vmxctx->guest_dr3);
2780 load_dr6(vmxctx->guest_dr6);
2783 static __inline void
2784 vmx_dr_leave_guest(struct vmxctx *vmxctx)
2787 /* Save guest debug registers. */
2788 vmxctx->guest_dr0 = rdr0();
2789 vmxctx->guest_dr1 = rdr1();
2790 vmxctx->guest_dr2 = rdr2();
2791 vmxctx->guest_dr3 = rdr3();
2792 vmxctx->guest_dr6 = rdr6();
2795 * Restore host debug registers. Restore DR7, DEBUGCTL, and
2798 load_dr0(vmxctx->host_dr0);
2799 load_dr1(vmxctx->host_dr1);
2800 load_dr2(vmxctx->host_dr2);
2801 load_dr3(vmxctx->host_dr3);
2802 load_dr6(vmxctx->host_dr6);
2803 wrmsr(MSR_DEBUGCTLMSR, vmxctx->host_debugctl);
2804 load_dr7(vmxctx->host_dr7);
2805 write_rflags(read_rflags() | vmxctx->host_tf);
2809 vmx_run(void *arg, int vcpu, register_t rip, pmap_t pmap,
2810 struct vm_eventinfo *evinfo)
2812 int rc, handled, launched;
2815 struct vmxctx *vmxctx;
2817 struct vm_exit *vmexit;
2818 struct vlapic *vlapic;
2819 uint32_t exit_reason;
2823 vmcs = &vmx->vmcs[vcpu];
2824 vmxctx = &vmx->ctx[vcpu];
2825 vlapic = vm_lapic(vm, vcpu);
2826 vmexit = vm_exitinfo(vm, vcpu);
2829 KASSERT(vmxctx->pmap == pmap,
2830 ("pmap %p different than ctx pmap %p", pmap, vmxctx->pmap));
2832 vmx_msr_guest_enter(vmx, vcpu);
2838 * We do this every time because we may setup the virtual machine
2839 * from a different process than the one that actually runs it.
2841 * If the life of a virtual machine was spent entirely in the context
2842 * of a single process we could do this once in vmx_vminit().
2844 vmcs_write(VMCS_HOST_CR3, rcr3());
2846 vmcs_write(VMCS_GUEST_RIP, rip);
2847 vmx_set_pcpu_defaults(vmx, vcpu, pmap);
2849 KASSERT(vmcs_guest_rip() == rip, ("%s: vmcs guest rip mismatch "
2850 "%#lx/%#lx", __func__, vmcs_guest_rip(), rip));
2852 handled = UNHANDLED;
2854 * Interrupts are disabled from this point on until the
2855 * guest starts executing. This is done for the following
2858 * If an AST is asserted on this thread after the check below,
2859 * then the IPI_AST notification will not be lost, because it
2860 * will cause a VM exit due to external interrupt as soon as
2861 * the guest state is loaded.
2863 * A posted interrupt after 'vmx_inject_interrupts()' will
2864 * not be "lost" because it will be held pending in the host
2865 * APIC because interrupts are disabled. The pending interrupt
2866 * will be recognized as soon as the guest state is loaded.
2868 * The same reasoning applies to the IPI generated by
2869 * pmap_invalidate_ept().
2872 vmx_inject_interrupts(vmx, vcpu, vlapic, rip);
2875 * Check for vcpu suspension after injecting events because
2876 * vmx_inject_interrupts() can suspend the vcpu due to a
2879 if (vcpu_suspended(evinfo)) {
2881 vm_exit_suspended(vmx->vm, vcpu, rip);
2885 if (vcpu_rendezvous_pending(evinfo)) {
2887 vm_exit_rendezvous(vmx->vm, vcpu, rip);
2891 if (vcpu_reqidle(evinfo)) {
2893 vm_exit_reqidle(vmx->vm, vcpu, rip);
2897 if (vcpu_should_yield(vm, vcpu)) {
2899 vm_exit_astpending(vmx->vm, vcpu, rip);
2900 vmx_astpending_trace(vmx, vcpu, rip);
2905 if (vcpu_debugged(vm, vcpu)) {
2907 vm_exit_debug(vmx->vm, vcpu, rip);
2911 vmx_run_trace(vmx, vcpu);
2912 vmx_dr_enter_guest(vmxctx);
2913 rc = vmx_enter_guest(vmxctx, vmx, launched);
2914 vmx_dr_leave_guest(vmxctx);
2916 /* Collect some information for VM exit processing */
2917 vmexit->rip = rip = vmcs_guest_rip();
2918 vmexit->inst_length = vmexit_instruction_length();
2919 vmexit->u.vmx.exit_reason = exit_reason = vmcs_exit_reason();
2920 vmexit->u.vmx.exit_qualification = vmcs_exit_qualification();
2922 /* Update 'nextrip' */
2923 vmx->state[vcpu].nextrip = rip;
2925 if (rc == VMX_GUEST_VMEXIT) {
2926 vmx_exit_handle_nmi(vmx, vcpu, vmexit);
2928 handled = vmx_exit_process(vmx, vcpu, vmexit);
2931 vmx_exit_inst_error(vmxctx, rc, vmexit);
2934 vmx_exit_trace(vmx, vcpu, rip, exit_reason, handled);
2939 * If a VM exit has been handled then the exitcode must be BOGUS
2940 * If a VM exit is not handled then the exitcode must not be BOGUS
2942 if ((handled && vmexit->exitcode != VM_EXITCODE_BOGUS) ||
2943 (!handled && vmexit->exitcode == VM_EXITCODE_BOGUS)) {
2944 panic("Mismatch between handled (%d) and exitcode (%d)",
2945 handled, vmexit->exitcode);
2949 vmm_stat_incr(vm, vcpu, VMEXIT_USERSPACE, 1);
2951 VCPU_CTR1(vm, vcpu, "returning from vmx_run: exitcode %d",
2955 vmx_msr_guest_exit(vmx, vcpu);
2961 vmx_vmcleanup(void *arg)
2964 struct vmx *vmx = arg;
2966 if (apic_access_virtualization(vmx, 0))
2967 vm_unmap_mmio(vmx->vm, DEFAULT_APIC_BASE, PAGE_SIZE);
2969 for (i = 0; i < VM_MAXCPU; i++)
2970 vpid_free(vmx->state[i].vpid);
2978 vmxctx_regptr(struct vmxctx *vmxctx, int reg)
2982 case VM_REG_GUEST_RAX:
2983 return (&vmxctx->guest_rax);
2984 case VM_REG_GUEST_RBX:
2985 return (&vmxctx->guest_rbx);
2986 case VM_REG_GUEST_RCX:
2987 return (&vmxctx->guest_rcx);
2988 case VM_REG_GUEST_RDX:
2989 return (&vmxctx->guest_rdx);
2990 case VM_REG_GUEST_RSI:
2991 return (&vmxctx->guest_rsi);
2992 case VM_REG_GUEST_RDI:
2993 return (&vmxctx->guest_rdi);
2994 case VM_REG_GUEST_RBP:
2995 return (&vmxctx->guest_rbp);
2996 case VM_REG_GUEST_R8:
2997 return (&vmxctx->guest_r8);
2998 case VM_REG_GUEST_R9:
2999 return (&vmxctx->guest_r9);
3000 case VM_REG_GUEST_R10:
3001 return (&vmxctx->guest_r10);
3002 case VM_REG_GUEST_R11:
3003 return (&vmxctx->guest_r11);
3004 case VM_REG_GUEST_R12:
3005 return (&vmxctx->guest_r12);
3006 case VM_REG_GUEST_R13:
3007 return (&vmxctx->guest_r13);
3008 case VM_REG_GUEST_R14:
3009 return (&vmxctx->guest_r14);
3010 case VM_REG_GUEST_R15:
3011 return (&vmxctx->guest_r15);
3012 case VM_REG_GUEST_CR2:
3013 return (&vmxctx->guest_cr2);
3014 case VM_REG_GUEST_DR0:
3015 return (&vmxctx->guest_dr0);
3016 case VM_REG_GUEST_DR1:
3017 return (&vmxctx->guest_dr1);
3018 case VM_REG_GUEST_DR2:
3019 return (&vmxctx->guest_dr2);
3020 case VM_REG_GUEST_DR3:
3021 return (&vmxctx->guest_dr3);
3022 case VM_REG_GUEST_DR6:
3023 return (&vmxctx->guest_dr6);
3031 vmxctx_getreg(struct vmxctx *vmxctx, int reg, uint64_t *retval)
3035 if ((regp = vmxctx_regptr(vmxctx, reg)) != NULL) {
3043 vmxctx_setreg(struct vmxctx *vmxctx, int reg, uint64_t val)
3047 if ((regp = vmxctx_regptr(vmxctx, reg)) != NULL) {
3055 vmx_get_intr_shadow(struct vmx *vmx, int vcpu, int running, uint64_t *retval)
3060 error = vmcs_getreg(&vmx->vmcs[vcpu], running,
3061 VMCS_IDENT(VMCS_GUEST_INTERRUPTIBILITY), &gi);
3062 *retval = (gi & HWINTR_BLOCKING) ? 1 : 0;
3067 vmx_modify_intr_shadow(struct vmx *vmx, int vcpu, int running, uint64_t val)
3074 * Forcing the vcpu into an interrupt shadow is not supported.
3081 vmcs = &vmx->vmcs[vcpu];
3082 ident = VMCS_IDENT(VMCS_GUEST_INTERRUPTIBILITY);
3083 error = vmcs_getreg(vmcs, running, ident, &gi);
3085 gi &= ~HWINTR_BLOCKING;
3086 error = vmcs_setreg(vmcs, running, ident, gi);
3089 VCPU_CTR2(vmx->vm, vcpu, "Setting intr_shadow to %#lx %s", val,
3090 error ? "failed" : "succeeded");
3095 vmx_shadow_reg(int reg)
3102 case VM_REG_GUEST_CR0:
3103 shreg = VMCS_CR0_SHADOW;
3105 case VM_REG_GUEST_CR4:
3106 shreg = VMCS_CR4_SHADOW;
3116 vmx_getreg(void *arg, int vcpu, int reg, uint64_t *retval)
3118 int running, hostcpu;
3119 struct vmx *vmx = arg;
3121 running = vcpu_is_running(vmx->vm, vcpu, &hostcpu);
3122 if (running && hostcpu != curcpu)
3123 panic("vmx_getreg: %s%d is running", vm_name(vmx->vm), vcpu);
3125 if (reg == VM_REG_GUEST_INTR_SHADOW)
3126 return (vmx_get_intr_shadow(vmx, vcpu, running, retval));
3128 if (vmxctx_getreg(&vmx->ctx[vcpu], reg, retval) == 0)
3131 return (vmcs_getreg(&vmx->vmcs[vcpu], running, reg, retval));
3135 vmx_setreg(void *arg, int vcpu, int reg, uint64_t val)
3137 int error, hostcpu, running, shadow;
3140 struct vmx *vmx = arg;
3142 running = vcpu_is_running(vmx->vm, vcpu, &hostcpu);
3143 if (running && hostcpu != curcpu)
3144 panic("vmx_setreg: %s%d is running", vm_name(vmx->vm), vcpu);
3146 if (reg == VM_REG_GUEST_INTR_SHADOW)
3147 return (vmx_modify_intr_shadow(vmx, vcpu, running, val));
3149 if (vmxctx_setreg(&vmx->ctx[vcpu], reg, val) == 0)
3152 error = vmcs_setreg(&vmx->vmcs[vcpu], running, reg, val);
3156 * If the "load EFER" VM-entry control is 1 then the
3157 * value of EFER.LMA must be identical to "IA-32e mode guest"
3158 * bit in the VM-entry control.
3160 if ((entry_ctls & VM_ENTRY_LOAD_EFER) != 0 &&
3161 (reg == VM_REG_GUEST_EFER)) {
3162 vmcs_getreg(&vmx->vmcs[vcpu], running,
3163 VMCS_IDENT(VMCS_ENTRY_CTLS), &ctls);
3165 ctls |= VM_ENTRY_GUEST_LMA;
3167 ctls &= ~VM_ENTRY_GUEST_LMA;
3168 vmcs_setreg(&vmx->vmcs[vcpu], running,
3169 VMCS_IDENT(VMCS_ENTRY_CTLS), ctls);
3172 shadow = vmx_shadow_reg(reg);
3175 * Store the unmodified value in the shadow
3177 error = vmcs_setreg(&vmx->vmcs[vcpu], running,
3178 VMCS_IDENT(shadow), val);
3181 if (reg == VM_REG_GUEST_CR3) {
3183 * Invalidate the guest vcpu's TLB mappings to emulate
3184 * the behavior of updating %cr3.
3186 * XXX the processor retains global mappings when %cr3
3187 * is updated but vmx_invvpid() does not.
3189 pmap = vmx->ctx[vcpu].pmap;
3190 vmx_invvpid(vmx, vcpu, pmap, running);
3198 vmx_getdesc(void *arg, int vcpu, int reg, struct seg_desc *desc)
3200 int hostcpu, running;
3201 struct vmx *vmx = arg;
3203 running = vcpu_is_running(vmx->vm, vcpu, &hostcpu);
3204 if (running && hostcpu != curcpu)
3205 panic("vmx_getdesc: %s%d is running", vm_name(vmx->vm), vcpu);
3207 return (vmcs_getdesc(&vmx->vmcs[vcpu], running, reg, desc));
3211 vmx_setdesc(void *arg, int vcpu, int reg, struct seg_desc *desc)
3213 int hostcpu, running;
3214 struct vmx *vmx = arg;
3216 running = vcpu_is_running(vmx->vm, vcpu, &hostcpu);
3217 if (running && hostcpu != curcpu)
3218 panic("vmx_setdesc: %s%d is running", vm_name(vmx->vm), vcpu);
3220 return (vmcs_setdesc(&vmx->vmcs[vcpu], running, reg, desc));
3224 vmx_getcap(void *arg, int vcpu, int type, int *retval)
3226 struct vmx *vmx = arg;
3232 vcap = vmx->cap[vcpu].set;
3235 case VM_CAP_HALT_EXIT:
3239 case VM_CAP_PAUSE_EXIT:
3243 case VM_CAP_MTRAP_EXIT:
3244 if (cap_monitor_trap)
3247 case VM_CAP_UNRESTRICTED_GUEST:
3248 if (cap_unrestricted_guest)
3251 case VM_CAP_ENABLE_INVPCID:
3260 *retval = (vcap & (1 << type)) ? 1 : 0;
3266 vmx_setcap(void *arg, int vcpu, int type, int val)
3268 struct vmx *vmx = arg;
3269 struct vmcs *vmcs = &vmx->vmcs[vcpu];
3281 case VM_CAP_HALT_EXIT:
3282 if (cap_halt_exit) {
3284 pptr = &vmx->cap[vcpu].proc_ctls;
3286 flag = PROCBASED_HLT_EXITING;
3287 reg = VMCS_PRI_PROC_BASED_CTLS;
3290 case VM_CAP_MTRAP_EXIT:
3291 if (cap_monitor_trap) {
3293 pptr = &vmx->cap[vcpu].proc_ctls;
3295 flag = PROCBASED_MTF;
3296 reg = VMCS_PRI_PROC_BASED_CTLS;
3299 case VM_CAP_PAUSE_EXIT:
3300 if (cap_pause_exit) {
3302 pptr = &vmx->cap[vcpu].proc_ctls;
3304 flag = PROCBASED_PAUSE_EXITING;
3305 reg = VMCS_PRI_PROC_BASED_CTLS;
3308 case VM_CAP_UNRESTRICTED_GUEST:
3309 if (cap_unrestricted_guest) {
3311 pptr = &vmx->cap[vcpu].proc_ctls2;
3313 flag = PROCBASED2_UNRESTRICTED_GUEST;
3314 reg = VMCS_SEC_PROC_BASED_CTLS;
3317 case VM_CAP_ENABLE_INVPCID:
3320 pptr = &vmx->cap[vcpu].proc_ctls2;
3322 flag = PROCBASED2_ENABLE_INVPCID;
3323 reg = VMCS_SEC_PROC_BASED_CTLS;
3337 error = vmwrite(reg, baseval);
3344 * Update optional stored flags, and record
3352 vmx->cap[vcpu].set |= (1 << type);
3354 vmx->cap[vcpu].set &= ~(1 << type);
3363 struct vlapic vlapic;
3364 struct pir_desc *pir_desc;
3368 #define VMX_CTR_PIR(vm, vcpuid, pir_desc, notify, vector, level, msg) \
3370 VCPU_CTR2(vm, vcpuid, msg " assert %s-triggered vector %d", \
3371 level ? "level" : "edge", vector); \
3372 VCPU_CTR1(vm, vcpuid, msg " pir0 0x%016lx", pir_desc->pir[0]); \
3373 VCPU_CTR1(vm, vcpuid, msg " pir1 0x%016lx", pir_desc->pir[1]); \
3374 VCPU_CTR1(vm, vcpuid, msg " pir2 0x%016lx", pir_desc->pir[2]); \
3375 VCPU_CTR1(vm, vcpuid, msg " pir3 0x%016lx", pir_desc->pir[3]); \
3376 VCPU_CTR1(vm, vcpuid, msg " notify: %s", notify ? "yes" : "no");\
3380 * vlapic->ops handlers that utilize the APICv hardware assist described in
3381 * Chapter 29 of the Intel SDM.
3384 vmx_set_intr_ready(struct vlapic *vlapic, int vector, bool level)
3386 struct vlapic_vtx *vlapic_vtx;
3387 struct pir_desc *pir_desc;
3391 vlapic_vtx = (struct vlapic_vtx *)vlapic;
3392 pir_desc = vlapic_vtx->pir_desc;
3395 * Keep track of interrupt requests in the PIR descriptor. This is
3396 * because the virtual APIC page pointed to by the VMCS cannot be
3397 * modified if the vcpu is running.
3400 mask = 1UL << (vector % 64);
3401 atomic_set_long(&pir_desc->pir[idx], mask);
3402 notify = atomic_cmpset_long(&pir_desc->pending, 0, 1);
3404 VMX_CTR_PIR(vlapic->vm, vlapic->vcpuid, pir_desc, notify, vector,
3405 level, "vmx_set_intr_ready");
3410 vmx_pending_intr(struct vlapic *vlapic, int *vecptr)
3412 struct vlapic_vtx *vlapic_vtx;
3413 struct pir_desc *pir_desc;
3414 struct LAPIC *lapic;
3415 uint64_t pending, pirval;
3420 * This function is only expected to be called from the 'HLT' exit
3421 * handler which does not care about the vector that is pending.
3423 KASSERT(vecptr == NULL, ("vmx_pending_intr: vecptr must be NULL"));
3425 vlapic_vtx = (struct vlapic_vtx *)vlapic;
3426 pir_desc = vlapic_vtx->pir_desc;
3428 pending = atomic_load_acq_long(&pir_desc->pending);
3431 * While a virtual interrupt may have already been
3432 * processed the actual delivery maybe pending the
3433 * interruptibility of the guest. Recognize a pending
3434 * interrupt by reevaluating virtual interrupts
3435 * following Section 29.2.1 in the Intel SDM Volume 3.
3437 struct vm_exit *vmexit;
3440 vmexit = vm_exitinfo(vlapic->vm, vlapic->vcpuid);
3441 KASSERT(vmexit->exitcode == VM_EXITCODE_HLT,
3442 ("vmx_pending_intr: exitcode not 'HLT'"));
3443 rvi = vmexit->u.hlt.intr_status & APIC_TPR_INT;
3444 lapic = vlapic->apic_page;
3445 ppr = lapic->ppr & APIC_TPR_INT;
3454 * If there is an interrupt pending then it will be recognized only
3455 * if its priority is greater than the processor priority.
3457 * Special case: if the processor priority is zero then any pending
3458 * interrupt will be recognized.
3460 lapic = vlapic->apic_page;
3461 ppr = lapic->ppr & APIC_TPR_INT;
3465 VCPU_CTR1(vlapic->vm, vlapic->vcpuid, "HLT with non-zero PPR %d",
3468 for (i = 3; i >= 0; i--) {
3469 pirval = pir_desc->pir[i];
3471 vpr = (i * 64 + flsl(pirval) - 1) & APIC_TPR_INT;
3479 vmx_intr_accepted(struct vlapic *vlapic, int vector)
3482 panic("vmx_intr_accepted: not expected to be called");
3486 vmx_set_tmr(struct vlapic *vlapic, int vector, bool level)
3488 struct vlapic_vtx *vlapic_vtx;
3493 KASSERT(vector >= 0 && vector <= 255, ("invalid vector %d", vector));
3494 KASSERT(!vcpu_is_running(vlapic->vm, vlapic->vcpuid, NULL),
3495 ("vmx_set_tmr: vcpu cannot be running"));
3497 vlapic_vtx = (struct vlapic_vtx *)vlapic;
3498 vmx = vlapic_vtx->vmx;
3499 vmcs = &vmx->vmcs[vlapic->vcpuid];
3500 mask = 1UL << (vector % 64);
3503 val = vmcs_read(VMCS_EOI_EXIT(vector));
3508 vmcs_write(VMCS_EOI_EXIT(vector), val);
3513 vmx_enable_x2apic_mode(struct vlapic *vlapic)
3517 uint32_t proc_ctls2;
3520 vcpuid = vlapic->vcpuid;
3521 vmx = ((struct vlapic_vtx *)vlapic)->vmx;
3522 vmcs = &vmx->vmcs[vcpuid];
3524 proc_ctls2 = vmx->cap[vcpuid].proc_ctls2;
3525 KASSERT((proc_ctls2 & PROCBASED2_VIRTUALIZE_APIC_ACCESSES) != 0,
3526 ("%s: invalid proc_ctls2 %#x", __func__, proc_ctls2));
3528 proc_ctls2 &= ~PROCBASED2_VIRTUALIZE_APIC_ACCESSES;
3529 proc_ctls2 |= PROCBASED2_VIRTUALIZE_X2APIC_MODE;
3530 vmx->cap[vcpuid].proc_ctls2 = proc_ctls2;
3533 vmcs_write(VMCS_SEC_PROC_BASED_CTLS, proc_ctls2);
3536 if (vlapic->vcpuid == 0) {
3538 * The nested page table mappings are shared by all vcpus
3539 * so unmap the APIC access page just once.
3541 error = vm_unmap_mmio(vmx->vm, DEFAULT_APIC_BASE, PAGE_SIZE);
3542 KASSERT(error == 0, ("%s: vm_unmap_mmio error %d",
3546 * The MSR bitmap is shared by all vcpus so modify it only
3547 * once in the context of vcpu 0.
3549 error = vmx_allow_x2apic_msrs(vmx);
3550 KASSERT(error == 0, ("%s: vmx_allow_x2apic_msrs error %d",
3556 vmx_post_intr(struct vlapic *vlapic, int hostcpu)
3559 ipi_cpu(hostcpu, pirvec);
3563 * Transfer the pending interrupts in the PIR descriptor to the IRR
3564 * in the virtual APIC page.
3567 vmx_inject_pir(struct vlapic *vlapic)
3569 struct vlapic_vtx *vlapic_vtx;
3570 struct pir_desc *pir_desc;
3571 struct LAPIC *lapic;
3572 uint64_t val, pirval;
3573 int rvi, pirbase = -1;
3574 uint16_t intr_status_old, intr_status_new;
3576 vlapic_vtx = (struct vlapic_vtx *)vlapic;
3577 pir_desc = vlapic_vtx->pir_desc;
3578 if (atomic_cmpset_long(&pir_desc->pending, 1, 0) == 0) {
3579 VCPU_CTR0(vlapic->vm, vlapic->vcpuid, "vmx_inject_pir: "
3580 "no posted interrupt pending");
3586 lapic = vlapic->apic_page;
3588 val = atomic_readandclear_long(&pir_desc->pir[0]);
3591 lapic->irr1 |= val >> 32;
3596 val = atomic_readandclear_long(&pir_desc->pir[1]);
3599 lapic->irr3 |= val >> 32;
3604 val = atomic_readandclear_long(&pir_desc->pir[2]);
3607 lapic->irr5 |= val >> 32;
3612 val = atomic_readandclear_long(&pir_desc->pir[3]);
3615 lapic->irr7 |= val >> 32;
3620 VLAPIC_CTR_IRR(vlapic, "vmx_inject_pir");
3623 * Update RVI so the processor can evaluate pending virtual
3624 * interrupts on VM-entry.
3626 * It is possible for pirval to be 0 here, even though the
3627 * pending bit has been set. The scenario is:
3628 * CPU-Y is sending a posted interrupt to CPU-X, which
3629 * is running a guest and processing posted interrupts in h/w.
3630 * CPU-X will eventually exit and the state seen in s/w is
3631 * the pending bit set, but no PIR bits set.
3634 * (vm running) (host running)
3635 * rx posted interrupt
3638 * READ/CLEAR PIR bits
3641 * pending bit set, PIR 0
3644 rvi = pirbase + flsl(pirval) - 1;
3645 intr_status_old = vmcs_read(VMCS_GUEST_INTR_STATUS);
3646 intr_status_new = (intr_status_old & 0xFF00) | rvi;
3647 if (intr_status_new > intr_status_old) {
3648 vmcs_write(VMCS_GUEST_INTR_STATUS, intr_status_new);
3649 VCPU_CTR2(vlapic->vm, vlapic->vcpuid, "vmx_inject_pir: "
3650 "guest_intr_status changed from 0x%04x to 0x%04x",
3651 intr_status_old, intr_status_new);
3656 static struct vlapic *
3657 vmx_vlapic_init(void *arg, int vcpuid)
3660 struct vlapic *vlapic;
3661 struct vlapic_vtx *vlapic_vtx;
3665 vlapic = malloc(sizeof(struct vlapic_vtx), M_VLAPIC, M_WAITOK | M_ZERO);
3666 vlapic->vm = vmx->vm;
3667 vlapic->vcpuid = vcpuid;
3668 vlapic->apic_page = (struct LAPIC *)&vmx->apic_page[vcpuid];
3670 vlapic_vtx = (struct vlapic_vtx *)vlapic;
3671 vlapic_vtx->pir_desc = &vmx->pir_desc[vcpuid];
3672 vlapic_vtx->vmx = vmx;
3674 if (virtual_interrupt_delivery) {
3675 vlapic->ops.set_intr_ready = vmx_set_intr_ready;
3676 vlapic->ops.pending_intr = vmx_pending_intr;
3677 vlapic->ops.intr_accepted = vmx_intr_accepted;
3678 vlapic->ops.set_tmr = vmx_set_tmr;
3679 vlapic->ops.enable_x2apic_mode = vmx_enable_x2apic_mode;
3682 if (posted_interrupts)
3683 vlapic->ops.post_intr = vmx_post_intr;
3685 vlapic_init(vlapic);
3691 vmx_vlapic_cleanup(void *arg, struct vlapic *vlapic)
3694 vlapic_cleanup(vlapic);
3695 free(vlapic, M_VLAPIC);
3698 struct vmm_ops vmm_ops_intel = {