sys/amd64/vmm/io/vlapic.c

   1 /*-
   2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
   3  *
   4  * Copyright (c) 2011 NetApp, Inc.
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
  17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED.  IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
  20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  26  * SUCH DAMAGE.
  27  *
  28  * $FreeBSD$
  29  */
  30
  31 #include <sys/cdefs.h>
  32 __FBSDID("$FreeBSD$");
  33
  34 #include <sys/param.h>
  35 #include <sys/lock.h>
  36 #include <sys/kernel.h>
  37 #include <sys/malloc.h>
  38 #include <sys/mutex.h>
  39 #include <sys/systm.h>
  40 #include <sys/smp.h>
  41
  42 #include <x86/specialreg.h>
  43 #include <x86/apicreg.h>
  44
  45 #include <machine/clock.h>
  46 #include <machine/smp.h>
  47
  48 #include <machine/vmm.h>
  49
  50 #include "vmm_lapic.h"
  51 #include "vmm_ktr.h"
  52 #include "vmm_stat.h"
  53
  54 #include "vlapic.h"
  55 #include "vlapic_priv.h"
  56 #include "vioapic.h"
  57
  58 #define PRIO(x)                 ((x) >> 4)
  59
  60 #define VLAPIC_VERSION          (16)
  61
  62 #define x2apic(vlapic)  (((vlapic)->msr_apicbase & APICBASE_X2APIC) ? 1 : 0)
  63
  64 /*
  65  * The 'vlapic->timer_mtx' is used to provide mutual exclusion between the
  66  * vlapic_callout_handler() and vcpu accesses to:
  67  * - timer_freq_bt, timer_period_bt, timer_fire_bt
  68  * - timer LVT register
  69  */
  70 #define VLAPIC_TIMER_LOCK(vlapic)       mtx_lock_spin(&((vlapic)->timer_mtx))
  71 #define VLAPIC_TIMER_UNLOCK(vlapic)     mtx_unlock_spin(&((vlapic)->timer_mtx))
  72 #define VLAPIC_TIMER_LOCKED(vlapic)     mtx_owned(&((vlapic)->timer_mtx))
  73
  74 /*
  75  * APIC timer frequency:
  76  * - arbitrary but chosen to be in the ballpark of contemporary hardware.
  77  * - power-of-two to avoid loss of precision when converted to a bintime.
  78  */
  79 #define VLAPIC_BUS_FREQ         (128 * 1024 * 1024)
  80
  81 static __inline uint32_t
  82 vlapic_get_id(struct vlapic *vlapic)
  83 {
  84
  85         if (x2apic(vlapic))
  86                 return (vlapic->vcpuid);
  87         else
  88                 return (vlapic->vcpuid << 24);
  89 }
  90
  91 static uint32_t
  92 x2apic_ldr(struct vlapic *vlapic)
  93 {
  94         int apicid;
  95         uint32_t ldr;
  96
  97         apicid = vlapic_get_id(vlapic);
  98         ldr = 1 << (apicid & 0xf);
  99         ldr |= (apicid & 0xffff0) << 12;
 100         return (ldr);
 101 }
 102
 103 void
 104 vlapic_dfr_write_handler(struct vlapic *vlapic)
 105 {
 106         struct LAPIC *lapic;
 107
 108         lapic = vlapic->apic_page;
 109         if (x2apic(vlapic)) {
 110                 VM_CTR1(vlapic->vm, "ignoring write to DFR in x2apic mode: %#x",
 111                     lapic->dfr);
 112                 lapic->dfr = 0;
 113                 return;
 114         }
 115
 116         lapic->dfr &= APIC_DFR_MODEL_MASK;
 117         lapic->dfr |= APIC_DFR_RESERVED;
 118
 119         if ((lapic->dfr & APIC_DFR_MODEL_MASK) == APIC_DFR_MODEL_FLAT)
 120                 VLAPIC_CTR0(vlapic, "vlapic DFR in Flat Model");
 121         else if ((lapic->dfr & APIC_DFR_MODEL_MASK) == APIC_DFR_MODEL_CLUSTER)
 122                 VLAPIC_CTR0(vlapic, "vlapic DFR in Cluster Model");
 123         else
 124                 VLAPIC_CTR1(vlapic, "DFR in Unknown Model %#x", lapic->dfr);
 125 }
 126
 127 void
 128 vlapic_ldr_write_handler(struct vlapic *vlapic)
 129 {
 130         struct LAPIC *lapic;
 131
 132         lapic = vlapic->apic_page;
 133
 134         /* LDR is read-only in x2apic mode */
 135         if (x2apic(vlapic)) {
 136                 VLAPIC_CTR1(vlapic, "ignoring write to LDR in x2apic mode: %#x",
 137                     lapic->ldr);
 138                 lapic->ldr = x2apic_ldr(vlapic);
 139         } else {
 140                 lapic->ldr &= ~APIC_LDR_RESERVED;
 141                 VLAPIC_CTR1(vlapic, "vlapic LDR set to %#x", lapic->ldr);
 142         }
 143 }
 144
 145 void
 146 vlapic_id_write_handler(struct vlapic *vlapic)
 147 {
 148         struct LAPIC *lapic;
 149
 150         /*
 151          * We don't allow the ID register to be modified so reset it back to
 152          * its default value.
 153          */
 154         lapic = vlapic->apic_page;
 155         lapic->id = vlapic_get_id(vlapic);
 156 }
 157
 158 static int
 159 vlapic_timer_divisor(uint32_t dcr)
 160 {
 161         switch (dcr & 0xB) {
 162         case APIC_TDCR_1:
 163                 return (1);
 164         case APIC_TDCR_2:
 165                 return (2);
 166         case APIC_TDCR_4:
 167                 return (4);
 168         case APIC_TDCR_8:
 169                 return (8);
 170         case APIC_TDCR_16:
 171                 return (16);
 172         case APIC_TDCR_32:
 173                 return (32);
 174         case APIC_TDCR_64:
 175                 return (64);
 176         case APIC_TDCR_128:
 177                 return (128);
 178         default:
 179                 panic("vlapic_timer_divisor: invalid dcr 0x%08x", dcr);
 180         }
 181 }
 182
 183 #if 0
 184 static inline void
 185 vlapic_dump_lvt(uint32_t offset, uint32_t *lvt)
 186 {
 187         printf("Offset %x: lvt %08x (V:%02x DS:%x M:%x)\n", offset,
 188             *lvt, *lvt & APIC_LVTT_VECTOR, *lvt & APIC_LVTT_DS,
 189             *lvt & APIC_LVTT_M);
 190 }
 191 #endif
 192
 193 static uint32_t
 194 vlapic_get_ccr(struct vlapic *vlapic)
 195 {
 196         struct bintime bt_now, bt_rem;
 197         struct LAPIC *lapic;
 198         uint32_t ccr;
 199
 200         ccr = 0;
 201         lapic = vlapic->apic_page;
 202
 203         VLAPIC_TIMER_LOCK(vlapic);
 204         if (callout_active(&vlapic->callout)) {
 205                 /*
 206                  * If the timer is scheduled to expire in the future then
 207                  * compute the value of 'ccr' based on the remaining time.
 208                  */
 209                 binuptime(&bt_now);
 210                 if (bintime_cmp(&vlapic->timer_fire_bt, &bt_now, >)) {
 211                         bt_rem = vlapic->timer_fire_bt;
 212                         bintime_sub(&bt_rem, &bt_now);
 213                         ccr += bt_rem.sec * BT2FREQ(&vlapic->timer_freq_bt);
 214                         ccr += bt_rem.frac / vlapic->timer_freq_bt.frac;
 215                 }
 216         }
 217         KASSERT(ccr <= lapic->icr_timer, ("vlapic_get_ccr: invalid ccr %#x, "
 218             "icr_timer is %#x", ccr, lapic->icr_timer));
 219         VLAPIC_CTR2(vlapic, "vlapic ccr_timer = %#x, icr_timer = %#x",
 220             ccr, lapic->icr_timer);
 221         VLAPIC_TIMER_UNLOCK(vlapic);
 222         return (ccr);
 223 }
 224
 225 void
 226 vlapic_dcr_write_handler(struct vlapic *vlapic)
 227 {
 228         struct LAPIC *lapic;
 229         int divisor;
 230
 231         lapic = vlapic->apic_page;
 232         VLAPIC_TIMER_LOCK(vlapic);
 233
 234         divisor = vlapic_timer_divisor(lapic->dcr_timer);
 235         VLAPIC_CTR2(vlapic, "vlapic dcr_timer=%#x, divisor=%d",
 236             lapic->dcr_timer, divisor);
 237
 238         /*
 239          * Update the timer frequency and the timer period.
 240          *
 241          * XXX changes to the frequency divider will not take effect until
 242          * the timer is reloaded.
 243          */
 244         FREQ2BT(VLAPIC_BUS_FREQ / divisor, &vlapic->timer_freq_bt);
 245         vlapic->timer_period_bt = vlapic->timer_freq_bt;
 246         bintime_mul(&vlapic->timer_period_bt, lapic->icr_timer);
 247
 248         VLAPIC_TIMER_UNLOCK(vlapic);
 249 }
 250
 251 void
 252 vlapic_esr_write_handler(struct vlapic *vlapic)
 253 {
 254         struct LAPIC *lapic;
 255
 256         lapic = vlapic->apic_page;
 257         lapic->esr = vlapic->esr_pending;
 258         vlapic->esr_pending = 0;
 259 }
 260
 261 int
 262 vlapic_set_intr_ready(struct vlapic *vlapic, int vector, bool level)
 263 {
 264         struct LAPIC *lapic;
 265         uint32_t *irrptr, *tmrptr, mask;
 266         int idx;
 267
 268         KASSERT(vector >= 0 && vector < 256, ("invalid vector %d", vector));
 269
 270         lapic = vlapic->apic_page;
 271         if (!(lapic->svr & APIC_SVR_ENABLE)) {
 272                 VLAPIC_CTR1(vlapic, "vlapic is software disabled, ignoring "
 273                     "interrupt %d", vector);
 274                 return (0);
 275         }
 276
 277         if (vector < 16) {
 278                 vlapic_set_error(vlapic, APIC_ESR_RECEIVE_ILLEGAL_VECTOR);
 279                 VLAPIC_CTR1(vlapic, "vlapic ignoring interrupt to vector %d",
 280                     vector);
 281                 return (1);
 282         }
 283
 284         if (vlapic->ops.set_intr_ready)
 285                 return ((*vlapic->ops.set_intr_ready)(vlapic, vector, level));
 286
 287         idx = (vector / 32) * 4;
 288         mask = 1 << (vector % 32);
 289
 290         irrptr = &lapic->irr0;
 291         atomic_set_int(&irrptr[idx], mask);
 292
 293         /*
 294          * Verify that the trigger-mode of the interrupt matches with
 295          * the vlapic TMR registers.
 296          */
 297         tmrptr = &lapic->tmr0;
 298         if ((tmrptr[idx] & mask) != (level ? mask : 0)) {
 299                 VLAPIC_CTR3(vlapic, "vlapic TMR[%d] is 0x%08x but "
 300                     "interrupt is %s-triggered", idx / 4, tmrptr[idx],
 301                     level ? "level" : "edge");
 302         }
 303
 304         VLAPIC_CTR_IRR(vlapic, "vlapic_set_intr_ready");
 305         return (1);
 306 }
 307
 308 static __inline uint32_t *
 309 vlapic_get_lvtptr(struct vlapic *vlapic, uint32_t offset)
 310 {
 311         struct LAPIC    *lapic = vlapic->apic_page;
 312         int              i;
 313
 314         switch (offset) {
 315         case APIC_OFFSET_CMCI_LVT:
 316                 return (&lapic->lvt_cmci);
 317         case APIC_OFFSET_TIMER_LVT ... APIC_OFFSET_ERROR_LVT:
 318                 i = (offset - APIC_OFFSET_TIMER_LVT) >> 2;
 319                 return ((&lapic->lvt_timer) + i);;
 320         default:
 321                 panic("vlapic_get_lvt: invalid LVT\n");
 322         }
 323 }
 324
 325 static __inline int
 326 lvt_off_to_idx(uint32_t offset)
 327 {
 328         int index;
 329
 330         switch (offset) {
 331         case APIC_OFFSET_CMCI_LVT:
 332                 index = APIC_LVT_CMCI;
 333                 break;
 334         case APIC_OFFSET_TIMER_LVT:
 335                 index = APIC_LVT_TIMER;
 336                 break;
 337         case APIC_OFFSET_THERM_LVT:
 338                 index = APIC_LVT_THERMAL;
 339                 break;
 340         case APIC_OFFSET_PERF_LVT:
 341                 index = APIC_LVT_PMC;
 342                 break;
 343         case APIC_OFFSET_LINT0_LVT:
 344                 index = APIC_LVT_LINT0;
 345                 break;
 346         case APIC_OFFSET_LINT1_LVT:
 347                 index = APIC_LVT_LINT1;
 348                 break;
 349         case APIC_OFFSET_ERROR_LVT:
 350                 index = APIC_LVT_ERROR;
 351                 break;
 352         default:
 353                 index = -1;
 354                 break;
 355         }
 356         KASSERT(index >= 0 && index <= VLAPIC_MAXLVT_INDEX, ("lvt_off_to_idx: "
 357             "invalid lvt index %d for offset %#x", index, offset));
 358
 359         return (index);
 360 }
 361
 362 static __inline uint32_t
 363 vlapic_get_lvt(struct vlapic *vlapic, uint32_t offset)
 364 {
 365         int idx;
 366         uint32_t val;
 367
 368         idx = lvt_off_to_idx(offset);
 369         val = atomic_load_acq_32(&vlapic->lvt_last[idx]);
 370         return (val);
 371 }
 372
 373 void
 374 vlapic_lvt_write_handler(struct vlapic *vlapic, uint32_t offset)
 375 {
 376         uint32_t *lvtptr, mask, val;
 377         struct LAPIC *lapic;
 378         int idx;
 379
 380         lapic = vlapic->apic_page;
 381         lvtptr = vlapic_get_lvtptr(vlapic, offset);
 382         val = *lvtptr;
 383         idx = lvt_off_to_idx(offset);
 384
 385         if (!(lapic->svr & APIC_SVR_ENABLE))
 386                 val |= APIC_LVT_M;
 387         mask = APIC_LVT_M | APIC_LVT_DS | APIC_LVT_VECTOR;
 388         switch (offset) {
 389         case APIC_OFFSET_TIMER_LVT:
 390                 mask |= APIC_LVTT_TM;
 391                 break;
 392         case APIC_OFFSET_ERROR_LVT:
 393                 break;
 394         case APIC_OFFSET_LINT0_LVT:
 395         case APIC_OFFSET_LINT1_LVT:
 396                 mask |= APIC_LVT_TM | APIC_LVT_RIRR | APIC_LVT_IIPP;
 397                 /* FALLTHROUGH */
 398         default:
 399                 mask |= APIC_LVT_DM;
 400                 break;
 401         }
 402         val &= mask;
 403         *lvtptr = val;
 404         atomic_store_rel_32(&vlapic->lvt_last[idx], val);
 405 }
 406
 407 static void
 408 vlapic_mask_lvts(struct vlapic *vlapic)
 409 {
 410         struct LAPIC *lapic = vlapic->apic_page;
 411
 412         lapic->lvt_cmci |= APIC_LVT_M;
 413         vlapic_lvt_write_handler(vlapic, APIC_OFFSET_CMCI_LVT);
 414
 415         lapic->lvt_timer |= APIC_LVT_M;
 416         vlapic_lvt_write_handler(vlapic, APIC_OFFSET_TIMER_LVT);
 417
 418         lapic->lvt_thermal |= APIC_LVT_M;
 419         vlapic_lvt_write_handler(vlapic, APIC_OFFSET_THERM_LVT);
 420
 421         lapic->lvt_pcint |= APIC_LVT_M;
 422         vlapic_lvt_write_handler(vlapic, APIC_OFFSET_PERF_LVT);
 423
 424         lapic->lvt_lint0 |= APIC_LVT_M;
 425         vlapic_lvt_write_handler(vlapic, APIC_OFFSET_LINT0_LVT);
 426
 427         lapic->lvt_lint1 |= APIC_LVT_M;
 428         vlapic_lvt_write_handler(vlapic, APIC_OFFSET_LINT1_LVT);
 429
 430         lapic->lvt_error |= APIC_LVT_M;
 431         vlapic_lvt_write_handler(vlapic, APIC_OFFSET_ERROR_LVT);
 432 }
 433
 434 static int
 435 vlapic_fire_lvt(struct vlapic *vlapic, uint32_t lvt)
 436 {
 437         uint32_t vec, mode;
 438
 439         if (lvt & APIC_LVT_M)
 440                 return (0);
 441
 442         vec = lvt & APIC_LVT_VECTOR;
 443         mode = lvt & APIC_LVT_DM;
 444
 445         switch (mode) {
 446         case APIC_LVT_DM_FIXED:
 447                 if (vec < 16) {
 448                         vlapic_set_error(vlapic, APIC_ESR_SEND_ILLEGAL_VECTOR);
 449                         return (0);
 450                 }
 451                 if (vlapic_set_intr_ready(vlapic, vec, false))
 452                         vcpu_notify_event(vlapic->vm, vlapic->vcpuid, true);
 453                 break;
 454         case APIC_LVT_DM_NMI:
 455                 vm_inject_nmi(vlapic->vm, vlapic->vcpuid);
 456                 break;
 457         case APIC_LVT_DM_EXTINT:
 458                 vm_inject_extint(vlapic->vm, vlapic->vcpuid);
 459                 break;
 460         default:
 461                 // Other modes ignored
 462                 return (0);
 463         }
 464         return (1);
 465 }
 466
 467 #if 1
 468 static void
 469 dump_isrvec_stk(struct vlapic *vlapic)
 470 {
 471         int i;
 472         uint32_t *isrptr;
 473
 474         isrptr = &vlapic->apic_page->isr0;
 475         for (i = 0; i < 8; i++)
 476                 printf("ISR%d 0x%08x\n", i, isrptr[i * 4]);
 477
 478         for (i = 0; i <= vlapic->isrvec_stk_top; i++)
 479                 printf("isrvec_stk[%d] = %d\n", i, vlapic->isrvec_stk[i]);
 480 }
 481 #endif
 482
 483 /*
 484  * Algorithm adopted from section "Interrupt, Task and Processor Priority"
 485  * in Intel Architecture Manual Vol 3a.
 486  */
 487 static void
 488 vlapic_update_ppr(struct vlapic *vlapic)
 489 {
 490         int isrvec, tpr, ppr;
 491
 492         /*
 493          * Note that the value on the stack at index 0 is always 0.
 494          *
 495          * This is a placeholder for the value of ISRV when none of the
 496          * bits is set in the ISRx registers.
 497          */
 498         isrvec = vlapic->isrvec_stk[vlapic->isrvec_stk_top];
 499         tpr = vlapic->apic_page->tpr;
 500
 501 #if 1
 502         {
 503                 int i, lastprio, curprio, vector, idx;
 504                 uint32_t *isrptr;
 505
 506                 if (vlapic->isrvec_stk_top == 0 && isrvec != 0)
 507                         panic("isrvec_stk is corrupted: %d", isrvec);
 508
 509                 /*
 510                  * Make sure that the priority of the nested interrupts is
 511                  * always increasing.
 512                  */
 513                 lastprio = -1;
 514                 for (i = 1; i <= vlapic->isrvec_stk_top; i++) {
 515                         curprio = PRIO(vlapic->isrvec_stk[i]);
 516                         if (curprio <= lastprio) {
 517                                 dump_isrvec_stk(vlapic);
 518                                 panic("isrvec_stk does not satisfy invariant");
 519                         }
 520                         lastprio = curprio;
 521                 }
 522
 523                 /*
 524                  * Make sure that each bit set in the ISRx registers has a
 525                  * corresponding entry on the isrvec stack.
 526                  */
 527                 i = 1;
 528                 isrptr = &vlapic->apic_page->isr0;
 529                 for (vector = 0; vector < 256; vector++) {
 530                         idx = (vector / 32) * 4;
 531                         if (isrptr[idx] & (1 << (vector % 32))) {
 532                                 if (i > vlapic->isrvec_stk_top ||
 533                                     vlapic->isrvec_stk[i] != vector) {
 534                                         dump_isrvec_stk(vlapic);
 535                                         panic("ISR and isrvec_stk out of sync");
 536                                 }
 537                                 i++;
 538                         }
 539                 }
 540         }
 541 #endif
 542
 543         if (PRIO(tpr) >= PRIO(isrvec))
 544                 ppr = tpr;
 545         else
 546                 ppr = isrvec & 0xf0;
 547
 548         vlapic->apic_page->ppr = ppr;
 549         VLAPIC_CTR1(vlapic, "vlapic_update_ppr 0x%02x", ppr);
 550 }
 551
 552 static VMM_STAT(VLAPIC_GRATUITOUS_EOI, "EOI without any in-service interrupt");
 553
 554 static void
 555 vlapic_process_eoi(struct vlapic *vlapic)
 556 {
 557         struct LAPIC    *lapic = vlapic->apic_page;
 558         uint32_t        *isrptr, *tmrptr;
 559         int             i, idx, bitpos, vector;
 560
 561         isrptr = &lapic->isr0;
 562         tmrptr = &lapic->tmr0;
 563
 564         for (i = 7; i >= 0; i--) {
 565                 idx = i * 4;
 566                 bitpos = fls(isrptr[idx]);
 567                 if (bitpos-- != 0) {
 568                         if (vlapic->isrvec_stk_top <= 0) {
 569                                 panic("invalid vlapic isrvec_stk_top %d",
 570                                       vlapic->isrvec_stk_top);
 571                         }
 572                         isrptr[idx] &= ~(1 << bitpos);
 573                         vector = i * 32 + bitpos;
 574                         VCPU_CTR1(vlapic->vm, vlapic->vcpuid, "EOI vector %d",
 575                             vector);
 576                         VLAPIC_CTR_ISR(vlapic, "vlapic_process_eoi");
 577                         vlapic->isrvec_stk_top--;
 578                         vlapic_update_ppr(vlapic);
 579                         if ((tmrptr[idx] & (1 << bitpos)) != 0) {
 580                                 vioapic_process_eoi(vlapic->vm, vlapic->vcpuid,
 581                                     vector);
 582                         }
 583                         return;
 584                 }
 585         }
 586         VCPU_CTR0(vlapic->vm, vlapic->vcpuid, "Gratuitous EOI");
 587         vmm_stat_incr(vlapic->vm, vlapic->vcpuid, VLAPIC_GRATUITOUS_EOI, 1);
 588 }
 589
 590 static __inline int
 591 vlapic_get_lvt_field(uint32_t lvt, uint32_t mask)
 592 {
 593
 594         return (lvt & mask);
 595 }
 596
 597 static __inline int
 598 vlapic_periodic_timer(struct vlapic *vlapic)
 599 {
 600         uint32_t lvt;
 601
 602         lvt = vlapic_get_lvt(vlapic, APIC_OFFSET_TIMER_LVT);
 603
 604         return (vlapic_get_lvt_field(lvt, APIC_LVTT_TM_PERIODIC));
 605 }
 606
 607 static VMM_STAT(VLAPIC_INTR_ERROR, "error interrupts generated by vlapic");
 608
 609 void
 610 vlapic_set_error(struct vlapic *vlapic, uint32_t mask)
 611 {
 612         uint32_t lvt;
 613
 614         vlapic->esr_pending |= mask;
 615         if (vlapic->esr_firing)
 616                 return;
 617         vlapic->esr_firing = 1;
 618
 619         // The error LVT always uses the fixed delivery mode.
 620         lvt = vlapic_get_lvt(vlapic, APIC_OFFSET_ERROR_LVT);
 621         if (vlapic_fire_lvt(vlapic, lvt | APIC_LVT_DM_FIXED)) {
 622                 vmm_stat_incr(vlapic->vm, vlapic->vcpuid, VLAPIC_INTR_ERROR, 1);
 623         }
 624         vlapic->esr_firing = 0;
 625 }
 626
 627 static VMM_STAT(VLAPIC_INTR_TIMER, "timer interrupts generated by vlapic");
 628
 629 static void
 630 vlapic_fire_timer(struct vlapic *vlapic)
 631 {
 632         uint32_t lvt;
 633
 634         KASSERT(VLAPIC_TIMER_LOCKED(vlapic), ("vlapic_fire_timer not locked"));
 635
 636         // The timer LVT always uses the fixed delivery mode.
 637         lvt = vlapic_get_lvt(vlapic, APIC_OFFSET_TIMER_LVT);
 638         if (vlapic_fire_lvt(vlapic, lvt | APIC_LVT_DM_FIXED)) {
 639                 VLAPIC_CTR0(vlapic, "vlapic timer fired");
 640                 vmm_stat_incr(vlapic->vm, vlapic->vcpuid, VLAPIC_INTR_TIMER, 1);
 641         }
 642 }
 643
 644 static VMM_STAT(VLAPIC_INTR_CMC,
 645     "corrected machine check interrupts generated by vlapic");
 646
 647 void
 648 vlapic_fire_cmci(struct vlapic *vlapic)
 649 {
 650         uint32_t lvt;
 651
 652         lvt = vlapic_get_lvt(vlapic, APIC_OFFSET_CMCI_LVT);
 653         if (vlapic_fire_lvt(vlapic, lvt)) {
 654                 vmm_stat_incr(vlapic->vm, vlapic->vcpuid, VLAPIC_INTR_CMC, 1);
 655         }
 656 }
 657
 658 static VMM_STAT_ARRAY(LVTS_TRIGGERRED, VLAPIC_MAXLVT_INDEX + 1,
 659     "lvts triggered");
 660
 661 int
 662 vlapic_trigger_lvt(struct vlapic *vlapic, int vector)
 663 {
 664         uint32_t lvt;
 665
 666         if (vlapic_enabled(vlapic) == false) {
 667                 /*
 668                  * When the local APIC is global/hardware disabled,
 669                  * LINT[1:0] pins are configured as INTR and NMI pins,
 670                  * respectively.
 671                 */
 672                 switch (vector) {
 673                         case APIC_LVT_LINT0:
 674                                 vm_inject_extint(vlapic->vm, vlapic->vcpuid);
 675                                 break;
 676                         case APIC_LVT_LINT1:
 677                                 vm_inject_nmi(vlapic->vm, vlapic->vcpuid);
 678                                 break;
 679                         default:
 680                                 break;
 681                 }
 682                 return (0);
 683         }
 684
 685         switch (vector) {
 686         case APIC_LVT_LINT0:
 687                 lvt = vlapic_get_lvt(vlapic, APIC_OFFSET_LINT0_LVT);
 688                 break;
 689         case APIC_LVT_LINT1:
 690                 lvt = vlapic_get_lvt(vlapic, APIC_OFFSET_LINT1_LVT);
 691                 break;
 692         case APIC_LVT_TIMER:
 693                 lvt = vlapic_get_lvt(vlapic, APIC_OFFSET_TIMER_LVT);
 694                 lvt |= APIC_LVT_DM_FIXED;
 695                 break;
 696         case APIC_LVT_ERROR:
 697                 lvt = vlapic_get_lvt(vlapic, APIC_OFFSET_ERROR_LVT);
 698                 lvt |= APIC_LVT_DM_FIXED;
 699                 break;
 700         case APIC_LVT_PMC:
 701                 lvt = vlapic_get_lvt(vlapic, APIC_OFFSET_PERF_LVT);
 702                 break;
 703         case APIC_LVT_THERMAL:
 704                 lvt = vlapic_get_lvt(vlapic, APIC_OFFSET_THERM_LVT);
 705                 break;
 706         case APIC_LVT_CMCI:
 707                 lvt = vlapic_get_lvt(vlapic, APIC_OFFSET_CMCI_LVT);
 708                 break;
 709         default:
 710                 return (EINVAL);
 711         }
 712         if (vlapic_fire_lvt(vlapic, lvt)) {
 713                 vmm_stat_array_incr(vlapic->vm, vlapic->vcpuid,
 714                     LVTS_TRIGGERRED, vector, 1);
 715         }
 716         return (0);
 717 }
 718
 719 static void
 720 vlapic_callout_handler(void *arg)
 721 {
 722         struct vlapic *vlapic;
 723         struct bintime bt, btnow;
 724         sbintime_t rem_sbt;
 725
 726         vlapic = arg;
 727
 728         VLAPIC_TIMER_LOCK(vlapic);
 729         if (callout_pending(&vlapic->callout))  /* callout was reset */
 730                 goto done;
 731
 732         if (!callout_active(&vlapic->callout))  /* callout was stopped */
 733                 goto done;
 734
 735         callout_deactivate(&vlapic->callout);
 736
 737         vlapic_fire_timer(vlapic);
 738
 739         if (vlapic_periodic_timer(vlapic)) {
 740                 binuptime(&btnow);
 741                 KASSERT(bintime_cmp(&btnow, &vlapic->timer_fire_bt, >=),
 742                     ("vlapic callout at %#lx.%#lx, expected at %#lx.#%lx",
 743                     btnow.sec, btnow.frac, vlapic->timer_fire_bt.sec,
 744                     vlapic->timer_fire_bt.frac));
 745
 746                 /*
 747                  * Compute the delta between when the timer was supposed to
 748                  * fire and the present time.
 749                  */
 750                 bt = btnow;
 751                 bintime_sub(&bt, &vlapic->timer_fire_bt);
 752
 753                 rem_sbt = bttosbt(vlapic->timer_period_bt);
 754                 if (bintime_cmp(&bt, &vlapic->timer_period_bt, <)) {
 755                         /*
 756                          * Adjust the time until the next countdown downward
 757                          * to account for the lost time.
 758                          */
 759                         rem_sbt -= bttosbt(bt);
 760                 } else {
 761                         /*
 762                          * If the delta is greater than the timer period then
 763                          * just reset our time base instead of trying to catch
 764                          * up.
 765                          */
 766                         vlapic->timer_fire_bt = btnow;
 767                         VLAPIC_CTR2(vlapic, "vlapic timer lagging by %lu "
 768                             "usecs, period is %lu usecs - resetting time base",
 769                             bttosbt(bt) / SBT_1US,
 770                             bttosbt(vlapic->timer_period_bt) / SBT_1US);
 771                 }
 772
 773                 bintime_add(&vlapic->timer_fire_bt, &vlapic->timer_period_bt);
 774                 callout_reset_sbt(&vlapic->callout, rem_sbt, 0,
 775                     vlapic_callout_handler, vlapic, 0);
 776         }
 777 done:
 778         VLAPIC_TIMER_UNLOCK(vlapic);
 779 }
 780
 781 void
 782 vlapic_icrtmr_write_handler(struct vlapic *vlapic)
 783 {
 784         struct LAPIC *lapic;
 785         sbintime_t sbt;
 786         uint32_t icr_timer;
 787
 788         VLAPIC_TIMER_LOCK(vlapic);
 789
 790         lapic = vlapic->apic_page;
 791         icr_timer = lapic->icr_timer;
 792
 793         vlapic->timer_period_bt = vlapic->timer_freq_bt;
 794         bintime_mul(&vlapic->timer_period_bt, icr_timer);
 795
 796         if (icr_timer != 0) {
 797                 binuptime(&vlapic->timer_fire_bt);
 798                 bintime_add(&vlapic->timer_fire_bt, &vlapic->timer_period_bt);
 799
 800                 sbt = bttosbt(vlapic->timer_period_bt);
 801                 callout_reset_sbt(&vlapic->callout, sbt, 0,
 802                     vlapic_callout_handler, vlapic, 0);
 803         } else
 804                 callout_stop(&vlapic->callout);
 805
 806         VLAPIC_TIMER_UNLOCK(vlapic);
 807 }
 808
 809 /*
 810  * This function populates 'dmask' with the set of vcpus that match the
 811  * addressing specified by the (dest, phys, lowprio) tuple.
 812  *
 813  * 'x2apic_dest' specifies whether 'dest' is interpreted as x2APIC (32-bit)
 814  * or xAPIC (8-bit) destination field.
 815  */
 816 static void
 817 vlapic_calcdest(struct vm *vm, cpuset_t *dmask, uint32_t dest, bool phys,
 818     bool lowprio, bool x2apic_dest)
 819 {
 820         struct vlapic *vlapic;
 821         uint32_t dfr, ldr, ldest, cluster;
 822         uint32_t mda_flat_ldest, mda_cluster_ldest, mda_ldest, mda_cluster_id;
 823         cpuset_t amask;
 824         int vcpuid;
 825
 826         if ((x2apic_dest && dest == 0xffffffff) ||
 827             (!x2apic_dest && dest == 0xff)) {
 828                 /*
 829                  * Broadcast in both logical and physical modes.
 830                  */
 831                 *dmask = vm_active_cpus(vm);
 832                 return;
 833         }
 834
 835         if (phys) {
 836                 /*
 837                  * Physical mode: destination is APIC ID.
 838                  */
 839                 CPU_ZERO(dmask);
 840                 vcpuid = vm_apicid2vcpuid(vm, dest);
 841                 if (vcpuid < VM_MAXCPU)
 842                         CPU_SET(vcpuid, dmask);
 843         } else {
 844                 /*
 845                  * In the "Flat Model" the MDA is interpreted as an 8-bit wide
 846                  * bitmask. This model is only available in the xAPIC mode.
 847                  */
 848                 mda_flat_ldest = dest & 0xff;
 849
 850                 /*
 851                  * In the "Cluster Model" the MDA is used to identify a
 852                  * specific cluster and a set of APICs in that cluster.
 853                  */
 854                 if (x2apic_dest) {
 855                         mda_cluster_id = dest >> 16;
 856                         mda_cluster_ldest = dest & 0xffff;
 857                 } else {
 858                         mda_cluster_id = (dest >> 4) & 0xf;
 859                         mda_cluster_ldest = dest & 0xf;
 860                 }
 861
 862                 /*
 863                  * Logical mode: match each APIC that has a bit set
 864                  * in its LDR that matches a bit in the ldest.
 865                  */
 866                 CPU_ZERO(dmask);
 867                 amask = vm_active_cpus(vm);
 868                 while ((vcpuid = CPU_FFS(&amask)) != 0) {
 869                         vcpuid--;
 870                         CPU_CLR(vcpuid, &amask);
 871
 872                         vlapic = vm_lapic(vm, vcpuid);
 873                         dfr = vlapic->apic_page->dfr;
 874                         ldr = vlapic->apic_page->ldr;
 875
 876                         if ((dfr & APIC_DFR_MODEL_MASK) ==
 877                             APIC_DFR_MODEL_FLAT) {
 878                                 ldest = ldr >> 24;
 879                                 mda_ldest = mda_flat_ldest;
 880                         } else if ((dfr & APIC_DFR_MODEL_MASK) ==
 881                             APIC_DFR_MODEL_CLUSTER) {
 882                                 if (x2apic(vlapic)) {
 883                                         cluster = ldr >> 16;
 884                                         ldest = ldr & 0xffff;
 885                                 } else {
 886                                         cluster = ldr >> 28;
 887                                         ldest = (ldr >> 24) & 0xf;
 888                                 }
 889                                 if (cluster != mda_cluster_id)
 890                                         continue;
 891                                 mda_ldest = mda_cluster_ldest;
 892                         } else {
 893                                 /*
 894                                  * Guest has configured a bad logical
 895                                  * model for this vcpu - skip it.
 896                                  */
 897                                 VLAPIC_CTR1(vlapic, "vlapic has bad logical "
 898                                     "model %x - cannot deliver interrupt", dfr);
 899                                 continue;
 900                         }
 901
 902                         if ((mda_ldest & ldest) != 0) {
 903                                 CPU_SET(vcpuid, dmask);
 904                                 if (lowprio)
 905                                         break;
 906                         }
 907                 }
 908         }
 909 }
 910
 911 static VMM_STAT_ARRAY(IPIS_SENT, VM_MAXCPU, "ipis sent to vcpu");
 912
 913 static void
 914 vlapic_set_tpr(struct vlapic *vlapic, uint8_t val)
 915 {
 916         struct LAPIC *lapic = vlapic->apic_page;
 917
 918         if (lapic->tpr != val) {
 919                 VCPU_CTR2(vlapic->vm, vlapic->vcpuid, "vlapic TPR changed "
 920                     "from %#x to %#x", lapic->tpr, val);
 921                 lapic->tpr = val;
 922                 vlapic_update_ppr(vlapic);
 923         }
 924 }
 925
 926 static uint8_t
 927 vlapic_get_tpr(struct vlapic *vlapic)
 928 {
 929         struct LAPIC *lapic = vlapic->apic_page;
 930
 931         return (lapic->tpr);
 932 }
 933
 934 void
 935 vlapic_set_cr8(struct vlapic *vlapic, uint64_t val)
 936 {
 937         uint8_t tpr;
 938
 939         if (val & ~0xf) {
 940                 vm_inject_gp(vlapic->vm, vlapic->vcpuid);
 941                 return;
 942         }
 943
 944         tpr = val << 4;
 945         vlapic_set_tpr(vlapic, tpr);
 946 }
 947
 948 uint64_t
 949 vlapic_get_cr8(struct vlapic *vlapic)
 950 {
 951         uint8_t tpr;
 952
 953         tpr = vlapic_get_tpr(vlapic);
 954         return (tpr >> 4);
 955 }
 956
 957 int
 958 vlapic_icrlo_write_handler(struct vlapic *vlapic, bool *retu)
 959 {
 960         int i;
 961         bool phys;
 962         cpuset_t dmask;
 963         uint64_t icrval;
 964         uint32_t dest, vec, mode;
 965         struct vlapic *vlapic2;
 966         struct vm_exit *vmexit;
 967         struct LAPIC *lapic;
 968
 969         lapic = vlapic->apic_page;
 970         lapic->icr_lo &= ~APIC_DELSTAT_PEND;
 971         icrval = ((uint64_t)lapic->icr_hi << 32) | lapic->icr_lo;
 972
 973         if (x2apic(vlapic))
 974                 dest = icrval >> 32;
 975         else
 976                 dest = icrval >> (32 + 24);
 977         vec = icrval & APIC_VECTOR_MASK;
 978         mode = icrval & APIC_DELMODE_MASK;
 979
 980         if (mode == APIC_DELMODE_FIXED && vec < 16) {
 981                 vlapic_set_error(vlapic, APIC_ESR_SEND_ILLEGAL_VECTOR);
 982                 VLAPIC_CTR1(vlapic, "Ignoring invalid IPI %d", vec);
 983                 return (0);
 984         }
 985
 986         VLAPIC_CTR2(vlapic, "icrlo 0x%016lx triggered ipi %d", icrval, vec);
 987
 988         if (mode == APIC_DELMODE_FIXED || mode == APIC_DELMODE_NMI) {
 989                 switch (icrval & APIC_DEST_MASK) {
 990                 case APIC_DEST_DESTFLD:
 991                         phys = ((icrval & APIC_DESTMODE_LOG) == 0);
 992                         vlapic_calcdest(vlapic->vm, &dmask, dest, phys, false,
 993                             x2apic(vlapic));
 994                         break;
 995                 case APIC_DEST_SELF:
 996                         CPU_SETOF(vlapic->vcpuid, &dmask);
 997                         break;
 998                 case APIC_DEST_ALLISELF:
 999                         dmask = vm_active_cpus(vlapic->vm);
1000                         break;
1001                 case APIC_DEST_ALLESELF:
1002                         dmask = vm_active_cpus(vlapic->vm);
1003                         CPU_CLR(vlapic->vcpuid, &dmask);
1004                         break;
1005                 default:
1006                         CPU_ZERO(&dmask);       /* satisfy gcc */
1007                         break;
1008                 }
1009
1010                 while ((i = CPU_FFS(&dmask)) != 0) {
1011                         i--;
1012                         CPU_CLR(i, &dmask);
1013                         if (mode == APIC_DELMODE_FIXED) {
1014                                 lapic_intr_edge(vlapic->vm, i, vec);
1015                                 vmm_stat_array_incr(vlapic->vm, vlapic->vcpuid,
1016                                                     IPIS_SENT, i, 1);
1017                                 VLAPIC_CTR2(vlapic, "vlapic sending ipi %d "
1018                                     "to vcpuid %d", vec, i);
1019                         } else {
1020                                 vm_inject_nmi(vlapic->vm, i);
1021                                 VLAPIC_CTR1(vlapic, "vlapic sending ipi nmi "
1022                                     "to vcpuid %d", i);
1023                         }
1024                 }
1025
1026                 return (0);     /* handled completely in the kernel */
1027         }
1028
1029         if (mode == APIC_DELMODE_INIT) {
1030                 if ((icrval & APIC_LEVEL_MASK) == APIC_LEVEL_DEASSERT)
1031                         return (0);
1032
1033                 if (vlapic->vcpuid == 0 && dest != 0 && dest < VM_MAXCPU) {
1034                         vlapic2 = vm_lapic(vlapic->vm, dest);
1035
1036                         /* move from INIT to waiting-for-SIPI state */
1037                         if (vlapic2->boot_state == BS_INIT) {
1038                                 vlapic2->boot_state = BS_SIPI;
1039                         }
1040
1041                         return (0);
1042                 }
1043         }
1044
1045         if (mode == APIC_DELMODE_STARTUP) {
1046                 if (vlapic->vcpuid == 0 && dest != 0 && dest < VM_MAXCPU) {
1047                         vlapic2 = vm_lapic(vlapic->vm, dest);
1048
1049                         /*
1050                          * Ignore SIPIs in any state other than wait-for-SIPI
1051                          */
1052                         if (vlapic2->boot_state != BS_SIPI)
1053                                 return (0);
1054
1055                         vlapic2->boot_state = BS_RUNNING;
1056
1057                         *retu = true;
1058                         vmexit = vm_exitinfo(vlapic->vm, vlapic->vcpuid);
1059                         vmexit->exitcode = VM_EXITCODE_SPINUP_AP;
1060                         vmexit->u.spinup_ap.vcpu = dest;
1061                         vmexit->u.spinup_ap.rip = vec << PAGE_SHIFT;
1062
1063                         return (0);
1064                 }
1065         }
1066
1067         /*
1068          * This will cause a return to userland.
1069          */
1070         return (1);
1071 }
1072
1073 void
1074 vlapic_self_ipi_handler(struct vlapic *vlapic, uint64_t val)
1075 {
1076         int vec;
1077
1078         KASSERT(x2apic(vlapic), ("SELF_IPI does not exist in xAPIC mode"));
1079
1080         vec = val & 0xff;
1081         lapic_intr_edge(vlapic->vm, vlapic->vcpuid, vec);
1082         vmm_stat_array_incr(vlapic->vm, vlapic->vcpuid, IPIS_SENT,
1083             vlapic->vcpuid, 1);
1084         VLAPIC_CTR1(vlapic, "vlapic self-ipi %d", vec);
1085 }
1086
1087 int
1088 vlapic_pending_intr(struct vlapic *vlapic, int *vecptr)
1089 {
1090         struct LAPIC    *lapic = vlapic->apic_page;
1091         int              idx, i, bitpos, vector;
1092         uint32_t        *irrptr, val;
1093
1094         if (vlapic->ops.pending_intr)
1095                 return ((*vlapic->ops.pending_intr)(vlapic, vecptr));
1096
1097         irrptr = &lapic->irr0;
1098
1099         for (i = 7; i >= 0; i--) {
1100                 idx = i * 4;
1101                 val = atomic_load_acq_int(&irrptr[idx]);
1102                 bitpos = fls(val);
1103                 if (bitpos != 0) {
1104                         vector = i * 32 + (bitpos - 1);
1105                         if (PRIO(vector) > PRIO(lapic->ppr)) {
1106                                 VLAPIC_CTR1(vlapic, "pending intr %d", vector);
1107                                 if (vecptr != NULL)
1108                                         *vecptr = vector;
1109                                 return (1);
1110                         } else
1111                                 break;
1112                 }
1113         }
1114         return (0);
1115 }
1116
1117 void
1118 vlapic_intr_accepted(struct vlapic *vlapic, int vector)
1119 {
1120         struct LAPIC    *lapic = vlapic->apic_page;
1121         uint32_t        *irrptr, *isrptr;
1122         int             idx, stk_top;
1123
1124         if (vlapic->ops.intr_accepted)
1125                 return ((*vlapic->ops.intr_accepted)(vlapic, vector));
1126
1127         /*
1128          * clear the ready bit for vector being accepted in irr
1129          * and set the vector as in service in isr.
1130          */
1131         idx = (vector / 32) * 4;
1132
1133         irrptr = &lapic->irr0;
1134         atomic_clear_int(&irrptr[idx], 1 << (vector % 32));
1135         VLAPIC_CTR_IRR(vlapic, "vlapic_intr_accepted");
1136
1137         isrptr = &lapic->isr0;
1138         isrptr[idx] |= 1 << (vector % 32);
1139         VLAPIC_CTR_ISR(vlapic, "vlapic_intr_accepted");
1140
1141         /*
1142          * Update the PPR
1143          */
1144         vlapic->isrvec_stk_top++;
1145
1146         stk_top = vlapic->isrvec_stk_top;
1147         if (stk_top >= ISRVEC_STK_SIZE)
1148                 panic("isrvec_stk_top overflow %d", stk_top);
1149
1150         vlapic->isrvec_stk[stk_top] = vector;
1151         vlapic_update_ppr(vlapic);
1152 }
1153
1154 void
1155 vlapic_svr_write_handler(struct vlapic *vlapic)
1156 {
1157         struct LAPIC *lapic;
1158         uint32_t old, new, changed;
1159
1160         lapic = vlapic->apic_page;
1161
1162         new = lapic->svr;
1163         old = vlapic->svr_last;
1164         vlapic->svr_last = new;
1165
1166         changed = old ^ new;
1167         if ((changed & APIC_SVR_ENABLE) != 0) {
1168                 if ((new & APIC_SVR_ENABLE) == 0) {
1169                         /*
1170                          * The apic is now disabled so stop the apic timer
1171                          * and mask all the LVT entries.
1172                          */
1173                         VLAPIC_CTR0(vlapic, "vlapic is software-disabled");
1174                         VLAPIC_TIMER_LOCK(vlapic);
1175                         callout_stop(&vlapic->callout);
1176                         VLAPIC_TIMER_UNLOCK(vlapic);
1177                         vlapic_mask_lvts(vlapic);
1178                 } else {
1179                         /*
1180                          * The apic is now enabled so restart the apic timer
1181                          * if it is configured in periodic mode.
1182                          */
1183                         VLAPIC_CTR0(vlapic, "vlapic is software-enabled");
1184                         if (vlapic_periodic_timer(vlapic))
1185                                 vlapic_icrtmr_write_handler(vlapic);
1186                 }
1187         }
1188 }
1189
1190 int
1191 vlapic_read(struct vlapic *vlapic, int mmio_access, uint64_t offset,
1192     uint64_t *data, bool *retu)
1193 {
1194         struct LAPIC    *lapic = vlapic->apic_page;
1195         uint32_t        *reg;
1196         int              i;
1197
1198         /* Ignore MMIO accesses in x2APIC mode */
1199         if (x2apic(vlapic) && mmio_access) {
1200                 VLAPIC_CTR1(vlapic, "MMIO read from offset %#lx in x2APIC mode",
1201                     offset);
1202                 *data = 0;
1203                 goto done;
1204         }
1205
1206         if (!x2apic(vlapic) && !mmio_access) {
1207                 /*
1208                  * XXX Generate GP fault for MSR accesses in xAPIC mode
1209                  */
1210                 VLAPIC_CTR1(vlapic, "x2APIC MSR read from offset %#lx in "
1211                     "xAPIC mode", offset);
1212                 *data = 0;
1213                 goto done;
1214         }
1215
1216         if (offset > sizeof(*lapic)) {
1217                 *data = 0;
1218                 goto done;
1219         }
1220
1221         offset &= ~3;
1222         switch(offset)
1223         {
1224                 case APIC_OFFSET_ID:
1225                         *data = lapic->id;
1226                         break;
1227                 case APIC_OFFSET_VER:
1228                         *data = lapic->version;
1229                         break;
1230                 case APIC_OFFSET_TPR:
1231                         *data = vlapic_get_tpr(vlapic);
1232                         break;
1233                 case APIC_OFFSET_APR:
1234                         *data = lapic->apr;
1235                         break;
1236                 case APIC_OFFSET_PPR:
1237                         *data = lapic->ppr;
1238                         break;
1239                 case APIC_OFFSET_EOI:
1240                         *data = lapic->eoi;
1241                         break;
1242                 case APIC_OFFSET_LDR:
1243                         *data = lapic->ldr;
1244                         break;
1245                 case APIC_OFFSET_DFR:
1246                         *data = lapic->dfr;
1247                         break;
1248                 case APIC_OFFSET_SVR:
1249                         *data = lapic->svr;
1250                         break;
1251                 case APIC_OFFSET_ISR0 ... APIC_OFFSET_ISR7:
1252                         i = (offset - APIC_OFFSET_ISR0) >> 2;
1253                         reg = &lapic->isr0;
1254                         *data = *(reg + i);
1255                         break;
1256                 case APIC_OFFSET_TMR0 ... APIC_OFFSET_TMR7:
1257                         i = (offset - APIC_OFFSET_TMR0) >> 2;
1258                         reg = &lapic->tmr0;
1259                         *data = *(reg + i);
1260                         break;
1261                 case APIC_OFFSET_IRR0 ... APIC_OFFSET_IRR7:
1262                         i = (offset - APIC_OFFSET_IRR0) >> 2;
1263                         reg = &lapic->irr0;
1264                         *data = atomic_load_acq_int(reg + i);
1265                         break;
1266                 case APIC_OFFSET_ESR:
1267                         *data = lapic->esr;
1268                         break;
1269                 case APIC_OFFSET_ICR_LOW:
1270                         *data = lapic->icr_lo;
1271                         if (x2apic(vlapic))
1272                                 *data |= (uint64_t)lapic->icr_hi << 32;
1273                         break;
1274                 case APIC_OFFSET_ICR_HI:
1275                         *data = lapic->icr_hi;
1276                         break;
1277                 case APIC_OFFSET_CMCI_LVT:
1278                 case APIC_OFFSET_TIMER_LVT ... APIC_OFFSET_ERROR_LVT:
1279                         *data = vlapic_get_lvt(vlapic, offset);
1280 #ifdef INVARIANTS
1281                         reg = vlapic_get_lvtptr(vlapic, offset);
1282                         KASSERT(*data == *reg, ("inconsistent lvt value at "
1283                             "offset %#lx: %#lx/%#x", offset, *data, *reg));
1284 #endif
1285                         break;
1286                 case APIC_OFFSET_TIMER_ICR:
1287                         *data = lapic->icr_timer;
1288                         break;
1289                 case APIC_OFFSET_TIMER_CCR:
1290                         *data = vlapic_get_ccr(vlapic);
1291                         break;
1292                 case APIC_OFFSET_TIMER_DCR:
1293                         *data = lapic->dcr_timer;
1294                         break;
1295                 case APIC_OFFSET_SELF_IPI:
1296                         /*
1297                          * XXX generate a GP fault if vlapic is in x2apic mode
1298                          */
1299                         *data = 0;
1300                         break;
1301                 case APIC_OFFSET_RRR:
1302                 default:
1303                         *data = 0;
1304                         break;
1305         }
1306 done:
1307         VLAPIC_CTR2(vlapic, "vlapic read offset %#x, data %#lx", offset, *data);
1308         return 0;
1309 }
1310
1311 int
1312 vlapic_write(struct vlapic *vlapic, int mmio_access, uint64_t offset,
1313     uint64_t data, bool *retu)
1314 {
1315         struct LAPIC    *lapic = vlapic->apic_page;
1316         uint32_t        *regptr;
1317         int             retval;
1318
1319         KASSERT((offset & 0xf) == 0 && offset < PAGE_SIZE,
1320             ("vlapic_write: invalid offset %#lx", offset));
1321
1322         VLAPIC_CTR2(vlapic, "vlapic write offset %#lx, data %#lx",
1323             offset, data);
1324
1325         if (offset > sizeof(*lapic))
1326                 return (0);
1327
1328         /* Ignore MMIO accesses in x2APIC mode */
1329         if (x2apic(vlapic) && mmio_access) {
1330                 VLAPIC_CTR2(vlapic, "MMIO write of %#lx to offset %#lx "
1331                     "in x2APIC mode", data, offset);
1332                 return (0);
1333         }
1334
1335         /*
1336          * XXX Generate GP fault for MSR accesses in xAPIC mode
1337          */
1338         if (!x2apic(vlapic) && !mmio_access) {
1339                 VLAPIC_CTR2(vlapic, "x2APIC MSR write of %#lx to offset %#lx "
1340                     "in xAPIC mode", data, offset);
1341                 return (0);
1342         }
1343
1344         retval = 0;
1345         switch(offset)
1346         {
1347                 case APIC_OFFSET_ID:
1348                         lapic->id = data;
1349                         vlapic_id_write_handler(vlapic);
1350                         break;
1351                 case APIC_OFFSET_TPR:
1352                         vlapic_set_tpr(vlapic, data & 0xff);
1353                         break;
1354                 case APIC_OFFSET_EOI:
1355                         vlapic_process_eoi(vlapic);
1356                         break;
1357                 case APIC_OFFSET_LDR:
1358                         lapic->ldr = data;
1359                         vlapic_ldr_write_handler(vlapic);
1360                         break;
1361                 case APIC_OFFSET_DFR:
1362                         lapic->dfr = data;
1363                         vlapic_dfr_write_handler(vlapic);
1364                         break;
1365                 case APIC_OFFSET_SVR:
1366                         lapic->svr = data;
1367                         vlapic_svr_write_handler(vlapic);
1368                         break;
1369                 case APIC_OFFSET_ICR_LOW:
1370                         lapic->icr_lo = data;
1371                         if (x2apic(vlapic))
1372                                 lapic->icr_hi = data >> 32;
1373                         retval = vlapic_icrlo_write_handler(vlapic, retu);
1374                         break;
1375                 case APIC_OFFSET_ICR_HI:
1376                         lapic->icr_hi = data;
1377                         break;
1378                 case APIC_OFFSET_CMCI_LVT:
1379                 case APIC_OFFSET_TIMER_LVT ... APIC_OFFSET_ERROR_LVT:
1380                         regptr = vlapic_get_lvtptr(vlapic, offset);
1381                         *regptr = data;
1382                         vlapic_lvt_write_handler(vlapic, offset);
1383                         break;
1384                 case APIC_OFFSET_TIMER_ICR:
1385                         lapic->icr_timer = data;
1386                         vlapic_icrtmr_write_handler(vlapic);
1387                         break;
1388
1389                 case APIC_OFFSET_TIMER_DCR:
1390                         lapic->dcr_timer = data;
1391                         vlapic_dcr_write_handler(vlapic);
1392                         break;
1393
1394                 case APIC_OFFSET_ESR:
1395                         vlapic_esr_write_handler(vlapic);
1396                         break;
1397
1398                 case APIC_OFFSET_SELF_IPI:
1399                         if (x2apic(vlapic))
1400                                 vlapic_self_ipi_handler(vlapic, data);
1401                         break;
1402
1403                 case APIC_OFFSET_VER:
1404                 case APIC_OFFSET_APR:
1405                 case APIC_OFFSET_PPR:
1406                 case APIC_OFFSET_RRR:
1407                 case APIC_OFFSET_ISR0 ... APIC_OFFSET_ISR7:
1408                 case APIC_OFFSET_TMR0 ... APIC_OFFSET_TMR7:
1409                 case APIC_OFFSET_IRR0 ... APIC_OFFSET_IRR7:
1410                 case APIC_OFFSET_TIMER_CCR:
1411                 default:
1412                         // Read only.
1413                         break;
1414         }
1415
1416         return (retval);
1417 }
1418
1419 static void
1420 vlapic_reset(struct vlapic *vlapic)
1421 {
1422         struct LAPIC *lapic;
1423
1424         lapic = vlapic->apic_page;
1425         bzero(lapic, sizeof(struct LAPIC));
1426
1427         lapic->id = vlapic_get_id(vlapic);
1428         lapic->version = VLAPIC_VERSION;
1429         lapic->version |= (VLAPIC_MAXLVT_INDEX << MAXLVTSHIFT);
1430         lapic->dfr = 0xffffffff;
1431         lapic->svr = APIC_SVR_VECTOR;
1432         vlapic_mask_lvts(vlapic);
1433         vlapic_reset_tmr(vlapic);
1434
1435         lapic->dcr_timer = 0;
1436         vlapic_dcr_write_handler(vlapic);
1437
1438         if (vlapic->vcpuid == 0)
1439                 vlapic->boot_state = BS_RUNNING;        /* BSP */
1440         else
1441                 vlapic->boot_state = BS_INIT;           /* AP */
1442
1443         vlapic->svr_last = lapic->svr;
1444 }
1445
1446 void
1447 vlapic_init(struct vlapic *vlapic)
1448 {
1449         KASSERT(vlapic->vm != NULL, ("vlapic_init: vm is not initialized"));
1450         KASSERT(vlapic->vcpuid >= 0 && vlapic->vcpuid < VM_MAXCPU,
1451             ("vlapic_init: vcpuid is not initialized"));
1452         KASSERT(vlapic->apic_page != NULL, ("vlapic_init: apic_page is not "
1453             "initialized"));
1454
1455         /*
1456          * If the vlapic is configured in x2apic mode then it will be
1457          * accessed in the critical section via the MSR emulation code.
1458          *
1459          * Therefore the timer mutex must be a spinlock because blockable
1460          * mutexes cannot be acquired in a critical section.
1461          */
1462         mtx_init(&vlapic->timer_mtx, "vlapic timer mtx", NULL, MTX_SPIN);
1463         callout_init(&vlapic->callout, 1);
1464
1465         vlapic->msr_apicbase = DEFAULT_APIC_BASE | APICBASE_ENABLED;
1466
1467         if (vlapic->vcpuid == 0)
1468                 vlapic->msr_apicbase |= APICBASE_BSP;
1469
1470         vlapic_reset(vlapic);
1471 }
1472
1473 void
1474 vlapic_cleanup(struct vlapic *vlapic)
1475 {
1476
1477         callout_drain(&vlapic->callout);
1478 }
1479
1480 uint64_t
1481 vlapic_get_apicbase(struct vlapic *vlapic)
1482 {
1483
1484         return (vlapic->msr_apicbase);
1485 }
1486
1487 int
1488 vlapic_set_apicbase(struct vlapic *vlapic, uint64_t new)
1489 {
1490
1491         if (vlapic->msr_apicbase != new) {
1492                 VLAPIC_CTR2(vlapic, "Changing APIC_BASE MSR from %#lx to %#lx "
1493                     "not supported", vlapic->msr_apicbase, new);
1494                 return (-1);
1495         }
1496
1497         return (0);
1498 }
1499
1500 void
1501 vlapic_set_x2apic_state(struct vm *vm, int vcpuid, enum x2apic_state state)
1502 {
1503         struct vlapic *vlapic;
1504         struct LAPIC *lapic;
1505
1506         vlapic = vm_lapic(vm, vcpuid);
1507
1508         if (state == X2APIC_DISABLED)
1509                 vlapic->msr_apicbase &= ~APICBASE_X2APIC;
1510         else
1511                 vlapic->msr_apicbase |= APICBASE_X2APIC;
1512
1513         /*
1514          * Reset the local APIC registers whose values are mode-dependent.
1515          *
1516          * XXX this works because the APIC mode can be changed only at vcpu
1517          * initialization time.
1518          */
1519         lapic = vlapic->apic_page;
1520         lapic->id = vlapic_get_id(vlapic);
1521         if (x2apic(vlapic)) {
1522                 lapic->ldr = x2apic_ldr(vlapic);
1523                 lapic->dfr = 0;
1524         } else {
1525                 lapic->ldr = 0;
1526                 lapic->dfr = 0xffffffff;
1527         }
1528
1529         if (state == X2APIC_ENABLED) {
1530                 if (vlapic->ops.enable_x2apic_mode)
1531                         (*vlapic->ops.enable_x2apic_mode)(vlapic);
1532         }
1533 }
1534
1535 void
1536 vlapic_deliver_intr(struct vm *vm, bool level, uint32_t dest, bool phys,
1537     int delmode, int vec)
1538 {
1539         bool lowprio;
1540         int vcpuid;
1541         cpuset_t dmask;
1542
1543         if (delmode != IOART_DELFIXED &&
1544             delmode != IOART_DELLOPRI &&
1545             delmode != IOART_DELEXINT) {
1546                 VM_CTR1(vm, "vlapic intr invalid delmode %#x", delmode);
1547                 return;
1548         }
1549         lowprio = (delmode == IOART_DELLOPRI);
1550
1551         /*
1552          * We don't provide any virtual interrupt redirection hardware so
1553          * all interrupts originating from the ioapic or MSI specify the
1554          * 'dest' in the legacy xAPIC format.
1555          */
1556         vlapic_calcdest(vm, &dmask, dest, phys, lowprio, false);
1557
1558         while ((vcpuid = CPU_FFS(&dmask)) != 0) {
1559                 vcpuid--;
1560                 CPU_CLR(vcpuid, &dmask);
1561                 if (delmode == IOART_DELEXINT) {
1562                         vm_inject_extint(vm, vcpuid);
1563                 } else {
1564                         lapic_set_intr(vm, vcpuid, vec, level);
1565                 }
1566         }
1567 }
1568
1569 void
1570 vlapic_post_intr(struct vlapic *vlapic, int hostcpu, int ipinum)
1571 {
1572         /*
1573          * Post an interrupt to the vcpu currently running on 'hostcpu'.
1574          *
1575          * This is done by leveraging features like Posted Interrupts (Intel)
1576          * Doorbell MSR (AMD AVIC) that avoid a VM exit.
1577          *
1578          * If neither of these features are available then fallback to
1579          * sending an IPI to 'hostcpu'.
1580          */
1581         if (vlapic->ops.post_intr)
1582                 (*vlapic->ops.post_intr)(vlapic, hostcpu);
1583         else
1584                 ipi_cpu(hostcpu, ipinum);
1585 }
1586
1587 bool
1588 vlapic_enabled(struct vlapic *vlapic)
1589 {
1590         struct LAPIC *lapic = vlapic->apic_page;
1591
1592         if ((vlapic->msr_apicbase & APICBASE_ENABLED) != 0 &&
1593             (lapic->svr & APIC_SVR_ENABLE) != 0)
1594                 return (true);
1595         else
1596                 return (false);
1597 }
1598
1599 static void
1600 vlapic_set_tmr(struct vlapic *vlapic, int vector, bool level)
1601 {
1602         struct LAPIC *lapic;
1603         uint32_t *tmrptr, mask;
1604         int idx;
1605
1606         lapic = vlapic->apic_page;
1607         tmrptr = &lapic->tmr0;
1608         idx = (vector / 32) * 4;
1609         mask = 1 << (vector % 32);
1610         if (level)
1611                 tmrptr[idx] |= mask;
1612         else
1613                 tmrptr[idx] &= ~mask;
1614
1615         if (vlapic->ops.set_tmr != NULL)
1616                 (*vlapic->ops.set_tmr)(vlapic, vector, level);
1617 }
1618
1619 void
1620 vlapic_reset_tmr(struct vlapic *vlapic)
1621 {
1622         int vector;
1623
1624         VLAPIC_CTR0(vlapic, "vlapic resetting all vectors to edge-triggered");
1625
1626         for (vector = 0; vector <= 255; vector++)
1627                 vlapic_set_tmr(vlapic, vector, false);
1628 }
1629
1630 void
1631 vlapic_set_tmr_level(struct vlapic *vlapic, uint32_t dest, bool phys,
1632     int delmode, int vector)
1633 {
1634         cpuset_t dmask;
1635         bool lowprio;
1636
1637         KASSERT(vector >= 0 && vector <= 255, ("invalid vector %d", vector));
1638
1639         /*
1640          * A level trigger is valid only for fixed and lowprio delivery modes.
1641          */
1642         if (delmode != APIC_DELMODE_FIXED && delmode != APIC_DELMODE_LOWPRIO) {
1643                 VLAPIC_CTR1(vlapic, "Ignoring level trigger-mode for "
1644                     "delivery-mode %d", delmode);
1645                 return;
1646         }
1647
1648         lowprio = (delmode == APIC_DELMODE_LOWPRIO);
1649         vlapic_calcdest(vlapic->vm, &dmask, dest, phys, lowprio, false);
1650
1651         if (!CPU_ISSET(vlapic->vcpuid, &dmask))
1652                 return;
1653
1654         VLAPIC_CTR1(vlapic, "vector %d set to level-triggered", vector);
1655         vlapic_set_tmr(vlapic, vector, true);
1656 }