1 /* $NetBSD: s3c2xx0reg.h,v 1.4 2004/02/12 03:47:29 bsh Exp $ */
4 * Copyright (c) 2002, 2003 Fujitsu Component Limited
5 * Copyright (c) 2002, 2003 Genetec Corporation
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37 /* s3c2410-specific registers */
38 #define UMCON_AFC (1 << 4) /* auto flow control */
39 #define UMSTAT_DCTS (1 << 2) /* CTS change */
40 #define ULCON_IR (1 << 6)
41 #define ULCON_PARITY_SHIFT 3
46 * UFSTAT_TXFULL register differs between Exynos and others.
47 * Others have UFSTAT_TXFULL (1 << 9)
49 #define UFSTAT_TXFULL (1 << 24)
51 #define SSCOM_UINTM 0x038
52 #define SSCOM_UINTP 0x030
54 /* common for s3c2800 and s3c24x0 */
55 #define SSCOM_ULCON 0x00 /* UART line control */
56 #define ULCON_PARITY_NONE (0 << ULCON_PARITY_SHIFT)
57 #define ULCON_PARITY_ODD (4 << ULCON_PARITY_SHIFT)
58 #define ULCON_PARITY_EVEN (5 << ULCON_PARITY_SHIFT)
59 #define ULCON_PARITY_ONE (6 << ULCON_PARITY_SHIFT)
60 #define ULCON_PARITY_ZERO (7 << ULCON_PARITY_SHIFT)
61 #define ULCON_STOP (1 << 2)
62 #define ULCON_LENGTH_5 0
63 #define ULCON_LENGTH_6 1
64 #define ULCON_LENGTH_7 2
65 #define ULCON_LENGTH_8 3
66 #define SSCOM_UCON 0x04 /* UART control */
67 #define UCON_TXINT_TYPE (1 << 9) /* Tx interrupt. 0=pulse,1=level */
68 #define UCON_TXINT_TYPE_LEVEL UCON_TXINT_TYPE
69 #define UCON_TXINT_TYPE_PULSE 0
70 #define UCON_RXINT_TYPE (1 << 8) /* Rx interrupt */
71 #define UCON_RXINT_TYPE_LEVEL UCON_RXINT_TYPE
72 #define UCON_RXINT_TYPE_PULSE 0
73 #define UCON_TOINT (1 << 7) /* Rx timeout interrupt */
74 #define UCON_ERRINT (1 << 6) /* receive error interrupt */
75 #define UCON_LOOP (1 << 5) /* loopback */
76 #define UCON_SBREAK (1 << 4) /* send break */
77 #define UCON_TXMODE_DISABLE (0 << 2)
78 #define UCON_TXMODE_INT (1 << 2)
79 #define UCON_TXMODE_DMA (2 << 2)
80 #define UCON_TXMODE_MASK (3 << 2)
81 #define UCON_RXMODE_DISABLE (0 << 0)
82 #define UCON_RXMODE_INT (1 << 0)
83 #define UCON_RXMODE_DMA (2 << 0)
84 #define UCON_RXMODE_MASK (3 << 0)
85 #define SSCOM_UFCON 0x08 /* FIFO control */
86 #define UFCON_TXTRIGGER_0 (0 << 6)
87 #define UFCON_TXTRIGGER_4 (1 << 6)
88 #define UFCON_TXTRIGGER_8 (2 << 6)
89 #define UFCON_TXTRIGGER_16 (3 << 6)
90 #define UFCON_RXTRIGGER_4 (0 << 4)
91 #define UFCON_RXTRIGGER_8 (1 << 4)
92 #define UFCON_RXTRIGGER_12 (2 << 4)
93 #define UFCON_RXTRIGGER_16 (3 << 4)
94 #define UFCON_TXFIFO_RESET (1 << 2)
95 #define UFCON_RXFIFO_RESET (1 << 1)
96 #define UFCON_FIFO_ENABLE (1 << 0)
97 #define SSCOM_UMCON 0x0c /* MODEM control */
98 #define UMCON_RTS (1 << 0) /* Request to send */
99 #define SSCOM_UTRSTAT 0x10 /* Status register */
100 #define UTRSTAT_TXSHIFTER_EMPTY ( 1<< 2)
101 #define UTRSTAT_TXEMPTY (1 << 1) /* TX fifo or buffer empty */
102 #define UTRSTAT_RXREADY (1 << 0) /* RX fifo or buffer is not empty */
103 #define SSCOM_UERSTAT 0x14 /* Error status register */
104 #define UERSTAT_BREAK (1 << 3) /* Break signal, not 2410 */
105 #define UERSTAT_FRAME (1 << 2) /* Frame error */
106 #define UERSTAT_PARITY (1 << 1) /* Parity error, not 2410 */
107 #define UERSTAT_OVERRUN (1 << 0) /* Overrun */
108 #define UERSTAT_ALL_ERRORS \
109 (UERSTAT_OVERRUN|UERSTAT_BREAK|UERSTAT_FRAME|UERSTAT_PARITY)
110 #define SSCOM_UFSTAT 0x18 /* Fifo status register */
111 #define UFSTAT_RXFULL (1 <<8) /* Rx fifo full */
112 #define UFSTAT_TXCOUNT_SHIFT 4 /* TX FIFO count */
113 #define UFSTAT_TXCOUNT (0x0f << UFSTAT_TXCOUNT_SHIFT)
114 #define UFSTAT_RXCOUNT_SHIFT 0 /* RX FIFO count */
115 #define UFSTAT_RXCOUNT (0x0f << UFSTAT_RXCOUNT_SHIFT)
116 #define SSCOM_UMSTAT 0x1c /* Modem status register */
117 #define UMSTAT_CTS (1 << 0) /* Clear to send */
118 #if _BYTE_ORDER == _LITTLE_ENDIAN
119 #define SSCOM_UTXH 0x20 /* Transmit data register */
120 #define SSCOM_URXH 0x24 /* Receive data register */
122 #define SSCOM_UTXH 0x23 /* Transmit data register */
123 #define SSCOM_URXH 0x27 /* Receive data register */
125 #define SSCOM_UBRDIV 0x28 /* baud-reate divisor */
126 #define SSCOM_SIZE 0x2c