2 * Copyright (c) 1991 Regents of the University of California.
4 * Copyright (c) 1994 John S. Dyson
6 * Copyright (c) 1994 David Greenman
8 * Copyright (c) 2003 Peter Wemm
10 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
11 * All rights reserved.
12 * Copyright (c) 2014 Andrew Turner
13 * All rights reserved.
14 * Copyright (c) 2014-2016 The FreeBSD Foundation
15 * All rights reserved.
17 * This code is derived from software contributed to Berkeley by
18 * the Systems Programming Group of the University of Utah Computer
19 * Science Department and William Jolitz of UUNET Technologies Inc.
21 * This software was developed by Andrew Turner under sponsorship from
22 * the FreeBSD Foundation.
24 * Redistribution and use in source and binary forms, with or without
25 * modification, are permitted provided that the following conditions
27 * 1. Redistributions of source code must retain the above copyright
28 * notice, this list of conditions and the following disclaimer.
29 * 2. Redistributions in binary form must reproduce the above copyright
30 * notice, this list of conditions and the following disclaimer in the
31 * documentation and/or other materials provided with the distribution.
32 * 3. All advertising materials mentioning features or use of this software
33 * must display the following acknowledgement:
34 * This product includes software developed by the University of
35 * California, Berkeley and its contributors.
36 * 4. Neither the name of the University nor the names of its contributors
37 * may be used to endorse or promote products derived from this software
38 * without specific prior written permission.
40 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
41 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
42 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
43 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
44 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
45 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
46 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
47 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
48 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
49 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
52 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
55 * Copyright (c) 2003 Networks Associates Technology, Inc.
56 * All rights reserved.
58 * This software was developed for the FreeBSD Project by Jake Burkholder,
59 * Safeport Network Services, and Network Associates Laboratories, the
60 * Security Research Division of Network Associates, Inc. under
61 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
62 * CHATS research program.
64 * Redistribution and use in source and binary forms, with or without
65 * modification, are permitted provided that the following conditions
67 * 1. Redistributions of source code must retain the above copyright
68 * notice, this list of conditions and the following disclaimer.
69 * 2. Redistributions in binary form must reproduce the above copyright
70 * notice, this list of conditions and the following disclaimer in the
71 * documentation and/or other materials provided with the distribution.
73 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
74 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
77 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
78 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
79 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
80 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
81 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
82 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
86 #include <sys/cdefs.h>
87 __FBSDID("$FreeBSD$");
90 * Manages physical address maps.
92 * Since the information managed by this module is
93 * also stored by the logical address mapping module,
94 * this module may throw away valid virtual-to-physical
95 * mappings at almost any time. However, invalidations
96 * of virtual-to-physical mappings must be done as
99 * In order to cope with hardware architectures which
100 * make virtual-to-physical map invalidates expensive,
101 * this module may delay invalidate or reduced protection
102 * operations until such time as they are actually
103 * necessary. This module is given full information as
104 * to which processors are currently using which maps,
105 * and to when physical maps must be made correct.
110 #include <sys/param.h>
111 #include <sys/bitstring.h>
113 #include <sys/systm.h>
114 #include <sys/kernel.h>
116 #include <sys/lock.h>
117 #include <sys/malloc.h>
118 #include <sys/mman.h>
119 #include <sys/msgbuf.h>
120 #include <sys/mutex.h>
121 #include <sys/proc.h>
122 #include <sys/rwlock.h>
124 #include <sys/vmem.h>
125 #include <sys/vmmeter.h>
126 #include <sys/sched.h>
127 #include <sys/sysctl.h>
128 #include <sys/_unrhdr.h>
132 #include <vm/vm_param.h>
133 #include <vm/vm_kern.h>
134 #include <vm/vm_page.h>
135 #include <vm/vm_map.h>
136 #include <vm/vm_object.h>
137 #include <vm/vm_extern.h>
138 #include <vm/vm_pageout.h>
139 #include <vm/vm_pager.h>
140 #include <vm/vm_phys.h>
141 #include <vm/vm_radix.h>
142 #include <vm/vm_reserv.h>
145 #include <machine/machdep.h>
146 #include <machine/md_var.h>
147 #include <machine/pcb.h>
149 #include <arm/include/physmem.h>
151 #define NL0PG (PAGE_SIZE/(sizeof (pd_entry_t)))
152 #define NL1PG (PAGE_SIZE/(sizeof (pd_entry_t)))
153 #define NL2PG (PAGE_SIZE/(sizeof (pd_entry_t)))
154 #define NL3PG (PAGE_SIZE/(sizeof (pt_entry_t)))
156 #define NUL0E L0_ENTRIES
157 #define NUL1E (NUL0E * NL1PG)
158 #define NUL2E (NUL1E * NL2PG)
160 #if !defined(DIAGNOSTIC)
161 #ifdef __GNUC_GNU_INLINE__
162 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
164 #define PMAP_INLINE extern inline
171 * These are configured by the mair_el1 register. This is set up in locore.S
173 #define DEVICE_MEMORY 0
174 #define UNCACHED_MEMORY 1
175 #define CACHED_MEMORY 2
179 #define PV_STAT(x) do { x ; } while (0)
181 #define PV_STAT(x) do { } while (0)
184 #define pmap_l2_pindex(v) ((v) >> L2_SHIFT)
185 #define pa_to_pvh(pa) (&pv_table[pmap_l2_pindex(pa)])
187 #define NPV_LIST_LOCKS MAXCPU
189 #define PHYS_TO_PV_LIST_LOCK(pa) \
190 (&pv_list_locks[pa_index(pa) % NPV_LIST_LOCKS])
192 #define CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa) do { \
193 struct rwlock **_lockp = (lockp); \
194 struct rwlock *_new_lock; \
196 _new_lock = PHYS_TO_PV_LIST_LOCK(pa); \
197 if (_new_lock != *_lockp) { \
198 if (*_lockp != NULL) \
199 rw_wunlock(*_lockp); \
200 *_lockp = _new_lock; \
205 #define CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m) \
206 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, VM_PAGE_TO_PHYS(m))
208 #define RELEASE_PV_LIST_LOCK(lockp) do { \
209 struct rwlock **_lockp = (lockp); \
211 if (*_lockp != NULL) { \
212 rw_wunlock(*_lockp); \
217 #define VM_PAGE_TO_PV_LIST_LOCK(m) \
218 PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m))
221 * The presence of this flag indicates that the mapping is writeable.
222 * If the ATTR_AP_RO bit is also set, then the mapping is clean, otherwise it is
223 * dirty. This flag may only be set on managed mappings.
225 * The DBM bit is reserved on ARMv8.0 but it seems we can safely treat it
226 * as a software managed bit.
228 #define ATTR_SW_DBM ATTR_DBM
230 struct pmap kernel_pmap_store;
232 /* Used for mapping ACPI memory before VM is initialized */
233 #define PMAP_PREINIT_MAPPING_COUNT 32
234 #define PMAP_PREINIT_MAPPING_SIZE (PMAP_PREINIT_MAPPING_COUNT * L2_SIZE)
235 static vm_offset_t preinit_map_va; /* Start VA of pre-init mapping space */
236 static int vm_initialized = 0; /* No need to use pre-init maps when set */
239 * Reserve a few L2 blocks starting from 'preinit_map_va' pointer.
240 * Always map entire L2 block for simplicity.
241 * VA of L2 block = preinit_map_va + i * L2_SIZE
243 static struct pmap_preinit_mapping {
247 } pmap_preinit_mapping[PMAP_PREINIT_MAPPING_COUNT];
249 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
250 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
251 vm_offset_t kernel_vm_end = 0;
254 * Data for the pv entry allocation mechanism.
256 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
257 static struct mtx pv_chunks_mutex;
258 static struct rwlock pv_list_locks[NPV_LIST_LOCKS];
259 static struct md_page *pv_table;
260 static struct md_page pv_dummy;
262 vm_paddr_t dmap_phys_base; /* The start of the dmap region */
263 vm_paddr_t dmap_phys_max; /* The limit of the dmap region */
264 vm_offset_t dmap_max_addr; /* The virtual address limit of the dmap */
266 /* This code assumes all L1 DMAP entries will be used */
267 CTASSERT((DMAP_MIN_ADDRESS & ~L0_OFFSET) == DMAP_MIN_ADDRESS);
268 CTASSERT((DMAP_MAX_ADDRESS & ~L0_OFFSET) == DMAP_MAX_ADDRESS);
270 #define DMAP_TABLES ((DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS) >> L0_SHIFT)
271 extern pt_entry_t pagetable_dmap[];
273 #define PHYSMAP_SIZE (2 * (VM_PHYSSEG_MAX - 1))
274 static vm_paddr_t physmap[PHYSMAP_SIZE];
275 static u_int physmap_idx;
277 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters");
279 static int superpages_enabled = 1;
280 SYSCTL_INT(_vm_pmap, OID_AUTO, superpages_enabled,
281 CTLFLAG_RDTUN | CTLFLAG_NOFETCH, &superpages_enabled, 0,
282 "Are large page mappings enabled?");
285 * Internal flags for pmap_enter()'s helper functions.
287 #define PMAP_ENTER_NORECLAIM 0x1000000 /* Don't reclaim PV entries. */
288 #define PMAP_ENTER_NOREPLACE 0x2000000 /* Don't replace mappings. */
290 static void free_pv_chunk(struct pv_chunk *pc);
291 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
292 static pv_entry_t get_pv_entry(pmap_t pmap, struct rwlock **lockp);
293 static vm_page_t reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp);
294 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
295 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
298 static int pmap_change_attr(vm_offset_t va, vm_size_t size, int mode);
299 static int pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode);
300 static pt_entry_t *pmap_demote_l1(pmap_t pmap, pt_entry_t *l1, vm_offset_t va);
301 static pt_entry_t *pmap_demote_l2_locked(pmap_t pmap, pt_entry_t *l2,
302 vm_offset_t va, struct rwlock **lockp);
303 static pt_entry_t *pmap_demote_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t va);
304 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
305 vm_page_t m, vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp);
306 static int pmap_enter_l2(pmap_t pmap, vm_offset_t va, pd_entry_t new_l2,
307 u_int flags, vm_page_t m, struct rwlock **lockp);
308 static int pmap_remove_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t sva,
309 pd_entry_t l1e, struct spglist *free, struct rwlock **lockp);
310 static int pmap_remove_l3(pmap_t pmap, pt_entry_t *l3, vm_offset_t sva,
311 pd_entry_t l2e, struct spglist *free, struct rwlock **lockp);
312 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
313 vm_page_t m, struct rwlock **lockp);
315 static vm_page_t _pmap_alloc_l3(pmap_t pmap, vm_pindex_t ptepindex,
316 struct rwlock **lockp);
318 static void _pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m,
319 struct spglist *free);
320 static int pmap_unuse_pt(pmap_t, vm_offset_t, pd_entry_t, struct spglist *);
321 static __inline vm_page_t pmap_remove_pt_page(pmap_t pmap, vm_offset_t va);
324 * These load the old table data and store the new value.
325 * They need to be atomic as the System MMU may write to the table at
326 * the same time as the CPU.
328 #define pmap_clear(table) atomic_store_64(table, 0)
329 #define pmap_clear_bits(table, bits) atomic_clear_64(table, bits)
330 #define pmap_load(table) (*table)
331 #define pmap_load_clear(table) atomic_swap_64(table, 0)
332 #define pmap_load_store(table, entry) atomic_swap_64(table, entry)
333 #define pmap_set_bits(table, bits) atomic_set_64(table, bits)
334 #define pmap_store(table, entry) atomic_store_64(table, entry)
336 /********************/
337 /* Inline functions */
338 /********************/
341 pagecopy(void *s, void *d)
344 memcpy(d, s, PAGE_SIZE);
347 static __inline pd_entry_t *
348 pmap_l0(pmap_t pmap, vm_offset_t va)
351 return (&pmap->pm_l0[pmap_l0_index(va)]);
354 static __inline pd_entry_t *
355 pmap_l0_to_l1(pd_entry_t *l0, vm_offset_t va)
359 l1 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l0) & ~ATTR_MASK);
360 return (&l1[pmap_l1_index(va)]);
363 static __inline pd_entry_t *
364 pmap_l1(pmap_t pmap, vm_offset_t va)
368 l0 = pmap_l0(pmap, va);
369 if ((pmap_load(l0) & ATTR_DESCR_MASK) != L0_TABLE)
372 return (pmap_l0_to_l1(l0, va));
375 static __inline pd_entry_t *
376 pmap_l1_to_l2(pd_entry_t *l1, vm_offset_t va)
380 l2 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l1) & ~ATTR_MASK);
381 return (&l2[pmap_l2_index(va)]);
384 static __inline pd_entry_t *
385 pmap_l2(pmap_t pmap, vm_offset_t va)
389 l1 = pmap_l1(pmap, va);
390 if ((pmap_load(l1) & ATTR_DESCR_MASK) != L1_TABLE)
393 return (pmap_l1_to_l2(l1, va));
396 static __inline pt_entry_t *
397 pmap_l2_to_l3(pd_entry_t *l2, vm_offset_t va)
401 l3 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l2) & ~ATTR_MASK);
402 return (&l3[pmap_l3_index(va)]);
406 * Returns the lowest valid pde for a given virtual address.
407 * The next level may or may not point to a valid page or block.
409 static __inline pd_entry_t *
410 pmap_pde(pmap_t pmap, vm_offset_t va, int *level)
412 pd_entry_t *l0, *l1, *l2, desc;
414 l0 = pmap_l0(pmap, va);
415 desc = pmap_load(l0) & ATTR_DESCR_MASK;
416 if (desc != L0_TABLE) {
421 l1 = pmap_l0_to_l1(l0, va);
422 desc = pmap_load(l1) & ATTR_DESCR_MASK;
423 if (desc != L1_TABLE) {
428 l2 = pmap_l1_to_l2(l1, va);
429 desc = pmap_load(l2) & ATTR_DESCR_MASK;
430 if (desc != L2_TABLE) {
440 * Returns the lowest valid pte block or table entry for a given virtual
441 * address. If there are no valid entries return NULL and set the level to
442 * the first invalid level.
444 static __inline pt_entry_t *
445 pmap_pte(pmap_t pmap, vm_offset_t va, int *level)
447 pd_entry_t *l1, *l2, desc;
450 l1 = pmap_l1(pmap, va);
455 desc = pmap_load(l1) & ATTR_DESCR_MASK;
456 if (desc == L1_BLOCK) {
461 if (desc != L1_TABLE) {
466 l2 = pmap_l1_to_l2(l1, va);
467 desc = pmap_load(l2) & ATTR_DESCR_MASK;
468 if (desc == L2_BLOCK) {
473 if (desc != L2_TABLE) {
479 l3 = pmap_l2_to_l3(l2, va);
480 if ((pmap_load(l3) & ATTR_DESCR_MASK) != L3_PAGE)
487 pmap_ps_enabled(pmap_t pmap __unused)
490 return (superpages_enabled != 0);
494 pmap_get_tables(pmap_t pmap, vm_offset_t va, pd_entry_t **l0, pd_entry_t **l1,
495 pd_entry_t **l2, pt_entry_t **l3)
497 pd_entry_t *l0p, *l1p, *l2p;
499 if (pmap->pm_l0 == NULL)
502 l0p = pmap_l0(pmap, va);
505 if ((pmap_load(l0p) & ATTR_DESCR_MASK) != L0_TABLE)
508 l1p = pmap_l0_to_l1(l0p, va);
511 if ((pmap_load(l1p) & ATTR_DESCR_MASK) == L1_BLOCK) {
517 if ((pmap_load(l1p) & ATTR_DESCR_MASK) != L1_TABLE)
520 l2p = pmap_l1_to_l2(l1p, va);
523 if ((pmap_load(l2p) & ATTR_DESCR_MASK) == L2_BLOCK) {
528 if ((pmap_load(l2p) & ATTR_DESCR_MASK) != L2_TABLE)
531 *l3 = pmap_l2_to_l3(l2p, va);
537 pmap_l3_valid(pt_entry_t l3)
540 return ((l3 & ATTR_DESCR_MASK) == L3_PAGE);
544 CTASSERT(L1_BLOCK == L2_BLOCK);
547 * Checks if the PTE is dirty.
550 pmap_pte_dirty(pt_entry_t pte)
553 KASSERT((pte & ATTR_SW_MANAGED) != 0, ("pte %#lx is unmanaged", pte));
554 KASSERT((pte & (ATTR_AP_RW_BIT | ATTR_SW_DBM)) != 0,
555 ("pte %#lx is writeable and missing ATTR_SW_DBM", pte));
557 return ((pte & (ATTR_AP_RW_BIT | ATTR_SW_DBM)) ==
558 (ATTR_AP(ATTR_AP_RW) | ATTR_SW_DBM));
562 pmap_resident_count_inc(pmap_t pmap, int count)
565 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
566 pmap->pm_stats.resident_count += count;
570 pmap_resident_count_dec(pmap_t pmap, int count)
573 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
574 KASSERT(pmap->pm_stats.resident_count >= count,
575 ("pmap %p resident count underflow %ld %d", pmap,
576 pmap->pm_stats.resident_count, count));
577 pmap->pm_stats.resident_count -= count;
581 pmap_early_page_idx(vm_offset_t l1pt, vm_offset_t va, u_int *l1_slot,
587 l1 = (pd_entry_t *)l1pt;
588 *l1_slot = (va >> L1_SHIFT) & Ln_ADDR_MASK;
590 /* Check locore has used a table L1 map */
591 KASSERT((l1[*l1_slot] & ATTR_DESCR_MASK) == L1_TABLE,
592 ("Invalid bootstrap L1 table"));
593 /* Find the address of the L2 table */
594 l2 = (pt_entry_t *)init_pt_va;
595 *l2_slot = pmap_l2_index(va);
601 pmap_early_vtophys(vm_offset_t l1pt, vm_offset_t va)
603 u_int l1_slot, l2_slot;
606 l2 = pmap_early_page_idx(l1pt, va, &l1_slot, &l2_slot);
608 return ((l2[l2_slot] & ~ATTR_MASK) + (va & L2_OFFSET));
612 pmap_bootstrap_dmap(vm_offset_t kern_l1, vm_paddr_t min_pa,
613 vm_offset_t freemempos)
617 vm_paddr_t l2_pa, pa;
618 u_int l1_slot, l2_slot, prev_l1_slot;
621 dmap_phys_base = min_pa & ~L1_OFFSET;
627 #define DMAP_TABLES ((DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS) >> L0_SHIFT)
628 memset(pagetable_dmap, 0, PAGE_SIZE * DMAP_TABLES);
630 for (i = 0; i < (physmap_idx * 2); i += 2) {
631 pa = physmap[i] & ~L2_OFFSET;
632 va = pa - dmap_phys_base + DMAP_MIN_ADDRESS;
634 /* Create L2 mappings at the start of the region */
635 if ((pa & L1_OFFSET) != 0) {
636 l1_slot = ((va - DMAP_MIN_ADDRESS) >> L1_SHIFT);
637 if (l1_slot != prev_l1_slot) {
638 prev_l1_slot = l1_slot;
639 l2 = (pt_entry_t *)freemempos;
640 l2_pa = pmap_early_vtophys(kern_l1,
642 freemempos += PAGE_SIZE;
644 pmap_store(&pagetable_dmap[l1_slot],
645 (l2_pa & ~Ln_TABLE_MASK) | L1_TABLE);
647 memset(l2, 0, PAGE_SIZE);
650 ("pmap_bootstrap_dmap: NULL l2 map"));
651 for (; va < DMAP_MAX_ADDRESS && pa < physmap[i + 1];
652 pa += L2_SIZE, va += L2_SIZE) {
654 * We are on a boundary, stop to
655 * create a level 1 block
657 if ((pa & L1_OFFSET) == 0)
660 l2_slot = pmap_l2_index(va);
661 KASSERT(l2_slot != 0, ("..."));
662 pmap_store(&l2[l2_slot],
663 (pa & ~L2_OFFSET) | ATTR_DEFAULT | ATTR_XN |
664 ATTR_IDX(CACHED_MEMORY) | L2_BLOCK);
666 KASSERT(va == (pa - dmap_phys_base + DMAP_MIN_ADDRESS),
670 for (; va < DMAP_MAX_ADDRESS && pa < physmap[i + 1] &&
671 (physmap[i + 1] - pa) >= L1_SIZE;
672 pa += L1_SIZE, va += L1_SIZE) {
673 l1_slot = ((va - DMAP_MIN_ADDRESS) >> L1_SHIFT);
674 pmap_store(&pagetable_dmap[l1_slot],
675 (pa & ~L1_OFFSET) | ATTR_DEFAULT | ATTR_XN |
676 ATTR_IDX(CACHED_MEMORY) | L1_BLOCK);
679 /* Create L2 mappings at the end of the region */
680 if (pa < physmap[i + 1]) {
681 l1_slot = ((va - DMAP_MIN_ADDRESS) >> L1_SHIFT);
682 if (l1_slot != prev_l1_slot) {
683 prev_l1_slot = l1_slot;
684 l2 = (pt_entry_t *)freemempos;
685 l2_pa = pmap_early_vtophys(kern_l1,
687 freemempos += PAGE_SIZE;
689 pmap_store(&pagetable_dmap[l1_slot],
690 (l2_pa & ~Ln_TABLE_MASK) | L1_TABLE);
692 memset(l2, 0, PAGE_SIZE);
695 ("pmap_bootstrap_dmap: NULL l2 map"));
696 for (; va < DMAP_MAX_ADDRESS && pa < physmap[i + 1];
697 pa += L2_SIZE, va += L2_SIZE) {
698 l2_slot = pmap_l2_index(va);
699 pmap_store(&l2[l2_slot],
700 (pa & ~L2_OFFSET) | ATTR_DEFAULT | ATTR_XN |
701 ATTR_IDX(CACHED_MEMORY) | L2_BLOCK);
705 if (pa > dmap_phys_max) {
717 pmap_bootstrap_l2(vm_offset_t l1pt, vm_offset_t va, vm_offset_t l2_start)
724 KASSERT((va & L1_OFFSET) == 0, ("Invalid virtual address"));
726 l1 = (pd_entry_t *)l1pt;
727 l1_slot = pmap_l1_index(va);
730 for (; va < VM_MAX_KERNEL_ADDRESS; l1_slot++, va += L1_SIZE) {
731 KASSERT(l1_slot < Ln_ENTRIES, ("Invalid L1 index"));
733 pa = pmap_early_vtophys(l1pt, l2pt);
734 pmap_store(&l1[l1_slot],
735 (pa & ~Ln_TABLE_MASK) | L1_TABLE);
739 /* Clean the L2 page table */
740 memset((void *)l2_start, 0, l2pt - l2_start);
746 pmap_bootstrap_l3(vm_offset_t l1pt, vm_offset_t va, vm_offset_t l3_start)
753 KASSERT((va & L2_OFFSET) == 0, ("Invalid virtual address"));
755 l2 = pmap_l2(kernel_pmap, va);
756 l2 = (pd_entry_t *)rounddown2((uintptr_t)l2, PAGE_SIZE);
757 l2_slot = pmap_l2_index(va);
760 for (; va < VM_MAX_KERNEL_ADDRESS; l2_slot++, va += L2_SIZE) {
761 KASSERT(l2_slot < Ln_ENTRIES, ("Invalid L2 index"));
763 pa = pmap_early_vtophys(l1pt, l3pt);
764 pmap_store(&l2[l2_slot],
765 (pa & ~Ln_TABLE_MASK) | L2_TABLE);
769 /* Clean the L2 page table */
770 memset((void *)l3_start, 0, l3pt - l3_start);
776 * Bootstrap the system enough to run with virtual memory.
779 pmap_bootstrap(vm_offset_t l0pt, vm_offset_t l1pt, vm_paddr_t kernstart,
782 u_int l1_slot, l2_slot;
784 vm_offset_t va, freemempos;
785 vm_offset_t dpcpu, msgbufpv;
786 vm_paddr_t start_pa, pa, min_pa;
790 kern_delta = KERNBASE - kernstart;
792 printf("pmap_bootstrap %lx %lx %lx\n", l1pt, kernstart, kernlen);
793 printf("%lx\n", l1pt);
794 printf("%lx\n", (KERNBASE >> L1_SHIFT) & Ln_ADDR_MASK);
796 /* Set this early so we can use the pagetable walking functions */
797 kernel_pmap_store.pm_l0 = (pd_entry_t *)l0pt;
798 PMAP_LOCK_INIT(kernel_pmap);
800 /* Assume the address we were loaded to is a valid physical address */
801 min_pa = KERNBASE - kern_delta;
803 physmap_idx = arm_physmem_avail(physmap, nitems(physmap));
807 * Find the minimum physical address. physmap is sorted,
808 * but may contain empty ranges.
810 for (i = 0; i < (physmap_idx * 2); i += 2) {
811 if (physmap[i] == physmap[i + 1])
813 if (physmap[i] <= min_pa)
817 freemempos = KERNBASE + kernlen;
818 freemempos = roundup2(freemempos, PAGE_SIZE);
820 /* Create a direct map region early so we can use it for pa -> va */
821 freemempos = pmap_bootstrap_dmap(l1pt, min_pa, freemempos);
824 start_pa = pa = KERNBASE - kern_delta;
827 * Read the page table to find out what is already mapped.
828 * This assumes we have mapped a block of memory from KERNBASE
829 * using a single L1 entry.
831 l2 = pmap_early_page_idx(l1pt, KERNBASE, &l1_slot, &l2_slot);
833 /* Sanity check the index, KERNBASE should be the first VA */
834 KASSERT(l2_slot == 0, ("The L2 index is non-zero"));
836 /* Find how many pages we have mapped */
837 for (; l2_slot < Ln_ENTRIES; l2_slot++) {
838 if ((l2[l2_slot] & ATTR_DESCR_MASK) == 0)
841 /* Check locore used L2 blocks */
842 KASSERT((l2[l2_slot] & ATTR_DESCR_MASK) == L2_BLOCK,
843 ("Invalid bootstrap L2 table"));
844 KASSERT((l2[l2_slot] & ~ATTR_MASK) == pa,
845 ("Incorrect PA in L2 table"));
851 va = roundup2(va, L1_SIZE);
853 /* Create the l2 tables up to VM_MAX_KERNEL_ADDRESS */
854 freemempos = pmap_bootstrap_l2(l1pt, va, freemempos);
855 /* And the l3 tables for the early devmap */
856 freemempos = pmap_bootstrap_l3(l1pt,
857 VM_MAX_KERNEL_ADDRESS - (PMAP_MAPDEV_EARLY_SIZE), freemempos);
861 #define alloc_pages(var, np) \
862 (var) = freemempos; \
863 freemempos += (np * PAGE_SIZE); \
864 memset((char *)(var), 0, ((np) * PAGE_SIZE));
866 /* Allocate dynamic per-cpu area. */
867 alloc_pages(dpcpu, DPCPU_SIZE / PAGE_SIZE);
868 dpcpu_init((void *)dpcpu, 0);
870 /* Allocate memory for the msgbuf, e.g. for /sbin/dmesg */
871 alloc_pages(msgbufpv, round_page(msgbufsize) / PAGE_SIZE);
872 msgbufp = (void *)msgbufpv;
874 /* Reserve some VA space for early BIOS/ACPI mapping */
875 preinit_map_va = roundup2(freemempos, L2_SIZE);
877 virtual_avail = preinit_map_va + PMAP_PREINIT_MAPPING_SIZE;
878 virtual_avail = roundup2(virtual_avail, L1_SIZE);
879 virtual_end = VM_MAX_KERNEL_ADDRESS - (PMAP_MAPDEV_EARLY_SIZE);
880 kernel_vm_end = virtual_avail;
882 pa = pmap_early_vtophys(l1pt, freemempos);
884 arm_physmem_exclude_region(start_pa, pa - start_pa, EXFLAG_NOALLOC);
890 * Initialize a vm_page's machine-dependent fields.
893 pmap_page_init(vm_page_t m)
896 TAILQ_INIT(&m->md.pv_list);
897 m->md.pv_memattr = VM_MEMATTR_WRITE_BACK;
901 * Initialize the pmap module.
902 * Called by vm_init, to initialize any structures that the pmap
903 * system needs to map virtual memory.
912 * Are large page mappings enabled?
914 TUNABLE_INT_FETCH("vm.pmap.superpages_enabled", &superpages_enabled);
915 if (superpages_enabled) {
916 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
917 ("pmap_init: can't assign to pagesizes[1]"));
918 pagesizes[1] = L2_SIZE;
922 * Initialize the pv chunk list mutex.
924 mtx_init(&pv_chunks_mutex, "pmap pv chunk list", NULL, MTX_DEF);
927 * Initialize the pool of pv list locks.
929 for (i = 0; i < NPV_LIST_LOCKS; i++)
930 rw_init(&pv_list_locks[i], "pmap pv list");
933 * Calculate the size of the pv head table for superpages.
935 pv_npg = howmany(vm_phys_segs[vm_phys_nsegs - 1].end, L2_SIZE);
938 * Allocate memory for the pv head table for superpages.
940 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
942 pv_table = (struct md_page *)kmem_malloc(s, M_WAITOK | M_ZERO);
943 for (i = 0; i < pv_npg; i++)
944 TAILQ_INIT(&pv_table[i].pv_list);
945 TAILQ_INIT(&pv_dummy.pv_list);
950 static SYSCTL_NODE(_vm_pmap, OID_AUTO, l2, CTLFLAG_RD, 0,
951 "2MB page mapping counters");
953 static u_long pmap_l2_demotions;
954 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, demotions, CTLFLAG_RD,
955 &pmap_l2_demotions, 0, "2MB page demotions");
957 static u_long pmap_l2_mappings;
958 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, mappings, CTLFLAG_RD,
959 &pmap_l2_mappings, 0, "2MB page mappings");
961 static u_long pmap_l2_p_failures;
962 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, p_failures, CTLFLAG_RD,
963 &pmap_l2_p_failures, 0, "2MB page promotion failures");
965 static u_long pmap_l2_promotions;
966 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, promotions, CTLFLAG_RD,
967 &pmap_l2_promotions, 0, "2MB page promotions");
970 * Invalidate a single TLB entry.
973 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
979 "tlbi vaae1is, %0 \n"
982 : : "r"(va >> PAGE_SHIFT));
987 pmap_invalidate_range_nopin(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
992 for (addr = sva; addr < eva; addr += PAGE_SIZE) {
994 "tlbi vaae1is, %0" : : "r"(addr >> PAGE_SHIFT));
1001 static __inline void
1002 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1006 pmap_invalidate_range_nopin(pmap, sva, eva);
1010 static __inline void
1011 pmap_invalidate_all(pmap_t pmap)
1024 * Routine: pmap_extract
1026 * Extract the physical page address associated
1027 * with the given map/virtual_address pair.
1030 pmap_extract(pmap_t pmap, vm_offset_t va)
1032 pt_entry_t *pte, tpte;
1039 * Find the block or page map for this virtual address. pmap_pte
1040 * will return either a valid block/page entry, or NULL.
1042 pte = pmap_pte(pmap, va, &lvl);
1044 tpte = pmap_load(pte);
1045 pa = tpte & ~ATTR_MASK;
1048 KASSERT((tpte & ATTR_DESCR_MASK) == L1_BLOCK,
1049 ("pmap_extract: Invalid L1 pte found: %lx",
1050 tpte & ATTR_DESCR_MASK));
1051 pa |= (va & L1_OFFSET);
1054 KASSERT((tpte & ATTR_DESCR_MASK) == L2_BLOCK,
1055 ("pmap_extract: Invalid L2 pte found: %lx",
1056 tpte & ATTR_DESCR_MASK));
1057 pa |= (va & L2_OFFSET);
1060 KASSERT((tpte & ATTR_DESCR_MASK) == L3_PAGE,
1061 ("pmap_extract: Invalid L3 pte found: %lx",
1062 tpte & ATTR_DESCR_MASK));
1063 pa |= (va & L3_OFFSET);
1072 * Routine: pmap_extract_and_hold
1074 * Atomically extract and hold the physical page
1075 * with the given pmap and virtual address pair
1076 * if that mapping permits the given protection.
1079 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1081 pt_entry_t *pte, tpte;
1091 pte = pmap_pte(pmap, va, &lvl);
1093 tpte = pmap_load(pte);
1095 KASSERT(lvl > 0 && lvl <= 3,
1096 ("pmap_extract_and_hold: Invalid level %d", lvl));
1097 CTASSERT(L1_BLOCK == L2_BLOCK);
1098 KASSERT((lvl == 3 && (tpte & ATTR_DESCR_MASK) == L3_PAGE) ||
1099 (lvl < 3 && (tpte & ATTR_DESCR_MASK) == L1_BLOCK),
1100 ("pmap_extract_and_hold: Invalid pte at L%d: %lx", lvl,
1101 tpte & ATTR_DESCR_MASK));
1102 if (((tpte & ATTR_AP_RW_BIT) == ATTR_AP(ATTR_AP_RW)) ||
1103 ((prot & VM_PROT_WRITE) == 0)) {
1106 off = va & L1_OFFSET;
1109 off = va & L2_OFFSET;
1115 if (vm_page_pa_tryrelock(pmap,
1116 (tpte & ~ATTR_MASK) | off, &pa))
1118 m = PHYS_TO_VM_PAGE((tpte & ~ATTR_MASK) | off);
1128 pmap_kextract(vm_offset_t va)
1130 pt_entry_t *pte, tpte;
1134 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS) {
1135 pa = DMAP_TO_PHYS(va);
1138 pte = pmap_pte(kernel_pmap, va, &lvl);
1140 tpte = pmap_load(pte);
1141 pa = tpte & ~ATTR_MASK;
1144 KASSERT((tpte & ATTR_DESCR_MASK) == L1_BLOCK,
1145 ("pmap_kextract: Invalid L1 pte found: %lx",
1146 tpte & ATTR_DESCR_MASK));
1147 pa |= (va & L1_OFFSET);
1150 KASSERT((tpte & ATTR_DESCR_MASK) == L2_BLOCK,
1151 ("pmap_kextract: Invalid L2 pte found: %lx",
1152 tpte & ATTR_DESCR_MASK));
1153 pa |= (va & L2_OFFSET);
1156 KASSERT((tpte & ATTR_DESCR_MASK) == L3_PAGE,
1157 ("pmap_kextract: Invalid L3 pte found: %lx",
1158 tpte & ATTR_DESCR_MASK));
1159 pa |= (va & L3_OFFSET);
1167 /***************************************************
1168 * Low level mapping routines.....
1169 ***************************************************/
1172 pmap_kenter(vm_offset_t sva, vm_size_t size, vm_paddr_t pa, int mode)
1175 pt_entry_t *pte, attr;
1179 KASSERT((pa & L3_OFFSET) == 0,
1180 ("pmap_kenter: Invalid physical address"));
1181 KASSERT((sva & L3_OFFSET) == 0,
1182 ("pmap_kenter: Invalid virtual address"));
1183 KASSERT((size & PAGE_MASK) == 0,
1184 ("pmap_kenter: Mapping is not page-sized"));
1186 attr = ATTR_DEFAULT | ATTR_IDX(mode) | L3_PAGE;
1187 if (mode == DEVICE_MEMORY)
1192 pde = pmap_pde(kernel_pmap, va, &lvl);
1193 KASSERT(pde != NULL,
1194 ("pmap_kenter: Invalid page entry, va: 0x%lx", va));
1195 KASSERT(lvl == 2, ("pmap_kenter: Invalid level %d", lvl));
1197 pte = pmap_l2_to_l3(pde, va);
1198 pmap_load_store(pte, (pa & ~L3_OFFSET) | attr);
1204 pmap_invalidate_range(kernel_pmap, sva, va);
1208 pmap_kenter_device(vm_offset_t sva, vm_size_t size, vm_paddr_t pa)
1211 pmap_kenter(sva, size, pa, DEVICE_MEMORY);
1215 * Remove a page from the kernel pagetables.
1218 pmap_kremove(vm_offset_t va)
1223 pte = pmap_pte(kernel_pmap, va, &lvl);
1224 KASSERT(pte != NULL, ("pmap_kremove: Invalid address"));
1225 KASSERT(lvl == 3, ("pmap_kremove: Invalid pte level %d", lvl));
1228 pmap_invalidate_page(kernel_pmap, va);
1232 pmap_kremove_device(vm_offset_t sva, vm_size_t size)
1238 KASSERT((sva & L3_OFFSET) == 0,
1239 ("pmap_kremove_device: Invalid virtual address"));
1240 KASSERT((size & PAGE_MASK) == 0,
1241 ("pmap_kremove_device: Mapping is not page-sized"));
1245 pte = pmap_pte(kernel_pmap, va, &lvl);
1246 KASSERT(pte != NULL, ("Invalid page table, va: 0x%lx", va));
1248 ("Invalid device pagetable level: %d != 3", lvl));
1254 pmap_invalidate_range(kernel_pmap, sva, va);
1258 * Used to map a range of physical addresses into kernel
1259 * virtual address space.
1261 * The value passed in '*virt' is a suggested virtual address for
1262 * the mapping. Architectures which can support a direct-mapped
1263 * physical to virtual region can return the appropriate address
1264 * within that region, leaving '*virt' unchanged. Other
1265 * architectures should map the pages starting at '*virt' and
1266 * update '*virt' with the first usable address after the mapped
1270 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
1272 return PHYS_TO_DMAP(start);
1277 * Add a list of wired pages to the kva
1278 * this routine is only used for temporary
1279 * kernel mappings that do not need to have
1280 * page modification or references recorded.
1281 * Note that old mappings are simply written
1282 * over. The page *must* be wired.
1283 * Note: SMP coherent. Uses a ranged shootdown IPI.
1286 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
1289 pt_entry_t *pte, pa;
1295 for (i = 0; i < count; i++) {
1296 pde = pmap_pde(kernel_pmap, va, &lvl);
1297 KASSERT(pde != NULL,
1298 ("pmap_qenter: Invalid page entry, va: 0x%lx", va));
1300 ("pmap_qenter: Invalid level %d", lvl));
1303 pa = VM_PAGE_TO_PHYS(m) | ATTR_DEFAULT | ATTR_AP(ATTR_AP_RW) |
1304 ATTR_IDX(m->md.pv_memattr) | L3_PAGE;
1305 if (m->md.pv_memattr == DEVICE_MEMORY)
1307 pte = pmap_l2_to_l3(pde, va);
1308 pmap_load_store(pte, pa);
1312 pmap_invalidate_range(kernel_pmap, sva, va);
1316 * This routine tears out page mappings from the
1317 * kernel -- it is meant only for temporary mappings.
1320 pmap_qremove(vm_offset_t sva, int count)
1326 KASSERT(sva >= VM_MIN_KERNEL_ADDRESS, ("usermode va %lx", sva));
1329 while (count-- > 0) {
1330 pte = pmap_pte(kernel_pmap, va, &lvl);
1332 ("Invalid device pagetable level: %d != 3", lvl));
1339 pmap_invalidate_range(kernel_pmap, sva, va);
1342 /***************************************************
1343 * Page table page management routines.....
1344 ***************************************************/
1346 * Schedule the specified unused page table page to be freed. Specifically,
1347 * add the page to the specified list of pages that will be released to the
1348 * physical memory manager after the TLB has been updated.
1350 static __inline void
1351 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
1352 boolean_t set_PG_ZERO)
1356 m->flags |= PG_ZERO;
1358 m->flags &= ~PG_ZERO;
1359 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
1363 * Decrements a page table page's wire count, which is used to record the
1364 * number of valid page table entries within the page. If the wire count
1365 * drops to zero, then the page table page is unmapped. Returns TRUE if the
1366 * page table page was unmapped and FALSE otherwise.
1368 static inline boolean_t
1369 pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
1373 if (m->wire_count == 0) {
1374 _pmap_unwire_l3(pmap, va, m, free);
1381 _pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
1384 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1386 * unmap the page table page
1388 if (m->pindex >= (NUL2E + NUL1E)) {
1392 l0 = pmap_l0(pmap, va);
1394 } else if (m->pindex >= NUL2E) {
1398 l1 = pmap_l1(pmap, va);
1404 l2 = pmap_l2(pmap, va);
1407 pmap_resident_count_dec(pmap, 1);
1408 if (m->pindex < NUL2E) {
1409 /* We just released an l3, unhold the matching l2 */
1410 pd_entry_t *l1, tl1;
1413 l1 = pmap_l1(pmap, va);
1414 tl1 = pmap_load(l1);
1415 l2pg = PHYS_TO_VM_PAGE(tl1 & ~ATTR_MASK);
1416 pmap_unwire_l3(pmap, va, l2pg, free);
1417 } else if (m->pindex < (NUL2E + NUL1E)) {
1418 /* We just released an l2, unhold the matching l1 */
1419 pd_entry_t *l0, tl0;
1422 l0 = pmap_l0(pmap, va);
1423 tl0 = pmap_load(l0);
1424 l1pg = PHYS_TO_VM_PAGE(tl0 & ~ATTR_MASK);
1425 pmap_unwire_l3(pmap, va, l1pg, free);
1427 pmap_invalidate_page(pmap, va);
1430 * Put page on a list so that it is released after
1431 * *ALL* TLB shootdown is done
1433 pmap_add_delayed_free_list(m, free, TRUE);
1437 * After removing a page table entry, this routine is used to
1438 * conditionally free the page, and manage the hold/wire counts.
1441 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, pd_entry_t ptepde,
1442 struct spglist *free)
1446 if (va >= VM_MAXUSER_ADDRESS)
1448 KASSERT(ptepde != 0, ("pmap_unuse_pt: ptepde != 0"));
1449 mpte = PHYS_TO_VM_PAGE(ptepde & ~ATTR_MASK);
1450 return (pmap_unwire_l3(pmap, va, mpte, free));
1454 pmap_pinit0(pmap_t pmap)
1457 PMAP_LOCK_INIT(pmap);
1458 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats));
1459 pmap->pm_l0 = kernel_pmap->pm_l0;
1460 pmap->pm_root.rt_root = 0;
1464 pmap_pinit(pmap_t pmap)
1470 * allocate the l0 page
1472 while ((l0pt = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
1473 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL)
1476 l0phys = VM_PAGE_TO_PHYS(l0pt);
1477 pmap->pm_l0 = (pd_entry_t *)PHYS_TO_DMAP(l0phys);
1479 if ((l0pt->flags & PG_ZERO) == 0)
1480 pagezero(pmap->pm_l0);
1482 pmap->pm_root.rt_root = 0;
1483 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats));
1489 * This routine is called if the desired page table page does not exist.
1491 * If page table page allocation fails, this routine may sleep before
1492 * returning NULL. It sleeps only if a lock pointer was given.
1494 * Note: If a page allocation fails at page table level two or three,
1495 * one or two pages may be held during the wait, only to be released
1496 * afterwards. This conservative approach is easily argued to avoid
1500 _pmap_alloc_l3(pmap_t pmap, vm_pindex_t ptepindex, struct rwlock **lockp)
1502 vm_page_t m, l1pg, l2pg;
1504 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1507 * Allocate a page table page.
1509 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
1510 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
1511 if (lockp != NULL) {
1512 RELEASE_PV_LIST_LOCK(lockp);
1519 * Indicate the need to retry. While waiting, the page table
1520 * page may have been allocated.
1524 if ((m->flags & PG_ZERO) == 0)
1528 * Map the pagetable page into the process address space, if
1529 * it isn't already there.
1532 if (ptepindex >= (NUL2E + NUL1E)) {
1534 vm_pindex_t l0index;
1536 l0index = ptepindex - (NUL2E + NUL1E);
1537 l0 = &pmap->pm_l0[l0index];
1538 pmap_store(l0, VM_PAGE_TO_PHYS(m) | L0_TABLE);
1539 } else if (ptepindex >= NUL2E) {
1540 vm_pindex_t l0index, l1index;
1541 pd_entry_t *l0, *l1;
1544 l1index = ptepindex - NUL2E;
1545 l0index = l1index >> L0_ENTRIES_SHIFT;
1547 l0 = &pmap->pm_l0[l0index];
1548 tl0 = pmap_load(l0);
1550 /* recurse for allocating page dir */
1551 if (_pmap_alloc_l3(pmap, NUL2E + NUL1E + l0index,
1553 vm_page_unwire_noq(m);
1554 vm_page_free_zero(m);
1558 l1pg = PHYS_TO_VM_PAGE(tl0 & ~ATTR_MASK);
1562 l1 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l0) & ~ATTR_MASK);
1563 l1 = &l1[ptepindex & Ln_ADDR_MASK];
1564 pmap_store(l1, VM_PAGE_TO_PHYS(m) | L1_TABLE);
1566 vm_pindex_t l0index, l1index;
1567 pd_entry_t *l0, *l1, *l2;
1568 pd_entry_t tl0, tl1;
1570 l1index = ptepindex >> Ln_ENTRIES_SHIFT;
1571 l0index = l1index >> L0_ENTRIES_SHIFT;
1573 l0 = &pmap->pm_l0[l0index];
1574 tl0 = pmap_load(l0);
1576 /* recurse for allocating page dir */
1577 if (_pmap_alloc_l3(pmap, NUL2E + l1index,
1579 vm_page_unwire_noq(m);
1580 vm_page_free_zero(m);
1583 tl0 = pmap_load(l0);
1584 l1 = (pd_entry_t *)PHYS_TO_DMAP(tl0 & ~ATTR_MASK);
1585 l1 = &l1[l1index & Ln_ADDR_MASK];
1587 l1 = (pd_entry_t *)PHYS_TO_DMAP(tl0 & ~ATTR_MASK);
1588 l1 = &l1[l1index & Ln_ADDR_MASK];
1589 tl1 = pmap_load(l1);
1591 /* recurse for allocating page dir */
1592 if (_pmap_alloc_l3(pmap, NUL2E + l1index,
1594 vm_page_unwire_noq(m);
1595 vm_page_free_zero(m);
1599 l2pg = PHYS_TO_VM_PAGE(tl1 & ~ATTR_MASK);
1604 l2 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l1) & ~ATTR_MASK);
1605 l2 = &l2[ptepindex & Ln_ADDR_MASK];
1606 pmap_store(l2, VM_PAGE_TO_PHYS(m) | L2_TABLE);
1609 pmap_resident_count_inc(pmap, 1);
1615 pmap_alloc_l2(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
1619 vm_pindex_t l2pindex;
1622 l1 = pmap_l1(pmap, va);
1623 if (l1 != NULL && (pmap_load(l1) & ATTR_DESCR_MASK) == L1_TABLE) {
1624 /* Add a reference to the L2 page. */
1625 l2pg = PHYS_TO_VM_PAGE(pmap_load(l1) & ~ATTR_MASK);
1628 /* Allocate a L2 page. */
1629 l2pindex = pmap_l2_pindex(va) >> Ln_ENTRIES_SHIFT;
1630 l2pg = _pmap_alloc_l3(pmap, NUL2E + l2pindex, lockp);
1631 if (l2pg == NULL && lockp != NULL)
1638 pmap_alloc_l3(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
1640 vm_pindex_t ptepindex;
1641 pd_entry_t *pde, tpde;
1649 * Calculate pagetable page index
1651 ptepindex = pmap_l2_pindex(va);
1654 * Get the page directory entry
1656 pde = pmap_pde(pmap, va, &lvl);
1659 * If the page table page is mapped, we just increment the hold count,
1660 * and activate it. If we get a level 2 pde it will point to a level 3
1668 pte = pmap_l0_to_l1(pde, va);
1669 KASSERT(pmap_load(pte) == 0,
1670 ("pmap_alloc_l3: TODO: l0 superpages"));
1675 pte = pmap_l1_to_l2(pde, va);
1676 KASSERT(pmap_load(pte) == 0,
1677 ("pmap_alloc_l3: TODO: l1 superpages"));
1681 tpde = pmap_load(pde);
1683 m = PHYS_TO_VM_PAGE(tpde & ~ATTR_MASK);
1689 panic("pmap_alloc_l3: Invalid level %d", lvl);
1693 * Here if the pte page isn't mapped, or if it has been deallocated.
1695 m = _pmap_alloc_l3(pmap, ptepindex, lockp);
1696 if (m == NULL && lockp != NULL)
1702 /***************************************************
1703 * Pmap allocation/deallocation routines.
1704 ***************************************************/
1707 * Release any resources held by the given physical map.
1708 * Called when a pmap initialized by pmap_pinit is being released.
1709 * Should only be called if the map contains no valid mappings.
1712 pmap_release(pmap_t pmap)
1716 KASSERT(pmap->pm_stats.resident_count == 0,
1717 ("pmap_release: pmap resident count %ld != 0",
1718 pmap->pm_stats.resident_count));
1719 KASSERT(vm_radix_is_empty(&pmap->pm_root),
1720 ("pmap_release: pmap has reserved page table page(s)"));
1722 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pmap->pm_l0));
1724 vm_page_unwire_noq(m);
1725 vm_page_free_zero(m);
1729 kvm_size(SYSCTL_HANDLER_ARGS)
1731 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS;
1733 return sysctl_handle_long(oidp, &ksize, 0, req);
1735 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD,
1736 0, 0, kvm_size, "LU", "Size of KVM");
1739 kvm_free(SYSCTL_HANDLER_ARGS)
1741 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
1743 return sysctl_handle_long(oidp, &kfree, 0, req);
1745 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD,
1746 0, 0, kvm_free, "LU", "Amount of KVM free");
1749 * grow the number of kernel page table entries, if needed
1752 pmap_growkernel(vm_offset_t addr)
1756 pd_entry_t *l0, *l1, *l2;
1758 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
1760 addr = roundup2(addr, L2_SIZE);
1761 if (addr - 1 >= vm_map_max(kernel_map))
1762 addr = vm_map_max(kernel_map);
1763 while (kernel_vm_end < addr) {
1764 l0 = pmap_l0(kernel_pmap, kernel_vm_end);
1765 KASSERT(pmap_load(l0) != 0,
1766 ("pmap_growkernel: No level 0 kernel entry"));
1768 l1 = pmap_l0_to_l1(l0, kernel_vm_end);
1769 if (pmap_load(l1) == 0) {
1770 /* We need a new PDP entry */
1771 nkpg = vm_page_alloc(NULL, kernel_vm_end >> L1_SHIFT,
1772 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ |
1773 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
1775 panic("pmap_growkernel: no memory to grow kernel");
1776 if ((nkpg->flags & PG_ZERO) == 0)
1777 pmap_zero_page(nkpg);
1778 paddr = VM_PAGE_TO_PHYS(nkpg);
1779 pmap_store(l1, paddr | L1_TABLE);
1780 continue; /* try again */
1782 l2 = pmap_l1_to_l2(l1, kernel_vm_end);
1783 if ((pmap_load(l2) & ATTR_AF) != 0) {
1784 kernel_vm_end = (kernel_vm_end + L2_SIZE) & ~L2_OFFSET;
1785 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
1786 kernel_vm_end = vm_map_max(kernel_map);
1792 nkpg = vm_page_alloc(NULL, kernel_vm_end >> L2_SHIFT,
1793 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
1796 panic("pmap_growkernel: no memory to grow kernel");
1797 if ((nkpg->flags & PG_ZERO) == 0)
1798 pmap_zero_page(nkpg);
1799 paddr = VM_PAGE_TO_PHYS(nkpg);
1800 pmap_load_store(l2, paddr | L2_TABLE);
1801 pmap_invalidate_page(kernel_pmap, kernel_vm_end);
1803 kernel_vm_end = (kernel_vm_end + L2_SIZE) & ~L2_OFFSET;
1804 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
1805 kernel_vm_end = vm_map_max(kernel_map);
1812 /***************************************************
1813 * page management routines.
1814 ***************************************************/
1816 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
1817 CTASSERT(_NPCM == 3);
1818 CTASSERT(_NPCPV == 168);
1820 static __inline struct pv_chunk *
1821 pv_to_chunk(pv_entry_t pv)
1824 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
1827 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
1829 #define PC_FREE0 0xfffffffffffffffful
1830 #define PC_FREE1 0xfffffffffffffffful
1831 #define PC_FREE2 0x000000fffffffffful
1833 static const uint64_t pc_freemask[_NPCM] = { PC_FREE0, PC_FREE1, PC_FREE2 };
1837 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
1839 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
1840 "Current number of pv entry chunks");
1841 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
1842 "Current number of pv entry chunks allocated");
1843 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
1844 "Current number of pv entry chunks frees");
1845 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
1846 "Number of times tried to get a chunk page but failed.");
1848 static long pv_entry_frees, pv_entry_allocs, pv_entry_count;
1849 static int pv_entry_spare;
1851 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
1852 "Current number of pv entry frees");
1853 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
1854 "Current number of pv entry allocs");
1855 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
1856 "Current number of pv entries");
1857 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
1858 "Current number of spare pv entries");
1863 * We are in a serious low memory condition. Resort to
1864 * drastic measures to free some pages so we can allocate
1865 * another pv entry chunk.
1867 * Returns NULL if PV entries were reclaimed from the specified pmap.
1869 * We do not, however, unmap 2mpages because subsequent accesses will
1870 * allocate per-page pv entries until repromotion occurs, thereby
1871 * exacerbating the shortage of free pv entries.
1874 reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp)
1876 struct pv_chunk *pc, *pc_marker, *pc_marker_end;
1877 struct pv_chunk_header pc_marker_b, pc_marker_end_b;
1878 struct md_page *pvh;
1880 pmap_t next_pmap, pmap;
1881 pt_entry_t *pte, tpte;
1885 struct spglist free;
1887 int bit, field, freed, lvl;
1888 static int active_reclaims = 0;
1890 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
1891 KASSERT(lockp != NULL, ("reclaim_pv_chunk: lockp is NULL"));
1896 bzero(&pc_marker_b, sizeof(pc_marker_b));
1897 bzero(&pc_marker_end_b, sizeof(pc_marker_end_b));
1898 pc_marker = (struct pv_chunk *)&pc_marker_b;
1899 pc_marker_end = (struct pv_chunk *)&pc_marker_end_b;
1901 mtx_lock(&pv_chunks_mutex);
1903 TAILQ_INSERT_HEAD(&pv_chunks, pc_marker, pc_lru);
1904 TAILQ_INSERT_TAIL(&pv_chunks, pc_marker_end, pc_lru);
1905 while ((pc = TAILQ_NEXT(pc_marker, pc_lru)) != pc_marker_end &&
1906 SLIST_EMPTY(&free)) {
1907 next_pmap = pc->pc_pmap;
1908 if (next_pmap == NULL) {
1910 * The next chunk is a marker. However, it is
1911 * not our marker, so active_reclaims must be
1912 * > 1. Consequently, the next_chunk code
1913 * will not rotate the pv_chunks list.
1917 mtx_unlock(&pv_chunks_mutex);
1920 * A pv_chunk can only be removed from the pc_lru list
1921 * when both pv_chunks_mutex is owned and the
1922 * corresponding pmap is locked.
1924 if (pmap != next_pmap) {
1925 if (pmap != NULL && pmap != locked_pmap)
1928 /* Avoid deadlock and lock recursion. */
1929 if (pmap > locked_pmap) {
1930 RELEASE_PV_LIST_LOCK(lockp);
1932 mtx_lock(&pv_chunks_mutex);
1934 } else if (pmap != locked_pmap) {
1935 if (PMAP_TRYLOCK(pmap)) {
1936 mtx_lock(&pv_chunks_mutex);
1939 pmap = NULL; /* pmap is not locked */
1940 mtx_lock(&pv_chunks_mutex);
1941 pc = TAILQ_NEXT(pc_marker, pc_lru);
1943 pc->pc_pmap != next_pmap)
1951 * Destroy every non-wired, 4 KB page mapping in the chunk.
1954 for (field = 0; field < _NPCM; field++) {
1955 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
1956 inuse != 0; inuse &= ~(1UL << bit)) {
1957 bit = ffsl(inuse) - 1;
1958 pv = &pc->pc_pventry[field * 64 + bit];
1960 pde = pmap_pde(pmap, va, &lvl);
1963 pte = pmap_l2_to_l3(pde, va);
1964 tpte = pmap_load(pte);
1965 if ((tpte & ATTR_SW_WIRED) != 0)
1967 tpte = pmap_load_clear(pte);
1968 pmap_invalidate_page(pmap, va);
1969 m = PHYS_TO_VM_PAGE(tpte & ~ATTR_MASK);
1970 if (pmap_pte_dirty(tpte))
1972 if ((tpte & ATTR_AF) != 0)
1973 vm_page_aflag_set(m, PGA_REFERENCED);
1974 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
1975 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
1977 if (TAILQ_EMPTY(&m->md.pv_list) &&
1978 (m->flags & PG_FICTITIOUS) == 0) {
1979 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
1980 if (TAILQ_EMPTY(&pvh->pv_list)) {
1981 vm_page_aflag_clear(m,
1985 pc->pc_map[field] |= 1UL << bit;
1986 pmap_unuse_pt(pmap, va, pmap_load(pde), &free);
1991 mtx_lock(&pv_chunks_mutex);
1994 /* Every freed mapping is for a 4 KB page. */
1995 pmap_resident_count_dec(pmap, freed);
1996 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
1997 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
1998 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
1999 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2000 if (pc->pc_map[0] == PC_FREE0 && pc->pc_map[1] == PC_FREE1 &&
2001 pc->pc_map[2] == PC_FREE2) {
2002 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
2003 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
2004 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
2005 /* Entire chunk is free; return it. */
2006 m_pc = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
2007 dump_drop_page(m_pc->phys_addr);
2008 mtx_lock(&pv_chunks_mutex);
2009 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2012 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2013 mtx_lock(&pv_chunks_mutex);
2014 /* One freed pv entry in locked_pmap is sufficient. */
2015 if (pmap == locked_pmap)
2019 TAILQ_REMOVE(&pv_chunks, pc_marker, pc_lru);
2020 TAILQ_INSERT_AFTER(&pv_chunks, pc, pc_marker, pc_lru);
2021 if (active_reclaims == 1 && pmap != NULL) {
2023 * Rotate the pv chunks list so that we do not
2024 * scan the same pv chunks that could not be
2025 * freed (because they contained a wired
2026 * and/or superpage mapping) on every
2027 * invocation of reclaim_pv_chunk().
2029 while ((pc = TAILQ_FIRST(&pv_chunks)) != pc_marker) {
2030 MPASS(pc->pc_pmap != NULL);
2031 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2032 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
2036 TAILQ_REMOVE(&pv_chunks, pc_marker, pc_lru);
2037 TAILQ_REMOVE(&pv_chunks, pc_marker_end, pc_lru);
2039 mtx_unlock(&pv_chunks_mutex);
2040 if (pmap != NULL && pmap != locked_pmap)
2042 if (m_pc == NULL && !SLIST_EMPTY(&free)) {
2043 m_pc = SLIST_FIRST(&free);
2044 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
2045 /* Recycle a freed page table page. */
2046 m_pc->wire_count = 1;
2048 vm_page_free_pages_toq(&free, true);
2053 * free the pv_entry back to the free list
2056 free_pv_entry(pmap_t pmap, pv_entry_t pv)
2058 struct pv_chunk *pc;
2059 int idx, field, bit;
2061 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2062 PV_STAT(atomic_add_long(&pv_entry_frees, 1));
2063 PV_STAT(atomic_add_int(&pv_entry_spare, 1));
2064 PV_STAT(atomic_subtract_long(&pv_entry_count, 1));
2065 pc = pv_to_chunk(pv);
2066 idx = pv - &pc->pc_pventry[0];
2069 pc->pc_map[field] |= 1ul << bit;
2070 if (pc->pc_map[0] != PC_FREE0 || pc->pc_map[1] != PC_FREE1 ||
2071 pc->pc_map[2] != PC_FREE2) {
2072 /* 98% of the time, pc is already at the head of the list. */
2073 if (__predict_false(pc != TAILQ_FIRST(&pmap->pm_pvchunk))) {
2074 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2075 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2079 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2084 free_pv_chunk(struct pv_chunk *pc)
2088 mtx_lock(&pv_chunks_mutex);
2089 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2090 mtx_unlock(&pv_chunks_mutex);
2091 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
2092 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
2093 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
2094 /* entire chunk is free, return it */
2095 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
2096 dump_drop_page(m->phys_addr);
2097 vm_page_unwire_noq(m);
2102 * Returns a new PV entry, allocating a new PV chunk from the system when
2103 * needed. If this PV chunk allocation fails and a PV list lock pointer was
2104 * given, a PV chunk is reclaimed from an arbitrary pmap. Otherwise, NULL is
2107 * The given PV list lock may be released.
2110 get_pv_entry(pmap_t pmap, struct rwlock **lockp)
2114 struct pv_chunk *pc;
2117 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2118 PV_STAT(atomic_add_long(&pv_entry_allocs, 1));
2120 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2122 for (field = 0; field < _NPCM; field++) {
2123 if (pc->pc_map[field]) {
2124 bit = ffsl(pc->pc_map[field]) - 1;
2128 if (field < _NPCM) {
2129 pv = &pc->pc_pventry[field * 64 + bit];
2130 pc->pc_map[field] &= ~(1ul << bit);
2131 /* If this was the last item, move it to tail */
2132 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 &&
2133 pc->pc_map[2] == 0) {
2134 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2135 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc,
2138 PV_STAT(atomic_add_long(&pv_entry_count, 1));
2139 PV_STAT(atomic_subtract_int(&pv_entry_spare, 1));
2143 /* No free items, allocate another chunk */
2144 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
2147 if (lockp == NULL) {
2148 PV_STAT(pc_chunk_tryfail++);
2151 m = reclaim_pv_chunk(pmap, lockp);
2155 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
2156 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
2157 dump_add_page(m->phys_addr);
2158 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
2160 pc->pc_map[0] = PC_FREE0 & ~1ul; /* preallocated bit 0 */
2161 pc->pc_map[1] = PC_FREE1;
2162 pc->pc_map[2] = PC_FREE2;
2163 mtx_lock(&pv_chunks_mutex);
2164 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
2165 mtx_unlock(&pv_chunks_mutex);
2166 pv = &pc->pc_pventry[0];
2167 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2168 PV_STAT(atomic_add_long(&pv_entry_count, 1));
2169 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV - 1));
2174 * Ensure that the number of spare PV entries in the specified pmap meets or
2175 * exceeds the given count, "needed".
2177 * The given PV list lock may be released.
2180 reserve_pv_entries(pmap_t pmap, int needed, struct rwlock **lockp)
2182 struct pch new_tail;
2183 struct pv_chunk *pc;
2188 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2189 KASSERT(lockp != NULL, ("reserve_pv_entries: lockp is NULL"));
2192 * Newly allocated PV chunks must be stored in a private list until
2193 * the required number of PV chunks have been allocated. Otherwise,
2194 * reclaim_pv_chunk() could recycle one of these chunks. In
2195 * contrast, these chunks must be added to the pmap upon allocation.
2197 TAILQ_INIT(&new_tail);
2200 TAILQ_FOREACH(pc, &pmap->pm_pvchunk, pc_list) {
2201 bit_count((bitstr_t *)pc->pc_map, 0,
2202 sizeof(pc->pc_map) * NBBY, &free);
2206 if (avail >= needed)
2209 for (reclaimed = false; avail < needed; avail += _NPCPV) {
2210 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
2213 m = reclaim_pv_chunk(pmap, lockp);
2218 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
2219 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
2220 dump_add_page(m->phys_addr);
2221 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
2223 pc->pc_map[0] = PC_FREE0;
2224 pc->pc_map[1] = PC_FREE1;
2225 pc->pc_map[2] = PC_FREE2;
2226 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2227 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
2228 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV));
2231 * The reclaim might have freed a chunk from the current pmap.
2232 * If that chunk contained available entries, we need to
2233 * re-count the number of available entries.
2238 if (!TAILQ_EMPTY(&new_tail)) {
2239 mtx_lock(&pv_chunks_mutex);
2240 TAILQ_CONCAT(&pv_chunks, &new_tail, pc_lru);
2241 mtx_unlock(&pv_chunks_mutex);
2246 * First find and then remove the pv entry for the specified pmap and virtual
2247 * address from the specified pv list. Returns the pv entry if found and NULL
2248 * otherwise. This operation can be performed on pv lists for either 4KB or
2249 * 2MB page mappings.
2251 static __inline pv_entry_t
2252 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2256 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
2257 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
2258 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
2267 * After demotion from a 2MB page mapping to 512 4KB page mappings,
2268 * destroy the pv entry for the 2MB page mapping and reinstantiate the pv
2269 * entries for each of the 4KB page mappings.
2272 pmap_pv_demote_l2(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
2273 struct rwlock **lockp)
2275 struct md_page *pvh;
2276 struct pv_chunk *pc;
2278 vm_offset_t va_last;
2282 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2283 KASSERT((va & L2_OFFSET) == 0,
2284 ("pmap_pv_demote_l2: va is not 2mpage aligned"));
2285 KASSERT((pa & L2_OFFSET) == 0,
2286 ("pmap_pv_demote_l2: pa is not 2mpage aligned"));
2287 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
2290 * Transfer the 2mpage's pv entry for this mapping to the first
2291 * page's pv list. Once this transfer begins, the pv list lock
2292 * must not be released until the last pv entry is reinstantiated.
2294 pvh = pa_to_pvh(pa);
2295 pv = pmap_pvh_remove(pvh, pmap, va);
2296 KASSERT(pv != NULL, ("pmap_pv_demote_l2: pv not found"));
2297 m = PHYS_TO_VM_PAGE(pa);
2298 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2300 /* Instantiate the remaining Ln_ENTRIES - 1 pv entries. */
2301 PV_STAT(atomic_add_long(&pv_entry_allocs, Ln_ENTRIES - 1));
2302 va_last = va + L2_SIZE - PAGE_SIZE;
2304 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2305 KASSERT(pc->pc_map[0] != 0 || pc->pc_map[1] != 0 ||
2306 pc->pc_map[2] != 0, ("pmap_pv_demote_l2: missing spare"));
2307 for (field = 0; field < _NPCM; field++) {
2308 while (pc->pc_map[field]) {
2309 bit = ffsl(pc->pc_map[field]) - 1;
2310 pc->pc_map[field] &= ~(1ul << bit);
2311 pv = &pc->pc_pventry[field * 64 + bit];
2315 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2316 ("pmap_pv_demote_l2: page %p is not managed", m));
2317 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2323 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2324 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2327 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 && pc->pc_map[2] == 0) {
2328 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2329 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2331 PV_STAT(atomic_add_long(&pv_entry_count, Ln_ENTRIES - 1));
2332 PV_STAT(atomic_subtract_int(&pv_entry_spare, Ln_ENTRIES - 1));
2336 * First find and then destroy the pv entry for the specified pmap and virtual
2337 * address. This operation can be performed on pv lists for either 4KB or 2MB
2341 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2345 pv = pmap_pvh_remove(pvh, pmap, va);
2346 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
2347 free_pv_entry(pmap, pv);
2351 * Conditionally create the PV entry for a 4KB page mapping if the required
2352 * memory can be allocated without resorting to reclamation.
2355 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m,
2356 struct rwlock **lockp)
2360 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2361 /* Pass NULL instead of the lock pointer to disable reclamation. */
2362 if ((pv = get_pv_entry(pmap, NULL)) != NULL) {
2364 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
2365 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2373 * Create the PV entry for a 2MB page mapping. Always returns true unless the
2374 * flag PMAP_ENTER_NORECLAIM is specified. If that flag is specified, returns
2375 * false if the PV entry cannot be allocated without resorting to reclamation.
2378 pmap_pv_insert_l2(pmap_t pmap, vm_offset_t va, pd_entry_t l2e, u_int flags,
2379 struct rwlock **lockp)
2381 struct md_page *pvh;
2385 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2386 /* Pass NULL instead of the lock pointer to disable reclamation. */
2387 if ((pv = get_pv_entry(pmap, (flags & PMAP_ENTER_NORECLAIM) != 0 ?
2388 NULL : lockp)) == NULL)
2391 pa = l2e & ~ATTR_MASK;
2392 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
2393 pvh = pa_to_pvh(pa);
2394 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2400 pmap_remove_kernel_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t va)
2402 pt_entry_t newl2, oldl2;
2406 KASSERT(!VIRT_IN_DMAP(va), ("removing direct mapping of %#lx", va));
2407 KASSERT(pmap == kernel_pmap, ("pmap %p is not kernel_pmap", pmap));
2408 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2410 ml3 = pmap_remove_pt_page(pmap, va);
2412 panic("pmap_remove_kernel_l2: Missing pt page");
2414 ml3pa = VM_PAGE_TO_PHYS(ml3);
2415 newl2 = ml3pa | L2_TABLE;
2418 * If this page table page was unmapped by a promotion, then it
2419 * contains valid mappings. Zero it to invalidate those mappings.
2421 if (ml3->valid != 0)
2422 pagezero((void *)PHYS_TO_DMAP(ml3pa));
2425 * Demote the mapping. The caller must have already invalidated the
2426 * mapping (i.e., the "break" in break-before-make).
2428 oldl2 = pmap_load_store(l2, newl2);
2429 KASSERT(oldl2 == 0, ("%s: found existing mapping at %p: %#lx",
2430 __func__, l2, oldl2));
2434 * pmap_remove_l2: Do the things to unmap a level 2 superpage.
2437 pmap_remove_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t sva,
2438 pd_entry_t l1e, struct spglist *free, struct rwlock **lockp)
2440 struct md_page *pvh;
2442 vm_offset_t eva, va;
2445 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2446 KASSERT((sva & L2_OFFSET) == 0, ("pmap_remove_l2: sva is not aligned"));
2447 old_l2 = pmap_load_clear(l2);
2448 KASSERT((old_l2 & ATTR_DESCR_MASK) == L2_BLOCK,
2449 ("pmap_remove_l2: L2e %lx is not a block mapping", old_l2));
2452 * Since a promotion must break the 4KB page mappings before making
2453 * the 2MB page mapping, a pmap_invalidate_page() suffices.
2455 pmap_invalidate_page(pmap, sva);
2457 if (old_l2 & ATTR_SW_WIRED)
2458 pmap->pm_stats.wired_count -= L2_SIZE / PAGE_SIZE;
2459 pmap_resident_count_dec(pmap, L2_SIZE / PAGE_SIZE);
2460 if (old_l2 & ATTR_SW_MANAGED) {
2461 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, old_l2 & ~ATTR_MASK);
2462 pvh = pa_to_pvh(old_l2 & ~ATTR_MASK);
2463 pmap_pvh_free(pvh, pmap, sva);
2464 eva = sva + L2_SIZE;
2465 for (va = sva, m = PHYS_TO_VM_PAGE(old_l2 & ~ATTR_MASK);
2466 va < eva; va += PAGE_SIZE, m++) {
2467 if (pmap_pte_dirty(old_l2))
2469 if (old_l2 & ATTR_AF)
2470 vm_page_aflag_set(m, PGA_REFERENCED);
2471 if (TAILQ_EMPTY(&m->md.pv_list) &&
2472 TAILQ_EMPTY(&pvh->pv_list))
2473 vm_page_aflag_clear(m, PGA_WRITEABLE);
2476 if (pmap == kernel_pmap) {
2477 pmap_remove_kernel_l2(pmap, l2, sva);
2479 ml3 = pmap_remove_pt_page(pmap, sva);
2481 KASSERT(ml3->valid == VM_PAGE_BITS_ALL,
2482 ("pmap_remove_l2: l3 page not promoted"));
2483 pmap_resident_count_dec(pmap, 1);
2484 KASSERT(ml3->wire_count == NL3PG,
2485 ("pmap_remove_l2: l3 page wire count error"));
2486 ml3->wire_count = 0;
2487 pmap_add_delayed_free_list(ml3, free, FALSE);
2490 return (pmap_unuse_pt(pmap, sva, l1e, free));
2494 * pmap_remove_l3: do the things to unmap a page in a process
2497 pmap_remove_l3(pmap_t pmap, pt_entry_t *l3, vm_offset_t va,
2498 pd_entry_t l2e, struct spglist *free, struct rwlock **lockp)
2500 struct md_page *pvh;
2504 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2505 old_l3 = pmap_load_clear(l3);
2506 pmap_invalidate_page(pmap, va);
2507 if (old_l3 & ATTR_SW_WIRED)
2508 pmap->pm_stats.wired_count -= 1;
2509 pmap_resident_count_dec(pmap, 1);
2510 if (old_l3 & ATTR_SW_MANAGED) {
2511 m = PHYS_TO_VM_PAGE(old_l3 & ~ATTR_MASK);
2512 if (pmap_pte_dirty(old_l3))
2514 if (old_l3 & ATTR_AF)
2515 vm_page_aflag_set(m, PGA_REFERENCED);
2516 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
2517 pmap_pvh_free(&m->md, pmap, va);
2518 if (TAILQ_EMPTY(&m->md.pv_list) &&
2519 (m->flags & PG_FICTITIOUS) == 0) {
2520 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2521 if (TAILQ_EMPTY(&pvh->pv_list))
2522 vm_page_aflag_clear(m, PGA_WRITEABLE);
2525 return (pmap_unuse_pt(pmap, va, l2e, free));
2529 * Remove the specified range of addresses from the L3 page table that is
2530 * identified by the given L2 entry.
2533 pmap_remove_l3_range(pmap_t pmap, pd_entry_t l2e, vm_offset_t sva,
2534 vm_offset_t eva, struct spglist *free, struct rwlock **lockp)
2536 struct md_page *pvh;
2537 struct rwlock *new_lock;
2538 pt_entry_t *l3, old_l3;
2542 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2543 KASSERT(rounddown2(sva, L2_SIZE) + L2_SIZE == roundup2(eva, L2_SIZE),
2544 ("pmap_remove_l3_range: range crosses an L3 page table boundary"));
2546 for (l3 = pmap_l2_to_l3(&l2e, sva); sva != eva; l3++, sva += L3_SIZE) {
2547 if (!pmap_l3_valid(pmap_load(l3))) {
2549 pmap_invalidate_range(pmap, va, sva);
2554 old_l3 = pmap_load_clear(l3);
2555 if ((old_l3 & ATTR_SW_WIRED) != 0)
2556 pmap->pm_stats.wired_count--;
2557 pmap_resident_count_dec(pmap, 1);
2558 if ((old_l3 & ATTR_SW_MANAGED) != 0) {
2559 m = PHYS_TO_VM_PAGE(old_l3 & ~ATTR_MASK);
2560 if (pmap_pte_dirty(old_l3))
2562 if ((old_l3 & ATTR_AF) != 0)
2563 vm_page_aflag_set(m, PGA_REFERENCED);
2564 new_lock = PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m));
2565 if (new_lock != *lockp) {
2566 if (*lockp != NULL) {
2568 * Pending TLB invalidations must be
2569 * performed before the PV list lock is
2570 * released. Otherwise, a concurrent
2571 * pmap_remove_all() on a physical page
2572 * could return while a stale TLB entry
2573 * still provides access to that page.
2576 pmap_invalidate_range(pmap, va,
2585 pmap_pvh_free(&m->md, pmap, sva);
2586 if (TAILQ_EMPTY(&m->md.pv_list) &&
2587 (m->flags & PG_FICTITIOUS) == 0) {
2588 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2589 if (TAILQ_EMPTY(&pvh->pv_list))
2590 vm_page_aflag_clear(m, PGA_WRITEABLE);
2595 if (pmap_unuse_pt(pmap, sva, l2e, free)) {
2601 pmap_invalidate_range(pmap, va, sva);
2605 * Remove the given range of addresses from the specified map.
2607 * It is assumed that the start and end are properly
2608 * rounded to the page size.
2611 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2613 struct rwlock *lock;
2614 vm_offset_t va_next;
2615 pd_entry_t *l0, *l1, *l2;
2616 pt_entry_t l3_paddr;
2617 struct spglist free;
2620 * Perform an unsynchronized read. This is, however, safe.
2622 if (pmap->pm_stats.resident_count == 0)
2630 for (; sva < eva; sva = va_next) {
2632 if (pmap->pm_stats.resident_count == 0)
2635 l0 = pmap_l0(pmap, sva);
2636 if (pmap_load(l0) == 0) {
2637 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
2643 l1 = pmap_l0_to_l1(l0, sva);
2644 if (pmap_load(l1) == 0) {
2645 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
2652 * Calculate index for next page table.
2654 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
2658 l2 = pmap_l1_to_l2(l1, sva);
2662 l3_paddr = pmap_load(l2);
2664 if ((l3_paddr & ATTR_DESCR_MASK) == L2_BLOCK) {
2665 if (sva + L2_SIZE == va_next && eva >= va_next) {
2666 pmap_remove_l2(pmap, l2, sva, pmap_load(l1),
2669 } else if (pmap_demote_l2_locked(pmap, l2, sva,
2672 l3_paddr = pmap_load(l2);
2676 * Weed out invalid mappings.
2678 if ((l3_paddr & ATTR_DESCR_MASK) != L2_TABLE)
2682 * Limit our scan to either the end of the va represented
2683 * by the current page table page, or to the end of the
2684 * range being removed.
2689 pmap_remove_l3_range(pmap, l3_paddr, sva, va_next, &free,
2695 vm_page_free_pages_toq(&free, true);
2699 * Routine: pmap_remove_all
2701 * Removes this physical page from
2702 * all physical maps in which it resides.
2703 * Reflects back modify bits to the pager.
2706 * Original versions of this routine were very
2707 * inefficient because they iteratively called
2708 * pmap_remove (slow...)
2712 pmap_remove_all(vm_page_t m)
2714 struct md_page *pvh;
2717 struct rwlock *lock;
2718 pd_entry_t *pde, tpde;
2719 pt_entry_t *pte, tpte;
2721 struct spglist free;
2722 int lvl, pvh_gen, md_gen;
2724 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2725 ("pmap_remove_all: page %p is not managed", m));
2727 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
2728 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
2729 pa_to_pvh(VM_PAGE_TO_PHYS(m));
2732 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
2734 if (!PMAP_TRYLOCK(pmap)) {
2735 pvh_gen = pvh->pv_gen;
2739 if (pvh_gen != pvh->pv_gen) {
2746 pte = pmap_pte(pmap, va, &lvl);
2747 KASSERT(pte != NULL,
2748 ("pmap_remove_all: no page table entry found"));
2750 ("pmap_remove_all: invalid pte level %d", lvl));
2752 pmap_demote_l2_locked(pmap, pte, va, &lock);
2755 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
2757 if (!PMAP_TRYLOCK(pmap)) {
2758 pvh_gen = pvh->pv_gen;
2759 md_gen = m->md.pv_gen;
2763 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
2769 pmap_resident_count_dec(pmap, 1);
2771 pde = pmap_pde(pmap, pv->pv_va, &lvl);
2772 KASSERT(pde != NULL,
2773 ("pmap_remove_all: no page directory entry found"));
2775 ("pmap_remove_all: invalid pde level %d", lvl));
2776 tpde = pmap_load(pde);
2778 pte = pmap_l2_to_l3(pde, pv->pv_va);
2779 tpte = pmap_load_clear(pte);
2780 pmap_invalidate_page(pmap, pv->pv_va);
2781 if (tpte & ATTR_SW_WIRED)
2782 pmap->pm_stats.wired_count--;
2783 if ((tpte & ATTR_AF) != 0)
2784 vm_page_aflag_set(m, PGA_REFERENCED);
2787 * Update the vm_page_t clean and reference bits.
2789 if (pmap_pte_dirty(tpte))
2791 pmap_unuse_pt(pmap, pv->pv_va, tpde, &free);
2792 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
2794 free_pv_entry(pmap, pv);
2797 vm_page_aflag_clear(m, PGA_WRITEABLE);
2799 vm_page_free_pages_toq(&free, true);
2803 * pmap_protect_l2: do the things to protect a 2MB page in a pmap
2806 pmap_protect_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t sva, pt_entry_t mask,
2812 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2813 KASSERT((sva & L2_OFFSET) == 0,
2814 ("pmap_protect_l2: sva is not 2mpage aligned"));
2815 old_l2 = pmap_load(l2);
2816 KASSERT((old_l2 & ATTR_DESCR_MASK) == L2_BLOCK,
2817 ("pmap_protect_l2: L2e %lx is not a block mapping", old_l2));
2820 * Return if the L2 entry already has the desired access restrictions
2824 if ((old_l2 & mask) == nbits)
2828 * When a dirty read/write superpage mapping is write protected,
2829 * update the dirty field of each of the superpage's constituent 4KB
2832 if ((old_l2 & ATTR_SW_MANAGED) != 0 &&
2833 (nbits & ATTR_AP(ATTR_AP_RO)) != 0 && pmap_pte_dirty(old_l2)) {
2834 m = PHYS_TO_VM_PAGE(old_l2 & ~ATTR_MASK);
2835 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
2839 if (!atomic_fcmpset_64(l2, &old_l2, (old_l2 & ~mask) | nbits))
2843 * Since a promotion must break the 4KB page mappings before making
2844 * the 2MB page mapping, a pmap_invalidate_page() suffices.
2846 pmap_invalidate_page(pmap, sva);
2850 * Set the physical protection on the
2851 * specified range of this map as requested.
2854 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
2856 vm_offset_t va, va_next;
2857 pd_entry_t *l0, *l1, *l2;
2858 pt_entry_t *l3p, l3, mask, nbits;
2860 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
2861 if (prot == VM_PROT_NONE) {
2862 pmap_remove(pmap, sva, eva);
2867 if ((prot & VM_PROT_WRITE) == 0) {
2868 mask |= ATTR_AP_RW_BIT | ATTR_SW_DBM;
2869 nbits |= ATTR_AP(ATTR_AP_RO);
2871 if ((prot & VM_PROT_EXECUTE) == 0) {
2879 for (; sva < eva; sva = va_next) {
2881 l0 = pmap_l0(pmap, sva);
2882 if (pmap_load(l0) == 0) {
2883 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
2889 l1 = pmap_l0_to_l1(l0, sva);
2890 if (pmap_load(l1) == 0) {
2891 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
2897 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
2901 l2 = pmap_l1_to_l2(l1, sva);
2902 if (pmap_load(l2) == 0)
2905 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK) {
2906 if (sva + L2_SIZE == va_next && eva >= va_next) {
2907 pmap_protect_l2(pmap, l2, sva, mask, nbits);
2909 } else if (pmap_demote_l2(pmap, l2, sva) == NULL)
2912 KASSERT((pmap_load(l2) & ATTR_DESCR_MASK) == L2_TABLE,
2913 ("pmap_protect: Invalid L2 entry after demotion"));
2919 for (l3p = pmap_l2_to_l3(l2, sva); sva != va_next; l3p++,
2921 l3 = pmap_load(l3p);
2924 * Go to the next L3 entry if the current one is
2925 * invalid or already has the desired access
2926 * restrictions in place. (The latter case occurs
2927 * frequently. For example, in a "buildworld"
2928 * workload, almost 1 out of 4 L3 entries already
2929 * have the desired restrictions.)
2931 if (!pmap_l3_valid(l3) || (l3 & mask) == nbits) {
2932 if (va != va_next) {
2933 pmap_invalidate_range(pmap, va, sva);
2940 * When a dirty read/write mapping is write protected,
2941 * update the page's dirty field.
2943 if ((l3 & ATTR_SW_MANAGED) != 0 &&
2944 (nbits & ATTR_AP(ATTR_AP_RO)) != 0 &&
2946 vm_page_dirty(PHYS_TO_VM_PAGE(l3 & ~ATTR_MASK));
2948 if (!atomic_fcmpset_64(l3p, &l3, (l3 & ~mask) | nbits))
2954 pmap_invalidate_range(pmap, va, sva);
2960 * Inserts the specified page table page into the specified pmap's collection
2961 * of idle page table pages. Each of a pmap's page table pages is responsible
2962 * for mapping a distinct range of virtual addresses. The pmap's collection is
2963 * ordered by this virtual address range.
2965 * If "promoted" is false, then the page table page "mpte" must be zero filled.
2968 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte, bool promoted)
2971 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2972 mpte->valid = promoted ? VM_PAGE_BITS_ALL : 0;
2973 return (vm_radix_insert(&pmap->pm_root, mpte));
2977 * Removes the page table page mapping the specified virtual address from the
2978 * specified pmap's collection of idle page table pages, and returns it.
2979 * Otherwise, returns NULL if there is no page table page corresponding to the
2980 * specified virtual address.
2982 static __inline vm_page_t
2983 pmap_remove_pt_page(pmap_t pmap, vm_offset_t va)
2986 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2987 return (vm_radix_remove(&pmap->pm_root, pmap_l2_pindex(va)));
2991 * Performs a break-before-make update of a pmap entry. This is needed when
2992 * either promoting or demoting pages to ensure the TLB doesn't get into an
2993 * inconsistent state.
2996 pmap_update_entry(pmap_t pmap, pd_entry_t *pte, pd_entry_t newpte,
2997 vm_offset_t va, vm_size_t size)
3001 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3004 * Ensure we don't get switched out with the page table in an
3005 * inconsistent state. We also need to ensure no interrupts fire
3006 * as they may make use of an address we are about to invalidate.
3008 intr = intr_disable();
3011 /* Clear the old mapping */
3013 pmap_invalidate_range_nopin(pmap, va, va + size);
3015 /* Create the new mapping */
3016 pmap_store(pte, newpte);
3023 #if VM_NRESERVLEVEL > 0
3025 * After promotion from 512 4KB page mappings to a single 2MB page mapping,
3026 * replace the many pv entries for the 4KB page mappings by a single pv entry
3027 * for the 2MB page mapping.
3030 pmap_pv_promote_l2(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
3031 struct rwlock **lockp)
3033 struct md_page *pvh;
3035 vm_offset_t va_last;
3038 KASSERT((pa & L2_OFFSET) == 0,
3039 ("pmap_pv_promote_l2: pa is not 2mpage aligned"));
3040 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
3043 * Transfer the first page's pv entry for this mapping to the 2mpage's
3044 * pv list. Aside from avoiding the cost of a call to get_pv_entry(),
3045 * a transfer avoids the possibility that get_pv_entry() calls
3046 * reclaim_pv_chunk() and that reclaim_pv_chunk() removes one of the
3047 * mappings that is being promoted.
3049 m = PHYS_TO_VM_PAGE(pa);
3050 va = va & ~L2_OFFSET;
3051 pv = pmap_pvh_remove(&m->md, pmap, va);
3052 KASSERT(pv != NULL, ("pmap_pv_promote_l2: pv not found"));
3053 pvh = pa_to_pvh(pa);
3054 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
3056 /* Free the remaining NPTEPG - 1 pv entries. */
3057 va_last = va + L2_SIZE - PAGE_SIZE;
3061 pmap_pvh_free(&m->md, pmap, va);
3062 } while (va < va_last);
3066 * Tries to promote the 512, contiguous 4KB page mappings that are within a
3067 * single level 2 table entry to a single 2MB page mapping. For promotion
3068 * to occur, two conditions must be met: (1) the 4KB page mappings must map
3069 * aligned, contiguous physical memory and (2) the 4KB page mappings must have
3070 * identical characteristics.
3073 pmap_promote_l2(pmap_t pmap, pd_entry_t *l2, vm_offset_t va,
3074 struct rwlock **lockp)
3076 pt_entry_t *firstl3, *l3, newl2, oldl3, pa;
3080 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3082 sva = va & ~L2_OFFSET;
3083 firstl3 = pmap_l2_to_l3(l2, sva);
3084 newl2 = pmap_load(firstl3);
3087 if (((newl2 & (~ATTR_MASK | ATTR_AF)) & L2_OFFSET) != ATTR_AF) {
3088 atomic_add_long(&pmap_l2_p_failures, 1);
3089 CTR2(KTR_PMAP, "pmap_promote_l2: failure for va %#lx"
3090 " in pmap %p", va, pmap);
3094 if ((newl2 & (ATTR_AP_RW_BIT | ATTR_SW_DBM)) ==
3095 (ATTR_AP(ATTR_AP_RO) | ATTR_SW_DBM)) {
3096 if (!atomic_fcmpset_64(l2, &newl2, newl2 & ~ATTR_SW_DBM))
3098 newl2 &= ~ATTR_SW_DBM;
3101 pa = newl2 + L2_SIZE - PAGE_SIZE;
3102 for (l3 = firstl3 + NL3PG - 1; l3 > firstl3; l3--) {
3103 oldl3 = pmap_load(l3);
3105 if ((oldl3 & (ATTR_AP_RW_BIT | ATTR_SW_DBM)) ==
3106 (ATTR_AP(ATTR_AP_RO) | ATTR_SW_DBM)) {
3107 if (!atomic_fcmpset_64(l3, &oldl3, oldl3 &
3110 oldl3 &= ~ATTR_SW_DBM;
3113 atomic_add_long(&pmap_l2_p_failures, 1);
3114 CTR2(KTR_PMAP, "pmap_promote_l2: failure for va %#lx"
3115 " in pmap %p", va, pmap);
3122 * Save the page table page in its current state until the L2
3123 * mapping the superpage is demoted by pmap_demote_l2() or
3124 * destroyed by pmap_remove_l3().
3126 mpte = PHYS_TO_VM_PAGE(pmap_load(l2) & ~ATTR_MASK);
3127 KASSERT(mpte >= vm_page_array &&
3128 mpte < &vm_page_array[vm_page_array_size],
3129 ("pmap_promote_l2: page table page is out of range"));
3130 KASSERT(mpte->pindex == pmap_l2_pindex(va),
3131 ("pmap_promote_l2: page table page's pindex is wrong"));
3132 if (pmap_insert_pt_page(pmap, mpte, true)) {
3133 atomic_add_long(&pmap_l2_p_failures, 1);
3135 "pmap_promote_l2: failure for va %#lx in pmap %p", va,
3140 if ((newl2 & ATTR_SW_MANAGED) != 0)
3141 pmap_pv_promote_l2(pmap, va, newl2 & ~ATTR_MASK, lockp);
3143 newl2 &= ~ATTR_DESCR_MASK;
3146 pmap_update_entry(pmap, l2, newl2, sva, L2_SIZE);
3148 atomic_add_long(&pmap_l2_promotions, 1);
3149 CTR2(KTR_PMAP, "pmap_promote_l2: success for va %#lx in pmap %p", va,
3152 #endif /* VM_NRESERVLEVEL > 0 */
3155 * Insert the given physical page (p) at
3156 * the specified virtual address (v) in the
3157 * target physical map with the protection requested.
3159 * If specified, the page will be wired down, meaning
3160 * that the related pte can not be reclaimed.
3162 * NB: This is the only routine which MAY NOT lazy-evaluate
3163 * or lose information. That is, this routine must actually
3164 * insert this page into the given map NOW.
3167 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
3168 u_int flags, int8_t psind)
3170 struct rwlock *lock;
3172 pt_entry_t new_l3, orig_l3;
3173 pt_entry_t *l2, *l3;
3180 va = trunc_page(va);
3181 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
3182 VM_OBJECT_ASSERT_LOCKED(m->object);
3183 pa = VM_PAGE_TO_PHYS(m);
3184 new_l3 = (pt_entry_t)(pa | ATTR_DEFAULT | ATTR_IDX(m->md.pv_memattr) |
3186 if ((prot & VM_PROT_WRITE) == 0)
3187 new_l3 |= ATTR_AP(ATTR_AP_RO);
3188 if ((prot & VM_PROT_EXECUTE) == 0 || m->md.pv_memattr == DEVICE_MEMORY)
3190 if ((flags & PMAP_ENTER_WIRED) != 0)
3191 new_l3 |= ATTR_SW_WIRED;
3192 if (va < VM_MAXUSER_ADDRESS)
3193 new_l3 |= ATTR_AP(ATTR_AP_USER) | ATTR_PXN;
3194 if ((m->oflags & VPO_UNMANAGED) == 0) {
3195 new_l3 |= ATTR_SW_MANAGED;
3196 if ((prot & VM_PROT_WRITE) != 0) {
3197 new_l3 |= ATTR_SW_DBM;
3198 if ((flags & VM_PROT_WRITE) == 0)
3199 new_l3 |= ATTR_AP(ATTR_AP_RO);
3203 CTR2(KTR_PMAP, "pmap_enter: %.16lx -> %.16lx", va, pa);
3208 /* Assert the required virtual and physical alignment. */
3209 KASSERT((va & L2_OFFSET) == 0, ("pmap_enter: va unaligned"));
3210 KASSERT(m->psind > 0, ("pmap_enter: m->psind < psind"));
3211 rv = pmap_enter_l2(pmap, va, (new_l3 & ~L3_PAGE) | L2_BLOCK,
3218 * In the case that a page table page is not
3219 * resident, we are creating it here.
3222 pde = pmap_pde(pmap, va, &lvl);
3223 if (pde != NULL && lvl == 2) {
3224 l3 = pmap_l2_to_l3(pde, va);
3225 if (va < VM_MAXUSER_ADDRESS && mpte == NULL) {
3226 mpte = PHYS_TO_VM_PAGE(pmap_load(pde) & ~ATTR_MASK);
3230 } else if (pde != NULL && lvl == 1) {
3231 l2 = pmap_l1_to_l2(pde, va);
3232 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK &&
3233 (l3 = pmap_demote_l2_locked(pmap, l2, va, &lock)) != NULL) {
3234 l3 = &l3[pmap_l3_index(va)];
3235 if (va < VM_MAXUSER_ADDRESS) {
3236 mpte = PHYS_TO_VM_PAGE(
3237 pmap_load(l2) & ~ATTR_MASK);
3242 /* We need to allocate an L3 table. */
3244 if (va < VM_MAXUSER_ADDRESS) {
3245 nosleep = (flags & PMAP_ENTER_NOSLEEP) != 0;
3248 * We use _pmap_alloc_l3() instead of pmap_alloc_l3() in order
3249 * to handle the possibility that a superpage mapping for "va"
3250 * was created while we slept.
3252 mpte = _pmap_alloc_l3(pmap, pmap_l2_pindex(va),
3253 nosleep ? NULL : &lock);
3254 if (mpte == NULL && nosleep) {
3255 CTR0(KTR_PMAP, "pmap_enter: mpte == NULL");
3256 rv = KERN_RESOURCE_SHORTAGE;
3261 panic("pmap_enter: missing L3 table for kernel va %#lx", va);
3264 orig_l3 = pmap_load(l3);
3265 opa = orig_l3 & ~ATTR_MASK;
3269 * Is the specified virtual address already mapped?
3271 if (pmap_l3_valid(orig_l3)) {
3273 * Wiring change, just update stats. We don't worry about
3274 * wiring PT pages as they remain resident as long as there
3275 * are valid mappings in them. Hence, if a user page is wired,
3276 * the PT page will be also.
3278 if ((flags & PMAP_ENTER_WIRED) != 0 &&
3279 (orig_l3 & ATTR_SW_WIRED) == 0)
3280 pmap->pm_stats.wired_count++;
3281 else if ((flags & PMAP_ENTER_WIRED) == 0 &&
3282 (orig_l3 & ATTR_SW_WIRED) != 0)
3283 pmap->pm_stats.wired_count--;
3286 * Remove the extra PT page reference.
3290 KASSERT(mpte->wire_count > 0,
3291 ("pmap_enter: missing reference to page table page,"
3296 * Has the physical page changed?
3300 * No, might be a protection or wiring change.
3302 if ((orig_l3 & ATTR_SW_MANAGED) != 0 &&
3303 (new_l3 & ATTR_SW_DBM) != 0)
3304 vm_page_aflag_set(m, PGA_WRITEABLE);
3309 * The physical page has changed. Temporarily invalidate
3312 orig_l3 = pmap_load_clear(l3);
3313 KASSERT((orig_l3 & ~ATTR_MASK) == opa,
3314 ("pmap_enter: unexpected pa update for %#lx", va));
3315 if ((orig_l3 & ATTR_SW_MANAGED) != 0) {
3316 om = PHYS_TO_VM_PAGE(opa);
3319 * The pmap lock is sufficient to synchronize with
3320 * concurrent calls to pmap_page_test_mappings() and
3321 * pmap_ts_referenced().
3323 if (pmap_pte_dirty(orig_l3))
3325 if ((orig_l3 & ATTR_AF) != 0)
3326 vm_page_aflag_set(om, PGA_REFERENCED);
3327 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, opa);
3328 pv = pmap_pvh_remove(&om->md, pmap, va);
3329 if ((m->oflags & VPO_UNMANAGED) != 0)
3330 free_pv_entry(pmap, pv);
3331 if ((om->aflags & PGA_WRITEABLE) != 0 &&
3332 TAILQ_EMPTY(&om->md.pv_list) &&
3333 ((om->flags & PG_FICTITIOUS) != 0 ||
3334 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
3335 vm_page_aflag_clear(om, PGA_WRITEABLE);
3337 pmap_invalidate_page(pmap, va);
3341 * Increment the counters.
3343 if ((new_l3 & ATTR_SW_WIRED) != 0)
3344 pmap->pm_stats.wired_count++;
3345 pmap_resident_count_inc(pmap, 1);
3348 * Enter on the PV list if part of our managed memory.
3350 if ((m->oflags & VPO_UNMANAGED) == 0) {
3352 pv = get_pv_entry(pmap, &lock);
3355 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, pa);
3356 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3358 if ((new_l3 & ATTR_SW_DBM) != 0)
3359 vm_page_aflag_set(m, PGA_WRITEABLE);
3364 * Sync icache if exec permission and attribute VM_MEMATTR_WRITE_BACK
3365 * is set. Do it now, before the mapping is stored and made
3366 * valid for hardware table walk. If done later, then other can
3367 * access this page before caches are properly synced.
3368 * Don't do it for kernel memory which is mapped with exec
3369 * permission even if the memory isn't going to hold executable
3370 * code. The only time when icache sync is needed is after
3371 * kernel module is loaded and the relocation info is processed.
3372 * And it's done in elf_cpu_load_file().
3374 if ((prot & VM_PROT_EXECUTE) && pmap != kernel_pmap &&
3375 m->md.pv_memattr == VM_MEMATTR_WRITE_BACK &&
3376 (opa != pa || (orig_l3 & ATTR_XN)))
3377 cpu_icache_sync_range(PHYS_TO_DMAP(pa), PAGE_SIZE);
3380 * Update the L3 entry
3382 if (pmap_l3_valid(orig_l3)) {
3383 KASSERT(opa == pa, ("pmap_enter: invalid update"));
3384 if ((orig_l3 & ~ATTR_AF) != (new_l3 & ~ATTR_AF)) {
3385 /* same PA, different attributes */
3386 /* XXXMJ need to reload orig_l3 for hardware DBM. */
3387 pmap_load_store(l3, new_l3);
3388 pmap_invalidate_page(pmap, va);
3389 if ((orig_l3 & ATTR_SW_MANAGED) != 0 &&
3390 pmap_pte_dirty(orig_l3))
3395 * This can happens if multiple threads simultaneously
3396 * access not yet mapped page. This bad for performance
3397 * since this can cause full demotion-NOP-promotion
3399 * Another possible reasons are:
3400 * - VM and pmap memory layout are diverged
3401 * - tlb flush is missing somewhere and CPU doesn't see
3404 CTR4(KTR_PMAP, "%s: already mapped page - "
3405 "pmap %p va 0x%#lx pte 0x%lx",
3406 __func__, pmap, va, new_l3);
3410 pmap_store(l3, new_l3);
3414 #if VM_NRESERVLEVEL > 0
3415 if (pmap != pmap_kernel() &&
3416 (mpte == NULL || mpte->wire_count == NL3PG) &&
3417 pmap_ps_enabled(pmap) &&
3418 (m->flags & PG_FICTITIOUS) == 0 &&
3419 vm_reserv_level_iffullpop(m) == 0) {
3420 pmap_promote_l2(pmap, pde, va, &lock);
3433 * Tries to create a read- and/or execute-only 2MB page mapping. Returns true
3434 * if successful. Returns false if (1) a page table page cannot be allocated
3435 * without sleeping, (2) a mapping already exists at the specified virtual
3436 * address, or (3) a PV entry cannot be allocated without reclaiming another
3440 pmap_enter_2mpage(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
3441 struct rwlock **lockp)
3445 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3447 new_l2 = (pd_entry_t)(VM_PAGE_TO_PHYS(m) | ATTR_DEFAULT |
3448 ATTR_IDX(m->md.pv_memattr) | ATTR_AP(ATTR_AP_RO) | L2_BLOCK);
3449 if ((m->oflags & VPO_UNMANAGED) == 0) {
3450 new_l2 |= ATTR_SW_MANAGED;
3453 if ((prot & VM_PROT_EXECUTE) == 0 || m->md.pv_memattr == DEVICE_MEMORY)
3455 if (va < VM_MAXUSER_ADDRESS)
3456 new_l2 |= ATTR_AP(ATTR_AP_USER) | ATTR_PXN;
3457 return (pmap_enter_l2(pmap, va, new_l2, PMAP_ENTER_NOSLEEP |
3458 PMAP_ENTER_NOREPLACE | PMAP_ENTER_NORECLAIM, NULL, lockp) ==
3463 * Tries to create the specified 2MB page mapping. Returns KERN_SUCCESS if
3464 * the mapping was created, and either KERN_FAILURE or KERN_RESOURCE_SHORTAGE
3465 * otherwise. Returns KERN_FAILURE if PMAP_ENTER_NOREPLACE was specified and
3466 * a mapping already exists at the specified virtual address. Returns
3467 * KERN_RESOURCE_SHORTAGE if PMAP_ENTER_NOSLEEP was specified and a page table
3468 * page allocation failed. Returns KERN_RESOURCE_SHORTAGE if
3469 * PMAP_ENTER_NORECLAIM was specified and a PV entry allocation failed.
3471 * The parameter "m" is only used when creating a managed, writeable mapping.
3474 pmap_enter_l2(pmap_t pmap, vm_offset_t va, pd_entry_t new_l2, u_int flags,
3475 vm_page_t m, struct rwlock **lockp)
3477 struct spglist free;
3478 pd_entry_t *l2, old_l2;
3481 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3483 if ((l2pg = pmap_alloc_l2(pmap, va, (flags & PMAP_ENTER_NOSLEEP) != 0 ?
3484 NULL : lockp)) == NULL) {
3485 CTR2(KTR_PMAP, "pmap_enter_l2: failure for va %#lx in pmap %p",
3487 return (KERN_RESOURCE_SHORTAGE);
3490 l2 = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(l2pg));
3491 l2 = &l2[pmap_l2_index(va)];
3492 if ((old_l2 = pmap_load(l2)) != 0) {
3493 KASSERT(l2pg->wire_count > 1,
3494 ("pmap_enter_l2: l2pg's wire count is too low"));
3495 if ((flags & PMAP_ENTER_NOREPLACE) != 0) {
3498 "pmap_enter_l2: failure for va %#lx in pmap %p",
3500 return (KERN_FAILURE);
3503 if ((old_l2 & ATTR_DESCR_MASK) == L2_BLOCK)
3504 (void)pmap_remove_l2(pmap, l2, va,
3505 pmap_load(pmap_l1(pmap, va)), &free, lockp);
3507 pmap_remove_l3_range(pmap, old_l2, va, va + L2_SIZE,
3509 vm_page_free_pages_toq(&free, true);
3510 if (va >= VM_MAXUSER_ADDRESS) {
3512 * Both pmap_remove_l2() and pmap_remove_l3_range()
3513 * will leave the kernel page table page zero filled.
3514 * Nonetheless, the TLB could have an intermediate
3515 * entry for the kernel page table page.
3517 mt = PHYS_TO_VM_PAGE(pmap_load(l2) & ~ATTR_MASK);
3518 if (pmap_insert_pt_page(pmap, mt, false))
3519 panic("pmap_enter_l2: trie insert failed");
3521 pmap_invalidate_page(pmap, va);
3523 KASSERT(pmap_load(l2) == 0,
3524 ("pmap_enter_l2: non-zero L2 entry %p", l2));
3527 if ((new_l2 & ATTR_SW_MANAGED) != 0) {
3529 * Abort this mapping if its PV entry could not be created.
3531 if (!pmap_pv_insert_l2(pmap, va, new_l2, flags, lockp)) {
3533 if (pmap_unwire_l3(pmap, va, l2pg, &free)) {
3535 * Although "va" is not mapped, the TLB could
3536 * nonetheless have intermediate entries that
3537 * refer to the freed page table pages.
3538 * Invalidate those entries.
3540 * XXX redundant invalidation (See
3541 * _pmap_unwire_l3().)
3543 pmap_invalidate_page(pmap, va);
3544 vm_page_free_pages_toq(&free, true);
3547 "pmap_enter_l2: failure for va %#lx in pmap %p",
3549 return (KERN_RESOURCE_SHORTAGE);
3551 if ((new_l2 & ATTR_SW_DBM) != 0)
3552 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
3553 vm_page_aflag_set(mt, PGA_WRITEABLE);
3557 * Increment counters.
3559 if ((new_l2 & ATTR_SW_WIRED) != 0)
3560 pmap->pm_stats.wired_count += L2_SIZE / PAGE_SIZE;
3561 pmap->pm_stats.resident_count += L2_SIZE / PAGE_SIZE;
3564 * Map the superpage.
3566 pmap_store(l2, new_l2);
3569 atomic_add_long(&pmap_l2_mappings, 1);
3570 CTR2(KTR_PMAP, "pmap_enter_l2: success for va %#lx in pmap %p",
3573 return (KERN_SUCCESS);
3577 * Maps a sequence of resident pages belonging to the same object.
3578 * The sequence begins with the given page m_start. This page is
3579 * mapped at the given virtual address start. Each subsequent page is
3580 * mapped at a virtual address that is offset from start by the same
3581 * amount as the page is offset from m_start within the object. The
3582 * last page in the sequence is the page with the largest offset from
3583 * m_start that can be mapped at a virtual address less than the given
3584 * virtual address end. Not every virtual page between start and end
3585 * is mapped; only those for which a resident page exists with the
3586 * corresponding offset from m_start are mapped.
3589 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
3590 vm_page_t m_start, vm_prot_t prot)
3592 struct rwlock *lock;
3595 vm_pindex_t diff, psize;
3597 VM_OBJECT_ASSERT_LOCKED(m_start->object);
3599 psize = atop(end - start);
3604 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
3605 va = start + ptoa(diff);
3606 if ((va & L2_OFFSET) == 0 && va + L2_SIZE <= end &&
3607 m->psind == 1 && pmap_ps_enabled(pmap) &&
3608 pmap_enter_2mpage(pmap, va, m, prot, &lock))
3609 m = &m[L2_SIZE / PAGE_SIZE - 1];
3611 mpte = pmap_enter_quick_locked(pmap, va, m, prot, mpte,
3613 m = TAILQ_NEXT(m, listq);
3621 * this code makes some *MAJOR* assumptions:
3622 * 1. Current pmap & pmap exists.
3625 * 4. No page table pages.
3626 * but is *MUCH* faster than pmap_enter...
3630 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3632 struct rwlock *lock;
3636 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL, &lock);
3643 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
3644 vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp)
3646 struct spglist free;
3648 pt_entry_t *l2, *l3, l3_val;
3652 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
3653 (m->oflags & VPO_UNMANAGED) != 0,
3654 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
3655 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3657 CTR2(KTR_PMAP, "pmap_enter_quick_locked: %p %lx", pmap, va);
3659 * In the case that a page table page is not
3660 * resident, we are creating it here.
3662 if (va < VM_MAXUSER_ADDRESS) {
3663 vm_pindex_t l2pindex;
3666 * Calculate pagetable page index
3668 l2pindex = pmap_l2_pindex(va);
3669 if (mpte && (mpte->pindex == l2pindex)) {
3675 pde = pmap_pde(pmap, va, &lvl);
3678 * If the page table page is mapped, we just increment
3679 * the hold count, and activate it. Otherwise, we
3680 * attempt to allocate a page table page. If this
3681 * attempt fails, we don't retry. Instead, we give up.
3684 l2 = pmap_l1_to_l2(pde, va);
3685 if ((pmap_load(l2) & ATTR_DESCR_MASK) ==
3689 if (lvl == 2 && pmap_load(pde) != 0) {
3691 PHYS_TO_VM_PAGE(pmap_load(pde) & ~ATTR_MASK);
3695 * Pass NULL instead of the PV list lock
3696 * pointer, because we don't intend to sleep.
3698 mpte = _pmap_alloc_l3(pmap, l2pindex, NULL);
3703 l3 = (pt_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpte));
3704 l3 = &l3[pmap_l3_index(va)];
3707 pde = pmap_pde(kernel_pmap, va, &lvl);
3708 KASSERT(pde != NULL,
3709 ("pmap_enter_quick_locked: Invalid page entry, va: 0x%lx",
3712 ("pmap_enter_quick_locked: Invalid level %d", lvl));
3713 l3 = pmap_l2_to_l3(pde, va);
3717 * Abort if a mapping already exists.
3719 if (pmap_load(l3) != 0) {
3728 * Enter on the PV list if part of our managed memory.
3730 if ((m->oflags & VPO_UNMANAGED) == 0 &&
3731 !pmap_try_insert_pv_entry(pmap, va, m, lockp)) {
3734 if (pmap_unwire_l3(pmap, va, mpte, &free)) {
3735 pmap_invalidate_page(pmap, va);
3736 vm_page_free_pages_toq(&free, true);
3744 * Increment counters
3746 pmap_resident_count_inc(pmap, 1);
3748 pa = VM_PAGE_TO_PHYS(m);
3749 l3_val = pa | ATTR_DEFAULT | ATTR_IDX(m->md.pv_memattr) |
3750 ATTR_AP(ATTR_AP_RO) | L3_PAGE;
3751 if ((prot & VM_PROT_EXECUTE) == 0 || m->md.pv_memattr == DEVICE_MEMORY)
3753 else if (va < VM_MAXUSER_ADDRESS)
3757 * Now validate mapping with RO protection
3759 if ((m->oflags & VPO_UNMANAGED) == 0) {
3760 l3_val |= ATTR_SW_MANAGED;
3764 /* Sync icache before the mapping is stored to PTE */
3765 if ((prot & VM_PROT_EXECUTE) && pmap != kernel_pmap &&
3766 m->md.pv_memattr == VM_MEMATTR_WRITE_BACK)
3767 cpu_icache_sync_range(PHYS_TO_DMAP(pa), PAGE_SIZE);
3769 pmap_store(l3, l3_val);
3776 * This code maps large physical mmap regions into the
3777 * processor address space. Note that some shortcuts
3778 * are taken, but the code works.
3781 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
3782 vm_pindex_t pindex, vm_size_t size)
3785 VM_OBJECT_ASSERT_WLOCKED(object);
3786 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
3787 ("pmap_object_init_pt: non-device object"));
3791 * Clear the wired attribute from the mappings for the specified range of
3792 * addresses in the given pmap. Every valid mapping within that range
3793 * must have the wired attribute set. In contrast, invalid mappings
3794 * cannot have the wired attribute set, so they are ignored.
3796 * The wired attribute of the page table entry is not a hardware feature,
3797 * so there is no need to invalidate any TLB entries.
3800 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
3802 vm_offset_t va_next;
3803 pd_entry_t *l0, *l1, *l2;
3807 for (; sva < eva; sva = va_next) {
3808 l0 = pmap_l0(pmap, sva);
3809 if (pmap_load(l0) == 0) {
3810 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
3816 l1 = pmap_l0_to_l1(l0, sva);
3817 if (pmap_load(l1) == 0) {
3818 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
3824 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
3828 l2 = pmap_l1_to_l2(l1, sva);
3829 if (pmap_load(l2) == 0)
3832 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK) {
3833 if ((pmap_load(l2) & ATTR_SW_WIRED) == 0)
3834 panic("pmap_unwire: l2 %#jx is missing "
3835 "ATTR_SW_WIRED", (uintmax_t)pmap_load(l2));
3838 * Are we unwiring the entire large page? If not,
3839 * demote the mapping and fall through.
3841 if (sva + L2_SIZE == va_next && eva >= va_next) {
3842 pmap_clear_bits(l2, ATTR_SW_WIRED);
3843 pmap->pm_stats.wired_count -= L2_SIZE /
3846 } else if (pmap_demote_l2(pmap, l2, sva) == NULL)
3847 panic("pmap_unwire: demotion failed");
3849 KASSERT((pmap_load(l2) & ATTR_DESCR_MASK) == L2_TABLE,
3850 ("pmap_unwire: Invalid l2 entry after demotion"));
3854 for (l3 = pmap_l2_to_l3(l2, sva); sva != va_next; l3++,
3856 if (pmap_load(l3) == 0)
3858 if ((pmap_load(l3) & ATTR_SW_WIRED) == 0)
3859 panic("pmap_unwire: l3 %#jx is missing "
3860 "ATTR_SW_WIRED", (uintmax_t)pmap_load(l3));
3863 * ATTR_SW_WIRED must be cleared atomically. Although
3864 * the pmap lock synchronizes access to ATTR_SW_WIRED,
3865 * the System MMU may write to the entry concurrently.
3867 pmap_clear_bits(l3, ATTR_SW_WIRED);
3868 pmap->pm_stats.wired_count--;
3875 * Copy the range specified by src_addr/len
3876 * from the source map to the range dst_addr/len
3877 * in the destination map.
3879 * This routine is only advisory and need not do anything.
3881 * Because the executable mappings created by this routine are copied,
3882 * it should not have to flush the instruction cache.
3885 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
3886 vm_offset_t src_addr)
3888 struct rwlock *lock;
3889 struct spglist free;
3890 pd_entry_t *l0, *l1, *l2, srcptepaddr;
3891 pt_entry_t *dst_pte, mask, nbits, ptetemp, *src_pte;
3892 vm_offset_t addr, end_addr, va_next;
3893 vm_page_t dst_l2pg, dstmpte, srcmpte;
3895 if (dst_addr != src_addr)
3897 end_addr = src_addr + len;
3899 if (dst_pmap < src_pmap) {
3900 PMAP_LOCK(dst_pmap);
3901 PMAP_LOCK(src_pmap);
3903 PMAP_LOCK(src_pmap);
3904 PMAP_LOCK(dst_pmap);
3906 for (addr = src_addr; addr < end_addr; addr = va_next) {
3907 l0 = pmap_l0(src_pmap, addr);
3908 if (pmap_load(l0) == 0) {
3909 va_next = (addr + L0_SIZE) & ~L0_OFFSET;
3914 l1 = pmap_l0_to_l1(l0, addr);
3915 if (pmap_load(l1) == 0) {
3916 va_next = (addr + L1_SIZE) & ~L1_OFFSET;
3921 va_next = (addr + L2_SIZE) & ~L2_OFFSET;
3924 l2 = pmap_l1_to_l2(l1, addr);
3925 srcptepaddr = pmap_load(l2);
3926 if (srcptepaddr == 0)
3928 if ((srcptepaddr & ATTR_DESCR_MASK) == L2_BLOCK) {
3929 if ((addr & L2_OFFSET) != 0 ||
3930 addr + L2_SIZE > end_addr)
3932 dst_l2pg = pmap_alloc_l2(dst_pmap, addr, NULL);
3933 if (dst_l2pg == NULL)
3936 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dst_l2pg));
3937 l2 = &l2[pmap_l2_index(addr)];
3938 if (pmap_load(l2) == 0 &&
3939 ((srcptepaddr & ATTR_SW_MANAGED) == 0 ||
3940 pmap_pv_insert_l2(dst_pmap, addr, srcptepaddr,
3941 PMAP_ENTER_NORECLAIM, &lock))) {
3942 mask = ATTR_AF | ATTR_SW_WIRED;
3944 if ((srcptepaddr & ATTR_SW_DBM) != 0)
3945 nbits |= ATTR_AP_RW_BIT;
3946 pmap_store(l2, (srcptepaddr & ~mask) | nbits);
3947 pmap_resident_count_inc(dst_pmap, L2_SIZE /
3949 atomic_add_long(&pmap_l2_mappings, 1);
3951 dst_l2pg->wire_count--;
3954 KASSERT((srcptepaddr & ATTR_DESCR_MASK) == L2_TABLE,
3955 ("pmap_copy: invalid L2 entry"));
3956 srcptepaddr &= ~ATTR_MASK;
3957 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr);
3958 KASSERT(srcmpte->wire_count > 0,
3959 ("pmap_copy: source page table page is unused"));
3960 if (va_next > end_addr)
3962 src_pte = (pt_entry_t *)PHYS_TO_DMAP(srcptepaddr);
3963 src_pte = &src_pte[pmap_l3_index(addr)];
3965 for (; addr < va_next; addr += PAGE_SIZE, src_pte++) {
3966 ptetemp = pmap_load(src_pte);
3969 * We only virtual copy managed pages.
3971 if ((ptetemp & ATTR_SW_MANAGED) == 0)
3974 if (dstmpte != NULL) {
3975 KASSERT(dstmpte->pindex == pmap_l2_pindex(addr),
3976 ("dstmpte pindex/addr mismatch"));
3977 dstmpte->wire_count++;
3978 } else if ((dstmpte = pmap_alloc_l3(dst_pmap, addr,
3981 dst_pte = (pt_entry_t *)
3982 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dstmpte));
3983 dst_pte = &dst_pte[pmap_l3_index(addr)];
3984 if (pmap_load(dst_pte) == 0 &&
3985 pmap_try_insert_pv_entry(dst_pmap, addr,
3986 PHYS_TO_VM_PAGE(ptetemp & ~ATTR_MASK), &lock)) {
3988 * Clear the wired, modified, and accessed
3989 * (referenced) bits during the copy.
3991 mask = ATTR_AF | ATTR_SW_WIRED;
3993 if ((ptetemp & ATTR_SW_DBM) != 0)
3994 nbits |= ATTR_AP_RW_BIT;
3995 pmap_store(dst_pte, (ptetemp & ~mask) | nbits);
3996 pmap_resident_count_inc(dst_pmap, 1);
3999 if (pmap_unwire_l3(dst_pmap, addr, dstmpte,
4002 * Although "addr" is not mapped,
4003 * the TLB could nonetheless have
4004 * intermediate entries that refer
4005 * to the freed page table pages.
4006 * Invalidate those entries.
4008 * XXX redundant invalidation
4010 pmap_invalidate_page(dst_pmap, addr);
4011 vm_page_free_pages_toq(&free, true);
4015 /* Have we copied all of the valid mappings? */
4016 if (dstmpte->wire_count >= srcmpte->wire_count)
4022 * XXX This barrier may not be needed because the destination pmap is
4029 PMAP_UNLOCK(src_pmap);
4030 PMAP_UNLOCK(dst_pmap);
4034 * pmap_zero_page zeros the specified hardware page by mapping
4035 * the page into KVM and using bzero to clear its contents.
4038 pmap_zero_page(vm_page_t m)
4040 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
4042 pagezero((void *)va);
4046 * pmap_zero_page_area zeros the specified hardware page by mapping
4047 * the page into KVM and using bzero to clear its contents.
4049 * off and size may not cover an area beyond a single hardware page.
4052 pmap_zero_page_area(vm_page_t m, int off, int size)
4054 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
4056 if (off == 0 && size == PAGE_SIZE)
4057 pagezero((void *)va);
4059 bzero((char *)va + off, size);
4063 * pmap_copy_page copies the specified (machine independent)
4064 * page by mapping the page into virtual memory and using
4065 * bcopy to copy the page, one machine dependent page at a
4069 pmap_copy_page(vm_page_t msrc, vm_page_t mdst)
4071 vm_offset_t src = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(msrc));
4072 vm_offset_t dst = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mdst));
4074 pagecopy((void *)src, (void *)dst);
4077 int unmapped_buf_allowed = 1;
4080 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
4081 vm_offset_t b_offset, int xfersize)
4085 vm_paddr_t p_a, p_b;
4086 vm_offset_t a_pg_offset, b_pg_offset;
4089 while (xfersize > 0) {
4090 a_pg_offset = a_offset & PAGE_MASK;
4091 m_a = ma[a_offset >> PAGE_SHIFT];
4092 p_a = m_a->phys_addr;
4093 b_pg_offset = b_offset & PAGE_MASK;
4094 m_b = mb[b_offset >> PAGE_SHIFT];
4095 p_b = m_b->phys_addr;
4096 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
4097 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
4098 if (__predict_false(!PHYS_IN_DMAP(p_a))) {
4099 panic("!DMAP a %lx", p_a);
4101 a_cp = (char *)PHYS_TO_DMAP(p_a) + a_pg_offset;
4103 if (__predict_false(!PHYS_IN_DMAP(p_b))) {
4104 panic("!DMAP b %lx", p_b);
4106 b_cp = (char *)PHYS_TO_DMAP(p_b) + b_pg_offset;
4108 bcopy(a_cp, b_cp, cnt);
4116 pmap_quick_enter_page(vm_page_t m)
4119 return (PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)));
4123 pmap_quick_remove_page(vm_offset_t addr)
4128 * Returns true if the pmap's pv is one of the first
4129 * 16 pvs linked to from this page. This count may
4130 * be changed upwards or downwards in the future; it
4131 * is only necessary that true be returned for a small
4132 * subset of pmaps for proper page aging.
4135 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
4137 struct md_page *pvh;
4138 struct rwlock *lock;
4143 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4144 ("pmap_page_exists_quick: page %p is not managed", m));
4146 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
4148 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4149 if (PV_PMAP(pv) == pmap) {
4157 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
4158 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4159 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4160 if (PV_PMAP(pv) == pmap) {
4174 * pmap_page_wired_mappings:
4176 * Return the number of managed mappings to the given physical page
4180 pmap_page_wired_mappings(vm_page_t m)
4182 struct rwlock *lock;
4183 struct md_page *pvh;
4187 int count, lvl, md_gen, pvh_gen;
4189 if ((m->oflags & VPO_UNMANAGED) != 0)
4191 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
4195 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4197 if (!PMAP_TRYLOCK(pmap)) {
4198 md_gen = m->md.pv_gen;
4202 if (md_gen != m->md.pv_gen) {
4207 pte = pmap_pte(pmap, pv->pv_va, &lvl);
4208 if (pte != NULL && (pmap_load(pte) & ATTR_SW_WIRED) != 0)
4212 if ((m->flags & PG_FICTITIOUS) == 0) {
4213 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4214 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4216 if (!PMAP_TRYLOCK(pmap)) {
4217 md_gen = m->md.pv_gen;
4218 pvh_gen = pvh->pv_gen;
4222 if (md_gen != m->md.pv_gen ||
4223 pvh_gen != pvh->pv_gen) {
4228 pte = pmap_pte(pmap, pv->pv_va, &lvl);
4230 (pmap_load(pte) & ATTR_SW_WIRED) != 0)
4240 * Returns true if the given page is mapped individually or as part of
4241 * a 2mpage. Otherwise, returns false.
4244 pmap_page_is_mapped(vm_page_t m)
4246 struct rwlock *lock;
4249 if ((m->oflags & VPO_UNMANAGED) != 0)
4251 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
4253 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
4254 ((m->flags & PG_FICTITIOUS) == 0 &&
4255 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
4261 * Destroy all managed, non-wired mappings in the given user-space
4262 * pmap. This pmap cannot be active on any processor besides the
4265 * This function cannot be applied to the kernel pmap. Moreover, it
4266 * is not intended for general use. It is only to be used during
4267 * process termination. Consequently, it can be implemented in ways
4268 * that make it faster than pmap_remove(). First, it can more quickly
4269 * destroy mappings by iterating over the pmap's collection of PV
4270 * entries, rather than searching the page table. Second, it doesn't
4271 * have to test and clear the page table entries atomically, because
4272 * no processor is currently accessing the user address space. In
4273 * particular, a page table entry's dirty bit won't change state once
4274 * this function starts.
4277 pmap_remove_pages(pmap_t pmap)
4280 pt_entry_t *pte, tpte;
4281 struct spglist free;
4282 vm_page_t m, ml3, mt;
4284 struct md_page *pvh;
4285 struct pv_chunk *pc, *npc;
4286 struct rwlock *lock;
4288 uint64_t inuse, bitmask;
4289 int allfree, field, freed, idx, lvl;
4296 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
4299 for (field = 0; field < _NPCM; field++) {
4300 inuse = ~pc->pc_map[field] & pc_freemask[field];
4301 while (inuse != 0) {
4302 bit = ffsl(inuse) - 1;
4303 bitmask = 1UL << bit;
4304 idx = field * 64 + bit;
4305 pv = &pc->pc_pventry[idx];
4308 pde = pmap_pde(pmap, pv->pv_va, &lvl);
4309 KASSERT(pde != NULL,
4310 ("Attempting to remove an unmapped page"));
4314 pte = pmap_l1_to_l2(pde, pv->pv_va);
4315 tpte = pmap_load(pte);
4316 KASSERT((tpte & ATTR_DESCR_MASK) ==
4318 ("Attempting to remove an invalid "
4319 "block: %lx", tpte));
4320 tpte = pmap_load(pte);
4323 pte = pmap_l2_to_l3(pde, pv->pv_va);
4324 tpte = pmap_load(pte);
4325 KASSERT((tpte & ATTR_DESCR_MASK) ==
4327 ("Attempting to remove an invalid "
4328 "page: %lx", tpte));
4332 "Invalid page directory level: %d",
4337 * We cannot remove wired pages from a process' mapping at this time
4339 if (tpte & ATTR_SW_WIRED) {
4344 pa = tpte & ~ATTR_MASK;
4346 m = PHYS_TO_VM_PAGE(pa);
4347 KASSERT(m->phys_addr == pa,
4348 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
4349 m, (uintmax_t)m->phys_addr,
4352 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
4353 m < &vm_page_array[vm_page_array_size],
4354 ("pmap_remove_pages: bad pte %#jx",
4358 * Because this pmap is not active on other
4359 * processors, the dirty bit cannot have
4360 * changed state since we last loaded pte.
4365 * Update the vm_page_t clean/reference bits.
4367 if (pmap_pte_dirty(tpte)) {
4370 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
4379 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(&lock, m);
4382 pc->pc_map[field] |= bitmask;
4385 pmap_resident_count_dec(pmap,
4386 L2_SIZE / PAGE_SIZE);
4387 pvh = pa_to_pvh(tpte & ~ATTR_MASK);
4388 TAILQ_REMOVE(&pvh->pv_list, pv,pv_next);
4390 if (TAILQ_EMPTY(&pvh->pv_list)) {
4391 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
4392 if ((mt->aflags & PGA_WRITEABLE) != 0 &&
4393 TAILQ_EMPTY(&mt->md.pv_list))
4394 vm_page_aflag_clear(mt, PGA_WRITEABLE);
4396 ml3 = pmap_remove_pt_page(pmap,
4399 KASSERT(ml3->valid == VM_PAGE_BITS_ALL,
4400 ("pmap_remove_pages: l3 page not promoted"));
4401 pmap_resident_count_dec(pmap,1);
4402 KASSERT(ml3->wire_count == NL3PG,
4403 ("pmap_remove_pages: l3 page wire count error"));
4404 ml3->wire_count = 0;
4405 pmap_add_delayed_free_list(ml3,
4410 pmap_resident_count_dec(pmap, 1);
4411 TAILQ_REMOVE(&m->md.pv_list, pv,
4414 if ((m->aflags & PGA_WRITEABLE) != 0 &&
4415 TAILQ_EMPTY(&m->md.pv_list) &&
4416 (m->flags & PG_FICTITIOUS) == 0) {
4418 VM_PAGE_TO_PHYS(m));
4419 if (TAILQ_EMPTY(&pvh->pv_list))
4420 vm_page_aflag_clear(m,
4425 pmap_unuse_pt(pmap, pv->pv_va, pmap_load(pde),
4430 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
4431 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
4432 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
4434 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4438 pmap_invalidate_all(pmap);
4442 vm_page_free_pages_toq(&free, true);
4446 * This is used to check if a page has been accessed or modified. As we
4447 * don't have a bit to see if it has been modified we have to assume it
4448 * has been if the page is read/write.
4451 pmap_page_test_mappings(vm_page_t m, boolean_t accessed, boolean_t modified)
4453 struct rwlock *lock;
4455 struct md_page *pvh;
4456 pt_entry_t *pte, mask, value;
4458 int lvl, md_gen, pvh_gen;
4462 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
4465 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4467 if (!PMAP_TRYLOCK(pmap)) {
4468 md_gen = m->md.pv_gen;
4472 if (md_gen != m->md.pv_gen) {
4477 pte = pmap_pte(pmap, pv->pv_va, &lvl);
4479 ("pmap_page_test_mappings: Invalid level %d", lvl));
4483 mask |= ATTR_AP_RW_BIT;
4484 value |= ATTR_AP(ATTR_AP_RW);
4487 mask |= ATTR_AF | ATTR_DESCR_MASK;
4488 value |= ATTR_AF | L3_PAGE;
4490 rv = (pmap_load(pte) & mask) == value;
4495 if ((m->flags & PG_FICTITIOUS) == 0) {
4496 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4497 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4499 if (!PMAP_TRYLOCK(pmap)) {
4500 md_gen = m->md.pv_gen;
4501 pvh_gen = pvh->pv_gen;
4505 if (md_gen != m->md.pv_gen ||
4506 pvh_gen != pvh->pv_gen) {
4511 pte = pmap_pte(pmap, pv->pv_va, &lvl);
4513 ("pmap_page_test_mappings: Invalid level %d", lvl));
4517 mask |= ATTR_AP_RW_BIT;
4518 value |= ATTR_AP(ATTR_AP_RW);
4521 mask |= ATTR_AF | ATTR_DESCR_MASK;
4522 value |= ATTR_AF | L2_BLOCK;
4524 rv = (pmap_load(pte) & mask) == value;
4538 * Return whether or not the specified physical page was modified
4539 * in any physical maps.
4542 pmap_is_modified(vm_page_t m)
4545 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4546 ("pmap_is_modified: page %p is not managed", m));
4549 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
4550 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
4551 * is clear, no PTEs can have PG_M set.
4553 VM_OBJECT_ASSERT_WLOCKED(m->object);
4554 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
4556 return (pmap_page_test_mappings(m, FALSE, TRUE));
4560 * pmap_is_prefaultable:
4562 * Return whether or not the specified virtual address is eligible
4566 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
4574 pte = pmap_pte(pmap, addr, &lvl);
4575 if (pte != NULL && pmap_load(pte) != 0) {
4583 * pmap_is_referenced:
4585 * Return whether or not the specified physical page was referenced
4586 * in any physical maps.
4589 pmap_is_referenced(vm_page_t m)
4592 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4593 ("pmap_is_referenced: page %p is not managed", m));
4594 return (pmap_page_test_mappings(m, TRUE, FALSE));
4598 * Clear the write and modified bits in each of the given page's mappings.
4601 pmap_remove_write(vm_page_t m)
4603 struct md_page *pvh;
4605 struct rwlock *lock;
4606 pv_entry_t next_pv, pv;
4607 pt_entry_t oldpte, *pte;
4609 int lvl, md_gen, pvh_gen;
4611 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4612 ("pmap_remove_write: page %p is not managed", m));
4615 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
4616 * set by another thread while the object is locked. Thus,
4617 * if PGA_WRITEABLE is clear, no page table entries need updating.
4619 VM_OBJECT_ASSERT_WLOCKED(m->object);
4620 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
4622 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
4623 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
4624 pa_to_pvh(VM_PAGE_TO_PHYS(m));
4627 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
4629 if (!PMAP_TRYLOCK(pmap)) {
4630 pvh_gen = pvh->pv_gen;
4634 if (pvh_gen != pvh->pv_gen) {
4641 pte = pmap_pte(pmap, pv->pv_va, &lvl);
4642 if ((pmap_load(pte) & ATTR_SW_DBM) != 0)
4643 (void)pmap_demote_l2_locked(pmap, pte, va, &lock);
4644 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
4645 ("inconsistent pv lock %p %p for page %p",
4646 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
4649 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4651 if (!PMAP_TRYLOCK(pmap)) {
4652 pvh_gen = pvh->pv_gen;
4653 md_gen = m->md.pv_gen;
4657 if (pvh_gen != pvh->pv_gen ||
4658 md_gen != m->md.pv_gen) {
4664 pte = pmap_pte(pmap, pv->pv_va, &lvl);
4665 oldpte = pmap_load(pte);
4667 if ((oldpte & ATTR_SW_DBM) != 0) {
4668 if (!atomic_fcmpset_long(pte, &oldpte,
4669 (oldpte | ATTR_AP_RW_BIT) & ~ATTR_SW_DBM))
4671 if ((oldpte & ATTR_AP_RW_BIT) ==
4672 ATTR_AP(ATTR_AP_RW))
4674 pmap_invalidate_page(pmap, pv->pv_va);
4679 vm_page_aflag_clear(m, PGA_WRITEABLE);
4683 * pmap_ts_referenced:
4685 * Return a count of reference bits for a page, clearing those bits.
4686 * It is not necessary for every reference bit to be cleared, but it
4687 * is necessary that 0 only be returned when there are truly no
4688 * reference bits set.
4690 * As an optimization, update the page's dirty field if a modified bit is
4691 * found while counting reference bits. This opportunistic update can be
4692 * performed at low cost and can eliminate the need for some future calls
4693 * to pmap_is_modified(). However, since this function stops after
4694 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
4695 * dirty pages. Those dirty pages will only be detected by a future call
4696 * to pmap_is_modified().
4699 pmap_ts_referenced(vm_page_t m)
4701 struct md_page *pvh;
4704 struct rwlock *lock;
4705 pd_entry_t *pde, tpde;
4706 pt_entry_t *pte, tpte;
4709 int cleared, lvl, md_gen, not_cleared, pvh_gen;
4710 struct spglist free;
4712 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4713 ("pmap_ts_referenced: page %p is not managed", m));
4716 pa = VM_PAGE_TO_PHYS(m);
4717 lock = PHYS_TO_PV_LIST_LOCK(pa);
4718 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : pa_to_pvh(pa);
4722 if ((pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
4723 goto small_mappings;
4729 if (!PMAP_TRYLOCK(pmap)) {
4730 pvh_gen = pvh->pv_gen;
4734 if (pvh_gen != pvh->pv_gen) {
4740 pde = pmap_pde(pmap, pv->pv_va, &lvl);
4741 KASSERT(pde != NULL, ("pmap_ts_referenced: no l1 table found"));
4743 ("pmap_ts_referenced: invalid pde level %d", lvl));
4744 tpde = pmap_load(pde);
4745 KASSERT((tpde & ATTR_DESCR_MASK) == L1_TABLE,
4746 ("pmap_ts_referenced: found an invalid l1 table"));
4747 pte = pmap_l1_to_l2(pde, pv->pv_va);
4748 tpte = pmap_load(pte);
4749 if (pmap_pte_dirty(tpte)) {
4751 * Although "tpte" is mapping a 2MB page, because
4752 * this function is called at a 4KB page granularity,
4753 * we only update the 4KB page under test.
4758 if ((tpte & ATTR_AF) != 0) {
4760 * Since this reference bit is shared by 512 4KB pages,
4761 * it should not be cleared every time it is tested.
4762 * Apply a simple "hash" function on the physical page
4763 * number, the virtual superpage number, and the pmap
4764 * address to select one 4KB page out of the 512 on
4765 * which testing the reference bit will result in
4766 * clearing that reference bit. This function is
4767 * designed to avoid the selection of the same 4KB page
4768 * for every 2MB page mapping.
4770 * On demotion, a mapping that hasn't been referenced
4771 * is simply destroyed. To avoid the possibility of a
4772 * subsequent page fault on a demoted wired mapping,
4773 * always leave its reference bit set. Moreover,
4774 * since the superpage is wired, the current state of
4775 * its reference bit won't affect page replacement.
4777 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> L2_SHIFT) ^
4778 (uintptr_t)pmap) & (Ln_ENTRIES - 1)) == 0 &&
4779 (tpte & ATTR_SW_WIRED) == 0) {
4780 pmap_clear_bits(pte, ATTR_AF);
4781 pmap_invalidate_page(pmap, pv->pv_va);
4787 /* Rotate the PV list if it has more than one entry. */
4788 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
4789 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
4790 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
4793 if (cleared + not_cleared >= PMAP_TS_REFERENCED_MAX)
4795 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
4797 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
4804 if (!PMAP_TRYLOCK(pmap)) {
4805 pvh_gen = pvh->pv_gen;
4806 md_gen = m->md.pv_gen;
4810 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
4815 pde = pmap_pde(pmap, pv->pv_va, &lvl);
4816 KASSERT(pde != NULL, ("pmap_ts_referenced: no l2 table found"));
4818 ("pmap_ts_referenced: invalid pde level %d", lvl));
4819 tpde = pmap_load(pde);
4820 KASSERT((tpde & ATTR_DESCR_MASK) == L2_TABLE,
4821 ("pmap_ts_referenced: found an invalid l2 table"));
4822 pte = pmap_l2_to_l3(pde, pv->pv_va);
4823 tpte = pmap_load(pte);
4824 if (pmap_pte_dirty(tpte))
4826 if ((tpte & ATTR_AF) != 0) {
4827 if ((tpte & ATTR_SW_WIRED) == 0) {
4828 pmap_clear_bits(pte, ATTR_AF);
4829 pmap_invalidate_page(pmap, pv->pv_va);
4835 /* Rotate the PV list if it has more than one entry. */
4836 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
4837 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4838 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4841 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && cleared +
4842 not_cleared < PMAP_TS_REFERENCED_MAX);
4845 vm_page_free_pages_toq(&free, true);
4846 return (cleared + not_cleared);
4850 * Apply the given advice to the specified range of addresses within the
4851 * given pmap. Depending on the advice, clear the referenced and/or
4852 * modified flags in each mapping and set the mapped page's dirty field.
4855 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
4857 struct rwlock *lock;
4858 vm_offset_t va, va_next;
4860 pd_entry_t *l0, *l1, *l2, oldl2;
4861 pt_entry_t *l3, oldl3;
4863 if (advice != MADV_DONTNEED && advice != MADV_FREE)
4867 for (; sva < eva; sva = va_next) {
4868 l0 = pmap_l0(pmap, sva);
4869 if (pmap_load(l0) == 0) {
4870 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
4875 l1 = pmap_l0_to_l1(l0, sva);
4876 if (pmap_load(l1) == 0) {
4877 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
4882 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
4885 l2 = pmap_l1_to_l2(l1, sva);
4886 oldl2 = pmap_load(l2);
4889 if ((oldl2 & ATTR_DESCR_MASK) == L2_BLOCK) {
4890 if ((oldl2 & ATTR_SW_MANAGED) == 0)
4893 if (!pmap_demote_l2_locked(pmap, l2, sva, &lock)) {
4898 * The 2MB page mapping was destroyed.
4904 * Unless the page mappings are wired, remove the
4905 * mapping to a single page so that a subsequent
4906 * access may repromote. Choosing the last page
4907 * within the address range [sva, min(va_next, eva))
4908 * generally results in more repromotions. Since the
4909 * underlying page table page is fully populated, this
4910 * removal never frees a page table page.
4912 if ((oldl2 & ATTR_SW_WIRED) == 0) {
4918 ("pmap_advise: no address gap"));
4919 l3 = pmap_l2_to_l3(l2, va);
4920 KASSERT(pmap_load(l3) != 0,
4921 ("pmap_advise: invalid PTE"));
4922 pmap_remove_l3(pmap, l3, va, pmap_load(l2),
4928 KASSERT((pmap_load(l2) & ATTR_DESCR_MASK) == L2_TABLE,
4929 ("pmap_advise: invalid L2 entry after demotion"));
4933 for (l3 = pmap_l2_to_l3(l2, sva); sva != va_next; l3++,
4935 oldl3 = pmap_load(l3);
4936 if ((oldl3 & (ATTR_SW_MANAGED | ATTR_DESCR_MASK)) !=
4937 (ATTR_SW_MANAGED | L3_PAGE))
4939 else if (pmap_pte_dirty(oldl3)) {
4940 if (advice == MADV_DONTNEED) {
4942 * Future calls to pmap_is_modified()
4943 * can be avoided by making the page
4946 m = PHYS_TO_VM_PAGE(oldl3 & ~ATTR_MASK);
4949 while (!atomic_fcmpset_long(l3, &oldl3,
4950 (oldl3 & ~ATTR_AF) | ATTR_AP(ATTR_AP_RO)))
4952 } else if ((oldl3 & ATTR_AF) != 0)
4953 pmap_clear_bits(l3, ATTR_AF);
4960 if (va != va_next) {
4961 pmap_invalidate_range(pmap, va, sva);
4966 pmap_invalidate_range(pmap, va, sva);
4972 * Clear the modify bits on the specified physical page.
4975 pmap_clear_modify(vm_page_t m)
4977 struct md_page *pvh;
4978 struct rwlock *lock;
4980 pv_entry_t next_pv, pv;
4981 pd_entry_t *l2, oldl2;
4982 pt_entry_t *l3, oldl3;
4984 int md_gen, pvh_gen;
4986 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4987 ("pmap_clear_modify: page %p is not managed", m));
4988 VM_OBJECT_ASSERT_WLOCKED(m->object);
4989 KASSERT(!vm_page_xbusied(m),
4990 ("pmap_clear_modify: page %p is exclusive busied", m));
4993 * If the page is not PGA_WRITEABLE, then no PTEs can have ATTR_SW_DBM
4994 * set. If the object containing the page is locked and the page is not
4995 * exclusive busied, then PGA_WRITEABLE cannot be concurrently set.
4997 if ((m->aflags & PGA_WRITEABLE) == 0)
4999 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
5000 pa_to_pvh(VM_PAGE_TO_PHYS(m));
5001 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5004 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
5006 if (!PMAP_TRYLOCK(pmap)) {
5007 pvh_gen = pvh->pv_gen;
5011 if (pvh_gen != pvh->pv_gen) {
5017 l2 = pmap_l2(pmap, va);
5018 oldl2 = pmap_load(l2);
5019 if ((oldl2 & ATTR_SW_DBM) != 0) {
5020 if (pmap_demote_l2_locked(pmap, l2, va, &lock)) {
5021 if ((oldl2 & ATTR_SW_WIRED) == 0) {
5023 * Write protect the mapping to a
5024 * single page so that a subsequent
5025 * write access may repromote.
5027 va += VM_PAGE_TO_PHYS(m) -
5028 (oldl2 & ~ATTR_MASK);
5029 l3 = pmap_l2_to_l3(l2, va);
5030 oldl3 = pmap_load(l3);
5031 if (pmap_l3_valid(oldl3)) {
5032 while (!atomic_fcmpset_long(l3,
5033 &oldl3, (oldl3 & ~ATTR_SW_DBM) |
5034 ATTR_AP(ATTR_AP_RO)))
5037 pmap_invalidate_page(pmap, va);
5044 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5046 if (!PMAP_TRYLOCK(pmap)) {
5047 md_gen = m->md.pv_gen;
5048 pvh_gen = pvh->pv_gen;
5052 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
5057 l2 = pmap_l2(pmap, pv->pv_va);
5058 l3 = pmap_l2_to_l3(l2, pv->pv_va);
5059 oldl3 = pmap_load(l3);
5060 if (pmap_l3_valid(oldl3) &&
5061 (oldl3 & (ATTR_AP_RW_BIT | ATTR_SW_DBM)) == ATTR_SW_DBM) {
5062 pmap_set_bits(l3, ATTR_AP(ATTR_AP_RO));
5063 pmap_invalidate_page(pmap, pv->pv_va);
5071 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
5073 struct pmap_preinit_mapping *ppim;
5074 vm_offset_t va, offset;
5077 int i, lvl, l2_blocks, free_l2_count, start_idx;
5079 if (!vm_initialized) {
5081 * No L3 ptables so map entire L2 blocks where start VA is:
5082 * preinit_map_va + start_idx * L2_SIZE
5083 * There may be duplicate mappings (multiple VA -> same PA) but
5084 * ARM64 dcache is always PIPT so that's acceptable.
5089 /* Calculate how many L2 blocks are needed for the mapping */
5090 l2_blocks = (roundup2(pa + size, L2_SIZE) -
5091 rounddown2(pa, L2_SIZE)) >> L2_SHIFT;
5093 offset = pa & L2_OFFSET;
5095 if (preinit_map_va == 0)
5098 /* Map 2MiB L2 blocks from reserved VA space */
5102 /* Find enough free contiguous VA space */
5103 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5104 ppim = pmap_preinit_mapping + i;
5105 if (free_l2_count > 0 && ppim->pa != 0) {
5106 /* Not enough space here */
5112 if (ppim->pa == 0) {
5114 if (start_idx == -1)
5117 if (free_l2_count == l2_blocks)
5121 if (free_l2_count != l2_blocks)
5122 panic("%s: too many preinit mappings", __func__);
5124 va = preinit_map_va + (start_idx * L2_SIZE);
5125 for (i = start_idx; i < start_idx + l2_blocks; i++) {
5126 /* Mark entries as allocated */
5127 ppim = pmap_preinit_mapping + i;
5129 ppim->va = va + offset;
5134 pa = rounddown2(pa, L2_SIZE);
5135 for (i = 0; i < l2_blocks; i++) {
5136 pde = pmap_pde(kernel_pmap, va, &lvl);
5137 KASSERT(pde != NULL,
5138 ("pmap_mapbios: Invalid page entry, va: 0x%lx",
5141 ("pmap_mapbios: Invalid level %d", lvl));
5143 /* Insert L2_BLOCK */
5144 l2 = pmap_l1_to_l2(pde, va);
5146 pa | ATTR_DEFAULT | ATTR_XN |
5147 ATTR_IDX(CACHED_MEMORY) | L2_BLOCK);
5152 pmap_invalidate_all(kernel_pmap);
5154 va = preinit_map_va + (start_idx * L2_SIZE);
5157 /* kva_alloc may be used to map the pages */
5158 offset = pa & PAGE_MASK;
5159 size = round_page(offset + size);
5161 va = kva_alloc(size);
5163 panic("%s: Couldn't allocate KVA", __func__);
5165 pde = pmap_pde(kernel_pmap, va, &lvl);
5166 KASSERT(lvl == 2, ("pmap_mapbios: Invalid level %d", lvl));
5168 /* L3 table is linked */
5169 va = trunc_page(va);
5170 pa = trunc_page(pa);
5171 pmap_kenter(va, size, pa, CACHED_MEMORY);
5174 return ((void *)(va + offset));
5178 pmap_unmapbios(vm_offset_t va, vm_size_t size)
5180 struct pmap_preinit_mapping *ppim;
5181 vm_offset_t offset, tmpsize, va_trunc;
5184 int i, lvl, l2_blocks, block;
5188 (roundup2(va + size, L2_SIZE) - rounddown2(va, L2_SIZE)) >> L2_SHIFT;
5189 KASSERT(l2_blocks > 0, ("pmap_unmapbios: invalid size %lx", size));
5191 /* Remove preinit mapping */
5192 preinit_map = false;
5194 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5195 ppim = pmap_preinit_mapping + i;
5196 if (ppim->va == va) {
5197 KASSERT(ppim->size == size,
5198 ("pmap_unmapbios: size mismatch"));
5203 offset = block * L2_SIZE;
5204 va_trunc = rounddown2(va, L2_SIZE) + offset;
5206 /* Remove L2_BLOCK */
5207 pde = pmap_pde(kernel_pmap, va_trunc, &lvl);
5208 KASSERT(pde != NULL,
5209 ("pmap_unmapbios: Invalid page entry, va: 0x%lx",
5211 l2 = pmap_l1_to_l2(pde, va_trunc);
5214 if (block == (l2_blocks - 1))
5220 pmap_invalidate_all(kernel_pmap);
5224 /* Unmap the pages reserved with kva_alloc. */
5225 if (vm_initialized) {
5226 offset = va & PAGE_MASK;
5227 size = round_page(offset + size);
5228 va = trunc_page(va);
5230 pde = pmap_pde(kernel_pmap, va, &lvl);
5231 KASSERT(pde != NULL,
5232 ("pmap_unmapbios: Invalid page entry, va: 0x%lx", va));
5233 KASSERT(lvl == 2, ("pmap_unmapbios: Invalid level %d", lvl));
5235 /* Unmap and invalidate the pages */
5236 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
5237 pmap_kremove(va + tmpsize);
5244 * Sets the memory attribute for the specified page.
5247 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
5250 m->md.pv_memattr = ma;
5253 * If "m" is a normal page, update its direct mapping. This update
5254 * can be relied upon to perform any cache operations that are
5255 * required for data coherence.
5257 if ((m->flags & PG_FICTITIOUS) == 0 &&
5258 pmap_change_attr(PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)), PAGE_SIZE,
5259 m->md.pv_memattr) != 0)
5260 panic("memory attribute change on the direct map failed");
5264 * Changes the specified virtual address range's memory type to that given by
5265 * the parameter "mode". The specified virtual address range must be
5266 * completely contained within either the direct map or the kernel map. If
5267 * the virtual address range is contained within the kernel map, then the
5268 * memory type for each of the corresponding ranges of the direct map is also
5269 * changed. (The corresponding ranges of the direct map are those ranges that
5270 * map the same physical pages as the specified virtual address range.) These
5271 * changes to the direct map are necessary because Intel describes the
5272 * behavior of their processors as "undefined" if two or more mappings to the
5273 * same physical page have different memory types.
5275 * Returns zero if the change completed successfully, and either EINVAL or
5276 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
5277 * of the virtual address range was not mapped, and ENOMEM is returned if
5278 * there was insufficient memory available to complete the change. In the
5279 * latter case, the memory type may have been changed on some part of the
5280 * virtual address range or the direct map.
5283 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
5287 PMAP_LOCK(kernel_pmap);
5288 error = pmap_change_attr_locked(va, size, mode);
5289 PMAP_UNLOCK(kernel_pmap);
5294 pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode)
5296 vm_offset_t base, offset, tmpva;
5297 pt_entry_t l3, *pte, *newpte;
5300 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
5301 base = trunc_page(va);
5302 offset = va & PAGE_MASK;
5303 size = round_page(offset + size);
5305 if (!VIRT_IN_DMAP(base))
5308 for (tmpva = base; tmpva < base + size; ) {
5309 pte = pmap_pte(kernel_pmap, tmpva, &lvl);
5313 if ((pmap_load(pte) & ATTR_IDX_MASK) == ATTR_IDX(mode)) {
5315 * We already have the correct attribute,
5316 * ignore this entry.
5320 panic("Invalid DMAP table level: %d\n", lvl);
5322 tmpva = (tmpva & ~L1_OFFSET) + L1_SIZE;
5325 tmpva = (tmpva & ~L2_OFFSET) + L2_SIZE;
5333 * Split the entry to an level 3 table, then
5334 * set the new attribute.
5338 panic("Invalid DMAP table level: %d\n", lvl);
5340 newpte = pmap_demote_l1(kernel_pmap, pte,
5341 tmpva & ~L1_OFFSET);
5344 pte = pmap_l1_to_l2(pte, tmpva);
5346 newpte = pmap_demote_l2(kernel_pmap, pte,
5350 pte = pmap_l2_to_l3(pte, tmpva);
5352 /* Update the entry */
5353 l3 = pmap_load(pte);
5354 l3 &= ~ATTR_IDX_MASK;
5355 l3 |= ATTR_IDX(mode);
5356 if (mode == DEVICE_MEMORY)
5359 pmap_update_entry(kernel_pmap, pte, l3, tmpva,
5363 * If moving to a non-cacheable entry flush
5366 if (mode == VM_MEMATTR_UNCACHEABLE)
5367 cpu_dcache_wbinv_range(tmpva, L3_SIZE);
5379 * Create an L2 table to map all addresses within an L1 mapping.
5382 pmap_demote_l1(pmap_t pmap, pt_entry_t *l1, vm_offset_t va)
5384 pt_entry_t *l2, newl2, oldl1;
5386 vm_paddr_t l2phys, phys;
5390 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5391 oldl1 = pmap_load(l1);
5392 KASSERT((oldl1 & ATTR_DESCR_MASK) == L1_BLOCK,
5393 ("pmap_demote_l1: Demoting a non-block entry"));
5394 KASSERT((va & L1_OFFSET) == 0,
5395 ("pmap_demote_l1: Invalid virtual address %#lx", va));
5396 KASSERT((oldl1 & ATTR_SW_MANAGED) == 0,
5397 ("pmap_demote_l1: Level 1 table shouldn't be managed"));
5400 if (va <= (vm_offset_t)l1 && va + L1_SIZE > (vm_offset_t)l1) {
5401 tmpl1 = kva_alloc(PAGE_SIZE);
5406 if ((ml2 = vm_page_alloc(NULL, 0, VM_ALLOC_INTERRUPT |
5407 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
5408 CTR2(KTR_PMAP, "pmap_demote_l1: failure for va %#lx"
5409 " in pmap %p", va, pmap);
5413 l2phys = VM_PAGE_TO_PHYS(ml2);
5414 l2 = (pt_entry_t *)PHYS_TO_DMAP(l2phys);
5416 /* Address the range points at */
5417 phys = oldl1 & ~ATTR_MASK;
5418 /* The attributed from the old l1 table to be copied */
5419 newl2 = oldl1 & ATTR_MASK;
5421 /* Create the new entries */
5422 for (i = 0; i < Ln_ENTRIES; i++) {
5423 l2[i] = newl2 | phys;
5426 KASSERT(l2[0] == ((oldl1 & ~ATTR_DESCR_MASK) | L2_BLOCK),
5427 ("Invalid l2 page (%lx != %lx)", l2[0],
5428 (oldl1 & ~ATTR_DESCR_MASK) | L2_BLOCK));
5431 pmap_kenter(tmpl1, PAGE_SIZE,
5432 DMAP_TO_PHYS((vm_offset_t)l1) & ~L3_OFFSET, CACHED_MEMORY);
5433 l1 = (pt_entry_t *)(tmpl1 + ((vm_offset_t)l1 & PAGE_MASK));
5436 pmap_update_entry(pmap, l1, l2phys | L1_TABLE, va, PAGE_SIZE);
5439 pmap_kremove(tmpl1);
5440 kva_free(tmpl1, PAGE_SIZE);
5447 pmap_fill_l3(pt_entry_t *firstl3, pt_entry_t newl3)
5451 for (l3 = firstl3; l3 - firstl3 < Ln_ENTRIES; l3++) {
5458 pmap_demote_l2_abort(pmap_t pmap, vm_offset_t va, pt_entry_t *l2,
5459 struct rwlock **lockp)
5461 struct spglist free;
5464 (void)pmap_remove_l2(pmap, l2, va, pmap_load(pmap_l1(pmap, va)), &free,
5466 vm_page_free_pages_toq(&free, true);
5470 * Create an L3 table to map all addresses within an L2 mapping.
5473 pmap_demote_l2_locked(pmap_t pmap, pt_entry_t *l2, vm_offset_t va,
5474 struct rwlock **lockp)
5476 pt_entry_t *l3, newl3, oldl2;
5481 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5483 oldl2 = pmap_load(l2);
5484 KASSERT((oldl2 & ATTR_DESCR_MASK) == L2_BLOCK,
5485 ("pmap_demote_l2: Demoting a non-block entry"));
5489 if (va <= (vm_offset_t)l2 && va + L2_SIZE > (vm_offset_t)l2) {
5490 tmpl2 = kva_alloc(PAGE_SIZE);
5496 * Invalidate the 2MB page mapping and return "failure" if the
5497 * mapping was never accessed.
5499 if ((oldl2 & ATTR_AF) == 0) {
5500 KASSERT((oldl2 & ATTR_SW_WIRED) == 0,
5501 ("pmap_demote_l2: a wired mapping is missing ATTR_AF"));
5502 pmap_demote_l2_abort(pmap, va, l2, lockp);
5503 CTR2(KTR_PMAP, "pmap_demote_l2: failure for va %#lx in pmap %p",
5508 if ((ml3 = pmap_remove_pt_page(pmap, va)) == NULL) {
5509 KASSERT((oldl2 & ATTR_SW_WIRED) == 0,
5510 ("pmap_demote_l2: page table page for a wired mapping"
5514 * If the page table page is missing and the mapping
5515 * is for a kernel address, the mapping must belong to
5516 * the direct map. Page table pages are preallocated
5517 * for every other part of the kernel address space,
5518 * so the direct map region is the only part of the
5519 * kernel address space that must be handled here.
5521 KASSERT(va < VM_MAXUSER_ADDRESS || VIRT_IN_DMAP(va),
5522 ("pmap_demote_l2: No saved mpte for va %#lx", va));
5525 * If the 2MB page mapping belongs to the direct map
5526 * region of the kernel's address space, then the page
5527 * allocation request specifies the highest possible
5528 * priority (VM_ALLOC_INTERRUPT). Otherwise, the
5529 * priority is normal.
5531 ml3 = vm_page_alloc(NULL, pmap_l2_pindex(va),
5532 (VIRT_IN_DMAP(va) ? VM_ALLOC_INTERRUPT : VM_ALLOC_NORMAL) |
5533 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED);
5536 * If the allocation of the new page table page fails,
5537 * invalidate the 2MB page mapping and return "failure".
5540 pmap_demote_l2_abort(pmap, va, l2, lockp);
5541 CTR2(KTR_PMAP, "pmap_demote_l2: failure for va %#lx"
5542 " in pmap %p", va, pmap);
5546 if (va < VM_MAXUSER_ADDRESS) {
5547 ml3->wire_count = NL3PG;
5548 pmap_resident_count_inc(pmap, 1);
5551 l3phys = VM_PAGE_TO_PHYS(ml3);
5552 l3 = (pt_entry_t *)PHYS_TO_DMAP(l3phys);
5553 newl3 = (oldl2 & ~ATTR_DESCR_MASK) | L3_PAGE;
5554 KASSERT((oldl2 & (ATTR_AP_RW_BIT | ATTR_SW_DBM)) !=
5555 (ATTR_AP(ATTR_AP_RO) | ATTR_SW_DBM),
5556 ("pmap_demote_l2: L2 entry is writeable but not dirty"));
5559 * If the page table page is not leftover from an earlier promotion,
5560 * or the mapping attributes have changed, (re)initialize the L3 table.
5562 if (ml3->valid == 0 || (l3[0] & ATTR_MASK) != (newl3 & ATTR_MASK))
5563 pmap_fill_l3(l3, newl3);
5566 * Map the temporary page so we don't lose access to the l2 table.
5569 pmap_kenter(tmpl2, PAGE_SIZE,
5570 DMAP_TO_PHYS((vm_offset_t)l2) & ~L3_OFFSET, CACHED_MEMORY);
5571 l2 = (pt_entry_t *)(tmpl2 + ((vm_offset_t)l2 & PAGE_MASK));
5575 * The spare PV entries must be reserved prior to demoting the
5576 * mapping, that is, prior to changing the PDE. Otherwise, the state
5577 * of the L2 and the PV lists will be inconsistent, which can result
5578 * in reclaim_pv_chunk() attempting to remove a PV entry from the
5579 * wrong PV list and pmap_pv_demote_l2() failing to find the expected
5580 * PV entry for the 2MB page mapping that is being demoted.
5582 if ((oldl2 & ATTR_SW_MANAGED) != 0)
5583 reserve_pv_entries(pmap, Ln_ENTRIES - 1, lockp);
5586 * Pass PAGE_SIZE so that a single TLB invalidation is performed on
5587 * the 2MB page mapping.
5589 pmap_update_entry(pmap, l2, l3phys | L2_TABLE, va, PAGE_SIZE);
5592 * Demote the PV entry.
5594 if ((oldl2 & ATTR_SW_MANAGED) != 0)
5595 pmap_pv_demote_l2(pmap, va, oldl2 & ~ATTR_MASK, lockp);
5597 atomic_add_long(&pmap_l2_demotions, 1);
5598 CTR3(KTR_PMAP, "pmap_demote_l2: success for va %#lx"
5599 " in pmap %p %lx", va, pmap, l3[0]);
5603 pmap_kremove(tmpl2);
5604 kva_free(tmpl2, PAGE_SIZE);
5612 pmap_demote_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t va)
5614 struct rwlock *lock;
5618 l3 = pmap_demote_l2_locked(pmap, l2, va, &lock);
5625 * perform the pmap work for mincore
5628 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
5630 pt_entry_t *pte, tpte;
5631 vm_paddr_t mask, pa;
5638 pte = pmap_pte(pmap, addr, &lvl);
5640 tpte = pmap_load(pte);
5653 panic("pmap_mincore: invalid level %d", lvl);
5656 managed = (tpte & ATTR_SW_MANAGED) != 0;
5657 val = MINCORE_INCORE;
5659 val |= MINCORE_SUPER;
5660 if ((managed && pmap_pte_dirty(tpte)) || (!managed &&
5661 (tpte & ATTR_AP_RW_BIT) == ATTR_AP(ATTR_AP_RW)))
5662 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
5663 if ((tpte & ATTR_AF) == ATTR_AF)
5664 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
5666 pa = (tpte & ~ATTR_MASK) | (addr & mask);
5670 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
5671 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) && managed) {
5672 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
5673 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
5676 PA_UNLOCK_COND(*locked_pa);
5683 pmap_activate(struct thread *td)
5688 pmap = vmspace_pmap(td->td_proc->p_vmspace);
5689 td->td_proc->p_md.md_l0addr = vtophys(pmap->pm_l0);
5691 "msr ttbr0_el1, %0 \n"
5693 : : "r"(td->td_proc->p_md.md_l0addr));
5694 pmap_invalidate_all(pmap);
5699 pmap_switch(struct thread *old, struct thread *new)
5701 pcpu_bp_harden bp_harden;
5704 /* Store the new curthread */
5705 PCPU_SET(curthread, new);
5707 /* And the new pcb */
5709 PCPU_SET(curpcb, pcb);
5712 * TODO: We may need to flush the cache here if switching
5713 * to a user process.
5717 old->td_proc->p_md.md_l0addr != new->td_proc->p_md.md_l0addr) {
5719 /* Switch to the new pmap */
5720 "msr ttbr0_el1, %0 \n"
5723 /* Invalidate the TLB */
5728 : : "r"(new->td_proc->p_md.md_l0addr));
5731 * Stop userspace from training the branch predictor against
5732 * other processes. This will call into a CPU specific
5733 * function that clears the branch predictor state.
5735 bp_harden = PCPU_GET(bp_harden);
5736 if (bp_harden != NULL)
5744 pmap_sync_icache(pmap_t pmap, vm_offset_t va, vm_size_t sz)
5747 if (va >= VM_MIN_KERNEL_ADDRESS) {
5748 cpu_icache_sync_range(va, sz);
5753 /* Find the length of data in this page to flush */
5754 offset = va & PAGE_MASK;
5755 len = imin(PAGE_SIZE - offset, sz);
5758 /* Extract the physical address & find it in the DMAP */
5759 pa = pmap_extract(pmap, va);
5761 cpu_icache_sync_range(PHYS_TO_DMAP(pa), len);
5763 /* Move to the next page */
5766 /* Set the length for the next iteration */
5767 len = imin(PAGE_SIZE, sz);
5773 pmap_fault(pmap_t pmap, uint64_t esr, uint64_t far)
5775 pt_entry_t pte, *ptep;
5782 ec = ESR_ELx_EXCEPTION(esr);
5784 case EXCP_INSN_ABORT_L:
5785 case EXCP_INSN_ABORT:
5786 case EXCP_DATA_ABORT_L:
5787 case EXCP_DATA_ABORT:
5793 /* Data and insn aborts use same encoding for FSC field. */
5794 switch (esr & ISS_DATA_DFSC_MASK) {
5795 case ISS_DATA_DFSC_AFF_L1:
5796 case ISS_DATA_DFSC_AFF_L2:
5797 case ISS_DATA_DFSC_AFF_L3:
5799 ptep = pmap_pte(pmap, far, &lvl);
5801 pmap_set_bits(ptep, ATTR_AF);
5804 * XXXMJ as an optimization we could mark the entry
5805 * dirty if this is a write fault.
5810 case ISS_DATA_DFSC_PF_L1:
5811 case ISS_DATA_DFSC_PF_L2:
5812 case ISS_DATA_DFSC_PF_L3:
5813 if ((ec != EXCP_DATA_ABORT_L && ec != EXCP_DATA_ABORT) ||
5814 (esr & ISS_DATA_WnR) == 0)
5817 ptep = pmap_pte(pmap, far, &lvl);
5819 ((pte = pmap_load(ptep)) & ATTR_SW_DBM) != 0) {
5820 if ((pte & ATTR_AP_RW_BIT) == ATTR_AP(ATTR_AP_RO)) {
5821 pmap_clear_bits(ptep, ATTR_AP_RW_BIT);
5822 pmap_invalidate_page(pmap, far);
5828 case ISS_DATA_DFSC_TF_L0:
5829 case ISS_DATA_DFSC_TF_L1:
5830 case ISS_DATA_DFSC_TF_L2:
5831 case ISS_DATA_DFSC_TF_L3:
5833 /* Ask the MMU to check the address */
5834 intr = intr_disable();
5835 if (pmap == kernel_pmap)
5836 par = arm64_address_translate_s1e1r(far);
5838 par = arm64_address_translate_s1e0r(far);
5843 * If the translation was successful the address was invalid
5844 * due to a break-before-make sequence. We can unlock and
5845 * return success to the trap handler.
5847 if (PAR_SUCCESS(par))
5856 * Increase the starting virtual address of the given mapping if a
5857 * different alignment might result in more superpage mappings.
5860 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
5861 vm_offset_t *addr, vm_size_t size)
5863 vm_offset_t superpage_offset;
5867 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
5868 offset += ptoa(object->pg_color);
5869 superpage_offset = offset & L2_OFFSET;
5870 if (size - ((L2_SIZE - superpage_offset) & L2_OFFSET) < L2_SIZE ||
5871 (*addr & L2_OFFSET) == superpage_offset)
5873 if ((*addr & L2_OFFSET) < superpage_offset)
5874 *addr = (*addr & ~L2_OFFSET) + superpage_offset;
5876 *addr = ((*addr + L2_OFFSET) & ~L2_OFFSET) + superpage_offset;
5880 * Get the kernel virtual address of a set of physical pages. If there are
5881 * physical addresses not covered by the DMAP perform a transient mapping
5882 * that will be removed when calling pmap_unmap_io_transient.
5884 * \param page The pages the caller wishes to obtain the virtual
5885 * address on the kernel memory map.
5886 * \param vaddr On return contains the kernel virtual memory address
5887 * of the pages passed in the page parameter.
5888 * \param count Number of pages passed in.
5889 * \param can_fault TRUE if the thread using the mapped pages can take
5890 * page faults, FALSE otherwise.
5892 * \returns TRUE if the caller must call pmap_unmap_io_transient when
5893 * finished or FALSE otherwise.
5897 pmap_map_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
5898 boolean_t can_fault)
5901 boolean_t needs_mapping;
5905 * Allocate any KVA space that we need, this is done in a separate
5906 * loop to prevent calling vmem_alloc while pinned.
5908 needs_mapping = FALSE;
5909 for (i = 0; i < count; i++) {
5910 paddr = VM_PAGE_TO_PHYS(page[i]);
5911 if (__predict_false(!PHYS_IN_DMAP(paddr))) {
5912 error = vmem_alloc(kernel_arena, PAGE_SIZE,
5913 M_BESTFIT | M_WAITOK, &vaddr[i]);
5914 KASSERT(error == 0, ("vmem_alloc failed: %d", error));
5915 needs_mapping = TRUE;
5917 vaddr[i] = PHYS_TO_DMAP(paddr);
5921 /* Exit early if everything is covered by the DMAP */
5927 for (i = 0; i < count; i++) {
5928 paddr = VM_PAGE_TO_PHYS(page[i]);
5929 if (!PHYS_IN_DMAP(paddr)) {
5931 "pmap_map_io_transient: TODO: Map out of DMAP data");
5935 return (needs_mapping);
5939 pmap_unmap_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
5940 boolean_t can_fault)
5947 for (i = 0; i < count; i++) {
5948 paddr = VM_PAGE_TO_PHYS(page[i]);
5949 if (!PHYS_IN_DMAP(paddr)) {
5950 panic("ARM64TODO: pmap_unmap_io_transient: Unmap data");
5956 pmap_is_valid_memattr(pmap_t pmap __unused, vm_memattr_t mode)
5959 return (mode >= VM_MEMATTR_DEVICE && mode <= VM_MEMATTR_WRITE_THROUGH);