2 * Copyright (c) 1991 Regents of the University of California.
4 * Copyright (c) 1994 John S. Dyson
6 * Copyright (c) 1994 David Greenman
8 * Copyright (c) 2003 Peter Wemm
10 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
11 * All rights reserved.
12 * Copyright (c) 2014 Andrew Turner
13 * All rights reserved.
14 * Copyright (c) 2014-2016 The FreeBSD Foundation
15 * All rights reserved.
17 * This code is derived from software contributed to Berkeley by
18 * the Systems Programming Group of the University of Utah Computer
19 * Science Department and William Jolitz of UUNET Technologies Inc.
21 * This software was developed by Andrew Turner under sponsorship from
22 * the FreeBSD Foundation.
24 * Redistribution and use in source and binary forms, with or without
25 * modification, are permitted provided that the following conditions
27 * 1. Redistributions of source code must retain the above copyright
28 * notice, this list of conditions and the following disclaimer.
29 * 2. Redistributions in binary form must reproduce the above copyright
30 * notice, this list of conditions and the following disclaimer in the
31 * documentation and/or other materials provided with the distribution.
32 * 3. All advertising materials mentioning features or use of this software
33 * must display the following acknowledgement:
34 * This product includes software developed by the University of
35 * California, Berkeley and its contributors.
36 * 4. Neither the name of the University nor the names of its contributors
37 * may be used to endorse or promote products derived from this software
38 * without specific prior written permission.
40 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
41 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
42 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
43 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
44 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
45 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
46 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
47 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
48 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
49 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
52 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
55 * Copyright (c) 2003 Networks Associates Technology, Inc.
56 * All rights reserved.
58 * This software was developed for the FreeBSD Project by Jake Burkholder,
59 * Safeport Network Services, and Network Associates Laboratories, the
60 * Security Research Division of Network Associates, Inc. under
61 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
62 * CHATS research program.
64 * Redistribution and use in source and binary forms, with or without
65 * modification, are permitted provided that the following conditions
67 * 1. Redistributions of source code must retain the above copyright
68 * notice, this list of conditions and the following disclaimer.
69 * 2. Redistributions in binary form must reproduce the above copyright
70 * notice, this list of conditions and the following disclaimer in the
71 * documentation and/or other materials provided with the distribution.
73 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
74 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
77 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
78 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
79 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
80 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
81 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
82 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
86 #include <sys/cdefs.h>
87 __FBSDID("$FreeBSD$");
90 * Manages physical address maps.
92 * Since the information managed by this module is
93 * also stored by the logical address mapping module,
94 * this module may throw away valid virtual-to-physical
95 * mappings at almost any time. However, invalidations
96 * of virtual-to-physical mappings must be done as
99 * In order to cope with hardware architectures which
100 * make virtual-to-physical map invalidates expensive,
101 * this module may delay invalidate or reduced protection
102 * operations until such time as they are actually
103 * necessary. This module is given full information as
104 * to which processors are currently using which maps,
105 * and to when physical maps must be made correct.
110 #include <sys/param.h>
111 #include <sys/bitstring.h>
113 #include <sys/systm.h>
114 #include <sys/kernel.h>
116 #include <sys/limits.h>
117 #include <sys/lock.h>
118 #include <sys/malloc.h>
119 #include <sys/mman.h>
120 #include <sys/msgbuf.h>
121 #include <sys/mutex.h>
122 #include <sys/physmem.h>
123 #include <sys/proc.h>
124 #include <sys/rwlock.h>
125 #include <sys/sbuf.h>
127 #include <sys/vmem.h>
128 #include <sys/vmmeter.h>
129 #include <sys/sched.h>
130 #include <sys/sysctl.h>
131 #include <sys/_unrhdr.h>
135 #include <vm/vm_param.h>
136 #include <vm/vm_kern.h>
137 #include <vm/vm_page.h>
138 #include <vm/vm_map.h>
139 #include <vm/vm_object.h>
140 #include <vm/vm_extern.h>
141 #include <vm/vm_pageout.h>
142 #include <vm/vm_pager.h>
143 #include <vm/vm_phys.h>
144 #include <vm/vm_radix.h>
145 #include <vm/vm_reserv.h>
148 #include <machine/machdep.h>
149 #include <machine/md_var.h>
150 #include <machine/pcb.h>
152 #define PMAP_ASSERT_STAGE1(pmap) MPASS((pmap)->pm_stage == PM_STAGE1)
154 #define NL0PG (PAGE_SIZE/(sizeof (pd_entry_t)))
155 #define NL1PG (PAGE_SIZE/(sizeof (pd_entry_t)))
156 #define NL2PG (PAGE_SIZE/(sizeof (pd_entry_t)))
157 #define NL3PG (PAGE_SIZE/(sizeof (pt_entry_t)))
159 #define NUL0E L0_ENTRIES
160 #define NUL1E (NUL0E * NL1PG)
161 #define NUL2E (NUL1E * NL2PG)
163 #if !defined(DIAGNOSTIC)
164 #ifdef __GNUC_GNU_INLINE__
165 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
167 #define PMAP_INLINE extern inline
174 #define PV_STAT(x) do { x ; } while (0)
176 #define PV_STAT(x) do { } while (0)
179 #define pmap_l2_pindex(v) ((v) >> L2_SHIFT)
180 #define pa_to_pvh(pa) (&pv_table[pmap_l2_pindex(pa)])
182 #define NPV_LIST_LOCKS MAXCPU
184 #define PHYS_TO_PV_LIST_LOCK(pa) \
185 (&pv_list_locks[pa_index(pa) % NPV_LIST_LOCKS])
187 #define CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa) do { \
188 struct rwlock **_lockp = (lockp); \
189 struct rwlock *_new_lock; \
191 _new_lock = PHYS_TO_PV_LIST_LOCK(pa); \
192 if (_new_lock != *_lockp) { \
193 if (*_lockp != NULL) \
194 rw_wunlock(*_lockp); \
195 *_lockp = _new_lock; \
200 #define CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m) \
201 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, VM_PAGE_TO_PHYS(m))
203 #define RELEASE_PV_LIST_LOCK(lockp) do { \
204 struct rwlock **_lockp = (lockp); \
206 if (*_lockp != NULL) { \
207 rw_wunlock(*_lockp); \
212 #define VM_PAGE_TO_PV_LIST_LOCK(m) \
213 PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m))
216 * The presence of this flag indicates that the mapping is writeable.
217 * If the ATTR_S1_AP_RO bit is also set, then the mapping is clean, otherwise
218 * it is dirty. This flag may only be set on managed mappings.
220 * The DBM bit is reserved on ARMv8.0 but it seems we can safely treat it
221 * as a software managed bit.
223 #define ATTR_SW_DBM ATTR_DBM
225 struct pmap kernel_pmap_store;
227 /* Used for mapping ACPI memory before VM is initialized */
228 #define PMAP_PREINIT_MAPPING_COUNT 32
229 #define PMAP_PREINIT_MAPPING_SIZE (PMAP_PREINIT_MAPPING_COUNT * L2_SIZE)
230 static vm_offset_t preinit_map_va; /* Start VA of pre-init mapping space */
231 static int vm_initialized = 0; /* No need to use pre-init maps when set */
234 * Reserve a few L2 blocks starting from 'preinit_map_va' pointer.
235 * Always map entire L2 block for simplicity.
236 * VA of L2 block = preinit_map_va + i * L2_SIZE
238 static struct pmap_preinit_mapping {
242 } pmap_preinit_mapping[PMAP_PREINIT_MAPPING_COUNT];
244 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
245 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
246 vm_offset_t kernel_vm_end = 0;
249 * Data for the pv entry allocation mechanism.
251 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
252 static struct mtx pv_chunks_mutex;
253 static struct rwlock pv_list_locks[NPV_LIST_LOCKS];
254 static struct md_page *pv_table;
255 static struct md_page pv_dummy;
257 vm_paddr_t dmap_phys_base; /* The start of the dmap region */
258 vm_paddr_t dmap_phys_max; /* The limit of the dmap region */
259 vm_offset_t dmap_max_addr; /* The virtual address limit of the dmap */
261 /* This code assumes all L1 DMAP entries will be used */
262 CTASSERT((DMAP_MIN_ADDRESS & ~L0_OFFSET) == DMAP_MIN_ADDRESS);
263 CTASSERT((DMAP_MAX_ADDRESS & ~L0_OFFSET) == DMAP_MAX_ADDRESS);
265 #define DMAP_TABLES ((DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS) >> L0_SHIFT)
266 extern pt_entry_t pagetable_dmap[];
268 #define PHYSMAP_SIZE (2 * (VM_PHYSSEG_MAX - 1))
269 static vm_paddr_t physmap[PHYSMAP_SIZE];
270 static u_int physmap_idx;
272 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
273 "VM/pmap parameters");
276 * This ASID allocator uses a bit vector ("asid_set") to remember which ASIDs
277 * that it has currently allocated to a pmap, a cursor ("asid_next") to
278 * optimize its search for a free ASID in the bit vector, and an epoch number
279 * ("asid_epoch") to indicate when it has reclaimed all previously allocated
280 * ASIDs that are not currently active on a processor.
282 * The current epoch number is always in the range [0, INT_MAX). Negative
283 * numbers and INT_MAX are reserved for special cases that are described
292 struct mtx asid_set_mutex;
295 static struct asid_set asids;
297 static SYSCTL_NODE(_vm_pmap, OID_AUTO, asid, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
299 SYSCTL_INT(_vm_pmap_asid, OID_AUTO, bits, CTLFLAG_RD, &asids.asid_bits, 0,
300 "The number of bits in an ASID");
301 SYSCTL_INT(_vm_pmap_asid, OID_AUTO, next, CTLFLAG_RD, &asids.asid_next, 0,
302 "The last allocated ASID plus one");
303 SYSCTL_INT(_vm_pmap_asid, OID_AUTO, epoch, CTLFLAG_RD, &asids.asid_epoch, 0,
304 "The current epoch number");
307 * A pmap's cookie encodes an ASID and epoch number. Cookies for reserved
308 * ASIDs have a negative epoch number, specifically, INT_MIN. Cookies for
309 * dynamically allocated ASIDs have a non-negative epoch number.
311 * An invalid ASID is represented by -1.
313 * There are two special-case cookie values: (1) COOKIE_FROM(-1, INT_MIN),
314 * which indicates that an ASID should never be allocated to the pmap, and
315 * (2) COOKIE_FROM(-1, INT_MAX), which indicates that an ASID should be
316 * allocated when the pmap is next activated.
318 #define COOKIE_FROM(asid, epoch) ((long)((u_int)(asid) | \
319 ((u_long)(epoch) << 32)))
320 #define COOKIE_TO_ASID(cookie) ((int)(cookie))
321 #define COOKIE_TO_EPOCH(cookie) ((int)((u_long)(cookie) >> 32))
323 static int superpages_enabled = 1;
324 SYSCTL_INT(_vm_pmap, OID_AUTO, superpages_enabled,
325 CTLFLAG_RDTUN | CTLFLAG_NOFETCH, &superpages_enabled, 0,
326 "Are large page mappings enabled?");
329 * Internal flags for pmap_enter()'s helper functions.
331 #define PMAP_ENTER_NORECLAIM 0x1000000 /* Don't reclaim PV entries. */
332 #define PMAP_ENTER_NOREPLACE 0x2000000 /* Don't replace mappings. */
334 static void free_pv_chunk(struct pv_chunk *pc);
335 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
336 static pv_entry_t get_pv_entry(pmap_t pmap, struct rwlock **lockp);
337 static vm_page_t reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp);
338 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
339 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
342 static void pmap_abort_ptp(pmap_t pmap, vm_offset_t va, vm_page_t mpte);
343 static bool pmap_activate_int(pmap_t pmap);
344 static void pmap_alloc_asid(pmap_t pmap);
345 static int pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode);
346 static pt_entry_t *pmap_demote_l1(pmap_t pmap, pt_entry_t *l1, vm_offset_t va);
347 static pt_entry_t *pmap_demote_l2_locked(pmap_t pmap, pt_entry_t *l2,
348 vm_offset_t va, struct rwlock **lockp);
349 static pt_entry_t *pmap_demote_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t va);
350 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
351 vm_page_t m, vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp);
352 static int pmap_enter_l2(pmap_t pmap, vm_offset_t va, pd_entry_t new_l2,
353 u_int flags, vm_page_t m, struct rwlock **lockp);
354 static int pmap_remove_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t sva,
355 pd_entry_t l1e, struct spglist *free, struct rwlock **lockp);
356 static int pmap_remove_l3(pmap_t pmap, pt_entry_t *l3, vm_offset_t sva,
357 pd_entry_t l2e, struct spglist *free, struct rwlock **lockp);
358 static void pmap_reset_asid_set(pmap_t pmap);
359 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
360 vm_page_t m, struct rwlock **lockp);
362 static vm_page_t _pmap_alloc_l3(pmap_t pmap, vm_pindex_t ptepindex,
363 struct rwlock **lockp);
365 static void _pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m,
366 struct spglist *free);
367 static int pmap_unuse_pt(pmap_t, vm_offset_t, pd_entry_t, struct spglist *);
368 static __inline vm_page_t pmap_remove_pt_page(pmap_t pmap, vm_offset_t va);
371 * These load the old table data and store the new value.
372 * They need to be atomic as the System MMU may write to the table at
373 * the same time as the CPU.
375 #define pmap_clear(table) atomic_store_64(table, 0)
376 #define pmap_clear_bits(table, bits) atomic_clear_64(table, bits)
377 #define pmap_load(table) (*table)
378 #define pmap_load_clear(table) atomic_swap_64(table, 0)
379 #define pmap_load_store(table, entry) atomic_swap_64(table, entry)
380 #define pmap_set_bits(table, bits) atomic_set_64(table, bits)
381 #define pmap_store(table, entry) atomic_store_64(table, entry)
383 /********************/
384 /* Inline functions */
385 /********************/
388 pagecopy(void *s, void *d)
391 memcpy(d, s, PAGE_SIZE);
394 static __inline pd_entry_t *
395 pmap_l0(pmap_t pmap, vm_offset_t va)
398 return (&pmap->pm_l0[pmap_l0_index(va)]);
401 static __inline pd_entry_t *
402 pmap_l0_to_l1(pd_entry_t *l0, vm_offset_t va)
406 l1 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l0) & ~ATTR_MASK);
407 return (&l1[pmap_l1_index(va)]);
410 static __inline pd_entry_t *
411 pmap_l1(pmap_t pmap, vm_offset_t va)
415 l0 = pmap_l0(pmap, va);
416 if ((pmap_load(l0) & ATTR_DESCR_MASK) != L0_TABLE)
419 return (pmap_l0_to_l1(l0, va));
422 static __inline pd_entry_t *
423 pmap_l1_to_l2(pd_entry_t *l1, vm_offset_t va)
427 l2 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l1) & ~ATTR_MASK);
428 return (&l2[pmap_l2_index(va)]);
431 static __inline pd_entry_t *
432 pmap_l2(pmap_t pmap, vm_offset_t va)
436 l1 = pmap_l1(pmap, va);
437 if ((pmap_load(l1) & ATTR_DESCR_MASK) != L1_TABLE)
440 return (pmap_l1_to_l2(l1, va));
443 static __inline pt_entry_t *
444 pmap_l2_to_l3(pd_entry_t *l2, vm_offset_t va)
448 l3 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l2) & ~ATTR_MASK);
449 return (&l3[pmap_l3_index(va)]);
453 * Returns the lowest valid pde for a given virtual address.
454 * The next level may or may not point to a valid page or block.
456 static __inline pd_entry_t *
457 pmap_pde(pmap_t pmap, vm_offset_t va, int *level)
459 pd_entry_t *l0, *l1, *l2, desc;
461 l0 = pmap_l0(pmap, va);
462 desc = pmap_load(l0) & ATTR_DESCR_MASK;
463 if (desc != L0_TABLE) {
468 l1 = pmap_l0_to_l1(l0, va);
469 desc = pmap_load(l1) & ATTR_DESCR_MASK;
470 if (desc != L1_TABLE) {
475 l2 = pmap_l1_to_l2(l1, va);
476 desc = pmap_load(l2) & ATTR_DESCR_MASK;
477 if (desc != L2_TABLE) {
487 * Returns the lowest valid pte block or table entry for a given virtual
488 * address. If there are no valid entries return NULL and set the level to
489 * the first invalid level.
491 static __inline pt_entry_t *
492 pmap_pte(pmap_t pmap, vm_offset_t va, int *level)
494 pd_entry_t *l1, *l2, desc;
497 l1 = pmap_l1(pmap, va);
502 desc = pmap_load(l1) & ATTR_DESCR_MASK;
503 if (desc == L1_BLOCK) {
508 if (desc != L1_TABLE) {
513 l2 = pmap_l1_to_l2(l1, va);
514 desc = pmap_load(l2) & ATTR_DESCR_MASK;
515 if (desc == L2_BLOCK) {
520 if (desc != L2_TABLE) {
526 l3 = pmap_l2_to_l3(l2, va);
527 if ((pmap_load(l3) & ATTR_DESCR_MASK) != L3_PAGE)
534 pmap_ps_enabled(pmap_t pmap __unused)
537 return (superpages_enabled != 0);
541 pmap_get_tables(pmap_t pmap, vm_offset_t va, pd_entry_t **l0, pd_entry_t **l1,
542 pd_entry_t **l2, pt_entry_t **l3)
544 pd_entry_t *l0p, *l1p, *l2p;
546 if (pmap->pm_l0 == NULL)
549 l0p = pmap_l0(pmap, va);
552 if ((pmap_load(l0p) & ATTR_DESCR_MASK) != L0_TABLE)
555 l1p = pmap_l0_to_l1(l0p, va);
558 if ((pmap_load(l1p) & ATTR_DESCR_MASK) == L1_BLOCK) {
564 if ((pmap_load(l1p) & ATTR_DESCR_MASK) != L1_TABLE)
567 l2p = pmap_l1_to_l2(l1p, va);
570 if ((pmap_load(l2p) & ATTR_DESCR_MASK) == L2_BLOCK) {
575 if ((pmap_load(l2p) & ATTR_DESCR_MASK) != L2_TABLE)
578 *l3 = pmap_l2_to_l3(l2p, va);
584 pmap_l3_valid(pt_entry_t l3)
587 return ((l3 & ATTR_DESCR_MASK) == L3_PAGE);
591 CTASSERT(L1_BLOCK == L2_BLOCK);
594 * Checks if the PTE is dirty.
597 pmap_pte_dirty(pmap_t pmap, pt_entry_t pte)
600 PMAP_ASSERT_STAGE1(pmap);
601 KASSERT((pte & ATTR_SW_MANAGED) != 0, ("pte %#lx is unmanaged", pte));
602 KASSERT((pte & (ATTR_S1_AP_RW_BIT | ATTR_SW_DBM)) != 0,
603 ("pte %#lx is writeable and missing ATTR_SW_DBM", pte));
605 return ((pte & (ATTR_S1_AP_RW_BIT | ATTR_SW_DBM)) ==
606 (ATTR_S1_AP(ATTR_S1_AP_RW) | ATTR_SW_DBM));
610 pmap_resident_count_inc(pmap_t pmap, int count)
613 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
614 pmap->pm_stats.resident_count += count;
618 pmap_resident_count_dec(pmap_t pmap, int count)
621 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
622 KASSERT(pmap->pm_stats.resident_count >= count,
623 ("pmap %p resident count underflow %ld %d", pmap,
624 pmap->pm_stats.resident_count, count));
625 pmap->pm_stats.resident_count -= count;
629 pmap_early_page_idx(vm_offset_t l1pt, vm_offset_t va, u_int *l1_slot,
635 l1 = (pd_entry_t *)l1pt;
636 *l1_slot = (va >> L1_SHIFT) & Ln_ADDR_MASK;
638 /* Check locore has used a table L1 map */
639 KASSERT((l1[*l1_slot] & ATTR_DESCR_MASK) == L1_TABLE,
640 ("Invalid bootstrap L1 table"));
641 /* Find the address of the L2 table */
642 l2 = (pt_entry_t *)init_pt_va;
643 *l2_slot = pmap_l2_index(va);
649 pmap_early_vtophys(vm_offset_t l1pt, vm_offset_t va)
651 u_int l1_slot, l2_slot;
654 l2 = pmap_early_page_idx(l1pt, va, &l1_slot, &l2_slot);
656 return ((l2[l2_slot] & ~ATTR_MASK) + (va & L2_OFFSET));
660 pmap_bootstrap_dmap(vm_offset_t kern_l1, vm_paddr_t min_pa,
661 vm_offset_t freemempos)
665 vm_paddr_t l2_pa, pa;
666 u_int l1_slot, l2_slot, prev_l1_slot;
669 dmap_phys_base = min_pa & ~L1_OFFSET;
675 #define DMAP_TABLES ((DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS) >> L0_SHIFT)
676 memset(pagetable_dmap, 0, PAGE_SIZE * DMAP_TABLES);
678 for (i = 0; i < (physmap_idx * 2); i += 2) {
679 pa = physmap[i] & ~L2_OFFSET;
680 va = pa - dmap_phys_base + DMAP_MIN_ADDRESS;
682 /* Create L2 mappings at the start of the region */
683 if ((pa & L1_OFFSET) != 0) {
684 l1_slot = ((va - DMAP_MIN_ADDRESS) >> L1_SHIFT);
685 if (l1_slot != prev_l1_slot) {
686 prev_l1_slot = l1_slot;
687 l2 = (pt_entry_t *)freemempos;
688 l2_pa = pmap_early_vtophys(kern_l1,
690 freemempos += PAGE_SIZE;
692 pmap_store(&pagetable_dmap[l1_slot],
693 (l2_pa & ~Ln_TABLE_MASK) | L1_TABLE);
695 memset(l2, 0, PAGE_SIZE);
698 ("pmap_bootstrap_dmap: NULL l2 map"));
699 for (; va < DMAP_MAX_ADDRESS && pa < physmap[i + 1];
700 pa += L2_SIZE, va += L2_SIZE) {
702 * We are on a boundary, stop to
703 * create a level 1 block
705 if ((pa & L1_OFFSET) == 0)
708 l2_slot = pmap_l2_index(va);
709 KASSERT(l2_slot != 0, ("..."));
710 pmap_store(&l2[l2_slot],
711 (pa & ~L2_OFFSET) | ATTR_DEFAULT |
713 ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK) |
716 KASSERT(va == (pa - dmap_phys_base + DMAP_MIN_ADDRESS),
720 for (; va < DMAP_MAX_ADDRESS && pa < physmap[i + 1] &&
721 (physmap[i + 1] - pa) >= L1_SIZE;
722 pa += L1_SIZE, va += L1_SIZE) {
723 l1_slot = ((va - DMAP_MIN_ADDRESS) >> L1_SHIFT);
724 pmap_store(&pagetable_dmap[l1_slot],
725 (pa & ~L1_OFFSET) | ATTR_DEFAULT | ATTR_S1_XN |
726 ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK) | L1_BLOCK);
729 /* Create L2 mappings at the end of the region */
730 if (pa < physmap[i + 1]) {
731 l1_slot = ((va - DMAP_MIN_ADDRESS) >> L1_SHIFT);
732 if (l1_slot != prev_l1_slot) {
733 prev_l1_slot = l1_slot;
734 l2 = (pt_entry_t *)freemempos;
735 l2_pa = pmap_early_vtophys(kern_l1,
737 freemempos += PAGE_SIZE;
739 pmap_store(&pagetable_dmap[l1_slot],
740 (l2_pa & ~Ln_TABLE_MASK) | L1_TABLE);
742 memset(l2, 0, PAGE_SIZE);
745 ("pmap_bootstrap_dmap: NULL l2 map"));
746 for (; va < DMAP_MAX_ADDRESS && pa < physmap[i + 1];
747 pa += L2_SIZE, va += L2_SIZE) {
748 l2_slot = pmap_l2_index(va);
749 pmap_store(&l2[l2_slot],
750 (pa & ~L2_OFFSET) | ATTR_DEFAULT |
752 ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK) |
757 if (pa > dmap_phys_max) {
769 pmap_bootstrap_l2(vm_offset_t l1pt, vm_offset_t va, vm_offset_t l2_start)
776 KASSERT((va & L1_OFFSET) == 0, ("Invalid virtual address"));
778 l1 = (pd_entry_t *)l1pt;
779 l1_slot = pmap_l1_index(va);
782 for (; va < VM_MAX_KERNEL_ADDRESS; l1_slot++, va += L1_SIZE) {
783 KASSERT(l1_slot < Ln_ENTRIES, ("Invalid L1 index"));
785 pa = pmap_early_vtophys(l1pt, l2pt);
786 pmap_store(&l1[l1_slot],
787 (pa & ~Ln_TABLE_MASK) | L1_TABLE);
791 /* Clean the L2 page table */
792 memset((void *)l2_start, 0, l2pt - l2_start);
798 pmap_bootstrap_l3(vm_offset_t l1pt, vm_offset_t va, vm_offset_t l3_start)
805 KASSERT((va & L2_OFFSET) == 0, ("Invalid virtual address"));
807 l2 = pmap_l2(kernel_pmap, va);
808 l2 = (pd_entry_t *)rounddown2((uintptr_t)l2, PAGE_SIZE);
809 l2_slot = pmap_l2_index(va);
812 for (; va < VM_MAX_KERNEL_ADDRESS; l2_slot++, va += L2_SIZE) {
813 KASSERT(l2_slot < Ln_ENTRIES, ("Invalid L2 index"));
815 pa = pmap_early_vtophys(l1pt, l3pt);
816 pmap_store(&l2[l2_slot],
817 (pa & ~Ln_TABLE_MASK) | ATTR_S1_UXN | L2_TABLE);
821 /* Clean the L2 page table */
822 memset((void *)l3_start, 0, l3pt - l3_start);
828 * Bootstrap the system enough to run with virtual memory.
831 pmap_bootstrap(vm_offset_t l0pt, vm_offset_t l1pt, vm_paddr_t kernstart,
834 vm_offset_t freemempos;
835 vm_offset_t dpcpu, msgbufpv;
836 vm_paddr_t start_pa, pa, min_pa;
840 /* Verify that the ASID is set through TTBR0. */
841 KASSERT((READ_SPECIALREG(tcr_el1) & TCR_A1) == 0,
842 ("pmap_bootstrap: TCR_EL1.A1 != 0"));
844 kern_delta = KERNBASE - kernstart;
846 printf("pmap_bootstrap %lx %lx %lx\n", l1pt, kernstart, kernlen);
847 printf("%lx\n", l1pt);
848 printf("%lx\n", (KERNBASE >> L1_SHIFT) & Ln_ADDR_MASK);
850 /* Set this early so we can use the pagetable walking functions */
851 kernel_pmap_store.pm_l0 = (pd_entry_t *)l0pt;
852 PMAP_LOCK_INIT(kernel_pmap);
853 kernel_pmap->pm_l0_paddr = l0pt - kern_delta;
854 kernel_pmap->pm_cookie = COOKIE_FROM(-1, INT_MIN);
855 kernel_pmap->pm_stage = PM_STAGE1;
856 kernel_pmap->pm_asid_set = &asids;
858 /* Assume the address we were loaded to is a valid physical address */
859 min_pa = KERNBASE - kern_delta;
861 physmap_idx = physmem_avail(physmap, nitems(physmap));
865 * Find the minimum physical address. physmap is sorted,
866 * but may contain empty ranges.
868 for (i = 0; i < physmap_idx * 2; i += 2) {
869 if (physmap[i] == physmap[i + 1])
871 if (physmap[i] <= min_pa)
875 freemempos = KERNBASE + kernlen;
876 freemempos = roundup2(freemempos, PAGE_SIZE);
878 /* Create a direct map region early so we can use it for pa -> va */
879 freemempos = pmap_bootstrap_dmap(l1pt, min_pa, freemempos);
881 start_pa = pa = KERNBASE - kern_delta;
884 * Create the l2 tables up to VM_MAX_KERNEL_ADDRESS. We assume that the
885 * loader allocated the first and only l2 page table page used to map
886 * the kernel, preloaded files and module metadata.
888 freemempos = pmap_bootstrap_l2(l1pt, KERNBASE + L1_SIZE, freemempos);
889 /* And the l3 tables for the early devmap */
890 freemempos = pmap_bootstrap_l3(l1pt,
891 VM_MAX_KERNEL_ADDRESS - (PMAP_MAPDEV_EARLY_SIZE), freemempos);
895 #define alloc_pages(var, np) \
896 (var) = freemempos; \
897 freemempos += (np * PAGE_SIZE); \
898 memset((char *)(var), 0, ((np) * PAGE_SIZE));
900 /* Allocate dynamic per-cpu area. */
901 alloc_pages(dpcpu, DPCPU_SIZE / PAGE_SIZE);
902 dpcpu_init((void *)dpcpu, 0);
904 /* Allocate memory for the msgbuf, e.g. for /sbin/dmesg */
905 alloc_pages(msgbufpv, round_page(msgbufsize) / PAGE_SIZE);
906 msgbufp = (void *)msgbufpv;
908 /* Reserve some VA space for early BIOS/ACPI mapping */
909 preinit_map_va = roundup2(freemempos, L2_SIZE);
911 virtual_avail = preinit_map_va + PMAP_PREINIT_MAPPING_SIZE;
912 virtual_avail = roundup2(virtual_avail, L1_SIZE);
913 virtual_end = VM_MAX_KERNEL_ADDRESS - (PMAP_MAPDEV_EARLY_SIZE);
914 kernel_vm_end = virtual_avail;
916 pa = pmap_early_vtophys(l1pt, freemempos);
918 physmem_exclude_region(start_pa, pa - start_pa, EXFLAG_NOALLOC);
924 * Initialize a vm_page's machine-dependent fields.
927 pmap_page_init(vm_page_t m)
930 TAILQ_INIT(&m->md.pv_list);
931 m->md.pv_memattr = VM_MEMATTR_WRITE_BACK;
935 pmap_init_asids(struct asid_set *set, int bits)
939 set->asid_bits = bits;
942 * We may be too early in the overall initialization process to use
945 set->asid_set_size = 1 << set->asid_bits;
946 set->asid_set = (bitstr_t *)kmem_malloc(bitstr_size(set->asid_set_size),
948 for (i = 0; i < ASID_FIRST_AVAILABLE; i++)
949 bit_set(set->asid_set, i);
950 set->asid_next = ASID_FIRST_AVAILABLE;
951 mtx_init(&set->asid_set_mutex, "asid set", NULL, MTX_SPIN);
955 * Initialize the pmap module.
956 * Called by vm_init, to initialize any structures that the pmap
957 * system needs to map virtual memory.
966 * Are large page mappings enabled?
968 TUNABLE_INT_FETCH("vm.pmap.superpages_enabled", &superpages_enabled);
969 if (superpages_enabled) {
970 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
971 ("pmap_init: can't assign to pagesizes[1]"));
972 pagesizes[1] = L2_SIZE;
976 * Initialize the ASID allocator.
978 pmap_init_asids(&asids,
979 (READ_SPECIALREG(tcr_el1) & TCR_ASID_16) != 0 ? 16 : 8);
982 * Initialize the pv chunk list mutex.
984 mtx_init(&pv_chunks_mutex, "pmap pv chunk list", NULL, MTX_DEF);
987 * Initialize the pool of pv list locks.
989 for (i = 0; i < NPV_LIST_LOCKS; i++)
990 rw_init(&pv_list_locks[i], "pmap pv list");
993 * Calculate the size of the pv head table for superpages.
995 pv_npg = howmany(vm_phys_segs[vm_phys_nsegs - 1].end, L2_SIZE);
998 * Allocate memory for the pv head table for superpages.
1000 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
1002 pv_table = (struct md_page *)kmem_malloc(s, M_WAITOK | M_ZERO);
1003 for (i = 0; i < pv_npg; i++)
1004 TAILQ_INIT(&pv_table[i].pv_list);
1005 TAILQ_INIT(&pv_dummy.pv_list);
1010 static SYSCTL_NODE(_vm_pmap, OID_AUTO, l2, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
1011 "2MB page mapping counters");
1013 static u_long pmap_l2_demotions;
1014 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, demotions, CTLFLAG_RD,
1015 &pmap_l2_demotions, 0, "2MB page demotions");
1017 static u_long pmap_l2_mappings;
1018 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, mappings, CTLFLAG_RD,
1019 &pmap_l2_mappings, 0, "2MB page mappings");
1021 static u_long pmap_l2_p_failures;
1022 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, p_failures, CTLFLAG_RD,
1023 &pmap_l2_p_failures, 0, "2MB page promotion failures");
1025 static u_long pmap_l2_promotions;
1026 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, promotions, CTLFLAG_RD,
1027 &pmap_l2_promotions, 0, "2MB page promotions");
1030 * Invalidate a single TLB entry.
1032 static __inline void
1033 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
1037 PMAP_ASSERT_STAGE1(pmap);
1040 if (pmap == kernel_pmap) {
1042 __asm __volatile("tlbi vaae1is, %0" : : "r" (r));
1044 r = ASID_TO_OPERAND(COOKIE_TO_ASID(pmap->pm_cookie)) | atop(va);
1045 __asm __volatile("tlbi vae1is, %0" : : "r" (r));
1051 static __inline void
1052 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1054 uint64_t end, r, start;
1056 PMAP_ASSERT_STAGE1(pmap);
1059 if (pmap == kernel_pmap) {
1062 for (r = start; r < end; r++)
1063 __asm __volatile("tlbi vaae1is, %0" : : "r" (r));
1065 start = end = ASID_TO_OPERAND(COOKIE_TO_ASID(pmap->pm_cookie));
1068 for (r = start; r < end; r++)
1069 __asm __volatile("tlbi vae1is, %0" : : "r" (r));
1075 static __inline void
1076 pmap_invalidate_all(pmap_t pmap)
1080 PMAP_ASSERT_STAGE1(pmap);
1083 if (pmap == kernel_pmap) {
1084 __asm __volatile("tlbi vmalle1is");
1086 r = ASID_TO_OPERAND(COOKIE_TO_ASID(pmap->pm_cookie));
1087 __asm __volatile("tlbi aside1is, %0" : : "r" (r));
1094 * Routine: pmap_extract
1096 * Extract the physical page address associated
1097 * with the given map/virtual_address pair.
1100 pmap_extract(pmap_t pmap, vm_offset_t va)
1102 pt_entry_t *pte, tpte;
1109 * Find the block or page map for this virtual address. pmap_pte
1110 * will return either a valid block/page entry, or NULL.
1112 pte = pmap_pte(pmap, va, &lvl);
1114 tpte = pmap_load(pte);
1115 pa = tpte & ~ATTR_MASK;
1118 KASSERT((tpte & ATTR_DESCR_MASK) == L1_BLOCK,
1119 ("pmap_extract: Invalid L1 pte found: %lx",
1120 tpte & ATTR_DESCR_MASK));
1121 pa |= (va & L1_OFFSET);
1124 KASSERT((tpte & ATTR_DESCR_MASK) == L2_BLOCK,
1125 ("pmap_extract: Invalid L2 pte found: %lx",
1126 tpte & ATTR_DESCR_MASK));
1127 pa |= (va & L2_OFFSET);
1130 KASSERT((tpte & ATTR_DESCR_MASK) == L3_PAGE,
1131 ("pmap_extract: Invalid L3 pte found: %lx",
1132 tpte & ATTR_DESCR_MASK));
1133 pa |= (va & L3_OFFSET);
1142 * Routine: pmap_extract_and_hold
1144 * Atomically extract and hold the physical page
1145 * with the given pmap and virtual address pair
1146 * if that mapping permits the given protection.
1149 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1151 pt_entry_t *pte, tpte;
1156 PMAP_ASSERT_STAGE1(pmap);
1160 pte = pmap_pte(pmap, va, &lvl);
1162 tpte = pmap_load(pte);
1164 KASSERT(lvl > 0 && lvl <= 3,
1165 ("pmap_extract_and_hold: Invalid level %d", lvl));
1166 CTASSERT(L1_BLOCK == L2_BLOCK);
1167 KASSERT((lvl == 3 && (tpte & ATTR_DESCR_MASK) == L3_PAGE) ||
1168 (lvl < 3 && (tpte & ATTR_DESCR_MASK) == L1_BLOCK),
1169 ("pmap_extract_and_hold: Invalid pte at L%d: %lx", lvl,
1170 tpte & ATTR_DESCR_MASK));
1171 if (((tpte & ATTR_S1_AP_RW_BIT) == ATTR_S1_AP(ATTR_S1_AP_RW)) ||
1172 ((prot & VM_PROT_WRITE) == 0)) {
1175 off = va & L1_OFFSET;
1178 off = va & L2_OFFSET;
1184 m = PHYS_TO_VM_PAGE((tpte & ~ATTR_MASK) | off);
1185 if (!vm_page_wire_mapped(m))
1194 pmap_kextract(vm_offset_t va)
1196 pt_entry_t *pte, tpte;
1198 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS)
1199 return (DMAP_TO_PHYS(va));
1200 pte = pmap_l1(kernel_pmap, va);
1205 * A concurrent pmap_update_entry() will clear the entry's valid bit
1206 * but leave the rest of the entry unchanged. Therefore, we treat a
1207 * non-zero entry as being valid, and we ignore the valid bit when
1208 * determining whether the entry maps a block, page, or table.
1210 tpte = pmap_load(pte);
1213 if ((tpte & ATTR_DESCR_TYPE_MASK) == ATTR_DESCR_TYPE_BLOCK)
1214 return ((tpte & ~ATTR_MASK) | (va & L1_OFFSET));
1215 pte = pmap_l1_to_l2(&tpte, va);
1216 tpte = pmap_load(pte);
1219 if ((tpte & ATTR_DESCR_TYPE_MASK) == ATTR_DESCR_TYPE_BLOCK)
1220 return ((tpte & ~ATTR_MASK) | (va & L2_OFFSET));
1221 pte = pmap_l2_to_l3(&tpte, va);
1222 tpte = pmap_load(pte);
1225 return ((tpte & ~ATTR_MASK) | (va & L3_OFFSET));
1228 /***************************************************
1229 * Low level mapping routines.....
1230 ***************************************************/
1233 pmap_kenter(vm_offset_t sva, vm_size_t size, vm_paddr_t pa, int mode)
1236 pt_entry_t *pte, attr;
1240 KASSERT((pa & L3_OFFSET) == 0,
1241 ("pmap_kenter: Invalid physical address"));
1242 KASSERT((sva & L3_OFFSET) == 0,
1243 ("pmap_kenter: Invalid virtual address"));
1244 KASSERT((size & PAGE_MASK) == 0,
1245 ("pmap_kenter: Mapping is not page-sized"));
1247 attr = ATTR_DEFAULT | ATTR_S1_AP(ATTR_S1_AP_RW) | ATTR_S1_XN |
1248 ATTR_S1_IDX(mode) | L3_PAGE;
1251 pde = pmap_pde(kernel_pmap, va, &lvl);
1252 KASSERT(pde != NULL,
1253 ("pmap_kenter: Invalid page entry, va: 0x%lx", va));
1254 KASSERT(lvl == 2, ("pmap_kenter: Invalid level %d", lvl));
1256 pte = pmap_l2_to_l3(pde, va);
1257 pmap_load_store(pte, (pa & ~L3_OFFSET) | attr);
1263 pmap_invalidate_range(kernel_pmap, sva, va);
1267 pmap_kenter_device(vm_offset_t sva, vm_size_t size, vm_paddr_t pa)
1270 pmap_kenter(sva, size, pa, VM_MEMATTR_DEVICE);
1274 * Remove a page from the kernel pagetables.
1277 pmap_kremove(vm_offset_t va)
1282 pte = pmap_pte(kernel_pmap, va, &lvl);
1283 KASSERT(pte != NULL, ("pmap_kremove: Invalid address"));
1284 KASSERT(lvl == 3, ("pmap_kremove: Invalid pte level %d", lvl));
1287 pmap_invalidate_page(kernel_pmap, va);
1291 pmap_kremove_device(vm_offset_t sva, vm_size_t size)
1297 KASSERT((sva & L3_OFFSET) == 0,
1298 ("pmap_kremove_device: Invalid virtual address"));
1299 KASSERT((size & PAGE_MASK) == 0,
1300 ("pmap_kremove_device: Mapping is not page-sized"));
1304 pte = pmap_pte(kernel_pmap, va, &lvl);
1305 KASSERT(pte != NULL, ("Invalid page table, va: 0x%lx", va));
1307 ("Invalid device pagetable level: %d != 3", lvl));
1313 pmap_invalidate_range(kernel_pmap, sva, va);
1317 * Used to map a range of physical addresses into kernel
1318 * virtual address space.
1320 * The value passed in '*virt' is a suggested virtual address for
1321 * the mapping. Architectures which can support a direct-mapped
1322 * physical to virtual region can return the appropriate address
1323 * within that region, leaving '*virt' unchanged. Other
1324 * architectures should map the pages starting at '*virt' and
1325 * update '*virt' with the first usable address after the mapped
1329 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
1331 return PHYS_TO_DMAP(start);
1336 * Add a list of wired pages to the kva
1337 * this routine is only used for temporary
1338 * kernel mappings that do not need to have
1339 * page modification or references recorded.
1340 * Note that old mappings are simply written
1341 * over. The page *must* be wired.
1342 * Note: SMP coherent. Uses a ranged shootdown IPI.
1345 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
1348 pt_entry_t *pte, pa;
1354 for (i = 0; i < count; i++) {
1355 pde = pmap_pde(kernel_pmap, va, &lvl);
1356 KASSERT(pde != NULL,
1357 ("pmap_qenter: Invalid page entry, va: 0x%lx", va));
1359 ("pmap_qenter: Invalid level %d", lvl));
1362 pa = VM_PAGE_TO_PHYS(m) | ATTR_DEFAULT |
1363 ATTR_S1_AP(ATTR_S1_AP_RW) | ATTR_S1_XN |
1364 ATTR_S1_IDX(m->md.pv_memattr) | L3_PAGE;
1365 pte = pmap_l2_to_l3(pde, va);
1366 pmap_load_store(pte, pa);
1370 pmap_invalidate_range(kernel_pmap, sva, va);
1374 * This routine tears out page mappings from the
1375 * kernel -- it is meant only for temporary mappings.
1378 pmap_qremove(vm_offset_t sva, int count)
1384 KASSERT(sva >= VM_MIN_KERNEL_ADDRESS, ("usermode va %lx", sva));
1387 while (count-- > 0) {
1388 pte = pmap_pte(kernel_pmap, va, &lvl);
1390 ("Invalid device pagetable level: %d != 3", lvl));
1397 pmap_invalidate_range(kernel_pmap, sva, va);
1400 /***************************************************
1401 * Page table page management routines.....
1402 ***************************************************/
1404 * Schedule the specified unused page table page to be freed. Specifically,
1405 * add the page to the specified list of pages that will be released to the
1406 * physical memory manager after the TLB has been updated.
1408 static __inline void
1409 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
1410 boolean_t set_PG_ZERO)
1414 m->flags |= PG_ZERO;
1416 m->flags &= ~PG_ZERO;
1417 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
1421 * Decrements a page table page's reference count, which is used to record the
1422 * number of valid page table entries within the page. If the reference count
1423 * drops to zero, then the page table page is unmapped. Returns TRUE if the
1424 * page table page was unmapped and FALSE otherwise.
1426 static inline boolean_t
1427 pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
1431 if (m->ref_count == 0) {
1432 _pmap_unwire_l3(pmap, va, m, free);
1439 _pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
1442 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1444 * unmap the page table page
1446 if (m->pindex >= (NUL2E + NUL1E)) {
1450 l0 = pmap_l0(pmap, va);
1452 } else if (m->pindex >= NUL2E) {
1456 l1 = pmap_l1(pmap, va);
1462 l2 = pmap_l2(pmap, va);
1465 pmap_resident_count_dec(pmap, 1);
1466 if (m->pindex < NUL2E) {
1467 /* We just released an l3, unhold the matching l2 */
1468 pd_entry_t *l1, tl1;
1471 l1 = pmap_l1(pmap, va);
1472 tl1 = pmap_load(l1);
1473 l2pg = PHYS_TO_VM_PAGE(tl1 & ~ATTR_MASK);
1474 pmap_unwire_l3(pmap, va, l2pg, free);
1475 } else if (m->pindex < (NUL2E + NUL1E)) {
1476 /* We just released an l2, unhold the matching l1 */
1477 pd_entry_t *l0, tl0;
1480 l0 = pmap_l0(pmap, va);
1481 tl0 = pmap_load(l0);
1482 l1pg = PHYS_TO_VM_PAGE(tl0 & ~ATTR_MASK);
1483 pmap_unwire_l3(pmap, va, l1pg, free);
1485 pmap_invalidate_page(pmap, va);
1488 * Put page on a list so that it is released after
1489 * *ALL* TLB shootdown is done
1491 pmap_add_delayed_free_list(m, free, TRUE);
1495 * After removing a page table entry, this routine is used to
1496 * conditionally free the page, and manage the reference count.
1499 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, pd_entry_t ptepde,
1500 struct spglist *free)
1504 if (va >= VM_MAXUSER_ADDRESS)
1506 KASSERT(ptepde != 0, ("pmap_unuse_pt: ptepde != 0"));
1507 mpte = PHYS_TO_VM_PAGE(ptepde & ~ATTR_MASK);
1508 return (pmap_unwire_l3(pmap, va, mpte, free));
1512 * Release a page table page reference after a failed attempt to create a
1516 pmap_abort_ptp(pmap_t pmap, vm_offset_t va, vm_page_t mpte)
1518 struct spglist free;
1521 if (pmap_unwire_l3(pmap, va, mpte, &free)) {
1523 * Although "va" was never mapped, the TLB could nonetheless
1524 * have intermediate entries that refer to the freed page
1525 * table pages. Invalidate those entries.
1527 * XXX redundant invalidation (See _pmap_unwire_l3().)
1529 pmap_invalidate_page(pmap, va);
1530 vm_page_free_pages_toq(&free, true);
1535 pmap_pinit0(pmap_t pmap)
1538 PMAP_LOCK_INIT(pmap);
1539 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats));
1540 pmap->pm_l0_paddr = READ_SPECIALREG(ttbr0_el1);
1541 pmap->pm_l0 = (pd_entry_t *)PHYS_TO_DMAP(pmap->pm_l0_paddr);
1542 pmap->pm_root.rt_root = 0;
1543 pmap->pm_cookie = COOKIE_FROM(ASID_RESERVED_FOR_PID_0, INT_MIN);
1544 pmap->pm_stage = PM_STAGE1;
1545 pmap->pm_asid_set = &asids;
1547 PCPU_SET(curpmap, pmap);
1551 pmap_pinit(pmap_t pmap)
1556 * allocate the l0 page
1558 while ((l0pt = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
1559 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL)
1562 pmap->pm_l0_paddr = VM_PAGE_TO_PHYS(l0pt);
1563 pmap->pm_l0 = (pd_entry_t *)PHYS_TO_DMAP(pmap->pm_l0_paddr);
1565 if ((l0pt->flags & PG_ZERO) == 0)
1566 pagezero(pmap->pm_l0);
1568 pmap->pm_root.rt_root = 0;
1569 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats));
1570 pmap->pm_cookie = COOKIE_FROM(-1, INT_MAX);
1571 pmap->pm_stage = PM_STAGE1;
1572 pmap->pm_asid_set = &asids;
1573 /* XXX Temporarily disable deferred ASID allocation. */
1574 pmap_alloc_asid(pmap);
1580 * This routine is called if the desired page table page does not exist.
1582 * If page table page allocation fails, this routine may sleep before
1583 * returning NULL. It sleeps only if a lock pointer was given.
1585 * Note: If a page allocation fails at page table level two or three,
1586 * one or two pages may be held during the wait, only to be released
1587 * afterwards. This conservative approach is easily argued to avoid
1591 _pmap_alloc_l3(pmap_t pmap, vm_pindex_t ptepindex, struct rwlock **lockp)
1593 vm_page_t m, l1pg, l2pg;
1595 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1598 * Allocate a page table page.
1600 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
1601 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
1602 if (lockp != NULL) {
1603 RELEASE_PV_LIST_LOCK(lockp);
1610 * Indicate the need to retry. While waiting, the page table
1611 * page may have been allocated.
1615 if ((m->flags & PG_ZERO) == 0)
1619 * Because of AArch64's weak memory consistency model, we must have a
1620 * barrier here to ensure that the stores for zeroing "m", whether by
1621 * pmap_zero_page() or an earlier function, are visible before adding
1622 * "m" to the page table. Otherwise, a page table walk by another
1623 * processor's MMU could see the mapping to "m" and a stale, non-zero
1629 * Map the pagetable page into the process address space, if
1630 * it isn't already there.
1633 if (ptepindex >= (NUL2E + NUL1E)) {
1635 vm_pindex_t l0index;
1637 l0index = ptepindex - (NUL2E + NUL1E);
1638 l0 = &pmap->pm_l0[l0index];
1639 pmap_store(l0, VM_PAGE_TO_PHYS(m) | L0_TABLE);
1640 } else if (ptepindex >= NUL2E) {
1641 vm_pindex_t l0index, l1index;
1642 pd_entry_t *l0, *l1;
1645 l1index = ptepindex - NUL2E;
1646 l0index = l1index >> L0_ENTRIES_SHIFT;
1648 l0 = &pmap->pm_l0[l0index];
1649 tl0 = pmap_load(l0);
1651 /* recurse for allocating page dir */
1652 if (_pmap_alloc_l3(pmap, NUL2E + NUL1E + l0index,
1654 vm_page_unwire_noq(m);
1655 vm_page_free_zero(m);
1659 l1pg = PHYS_TO_VM_PAGE(tl0 & ~ATTR_MASK);
1663 l1 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l0) & ~ATTR_MASK);
1664 l1 = &l1[ptepindex & Ln_ADDR_MASK];
1665 pmap_store(l1, VM_PAGE_TO_PHYS(m) | L1_TABLE);
1667 vm_pindex_t l0index, l1index;
1668 pd_entry_t *l0, *l1, *l2;
1669 pd_entry_t tl0, tl1;
1671 l1index = ptepindex >> Ln_ENTRIES_SHIFT;
1672 l0index = l1index >> L0_ENTRIES_SHIFT;
1674 l0 = &pmap->pm_l0[l0index];
1675 tl0 = pmap_load(l0);
1677 /* recurse for allocating page dir */
1678 if (_pmap_alloc_l3(pmap, NUL2E + l1index,
1680 vm_page_unwire_noq(m);
1681 vm_page_free_zero(m);
1684 tl0 = pmap_load(l0);
1685 l1 = (pd_entry_t *)PHYS_TO_DMAP(tl0 & ~ATTR_MASK);
1686 l1 = &l1[l1index & Ln_ADDR_MASK];
1688 l1 = (pd_entry_t *)PHYS_TO_DMAP(tl0 & ~ATTR_MASK);
1689 l1 = &l1[l1index & Ln_ADDR_MASK];
1690 tl1 = pmap_load(l1);
1692 /* recurse for allocating page dir */
1693 if (_pmap_alloc_l3(pmap, NUL2E + l1index,
1695 vm_page_unwire_noq(m);
1696 vm_page_free_zero(m);
1700 l2pg = PHYS_TO_VM_PAGE(tl1 & ~ATTR_MASK);
1705 l2 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l1) & ~ATTR_MASK);
1706 l2 = &l2[ptepindex & Ln_ADDR_MASK];
1707 pmap_store(l2, VM_PAGE_TO_PHYS(m) | L2_TABLE);
1710 pmap_resident_count_inc(pmap, 1);
1716 pmap_alloc_l2(pmap_t pmap, vm_offset_t va, vm_page_t *l2pgp,
1717 struct rwlock **lockp)
1719 pd_entry_t *l1, *l2;
1721 vm_pindex_t l2pindex;
1724 l1 = pmap_l1(pmap, va);
1725 if (l1 != NULL && (pmap_load(l1) & ATTR_DESCR_MASK) == L1_TABLE) {
1726 l2 = pmap_l1_to_l2(l1, va);
1727 if (va < VM_MAXUSER_ADDRESS) {
1728 /* Add a reference to the L2 page. */
1729 l2pg = PHYS_TO_VM_PAGE(pmap_load(l1) & ~ATTR_MASK);
1733 } else if (va < VM_MAXUSER_ADDRESS) {
1734 /* Allocate a L2 page. */
1735 l2pindex = pmap_l2_pindex(va) >> Ln_ENTRIES_SHIFT;
1736 l2pg = _pmap_alloc_l3(pmap, NUL2E + l2pindex, lockp);
1743 l2 = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(l2pg));
1744 l2 = &l2[pmap_l2_index(va)];
1746 panic("pmap_alloc_l2: missing page table page for va %#lx",
1753 pmap_alloc_l3(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
1755 vm_pindex_t ptepindex;
1756 pd_entry_t *pde, tpde;
1764 * Calculate pagetable page index
1766 ptepindex = pmap_l2_pindex(va);
1769 * Get the page directory entry
1771 pde = pmap_pde(pmap, va, &lvl);
1774 * If the page table page is mapped, we just increment the hold count,
1775 * and activate it. If we get a level 2 pde it will point to a level 3
1783 pte = pmap_l0_to_l1(pde, va);
1784 KASSERT(pmap_load(pte) == 0,
1785 ("pmap_alloc_l3: TODO: l0 superpages"));
1790 pte = pmap_l1_to_l2(pde, va);
1791 KASSERT(pmap_load(pte) == 0,
1792 ("pmap_alloc_l3: TODO: l1 superpages"));
1796 tpde = pmap_load(pde);
1798 m = PHYS_TO_VM_PAGE(tpde & ~ATTR_MASK);
1804 panic("pmap_alloc_l3: Invalid level %d", lvl);
1808 * Here if the pte page isn't mapped, or if it has been deallocated.
1810 m = _pmap_alloc_l3(pmap, ptepindex, lockp);
1811 if (m == NULL && lockp != NULL)
1817 /***************************************************
1818 * Pmap allocation/deallocation routines.
1819 ***************************************************/
1822 * Release any resources held by the given physical map.
1823 * Called when a pmap initialized by pmap_pinit is being released.
1824 * Should only be called if the map contains no valid mappings.
1827 pmap_release(pmap_t pmap)
1829 struct asid_set *set;
1833 KASSERT(pmap->pm_stats.resident_count == 0,
1834 ("pmap_release: pmap resident count %ld != 0",
1835 pmap->pm_stats.resident_count));
1836 KASSERT(vm_radix_is_empty(&pmap->pm_root),
1837 ("pmap_release: pmap has reserved page table page(s)"));
1838 PMAP_ASSERT_STAGE1(pmap);
1840 set = pmap->pm_asid_set;
1841 KASSERT(set != NULL, ("%s: NULL asid set", __func__));
1843 mtx_lock_spin(&set->asid_set_mutex);
1844 if (COOKIE_TO_EPOCH(pmap->pm_cookie) == set->asid_epoch) {
1845 asid = COOKIE_TO_ASID(pmap->pm_cookie);
1846 KASSERT(asid >= ASID_FIRST_AVAILABLE &&
1847 asid < set->asid_set_size,
1848 ("pmap_release: pmap cookie has out-of-range asid"));
1849 bit_clear(set->asid_set, asid);
1851 mtx_unlock_spin(&set->asid_set_mutex);
1853 m = PHYS_TO_VM_PAGE(pmap->pm_l0_paddr);
1854 vm_page_unwire_noq(m);
1855 vm_page_free_zero(m);
1859 kvm_size(SYSCTL_HANDLER_ARGS)
1861 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS;
1863 return sysctl_handle_long(oidp, &ksize, 0, req);
1865 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG | CTLFLAG_RD | CTLFLAG_MPSAFE,
1866 0, 0, kvm_size, "LU",
1870 kvm_free(SYSCTL_HANDLER_ARGS)
1872 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
1874 return sysctl_handle_long(oidp, &kfree, 0, req);
1876 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG | CTLFLAG_RD | CTLFLAG_MPSAFE,
1877 0, 0, kvm_free, "LU",
1878 "Amount of KVM free");
1881 * grow the number of kernel page table entries, if needed
1884 pmap_growkernel(vm_offset_t addr)
1888 pd_entry_t *l0, *l1, *l2;
1890 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
1892 addr = roundup2(addr, L2_SIZE);
1893 if (addr - 1 >= vm_map_max(kernel_map))
1894 addr = vm_map_max(kernel_map);
1895 while (kernel_vm_end < addr) {
1896 l0 = pmap_l0(kernel_pmap, kernel_vm_end);
1897 KASSERT(pmap_load(l0) != 0,
1898 ("pmap_growkernel: No level 0 kernel entry"));
1900 l1 = pmap_l0_to_l1(l0, kernel_vm_end);
1901 if (pmap_load(l1) == 0) {
1902 /* We need a new PDP entry */
1903 nkpg = vm_page_alloc(NULL, kernel_vm_end >> L1_SHIFT,
1904 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ |
1905 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
1907 panic("pmap_growkernel: no memory to grow kernel");
1908 if ((nkpg->flags & PG_ZERO) == 0)
1909 pmap_zero_page(nkpg);
1910 /* See the dmb() in _pmap_alloc_l3(). */
1912 paddr = VM_PAGE_TO_PHYS(nkpg);
1913 pmap_store(l1, paddr | L1_TABLE);
1914 continue; /* try again */
1916 l2 = pmap_l1_to_l2(l1, kernel_vm_end);
1917 if (pmap_load(l2) != 0) {
1918 kernel_vm_end = (kernel_vm_end + L2_SIZE) & ~L2_OFFSET;
1919 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
1920 kernel_vm_end = vm_map_max(kernel_map);
1926 nkpg = vm_page_alloc(NULL, kernel_vm_end >> L2_SHIFT,
1927 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
1930 panic("pmap_growkernel: no memory to grow kernel");
1931 if ((nkpg->flags & PG_ZERO) == 0)
1932 pmap_zero_page(nkpg);
1933 /* See the dmb() in _pmap_alloc_l3(). */
1935 paddr = VM_PAGE_TO_PHYS(nkpg);
1936 pmap_store(l2, paddr | L2_TABLE);
1938 kernel_vm_end = (kernel_vm_end + L2_SIZE) & ~L2_OFFSET;
1939 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
1940 kernel_vm_end = vm_map_max(kernel_map);
1947 /***************************************************
1948 * page management routines.
1949 ***************************************************/
1951 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
1952 CTASSERT(_NPCM == 3);
1953 CTASSERT(_NPCPV == 168);
1955 static __inline struct pv_chunk *
1956 pv_to_chunk(pv_entry_t pv)
1959 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
1962 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
1964 #define PC_FREE0 0xfffffffffffffffful
1965 #define PC_FREE1 0xfffffffffffffffful
1966 #define PC_FREE2 0x000000fffffffffful
1968 static const uint64_t pc_freemask[_NPCM] = { PC_FREE0, PC_FREE1, PC_FREE2 };
1972 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
1974 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
1975 "Current number of pv entry chunks");
1976 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
1977 "Current number of pv entry chunks allocated");
1978 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
1979 "Current number of pv entry chunks frees");
1980 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
1981 "Number of times tried to get a chunk page but failed.");
1983 static long pv_entry_frees, pv_entry_allocs, pv_entry_count;
1984 static int pv_entry_spare;
1986 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
1987 "Current number of pv entry frees");
1988 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
1989 "Current number of pv entry allocs");
1990 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
1991 "Current number of pv entries");
1992 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
1993 "Current number of spare pv entries");
1998 * We are in a serious low memory condition. Resort to
1999 * drastic measures to free some pages so we can allocate
2000 * another pv entry chunk.
2002 * Returns NULL if PV entries were reclaimed from the specified pmap.
2004 * We do not, however, unmap 2mpages because subsequent accesses will
2005 * allocate per-page pv entries until repromotion occurs, thereby
2006 * exacerbating the shortage of free pv entries.
2009 reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp)
2011 struct pv_chunk *pc, *pc_marker, *pc_marker_end;
2012 struct pv_chunk_header pc_marker_b, pc_marker_end_b;
2013 struct md_page *pvh;
2015 pmap_t next_pmap, pmap;
2016 pt_entry_t *pte, tpte;
2020 struct spglist free;
2022 int bit, field, freed, lvl;
2023 static int active_reclaims = 0;
2025 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
2026 KASSERT(lockp != NULL, ("reclaim_pv_chunk: lockp is NULL"));
2031 bzero(&pc_marker_b, sizeof(pc_marker_b));
2032 bzero(&pc_marker_end_b, sizeof(pc_marker_end_b));
2033 pc_marker = (struct pv_chunk *)&pc_marker_b;
2034 pc_marker_end = (struct pv_chunk *)&pc_marker_end_b;
2036 mtx_lock(&pv_chunks_mutex);
2038 TAILQ_INSERT_HEAD(&pv_chunks, pc_marker, pc_lru);
2039 TAILQ_INSERT_TAIL(&pv_chunks, pc_marker_end, pc_lru);
2040 while ((pc = TAILQ_NEXT(pc_marker, pc_lru)) != pc_marker_end &&
2041 SLIST_EMPTY(&free)) {
2042 next_pmap = pc->pc_pmap;
2043 if (next_pmap == NULL) {
2045 * The next chunk is a marker. However, it is
2046 * not our marker, so active_reclaims must be
2047 * > 1. Consequently, the next_chunk code
2048 * will not rotate the pv_chunks list.
2052 mtx_unlock(&pv_chunks_mutex);
2055 * A pv_chunk can only be removed from the pc_lru list
2056 * when both pv_chunks_mutex is owned and the
2057 * corresponding pmap is locked.
2059 if (pmap != next_pmap) {
2060 if (pmap != NULL && pmap != locked_pmap)
2063 /* Avoid deadlock and lock recursion. */
2064 if (pmap > locked_pmap) {
2065 RELEASE_PV_LIST_LOCK(lockp);
2067 mtx_lock(&pv_chunks_mutex);
2069 } else if (pmap != locked_pmap) {
2070 if (PMAP_TRYLOCK(pmap)) {
2071 mtx_lock(&pv_chunks_mutex);
2074 pmap = NULL; /* pmap is not locked */
2075 mtx_lock(&pv_chunks_mutex);
2076 pc = TAILQ_NEXT(pc_marker, pc_lru);
2078 pc->pc_pmap != next_pmap)
2086 * Destroy every non-wired, 4 KB page mapping in the chunk.
2089 for (field = 0; field < _NPCM; field++) {
2090 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
2091 inuse != 0; inuse &= ~(1UL << bit)) {
2092 bit = ffsl(inuse) - 1;
2093 pv = &pc->pc_pventry[field * 64 + bit];
2095 pde = pmap_pde(pmap, va, &lvl);
2098 pte = pmap_l2_to_l3(pde, va);
2099 tpte = pmap_load(pte);
2100 if ((tpte & ATTR_SW_WIRED) != 0)
2102 tpte = pmap_load_clear(pte);
2103 m = PHYS_TO_VM_PAGE(tpte & ~ATTR_MASK);
2104 if (pmap_pte_dirty(pmap, tpte))
2106 if ((tpte & ATTR_AF) != 0) {
2107 pmap_invalidate_page(pmap, va);
2108 vm_page_aflag_set(m, PGA_REFERENCED);
2110 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
2111 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
2113 if (TAILQ_EMPTY(&m->md.pv_list) &&
2114 (m->flags & PG_FICTITIOUS) == 0) {
2115 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2116 if (TAILQ_EMPTY(&pvh->pv_list)) {
2117 vm_page_aflag_clear(m,
2121 pc->pc_map[field] |= 1UL << bit;
2122 pmap_unuse_pt(pmap, va, pmap_load(pde), &free);
2127 mtx_lock(&pv_chunks_mutex);
2130 /* Every freed mapping is for a 4 KB page. */
2131 pmap_resident_count_dec(pmap, freed);
2132 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
2133 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
2134 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
2135 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2136 if (pc->pc_map[0] == PC_FREE0 && pc->pc_map[1] == PC_FREE1 &&
2137 pc->pc_map[2] == PC_FREE2) {
2138 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
2139 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
2140 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
2141 /* Entire chunk is free; return it. */
2142 m_pc = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
2143 dump_drop_page(m_pc->phys_addr);
2144 mtx_lock(&pv_chunks_mutex);
2145 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2148 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2149 mtx_lock(&pv_chunks_mutex);
2150 /* One freed pv entry in locked_pmap is sufficient. */
2151 if (pmap == locked_pmap)
2155 TAILQ_REMOVE(&pv_chunks, pc_marker, pc_lru);
2156 TAILQ_INSERT_AFTER(&pv_chunks, pc, pc_marker, pc_lru);
2157 if (active_reclaims == 1 && pmap != NULL) {
2159 * Rotate the pv chunks list so that we do not
2160 * scan the same pv chunks that could not be
2161 * freed (because they contained a wired
2162 * and/or superpage mapping) on every
2163 * invocation of reclaim_pv_chunk().
2165 while ((pc = TAILQ_FIRST(&pv_chunks)) != pc_marker) {
2166 MPASS(pc->pc_pmap != NULL);
2167 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2168 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
2172 TAILQ_REMOVE(&pv_chunks, pc_marker, pc_lru);
2173 TAILQ_REMOVE(&pv_chunks, pc_marker_end, pc_lru);
2175 mtx_unlock(&pv_chunks_mutex);
2176 if (pmap != NULL && pmap != locked_pmap)
2178 if (m_pc == NULL && !SLIST_EMPTY(&free)) {
2179 m_pc = SLIST_FIRST(&free);
2180 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
2181 /* Recycle a freed page table page. */
2182 m_pc->ref_count = 1;
2184 vm_page_free_pages_toq(&free, true);
2189 * free the pv_entry back to the free list
2192 free_pv_entry(pmap_t pmap, pv_entry_t pv)
2194 struct pv_chunk *pc;
2195 int idx, field, bit;
2197 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2198 PV_STAT(atomic_add_long(&pv_entry_frees, 1));
2199 PV_STAT(atomic_add_int(&pv_entry_spare, 1));
2200 PV_STAT(atomic_subtract_long(&pv_entry_count, 1));
2201 pc = pv_to_chunk(pv);
2202 idx = pv - &pc->pc_pventry[0];
2205 pc->pc_map[field] |= 1ul << bit;
2206 if (pc->pc_map[0] != PC_FREE0 || pc->pc_map[1] != PC_FREE1 ||
2207 pc->pc_map[2] != PC_FREE2) {
2208 /* 98% of the time, pc is already at the head of the list. */
2209 if (__predict_false(pc != TAILQ_FIRST(&pmap->pm_pvchunk))) {
2210 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2211 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2215 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2220 free_pv_chunk(struct pv_chunk *pc)
2224 mtx_lock(&pv_chunks_mutex);
2225 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2226 mtx_unlock(&pv_chunks_mutex);
2227 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
2228 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
2229 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
2230 /* entire chunk is free, return it */
2231 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
2232 dump_drop_page(m->phys_addr);
2233 vm_page_unwire_noq(m);
2238 * Returns a new PV entry, allocating a new PV chunk from the system when
2239 * needed. If this PV chunk allocation fails and a PV list lock pointer was
2240 * given, a PV chunk is reclaimed from an arbitrary pmap. Otherwise, NULL is
2243 * The given PV list lock may be released.
2246 get_pv_entry(pmap_t pmap, struct rwlock **lockp)
2250 struct pv_chunk *pc;
2253 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2254 PV_STAT(atomic_add_long(&pv_entry_allocs, 1));
2256 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2258 for (field = 0; field < _NPCM; field++) {
2259 if (pc->pc_map[field]) {
2260 bit = ffsl(pc->pc_map[field]) - 1;
2264 if (field < _NPCM) {
2265 pv = &pc->pc_pventry[field * 64 + bit];
2266 pc->pc_map[field] &= ~(1ul << bit);
2267 /* If this was the last item, move it to tail */
2268 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 &&
2269 pc->pc_map[2] == 0) {
2270 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2271 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc,
2274 PV_STAT(atomic_add_long(&pv_entry_count, 1));
2275 PV_STAT(atomic_subtract_int(&pv_entry_spare, 1));
2279 /* No free items, allocate another chunk */
2280 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
2283 if (lockp == NULL) {
2284 PV_STAT(pc_chunk_tryfail++);
2287 m = reclaim_pv_chunk(pmap, lockp);
2291 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
2292 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
2293 dump_add_page(m->phys_addr);
2294 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
2296 pc->pc_map[0] = PC_FREE0 & ~1ul; /* preallocated bit 0 */
2297 pc->pc_map[1] = PC_FREE1;
2298 pc->pc_map[2] = PC_FREE2;
2299 mtx_lock(&pv_chunks_mutex);
2300 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
2301 mtx_unlock(&pv_chunks_mutex);
2302 pv = &pc->pc_pventry[0];
2303 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2304 PV_STAT(atomic_add_long(&pv_entry_count, 1));
2305 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV - 1));
2310 * Ensure that the number of spare PV entries in the specified pmap meets or
2311 * exceeds the given count, "needed".
2313 * The given PV list lock may be released.
2316 reserve_pv_entries(pmap_t pmap, int needed, struct rwlock **lockp)
2318 struct pch new_tail;
2319 struct pv_chunk *pc;
2324 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2325 KASSERT(lockp != NULL, ("reserve_pv_entries: lockp is NULL"));
2328 * Newly allocated PV chunks must be stored in a private list until
2329 * the required number of PV chunks have been allocated. Otherwise,
2330 * reclaim_pv_chunk() could recycle one of these chunks. In
2331 * contrast, these chunks must be added to the pmap upon allocation.
2333 TAILQ_INIT(&new_tail);
2336 TAILQ_FOREACH(pc, &pmap->pm_pvchunk, pc_list) {
2337 bit_count((bitstr_t *)pc->pc_map, 0,
2338 sizeof(pc->pc_map) * NBBY, &free);
2342 if (avail >= needed)
2345 for (reclaimed = false; avail < needed; avail += _NPCPV) {
2346 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
2349 m = reclaim_pv_chunk(pmap, lockp);
2354 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
2355 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
2356 dump_add_page(m->phys_addr);
2357 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
2359 pc->pc_map[0] = PC_FREE0;
2360 pc->pc_map[1] = PC_FREE1;
2361 pc->pc_map[2] = PC_FREE2;
2362 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2363 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
2364 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV));
2367 * The reclaim might have freed a chunk from the current pmap.
2368 * If that chunk contained available entries, we need to
2369 * re-count the number of available entries.
2374 if (!TAILQ_EMPTY(&new_tail)) {
2375 mtx_lock(&pv_chunks_mutex);
2376 TAILQ_CONCAT(&pv_chunks, &new_tail, pc_lru);
2377 mtx_unlock(&pv_chunks_mutex);
2382 * First find and then remove the pv entry for the specified pmap and virtual
2383 * address from the specified pv list. Returns the pv entry if found and NULL
2384 * otherwise. This operation can be performed on pv lists for either 4KB or
2385 * 2MB page mappings.
2387 static __inline pv_entry_t
2388 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2392 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
2393 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
2394 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
2403 * After demotion from a 2MB page mapping to 512 4KB page mappings,
2404 * destroy the pv entry for the 2MB page mapping and reinstantiate the pv
2405 * entries for each of the 4KB page mappings.
2408 pmap_pv_demote_l2(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
2409 struct rwlock **lockp)
2411 struct md_page *pvh;
2412 struct pv_chunk *pc;
2414 vm_offset_t va_last;
2418 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2419 KASSERT((va & L2_OFFSET) == 0,
2420 ("pmap_pv_demote_l2: va is not 2mpage aligned"));
2421 KASSERT((pa & L2_OFFSET) == 0,
2422 ("pmap_pv_demote_l2: pa is not 2mpage aligned"));
2423 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
2426 * Transfer the 2mpage's pv entry for this mapping to the first
2427 * page's pv list. Once this transfer begins, the pv list lock
2428 * must not be released until the last pv entry is reinstantiated.
2430 pvh = pa_to_pvh(pa);
2431 pv = pmap_pvh_remove(pvh, pmap, va);
2432 KASSERT(pv != NULL, ("pmap_pv_demote_l2: pv not found"));
2433 m = PHYS_TO_VM_PAGE(pa);
2434 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2436 /* Instantiate the remaining Ln_ENTRIES - 1 pv entries. */
2437 PV_STAT(atomic_add_long(&pv_entry_allocs, Ln_ENTRIES - 1));
2438 va_last = va + L2_SIZE - PAGE_SIZE;
2440 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2441 KASSERT(pc->pc_map[0] != 0 || pc->pc_map[1] != 0 ||
2442 pc->pc_map[2] != 0, ("pmap_pv_demote_l2: missing spare"));
2443 for (field = 0; field < _NPCM; field++) {
2444 while (pc->pc_map[field]) {
2445 bit = ffsl(pc->pc_map[field]) - 1;
2446 pc->pc_map[field] &= ~(1ul << bit);
2447 pv = &pc->pc_pventry[field * 64 + bit];
2451 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2452 ("pmap_pv_demote_l2: page %p is not managed", m));
2453 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2459 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2460 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2463 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 && pc->pc_map[2] == 0) {
2464 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2465 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2467 PV_STAT(atomic_add_long(&pv_entry_count, Ln_ENTRIES - 1));
2468 PV_STAT(atomic_subtract_int(&pv_entry_spare, Ln_ENTRIES - 1));
2472 * First find and then destroy the pv entry for the specified pmap and virtual
2473 * address. This operation can be performed on pv lists for either 4KB or 2MB
2477 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2481 pv = pmap_pvh_remove(pvh, pmap, va);
2482 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
2483 free_pv_entry(pmap, pv);
2487 * Conditionally create the PV entry for a 4KB page mapping if the required
2488 * memory can be allocated without resorting to reclamation.
2491 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m,
2492 struct rwlock **lockp)
2496 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2497 /* Pass NULL instead of the lock pointer to disable reclamation. */
2498 if ((pv = get_pv_entry(pmap, NULL)) != NULL) {
2500 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
2501 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2509 * Create the PV entry for a 2MB page mapping. Always returns true unless the
2510 * flag PMAP_ENTER_NORECLAIM is specified. If that flag is specified, returns
2511 * false if the PV entry cannot be allocated without resorting to reclamation.
2514 pmap_pv_insert_l2(pmap_t pmap, vm_offset_t va, pd_entry_t l2e, u_int flags,
2515 struct rwlock **lockp)
2517 struct md_page *pvh;
2521 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2522 /* Pass NULL instead of the lock pointer to disable reclamation. */
2523 if ((pv = get_pv_entry(pmap, (flags & PMAP_ENTER_NORECLAIM) != 0 ?
2524 NULL : lockp)) == NULL)
2527 pa = l2e & ~ATTR_MASK;
2528 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
2529 pvh = pa_to_pvh(pa);
2530 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2536 pmap_remove_kernel_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t va)
2538 pt_entry_t newl2, oldl2;
2542 KASSERT(!VIRT_IN_DMAP(va), ("removing direct mapping of %#lx", va));
2543 KASSERT(pmap == kernel_pmap, ("pmap %p is not kernel_pmap", pmap));
2544 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2546 ml3 = pmap_remove_pt_page(pmap, va);
2548 panic("pmap_remove_kernel_l2: Missing pt page");
2550 ml3pa = VM_PAGE_TO_PHYS(ml3);
2551 newl2 = ml3pa | L2_TABLE;
2554 * If this page table page was unmapped by a promotion, then it
2555 * contains valid mappings. Zero it to invalidate those mappings.
2557 if (ml3->valid != 0)
2558 pagezero((void *)PHYS_TO_DMAP(ml3pa));
2561 * Demote the mapping. The caller must have already invalidated the
2562 * mapping (i.e., the "break" in break-before-make).
2564 oldl2 = pmap_load_store(l2, newl2);
2565 KASSERT(oldl2 == 0, ("%s: found existing mapping at %p: %#lx",
2566 __func__, l2, oldl2));
2570 * pmap_remove_l2: Do the things to unmap a level 2 superpage.
2573 pmap_remove_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t sva,
2574 pd_entry_t l1e, struct spglist *free, struct rwlock **lockp)
2576 struct md_page *pvh;
2578 vm_offset_t eva, va;
2581 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2582 KASSERT((sva & L2_OFFSET) == 0, ("pmap_remove_l2: sva is not aligned"));
2583 old_l2 = pmap_load_clear(l2);
2584 KASSERT((old_l2 & ATTR_DESCR_MASK) == L2_BLOCK,
2585 ("pmap_remove_l2: L2e %lx is not a block mapping", old_l2));
2588 * Since a promotion must break the 4KB page mappings before making
2589 * the 2MB page mapping, a pmap_invalidate_page() suffices.
2591 pmap_invalidate_page(pmap, sva);
2593 if (old_l2 & ATTR_SW_WIRED)
2594 pmap->pm_stats.wired_count -= L2_SIZE / PAGE_SIZE;
2595 pmap_resident_count_dec(pmap, L2_SIZE / PAGE_SIZE);
2596 if (old_l2 & ATTR_SW_MANAGED) {
2597 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, old_l2 & ~ATTR_MASK);
2598 pvh = pa_to_pvh(old_l2 & ~ATTR_MASK);
2599 pmap_pvh_free(pvh, pmap, sva);
2600 eva = sva + L2_SIZE;
2601 for (va = sva, m = PHYS_TO_VM_PAGE(old_l2 & ~ATTR_MASK);
2602 va < eva; va += PAGE_SIZE, m++) {
2603 if (pmap_pte_dirty(pmap, old_l2))
2605 if (old_l2 & ATTR_AF)
2606 vm_page_aflag_set(m, PGA_REFERENCED);
2607 if (TAILQ_EMPTY(&m->md.pv_list) &&
2608 TAILQ_EMPTY(&pvh->pv_list))
2609 vm_page_aflag_clear(m, PGA_WRITEABLE);
2612 if (pmap == kernel_pmap) {
2613 pmap_remove_kernel_l2(pmap, l2, sva);
2615 ml3 = pmap_remove_pt_page(pmap, sva);
2617 KASSERT(ml3->valid == VM_PAGE_BITS_ALL,
2618 ("pmap_remove_l2: l3 page not promoted"));
2619 pmap_resident_count_dec(pmap, 1);
2620 KASSERT(ml3->ref_count == NL3PG,
2621 ("pmap_remove_l2: l3 page ref count error"));
2623 pmap_add_delayed_free_list(ml3, free, FALSE);
2626 return (pmap_unuse_pt(pmap, sva, l1e, free));
2630 * pmap_remove_l3: do the things to unmap a page in a process
2633 pmap_remove_l3(pmap_t pmap, pt_entry_t *l3, vm_offset_t va,
2634 pd_entry_t l2e, struct spglist *free, struct rwlock **lockp)
2636 struct md_page *pvh;
2640 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2641 old_l3 = pmap_load_clear(l3);
2642 pmap_invalidate_page(pmap, va);
2643 if (old_l3 & ATTR_SW_WIRED)
2644 pmap->pm_stats.wired_count -= 1;
2645 pmap_resident_count_dec(pmap, 1);
2646 if (old_l3 & ATTR_SW_MANAGED) {
2647 m = PHYS_TO_VM_PAGE(old_l3 & ~ATTR_MASK);
2648 if (pmap_pte_dirty(pmap, old_l3))
2650 if (old_l3 & ATTR_AF)
2651 vm_page_aflag_set(m, PGA_REFERENCED);
2652 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
2653 pmap_pvh_free(&m->md, pmap, va);
2654 if (TAILQ_EMPTY(&m->md.pv_list) &&
2655 (m->flags & PG_FICTITIOUS) == 0) {
2656 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2657 if (TAILQ_EMPTY(&pvh->pv_list))
2658 vm_page_aflag_clear(m, PGA_WRITEABLE);
2661 return (pmap_unuse_pt(pmap, va, l2e, free));
2665 * Remove the specified range of addresses from the L3 page table that is
2666 * identified by the given L2 entry.
2669 pmap_remove_l3_range(pmap_t pmap, pd_entry_t l2e, vm_offset_t sva,
2670 vm_offset_t eva, struct spglist *free, struct rwlock **lockp)
2672 struct md_page *pvh;
2673 struct rwlock *new_lock;
2674 pt_entry_t *l3, old_l3;
2678 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2679 KASSERT(rounddown2(sva, L2_SIZE) + L2_SIZE == roundup2(eva, L2_SIZE),
2680 ("pmap_remove_l3_range: range crosses an L3 page table boundary"));
2681 l3pg = sva < VM_MAXUSER_ADDRESS ? PHYS_TO_VM_PAGE(l2e & ~ATTR_MASK) :
2684 for (l3 = pmap_l2_to_l3(&l2e, sva); sva != eva; l3++, sva += L3_SIZE) {
2685 if (!pmap_l3_valid(pmap_load(l3))) {
2687 pmap_invalidate_range(pmap, va, sva);
2692 old_l3 = pmap_load_clear(l3);
2693 if ((old_l3 & ATTR_SW_WIRED) != 0)
2694 pmap->pm_stats.wired_count--;
2695 pmap_resident_count_dec(pmap, 1);
2696 if ((old_l3 & ATTR_SW_MANAGED) != 0) {
2697 m = PHYS_TO_VM_PAGE(old_l3 & ~ATTR_MASK);
2698 if (pmap_pte_dirty(pmap, old_l3))
2700 if ((old_l3 & ATTR_AF) != 0)
2701 vm_page_aflag_set(m, PGA_REFERENCED);
2702 new_lock = PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m));
2703 if (new_lock != *lockp) {
2704 if (*lockp != NULL) {
2706 * Pending TLB invalidations must be
2707 * performed before the PV list lock is
2708 * released. Otherwise, a concurrent
2709 * pmap_remove_all() on a physical page
2710 * could return while a stale TLB entry
2711 * still provides access to that page.
2714 pmap_invalidate_range(pmap, va,
2723 pmap_pvh_free(&m->md, pmap, sva);
2724 if (TAILQ_EMPTY(&m->md.pv_list) &&
2725 (m->flags & PG_FICTITIOUS) == 0) {
2726 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2727 if (TAILQ_EMPTY(&pvh->pv_list))
2728 vm_page_aflag_clear(m, PGA_WRITEABLE);
2733 if (l3pg != NULL && pmap_unwire_l3(pmap, sva, l3pg, free)) {
2739 pmap_invalidate_range(pmap, va, sva);
2743 * Remove the given range of addresses from the specified map.
2745 * It is assumed that the start and end are properly
2746 * rounded to the page size.
2749 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2751 struct rwlock *lock;
2752 vm_offset_t va_next;
2753 pd_entry_t *l0, *l1, *l2;
2754 pt_entry_t l3_paddr;
2755 struct spglist free;
2758 * Perform an unsynchronized read. This is, however, safe.
2760 if (pmap->pm_stats.resident_count == 0)
2768 for (; sva < eva; sva = va_next) {
2770 if (pmap->pm_stats.resident_count == 0)
2773 l0 = pmap_l0(pmap, sva);
2774 if (pmap_load(l0) == 0) {
2775 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
2781 l1 = pmap_l0_to_l1(l0, sva);
2782 if (pmap_load(l1) == 0) {
2783 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
2790 * Calculate index for next page table.
2792 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
2796 l2 = pmap_l1_to_l2(l1, sva);
2800 l3_paddr = pmap_load(l2);
2802 if ((l3_paddr & ATTR_DESCR_MASK) == L2_BLOCK) {
2803 if (sva + L2_SIZE == va_next && eva >= va_next) {
2804 pmap_remove_l2(pmap, l2, sva, pmap_load(l1),
2807 } else if (pmap_demote_l2_locked(pmap, l2, sva,
2810 l3_paddr = pmap_load(l2);
2814 * Weed out invalid mappings.
2816 if ((l3_paddr & ATTR_DESCR_MASK) != L2_TABLE)
2820 * Limit our scan to either the end of the va represented
2821 * by the current page table page, or to the end of the
2822 * range being removed.
2827 pmap_remove_l3_range(pmap, l3_paddr, sva, va_next, &free,
2833 vm_page_free_pages_toq(&free, true);
2837 * Routine: pmap_remove_all
2839 * Removes this physical page from
2840 * all physical maps in which it resides.
2841 * Reflects back modify bits to the pager.
2844 * Original versions of this routine were very
2845 * inefficient because they iteratively called
2846 * pmap_remove (slow...)
2850 pmap_remove_all(vm_page_t m)
2852 struct md_page *pvh;
2855 struct rwlock *lock;
2856 pd_entry_t *pde, tpde;
2857 pt_entry_t *pte, tpte;
2859 struct spglist free;
2860 int lvl, pvh_gen, md_gen;
2862 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2863 ("pmap_remove_all: page %p is not managed", m));
2865 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
2866 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
2867 pa_to_pvh(VM_PAGE_TO_PHYS(m));
2870 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
2872 if (!PMAP_TRYLOCK(pmap)) {
2873 pvh_gen = pvh->pv_gen;
2877 if (pvh_gen != pvh->pv_gen) {
2884 pte = pmap_pte(pmap, va, &lvl);
2885 KASSERT(pte != NULL,
2886 ("pmap_remove_all: no page table entry found"));
2888 ("pmap_remove_all: invalid pte level %d", lvl));
2890 pmap_demote_l2_locked(pmap, pte, va, &lock);
2893 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
2895 PMAP_ASSERT_STAGE1(pmap);
2896 if (!PMAP_TRYLOCK(pmap)) {
2897 pvh_gen = pvh->pv_gen;
2898 md_gen = m->md.pv_gen;
2902 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
2908 pmap_resident_count_dec(pmap, 1);
2910 pde = pmap_pde(pmap, pv->pv_va, &lvl);
2911 KASSERT(pde != NULL,
2912 ("pmap_remove_all: no page directory entry found"));
2914 ("pmap_remove_all: invalid pde level %d", lvl));
2915 tpde = pmap_load(pde);
2917 pte = pmap_l2_to_l3(pde, pv->pv_va);
2918 tpte = pmap_load_clear(pte);
2919 if (tpte & ATTR_SW_WIRED)
2920 pmap->pm_stats.wired_count--;
2921 if ((tpte & ATTR_AF) != 0) {
2922 pmap_invalidate_page(pmap, pv->pv_va);
2923 vm_page_aflag_set(m, PGA_REFERENCED);
2927 * Update the vm_page_t clean and reference bits.
2929 if (pmap_pte_dirty(pmap, tpte))
2931 pmap_unuse_pt(pmap, pv->pv_va, tpde, &free);
2932 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
2934 free_pv_entry(pmap, pv);
2937 vm_page_aflag_clear(m, PGA_WRITEABLE);
2939 vm_page_free_pages_toq(&free, true);
2943 * pmap_protect_l2: do the things to protect a 2MB page in a pmap
2946 pmap_protect_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t sva, pt_entry_t mask,
2952 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2953 PMAP_ASSERT_STAGE1(pmap);
2954 KASSERT((sva & L2_OFFSET) == 0,
2955 ("pmap_protect_l2: sva is not 2mpage aligned"));
2956 old_l2 = pmap_load(l2);
2957 KASSERT((old_l2 & ATTR_DESCR_MASK) == L2_BLOCK,
2958 ("pmap_protect_l2: L2e %lx is not a block mapping", old_l2));
2961 * Return if the L2 entry already has the desired access restrictions
2965 if ((old_l2 & mask) == nbits)
2969 * When a dirty read/write superpage mapping is write protected,
2970 * update the dirty field of each of the superpage's constituent 4KB
2973 if ((old_l2 & ATTR_SW_MANAGED) != 0 &&
2974 (nbits & ATTR_S1_AP(ATTR_S1_AP_RO)) != 0 &&
2975 pmap_pte_dirty(pmap, old_l2)) {
2976 m = PHYS_TO_VM_PAGE(old_l2 & ~ATTR_MASK);
2977 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
2981 if (!atomic_fcmpset_64(l2, &old_l2, (old_l2 & ~mask) | nbits))
2985 * Since a promotion must break the 4KB page mappings before making
2986 * the 2MB page mapping, a pmap_invalidate_page() suffices.
2988 pmap_invalidate_page(pmap, sva);
2992 * Set the physical protection on the
2993 * specified range of this map as requested.
2996 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
2998 vm_offset_t va, va_next;
2999 pd_entry_t *l0, *l1, *l2;
3000 pt_entry_t *l3p, l3, mask, nbits;
3002 PMAP_ASSERT_STAGE1(pmap);
3003 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
3004 if (prot == VM_PROT_NONE) {
3005 pmap_remove(pmap, sva, eva);
3010 if ((prot & VM_PROT_WRITE) == 0) {
3011 mask |= ATTR_S1_AP_RW_BIT | ATTR_SW_DBM;
3012 nbits |= ATTR_S1_AP(ATTR_S1_AP_RO);
3014 if ((prot & VM_PROT_EXECUTE) == 0) {
3016 nbits |= ATTR_S1_XN;
3022 for (; sva < eva; sva = va_next) {
3024 l0 = pmap_l0(pmap, sva);
3025 if (pmap_load(l0) == 0) {
3026 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
3032 l1 = pmap_l0_to_l1(l0, sva);
3033 if (pmap_load(l1) == 0) {
3034 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
3040 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
3044 l2 = pmap_l1_to_l2(l1, sva);
3045 if (pmap_load(l2) == 0)
3048 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK) {
3049 if (sva + L2_SIZE == va_next && eva >= va_next) {
3050 pmap_protect_l2(pmap, l2, sva, mask, nbits);
3052 } else if (pmap_demote_l2(pmap, l2, sva) == NULL)
3055 KASSERT((pmap_load(l2) & ATTR_DESCR_MASK) == L2_TABLE,
3056 ("pmap_protect: Invalid L2 entry after demotion"));
3062 for (l3p = pmap_l2_to_l3(l2, sva); sva != va_next; l3p++,
3064 l3 = pmap_load(l3p);
3067 * Go to the next L3 entry if the current one is
3068 * invalid or already has the desired access
3069 * restrictions in place. (The latter case occurs
3070 * frequently. For example, in a "buildworld"
3071 * workload, almost 1 out of 4 L3 entries already
3072 * have the desired restrictions.)
3074 if (!pmap_l3_valid(l3) || (l3 & mask) == nbits) {
3075 if (va != va_next) {
3076 pmap_invalidate_range(pmap, va, sva);
3083 * When a dirty read/write mapping is write protected,
3084 * update the page's dirty field.
3086 if ((l3 & ATTR_SW_MANAGED) != 0 &&
3087 (nbits & ATTR_S1_AP(ATTR_S1_AP_RO)) != 0 &&
3088 pmap_pte_dirty(pmap, l3))
3089 vm_page_dirty(PHYS_TO_VM_PAGE(l3 & ~ATTR_MASK));
3091 if (!atomic_fcmpset_64(l3p, &l3, (l3 & ~mask) | nbits))
3097 pmap_invalidate_range(pmap, va, sva);
3103 * Inserts the specified page table page into the specified pmap's collection
3104 * of idle page table pages. Each of a pmap's page table pages is responsible
3105 * for mapping a distinct range of virtual addresses. The pmap's collection is
3106 * ordered by this virtual address range.
3108 * If "promoted" is false, then the page table page "mpte" must be zero filled.
3111 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte, bool promoted)
3114 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3115 mpte->valid = promoted ? VM_PAGE_BITS_ALL : 0;
3116 return (vm_radix_insert(&pmap->pm_root, mpte));
3120 * Removes the page table page mapping the specified virtual address from the
3121 * specified pmap's collection of idle page table pages, and returns it.
3122 * Otherwise, returns NULL if there is no page table page corresponding to the
3123 * specified virtual address.
3125 static __inline vm_page_t
3126 pmap_remove_pt_page(pmap_t pmap, vm_offset_t va)
3129 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3130 return (vm_radix_remove(&pmap->pm_root, pmap_l2_pindex(va)));
3134 * Performs a break-before-make update of a pmap entry. This is needed when
3135 * either promoting or demoting pages to ensure the TLB doesn't get into an
3136 * inconsistent state.
3139 pmap_update_entry(pmap_t pmap, pd_entry_t *pte, pd_entry_t newpte,
3140 vm_offset_t va, vm_size_t size)
3144 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3147 * Ensure we don't get switched out with the page table in an
3148 * inconsistent state. We also need to ensure no interrupts fire
3149 * as they may make use of an address we are about to invalidate.
3151 intr = intr_disable();
3154 * Clear the old mapping's valid bit, but leave the rest of the entry
3155 * unchanged, so that a lockless, concurrent pmap_kextract() can still
3156 * lookup the physical address.
3158 pmap_clear_bits(pte, ATTR_DESCR_VALID);
3159 pmap_invalidate_range(pmap, va, va + size);
3161 /* Create the new mapping */
3162 pmap_store(pte, newpte);
3168 #if VM_NRESERVLEVEL > 0
3170 * After promotion from 512 4KB page mappings to a single 2MB page mapping,
3171 * replace the many pv entries for the 4KB page mappings by a single pv entry
3172 * for the 2MB page mapping.
3175 pmap_pv_promote_l2(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
3176 struct rwlock **lockp)
3178 struct md_page *pvh;
3180 vm_offset_t va_last;
3183 KASSERT((pa & L2_OFFSET) == 0,
3184 ("pmap_pv_promote_l2: pa is not 2mpage aligned"));
3185 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
3188 * Transfer the first page's pv entry for this mapping to the 2mpage's
3189 * pv list. Aside from avoiding the cost of a call to get_pv_entry(),
3190 * a transfer avoids the possibility that get_pv_entry() calls
3191 * reclaim_pv_chunk() and that reclaim_pv_chunk() removes one of the
3192 * mappings that is being promoted.
3194 m = PHYS_TO_VM_PAGE(pa);
3195 va = va & ~L2_OFFSET;
3196 pv = pmap_pvh_remove(&m->md, pmap, va);
3197 KASSERT(pv != NULL, ("pmap_pv_promote_l2: pv not found"));
3198 pvh = pa_to_pvh(pa);
3199 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
3201 /* Free the remaining NPTEPG - 1 pv entries. */
3202 va_last = va + L2_SIZE - PAGE_SIZE;
3206 pmap_pvh_free(&m->md, pmap, va);
3207 } while (va < va_last);
3211 * Tries to promote the 512, contiguous 4KB page mappings that are within a
3212 * single level 2 table entry to a single 2MB page mapping. For promotion
3213 * to occur, two conditions must be met: (1) the 4KB page mappings must map
3214 * aligned, contiguous physical memory and (2) the 4KB page mappings must have
3215 * identical characteristics.
3218 pmap_promote_l2(pmap_t pmap, pd_entry_t *l2, vm_offset_t va,
3219 struct rwlock **lockp)
3221 pt_entry_t *firstl3, *l3, newl2, oldl3, pa;
3225 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3226 PMAP_ASSERT_STAGE1(pmap);
3228 sva = va & ~L2_OFFSET;
3229 firstl3 = pmap_l2_to_l3(l2, sva);
3230 newl2 = pmap_load(firstl3);
3233 if (((newl2 & (~ATTR_MASK | ATTR_AF)) & L2_OFFSET) != ATTR_AF) {
3234 atomic_add_long(&pmap_l2_p_failures, 1);
3235 CTR2(KTR_PMAP, "pmap_promote_l2: failure for va %#lx"
3236 " in pmap %p", va, pmap);
3240 if ((newl2 & (ATTR_S1_AP_RW_BIT | ATTR_SW_DBM)) ==
3241 (ATTR_S1_AP(ATTR_S1_AP_RO) | ATTR_SW_DBM)) {
3242 if (!atomic_fcmpset_64(l2, &newl2, newl2 & ~ATTR_SW_DBM))
3244 newl2 &= ~ATTR_SW_DBM;
3247 pa = newl2 + L2_SIZE - PAGE_SIZE;
3248 for (l3 = firstl3 + NL3PG - 1; l3 > firstl3; l3--) {
3249 oldl3 = pmap_load(l3);
3251 if ((oldl3 & (ATTR_S1_AP_RW_BIT | ATTR_SW_DBM)) ==
3252 (ATTR_S1_AP(ATTR_S1_AP_RO) | ATTR_SW_DBM)) {
3253 if (!atomic_fcmpset_64(l3, &oldl3, oldl3 &
3256 oldl3 &= ~ATTR_SW_DBM;
3259 atomic_add_long(&pmap_l2_p_failures, 1);
3260 CTR2(KTR_PMAP, "pmap_promote_l2: failure for va %#lx"
3261 " in pmap %p", va, pmap);
3268 * Save the page table page in its current state until the L2
3269 * mapping the superpage is demoted by pmap_demote_l2() or
3270 * destroyed by pmap_remove_l3().
3272 mpte = PHYS_TO_VM_PAGE(pmap_load(l2) & ~ATTR_MASK);
3273 KASSERT(mpte >= vm_page_array &&
3274 mpte < &vm_page_array[vm_page_array_size],
3275 ("pmap_promote_l2: page table page is out of range"));
3276 KASSERT(mpte->pindex == pmap_l2_pindex(va),
3277 ("pmap_promote_l2: page table page's pindex is wrong"));
3278 if (pmap_insert_pt_page(pmap, mpte, true)) {
3279 atomic_add_long(&pmap_l2_p_failures, 1);
3281 "pmap_promote_l2: failure for va %#lx in pmap %p", va,
3286 if ((newl2 & ATTR_SW_MANAGED) != 0)
3287 pmap_pv_promote_l2(pmap, va, newl2 & ~ATTR_MASK, lockp);
3289 newl2 &= ~ATTR_DESCR_MASK;
3292 pmap_update_entry(pmap, l2, newl2, sva, L2_SIZE);
3294 atomic_add_long(&pmap_l2_promotions, 1);
3295 CTR2(KTR_PMAP, "pmap_promote_l2: success for va %#lx in pmap %p", va,
3298 #endif /* VM_NRESERVLEVEL > 0 */
3301 * Insert the given physical page (p) at
3302 * the specified virtual address (v) in the
3303 * target physical map with the protection requested.
3305 * If specified, the page will be wired down, meaning
3306 * that the related pte can not be reclaimed.
3308 * NB: This is the only routine which MAY NOT lazy-evaluate
3309 * or lose information. That is, this routine must actually
3310 * insert this page into the given map NOW.
3313 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
3314 u_int flags, int8_t psind)
3316 struct rwlock *lock;
3318 pt_entry_t new_l3, orig_l3;
3319 pt_entry_t *l2, *l3;
3326 PMAP_ASSERT_STAGE1(pmap);
3328 va = trunc_page(va);
3329 if ((m->oflags & VPO_UNMANAGED) == 0)
3330 VM_PAGE_OBJECT_BUSY_ASSERT(m);
3331 pa = VM_PAGE_TO_PHYS(m);
3332 new_l3 = (pt_entry_t)(pa | ATTR_DEFAULT | ATTR_S1_IDX(m->md.pv_memattr) |
3334 if ((prot & VM_PROT_WRITE) == 0)
3335 new_l3 |= ATTR_S1_AP(ATTR_S1_AP_RO);
3336 if ((prot & VM_PROT_EXECUTE) == 0 ||
3337 m->md.pv_memattr == VM_MEMATTR_DEVICE)
3338 new_l3 |= ATTR_S1_XN;
3339 if ((flags & PMAP_ENTER_WIRED) != 0)
3340 new_l3 |= ATTR_SW_WIRED;
3341 if (va < VM_MAXUSER_ADDRESS)
3342 new_l3 |= ATTR_S1_AP(ATTR_S1_AP_USER) | ATTR_S1_PXN;
3344 new_l3 |= ATTR_S1_UXN;
3345 if (pmap != kernel_pmap)
3346 new_l3 |= ATTR_S1_nG;
3347 if ((m->oflags & VPO_UNMANAGED) == 0) {
3348 new_l3 |= ATTR_SW_MANAGED;
3349 if ((prot & VM_PROT_WRITE) != 0) {
3350 new_l3 |= ATTR_SW_DBM;
3351 if ((flags & VM_PROT_WRITE) == 0)
3352 new_l3 |= ATTR_S1_AP(ATTR_S1_AP_RO);
3356 CTR2(KTR_PMAP, "pmap_enter: %.16lx -> %.16lx", va, pa);
3361 /* Assert the required virtual and physical alignment. */
3362 KASSERT((va & L2_OFFSET) == 0, ("pmap_enter: va unaligned"));
3363 KASSERT(m->psind > 0, ("pmap_enter: m->psind < psind"));
3364 rv = pmap_enter_l2(pmap, va, (new_l3 & ~L3_PAGE) | L2_BLOCK,
3371 * In the case that a page table page is not
3372 * resident, we are creating it here.
3375 pde = pmap_pde(pmap, va, &lvl);
3376 if (pde != NULL && lvl == 2) {
3377 l3 = pmap_l2_to_l3(pde, va);
3378 if (va < VM_MAXUSER_ADDRESS && mpte == NULL) {
3379 mpte = PHYS_TO_VM_PAGE(pmap_load(pde) & ~ATTR_MASK);
3383 } else if (pde != NULL && lvl == 1) {
3384 l2 = pmap_l1_to_l2(pde, va);
3385 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK &&
3386 (l3 = pmap_demote_l2_locked(pmap, l2, va, &lock)) != NULL) {
3387 l3 = &l3[pmap_l3_index(va)];
3388 if (va < VM_MAXUSER_ADDRESS) {
3389 mpte = PHYS_TO_VM_PAGE(
3390 pmap_load(l2) & ~ATTR_MASK);
3395 /* We need to allocate an L3 table. */
3397 if (va < VM_MAXUSER_ADDRESS) {
3398 nosleep = (flags & PMAP_ENTER_NOSLEEP) != 0;
3401 * We use _pmap_alloc_l3() instead of pmap_alloc_l3() in order
3402 * to handle the possibility that a superpage mapping for "va"
3403 * was created while we slept.
3405 mpte = _pmap_alloc_l3(pmap, pmap_l2_pindex(va),
3406 nosleep ? NULL : &lock);
3407 if (mpte == NULL && nosleep) {
3408 CTR0(KTR_PMAP, "pmap_enter: mpte == NULL");
3409 rv = KERN_RESOURCE_SHORTAGE;
3414 panic("pmap_enter: missing L3 table for kernel va %#lx", va);
3417 orig_l3 = pmap_load(l3);
3418 opa = orig_l3 & ~ATTR_MASK;
3422 * Is the specified virtual address already mapped?
3424 if (pmap_l3_valid(orig_l3)) {
3426 * Wiring change, just update stats. We don't worry about
3427 * wiring PT pages as they remain resident as long as there
3428 * are valid mappings in them. Hence, if a user page is wired,
3429 * the PT page will be also.
3431 if ((flags & PMAP_ENTER_WIRED) != 0 &&
3432 (orig_l3 & ATTR_SW_WIRED) == 0)
3433 pmap->pm_stats.wired_count++;
3434 else if ((flags & PMAP_ENTER_WIRED) == 0 &&
3435 (orig_l3 & ATTR_SW_WIRED) != 0)
3436 pmap->pm_stats.wired_count--;
3439 * Remove the extra PT page reference.
3443 KASSERT(mpte->ref_count > 0,
3444 ("pmap_enter: missing reference to page table page,"
3449 * Has the physical page changed?
3453 * No, might be a protection or wiring change.
3455 if ((orig_l3 & ATTR_SW_MANAGED) != 0 &&
3456 (new_l3 & ATTR_SW_DBM) != 0)
3457 vm_page_aflag_set(m, PGA_WRITEABLE);
3462 * The physical page has changed. Temporarily invalidate
3465 orig_l3 = pmap_load_clear(l3);
3466 KASSERT((orig_l3 & ~ATTR_MASK) == opa,
3467 ("pmap_enter: unexpected pa update for %#lx", va));
3468 if ((orig_l3 & ATTR_SW_MANAGED) != 0) {
3469 om = PHYS_TO_VM_PAGE(opa);
3472 * The pmap lock is sufficient to synchronize with
3473 * concurrent calls to pmap_page_test_mappings() and
3474 * pmap_ts_referenced().
3476 if (pmap_pte_dirty(pmap, orig_l3))
3478 if ((orig_l3 & ATTR_AF) != 0) {
3479 pmap_invalidate_page(pmap, va);
3480 vm_page_aflag_set(om, PGA_REFERENCED);
3482 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, opa);
3483 pv = pmap_pvh_remove(&om->md, pmap, va);
3484 if ((m->oflags & VPO_UNMANAGED) != 0)
3485 free_pv_entry(pmap, pv);
3486 if ((om->a.flags & PGA_WRITEABLE) != 0 &&
3487 TAILQ_EMPTY(&om->md.pv_list) &&
3488 ((om->flags & PG_FICTITIOUS) != 0 ||
3489 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
3490 vm_page_aflag_clear(om, PGA_WRITEABLE);
3492 KASSERT((orig_l3 & ATTR_AF) != 0,
3493 ("pmap_enter: unmanaged mapping lacks ATTR_AF"));
3494 pmap_invalidate_page(pmap, va);
3499 * Increment the counters.
3501 if ((new_l3 & ATTR_SW_WIRED) != 0)
3502 pmap->pm_stats.wired_count++;
3503 pmap_resident_count_inc(pmap, 1);
3506 * Enter on the PV list if part of our managed memory.
3508 if ((m->oflags & VPO_UNMANAGED) == 0) {
3510 pv = get_pv_entry(pmap, &lock);
3513 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, pa);
3514 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3516 if ((new_l3 & ATTR_SW_DBM) != 0)
3517 vm_page_aflag_set(m, PGA_WRITEABLE);
3522 * Sync icache if exec permission and attribute VM_MEMATTR_WRITE_BACK
3523 * is set. Do it now, before the mapping is stored and made
3524 * valid for hardware table walk. If done later, then other can
3525 * access this page before caches are properly synced.
3526 * Don't do it for kernel memory which is mapped with exec
3527 * permission even if the memory isn't going to hold executable
3528 * code. The only time when icache sync is needed is after
3529 * kernel module is loaded and the relocation info is processed.
3530 * And it's done in elf_cpu_load_file().
3532 if ((prot & VM_PROT_EXECUTE) && pmap != kernel_pmap &&
3533 m->md.pv_memattr == VM_MEMATTR_WRITE_BACK &&
3534 (opa != pa || (orig_l3 & ATTR_S1_XN)))
3535 cpu_icache_sync_range(PHYS_TO_DMAP(pa), PAGE_SIZE);
3538 * Update the L3 entry
3540 if (pmap_l3_valid(orig_l3)) {
3541 KASSERT(opa == pa, ("pmap_enter: invalid update"));
3542 if ((orig_l3 & ~ATTR_AF) != (new_l3 & ~ATTR_AF)) {
3543 /* same PA, different attributes */
3544 orig_l3 = pmap_load_store(l3, new_l3);
3545 pmap_invalidate_page(pmap, va);
3546 if ((orig_l3 & ATTR_SW_MANAGED) != 0 &&
3547 pmap_pte_dirty(pmap, orig_l3))
3552 * This can happens if multiple threads simultaneously
3553 * access not yet mapped page. This bad for performance
3554 * since this can cause full demotion-NOP-promotion
3556 * Another possible reasons are:
3557 * - VM and pmap memory layout are diverged
3558 * - tlb flush is missing somewhere and CPU doesn't see
3561 CTR4(KTR_PMAP, "%s: already mapped page - "
3562 "pmap %p va 0x%#lx pte 0x%lx",
3563 __func__, pmap, va, new_l3);
3567 pmap_store(l3, new_l3);
3571 #if VM_NRESERVLEVEL > 0
3572 if ((mpte == NULL || mpte->ref_count == NL3PG) &&
3573 pmap_ps_enabled(pmap) &&
3574 (m->flags & PG_FICTITIOUS) == 0 &&
3575 vm_reserv_level_iffullpop(m) == 0) {
3576 pmap_promote_l2(pmap, pde, va, &lock);
3589 * Tries to create a read- and/or execute-only 2MB page mapping. Returns true
3590 * if successful. Returns false if (1) a page table page cannot be allocated
3591 * without sleeping, (2) a mapping already exists at the specified virtual
3592 * address, or (3) a PV entry cannot be allocated without reclaiming another
3596 pmap_enter_2mpage(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
3597 struct rwlock **lockp)
3601 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3602 PMAP_ASSERT_STAGE1(pmap);
3604 new_l2 = (pd_entry_t)(VM_PAGE_TO_PHYS(m) | ATTR_DEFAULT |
3605 ATTR_S1_IDX(m->md.pv_memattr) | ATTR_S1_AP(ATTR_S1_AP_RO) |
3607 if ((m->oflags & VPO_UNMANAGED) == 0) {
3608 new_l2 |= ATTR_SW_MANAGED;
3611 if ((prot & VM_PROT_EXECUTE) == 0 ||
3612 m->md.pv_memattr == VM_MEMATTR_DEVICE)
3613 new_l2 |= ATTR_S1_XN;
3614 if (va < VM_MAXUSER_ADDRESS)
3615 new_l2 |= ATTR_S1_AP(ATTR_S1_AP_USER) | ATTR_S1_PXN;
3617 new_l2 |= ATTR_S1_UXN;
3618 if (pmap != kernel_pmap)
3619 new_l2 |= ATTR_S1_nG;
3620 return (pmap_enter_l2(pmap, va, new_l2, PMAP_ENTER_NOSLEEP |
3621 PMAP_ENTER_NOREPLACE | PMAP_ENTER_NORECLAIM, NULL, lockp) ==
3626 * Returns true if every page table entry in the specified page table is
3630 pmap_every_pte_zero(vm_paddr_t pa)
3632 pt_entry_t *pt_end, *pte;
3634 KASSERT((pa & PAGE_MASK) == 0, ("pa is misaligned"));
3635 pte = (pt_entry_t *)PHYS_TO_DMAP(pa);
3636 for (pt_end = pte + Ln_ENTRIES; pte < pt_end; pte++) {
3644 * Tries to create the specified 2MB page mapping. Returns KERN_SUCCESS if
3645 * the mapping was created, and either KERN_FAILURE or KERN_RESOURCE_SHORTAGE
3646 * otherwise. Returns KERN_FAILURE if PMAP_ENTER_NOREPLACE was specified and
3647 * a mapping already exists at the specified virtual address. Returns
3648 * KERN_RESOURCE_SHORTAGE if PMAP_ENTER_NOSLEEP was specified and a page table
3649 * page allocation failed. Returns KERN_RESOURCE_SHORTAGE if
3650 * PMAP_ENTER_NORECLAIM was specified and a PV entry allocation failed.
3652 * The parameter "m" is only used when creating a managed, writeable mapping.
3655 pmap_enter_l2(pmap_t pmap, vm_offset_t va, pd_entry_t new_l2, u_int flags,
3656 vm_page_t m, struct rwlock **lockp)
3658 struct spglist free;
3659 pd_entry_t *l2, old_l2;
3662 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3664 if ((l2 = pmap_alloc_l2(pmap, va, &l2pg, (flags &
3665 PMAP_ENTER_NOSLEEP) != 0 ? NULL : lockp)) == NULL) {
3666 CTR2(KTR_PMAP, "pmap_enter_l2: failure for va %#lx in pmap %p",
3668 return (KERN_RESOURCE_SHORTAGE);
3672 * If there are existing mappings, either abort or remove them.
3674 if ((old_l2 = pmap_load(l2)) != 0) {
3675 KASSERT(l2pg == NULL || l2pg->ref_count > 1,
3676 ("pmap_enter_l2: l2pg's ref count is too low"));
3677 if ((flags & PMAP_ENTER_NOREPLACE) != 0 && (va <
3678 VM_MAXUSER_ADDRESS || (old_l2 & ATTR_DESCR_MASK) ==
3679 L2_BLOCK || !pmap_every_pte_zero(old_l2 & ~ATTR_MASK))) {
3682 CTR2(KTR_PMAP, "pmap_enter_l2: failure for va %#lx"
3683 " in pmap %p", va, pmap);
3684 return (KERN_FAILURE);
3687 if ((old_l2 & ATTR_DESCR_MASK) == L2_BLOCK)
3688 (void)pmap_remove_l2(pmap, l2, va,
3689 pmap_load(pmap_l1(pmap, va)), &free, lockp);
3691 pmap_remove_l3_range(pmap, old_l2, va, va + L2_SIZE,
3693 if (va < VM_MAXUSER_ADDRESS) {
3694 vm_page_free_pages_toq(&free, true);
3695 KASSERT(pmap_load(l2) == 0,
3696 ("pmap_enter_l2: non-zero L2 entry %p", l2));
3698 KASSERT(SLIST_EMPTY(&free),
3699 ("pmap_enter_l2: freed kernel page table page"));
3702 * Both pmap_remove_l2() and pmap_remove_l3_range()
3703 * will leave the kernel page table page zero filled.
3704 * Nonetheless, the TLB could have an intermediate
3705 * entry for the kernel page table page.
3707 mt = PHYS_TO_VM_PAGE(pmap_load(l2) & ~ATTR_MASK);
3708 if (pmap_insert_pt_page(pmap, mt, false))
3709 panic("pmap_enter_l2: trie insert failed");
3711 pmap_invalidate_page(pmap, va);
3715 if ((new_l2 & ATTR_SW_MANAGED) != 0) {
3717 * Abort this mapping if its PV entry could not be created.
3719 if (!pmap_pv_insert_l2(pmap, va, new_l2, flags, lockp)) {
3721 pmap_abort_ptp(pmap, va, l2pg);
3723 "pmap_enter_l2: failure for va %#lx in pmap %p",
3725 return (KERN_RESOURCE_SHORTAGE);
3727 if ((new_l2 & ATTR_SW_DBM) != 0)
3728 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
3729 vm_page_aflag_set(mt, PGA_WRITEABLE);
3733 * Increment counters.
3735 if ((new_l2 & ATTR_SW_WIRED) != 0)
3736 pmap->pm_stats.wired_count += L2_SIZE / PAGE_SIZE;
3737 pmap->pm_stats.resident_count += L2_SIZE / PAGE_SIZE;
3740 * Map the superpage.
3742 pmap_store(l2, new_l2);
3745 atomic_add_long(&pmap_l2_mappings, 1);
3746 CTR2(KTR_PMAP, "pmap_enter_l2: success for va %#lx in pmap %p",
3749 return (KERN_SUCCESS);
3753 * Maps a sequence of resident pages belonging to the same object.
3754 * The sequence begins with the given page m_start. This page is
3755 * mapped at the given virtual address start. Each subsequent page is
3756 * mapped at a virtual address that is offset from start by the same
3757 * amount as the page is offset from m_start within the object. The
3758 * last page in the sequence is the page with the largest offset from
3759 * m_start that can be mapped at a virtual address less than the given
3760 * virtual address end. Not every virtual page between start and end
3761 * is mapped; only those for which a resident page exists with the
3762 * corresponding offset from m_start are mapped.
3765 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
3766 vm_page_t m_start, vm_prot_t prot)
3768 struct rwlock *lock;
3771 vm_pindex_t diff, psize;
3773 VM_OBJECT_ASSERT_LOCKED(m_start->object);
3775 psize = atop(end - start);
3780 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
3781 va = start + ptoa(diff);
3782 if ((va & L2_OFFSET) == 0 && va + L2_SIZE <= end &&
3783 m->psind == 1 && pmap_ps_enabled(pmap) &&
3784 pmap_enter_2mpage(pmap, va, m, prot, &lock))
3785 m = &m[L2_SIZE / PAGE_SIZE - 1];
3787 mpte = pmap_enter_quick_locked(pmap, va, m, prot, mpte,
3789 m = TAILQ_NEXT(m, listq);
3797 * this code makes some *MAJOR* assumptions:
3798 * 1. Current pmap & pmap exists.
3801 * 4. No page table pages.
3802 * but is *MUCH* faster than pmap_enter...
3806 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3808 struct rwlock *lock;
3812 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL, &lock);
3819 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
3820 vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp)
3823 pt_entry_t *l2, *l3, l3_val;
3827 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
3828 (m->oflags & VPO_UNMANAGED) != 0,
3829 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
3830 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3831 PMAP_ASSERT_STAGE1(pmap);
3833 CTR2(KTR_PMAP, "pmap_enter_quick_locked: %p %lx", pmap, va);
3835 * In the case that a page table page is not
3836 * resident, we are creating it here.
3838 if (va < VM_MAXUSER_ADDRESS) {
3839 vm_pindex_t l2pindex;
3842 * Calculate pagetable page index
3844 l2pindex = pmap_l2_pindex(va);
3845 if (mpte && (mpte->pindex == l2pindex)) {
3851 pde = pmap_pde(pmap, va, &lvl);
3854 * If the page table page is mapped, we just increment
3855 * the hold count, and activate it. Otherwise, we
3856 * attempt to allocate a page table page. If this
3857 * attempt fails, we don't retry. Instead, we give up.
3860 l2 = pmap_l1_to_l2(pde, va);
3861 if ((pmap_load(l2) & ATTR_DESCR_MASK) ==
3865 if (lvl == 2 && pmap_load(pde) != 0) {
3867 PHYS_TO_VM_PAGE(pmap_load(pde) & ~ATTR_MASK);
3871 * Pass NULL instead of the PV list lock
3872 * pointer, because we don't intend to sleep.
3874 mpte = _pmap_alloc_l3(pmap, l2pindex, NULL);
3879 l3 = (pt_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpte));
3880 l3 = &l3[pmap_l3_index(va)];
3883 pde = pmap_pde(kernel_pmap, va, &lvl);
3884 KASSERT(pde != NULL,
3885 ("pmap_enter_quick_locked: Invalid page entry, va: 0x%lx",
3888 ("pmap_enter_quick_locked: Invalid level %d", lvl));
3889 l3 = pmap_l2_to_l3(pde, va);
3893 * Abort if a mapping already exists.
3895 if (pmap_load(l3) != 0) {
3902 * Enter on the PV list if part of our managed memory.
3904 if ((m->oflags & VPO_UNMANAGED) == 0 &&
3905 !pmap_try_insert_pv_entry(pmap, va, m, lockp)) {
3907 pmap_abort_ptp(pmap, va, mpte);
3912 * Increment counters
3914 pmap_resident_count_inc(pmap, 1);
3916 pa = VM_PAGE_TO_PHYS(m);
3917 l3_val = pa | ATTR_DEFAULT | ATTR_S1_IDX(m->md.pv_memattr) |
3918 ATTR_S1_AP(ATTR_S1_AP_RO) | L3_PAGE;
3919 if ((prot & VM_PROT_EXECUTE) == 0 ||
3920 m->md.pv_memattr == VM_MEMATTR_DEVICE)
3921 l3_val |= ATTR_S1_XN;
3922 if (va < VM_MAXUSER_ADDRESS)
3923 l3_val |= ATTR_S1_AP(ATTR_S1_AP_USER) | ATTR_S1_PXN;
3925 l3_val |= ATTR_S1_UXN;
3926 if (pmap != kernel_pmap)
3927 l3_val |= ATTR_S1_nG;
3930 * Now validate mapping with RO protection
3932 if ((m->oflags & VPO_UNMANAGED) == 0) {
3933 l3_val |= ATTR_SW_MANAGED;
3937 /* Sync icache before the mapping is stored to PTE */
3938 if ((prot & VM_PROT_EXECUTE) && pmap != kernel_pmap &&
3939 m->md.pv_memattr == VM_MEMATTR_WRITE_BACK)
3940 cpu_icache_sync_range(PHYS_TO_DMAP(pa), PAGE_SIZE);
3942 pmap_store(l3, l3_val);
3949 * This code maps large physical mmap regions into the
3950 * processor address space. Note that some shortcuts
3951 * are taken, but the code works.
3954 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
3955 vm_pindex_t pindex, vm_size_t size)
3958 VM_OBJECT_ASSERT_WLOCKED(object);
3959 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
3960 ("pmap_object_init_pt: non-device object"));
3964 * Clear the wired attribute from the mappings for the specified range of
3965 * addresses in the given pmap. Every valid mapping within that range
3966 * must have the wired attribute set. In contrast, invalid mappings
3967 * cannot have the wired attribute set, so they are ignored.
3969 * The wired attribute of the page table entry is not a hardware feature,
3970 * so there is no need to invalidate any TLB entries.
3973 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
3975 vm_offset_t va_next;
3976 pd_entry_t *l0, *l1, *l2;
3980 for (; sva < eva; sva = va_next) {
3981 l0 = pmap_l0(pmap, sva);
3982 if (pmap_load(l0) == 0) {
3983 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
3989 l1 = pmap_l0_to_l1(l0, sva);
3990 if (pmap_load(l1) == 0) {
3991 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
3997 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
4001 l2 = pmap_l1_to_l2(l1, sva);
4002 if (pmap_load(l2) == 0)
4005 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK) {
4006 if ((pmap_load(l2) & ATTR_SW_WIRED) == 0)
4007 panic("pmap_unwire: l2 %#jx is missing "
4008 "ATTR_SW_WIRED", (uintmax_t)pmap_load(l2));
4011 * Are we unwiring the entire large page? If not,
4012 * demote the mapping and fall through.
4014 if (sva + L2_SIZE == va_next && eva >= va_next) {
4015 pmap_clear_bits(l2, ATTR_SW_WIRED);
4016 pmap->pm_stats.wired_count -= L2_SIZE /
4019 } else if (pmap_demote_l2(pmap, l2, sva) == NULL)
4020 panic("pmap_unwire: demotion failed");
4022 KASSERT((pmap_load(l2) & ATTR_DESCR_MASK) == L2_TABLE,
4023 ("pmap_unwire: Invalid l2 entry after demotion"));
4027 for (l3 = pmap_l2_to_l3(l2, sva); sva != va_next; l3++,
4029 if (pmap_load(l3) == 0)
4031 if ((pmap_load(l3) & ATTR_SW_WIRED) == 0)
4032 panic("pmap_unwire: l3 %#jx is missing "
4033 "ATTR_SW_WIRED", (uintmax_t)pmap_load(l3));
4036 * ATTR_SW_WIRED must be cleared atomically. Although
4037 * the pmap lock synchronizes access to ATTR_SW_WIRED,
4038 * the System MMU may write to the entry concurrently.
4040 pmap_clear_bits(l3, ATTR_SW_WIRED);
4041 pmap->pm_stats.wired_count--;
4048 * Copy the range specified by src_addr/len
4049 * from the source map to the range dst_addr/len
4050 * in the destination map.
4052 * This routine is only advisory and need not do anything.
4054 * Because the executable mappings created by this routine are copied,
4055 * it should not have to flush the instruction cache.
4058 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
4059 vm_offset_t src_addr)
4061 struct rwlock *lock;
4062 pd_entry_t *l0, *l1, *l2, srcptepaddr;
4063 pt_entry_t *dst_pte, mask, nbits, ptetemp, *src_pte;
4064 vm_offset_t addr, end_addr, va_next;
4065 vm_page_t dst_l2pg, dstmpte, srcmpte;
4067 PMAP_ASSERT_STAGE1(dst_pmap);
4068 PMAP_ASSERT_STAGE1(src_pmap);
4070 if (dst_addr != src_addr)
4072 end_addr = src_addr + len;
4074 if (dst_pmap < src_pmap) {
4075 PMAP_LOCK(dst_pmap);
4076 PMAP_LOCK(src_pmap);
4078 PMAP_LOCK(src_pmap);
4079 PMAP_LOCK(dst_pmap);
4081 for (addr = src_addr; addr < end_addr; addr = va_next) {
4082 l0 = pmap_l0(src_pmap, addr);
4083 if (pmap_load(l0) == 0) {
4084 va_next = (addr + L0_SIZE) & ~L0_OFFSET;
4089 l1 = pmap_l0_to_l1(l0, addr);
4090 if (pmap_load(l1) == 0) {
4091 va_next = (addr + L1_SIZE) & ~L1_OFFSET;
4096 va_next = (addr + L2_SIZE) & ~L2_OFFSET;
4099 l2 = pmap_l1_to_l2(l1, addr);
4100 srcptepaddr = pmap_load(l2);
4101 if (srcptepaddr == 0)
4103 if ((srcptepaddr & ATTR_DESCR_MASK) == L2_BLOCK) {
4104 if ((addr & L2_OFFSET) != 0 ||
4105 addr + L2_SIZE > end_addr)
4107 l2 = pmap_alloc_l2(dst_pmap, addr, &dst_l2pg, NULL);
4110 if (pmap_load(l2) == 0 &&
4111 ((srcptepaddr & ATTR_SW_MANAGED) == 0 ||
4112 pmap_pv_insert_l2(dst_pmap, addr, srcptepaddr,
4113 PMAP_ENTER_NORECLAIM, &lock))) {
4114 mask = ATTR_AF | ATTR_SW_WIRED;
4116 if ((srcptepaddr & ATTR_SW_DBM) != 0)
4117 nbits |= ATTR_S1_AP_RW_BIT;
4118 pmap_store(l2, (srcptepaddr & ~mask) | nbits);
4119 pmap_resident_count_inc(dst_pmap, L2_SIZE /
4121 atomic_add_long(&pmap_l2_mappings, 1);
4123 pmap_abort_ptp(dst_pmap, addr, dst_l2pg);
4126 KASSERT((srcptepaddr & ATTR_DESCR_MASK) == L2_TABLE,
4127 ("pmap_copy: invalid L2 entry"));
4128 srcptepaddr &= ~ATTR_MASK;
4129 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr);
4130 KASSERT(srcmpte->ref_count > 0,
4131 ("pmap_copy: source page table page is unused"));
4132 if (va_next > end_addr)
4134 src_pte = (pt_entry_t *)PHYS_TO_DMAP(srcptepaddr);
4135 src_pte = &src_pte[pmap_l3_index(addr)];
4137 for (; addr < va_next; addr += PAGE_SIZE, src_pte++) {
4138 ptetemp = pmap_load(src_pte);
4141 * We only virtual copy managed pages.
4143 if ((ptetemp & ATTR_SW_MANAGED) == 0)
4146 if (dstmpte != NULL) {
4147 KASSERT(dstmpte->pindex == pmap_l2_pindex(addr),
4148 ("dstmpte pindex/addr mismatch"));
4149 dstmpte->ref_count++;
4150 } else if ((dstmpte = pmap_alloc_l3(dst_pmap, addr,
4153 dst_pte = (pt_entry_t *)
4154 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dstmpte));
4155 dst_pte = &dst_pte[pmap_l3_index(addr)];
4156 if (pmap_load(dst_pte) == 0 &&
4157 pmap_try_insert_pv_entry(dst_pmap, addr,
4158 PHYS_TO_VM_PAGE(ptetemp & ~ATTR_MASK), &lock)) {
4160 * Clear the wired, modified, and accessed
4161 * (referenced) bits during the copy.
4163 mask = ATTR_AF | ATTR_SW_WIRED;
4165 if ((ptetemp & ATTR_SW_DBM) != 0)
4166 nbits |= ATTR_S1_AP_RW_BIT;
4167 pmap_store(dst_pte, (ptetemp & ~mask) | nbits);
4168 pmap_resident_count_inc(dst_pmap, 1);
4170 pmap_abort_ptp(dst_pmap, addr, dstmpte);
4173 /* Have we copied all of the valid mappings? */
4174 if (dstmpte->ref_count >= srcmpte->ref_count)
4180 * XXX This barrier may not be needed because the destination pmap is
4187 PMAP_UNLOCK(src_pmap);
4188 PMAP_UNLOCK(dst_pmap);
4192 * pmap_zero_page zeros the specified hardware page by mapping
4193 * the page into KVM and using bzero to clear its contents.
4196 pmap_zero_page(vm_page_t m)
4198 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
4200 pagezero((void *)va);
4204 * pmap_zero_page_area zeros the specified hardware page by mapping
4205 * the page into KVM and using bzero to clear its contents.
4207 * off and size may not cover an area beyond a single hardware page.
4210 pmap_zero_page_area(vm_page_t m, int off, int size)
4212 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
4214 if (off == 0 && size == PAGE_SIZE)
4215 pagezero((void *)va);
4217 bzero((char *)va + off, size);
4221 * pmap_copy_page copies the specified (machine independent)
4222 * page by mapping the page into virtual memory and using
4223 * bcopy to copy the page, one machine dependent page at a
4227 pmap_copy_page(vm_page_t msrc, vm_page_t mdst)
4229 vm_offset_t src = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(msrc));
4230 vm_offset_t dst = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mdst));
4232 pagecopy((void *)src, (void *)dst);
4235 int unmapped_buf_allowed = 1;
4238 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
4239 vm_offset_t b_offset, int xfersize)
4243 vm_paddr_t p_a, p_b;
4244 vm_offset_t a_pg_offset, b_pg_offset;
4247 while (xfersize > 0) {
4248 a_pg_offset = a_offset & PAGE_MASK;
4249 m_a = ma[a_offset >> PAGE_SHIFT];
4250 p_a = m_a->phys_addr;
4251 b_pg_offset = b_offset & PAGE_MASK;
4252 m_b = mb[b_offset >> PAGE_SHIFT];
4253 p_b = m_b->phys_addr;
4254 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
4255 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
4256 if (__predict_false(!PHYS_IN_DMAP(p_a))) {
4257 panic("!DMAP a %lx", p_a);
4259 a_cp = (char *)PHYS_TO_DMAP(p_a) + a_pg_offset;
4261 if (__predict_false(!PHYS_IN_DMAP(p_b))) {
4262 panic("!DMAP b %lx", p_b);
4264 b_cp = (char *)PHYS_TO_DMAP(p_b) + b_pg_offset;
4266 bcopy(a_cp, b_cp, cnt);
4274 pmap_quick_enter_page(vm_page_t m)
4277 return (PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)));
4281 pmap_quick_remove_page(vm_offset_t addr)
4286 * Returns true if the pmap's pv is one of the first
4287 * 16 pvs linked to from this page. This count may
4288 * be changed upwards or downwards in the future; it
4289 * is only necessary that true be returned for a small
4290 * subset of pmaps for proper page aging.
4293 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
4295 struct md_page *pvh;
4296 struct rwlock *lock;
4301 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4302 ("pmap_page_exists_quick: page %p is not managed", m));
4304 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
4306 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4307 if (PV_PMAP(pv) == pmap) {
4315 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
4316 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4317 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4318 if (PV_PMAP(pv) == pmap) {
4332 * pmap_page_wired_mappings:
4334 * Return the number of managed mappings to the given physical page
4338 pmap_page_wired_mappings(vm_page_t m)
4340 struct rwlock *lock;
4341 struct md_page *pvh;
4345 int count, lvl, md_gen, pvh_gen;
4347 if ((m->oflags & VPO_UNMANAGED) != 0)
4349 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
4353 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4355 if (!PMAP_TRYLOCK(pmap)) {
4356 md_gen = m->md.pv_gen;
4360 if (md_gen != m->md.pv_gen) {
4365 pte = pmap_pte(pmap, pv->pv_va, &lvl);
4366 if (pte != NULL && (pmap_load(pte) & ATTR_SW_WIRED) != 0)
4370 if ((m->flags & PG_FICTITIOUS) == 0) {
4371 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4372 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4374 if (!PMAP_TRYLOCK(pmap)) {
4375 md_gen = m->md.pv_gen;
4376 pvh_gen = pvh->pv_gen;
4380 if (md_gen != m->md.pv_gen ||
4381 pvh_gen != pvh->pv_gen) {
4386 pte = pmap_pte(pmap, pv->pv_va, &lvl);
4388 (pmap_load(pte) & ATTR_SW_WIRED) != 0)
4398 * Returns true if the given page is mapped individually or as part of
4399 * a 2mpage. Otherwise, returns false.
4402 pmap_page_is_mapped(vm_page_t m)
4404 struct rwlock *lock;
4407 if ((m->oflags & VPO_UNMANAGED) != 0)
4409 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
4411 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
4412 ((m->flags & PG_FICTITIOUS) == 0 &&
4413 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
4419 * Destroy all managed, non-wired mappings in the given user-space
4420 * pmap. This pmap cannot be active on any processor besides the
4423 * This function cannot be applied to the kernel pmap. Moreover, it
4424 * is not intended for general use. It is only to be used during
4425 * process termination. Consequently, it can be implemented in ways
4426 * that make it faster than pmap_remove(). First, it can more quickly
4427 * destroy mappings by iterating over the pmap's collection of PV
4428 * entries, rather than searching the page table. Second, it doesn't
4429 * have to test and clear the page table entries atomically, because
4430 * no processor is currently accessing the user address space. In
4431 * particular, a page table entry's dirty bit won't change state once
4432 * this function starts.
4435 pmap_remove_pages(pmap_t pmap)
4438 pt_entry_t *pte, tpte;
4439 struct spglist free;
4440 vm_page_t m, ml3, mt;
4442 struct md_page *pvh;
4443 struct pv_chunk *pc, *npc;
4444 struct rwlock *lock;
4446 uint64_t inuse, bitmask;
4447 int allfree, field, freed, idx, lvl;
4450 KASSERT(pmap == PCPU_GET(curpmap), ("non-current pmap %p", pmap));
4456 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
4459 for (field = 0; field < _NPCM; field++) {
4460 inuse = ~pc->pc_map[field] & pc_freemask[field];
4461 while (inuse != 0) {
4462 bit = ffsl(inuse) - 1;
4463 bitmask = 1UL << bit;
4464 idx = field * 64 + bit;
4465 pv = &pc->pc_pventry[idx];
4468 pde = pmap_pde(pmap, pv->pv_va, &lvl);
4469 KASSERT(pde != NULL,
4470 ("Attempting to remove an unmapped page"));
4474 pte = pmap_l1_to_l2(pde, pv->pv_va);
4475 tpte = pmap_load(pte);
4476 KASSERT((tpte & ATTR_DESCR_MASK) ==
4478 ("Attempting to remove an invalid "
4479 "block: %lx", tpte));
4482 pte = pmap_l2_to_l3(pde, pv->pv_va);
4483 tpte = pmap_load(pte);
4484 KASSERT((tpte & ATTR_DESCR_MASK) ==
4486 ("Attempting to remove an invalid "
4487 "page: %lx", tpte));
4491 "Invalid page directory level: %d",
4496 * We cannot remove wired pages from a process' mapping at this time
4498 if (tpte & ATTR_SW_WIRED) {
4503 pa = tpte & ~ATTR_MASK;
4505 m = PHYS_TO_VM_PAGE(pa);
4506 KASSERT(m->phys_addr == pa,
4507 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
4508 m, (uintmax_t)m->phys_addr,
4511 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
4512 m < &vm_page_array[vm_page_array_size],
4513 ("pmap_remove_pages: bad pte %#jx",
4517 * Because this pmap is not active on other
4518 * processors, the dirty bit cannot have
4519 * changed state since we last loaded pte.
4524 * Update the vm_page_t clean/reference bits.
4526 if (pmap_pte_dirty(pmap, tpte)) {
4529 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
4538 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(&lock, m);
4541 pc->pc_map[field] |= bitmask;
4544 pmap_resident_count_dec(pmap,
4545 L2_SIZE / PAGE_SIZE);
4546 pvh = pa_to_pvh(tpte & ~ATTR_MASK);
4547 TAILQ_REMOVE(&pvh->pv_list, pv,pv_next);
4549 if (TAILQ_EMPTY(&pvh->pv_list)) {
4550 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
4551 if ((mt->a.flags & PGA_WRITEABLE) != 0 &&
4552 TAILQ_EMPTY(&mt->md.pv_list))
4553 vm_page_aflag_clear(mt, PGA_WRITEABLE);
4555 ml3 = pmap_remove_pt_page(pmap,
4558 KASSERT(ml3->valid == VM_PAGE_BITS_ALL,
4559 ("pmap_remove_pages: l3 page not promoted"));
4560 pmap_resident_count_dec(pmap,1);
4561 KASSERT(ml3->ref_count == NL3PG,
4562 ("pmap_remove_pages: l3 page ref count error"));
4564 pmap_add_delayed_free_list(ml3,
4569 pmap_resident_count_dec(pmap, 1);
4570 TAILQ_REMOVE(&m->md.pv_list, pv,
4573 if ((m->a.flags & PGA_WRITEABLE) != 0 &&
4574 TAILQ_EMPTY(&m->md.pv_list) &&
4575 (m->flags & PG_FICTITIOUS) == 0) {
4577 VM_PAGE_TO_PHYS(m));
4578 if (TAILQ_EMPTY(&pvh->pv_list))
4579 vm_page_aflag_clear(m,
4584 pmap_unuse_pt(pmap, pv->pv_va, pmap_load(pde),
4589 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
4590 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
4591 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
4593 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4599 pmap_invalidate_all(pmap);
4601 vm_page_free_pages_toq(&free, true);
4605 * This is used to check if a page has been accessed or modified.
4608 pmap_page_test_mappings(vm_page_t m, boolean_t accessed, boolean_t modified)
4610 struct rwlock *lock;
4612 struct md_page *pvh;
4613 pt_entry_t *pte, mask, value;
4615 int lvl, md_gen, pvh_gen;
4619 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
4622 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4624 PMAP_ASSERT_STAGE1(pmap);
4625 if (!PMAP_TRYLOCK(pmap)) {
4626 md_gen = m->md.pv_gen;
4630 if (md_gen != m->md.pv_gen) {
4635 pte = pmap_pte(pmap, pv->pv_va, &lvl);
4637 ("pmap_page_test_mappings: Invalid level %d", lvl));
4641 mask |= ATTR_S1_AP_RW_BIT;
4642 value |= ATTR_S1_AP(ATTR_S1_AP_RW);
4645 mask |= ATTR_AF | ATTR_DESCR_MASK;
4646 value |= ATTR_AF | L3_PAGE;
4648 rv = (pmap_load(pte) & mask) == value;
4653 if ((m->flags & PG_FICTITIOUS) == 0) {
4654 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4655 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4657 PMAP_ASSERT_STAGE1(pmap);
4658 if (!PMAP_TRYLOCK(pmap)) {
4659 md_gen = m->md.pv_gen;
4660 pvh_gen = pvh->pv_gen;
4664 if (md_gen != m->md.pv_gen ||
4665 pvh_gen != pvh->pv_gen) {
4670 pte = pmap_pte(pmap, pv->pv_va, &lvl);
4672 ("pmap_page_test_mappings: Invalid level %d", lvl));
4676 mask |= ATTR_S1_AP_RW_BIT;
4677 value |= ATTR_S1_AP(ATTR_S1_AP_RW);
4680 mask |= ATTR_AF | ATTR_DESCR_MASK;
4681 value |= ATTR_AF | L2_BLOCK;
4683 rv = (pmap_load(pte) & mask) == value;
4697 * Return whether or not the specified physical page was modified
4698 * in any physical maps.
4701 pmap_is_modified(vm_page_t m)
4704 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4705 ("pmap_is_modified: page %p is not managed", m));
4708 * If the page is not busied then this check is racy.
4710 if (!pmap_page_is_write_mapped(m))
4712 return (pmap_page_test_mappings(m, FALSE, TRUE));
4716 * pmap_is_prefaultable:
4718 * Return whether or not the specified virtual address is eligible
4722 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
4730 pte = pmap_pte(pmap, addr, &lvl);
4731 if (pte != NULL && pmap_load(pte) != 0) {
4739 * pmap_is_referenced:
4741 * Return whether or not the specified physical page was referenced
4742 * in any physical maps.
4745 pmap_is_referenced(vm_page_t m)
4748 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4749 ("pmap_is_referenced: page %p is not managed", m));
4750 return (pmap_page_test_mappings(m, TRUE, FALSE));
4754 * Clear the write and modified bits in each of the given page's mappings.
4757 pmap_remove_write(vm_page_t m)
4759 struct md_page *pvh;
4761 struct rwlock *lock;
4762 pv_entry_t next_pv, pv;
4763 pt_entry_t oldpte, *pte;
4765 int lvl, md_gen, pvh_gen;
4767 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4768 ("pmap_remove_write: page %p is not managed", m));
4769 vm_page_assert_busied(m);
4771 if (!pmap_page_is_write_mapped(m))
4773 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
4774 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
4775 pa_to_pvh(VM_PAGE_TO_PHYS(m));
4778 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
4780 PMAP_ASSERT_STAGE1(pmap);
4781 if (!PMAP_TRYLOCK(pmap)) {
4782 pvh_gen = pvh->pv_gen;
4786 if (pvh_gen != pvh->pv_gen) {
4793 pte = pmap_pte(pmap, pv->pv_va, &lvl);
4794 if ((pmap_load(pte) & ATTR_SW_DBM) != 0)
4795 (void)pmap_demote_l2_locked(pmap, pte, va, &lock);
4796 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
4797 ("inconsistent pv lock %p %p for page %p",
4798 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
4801 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4803 PMAP_ASSERT_STAGE1(pmap);
4804 if (!PMAP_TRYLOCK(pmap)) {
4805 pvh_gen = pvh->pv_gen;
4806 md_gen = m->md.pv_gen;
4810 if (pvh_gen != pvh->pv_gen ||
4811 md_gen != m->md.pv_gen) {
4817 pte = pmap_pte(pmap, pv->pv_va, &lvl);
4818 oldpte = pmap_load(pte);
4820 if ((oldpte & ATTR_SW_DBM) != 0) {
4821 if (!atomic_fcmpset_long(pte, &oldpte,
4822 (oldpte | ATTR_S1_AP_RW_BIT) & ~ATTR_SW_DBM))
4824 if ((oldpte & ATTR_S1_AP_RW_BIT) ==
4825 ATTR_S1_AP(ATTR_S1_AP_RW))
4827 pmap_invalidate_page(pmap, pv->pv_va);
4832 vm_page_aflag_clear(m, PGA_WRITEABLE);
4836 * pmap_ts_referenced:
4838 * Return a count of reference bits for a page, clearing those bits.
4839 * It is not necessary for every reference bit to be cleared, but it
4840 * is necessary that 0 only be returned when there are truly no
4841 * reference bits set.
4843 * As an optimization, update the page's dirty field if a modified bit is
4844 * found while counting reference bits. This opportunistic update can be
4845 * performed at low cost and can eliminate the need for some future calls
4846 * to pmap_is_modified(). However, since this function stops after
4847 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
4848 * dirty pages. Those dirty pages will only be detected by a future call
4849 * to pmap_is_modified().
4852 pmap_ts_referenced(vm_page_t m)
4854 struct md_page *pvh;
4857 struct rwlock *lock;
4858 pd_entry_t *pde, tpde;
4859 pt_entry_t *pte, tpte;
4862 int cleared, lvl, md_gen, not_cleared, pvh_gen;
4863 struct spglist free;
4865 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4866 ("pmap_ts_referenced: page %p is not managed", m));
4869 pa = VM_PAGE_TO_PHYS(m);
4870 lock = PHYS_TO_PV_LIST_LOCK(pa);
4871 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : pa_to_pvh(pa);
4875 if ((pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
4876 goto small_mappings;
4882 if (!PMAP_TRYLOCK(pmap)) {
4883 pvh_gen = pvh->pv_gen;
4887 if (pvh_gen != pvh->pv_gen) {
4893 pde = pmap_pde(pmap, pv->pv_va, &lvl);
4894 KASSERT(pde != NULL, ("pmap_ts_referenced: no l1 table found"));
4896 ("pmap_ts_referenced: invalid pde level %d", lvl));
4897 tpde = pmap_load(pde);
4898 KASSERT((tpde & ATTR_DESCR_MASK) == L1_TABLE,
4899 ("pmap_ts_referenced: found an invalid l1 table"));
4900 pte = pmap_l1_to_l2(pde, pv->pv_va);
4901 tpte = pmap_load(pte);
4902 if (pmap_pte_dirty(pmap, tpte)) {
4904 * Although "tpte" is mapping a 2MB page, because
4905 * this function is called at a 4KB page granularity,
4906 * we only update the 4KB page under test.
4911 if ((tpte & ATTR_AF) != 0) {
4913 * Since this reference bit is shared by 512 4KB pages,
4914 * it should not be cleared every time it is tested.
4915 * Apply a simple "hash" function on the physical page
4916 * number, the virtual superpage number, and the pmap
4917 * address to select one 4KB page out of the 512 on
4918 * which testing the reference bit will result in
4919 * clearing that reference bit. This function is
4920 * designed to avoid the selection of the same 4KB page
4921 * for every 2MB page mapping.
4923 * On demotion, a mapping that hasn't been referenced
4924 * is simply destroyed. To avoid the possibility of a
4925 * subsequent page fault on a demoted wired mapping,
4926 * always leave its reference bit set. Moreover,
4927 * since the superpage is wired, the current state of
4928 * its reference bit won't affect page replacement.
4930 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> L2_SHIFT) ^
4931 (uintptr_t)pmap) & (Ln_ENTRIES - 1)) == 0 &&
4932 (tpte & ATTR_SW_WIRED) == 0) {
4933 pmap_clear_bits(pte, ATTR_AF);
4934 pmap_invalidate_page(pmap, pv->pv_va);
4940 /* Rotate the PV list if it has more than one entry. */
4941 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
4942 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
4943 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
4946 if (cleared + not_cleared >= PMAP_TS_REFERENCED_MAX)
4948 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
4950 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
4957 if (!PMAP_TRYLOCK(pmap)) {
4958 pvh_gen = pvh->pv_gen;
4959 md_gen = m->md.pv_gen;
4963 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
4968 pde = pmap_pde(pmap, pv->pv_va, &lvl);
4969 KASSERT(pde != NULL, ("pmap_ts_referenced: no l2 table found"));
4971 ("pmap_ts_referenced: invalid pde level %d", lvl));
4972 tpde = pmap_load(pde);
4973 KASSERT((tpde & ATTR_DESCR_MASK) == L2_TABLE,
4974 ("pmap_ts_referenced: found an invalid l2 table"));
4975 pte = pmap_l2_to_l3(pde, pv->pv_va);
4976 tpte = pmap_load(pte);
4977 if (pmap_pte_dirty(pmap, tpte))
4979 if ((tpte & ATTR_AF) != 0) {
4980 if ((tpte & ATTR_SW_WIRED) == 0) {
4981 pmap_clear_bits(pte, ATTR_AF);
4982 pmap_invalidate_page(pmap, pv->pv_va);
4988 /* Rotate the PV list if it has more than one entry. */
4989 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
4990 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4991 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4994 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && cleared +
4995 not_cleared < PMAP_TS_REFERENCED_MAX);
4998 vm_page_free_pages_toq(&free, true);
4999 return (cleared + not_cleared);
5003 * Apply the given advice to the specified range of addresses within the
5004 * given pmap. Depending on the advice, clear the referenced and/or
5005 * modified flags in each mapping and set the mapped page's dirty field.
5008 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
5010 struct rwlock *lock;
5011 vm_offset_t va, va_next;
5013 pd_entry_t *l0, *l1, *l2, oldl2;
5014 pt_entry_t *l3, oldl3;
5016 PMAP_ASSERT_STAGE1(pmap);
5018 if (advice != MADV_DONTNEED && advice != MADV_FREE)
5022 for (; sva < eva; sva = va_next) {
5023 l0 = pmap_l0(pmap, sva);
5024 if (pmap_load(l0) == 0) {
5025 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
5030 l1 = pmap_l0_to_l1(l0, sva);
5031 if (pmap_load(l1) == 0) {
5032 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
5037 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
5040 l2 = pmap_l1_to_l2(l1, sva);
5041 oldl2 = pmap_load(l2);
5044 if ((oldl2 & ATTR_DESCR_MASK) == L2_BLOCK) {
5045 if ((oldl2 & ATTR_SW_MANAGED) == 0)
5048 if (!pmap_demote_l2_locked(pmap, l2, sva, &lock)) {
5053 * The 2MB page mapping was destroyed.
5059 * Unless the page mappings are wired, remove the
5060 * mapping to a single page so that a subsequent
5061 * access may repromote. Choosing the last page
5062 * within the address range [sva, min(va_next, eva))
5063 * generally results in more repromotions. Since the
5064 * underlying page table page is fully populated, this
5065 * removal never frees a page table page.
5067 if ((oldl2 & ATTR_SW_WIRED) == 0) {
5073 ("pmap_advise: no address gap"));
5074 l3 = pmap_l2_to_l3(l2, va);
5075 KASSERT(pmap_load(l3) != 0,
5076 ("pmap_advise: invalid PTE"));
5077 pmap_remove_l3(pmap, l3, va, pmap_load(l2),
5083 KASSERT((pmap_load(l2) & ATTR_DESCR_MASK) == L2_TABLE,
5084 ("pmap_advise: invalid L2 entry after demotion"));
5088 for (l3 = pmap_l2_to_l3(l2, sva); sva != va_next; l3++,
5090 oldl3 = pmap_load(l3);
5091 if ((oldl3 & (ATTR_SW_MANAGED | ATTR_DESCR_MASK)) !=
5092 (ATTR_SW_MANAGED | L3_PAGE))
5094 else if (pmap_pte_dirty(pmap, oldl3)) {
5095 if (advice == MADV_DONTNEED) {
5097 * Future calls to pmap_is_modified()
5098 * can be avoided by making the page
5101 m = PHYS_TO_VM_PAGE(oldl3 & ~ATTR_MASK);
5104 while (!atomic_fcmpset_long(l3, &oldl3,
5105 (oldl3 & ~ATTR_AF) |
5106 ATTR_S1_AP(ATTR_S1_AP_RO)))
5108 } else if ((oldl3 & ATTR_AF) != 0)
5109 pmap_clear_bits(l3, ATTR_AF);
5116 if (va != va_next) {
5117 pmap_invalidate_range(pmap, va, sva);
5122 pmap_invalidate_range(pmap, va, sva);
5128 * Clear the modify bits on the specified physical page.
5131 pmap_clear_modify(vm_page_t m)
5133 struct md_page *pvh;
5134 struct rwlock *lock;
5136 pv_entry_t next_pv, pv;
5137 pd_entry_t *l2, oldl2;
5138 pt_entry_t *l3, oldl3;
5140 int md_gen, pvh_gen;
5142 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5143 ("pmap_clear_modify: page %p is not managed", m));
5144 vm_page_assert_busied(m);
5146 if (!pmap_page_is_write_mapped(m))
5148 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
5149 pa_to_pvh(VM_PAGE_TO_PHYS(m));
5150 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5153 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
5155 PMAP_ASSERT_STAGE1(pmap);
5156 if (!PMAP_TRYLOCK(pmap)) {
5157 pvh_gen = pvh->pv_gen;
5161 if (pvh_gen != pvh->pv_gen) {
5167 l2 = pmap_l2(pmap, va);
5168 oldl2 = pmap_load(l2);
5169 /* If oldl2 has ATTR_SW_DBM set, then it is also dirty. */
5170 if ((oldl2 & ATTR_SW_DBM) != 0 &&
5171 pmap_demote_l2_locked(pmap, l2, va, &lock) &&
5172 (oldl2 & ATTR_SW_WIRED) == 0) {
5174 * Write protect the mapping to a single page so that
5175 * a subsequent write access may repromote.
5177 va += VM_PAGE_TO_PHYS(m) - (oldl2 & ~ATTR_MASK);
5178 l3 = pmap_l2_to_l3(l2, va);
5179 oldl3 = pmap_load(l3);
5180 while (!atomic_fcmpset_long(l3, &oldl3,
5181 (oldl3 & ~ATTR_SW_DBM) | ATTR_S1_AP(ATTR_S1_AP_RO)))
5184 pmap_invalidate_page(pmap, va);
5188 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5190 PMAP_ASSERT_STAGE1(pmap);
5191 if (!PMAP_TRYLOCK(pmap)) {
5192 md_gen = m->md.pv_gen;
5193 pvh_gen = pvh->pv_gen;
5197 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
5202 l2 = pmap_l2(pmap, pv->pv_va);
5203 l3 = pmap_l2_to_l3(l2, pv->pv_va);
5204 oldl3 = pmap_load(l3);
5205 if (pmap_l3_valid(oldl3) &&
5206 (oldl3 & (ATTR_S1_AP_RW_BIT | ATTR_SW_DBM)) == ATTR_SW_DBM){
5207 pmap_set_bits(l3, ATTR_S1_AP(ATTR_S1_AP_RO));
5208 pmap_invalidate_page(pmap, pv->pv_va);
5216 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
5218 struct pmap_preinit_mapping *ppim;
5219 vm_offset_t va, offset;
5222 int i, lvl, l2_blocks, free_l2_count, start_idx;
5224 if (!vm_initialized) {
5226 * No L3 ptables so map entire L2 blocks where start VA is:
5227 * preinit_map_va + start_idx * L2_SIZE
5228 * There may be duplicate mappings (multiple VA -> same PA) but
5229 * ARM64 dcache is always PIPT so that's acceptable.
5234 /* Calculate how many L2 blocks are needed for the mapping */
5235 l2_blocks = (roundup2(pa + size, L2_SIZE) -
5236 rounddown2(pa, L2_SIZE)) >> L2_SHIFT;
5238 offset = pa & L2_OFFSET;
5240 if (preinit_map_va == 0)
5243 /* Map 2MiB L2 blocks from reserved VA space */
5247 /* Find enough free contiguous VA space */
5248 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5249 ppim = pmap_preinit_mapping + i;
5250 if (free_l2_count > 0 && ppim->pa != 0) {
5251 /* Not enough space here */
5257 if (ppim->pa == 0) {
5259 if (start_idx == -1)
5262 if (free_l2_count == l2_blocks)
5266 if (free_l2_count != l2_blocks)
5267 panic("%s: too many preinit mappings", __func__);
5269 va = preinit_map_va + (start_idx * L2_SIZE);
5270 for (i = start_idx; i < start_idx + l2_blocks; i++) {
5271 /* Mark entries as allocated */
5272 ppim = pmap_preinit_mapping + i;
5274 ppim->va = va + offset;
5279 pa = rounddown2(pa, L2_SIZE);
5280 for (i = 0; i < l2_blocks; i++) {
5281 pde = pmap_pde(kernel_pmap, va, &lvl);
5282 KASSERT(pde != NULL,
5283 ("pmap_mapbios: Invalid page entry, va: 0x%lx",
5286 ("pmap_mapbios: Invalid level %d", lvl));
5288 /* Insert L2_BLOCK */
5289 l2 = pmap_l1_to_l2(pde, va);
5291 pa | ATTR_DEFAULT | ATTR_S1_XN |
5292 ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK) | L2_BLOCK);
5297 pmap_invalidate_all(kernel_pmap);
5299 va = preinit_map_va + (start_idx * L2_SIZE);
5302 /* kva_alloc may be used to map the pages */
5303 offset = pa & PAGE_MASK;
5304 size = round_page(offset + size);
5306 va = kva_alloc(size);
5308 panic("%s: Couldn't allocate KVA", __func__);
5310 pde = pmap_pde(kernel_pmap, va, &lvl);
5311 KASSERT(lvl == 2, ("pmap_mapbios: Invalid level %d", lvl));
5313 /* L3 table is linked */
5314 va = trunc_page(va);
5315 pa = trunc_page(pa);
5316 pmap_kenter(va, size, pa, VM_MEMATTR_WRITE_BACK);
5319 return ((void *)(va + offset));
5323 pmap_unmapbios(vm_offset_t va, vm_size_t size)
5325 struct pmap_preinit_mapping *ppim;
5326 vm_offset_t offset, tmpsize, va_trunc;
5329 int i, lvl, l2_blocks, block;
5333 (roundup2(va + size, L2_SIZE) - rounddown2(va, L2_SIZE)) >> L2_SHIFT;
5334 KASSERT(l2_blocks > 0, ("pmap_unmapbios: invalid size %lx", size));
5336 /* Remove preinit mapping */
5337 preinit_map = false;
5339 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5340 ppim = pmap_preinit_mapping + i;
5341 if (ppim->va == va) {
5342 KASSERT(ppim->size == size,
5343 ("pmap_unmapbios: size mismatch"));
5348 offset = block * L2_SIZE;
5349 va_trunc = rounddown2(va, L2_SIZE) + offset;
5351 /* Remove L2_BLOCK */
5352 pde = pmap_pde(kernel_pmap, va_trunc, &lvl);
5353 KASSERT(pde != NULL,
5354 ("pmap_unmapbios: Invalid page entry, va: 0x%lx",
5356 l2 = pmap_l1_to_l2(pde, va_trunc);
5359 if (block == (l2_blocks - 1))
5365 pmap_invalidate_all(kernel_pmap);
5369 /* Unmap the pages reserved with kva_alloc. */
5370 if (vm_initialized) {
5371 offset = va & PAGE_MASK;
5372 size = round_page(offset + size);
5373 va = trunc_page(va);
5375 pde = pmap_pde(kernel_pmap, va, &lvl);
5376 KASSERT(pde != NULL,
5377 ("pmap_unmapbios: Invalid page entry, va: 0x%lx", va));
5378 KASSERT(lvl == 2, ("pmap_unmapbios: Invalid level %d", lvl));
5380 /* Unmap and invalidate the pages */
5381 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
5382 pmap_kremove(va + tmpsize);
5389 * Sets the memory attribute for the specified page.
5392 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
5395 m->md.pv_memattr = ma;
5398 * If "m" is a normal page, update its direct mapping. This update
5399 * can be relied upon to perform any cache operations that are
5400 * required for data coherence.
5402 if ((m->flags & PG_FICTITIOUS) == 0 &&
5403 pmap_change_attr(PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)), PAGE_SIZE,
5404 m->md.pv_memattr) != 0)
5405 panic("memory attribute change on the direct map failed");
5409 * Changes the specified virtual address range's memory type to that given by
5410 * the parameter "mode". The specified virtual address range must be
5411 * completely contained within either the direct map or the kernel map. If
5412 * the virtual address range is contained within the kernel map, then the
5413 * memory type for each of the corresponding ranges of the direct map is also
5414 * changed. (The corresponding ranges of the direct map are those ranges that
5415 * map the same physical pages as the specified virtual address range.) These
5416 * changes to the direct map are necessary because Intel describes the
5417 * behavior of their processors as "undefined" if two or more mappings to the
5418 * same physical page have different memory types.
5420 * Returns zero if the change completed successfully, and either EINVAL or
5421 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
5422 * of the virtual address range was not mapped, and ENOMEM is returned if
5423 * there was insufficient memory available to complete the change. In the
5424 * latter case, the memory type may have been changed on some part of the
5425 * virtual address range or the direct map.
5428 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
5432 PMAP_LOCK(kernel_pmap);
5433 error = pmap_change_attr_locked(va, size, mode);
5434 PMAP_UNLOCK(kernel_pmap);
5439 pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode)
5441 vm_offset_t base, offset, tmpva;
5442 pt_entry_t l3, *pte, *newpte;
5445 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
5446 base = trunc_page(va);
5447 offset = va & PAGE_MASK;
5448 size = round_page(offset + size);
5450 if (!VIRT_IN_DMAP(base) &&
5451 !(base >= VM_MIN_KERNEL_ADDRESS && base < VM_MAX_KERNEL_ADDRESS))
5454 for (tmpva = base; tmpva < base + size; ) {
5455 pte = pmap_pte(kernel_pmap, tmpva, &lvl);
5459 if ((pmap_load(pte) & ATTR_S1_IDX_MASK) == ATTR_S1_IDX(mode)) {
5461 * We already have the correct attribute,
5462 * ignore this entry.
5466 panic("Invalid DMAP table level: %d\n", lvl);
5468 tmpva = (tmpva & ~L1_OFFSET) + L1_SIZE;
5471 tmpva = (tmpva & ~L2_OFFSET) + L2_SIZE;
5479 * Split the entry to an level 3 table, then
5480 * set the new attribute.
5484 panic("Invalid DMAP table level: %d\n", lvl);
5486 newpte = pmap_demote_l1(kernel_pmap, pte,
5487 tmpva & ~L1_OFFSET);
5490 pte = pmap_l1_to_l2(pte, tmpva);
5492 newpte = pmap_demote_l2(kernel_pmap, pte,
5496 pte = pmap_l2_to_l3(pte, tmpva);
5498 /* Update the entry */
5499 l3 = pmap_load(pte);
5500 l3 &= ~ATTR_S1_IDX_MASK;
5501 l3 |= ATTR_S1_IDX(mode);
5502 if (mode == VM_MEMATTR_DEVICE)
5505 pmap_update_entry(kernel_pmap, pte, l3, tmpva,
5509 * If moving to a non-cacheable entry flush
5512 if (mode == VM_MEMATTR_UNCACHEABLE)
5513 cpu_dcache_wbinv_range(tmpva, L3_SIZE);
5525 * Create an L2 table to map all addresses within an L1 mapping.
5528 pmap_demote_l1(pmap_t pmap, pt_entry_t *l1, vm_offset_t va)
5530 pt_entry_t *l2, newl2, oldl1;
5532 vm_paddr_t l2phys, phys;
5536 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5537 oldl1 = pmap_load(l1);
5538 KASSERT((oldl1 & ATTR_DESCR_MASK) == L1_BLOCK,
5539 ("pmap_demote_l1: Demoting a non-block entry"));
5540 KASSERT((va & L1_OFFSET) == 0,
5541 ("pmap_demote_l1: Invalid virtual address %#lx", va));
5542 KASSERT((oldl1 & ATTR_SW_MANAGED) == 0,
5543 ("pmap_demote_l1: Level 1 table shouldn't be managed"));
5546 if (va <= (vm_offset_t)l1 && va + L1_SIZE > (vm_offset_t)l1) {
5547 tmpl1 = kva_alloc(PAGE_SIZE);
5552 if ((ml2 = vm_page_alloc(NULL, 0, VM_ALLOC_INTERRUPT |
5553 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
5554 CTR2(KTR_PMAP, "pmap_demote_l1: failure for va %#lx"
5555 " in pmap %p", va, pmap);
5559 l2phys = VM_PAGE_TO_PHYS(ml2);
5560 l2 = (pt_entry_t *)PHYS_TO_DMAP(l2phys);
5562 /* Address the range points at */
5563 phys = oldl1 & ~ATTR_MASK;
5564 /* The attributed from the old l1 table to be copied */
5565 newl2 = oldl1 & ATTR_MASK;
5567 /* Create the new entries */
5568 for (i = 0; i < Ln_ENTRIES; i++) {
5569 l2[i] = newl2 | phys;
5572 KASSERT(l2[0] == ((oldl1 & ~ATTR_DESCR_MASK) | L2_BLOCK),
5573 ("Invalid l2 page (%lx != %lx)", l2[0],
5574 (oldl1 & ~ATTR_DESCR_MASK) | L2_BLOCK));
5577 pmap_kenter(tmpl1, PAGE_SIZE,
5578 DMAP_TO_PHYS((vm_offset_t)l1) & ~L3_OFFSET,
5579 VM_MEMATTR_WRITE_BACK);
5580 l1 = (pt_entry_t *)(tmpl1 + ((vm_offset_t)l1 & PAGE_MASK));
5583 pmap_update_entry(pmap, l1, l2phys | L1_TABLE, va, PAGE_SIZE);
5586 pmap_kremove(tmpl1);
5587 kva_free(tmpl1, PAGE_SIZE);
5594 pmap_fill_l3(pt_entry_t *firstl3, pt_entry_t newl3)
5598 for (l3 = firstl3; l3 - firstl3 < Ln_ENTRIES; l3++) {
5605 pmap_demote_l2_abort(pmap_t pmap, vm_offset_t va, pt_entry_t *l2,
5606 struct rwlock **lockp)
5608 struct spglist free;
5611 (void)pmap_remove_l2(pmap, l2, va, pmap_load(pmap_l1(pmap, va)), &free,
5613 vm_page_free_pages_toq(&free, true);
5617 * Create an L3 table to map all addresses within an L2 mapping.
5620 pmap_demote_l2_locked(pmap_t pmap, pt_entry_t *l2, vm_offset_t va,
5621 struct rwlock **lockp)
5623 pt_entry_t *l3, newl3, oldl2;
5628 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5629 PMAP_ASSERT_STAGE1(pmap);
5631 oldl2 = pmap_load(l2);
5632 KASSERT((oldl2 & ATTR_DESCR_MASK) == L2_BLOCK,
5633 ("pmap_demote_l2: Demoting a non-block entry"));
5637 if (va <= (vm_offset_t)l2 && va + L2_SIZE > (vm_offset_t)l2) {
5638 tmpl2 = kva_alloc(PAGE_SIZE);
5644 * Invalidate the 2MB page mapping and return "failure" if the
5645 * mapping was never accessed.
5647 if ((oldl2 & ATTR_AF) == 0) {
5648 KASSERT((oldl2 & ATTR_SW_WIRED) == 0,
5649 ("pmap_demote_l2: a wired mapping is missing ATTR_AF"));
5650 pmap_demote_l2_abort(pmap, va, l2, lockp);
5651 CTR2(KTR_PMAP, "pmap_demote_l2: failure for va %#lx in pmap %p",
5656 if ((ml3 = pmap_remove_pt_page(pmap, va)) == NULL) {
5657 KASSERT((oldl2 & ATTR_SW_WIRED) == 0,
5658 ("pmap_demote_l2: page table page for a wired mapping"
5662 * If the page table page is missing and the mapping
5663 * is for a kernel address, the mapping must belong to
5664 * the direct map. Page table pages are preallocated
5665 * for every other part of the kernel address space,
5666 * so the direct map region is the only part of the
5667 * kernel address space that must be handled here.
5669 KASSERT(va < VM_MAXUSER_ADDRESS || VIRT_IN_DMAP(va),
5670 ("pmap_demote_l2: No saved mpte for va %#lx", va));
5673 * If the 2MB page mapping belongs to the direct map
5674 * region of the kernel's address space, then the page
5675 * allocation request specifies the highest possible
5676 * priority (VM_ALLOC_INTERRUPT). Otherwise, the
5677 * priority is normal.
5679 ml3 = vm_page_alloc(NULL, pmap_l2_pindex(va),
5680 (VIRT_IN_DMAP(va) ? VM_ALLOC_INTERRUPT : VM_ALLOC_NORMAL) |
5681 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED);
5684 * If the allocation of the new page table page fails,
5685 * invalidate the 2MB page mapping and return "failure".
5688 pmap_demote_l2_abort(pmap, va, l2, lockp);
5689 CTR2(KTR_PMAP, "pmap_demote_l2: failure for va %#lx"
5690 " in pmap %p", va, pmap);
5694 if (va < VM_MAXUSER_ADDRESS) {
5695 ml3->ref_count = NL3PG;
5696 pmap_resident_count_inc(pmap, 1);
5699 l3phys = VM_PAGE_TO_PHYS(ml3);
5700 l3 = (pt_entry_t *)PHYS_TO_DMAP(l3phys);
5701 newl3 = (oldl2 & ~ATTR_DESCR_MASK) | L3_PAGE;
5702 KASSERT((oldl2 & (ATTR_S1_AP_RW_BIT | ATTR_SW_DBM)) !=
5703 (ATTR_S1_AP(ATTR_S1_AP_RO) | ATTR_SW_DBM),
5704 ("pmap_demote_l2: L2 entry is writeable but not dirty"));
5707 * If the page table page is not leftover from an earlier promotion,
5708 * or the mapping attributes have changed, (re)initialize the L3 table.
5710 * When pmap_update_entry() clears the old L2 mapping, it (indirectly)
5711 * performs a dsb(). That dsb() ensures that the stores for filling
5712 * "l3" are visible before "l3" is added to the page table.
5714 if (ml3->valid == 0 || (l3[0] & ATTR_MASK) != (newl3 & ATTR_MASK))
5715 pmap_fill_l3(l3, newl3);
5718 * Map the temporary page so we don't lose access to the l2 table.
5721 pmap_kenter(tmpl2, PAGE_SIZE,
5722 DMAP_TO_PHYS((vm_offset_t)l2) & ~L3_OFFSET,
5723 VM_MEMATTR_WRITE_BACK);
5724 l2 = (pt_entry_t *)(tmpl2 + ((vm_offset_t)l2 & PAGE_MASK));
5728 * The spare PV entries must be reserved prior to demoting the
5729 * mapping, that is, prior to changing the PDE. Otherwise, the state
5730 * of the L2 and the PV lists will be inconsistent, which can result
5731 * in reclaim_pv_chunk() attempting to remove a PV entry from the
5732 * wrong PV list and pmap_pv_demote_l2() failing to find the expected
5733 * PV entry for the 2MB page mapping that is being demoted.
5735 if ((oldl2 & ATTR_SW_MANAGED) != 0)
5736 reserve_pv_entries(pmap, Ln_ENTRIES - 1, lockp);
5739 * Pass PAGE_SIZE so that a single TLB invalidation is performed on
5740 * the 2MB page mapping.
5742 pmap_update_entry(pmap, l2, l3phys | L2_TABLE, va, PAGE_SIZE);
5745 * Demote the PV entry.
5747 if ((oldl2 & ATTR_SW_MANAGED) != 0)
5748 pmap_pv_demote_l2(pmap, va, oldl2 & ~ATTR_MASK, lockp);
5750 atomic_add_long(&pmap_l2_demotions, 1);
5751 CTR3(KTR_PMAP, "pmap_demote_l2: success for va %#lx"
5752 " in pmap %p %lx", va, pmap, l3[0]);
5756 pmap_kremove(tmpl2);
5757 kva_free(tmpl2, PAGE_SIZE);
5765 pmap_demote_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t va)
5767 struct rwlock *lock;
5771 l3 = pmap_demote_l2_locked(pmap, l2, va, &lock);
5778 * Perform the pmap work for mincore(2). If the page is not both referenced and
5779 * modified by this pmap, returns its physical address so that the caller can
5780 * find other mappings.
5783 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *pap)
5785 pt_entry_t *pte, tpte;
5786 vm_paddr_t mask, pa;
5790 PMAP_ASSERT_STAGE1(pmap);
5792 pte = pmap_pte(pmap, addr, &lvl);
5794 tpte = pmap_load(pte);
5807 panic("pmap_mincore: invalid level %d", lvl);
5810 managed = (tpte & ATTR_SW_MANAGED) != 0;
5811 val = MINCORE_INCORE;
5813 val |= MINCORE_SUPER;
5814 if ((managed && pmap_pte_dirty(pmap, tpte)) || (!managed &&
5815 (tpte & ATTR_S1_AP_RW_BIT) == ATTR_S1_AP(ATTR_S1_AP_RW)))
5816 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
5817 if ((tpte & ATTR_AF) == ATTR_AF)
5818 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
5820 pa = (tpte & ~ATTR_MASK) | (addr & mask);
5826 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
5827 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) && managed) {
5835 * Garbage collect every ASID that is neither active on a processor nor
5839 pmap_reset_asid_set(pmap_t pmap)
5842 int asid, cpuid, epoch;
5843 struct asid_set *set;
5845 PMAP_ASSERT_STAGE1(pmap);
5847 set = pmap->pm_asid_set;
5848 KASSERT(set != NULL, ("%s: NULL asid set", __func__));
5849 mtx_assert(&set->asid_set_mutex, MA_OWNED);
5852 * Ensure that the store to asid_epoch is globally visible before the
5853 * loads from pc_curpmap are performed.
5855 epoch = set->asid_epoch + 1;
5856 if (epoch == INT_MAX)
5858 set->asid_epoch = epoch;
5860 __asm __volatile("tlbi vmalle1is");
5862 bit_nclear(set->asid_set, ASID_FIRST_AVAILABLE,
5863 set->asid_set_size - 1);
5864 CPU_FOREACH(cpuid) {
5865 if (cpuid == curcpu)
5867 curpmap = pcpu_find(cpuid)->pc_curpmap;
5868 KASSERT(curpmap->pm_asid_set == set, ("Incorrect set"));
5869 asid = COOKIE_TO_ASID(curpmap->pm_cookie);
5872 bit_set(set->asid_set, asid);
5873 curpmap->pm_cookie = COOKIE_FROM(asid, epoch);
5878 * Allocate a new ASID for the specified pmap.
5881 pmap_alloc_asid(pmap_t pmap)
5883 struct asid_set *set;
5886 PMAP_ASSERT_STAGE1(pmap);
5887 set = pmap->pm_asid_set;
5888 KASSERT(set != NULL, ("%s: NULL asid set", __func__));
5890 mtx_lock_spin(&set->asid_set_mutex);
5893 * While this processor was waiting to acquire the asid set mutex,
5894 * pmap_reset_asid_set() running on another processor might have
5895 * updated this pmap's cookie to the current epoch. In which case, we
5896 * don't need to allocate a new ASID.
5898 if (COOKIE_TO_EPOCH(pmap->pm_cookie) == set->asid_epoch)
5901 bit_ffc_at(set->asid_set, set->asid_next, set->asid_set_size,
5903 if (new_asid == -1) {
5904 bit_ffc_at(set->asid_set, ASID_FIRST_AVAILABLE,
5905 set->asid_next, &new_asid);
5906 if (new_asid == -1) {
5907 pmap_reset_asid_set(pmap);
5908 bit_ffc_at(set->asid_set, ASID_FIRST_AVAILABLE,
5909 set->asid_set_size, &new_asid);
5910 KASSERT(new_asid != -1, ("ASID allocation failure"));
5913 bit_set(set->asid_set, new_asid);
5914 set->asid_next = new_asid + 1;
5915 pmap->pm_cookie = COOKIE_FROM(new_asid, set->asid_epoch);
5917 mtx_unlock_spin(&set->asid_set_mutex);
5921 * Compute the value that should be stored in ttbr0 to activate the specified
5922 * pmap. This value may change from time to time.
5925 pmap_to_ttbr0(pmap_t pmap)
5928 PMAP_ASSERT_STAGE1(pmap);
5929 return (ASID_TO_OPERAND(COOKIE_TO_ASID(pmap->pm_cookie)) |
5934 pmap_activate_int(pmap_t pmap)
5936 struct asid_set *set;
5939 PMAP_ASSERT_STAGE1(pmap);
5940 KASSERT(PCPU_GET(curpmap) != NULL, ("no active pmap"));
5941 KASSERT(pmap != kernel_pmap, ("kernel pmap activation"));
5942 if (pmap == PCPU_GET(curpmap)) {
5944 * Handle the possibility that the old thread was preempted
5945 * after an "ic" or "tlbi" instruction but before it performed
5946 * a "dsb" instruction. If the old thread migrates to a new
5947 * processor, its completion of a "dsb" instruction on that
5948 * new processor does not guarantee that the "ic" or "tlbi"
5949 * instructions performed on the old processor have completed.
5955 set = pmap->pm_asid_set;
5956 KASSERT(set != NULL, ("%s: NULL asid set", __func__));
5959 * Ensure that the store to curpmap is globally visible before the
5960 * load from asid_epoch is performed.
5962 PCPU_SET(curpmap, pmap);
5964 epoch = COOKIE_TO_EPOCH(pmap->pm_cookie);
5965 if (epoch >= 0 && epoch != set->asid_epoch)
5966 pmap_alloc_asid(pmap);
5968 set_ttbr0(pmap_to_ttbr0(pmap));
5969 if (PCPU_GET(bcast_tlbi_workaround) != 0)
5970 invalidate_local_icache();
5975 pmap_activate(struct thread *td)
5979 pmap = vmspace_pmap(td->td_proc->p_vmspace);
5980 PMAP_ASSERT_STAGE1(pmap);
5982 (void)pmap_activate_int(pmap);
5987 * To eliminate the unused parameter "old", we would have to add an instruction
5991 pmap_switch(struct thread *old __unused, struct thread *new)
5993 pcpu_bp_harden bp_harden;
5996 /* Store the new curthread */
5997 PCPU_SET(curthread, new);
5999 /* And the new pcb */
6001 PCPU_SET(curpcb, pcb);
6004 * TODO: We may need to flush the cache here if switching
6005 * to a user process.
6008 if (pmap_activate_int(vmspace_pmap(new->td_proc->p_vmspace))) {
6010 * Stop userspace from training the branch predictor against
6011 * other processes. This will call into a CPU specific
6012 * function that clears the branch predictor state.
6014 bp_harden = PCPU_GET(bp_harden);
6015 if (bp_harden != NULL)
6023 pmap_sync_icache(pmap_t pmap, vm_offset_t va, vm_size_t sz)
6026 PMAP_ASSERT_STAGE1(pmap);
6027 if (va >= VM_MIN_KERNEL_ADDRESS) {
6028 cpu_icache_sync_range(va, sz);
6033 /* Find the length of data in this page to flush */
6034 offset = va & PAGE_MASK;
6035 len = imin(PAGE_SIZE - offset, sz);
6038 /* Extract the physical address & find it in the DMAP */
6039 pa = pmap_extract(pmap, va);
6041 cpu_icache_sync_range(PHYS_TO_DMAP(pa), len);
6043 /* Move to the next page */
6046 /* Set the length for the next iteration */
6047 len = imin(PAGE_SIZE, sz);
6053 pmap_fault(pmap_t pmap, uint64_t esr, uint64_t far)
6055 pt_entry_t pte, *ptep;
6060 PMAP_ASSERT_STAGE1(pmap);
6063 ec = ESR_ELx_EXCEPTION(esr);
6065 case EXCP_INSN_ABORT_L:
6066 case EXCP_INSN_ABORT:
6067 case EXCP_DATA_ABORT_L:
6068 case EXCP_DATA_ABORT:
6074 /* Data and insn aborts use same encoding for FSC field. */
6075 switch (esr & ISS_DATA_DFSC_MASK) {
6076 case ISS_DATA_DFSC_AFF_L1:
6077 case ISS_DATA_DFSC_AFF_L2:
6078 case ISS_DATA_DFSC_AFF_L3:
6080 ptep = pmap_pte(pmap, far, &lvl);
6082 pmap_set_bits(ptep, ATTR_AF);
6085 * XXXMJ as an optimization we could mark the entry
6086 * dirty if this is a write fault.
6091 case ISS_DATA_DFSC_PF_L1:
6092 case ISS_DATA_DFSC_PF_L2:
6093 case ISS_DATA_DFSC_PF_L3:
6094 if ((ec != EXCP_DATA_ABORT_L && ec != EXCP_DATA_ABORT) ||
6095 (esr & ISS_DATA_WnR) == 0)
6098 ptep = pmap_pte(pmap, far, &lvl);
6100 ((pte = pmap_load(ptep)) & ATTR_SW_DBM) != 0) {
6101 if ((pte & ATTR_S1_AP_RW_BIT) ==
6102 ATTR_S1_AP(ATTR_S1_AP_RO)) {
6103 pmap_clear_bits(ptep, ATTR_S1_AP_RW_BIT);
6104 pmap_invalidate_page(pmap, far);
6110 case ISS_DATA_DFSC_TF_L0:
6111 case ISS_DATA_DFSC_TF_L1:
6112 case ISS_DATA_DFSC_TF_L2:
6113 case ISS_DATA_DFSC_TF_L3:
6115 * Retry the translation. A break-before-make sequence can
6116 * produce a transient fault.
6118 if (pmap == kernel_pmap) {
6120 * The translation fault may have occurred within a
6121 * critical section. Therefore, we must check the
6122 * address without acquiring the kernel pmap's lock.
6124 if (pmap_kextract(far) != 0)
6128 /* Ask the MMU to check the address. */
6129 intr = intr_disable();
6130 par = arm64_address_translate_s1e0r(far);
6135 * If the translation was successful, then we can
6136 * return success to the trap handler.
6138 if (PAR_SUCCESS(par))
6148 * Increase the starting virtual address of the given mapping if a
6149 * different alignment might result in more superpage mappings.
6152 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
6153 vm_offset_t *addr, vm_size_t size)
6155 vm_offset_t superpage_offset;
6159 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
6160 offset += ptoa(object->pg_color);
6161 superpage_offset = offset & L2_OFFSET;
6162 if (size - ((L2_SIZE - superpage_offset) & L2_OFFSET) < L2_SIZE ||
6163 (*addr & L2_OFFSET) == superpage_offset)
6165 if ((*addr & L2_OFFSET) < superpage_offset)
6166 *addr = (*addr & ~L2_OFFSET) + superpage_offset;
6168 *addr = ((*addr + L2_OFFSET) & ~L2_OFFSET) + superpage_offset;
6172 * Get the kernel virtual address of a set of physical pages. If there are
6173 * physical addresses not covered by the DMAP perform a transient mapping
6174 * that will be removed when calling pmap_unmap_io_transient.
6176 * \param page The pages the caller wishes to obtain the virtual
6177 * address on the kernel memory map.
6178 * \param vaddr On return contains the kernel virtual memory address
6179 * of the pages passed in the page parameter.
6180 * \param count Number of pages passed in.
6181 * \param can_fault TRUE if the thread using the mapped pages can take
6182 * page faults, FALSE otherwise.
6184 * \returns TRUE if the caller must call pmap_unmap_io_transient when
6185 * finished or FALSE otherwise.
6189 pmap_map_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
6190 boolean_t can_fault)
6193 boolean_t needs_mapping;
6197 * Allocate any KVA space that we need, this is done in a separate
6198 * loop to prevent calling vmem_alloc while pinned.
6200 needs_mapping = FALSE;
6201 for (i = 0; i < count; i++) {
6202 paddr = VM_PAGE_TO_PHYS(page[i]);
6203 if (__predict_false(!PHYS_IN_DMAP(paddr))) {
6204 error = vmem_alloc(kernel_arena, PAGE_SIZE,
6205 M_BESTFIT | M_WAITOK, &vaddr[i]);
6206 KASSERT(error == 0, ("vmem_alloc failed: %d", error));
6207 needs_mapping = TRUE;
6209 vaddr[i] = PHYS_TO_DMAP(paddr);
6213 /* Exit early if everything is covered by the DMAP */
6219 for (i = 0; i < count; i++) {
6220 paddr = VM_PAGE_TO_PHYS(page[i]);
6221 if (!PHYS_IN_DMAP(paddr)) {
6223 "pmap_map_io_transient: TODO: Map out of DMAP data");
6227 return (needs_mapping);
6231 pmap_unmap_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
6232 boolean_t can_fault)
6239 for (i = 0; i < count; i++) {
6240 paddr = VM_PAGE_TO_PHYS(page[i]);
6241 if (!PHYS_IN_DMAP(paddr)) {
6242 panic("ARM64TODO: pmap_unmap_io_transient: Unmap data");
6248 pmap_is_valid_memattr(pmap_t pmap __unused, vm_memattr_t mode)
6251 return (mode >= VM_MEMATTR_DEVICE && mode <= VM_MEMATTR_WRITE_THROUGH);
6255 * Track a range of the kernel's virtual address space that is contiguous
6256 * in various mapping attributes.
6258 struct pmap_kernel_map_range {
6268 sysctl_kmaps_dump(struct sbuf *sb, struct pmap_kernel_map_range *range,
6274 if (eva <= range->sva)
6277 index = range->attrs & ATTR_S1_IDX_MASK;
6279 case ATTR_S1_IDX(VM_MEMATTR_DEVICE):
6282 case ATTR_S1_IDX(VM_MEMATTR_UNCACHEABLE):
6285 case ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK):
6288 case ATTR_S1_IDX(VM_MEMATTR_WRITE_THROUGH):
6293 "%s: unknown memory type %x for range 0x%016lx-0x%016lx\n",
6294 __func__, index, range->sva, eva);
6299 sbuf_printf(sb, "0x%016lx-0x%016lx r%c%c%c %3s %d %d %d %d\n",
6301 (range->attrs & ATTR_S1_AP_RW_BIT) == ATTR_S1_AP_RW ? 'w' : '-',
6302 (range->attrs & ATTR_S1_PXN) != 0 ? '-' : 'x',
6303 (range->attrs & ATTR_S1_AP_USER) != 0 ? 'u' : 's',
6304 mode, range->l1blocks, range->l2blocks, range->l3contig,
6307 /* Reset to sentinel value. */
6308 range->sva = 0xfffffffffffffffful;
6312 * Determine whether the attributes specified by a page table entry match those
6313 * being tracked by the current range.
6316 sysctl_kmaps_match(struct pmap_kernel_map_range *range, pt_entry_t attrs)
6319 return (range->attrs == attrs);
6323 sysctl_kmaps_reinit(struct pmap_kernel_map_range *range, vm_offset_t va,
6327 memset(range, 0, sizeof(*range));
6329 range->attrs = attrs;
6333 * Given a leaf PTE, derive the mapping's attributes. If they do not match
6334 * those of the current run, dump the address range and its attributes, and
6338 sysctl_kmaps_check(struct sbuf *sb, struct pmap_kernel_map_range *range,
6339 vm_offset_t va, pd_entry_t l0e, pd_entry_t l1e, pd_entry_t l2e,
6344 attrs = l0e & (ATTR_S1_AP_MASK | ATTR_S1_XN);
6345 attrs |= l1e & (ATTR_S1_AP_MASK | ATTR_S1_XN);
6346 if ((l1e & ATTR_DESCR_MASK) == L1_BLOCK)
6347 attrs |= l1e & ATTR_S1_IDX_MASK;
6348 attrs |= l2e & (ATTR_S1_AP_MASK | ATTR_S1_XN);
6349 if ((l2e & ATTR_DESCR_MASK) == L2_BLOCK)
6350 attrs |= l2e & ATTR_S1_IDX_MASK;
6351 attrs |= l3e & (ATTR_S1_AP_MASK | ATTR_S1_XN | ATTR_S1_IDX_MASK);
6353 if (range->sva > va || !sysctl_kmaps_match(range, attrs)) {
6354 sysctl_kmaps_dump(sb, range, va);
6355 sysctl_kmaps_reinit(range, va, attrs);
6360 sysctl_kmaps(SYSCTL_HANDLER_ARGS)
6362 struct pmap_kernel_map_range range;
6363 struct sbuf sbuf, *sb;
6364 pd_entry_t l0e, *l1, l1e, *l2, l2e;
6365 pt_entry_t *l3, l3e;
6368 int error, i, j, k, l;
6370 error = sysctl_wire_old_buffer(req, 0);
6374 sbuf_new_for_sysctl(sb, NULL, PAGE_SIZE, req);
6376 /* Sentinel value. */
6377 range.sva = 0xfffffffffffffffful;
6380 * Iterate over the kernel page tables without holding the kernel pmap
6381 * lock. Kernel page table pages are never freed, so at worst we will
6382 * observe inconsistencies in the output.
6384 for (sva = 0xffff000000000000ul, i = pmap_l0_index(sva); i < Ln_ENTRIES;
6386 if (i == pmap_l0_index(DMAP_MIN_ADDRESS))
6387 sbuf_printf(sb, "\nDirect map:\n");
6388 else if (i == pmap_l0_index(VM_MIN_KERNEL_ADDRESS))
6389 sbuf_printf(sb, "\nKernel map:\n");
6391 l0e = kernel_pmap->pm_l0[i];
6392 if ((l0e & ATTR_DESCR_VALID) == 0) {
6393 sysctl_kmaps_dump(sb, &range, sva);
6397 pa = l0e & ~ATTR_MASK;
6398 l1 = (pd_entry_t *)PHYS_TO_DMAP(pa);
6400 for (j = pmap_l1_index(sva); j < Ln_ENTRIES; j++) {
6402 if ((l1e & ATTR_DESCR_VALID) == 0) {
6403 sysctl_kmaps_dump(sb, &range, sva);
6407 if ((l1e & ATTR_DESCR_MASK) == L1_BLOCK) {
6408 sysctl_kmaps_check(sb, &range, sva, l0e, l1e,
6414 pa = l1e & ~ATTR_MASK;
6415 l2 = (pd_entry_t *)PHYS_TO_DMAP(pa);
6417 for (k = pmap_l2_index(sva); k < Ln_ENTRIES; k++) {
6419 if ((l2e & ATTR_DESCR_VALID) == 0) {
6420 sysctl_kmaps_dump(sb, &range, sva);
6424 if ((l2e & ATTR_DESCR_MASK) == L2_BLOCK) {
6425 sysctl_kmaps_check(sb, &range, sva,
6431 pa = l2e & ~ATTR_MASK;
6432 l3 = (pt_entry_t *)PHYS_TO_DMAP(pa);
6434 for (l = pmap_l3_index(sva); l < Ln_ENTRIES;
6435 l++, sva += L3_SIZE) {
6437 if ((l3e & ATTR_DESCR_VALID) == 0) {
6438 sysctl_kmaps_dump(sb, &range,
6442 sysctl_kmaps_check(sb, &range, sva,
6443 l0e, l1e, l2e, l3e);
6444 if ((l3e & ATTR_CONTIGUOUS) != 0)
6445 range.l3contig += l % 16 == 0 ?
6454 error = sbuf_finish(sb);
6458 SYSCTL_OID(_vm_pmap, OID_AUTO, kernel_maps,
6459 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE,
6460 NULL, 0, sysctl_kmaps, "A",
6461 "Dump kernel address layout");