2 * Copyright (c) 1991 Regents of the University of California.
4 * Copyright (c) 1994 John S. Dyson
6 * Copyright (c) 1994 David Greenman
8 * Copyright (c) 2003 Peter Wemm
10 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
11 * All rights reserved.
12 * Copyright (c) 2014 Andrew Turner
13 * All rights reserved.
14 * Copyright (c) 2014-2016 The FreeBSD Foundation
15 * All rights reserved.
17 * This code is derived from software contributed to Berkeley by
18 * the Systems Programming Group of the University of Utah Computer
19 * Science Department and William Jolitz of UUNET Technologies Inc.
21 * This software was developed by Andrew Turner under sponsorship from
22 * the FreeBSD Foundation.
24 * Redistribution and use in source and binary forms, with or without
25 * modification, are permitted provided that the following conditions
27 * 1. Redistributions of source code must retain the above copyright
28 * notice, this list of conditions and the following disclaimer.
29 * 2. Redistributions in binary form must reproduce the above copyright
30 * notice, this list of conditions and the following disclaimer in the
31 * documentation and/or other materials provided with the distribution.
32 * 3. All advertising materials mentioning features or use of this software
33 * must display the following acknowledgement:
34 * This product includes software developed by the University of
35 * California, Berkeley and its contributors.
36 * 4. Neither the name of the University nor the names of its contributors
37 * may be used to endorse or promote products derived from this software
38 * without specific prior written permission.
40 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
41 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
42 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
43 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
44 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
45 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
46 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
47 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
48 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
49 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
52 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
55 * Copyright (c) 2003 Networks Associates Technology, Inc.
56 * All rights reserved.
58 * This software was developed for the FreeBSD Project by Jake Burkholder,
59 * Safeport Network Services, and Network Associates Laboratories, the
60 * Security Research Division of Network Associates, Inc. under
61 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
62 * CHATS research program.
64 * Redistribution and use in source and binary forms, with or without
65 * modification, are permitted provided that the following conditions
67 * 1. Redistributions of source code must retain the above copyright
68 * notice, this list of conditions and the following disclaimer.
69 * 2. Redistributions in binary form must reproduce the above copyright
70 * notice, this list of conditions and the following disclaimer in the
71 * documentation and/or other materials provided with the distribution.
73 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
74 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
77 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
78 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
79 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
80 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
81 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
82 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
86 #include <sys/cdefs.h>
87 __FBSDID("$FreeBSD$");
90 * Manages physical address maps.
92 * Since the information managed by this module is
93 * also stored by the logical address mapping module,
94 * this module may throw away valid virtual-to-physical
95 * mappings at almost any time. However, invalidations
96 * of virtual-to-physical mappings must be done as
99 * In order to cope with hardware architectures which
100 * make virtual-to-physical map invalidates expensive,
101 * this module may delay invalidate or reduced protection
102 * operations until such time as they are actually
103 * necessary. This module is given full information as
104 * to which processors are currently using which maps,
105 * and to when physical maps must be made correct.
110 #include <sys/param.h>
111 #include <sys/bitstring.h>
113 #include <sys/systm.h>
114 #include <sys/kernel.h>
116 #include <sys/limits.h>
117 #include <sys/lock.h>
118 #include <sys/malloc.h>
119 #include <sys/mman.h>
120 #include <sys/msgbuf.h>
121 #include <sys/mutex.h>
122 #include <sys/physmem.h>
123 #include <sys/proc.h>
124 #include <sys/rwlock.h>
125 #include <sys/sbuf.h>
127 #include <sys/vmem.h>
128 #include <sys/vmmeter.h>
129 #include <sys/sched.h>
130 #include <sys/sysctl.h>
131 #include <sys/_unrhdr.h>
135 #include <vm/vm_param.h>
136 #include <vm/vm_kern.h>
137 #include <vm/vm_page.h>
138 #include <vm/vm_map.h>
139 #include <vm/vm_object.h>
140 #include <vm/vm_extern.h>
141 #include <vm/vm_pageout.h>
142 #include <vm/vm_pager.h>
143 #include <vm/vm_phys.h>
144 #include <vm/vm_radix.h>
145 #include <vm/vm_reserv.h>
148 #include <machine/machdep.h>
149 #include <machine/md_var.h>
150 #include <machine/pcb.h>
152 #define PMAP_ASSERT_STAGE1(pmap) MPASS((pmap)->pm_stage == PM_STAGE1)
153 #define PMAP_ASSERT_STAGE2(pmap) MPASS((pmap)->pm_stage == PM_STAGE2)
155 #define NL0PG (PAGE_SIZE/(sizeof (pd_entry_t)))
156 #define NL1PG (PAGE_SIZE/(sizeof (pd_entry_t)))
157 #define NL2PG (PAGE_SIZE/(sizeof (pd_entry_t)))
158 #define NL3PG (PAGE_SIZE/(sizeof (pt_entry_t)))
160 #define NUL0E L0_ENTRIES
161 #define NUL1E (NUL0E * NL1PG)
162 #define NUL2E (NUL1E * NL2PG)
164 #if !defined(DIAGNOSTIC)
165 #ifdef __GNUC_GNU_INLINE__
166 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
168 #define PMAP_INLINE extern inline
175 #define PV_STAT(x) do { x ; } while (0)
177 #define PV_STAT(x) do { } while (0)
180 #define pmap_l2_pindex(v) ((v) >> L2_SHIFT)
181 #define pa_to_pvh(pa) (&pv_table[pmap_l2_pindex(pa)])
183 #define NPV_LIST_LOCKS MAXCPU
185 #define PHYS_TO_PV_LIST_LOCK(pa) \
186 (&pv_list_locks[pa_index(pa) % NPV_LIST_LOCKS])
188 #define CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa) do { \
189 struct rwlock **_lockp = (lockp); \
190 struct rwlock *_new_lock; \
192 _new_lock = PHYS_TO_PV_LIST_LOCK(pa); \
193 if (_new_lock != *_lockp) { \
194 if (*_lockp != NULL) \
195 rw_wunlock(*_lockp); \
196 *_lockp = _new_lock; \
201 #define CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m) \
202 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, VM_PAGE_TO_PHYS(m))
204 #define RELEASE_PV_LIST_LOCK(lockp) do { \
205 struct rwlock **_lockp = (lockp); \
207 if (*_lockp != NULL) { \
208 rw_wunlock(*_lockp); \
213 #define VM_PAGE_TO_PV_LIST_LOCK(m) \
214 PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m))
217 * The presence of this flag indicates that the mapping is writeable.
218 * If the ATTR_S1_AP_RO bit is also set, then the mapping is clean, otherwise
219 * it is dirty. This flag may only be set on managed mappings.
221 * The DBM bit is reserved on ARMv8.0 but it seems we can safely treat it
222 * as a software managed bit.
224 #define ATTR_SW_DBM ATTR_DBM
226 struct pmap kernel_pmap_store;
228 /* Used for mapping ACPI memory before VM is initialized */
229 #define PMAP_PREINIT_MAPPING_COUNT 32
230 #define PMAP_PREINIT_MAPPING_SIZE (PMAP_PREINIT_MAPPING_COUNT * L2_SIZE)
231 static vm_offset_t preinit_map_va; /* Start VA of pre-init mapping space */
232 static int vm_initialized = 0; /* No need to use pre-init maps when set */
235 * Reserve a few L2 blocks starting from 'preinit_map_va' pointer.
236 * Always map entire L2 block for simplicity.
237 * VA of L2 block = preinit_map_va + i * L2_SIZE
239 static struct pmap_preinit_mapping {
243 } pmap_preinit_mapping[PMAP_PREINIT_MAPPING_COUNT];
245 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
246 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
247 vm_offset_t kernel_vm_end = 0;
250 * Data for the pv entry allocation mechanism.
252 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
253 static struct mtx pv_chunks_mutex;
254 static struct rwlock pv_list_locks[NPV_LIST_LOCKS];
255 static struct md_page *pv_table;
256 static struct md_page pv_dummy;
258 vm_paddr_t dmap_phys_base; /* The start of the dmap region */
259 vm_paddr_t dmap_phys_max; /* The limit of the dmap region */
260 vm_offset_t dmap_max_addr; /* The virtual address limit of the dmap */
262 /* This code assumes all L1 DMAP entries will be used */
263 CTASSERT((DMAP_MIN_ADDRESS & ~L0_OFFSET) == DMAP_MIN_ADDRESS);
264 CTASSERT((DMAP_MAX_ADDRESS & ~L0_OFFSET) == DMAP_MAX_ADDRESS);
266 #define DMAP_TABLES ((DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS) >> L0_SHIFT)
267 extern pt_entry_t pagetable_dmap[];
269 #define PHYSMAP_SIZE (2 * (VM_PHYSSEG_MAX - 1))
270 static vm_paddr_t physmap[PHYSMAP_SIZE];
271 static u_int physmap_idx;
273 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
274 "VM/pmap parameters");
277 * This ASID allocator uses a bit vector ("asid_set") to remember which ASIDs
278 * that it has currently allocated to a pmap, a cursor ("asid_next") to
279 * optimize its search for a free ASID in the bit vector, and an epoch number
280 * ("asid_epoch") to indicate when it has reclaimed all previously allocated
281 * ASIDs that are not currently active on a processor.
283 * The current epoch number is always in the range [0, INT_MAX). Negative
284 * numbers and INT_MAX are reserved for special cases that are described
293 struct mtx asid_set_mutex;
296 static struct asid_set asids;
297 static struct asid_set vmids;
299 static SYSCTL_NODE(_vm_pmap, OID_AUTO, asid, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
301 SYSCTL_INT(_vm_pmap_asid, OID_AUTO, bits, CTLFLAG_RD, &asids.asid_bits, 0,
302 "The number of bits in an ASID");
303 SYSCTL_INT(_vm_pmap_asid, OID_AUTO, next, CTLFLAG_RD, &asids.asid_next, 0,
304 "The last allocated ASID plus one");
305 SYSCTL_INT(_vm_pmap_asid, OID_AUTO, epoch, CTLFLAG_RD, &asids.asid_epoch, 0,
306 "The current epoch number");
308 static SYSCTL_NODE(_vm_pmap, OID_AUTO, vmid, CTLFLAG_RD, 0, "VMID allocator");
309 SYSCTL_INT(_vm_pmap_vmid, OID_AUTO, bits, CTLFLAG_RD, &vmids.asid_bits, 0,
310 "The number of bits in an VMID");
311 SYSCTL_INT(_vm_pmap_vmid, OID_AUTO, next, CTLFLAG_RD, &vmids.asid_next, 0,
312 "The last allocated VMID plus one");
313 SYSCTL_INT(_vm_pmap_vmid, OID_AUTO, epoch, CTLFLAG_RD, &vmids.asid_epoch, 0,
314 "The current epoch number");
316 void (*pmap_clean_stage2_tlbi)(void);
317 void (*pmap_invalidate_vpipt_icache)(void);
320 * A pmap's cookie encodes an ASID and epoch number. Cookies for reserved
321 * ASIDs have a negative epoch number, specifically, INT_MIN. Cookies for
322 * dynamically allocated ASIDs have a non-negative epoch number.
324 * An invalid ASID is represented by -1.
326 * There are two special-case cookie values: (1) COOKIE_FROM(-1, INT_MIN),
327 * which indicates that an ASID should never be allocated to the pmap, and
328 * (2) COOKIE_FROM(-1, INT_MAX), which indicates that an ASID should be
329 * allocated when the pmap is next activated.
331 #define COOKIE_FROM(asid, epoch) ((long)((u_int)(asid) | \
332 ((u_long)(epoch) << 32)))
333 #define COOKIE_TO_ASID(cookie) ((int)(cookie))
334 #define COOKIE_TO_EPOCH(cookie) ((int)((u_long)(cookie) >> 32))
336 static int superpages_enabled = 1;
337 SYSCTL_INT(_vm_pmap, OID_AUTO, superpages_enabled,
338 CTLFLAG_RDTUN | CTLFLAG_NOFETCH, &superpages_enabled, 0,
339 "Are large page mappings enabled?");
342 * Internal flags for pmap_enter()'s helper functions.
344 #define PMAP_ENTER_NORECLAIM 0x1000000 /* Don't reclaim PV entries. */
345 #define PMAP_ENTER_NOREPLACE 0x2000000 /* Don't replace mappings. */
347 static void free_pv_chunk(struct pv_chunk *pc);
348 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
349 static pv_entry_t get_pv_entry(pmap_t pmap, struct rwlock **lockp);
350 static vm_page_t reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp);
351 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
352 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
355 static void pmap_abort_ptp(pmap_t pmap, vm_offset_t va, vm_page_t mpte);
356 static bool pmap_activate_int(pmap_t pmap);
357 static void pmap_alloc_asid(pmap_t pmap);
358 static int pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode);
359 static pt_entry_t *pmap_demote_l1(pmap_t pmap, pt_entry_t *l1, vm_offset_t va);
360 static pt_entry_t *pmap_demote_l2_locked(pmap_t pmap, pt_entry_t *l2,
361 vm_offset_t va, struct rwlock **lockp);
362 static pt_entry_t *pmap_demote_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t va);
363 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
364 vm_page_t m, vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp);
365 static int pmap_enter_l2(pmap_t pmap, vm_offset_t va, pd_entry_t new_l2,
366 u_int flags, vm_page_t m, struct rwlock **lockp);
367 static int pmap_remove_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t sva,
368 pd_entry_t l1e, struct spglist *free, struct rwlock **lockp);
369 static int pmap_remove_l3(pmap_t pmap, pt_entry_t *l3, vm_offset_t sva,
370 pd_entry_t l2e, struct spglist *free, struct rwlock **lockp);
371 static void pmap_reset_asid_set(pmap_t pmap);
372 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
373 vm_page_t m, struct rwlock **lockp);
375 static vm_page_t _pmap_alloc_l3(pmap_t pmap, vm_pindex_t ptepindex,
376 struct rwlock **lockp);
378 static void _pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m,
379 struct spglist *free);
380 static int pmap_unuse_pt(pmap_t, vm_offset_t, pd_entry_t, struct spglist *);
381 static __inline vm_page_t pmap_remove_pt_page(pmap_t pmap, vm_offset_t va);
384 * These load the old table data and store the new value.
385 * They need to be atomic as the System MMU may write to the table at
386 * the same time as the CPU.
388 #define pmap_clear(table) atomic_store_64(table, 0)
389 #define pmap_clear_bits(table, bits) atomic_clear_64(table, bits)
390 #define pmap_load(table) (*table)
391 #define pmap_load_clear(table) atomic_swap_64(table, 0)
392 #define pmap_load_store(table, entry) atomic_swap_64(table, entry)
393 #define pmap_set_bits(table, bits) atomic_set_64(table, bits)
394 #define pmap_store(table, entry) atomic_store_64(table, entry)
396 /********************/
397 /* Inline functions */
398 /********************/
401 pagecopy(void *s, void *d)
404 memcpy(d, s, PAGE_SIZE);
407 static __inline pd_entry_t *
408 pmap_l0(pmap_t pmap, vm_offset_t va)
411 return (&pmap->pm_l0[pmap_l0_index(va)]);
414 static __inline pd_entry_t *
415 pmap_l0_to_l1(pd_entry_t *l0, vm_offset_t va)
419 l1 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l0) & ~ATTR_MASK);
420 return (&l1[pmap_l1_index(va)]);
423 static __inline pd_entry_t *
424 pmap_l1(pmap_t pmap, vm_offset_t va)
428 l0 = pmap_l0(pmap, va);
429 if ((pmap_load(l0) & ATTR_DESCR_MASK) != L0_TABLE)
432 return (pmap_l0_to_l1(l0, va));
435 static __inline pd_entry_t *
436 pmap_l1_to_l2(pd_entry_t *l1, vm_offset_t va)
440 l2 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l1) & ~ATTR_MASK);
441 return (&l2[pmap_l2_index(va)]);
444 static __inline pd_entry_t *
445 pmap_l2(pmap_t pmap, vm_offset_t va)
449 l1 = pmap_l1(pmap, va);
450 if ((pmap_load(l1) & ATTR_DESCR_MASK) != L1_TABLE)
453 return (pmap_l1_to_l2(l1, va));
456 static __inline pt_entry_t *
457 pmap_l2_to_l3(pd_entry_t *l2, vm_offset_t va)
461 l3 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l2) & ~ATTR_MASK);
462 return (&l3[pmap_l3_index(va)]);
466 * Returns the lowest valid pde for a given virtual address.
467 * The next level may or may not point to a valid page or block.
469 static __inline pd_entry_t *
470 pmap_pde(pmap_t pmap, vm_offset_t va, int *level)
472 pd_entry_t *l0, *l1, *l2, desc;
474 l0 = pmap_l0(pmap, va);
475 desc = pmap_load(l0) & ATTR_DESCR_MASK;
476 if (desc != L0_TABLE) {
481 l1 = pmap_l0_to_l1(l0, va);
482 desc = pmap_load(l1) & ATTR_DESCR_MASK;
483 if (desc != L1_TABLE) {
488 l2 = pmap_l1_to_l2(l1, va);
489 desc = pmap_load(l2) & ATTR_DESCR_MASK;
490 if (desc != L2_TABLE) {
500 * Returns the lowest valid pte block or table entry for a given virtual
501 * address. If there are no valid entries return NULL and set the level to
502 * the first invalid level.
504 static __inline pt_entry_t *
505 pmap_pte(pmap_t pmap, vm_offset_t va, int *level)
507 pd_entry_t *l1, *l2, desc;
510 l1 = pmap_l1(pmap, va);
515 desc = pmap_load(l1) & ATTR_DESCR_MASK;
516 if (desc == L1_BLOCK) {
521 if (desc != L1_TABLE) {
526 l2 = pmap_l1_to_l2(l1, va);
527 desc = pmap_load(l2) & ATTR_DESCR_MASK;
528 if (desc == L2_BLOCK) {
533 if (desc != L2_TABLE) {
539 l3 = pmap_l2_to_l3(l2, va);
540 if ((pmap_load(l3) & ATTR_DESCR_MASK) != L3_PAGE)
547 pmap_ps_enabled(pmap_t pmap __unused)
550 return (superpages_enabled != 0);
554 pmap_get_tables(pmap_t pmap, vm_offset_t va, pd_entry_t **l0, pd_entry_t **l1,
555 pd_entry_t **l2, pt_entry_t **l3)
557 pd_entry_t *l0p, *l1p, *l2p;
559 if (pmap->pm_l0 == NULL)
562 l0p = pmap_l0(pmap, va);
565 if ((pmap_load(l0p) & ATTR_DESCR_MASK) != L0_TABLE)
568 l1p = pmap_l0_to_l1(l0p, va);
571 if ((pmap_load(l1p) & ATTR_DESCR_MASK) == L1_BLOCK) {
577 if ((pmap_load(l1p) & ATTR_DESCR_MASK) != L1_TABLE)
580 l2p = pmap_l1_to_l2(l1p, va);
583 if ((pmap_load(l2p) & ATTR_DESCR_MASK) == L2_BLOCK) {
588 if ((pmap_load(l2p) & ATTR_DESCR_MASK) != L2_TABLE)
591 *l3 = pmap_l2_to_l3(l2p, va);
597 pmap_l3_valid(pt_entry_t l3)
600 return ((l3 & ATTR_DESCR_MASK) == L3_PAGE);
604 CTASSERT(L1_BLOCK == L2_BLOCK);
607 pmap_pte_memattr(pmap_t pmap, vm_memattr_t memattr)
611 if (pmap->pm_stage == PM_STAGE1) {
612 val = ATTR_S1_IDX(memattr);
613 if (memattr == VM_MEMATTR_DEVICE)
621 case VM_MEMATTR_DEVICE:
622 return (ATTR_S2_MEMATTR(ATTR_S2_MEMATTR_DEVICE_nGnRnE) |
623 ATTR_S2_XN(ATTR_S2_XN_ALL));
624 case VM_MEMATTR_UNCACHEABLE:
625 return (ATTR_S2_MEMATTR(ATTR_S2_MEMATTR_NC));
626 case VM_MEMATTR_WRITE_BACK:
627 return (ATTR_S2_MEMATTR(ATTR_S2_MEMATTR_WB));
628 case VM_MEMATTR_WRITE_THROUGH:
629 return (ATTR_S2_MEMATTR(ATTR_S2_MEMATTR_WT));
631 panic("%s: invalid memory attribute %x", __func__, memattr);
636 pmap_pte_prot(pmap_t pmap, vm_prot_t prot)
641 if (pmap->pm_stage == PM_STAGE1) {
642 if ((prot & VM_PROT_EXECUTE) == 0)
644 if ((prot & VM_PROT_WRITE) == 0)
645 val |= ATTR_S1_AP(ATTR_S1_AP_RO);
647 if ((prot & VM_PROT_WRITE) != 0)
648 val |= ATTR_S2_S2AP(ATTR_S2_S2AP_WRITE);
649 if ((prot & VM_PROT_READ) != 0)
650 val |= ATTR_S2_S2AP(ATTR_S2_S2AP_READ);
651 if ((prot & VM_PROT_EXECUTE) == 0)
652 val |= ATTR_S2_XN(ATTR_S2_XN_ALL);
659 * Checks if the PTE is dirty.
662 pmap_pte_dirty(pmap_t pmap, pt_entry_t pte)
665 KASSERT((pte & ATTR_SW_MANAGED) != 0, ("pte %#lx is unmanaged", pte));
667 if (pmap->pm_stage == PM_STAGE1) {
668 KASSERT((pte & (ATTR_S1_AP_RW_BIT | ATTR_SW_DBM)) != 0,
669 ("pte %#lx is writeable and missing ATTR_SW_DBM", pte));
671 return ((pte & (ATTR_S1_AP_RW_BIT | ATTR_SW_DBM)) ==
672 (ATTR_S1_AP(ATTR_S1_AP_RW) | ATTR_SW_DBM));
675 return ((pte & ATTR_S2_S2AP(ATTR_S2_S2AP_WRITE)) ==
676 ATTR_S2_S2AP(ATTR_S2_S2AP_WRITE));
680 pmap_resident_count_inc(pmap_t pmap, int count)
683 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
684 pmap->pm_stats.resident_count += count;
688 pmap_resident_count_dec(pmap_t pmap, int count)
691 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
692 KASSERT(pmap->pm_stats.resident_count >= count,
693 ("pmap %p resident count underflow %ld %d", pmap,
694 pmap->pm_stats.resident_count, count));
695 pmap->pm_stats.resident_count -= count;
699 pmap_early_page_idx(vm_offset_t l1pt, vm_offset_t va, u_int *l1_slot,
705 l1 = (pd_entry_t *)l1pt;
706 *l1_slot = (va >> L1_SHIFT) & Ln_ADDR_MASK;
708 /* Check locore has used a table L1 map */
709 KASSERT((l1[*l1_slot] & ATTR_DESCR_MASK) == L1_TABLE,
710 ("Invalid bootstrap L1 table"));
711 /* Find the address of the L2 table */
712 l2 = (pt_entry_t *)init_pt_va;
713 *l2_slot = pmap_l2_index(va);
719 pmap_early_vtophys(vm_offset_t l1pt, vm_offset_t va)
721 u_int l1_slot, l2_slot;
724 l2 = pmap_early_page_idx(l1pt, va, &l1_slot, &l2_slot);
726 return ((l2[l2_slot] & ~ATTR_MASK) + (va & L2_OFFSET));
730 pmap_bootstrap_dmap(vm_offset_t kern_l1, vm_paddr_t min_pa,
731 vm_offset_t freemempos)
735 vm_paddr_t l2_pa, pa;
736 u_int l1_slot, l2_slot, prev_l1_slot;
739 dmap_phys_base = min_pa & ~L1_OFFSET;
745 #define DMAP_TABLES ((DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS) >> L0_SHIFT)
746 memset(pagetable_dmap, 0, PAGE_SIZE * DMAP_TABLES);
748 for (i = 0; i < (physmap_idx * 2); i += 2) {
749 pa = physmap[i] & ~L2_OFFSET;
750 va = pa - dmap_phys_base + DMAP_MIN_ADDRESS;
752 /* Create L2 mappings at the start of the region */
753 if ((pa & L1_OFFSET) != 0) {
754 l1_slot = ((va - DMAP_MIN_ADDRESS) >> L1_SHIFT);
755 if (l1_slot != prev_l1_slot) {
756 prev_l1_slot = l1_slot;
757 l2 = (pt_entry_t *)freemempos;
758 l2_pa = pmap_early_vtophys(kern_l1,
760 freemempos += PAGE_SIZE;
762 pmap_store(&pagetable_dmap[l1_slot],
763 (l2_pa & ~Ln_TABLE_MASK) | L1_TABLE);
765 memset(l2, 0, PAGE_SIZE);
768 ("pmap_bootstrap_dmap: NULL l2 map"));
769 for (; va < DMAP_MAX_ADDRESS && pa < physmap[i + 1];
770 pa += L2_SIZE, va += L2_SIZE) {
772 * We are on a boundary, stop to
773 * create a level 1 block
775 if ((pa & L1_OFFSET) == 0)
778 l2_slot = pmap_l2_index(va);
779 KASSERT(l2_slot != 0, ("..."));
780 pmap_store(&l2[l2_slot],
781 (pa & ~L2_OFFSET) | ATTR_DEFAULT |
783 ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK) |
786 KASSERT(va == (pa - dmap_phys_base + DMAP_MIN_ADDRESS),
790 for (; va < DMAP_MAX_ADDRESS && pa < physmap[i + 1] &&
791 (physmap[i + 1] - pa) >= L1_SIZE;
792 pa += L1_SIZE, va += L1_SIZE) {
793 l1_slot = ((va - DMAP_MIN_ADDRESS) >> L1_SHIFT);
794 pmap_store(&pagetable_dmap[l1_slot],
795 (pa & ~L1_OFFSET) | ATTR_DEFAULT | ATTR_S1_XN |
796 ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK) | L1_BLOCK);
799 /* Create L2 mappings at the end of the region */
800 if (pa < physmap[i + 1]) {
801 l1_slot = ((va - DMAP_MIN_ADDRESS) >> L1_SHIFT);
802 if (l1_slot != prev_l1_slot) {
803 prev_l1_slot = l1_slot;
804 l2 = (pt_entry_t *)freemempos;
805 l2_pa = pmap_early_vtophys(kern_l1,
807 freemempos += PAGE_SIZE;
809 pmap_store(&pagetable_dmap[l1_slot],
810 (l2_pa & ~Ln_TABLE_MASK) | L1_TABLE);
812 memset(l2, 0, PAGE_SIZE);
815 ("pmap_bootstrap_dmap: NULL l2 map"));
816 for (; va < DMAP_MAX_ADDRESS && pa < physmap[i + 1];
817 pa += L2_SIZE, va += L2_SIZE) {
818 l2_slot = pmap_l2_index(va);
819 pmap_store(&l2[l2_slot],
820 (pa & ~L2_OFFSET) | ATTR_DEFAULT |
822 ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK) |
827 if (pa > dmap_phys_max) {
839 pmap_bootstrap_l2(vm_offset_t l1pt, vm_offset_t va, vm_offset_t l2_start)
846 KASSERT((va & L1_OFFSET) == 0, ("Invalid virtual address"));
848 l1 = (pd_entry_t *)l1pt;
849 l1_slot = pmap_l1_index(va);
852 for (; va < VM_MAX_KERNEL_ADDRESS; l1_slot++, va += L1_SIZE) {
853 KASSERT(l1_slot < Ln_ENTRIES, ("Invalid L1 index"));
855 pa = pmap_early_vtophys(l1pt, l2pt);
856 pmap_store(&l1[l1_slot],
857 (pa & ~Ln_TABLE_MASK) | L1_TABLE);
861 /* Clean the L2 page table */
862 memset((void *)l2_start, 0, l2pt - l2_start);
868 pmap_bootstrap_l3(vm_offset_t l1pt, vm_offset_t va, vm_offset_t l3_start)
875 KASSERT((va & L2_OFFSET) == 0, ("Invalid virtual address"));
877 l2 = pmap_l2(kernel_pmap, va);
878 l2 = (pd_entry_t *)rounddown2((uintptr_t)l2, PAGE_SIZE);
879 l2_slot = pmap_l2_index(va);
882 for (; va < VM_MAX_KERNEL_ADDRESS; l2_slot++, va += L2_SIZE) {
883 KASSERT(l2_slot < Ln_ENTRIES, ("Invalid L2 index"));
885 pa = pmap_early_vtophys(l1pt, l3pt);
886 pmap_store(&l2[l2_slot],
887 (pa & ~Ln_TABLE_MASK) | ATTR_S1_UXN | L2_TABLE);
891 /* Clean the L2 page table */
892 memset((void *)l3_start, 0, l3pt - l3_start);
898 * Bootstrap the system enough to run with virtual memory.
901 pmap_bootstrap(vm_offset_t l0pt, vm_offset_t l1pt, vm_paddr_t kernstart,
904 vm_offset_t freemempos;
905 vm_offset_t dpcpu, msgbufpv;
906 vm_paddr_t start_pa, pa, min_pa;
910 /* Verify that the ASID is set through TTBR0. */
911 KASSERT((READ_SPECIALREG(tcr_el1) & TCR_A1) == 0,
912 ("pmap_bootstrap: TCR_EL1.A1 != 0"));
914 kern_delta = KERNBASE - kernstart;
916 printf("pmap_bootstrap %lx %lx %lx\n", l1pt, kernstart, kernlen);
917 printf("%lx\n", l1pt);
918 printf("%lx\n", (KERNBASE >> L1_SHIFT) & Ln_ADDR_MASK);
920 /* Set this early so we can use the pagetable walking functions */
921 kernel_pmap_store.pm_l0 = (pd_entry_t *)l0pt;
922 PMAP_LOCK_INIT(kernel_pmap);
923 kernel_pmap->pm_l0_paddr = l0pt - kern_delta;
924 kernel_pmap->pm_cookie = COOKIE_FROM(-1, INT_MIN);
925 kernel_pmap->pm_stage = PM_STAGE1;
926 kernel_pmap->pm_asid_set = &asids;
928 /* Assume the address we were loaded to is a valid physical address */
929 min_pa = KERNBASE - kern_delta;
931 physmap_idx = physmem_avail(physmap, nitems(physmap));
935 * Find the minimum physical address. physmap is sorted,
936 * but may contain empty ranges.
938 for (i = 0; i < physmap_idx * 2; i += 2) {
939 if (physmap[i] == physmap[i + 1])
941 if (physmap[i] <= min_pa)
945 freemempos = KERNBASE + kernlen;
946 freemempos = roundup2(freemempos, PAGE_SIZE);
948 /* Create a direct map region early so we can use it for pa -> va */
949 freemempos = pmap_bootstrap_dmap(l1pt, min_pa, freemempos);
951 start_pa = pa = KERNBASE - kern_delta;
954 * Create the l2 tables up to VM_MAX_KERNEL_ADDRESS. We assume that the
955 * loader allocated the first and only l2 page table page used to map
956 * the kernel, preloaded files and module metadata.
958 freemempos = pmap_bootstrap_l2(l1pt, KERNBASE + L1_SIZE, freemempos);
959 /* And the l3 tables for the early devmap */
960 freemempos = pmap_bootstrap_l3(l1pt,
961 VM_MAX_KERNEL_ADDRESS - (PMAP_MAPDEV_EARLY_SIZE), freemempos);
965 #define alloc_pages(var, np) \
966 (var) = freemempos; \
967 freemempos += (np * PAGE_SIZE); \
968 memset((char *)(var), 0, ((np) * PAGE_SIZE));
970 /* Allocate dynamic per-cpu area. */
971 alloc_pages(dpcpu, DPCPU_SIZE / PAGE_SIZE);
972 dpcpu_init((void *)dpcpu, 0);
974 /* Allocate memory for the msgbuf, e.g. for /sbin/dmesg */
975 alloc_pages(msgbufpv, round_page(msgbufsize) / PAGE_SIZE);
976 msgbufp = (void *)msgbufpv;
978 /* Reserve some VA space for early BIOS/ACPI mapping */
979 preinit_map_va = roundup2(freemempos, L2_SIZE);
981 virtual_avail = preinit_map_va + PMAP_PREINIT_MAPPING_SIZE;
982 virtual_avail = roundup2(virtual_avail, L1_SIZE);
983 virtual_end = VM_MAX_KERNEL_ADDRESS - (PMAP_MAPDEV_EARLY_SIZE);
984 kernel_vm_end = virtual_avail;
986 pa = pmap_early_vtophys(l1pt, freemempos);
988 physmem_exclude_region(start_pa, pa - start_pa, EXFLAG_NOALLOC);
994 * Initialize a vm_page's machine-dependent fields.
997 pmap_page_init(vm_page_t m)
1000 TAILQ_INIT(&m->md.pv_list);
1001 m->md.pv_memattr = VM_MEMATTR_WRITE_BACK;
1005 pmap_init_asids(struct asid_set *set, int bits)
1009 set->asid_bits = bits;
1012 * We may be too early in the overall initialization process to use
1015 set->asid_set_size = 1 << set->asid_bits;
1016 set->asid_set = (bitstr_t *)kmem_malloc(bitstr_size(set->asid_set_size),
1018 for (i = 0; i < ASID_FIRST_AVAILABLE; i++)
1019 bit_set(set->asid_set, i);
1020 set->asid_next = ASID_FIRST_AVAILABLE;
1021 mtx_init(&set->asid_set_mutex, "asid set", NULL, MTX_SPIN);
1025 * Initialize the pmap module.
1026 * Called by vm_init, to initialize any structures that the pmap
1027 * system needs to map virtual memory.
1034 int i, pv_npg, vmid_bits;
1037 * Are large page mappings enabled?
1039 TUNABLE_INT_FETCH("vm.pmap.superpages_enabled", &superpages_enabled);
1040 if (superpages_enabled) {
1041 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
1042 ("pmap_init: can't assign to pagesizes[1]"));
1043 pagesizes[1] = L2_SIZE;
1047 * Initialize the ASID allocator.
1049 pmap_init_asids(&asids,
1050 (READ_SPECIALREG(tcr_el1) & TCR_ASID_16) != 0 ? 16 : 8);
1053 mmfr1 = READ_SPECIALREG(id_aa64mmfr1_el1);
1056 if (ID_AA64MMFR1_VMIDBits_VAL(mmfr1) ==
1057 ID_AA64MMFR1_VMIDBits_16)
1059 pmap_init_asids(&vmids, vmid_bits);
1063 * Initialize the pv chunk list mutex.
1065 mtx_init(&pv_chunks_mutex, "pmap pv chunk list", NULL, MTX_DEF);
1068 * Initialize the pool of pv list locks.
1070 for (i = 0; i < NPV_LIST_LOCKS; i++)
1071 rw_init(&pv_list_locks[i], "pmap pv list");
1074 * Calculate the size of the pv head table for superpages.
1076 pv_npg = howmany(vm_phys_segs[vm_phys_nsegs - 1].end, L2_SIZE);
1079 * Allocate memory for the pv head table for superpages.
1081 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
1083 pv_table = (struct md_page *)kmem_malloc(s, M_WAITOK | M_ZERO);
1084 for (i = 0; i < pv_npg; i++)
1085 TAILQ_INIT(&pv_table[i].pv_list);
1086 TAILQ_INIT(&pv_dummy.pv_list);
1091 static SYSCTL_NODE(_vm_pmap, OID_AUTO, l2, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
1092 "2MB page mapping counters");
1094 static u_long pmap_l2_demotions;
1095 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, demotions, CTLFLAG_RD,
1096 &pmap_l2_demotions, 0, "2MB page demotions");
1098 static u_long pmap_l2_mappings;
1099 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, mappings, CTLFLAG_RD,
1100 &pmap_l2_mappings, 0, "2MB page mappings");
1102 static u_long pmap_l2_p_failures;
1103 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, p_failures, CTLFLAG_RD,
1104 &pmap_l2_p_failures, 0, "2MB page promotion failures");
1106 static u_long pmap_l2_promotions;
1107 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, promotions, CTLFLAG_RD,
1108 &pmap_l2_promotions, 0, "2MB page promotions");
1111 * Invalidate a single TLB entry.
1113 static __inline void
1114 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
1118 PMAP_ASSERT_STAGE1(pmap);
1121 if (pmap == kernel_pmap) {
1123 __asm __volatile("tlbi vaae1is, %0" : : "r" (r));
1125 r = ASID_TO_OPERAND(COOKIE_TO_ASID(pmap->pm_cookie)) | atop(va);
1126 __asm __volatile("tlbi vae1is, %0" : : "r" (r));
1132 static __inline void
1133 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1135 uint64_t end, r, start;
1137 PMAP_ASSERT_STAGE1(pmap);
1140 if (pmap == kernel_pmap) {
1143 for (r = start; r < end; r++)
1144 __asm __volatile("tlbi vaae1is, %0" : : "r" (r));
1146 start = end = ASID_TO_OPERAND(COOKIE_TO_ASID(pmap->pm_cookie));
1149 for (r = start; r < end; r++)
1150 __asm __volatile("tlbi vae1is, %0" : : "r" (r));
1156 static __inline void
1157 pmap_invalidate_all(pmap_t pmap)
1161 PMAP_ASSERT_STAGE1(pmap);
1164 if (pmap == kernel_pmap) {
1165 __asm __volatile("tlbi vmalle1is");
1167 r = ASID_TO_OPERAND(COOKIE_TO_ASID(pmap->pm_cookie));
1168 __asm __volatile("tlbi aside1is, %0" : : "r" (r));
1175 * Routine: pmap_extract
1177 * Extract the physical page address associated
1178 * with the given map/virtual_address pair.
1181 pmap_extract(pmap_t pmap, vm_offset_t va)
1183 pt_entry_t *pte, tpte;
1190 * Find the block or page map for this virtual address. pmap_pte
1191 * will return either a valid block/page entry, or NULL.
1193 pte = pmap_pte(pmap, va, &lvl);
1195 tpte = pmap_load(pte);
1196 pa = tpte & ~ATTR_MASK;
1199 KASSERT((tpte & ATTR_DESCR_MASK) == L1_BLOCK,
1200 ("pmap_extract: Invalid L1 pte found: %lx",
1201 tpte & ATTR_DESCR_MASK));
1202 pa |= (va & L1_OFFSET);
1205 KASSERT((tpte & ATTR_DESCR_MASK) == L2_BLOCK,
1206 ("pmap_extract: Invalid L2 pte found: %lx",
1207 tpte & ATTR_DESCR_MASK));
1208 pa |= (va & L2_OFFSET);
1211 KASSERT((tpte & ATTR_DESCR_MASK) == L3_PAGE,
1212 ("pmap_extract: Invalid L3 pte found: %lx",
1213 tpte & ATTR_DESCR_MASK));
1214 pa |= (va & L3_OFFSET);
1223 * Routine: pmap_extract_and_hold
1225 * Atomically extract and hold the physical page
1226 * with the given pmap and virtual address pair
1227 * if that mapping permits the given protection.
1230 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1232 pt_entry_t *pte, tpte;
1240 pte = pmap_pte(pmap, va, &lvl);
1242 tpte = pmap_load(pte);
1244 KASSERT(lvl > 0 && lvl <= 3,
1245 ("pmap_extract_and_hold: Invalid level %d", lvl));
1246 CTASSERT(L1_BLOCK == L2_BLOCK);
1247 KASSERT((lvl == 3 && (tpte & ATTR_DESCR_MASK) == L3_PAGE) ||
1248 (lvl < 3 && (tpte & ATTR_DESCR_MASK) == L1_BLOCK),
1249 ("pmap_extract_and_hold: Invalid pte at L%d: %lx", lvl,
1250 tpte & ATTR_DESCR_MASK));
1253 if ((prot & VM_PROT_WRITE) == 0)
1255 else if (pmap->pm_stage == PM_STAGE1 &&
1256 (tpte & ATTR_S1_AP_RW_BIT) == ATTR_S1_AP(ATTR_S1_AP_RW))
1258 else if (pmap->pm_stage == PM_STAGE2 &&
1259 ((tpte & ATTR_S2_S2AP(ATTR_S2_S2AP_WRITE)) ==
1260 ATTR_S2_S2AP(ATTR_S2_S2AP_WRITE)))
1266 off = va & L1_OFFSET;
1269 off = va & L2_OFFSET;
1275 m = PHYS_TO_VM_PAGE((tpte & ~ATTR_MASK) | off);
1276 if (!vm_page_wire_mapped(m))
1285 pmap_kextract(vm_offset_t va)
1287 pt_entry_t *pte, tpte;
1289 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS)
1290 return (DMAP_TO_PHYS(va));
1291 pte = pmap_l1(kernel_pmap, va);
1296 * A concurrent pmap_update_entry() will clear the entry's valid bit
1297 * but leave the rest of the entry unchanged. Therefore, we treat a
1298 * non-zero entry as being valid, and we ignore the valid bit when
1299 * determining whether the entry maps a block, page, or table.
1301 tpte = pmap_load(pte);
1304 if ((tpte & ATTR_DESCR_TYPE_MASK) == ATTR_DESCR_TYPE_BLOCK)
1305 return ((tpte & ~ATTR_MASK) | (va & L1_OFFSET));
1306 pte = pmap_l1_to_l2(&tpte, va);
1307 tpte = pmap_load(pte);
1310 if ((tpte & ATTR_DESCR_TYPE_MASK) == ATTR_DESCR_TYPE_BLOCK)
1311 return ((tpte & ~ATTR_MASK) | (va & L2_OFFSET));
1312 pte = pmap_l2_to_l3(&tpte, va);
1313 tpte = pmap_load(pte);
1316 return ((tpte & ~ATTR_MASK) | (va & L3_OFFSET));
1319 /***************************************************
1320 * Low level mapping routines.....
1321 ***************************************************/
1324 pmap_kenter(vm_offset_t sva, vm_size_t size, vm_paddr_t pa, int mode)
1327 pt_entry_t *pte, attr;
1331 KASSERT((pa & L3_OFFSET) == 0,
1332 ("pmap_kenter: Invalid physical address"));
1333 KASSERT((sva & L3_OFFSET) == 0,
1334 ("pmap_kenter: Invalid virtual address"));
1335 KASSERT((size & PAGE_MASK) == 0,
1336 ("pmap_kenter: Mapping is not page-sized"));
1338 attr = ATTR_DEFAULT | ATTR_S1_AP(ATTR_S1_AP_RW) | ATTR_S1_XN |
1339 ATTR_S1_IDX(mode) | L3_PAGE;
1342 pde = pmap_pde(kernel_pmap, va, &lvl);
1343 KASSERT(pde != NULL,
1344 ("pmap_kenter: Invalid page entry, va: 0x%lx", va));
1345 KASSERT(lvl == 2, ("pmap_kenter: Invalid level %d", lvl));
1347 pte = pmap_l2_to_l3(pde, va);
1348 pmap_load_store(pte, (pa & ~L3_OFFSET) | attr);
1354 pmap_invalidate_range(kernel_pmap, sva, va);
1358 pmap_kenter_device(vm_offset_t sva, vm_size_t size, vm_paddr_t pa)
1361 pmap_kenter(sva, size, pa, VM_MEMATTR_DEVICE);
1365 * Remove a page from the kernel pagetables.
1368 pmap_kremove(vm_offset_t va)
1373 pte = pmap_pte(kernel_pmap, va, &lvl);
1374 KASSERT(pte != NULL, ("pmap_kremove: Invalid address"));
1375 KASSERT(lvl == 3, ("pmap_kremove: Invalid pte level %d", lvl));
1378 pmap_invalidate_page(kernel_pmap, va);
1382 pmap_kremove_device(vm_offset_t sva, vm_size_t size)
1388 KASSERT((sva & L3_OFFSET) == 0,
1389 ("pmap_kremove_device: Invalid virtual address"));
1390 KASSERT((size & PAGE_MASK) == 0,
1391 ("pmap_kremove_device: Mapping is not page-sized"));
1395 pte = pmap_pte(kernel_pmap, va, &lvl);
1396 KASSERT(pte != NULL, ("Invalid page table, va: 0x%lx", va));
1398 ("Invalid device pagetable level: %d != 3", lvl));
1404 pmap_invalidate_range(kernel_pmap, sva, va);
1408 * Used to map a range of physical addresses into kernel
1409 * virtual address space.
1411 * The value passed in '*virt' is a suggested virtual address for
1412 * the mapping. Architectures which can support a direct-mapped
1413 * physical to virtual region can return the appropriate address
1414 * within that region, leaving '*virt' unchanged. Other
1415 * architectures should map the pages starting at '*virt' and
1416 * update '*virt' with the first usable address after the mapped
1420 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
1422 return PHYS_TO_DMAP(start);
1427 * Add a list of wired pages to the kva
1428 * this routine is only used for temporary
1429 * kernel mappings that do not need to have
1430 * page modification or references recorded.
1431 * Note that old mappings are simply written
1432 * over. The page *must* be wired.
1433 * Note: SMP coherent. Uses a ranged shootdown IPI.
1436 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
1439 pt_entry_t *pte, pa;
1445 for (i = 0; i < count; i++) {
1446 pde = pmap_pde(kernel_pmap, va, &lvl);
1447 KASSERT(pde != NULL,
1448 ("pmap_qenter: Invalid page entry, va: 0x%lx", va));
1450 ("pmap_qenter: Invalid level %d", lvl));
1453 pa = VM_PAGE_TO_PHYS(m) | ATTR_DEFAULT |
1454 ATTR_S1_AP(ATTR_S1_AP_RW) | ATTR_S1_XN |
1455 ATTR_S1_IDX(m->md.pv_memattr) | L3_PAGE;
1456 pte = pmap_l2_to_l3(pde, va);
1457 pmap_load_store(pte, pa);
1461 pmap_invalidate_range(kernel_pmap, sva, va);
1465 * This routine tears out page mappings from the
1466 * kernel -- it is meant only for temporary mappings.
1469 pmap_qremove(vm_offset_t sva, int count)
1475 KASSERT(sva >= VM_MIN_KERNEL_ADDRESS, ("usermode va %lx", sva));
1478 while (count-- > 0) {
1479 pte = pmap_pte(kernel_pmap, va, &lvl);
1481 ("Invalid device pagetable level: %d != 3", lvl));
1488 pmap_invalidate_range(kernel_pmap, sva, va);
1491 /***************************************************
1492 * Page table page management routines.....
1493 ***************************************************/
1495 * Schedule the specified unused page table page to be freed. Specifically,
1496 * add the page to the specified list of pages that will be released to the
1497 * physical memory manager after the TLB has been updated.
1499 static __inline void
1500 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
1501 boolean_t set_PG_ZERO)
1505 m->flags |= PG_ZERO;
1507 m->flags &= ~PG_ZERO;
1508 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
1512 * Decrements a page table page's reference count, which is used to record the
1513 * number of valid page table entries within the page. If the reference count
1514 * drops to zero, then the page table page is unmapped. Returns TRUE if the
1515 * page table page was unmapped and FALSE otherwise.
1517 static inline boolean_t
1518 pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
1522 if (m->ref_count == 0) {
1523 _pmap_unwire_l3(pmap, va, m, free);
1530 _pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
1533 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1535 * unmap the page table page
1537 if (m->pindex >= (NUL2E + NUL1E)) {
1541 l0 = pmap_l0(pmap, va);
1543 } else if (m->pindex >= NUL2E) {
1547 l1 = pmap_l1(pmap, va);
1553 l2 = pmap_l2(pmap, va);
1556 pmap_resident_count_dec(pmap, 1);
1557 if (m->pindex < NUL2E) {
1558 /* We just released an l3, unhold the matching l2 */
1559 pd_entry_t *l1, tl1;
1562 l1 = pmap_l1(pmap, va);
1563 tl1 = pmap_load(l1);
1564 l2pg = PHYS_TO_VM_PAGE(tl1 & ~ATTR_MASK);
1565 pmap_unwire_l3(pmap, va, l2pg, free);
1566 } else if (m->pindex < (NUL2E + NUL1E)) {
1567 /* We just released an l2, unhold the matching l1 */
1568 pd_entry_t *l0, tl0;
1571 l0 = pmap_l0(pmap, va);
1572 tl0 = pmap_load(l0);
1573 l1pg = PHYS_TO_VM_PAGE(tl0 & ~ATTR_MASK);
1574 pmap_unwire_l3(pmap, va, l1pg, free);
1576 pmap_invalidate_page(pmap, va);
1579 * Put page on a list so that it is released after
1580 * *ALL* TLB shootdown is done
1582 pmap_add_delayed_free_list(m, free, TRUE);
1586 * After removing a page table entry, this routine is used to
1587 * conditionally free the page, and manage the reference count.
1590 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, pd_entry_t ptepde,
1591 struct spglist *free)
1595 if (va >= VM_MAXUSER_ADDRESS)
1597 KASSERT(ptepde != 0, ("pmap_unuse_pt: ptepde != 0"));
1598 mpte = PHYS_TO_VM_PAGE(ptepde & ~ATTR_MASK);
1599 return (pmap_unwire_l3(pmap, va, mpte, free));
1603 * Release a page table page reference after a failed attempt to create a
1607 pmap_abort_ptp(pmap_t pmap, vm_offset_t va, vm_page_t mpte)
1609 struct spglist free;
1612 if (pmap_unwire_l3(pmap, va, mpte, &free)) {
1614 * Although "va" was never mapped, the TLB could nonetheless
1615 * have intermediate entries that refer to the freed page
1616 * table pages. Invalidate those entries.
1618 * XXX redundant invalidation (See _pmap_unwire_l3().)
1620 pmap_invalidate_page(pmap, va);
1621 vm_page_free_pages_toq(&free, true);
1626 pmap_pinit0(pmap_t pmap)
1629 PMAP_LOCK_INIT(pmap);
1630 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats));
1631 pmap->pm_l0_paddr = READ_SPECIALREG(ttbr0_el1);
1632 pmap->pm_l0 = (pd_entry_t *)PHYS_TO_DMAP(pmap->pm_l0_paddr);
1633 pmap->pm_root.rt_root = 0;
1634 pmap->pm_cookie = COOKIE_FROM(ASID_RESERVED_FOR_PID_0, INT_MIN);
1635 pmap->pm_stage = PM_STAGE1;
1636 pmap->pm_asid_set = &asids;
1638 PCPU_SET(curpmap, pmap);
1642 pmap_pinit_stage(pmap_t pmap, enum pmap_stage stage)
1647 * allocate the l0 page
1649 while ((l0pt = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
1650 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL)
1653 pmap->pm_l0_paddr = VM_PAGE_TO_PHYS(l0pt);
1654 pmap->pm_l0 = (pd_entry_t *)PHYS_TO_DMAP(pmap->pm_l0_paddr);
1656 if ((l0pt->flags & PG_ZERO) == 0)
1657 pagezero(pmap->pm_l0);
1659 pmap->pm_root.rt_root = 0;
1660 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats));
1661 pmap->pm_cookie = COOKIE_FROM(-1, INT_MAX);
1663 pmap->pm_stage = stage;
1666 pmap->pm_asid_set = &asids;
1669 pmap->pm_asid_set = &vmids;
1672 panic("%s: Invalid pmap type %d", __func__, stage);
1676 /* XXX Temporarily disable deferred ASID allocation. */
1677 pmap_alloc_asid(pmap);
1683 pmap_pinit(pmap_t pmap)
1686 return (pmap_pinit_stage(pmap, PM_STAGE1));
1690 * This routine is called if the desired page table page does not exist.
1692 * If page table page allocation fails, this routine may sleep before
1693 * returning NULL. It sleeps only if a lock pointer was given.
1695 * Note: If a page allocation fails at page table level two or three,
1696 * one or two pages may be held during the wait, only to be released
1697 * afterwards. This conservative approach is easily argued to avoid
1701 _pmap_alloc_l3(pmap_t pmap, vm_pindex_t ptepindex, struct rwlock **lockp)
1703 vm_page_t m, l1pg, l2pg;
1705 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1708 * Allocate a page table page.
1710 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
1711 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
1712 if (lockp != NULL) {
1713 RELEASE_PV_LIST_LOCK(lockp);
1720 * Indicate the need to retry. While waiting, the page table
1721 * page may have been allocated.
1725 if ((m->flags & PG_ZERO) == 0)
1729 * Because of AArch64's weak memory consistency model, we must have a
1730 * barrier here to ensure that the stores for zeroing "m", whether by
1731 * pmap_zero_page() or an earlier function, are visible before adding
1732 * "m" to the page table. Otherwise, a page table walk by another
1733 * processor's MMU could see the mapping to "m" and a stale, non-zero
1739 * Map the pagetable page into the process address space, if
1740 * it isn't already there.
1743 if (ptepindex >= (NUL2E + NUL1E)) {
1745 vm_pindex_t l0index;
1747 l0index = ptepindex - (NUL2E + NUL1E);
1748 l0 = &pmap->pm_l0[l0index];
1749 pmap_store(l0, VM_PAGE_TO_PHYS(m) | L0_TABLE);
1750 } else if (ptepindex >= NUL2E) {
1751 vm_pindex_t l0index, l1index;
1752 pd_entry_t *l0, *l1;
1755 l1index = ptepindex - NUL2E;
1756 l0index = l1index >> L0_ENTRIES_SHIFT;
1758 l0 = &pmap->pm_l0[l0index];
1759 tl0 = pmap_load(l0);
1761 /* recurse for allocating page dir */
1762 if (_pmap_alloc_l3(pmap, NUL2E + NUL1E + l0index,
1764 vm_page_unwire_noq(m);
1765 vm_page_free_zero(m);
1769 l1pg = PHYS_TO_VM_PAGE(tl0 & ~ATTR_MASK);
1773 l1 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l0) & ~ATTR_MASK);
1774 l1 = &l1[ptepindex & Ln_ADDR_MASK];
1775 pmap_store(l1, VM_PAGE_TO_PHYS(m) | L1_TABLE);
1777 vm_pindex_t l0index, l1index;
1778 pd_entry_t *l0, *l1, *l2;
1779 pd_entry_t tl0, tl1;
1781 l1index = ptepindex >> Ln_ENTRIES_SHIFT;
1782 l0index = l1index >> L0_ENTRIES_SHIFT;
1784 l0 = &pmap->pm_l0[l0index];
1785 tl0 = pmap_load(l0);
1787 /* recurse for allocating page dir */
1788 if (_pmap_alloc_l3(pmap, NUL2E + l1index,
1790 vm_page_unwire_noq(m);
1791 vm_page_free_zero(m);
1794 tl0 = pmap_load(l0);
1795 l1 = (pd_entry_t *)PHYS_TO_DMAP(tl0 & ~ATTR_MASK);
1796 l1 = &l1[l1index & Ln_ADDR_MASK];
1798 l1 = (pd_entry_t *)PHYS_TO_DMAP(tl0 & ~ATTR_MASK);
1799 l1 = &l1[l1index & Ln_ADDR_MASK];
1800 tl1 = pmap_load(l1);
1802 /* recurse for allocating page dir */
1803 if (_pmap_alloc_l3(pmap, NUL2E + l1index,
1805 vm_page_unwire_noq(m);
1806 vm_page_free_zero(m);
1810 l2pg = PHYS_TO_VM_PAGE(tl1 & ~ATTR_MASK);
1815 l2 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l1) & ~ATTR_MASK);
1816 l2 = &l2[ptepindex & Ln_ADDR_MASK];
1817 pmap_store(l2, VM_PAGE_TO_PHYS(m) | L2_TABLE);
1820 pmap_resident_count_inc(pmap, 1);
1826 pmap_alloc_l2(pmap_t pmap, vm_offset_t va, vm_page_t *l2pgp,
1827 struct rwlock **lockp)
1829 pd_entry_t *l1, *l2;
1831 vm_pindex_t l2pindex;
1834 l1 = pmap_l1(pmap, va);
1835 if (l1 != NULL && (pmap_load(l1) & ATTR_DESCR_MASK) == L1_TABLE) {
1836 l2 = pmap_l1_to_l2(l1, va);
1837 if (va < VM_MAXUSER_ADDRESS) {
1838 /* Add a reference to the L2 page. */
1839 l2pg = PHYS_TO_VM_PAGE(pmap_load(l1) & ~ATTR_MASK);
1843 } else if (va < VM_MAXUSER_ADDRESS) {
1844 /* Allocate a L2 page. */
1845 l2pindex = pmap_l2_pindex(va) >> Ln_ENTRIES_SHIFT;
1846 l2pg = _pmap_alloc_l3(pmap, NUL2E + l2pindex, lockp);
1853 l2 = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(l2pg));
1854 l2 = &l2[pmap_l2_index(va)];
1856 panic("pmap_alloc_l2: missing page table page for va %#lx",
1863 pmap_alloc_l3(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
1865 vm_pindex_t ptepindex;
1866 pd_entry_t *pde, tpde;
1874 * Calculate pagetable page index
1876 ptepindex = pmap_l2_pindex(va);
1879 * Get the page directory entry
1881 pde = pmap_pde(pmap, va, &lvl);
1884 * If the page table page is mapped, we just increment the hold count,
1885 * and activate it. If we get a level 2 pde it will point to a level 3
1893 pte = pmap_l0_to_l1(pde, va);
1894 KASSERT(pmap_load(pte) == 0,
1895 ("pmap_alloc_l3: TODO: l0 superpages"));
1900 pte = pmap_l1_to_l2(pde, va);
1901 KASSERT(pmap_load(pte) == 0,
1902 ("pmap_alloc_l3: TODO: l1 superpages"));
1906 tpde = pmap_load(pde);
1908 m = PHYS_TO_VM_PAGE(tpde & ~ATTR_MASK);
1914 panic("pmap_alloc_l3: Invalid level %d", lvl);
1918 * Here if the pte page isn't mapped, or if it has been deallocated.
1920 m = _pmap_alloc_l3(pmap, ptepindex, lockp);
1921 if (m == NULL && lockp != NULL)
1927 /***************************************************
1928 * Pmap allocation/deallocation routines.
1929 ***************************************************/
1932 * Release any resources held by the given physical map.
1933 * Called when a pmap initialized by pmap_pinit is being released.
1934 * Should only be called if the map contains no valid mappings.
1937 pmap_release(pmap_t pmap)
1939 struct asid_set *set;
1943 KASSERT(pmap->pm_stats.resident_count == 0,
1944 ("pmap_release: pmap resident count %ld != 0",
1945 pmap->pm_stats.resident_count));
1946 KASSERT(vm_radix_is_empty(&pmap->pm_root),
1947 ("pmap_release: pmap has reserved page table page(s)"));
1949 set = pmap->pm_asid_set;
1950 KASSERT(set != NULL, ("%s: NULL asid set", __func__));
1953 * Allow the ASID to be reused. In stage 2 VMIDs we don't invalidate
1954 * the entries when removing them so rely on a later tlb invalidation.
1955 * this will happen when updating the VMID generation. Because of this
1956 * we don't reuse VMIDs within a generation.
1958 if (pmap->pm_stage == PM_STAGE1) {
1959 mtx_lock_spin(&set->asid_set_mutex);
1960 if (COOKIE_TO_EPOCH(pmap->pm_cookie) == set->asid_epoch) {
1961 asid = COOKIE_TO_ASID(pmap->pm_cookie);
1962 KASSERT(asid >= ASID_FIRST_AVAILABLE &&
1963 asid < set->asid_set_size,
1964 ("pmap_release: pmap cookie has out-of-range asid"));
1965 bit_clear(set->asid_set, asid);
1967 mtx_unlock_spin(&set->asid_set_mutex);
1970 m = PHYS_TO_VM_PAGE(pmap->pm_l0_paddr);
1971 vm_page_unwire_noq(m);
1972 vm_page_free_zero(m);
1976 kvm_size(SYSCTL_HANDLER_ARGS)
1978 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS;
1980 return sysctl_handle_long(oidp, &ksize, 0, req);
1982 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG | CTLFLAG_RD | CTLFLAG_MPSAFE,
1983 0, 0, kvm_size, "LU",
1987 kvm_free(SYSCTL_HANDLER_ARGS)
1989 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
1991 return sysctl_handle_long(oidp, &kfree, 0, req);
1993 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG | CTLFLAG_RD | CTLFLAG_MPSAFE,
1994 0, 0, kvm_free, "LU",
1995 "Amount of KVM free");
1998 * grow the number of kernel page table entries, if needed
2001 pmap_growkernel(vm_offset_t addr)
2005 pd_entry_t *l0, *l1, *l2;
2007 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
2009 addr = roundup2(addr, L2_SIZE);
2010 if (addr - 1 >= vm_map_max(kernel_map))
2011 addr = vm_map_max(kernel_map);
2012 while (kernel_vm_end < addr) {
2013 l0 = pmap_l0(kernel_pmap, kernel_vm_end);
2014 KASSERT(pmap_load(l0) != 0,
2015 ("pmap_growkernel: No level 0 kernel entry"));
2017 l1 = pmap_l0_to_l1(l0, kernel_vm_end);
2018 if (pmap_load(l1) == 0) {
2019 /* We need a new PDP entry */
2020 nkpg = vm_page_alloc(NULL, kernel_vm_end >> L1_SHIFT,
2021 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ |
2022 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
2024 panic("pmap_growkernel: no memory to grow kernel");
2025 if ((nkpg->flags & PG_ZERO) == 0)
2026 pmap_zero_page(nkpg);
2027 /* See the dmb() in _pmap_alloc_l3(). */
2029 paddr = VM_PAGE_TO_PHYS(nkpg);
2030 pmap_store(l1, paddr | L1_TABLE);
2031 continue; /* try again */
2033 l2 = pmap_l1_to_l2(l1, kernel_vm_end);
2034 if (pmap_load(l2) != 0) {
2035 kernel_vm_end = (kernel_vm_end + L2_SIZE) & ~L2_OFFSET;
2036 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
2037 kernel_vm_end = vm_map_max(kernel_map);
2043 nkpg = vm_page_alloc(NULL, kernel_vm_end >> L2_SHIFT,
2044 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
2047 panic("pmap_growkernel: no memory to grow kernel");
2048 if ((nkpg->flags & PG_ZERO) == 0)
2049 pmap_zero_page(nkpg);
2050 /* See the dmb() in _pmap_alloc_l3(). */
2052 paddr = VM_PAGE_TO_PHYS(nkpg);
2053 pmap_store(l2, paddr | L2_TABLE);
2055 kernel_vm_end = (kernel_vm_end + L2_SIZE) & ~L2_OFFSET;
2056 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
2057 kernel_vm_end = vm_map_max(kernel_map);
2064 /***************************************************
2065 * page management routines.
2066 ***************************************************/
2068 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
2069 CTASSERT(_NPCM == 3);
2070 CTASSERT(_NPCPV == 168);
2072 static __inline struct pv_chunk *
2073 pv_to_chunk(pv_entry_t pv)
2076 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
2079 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
2081 #define PC_FREE0 0xfffffffffffffffful
2082 #define PC_FREE1 0xfffffffffffffffful
2083 #define PC_FREE2 0x000000fffffffffful
2085 static const uint64_t pc_freemask[_NPCM] = { PC_FREE0, PC_FREE1, PC_FREE2 };
2089 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
2091 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
2092 "Current number of pv entry chunks");
2093 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
2094 "Current number of pv entry chunks allocated");
2095 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
2096 "Current number of pv entry chunks frees");
2097 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
2098 "Number of times tried to get a chunk page but failed.");
2100 static long pv_entry_frees, pv_entry_allocs, pv_entry_count;
2101 static int pv_entry_spare;
2103 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
2104 "Current number of pv entry frees");
2105 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
2106 "Current number of pv entry allocs");
2107 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
2108 "Current number of pv entries");
2109 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
2110 "Current number of spare pv entries");
2115 * We are in a serious low memory condition. Resort to
2116 * drastic measures to free some pages so we can allocate
2117 * another pv entry chunk.
2119 * Returns NULL if PV entries were reclaimed from the specified pmap.
2121 * We do not, however, unmap 2mpages because subsequent accesses will
2122 * allocate per-page pv entries until repromotion occurs, thereby
2123 * exacerbating the shortage of free pv entries.
2126 reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp)
2128 struct pv_chunk *pc, *pc_marker, *pc_marker_end;
2129 struct pv_chunk_header pc_marker_b, pc_marker_end_b;
2130 struct md_page *pvh;
2132 pmap_t next_pmap, pmap;
2133 pt_entry_t *pte, tpte;
2137 struct spglist free;
2139 int bit, field, freed, lvl;
2140 static int active_reclaims = 0;
2142 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
2143 KASSERT(lockp != NULL, ("reclaim_pv_chunk: lockp is NULL"));
2148 bzero(&pc_marker_b, sizeof(pc_marker_b));
2149 bzero(&pc_marker_end_b, sizeof(pc_marker_end_b));
2150 pc_marker = (struct pv_chunk *)&pc_marker_b;
2151 pc_marker_end = (struct pv_chunk *)&pc_marker_end_b;
2153 mtx_lock(&pv_chunks_mutex);
2155 TAILQ_INSERT_HEAD(&pv_chunks, pc_marker, pc_lru);
2156 TAILQ_INSERT_TAIL(&pv_chunks, pc_marker_end, pc_lru);
2157 while ((pc = TAILQ_NEXT(pc_marker, pc_lru)) != pc_marker_end &&
2158 SLIST_EMPTY(&free)) {
2159 next_pmap = pc->pc_pmap;
2160 if (next_pmap == NULL) {
2162 * The next chunk is a marker. However, it is
2163 * not our marker, so active_reclaims must be
2164 * > 1. Consequently, the next_chunk code
2165 * will not rotate the pv_chunks list.
2169 mtx_unlock(&pv_chunks_mutex);
2172 * A pv_chunk can only be removed from the pc_lru list
2173 * when both pv_chunks_mutex is owned and the
2174 * corresponding pmap is locked.
2176 if (pmap != next_pmap) {
2177 if (pmap != NULL && pmap != locked_pmap)
2180 /* Avoid deadlock and lock recursion. */
2181 if (pmap > locked_pmap) {
2182 RELEASE_PV_LIST_LOCK(lockp);
2184 mtx_lock(&pv_chunks_mutex);
2186 } else if (pmap != locked_pmap) {
2187 if (PMAP_TRYLOCK(pmap)) {
2188 mtx_lock(&pv_chunks_mutex);
2191 pmap = NULL; /* pmap is not locked */
2192 mtx_lock(&pv_chunks_mutex);
2193 pc = TAILQ_NEXT(pc_marker, pc_lru);
2195 pc->pc_pmap != next_pmap)
2203 * Destroy every non-wired, 4 KB page mapping in the chunk.
2206 for (field = 0; field < _NPCM; field++) {
2207 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
2208 inuse != 0; inuse &= ~(1UL << bit)) {
2209 bit = ffsl(inuse) - 1;
2210 pv = &pc->pc_pventry[field * 64 + bit];
2212 pde = pmap_pde(pmap, va, &lvl);
2215 pte = pmap_l2_to_l3(pde, va);
2216 tpte = pmap_load(pte);
2217 if ((tpte & ATTR_SW_WIRED) != 0)
2219 tpte = pmap_load_clear(pte);
2220 m = PHYS_TO_VM_PAGE(tpte & ~ATTR_MASK);
2221 if (pmap_pte_dirty(pmap, tpte))
2223 if ((tpte & ATTR_AF) != 0) {
2224 pmap_invalidate_page(pmap, va);
2225 vm_page_aflag_set(m, PGA_REFERENCED);
2227 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
2228 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
2230 if (TAILQ_EMPTY(&m->md.pv_list) &&
2231 (m->flags & PG_FICTITIOUS) == 0) {
2232 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2233 if (TAILQ_EMPTY(&pvh->pv_list)) {
2234 vm_page_aflag_clear(m,
2238 pc->pc_map[field] |= 1UL << bit;
2239 pmap_unuse_pt(pmap, va, pmap_load(pde), &free);
2244 mtx_lock(&pv_chunks_mutex);
2247 /* Every freed mapping is for a 4 KB page. */
2248 pmap_resident_count_dec(pmap, freed);
2249 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
2250 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
2251 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
2252 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2253 if (pc->pc_map[0] == PC_FREE0 && pc->pc_map[1] == PC_FREE1 &&
2254 pc->pc_map[2] == PC_FREE2) {
2255 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
2256 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
2257 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
2258 /* Entire chunk is free; return it. */
2259 m_pc = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
2260 dump_drop_page(m_pc->phys_addr);
2261 mtx_lock(&pv_chunks_mutex);
2262 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2265 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2266 mtx_lock(&pv_chunks_mutex);
2267 /* One freed pv entry in locked_pmap is sufficient. */
2268 if (pmap == locked_pmap)
2272 TAILQ_REMOVE(&pv_chunks, pc_marker, pc_lru);
2273 TAILQ_INSERT_AFTER(&pv_chunks, pc, pc_marker, pc_lru);
2274 if (active_reclaims == 1 && pmap != NULL) {
2276 * Rotate the pv chunks list so that we do not
2277 * scan the same pv chunks that could not be
2278 * freed (because they contained a wired
2279 * and/or superpage mapping) on every
2280 * invocation of reclaim_pv_chunk().
2282 while ((pc = TAILQ_FIRST(&pv_chunks)) != pc_marker) {
2283 MPASS(pc->pc_pmap != NULL);
2284 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2285 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
2289 TAILQ_REMOVE(&pv_chunks, pc_marker, pc_lru);
2290 TAILQ_REMOVE(&pv_chunks, pc_marker_end, pc_lru);
2292 mtx_unlock(&pv_chunks_mutex);
2293 if (pmap != NULL && pmap != locked_pmap)
2295 if (m_pc == NULL && !SLIST_EMPTY(&free)) {
2296 m_pc = SLIST_FIRST(&free);
2297 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
2298 /* Recycle a freed page table page. */
2299 m_pc->ref_count = 1;
2301 vm_page_free_pages_toq(&free, true);
2306 * free the pv_entry back to the free list
2309 free_pv_entry(pmap_t pmap, pv_entry_t pv)
2311 struct pv_chunk *pc;
2312 int idx, field, bit;
2314 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2315 PV_STAT(atomic_add_long(&pv_entry_frees, 1));
2316 PV_STAT(atomic_add_int(&pv_entry_spare, 1));
2317 PV_STAT(atomic_subtract_long(&pv_entry_count, 1));
2318 pc = pv_to_chunk(pv);
2319 idx = pv - &pc->pc_pventry[0];
2322 pc->pc_map[field] |= 1ul << bit;
2323 if (pc->pc_map[0] != PC_FREE0 || pc->pc_map[1] != PC_FREE1 ||
2324 pc->pc_map[2] != PC_FREE2) {
2325 /* 98% of the time, pc is already at the head of the list. */
2326 if (__predict_false(pc != TAILQ_FIRST(&pmap->pm_pvchunk))) {
2327 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2328 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2332 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2337 free_pv_chunk(struct pv_chunk *pc)
2341 mtx_lock(&pv_chunks_mutex);
2342 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2343 mtx_unlock(&pv_chunks_mutex);
2344 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
2345 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
2346 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
2347 /* entire chunk is free, return it */
2348 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
2349 dump_drop_page(m->phys_addr);
2350 vm_page_unwire_noq(m);
2355 * Returns a new PV entry, allocating a new PV chunk from the system when
2356 * needed. If this PV chunk allocation fails and a PV list lock pointer was
2357 * given, a PV chunk is reclaimed from an arbitrary pmap. Otherwise, NULL is
2360 * The given PV list lock may be released.
2363 get_pv_entry(pmap_t pmap, struct rwlock **lockp)
2367 struct pv_chunk *pc;
2370 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2371 PV_STAT(atomic_add_long(&pv_entry_allocs, 1));
2373 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2375 for (field = 0; field < _NPCM; field++) {
2376 if (pc->pc_map[field]) {
2377 bit = ffsl(pc->pc_map[field]) - 1;
2381 if (field < _NPCM) {
2382 pv = &pc->pc_pventry[field * 64 + bit];
2383 pc->pc_map[field] &= ~(1ul << bit);
2384 /* If this was the last item, move it to tail */
2385 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 &&
2386 pc->pc_map[2] == 0) {
2387 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2388 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc,
2391 PV_STAT(atomic_add_long(&pv_entry_count, 1));
2392 PV_STAT(atomic_subtract_int(&pv_entry_spare, 1));
2396 /* No free items, allocate another chunk */
2397 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
2400 if (lockp == NULL) {
2401 PV_STAT(pc_chunk_tryfail++);
2404 m = reclaim_pv_chunk(pmap, lockp);
2408 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
2409 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
2410 dump_add_page(m->phys_addr);
2411 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
2413 pc->pc_map[0] = PC_FREE0 & ~1ul; /* preallocated bit 0 */
2414 pc->pc_map[1] = PC_FREE1;
2415 pc->pc_map[2] = PC_FREE2;
2416 mtx_lock(&pv_chunks_mutex);
2417 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
2418 mtx_unlock(&pv_chunks_mutex);
2419 pv = &pc->pc_pventry[0];
2420 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2421 PV_STAT(atomic_add_long(&pv_entry_count, 1));
2422 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV - 1));
2427 * Ensure that the number of spare PV entries in the specified pmap meets or
2428 * exceeds the given count, "needed".
2430 * The given PV list lock may be released.
2433 reserve_pv_entries(pmap_t pmap, int needed, struct rwlock **lockp)
2435 struct pch new_tail;
2436 struct pv_chunk *pc;
2441 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2442 KASSERT(lockp != NULL, ("reserve_pv_entries: lockp is NULL"));
2445 * Newly allocated PV chunks must be stored in a private list until
2446 * the required number of PV chunks have been allocated. Otherwise,
2447 * reclaim_pv_chunk() could recycle one of these chunks. In
2448 * contrast, these chunks must be added to the pmap upon allocation.
2450 TAILQ_INIT(&new_tail);
2453 TAILQ_FOREACH(pc, &pmap->pm_pvchunk, pc_list) {
2454 bit_count((bitstr_t *)pc->pc_map, 0,
2455 sizeof(pc->pc_map) * NBBY, &free);
2459 if (avail >= needed)
2462 for (reclaimed = false; avail < needed; avail += _NPCPV) {
2463 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
2466 m = reclaim_pv_chunk(pmap, lockp);
2471 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
2472 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
2473 dump_add_page(m->phys_addr);
2474 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
2476 pc->pc_map[0] = PC_FREE0;
2477 pc->pc_map[1] = PC_FREE1;
2478 pc->pc_map[2] = PC_FREE2;
2479 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2480 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
2481 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV));
2484 * The reclaim might have freed a chunk from the current pmap.
2485 * If that chunk contained available entries, we need to
2486 * re-count the number of available entries.
2491 if (!TAILQ_EMPTY(&new_tail)) {
2492 mtx_lock(&pv_chunks_mutex);
2493 TAILQ_CONCAT(&pv_chunks, &new_tail, pc_lru);
2494 mtx_unlock(&pv_chunks_mutex);
2499 * First find and then remove the pv entry for the specified pmap and virtual
2500 * address from the specified pv list. Returns the pv entry if found and NULL
2501 * otherwise. This operation can be performed on pv lists for either 4KB or
2502 * 2MB page mappings.
2504 static __inline pv_entry_t
2505 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2509 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
2510 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
2511 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
2520 * After demotion from a 2MB page mapping to 512 4KB page mappings,
2521 * destroy the pv entry for the 2MB page mapping and reinstantiate the pv
2522 * entries for each of the 4KB page mappings.
2525 pmap_pv_demote_l2(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
2526 struct rwlock **lockp)
2528 struct md_page *pvh;
2529 struct pv_chunk *pc;
2531 vm_offset_t va_last;
2535 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2536 KASSERT((va & L2_OFFSET) == 0,
2537 ("pmap_pv_demote_l2: va is not 2mpage aligned"));
2538 KASSERT((pa & L2_OFFSET) == 0,
2539 ("pmap_pv_demote_l2: pa is not 2mpage aligned"));
2540 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
2543 * Transfer the 2mpage's pv entry for this mapping to the first
2544 * page's pv list. Once this transfer begins, the pv list lock
2545 * must not be released until the last pv entry is reinstantiated.
2547 pvh = pa_to_pvh(pa);
2548 pv = pmap_pvh_remove(pvh, pmap, va);
2549 KASSERT(pv != NULL, ("pmap_pv_demote_l2: pv not found"));
2550 m = PHYS_TO_VM_PAGE(pa);
2551 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2553 /* Instantiate the remaining Ln_ENTRIES - 1 pv entries. */
2554 PV_STAT(atomic_add_long(&pv_entry_allocs, Ln_ENTRIES - 1));
2555 va_last = va + L2_SIZE - PAGE_SIZE;
2557 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2558 KASSERT(pc->pc_map[0] != 0 || pc->pc_map[1] != 0 ||
2559 pc->pc_map[2] != 0, ("pmap_pv_demote_l2: missing spare"));
2560 for (field = 0; field < _NPCM; field++) {
2561 while (pc->pc_map[field]) {
2562 bit = ffsl(pc->pc_map[field]) - 1;
2563 pc->pc_map[field] &= ~(1ul << bit);
2564 pv = &pc->pc_pventry[field * 64 + bit];
2568 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2569 ("pmap_pv_demote_l2: page %p is not managed", m));
2570 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2576 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2577 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2580 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 && pc->pc_map[2] == 0) {
2581 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2582 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2584 PV_STAT(atomic_add_long(&pv_entry_count, Ln_ENTRIES - 1));
2585 PV_STAT(atomic_subtract_int(&pv_entry_spare, Ln_ENTRIES - 1));
2589 * First find and then destroy the pv entry for the specified pmap and virtual
2590 * address. This operation can be performed on pv lists for either 4KB or 2MB
2594 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2598 pv = pmap_pvh_remove(pvh, pmap, va);
2599 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
2600 free_pv_entry(pmap, pv);
2604 * Conditionally create the PV entry for a 4KB page mapping if the required
2605 * memory can be allocated without resorting to reclamation.
2608 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m,
2609 struct rwlock **lockp)
2613 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2614 /* Pass NULL instead of the lock pointer to disable reclamation. */
2615 if ((pv = get_pv_entry(pmap, NULL)) != NULL) {
2617 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
2618 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2626 * Create the PV entry for a 2MB page mapping. Always returns true unless the
2627 * flag PMAP_ENTER_NORECLAIM is specified. If that flag is specified, returns
2628 * false if the PV entry cannot be allocated without resorting to reclamation.
2631 pmap_pv_insert_l2(pmap_t pmap, vm_offset_t va, pd_entry_t l2e, u_int flags,
2632 struct rwlock **lockp)
2634 struct md_page *pvh;
2638 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2639 /* Pass NULL instead of the lock pointer to disable reclamation. */
2640 if ((pv = get_pv_entry(pmap, (flags & PMAP_ENTER_NORECLAIM) != 0 ?
2641 NULL : lockp)) == NULL)
2644 pa = l2e & ~ATTR_MASK;
2645 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
2646 pvh = pa_to_pvh(pa);
2647 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2653 pmap_remove_kernel_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t va)
2655 pt_entry_t newl2, oldl2;
2659 KASSERT(!VIRT_IN_DMAP(va), ("removing direct mapping of %#lx", va));
2660 KASSERT(pmap == kernel_pmap, ("pmap %p is not kernel_pmap", pmap));
2661 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2663 ml3 = pmap_remove_pt_page(pmap, va);
2665 panic("pmap_remove_kernel_l2: Missing pt page");
2667 ml3pa = VM_PAGE_TO_PHYS(ml3);
2668 newl2 = ml3pa | L2_TABLE;
2671 * If this page table page was unmapped by a promotion, then it
2672 * contains valid mappings. Zero it to invalidate those mappings.
2674 if (ml3->valid != 0)
2675 pagezero((void *)PHYS_TO_DMAP(ml3pa));
2678 * Demote the mapping. The caller must have already invalidated the
2679 * mapping (i.e., the "break" in break-before-make).
2681 oldl2 = pmap_load_store(l2, newl2);
2682 KASSERT(oldl2 == 0, ("%s: found existing mapping at %p: %#lx",
2683 __func__, l2, oldl2));
2687 * pmap_remove_l2: Do the things to unmap a level 2 superpage.
2690 pmap_remove_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t sva,
2691 pd_entry_t l1e, struct spglist *free, struct rwlock **lockp)
2693 struct md_page *pvh;
2695 vm_offset_t eva, va;
2698 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2699 KASSERT((sva & L2_OFFSET) == 0, ("pmap_remove_l2: sva is not aligned"));
2700 old_l2 = pmap_load_clear(l2);
2701 KASSERT((old_l2 & ATTR_DESCR_MASK) == L2_BLOCK,
2702 ("pmap_remove_l2: L2e %lx is not a block mapping", old_l2));
2705 * Since a promotion must break the 4KB page mappings before making
2706 * the 2MB page mapping, a pmap_invalidate_page() suffices.
2708 pmap_invalidate_page(pmap, sva);
2710 if (old_l2 & ATTR_SW_WIRED)
2711 pmap->pm_stats.wired_count -= L2_SIZE / PAGE_SIZE;
2712 pmap_resident_count_dec(pmap, L2_SIZE / PAGE_SIZE);
2713 if (old_l2 & ATTR_SW_MANAGED) {
2714 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, old_l2 & ~ATTR_MASK);
2715 pvh = pa_to_pvh(old_l2 & ~ATTR_MASK);
2716 pmap_pvh_free(pvh, pmap, sva);
2717 eva = sva + L2_SIZE;
2718 for (va = sva, m = PHYS_TO_VM_PAGE(old_l2 & ~ATTR_MASK);
2719 va < eva; va += PAGE_SIZE, m++) {
2720 if (pmap_pte_dirty(pmap, old_l2))
2722 if (old_l2 & ATTR_AF)
2723 vm_page_aflag_set(m, PGA_REFERENCED);
2724 if (TAILQ_EMPTY(&m->md.pv_list) &&
2725 TAILQ_EMPTY(&pvh->pv_list))
2726 vm_page_aflag_clear(m, PGA_WRITEABLE);
2729 if (pmap == kernel_pmap) {
2730 pmap_remove_kernel_l2(pmap, l2, sva);
2732 ml3 = pmap_remove_pt_page(pmap, sva);
2734 KASSERT(ml3->valid == VM_PAGE_BITS_ALL,
2735 ("pmap_remove_l2: l3 page not promoted"));
2736 pmap_resident_count_dec(pmap, 1);
2737 KASSERT(ml3->ref_count == NL3PG,
2738 ("pmap_remove_l2: l3 page ref count error"));
2740 pmap_add_delayed_free_list(ml3, free, FALSE);
2743 return (pmap_unuse_pt(pmap, sva, l1e, free));
2747 * pmap_remove_l3: do the things to unmap a page in a process
2750 pmap_remove_l3(pmap_t pmap, pt_entry_t *l3, vm_offset_t va,
2751 pd_entry_t l2e, struct spglist *free, struct rwlock **lockp)
2753 struct md_page *pvh;
2757 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2758 old_l3 = pmap_load_clear(l3);
2759 pmap_invalidate_page(pmap, va);
2760 if (old_l3 & ATTR_SW_WIRED)
2761 pmap->pm_stats.wired_count -= 1;
2762 pmap_resident_count_dec(pmap, 1);
2763 if (old_l3 & ATTR_SW_MANAGED) {
2764 m = PHYS_TO_VM_PAGE(old_l3 & ~ATTR_MASK);
2765 if (pmap_pte_dirty(pmap, old_l3))
2767 if (old_l3 & ATTR_AF)
2768 vm_page_aflag_set(m, PGA_REFERENCED);
2769 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
2770 pmap_pvh_free(&m->md, pmap, va);
2771 if (TAILQ_EMPTY(&m->md.pv_list) &&
2772 (m->flags & PG_FICTITIOUS) == 0) {
2773 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2774 if (TAILQ_EMPTY(&pvh->pv_list))
2775 vm_page_aflag_clear(m, PGA_WRITEABLE);
2778 return (pmap_unuse_pt(pmap, va, l2e, free));
2782 * Remove the specified range of addresses from the L3 page table that is
2783 * identified by the given L2 entry.
2786 pmap_remove_l3_range(pmap_t pmap, pd_entry_t l2e, vm_offset_t sva,
2787 vm_offset_t eva, struct spglist *free, struct rwlock **lockp)
2789 struct md_page *pvh;
2790 struct rwlock *new_lock;
2791 pt_entry_t *l3, old_l3;
2795 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2796 KASSERT(rounddown2(sva, L2_SIZE) + L2_SIZE == roundup2(eva, L2_SIZE),
2797 ("pmap_remove_l3_range: range crosses an L3 page table boundary"));
2798 l3pg = sva < VM_MAXUSER_ADDRESS ? PHYS_TO_VM_PAGE(l2e & ~ATTR_MASK) :
2801 for (l3 = pmap_l2_to_l3(&l2e, sva); sva != eva; l3++, sva += L3_SIZE) {
2802 if (!pmap_l3_valid(pmap_load(l3))) {
2804 pmap_invalidate_range(pmap, va, sva);
2809 old_l3 = pmap_load_clear(l3);
2810 if ((old_l3 & ATTR_SW_WIRED) != 0)
2811 pmap->pm_stats.wired_count--;
2812 pmap_resident_count_dec(pmap, 1);
2813 if ((old_l3 & ATTR_SW_MANAGED) != 0) {
2814 m = PHYS_TO_VM_PAGE(old_l3 & ~ATTR_MASK);
2815 if (pmap_pte_dirty(pmap, old_l3))
2817 if ((old_l3 & ATTR_AF) != 0)
2818 vm_page_aflag_set(m, PGA_REFERENCED);
2819 new_lock = PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m));
2820 if (new_lock != *lockp) {
2821 if (*lockp != NULL) {
2823 * Pending TLB invalidations must be
2824 * performed before the PV list lock is
2825 * released. Otherwise, a concurrent
2826 * pmap_remove_all() on a physical page
2827 * could return while a stale TLB entry
2828 * still provides access to that page.
2831 pmap_invalidate_range(pmap, va,
2840 pmap_pvh_free(&m->md, pmap, sva);
2841 if (TAILQ_EMPTY(&m->md.pv_list) &&
2842 (m->flags & PG_FICTITIOUS) == 0) {
2843 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2844 if (TAILQ_EMPTY(&pvh->pv_list))
2845 vm_page_aflag_clear(m, PGA_WRITEABLE);
2850 if (l3pg != NULL && pmap_unwire_l3(pmap, sva, l3pg, free)) {
2856 pmap_invalidate_range(pmap, va, sva);
2860 * Remove the given range of addresses from the specified map.
2862 * It is assumed that the start and end are properly
2863 * rounded to the page size.
2866 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2868 struct rwlock *lock;
2869 vm_offset_t va_next;
2870 pd_entry_t *l0, *l1, *l2;
2871 pt_entry_t l3_paddr;
2872 struct spglist free;
2875 * Perform an unsynchronized read. This is, however, safe.
2877 if (pmap->pm_stats.resident_count == 0)
2885 for (; sva < eva; sva = va_next) {
2887 if (pmap->pm_stats.resident_count == 0)
2890 l0 = pmap_l0(pmap, sva);
2891 if (pmap_load(l0) == 0) {
2892 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
2898 l1 = pmap_l0_to_l1(l0, sva);
2899 if (pmap_load(l1) == 0) {
2900 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
2907 * Calculate index for next page table.
2909 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
2913 l2 = pmap_l1_to_l2(l1, sva);
2917 l3_paddr = pmap_load(l2);
2919 if ((l3_paddr & ATTR_DESCR_MASK) == L2_BLOCK) {
2920 if (sva + L2_SIZE == va_next && eva >= va_next) {
2921 pmap_remove_l2(pmap, l2, sva, pmap_load(l1),
2924 } else if (pmap_demote_l2_locked(pmap, l2, sva,
2927 l3_paddr = pmap_load(l2);
2931 * Weed out invalid mappings.
2933 if ((l3_paddr & ATTR_DESCR_MASK) != L2_TABLE)
2937 * Limit our scan to either the end of the va represented
2938 * by the current page table page, or to the end of the
2939 * range being removed.
2944 pmap_remove_l3_range(pmap, l3_paddr, sva, va_next, &free,
2950 vm_page_free_pages_toq(&free, true);
2954 * Routine: pmap_remove_all
2956 * Removes this physical page from
2957 * all physical maps in which it resides.
2958 * Reflects back modify bits to the pager.
2961 * Original versions of this routine were very
2962 * inefficient because they iteratively called
2963 * pmap_remove (slow...)
2967 pmap_remove_all(vm_page_t m)
2969 struct md_page *pvh;
2972 struct rwlock *lock;
2973 pd_entry_t *pde, tpde;
2974 pt_entry_t *pte, tpte;
2976 struct spglist free;
2977 int lvl, pvh_gen, md_gen;
2979 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2980 ("pmap_remove_all: page %p is not managed", m));
2982 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
2983 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
2984 pa_to_pvh(VM_PAGE_TO_PHYS(m));
2987 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
2989 if (!PMAP_TRYLOCK(pmap)) {
2990 pvh_gen = pvh->pv_gen;
2994 if (pvh_gen != pvh->pv_gen) {
3001 pte = pmap_pte(pmap, va, &lvl);
3002 KASSERT(pte != NULL,
3003 ("pmap_remove_all: no page table entry found"));
3005 ("pmap_remove_all: invalid pte level %d", lvl));
3007 pmap_demote_l2_locked(pmap, pte, va, &lock);
3010 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
3012 PMAP_ASSERT_STAGE1(pmap);
3013 if (!PMAP_TRYLOCK(pmap)) {
3014 pvh_gen = pvh->pv_gen;
3015 md_gen = m->md.pv_gen;
3019 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
3025 pmap_resident_count_dec(pmap, 1);
3027 pde = pmap_pde(pmap, pv->pv_va, &lvl);
3028 KASSERT(pde != NULL,
3029 ("pmap_remove_all: no page directory entry found"));
3031 ("pmap_remove_all: invalid pde level %d", lvl));
3032 tpde = pmap_load(pde);
3034 pte = pmap_l2_to_l3(pde, pv->pv_va);
3035 tpte = pmap_load_clear(pte);
3036 if (tpte & ATTR_SW_WIRED)
3037 pmap->pm_stats.wired_count--;
3038 if ((tpte & ATTR_AF) != 0) {
3039 pmap_invalidate_page(pmap, pv->pv_va);
3040 vm_page_aflag_set(m, PGA_REFERENCED);
3044 * Update the vm_page_t clean and reference bits.
3046 if (pmap_pte_dirty(pmap, tpte))
3048 pmap_unuse_pt(pmap, pv->pv_va, tpde, &free);
3049 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
3051 free_pv_entry(pmap, pv);
3054 vm_page_aflag_clear(m, PGA_WRITEABLE);
3056 vm_page_free_pages_toq(&free, true);
3060 * pmap_protect_l2: do the things to protect a 2MB page in a pmap
3063 pmap_protect_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t sva, pt_entry_t mask,
3069 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3070 PMAP_ASSERT_STAGE1(pmap);
3071 KASSERT((sva & L2_OFFSET) == 0,
3072 ("pmap_protect_l2: sva is not 2mpage aligned"));
3073 old_l2 = pmap_load(l2);
3074 KASSERT((old_l2 & ATTR_DESCR_MASK) == L2_BLOCK,
3075 ("pmap_protect_l2: L2e %lx is not a block mapping", old_l2));
3078 * Return if the L2 entry already has the desired access restrictions
3082 if ((old_l2 & mask) == nbits)
3086 * When a dirty read/write superpage mapping is write protected,
3087 * update the dirty field of each of the superpage's constituent 4KB
3090 if ((old_l2 & ATTR_SW_MANAGED) != 0 &&
3091 (nbits & ATTR_S1_AP(ATTR_S1_AP_RO)) != 0 &&
3092 pmap_pte_dirty(pmap, old_l2)) {
3093 m = PHYS_TO_VM_PAGE(old_l2 & ~ATTR_MASK);
3094 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
3098 if (!atomic_fcmpset_64(l2, &old_l2, (old_l2 & ~mask) | nbits))
3102 * Since a promotion must break the 4KB page mappings before making
3103 * the 2MB page mapping, a pmap_invalidate_page() suffices.
3105 pmap_invalidate_page(pmap, sva);
3109 * Set the physical protection on the
3110 * specified range of this map as requested.
3113 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
3115 vm_offset_t va, va_next;
3116 pd_entry_t *l0, *l1, *l2;
3117 pt_entry_t *l3p, l3, mask, nbits;
3119 PMAP_ASSERT_STAGE1(pmap);
3120 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
3121 if (prot == VM_PROT_NONE) {
3122 pmap_remove(pmap, sva, eva);
3127 if ((prot & VM_PROT_WRITE) == 0) {
3128 mask |= ATTR_S1_AP_RW_BIT | ATTR_SW_DBM;
3129 nbits |= ATTR_S1_AP(ATTR_S1_AP_RO);
3131 if ((prot & VM_PROT_EXECUTE) == 0) {
3133 nbits |= ATTR_S1_XN;
3139 for (; sva < eva; sva = va_next) {
3141 l0 = pmap_l0(pmap, sva);
3142 if (pmap_load(l0) == 0) {
3143 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
3149 l1 = pmap_l0_to_l1(l0, sva);
3150 if (pmap_load(l1) == 0) {
3151 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
3157 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
3161 l2 = pmap_l1_to_l2(l1, sva);
3162 if (pmap_load(l2) == 0)
3165 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK) {
3166 if (sva + L2_SIZE == va_next && eva >= va_next) {
3167 pmap_protect_l2(pmap, l2, sva, mask, nbits);
3169 } else if (pmap_demote_l2(pmap, l2, sva) == NULL)
3172 KASSERT((pmap_load(l2) & ATTR_DESCR_MASK) == L2_TABLE,
3173 ("pmap_protect: Invalid L2 entry after demotion"));
3179 for (l3p = pmap_l2_to_l3(l2, sva); sva != va_next; l3p++,
3181 l3 = pmap_load(l3p);
3184 * Go to the next L3 entry if the current one is
3185 * invalid or already has the desired access
3186 * restrictions in place. (The latter case occurs
3187 * frequently. For example, in a "buildworld"
3188 * workload, almost 1 out of 4 L3 entries already
3189 * have the desired restrictions.)
3191 if (!pmap_l3_valid(l3) || (l3 & mask) == nbits) {
3192 if (va != va_next) {
3193 pmap_invalidate_range(pmap, va, sva);
3200 * When a dirty read/write mapping is write protected,
3201 * update the page's dirty field.
3203 if ((l3 & ATTR_SW_MANAGED) != 0 &&
3204 (nbits & ATTR_S1_AP(ATTR_S1_AP_RO)) != 0 &&
3205 pmap_pte_dirty(pmap, l3))
3206 vm_page_dirty(PHYS_TO_VM_PAGE(l3 & ~ATTR_MASK));
3208 if (!atomic_fcmpset_64(l3p, &l3, (l3 & ~mask) | nbits))
3214 pmap_invalidate_range(pmap, va, sva);
3220 * Inserts the specified page table page into the specified pmap's collection
3221 * of idle page table pages. Each of a pmap's page table pages is responsible
3222 * for mapping a distinct range of virtual addresses. The pmap's collection is
3223 * ordered by this virtual address range.
3225 * If "promoted" is false, then the page table page "mpte" must be zero filled.
3228 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte, bool promoted)
3231 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3232 mpte->valid = promoted ? VM_PAGE_BITS_ALL : 0;
3233 return (vm_radix_insert(&pmap->pm_root, mpte));
3237 * Removes the page table page mapping the specified virtual address from the
3238 * specified pmap's collection of idle page table pages, and returns it.
3239 * Otherwise, returns NULL if there is no page table page corresponding to the
3240 * specified virtual address.
3242 static __inline vm_page_t
3243 pmap_remove_pt_page(pmap_t pmap, vm_offset_t va)
3246 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3247 return (vm_radix_remove(&pmap->pm_root, pmap_l2_pindex(va)));
3251 * Performs a break-before-make update of a pmap entry. This is needed when
3252 * either promoting or demoting pages to ensure the TLB doesn't get into an
3253 * inconsistent state.
3256 pmap_update_entry(pmap_t pmap, pd_entry_t *pte, pd_entry_t newpte,
3257 vm_offset_t va, vm_size_t size)
3261 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3264 * Ensure we don't get switched out with the page table in an
3265 * inconsistent state. We also need to ensure no interrupts fire
3266 * as they may make use of an address we are about to invalidate.
3268 intr = intr_disable();
3271 * Clear the old mapping's valid bit, but leave the rest of the entry
3272 * unchanged, so that a lockless, concurrent pmap_kextract() can still
3273 * lookup the physical address.
3275 pmap_clear_bits(pte, ATTR_DESCR_VALID);
3276 pmap_invalidate_range(pmap, va, va + size);
3278 /* Create the new mapping */
3279 pmap_store(pte, newpte);
3285 #if VM_NRESERVLEVEL > 0
3287 * After promotion from 512 4KB page mappings to a single 2MB page mapping,
3288 * replace the many pv entries for the 4KB page mappings by a single pv entry
3289 * for the 2MB page mapping.
3292 pmap_pv_promote_l2(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
3293 struct rwlock **lockp)
3295 struct md_page *pvh;
3297 vm_offset_t va_last;
3300 KASSERT((pa & L2_OFFSET) == 0,
3301 ("pmap_pv_promote_l2: pa is not 2mpage aligned"));
3302 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
3305 * Transfer the first page's pv entry for this mapping to the 2mpage's
3306 * pv list. Aside from avoiding the cost of a call to get_pv_entry(),
3307 * a transfer avoids the possibility that get_pv_entry() calls
3308 * reclaim_pv_chunk() and that reclaim_pv_chunk() removes one of the
3309 * mappings that is being promoted.
3311 m = PHYS_TO_VM_PAGE(pa);
3312 va = va & ~L2_OFFSET;
3313 pv = pmap_pvh_remove(&m->md, pmap, va);
3314 KASSERT(pv != NULL, ("pmap_pv_promote_l2: pv not found"));
3315 pvh = pa_to_pvh(pa);
3316 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
3318 /* Free the remaining NPTEPG - 1 pv entries. */
3319 va_last = va + L2_SIZE - PAGE_SIZE;
3323 pmap_pvh_free(&m->md, pmap, va);
3324 } while (va < va_last);
3328 * Tries to promote the 512, contiguous 4KB page mappings that are within a
3329 * single level 2 table entry to a single 2MB page mapping. For promotion
3330 * to occur, two conditions must be met: (1) the 4KB page mappings must map
3331 * aligned, contiguous physical memory and (2) the 4KB page mappings must have
3332 * identical characteristics.
3335 pmap_promote_l2(pmap_t pmap, pd_entry_t *l2, vm_offset_t va,
3336 struct rwlock **lockp)
3338 pt_entry_t *firstl3, *l3, newl2, oldl3, pa;
3342 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3343 PMAP_ASSERT_STAGE1(pmap);
3345 sva = va & ~L2_OFFSET;
3346 firstl3 = pmap_l2_to_l3(l2, sva);
3347 newl2 = pmap_load(firstl3);
3350 if (((newl2 & (~ATTR_MASK | ATTR_AF)) & L2_OFFSET) != ATTR_AF) {
3351 atomic_add_long(&pmap_l2_p_failures, 1);
3352 CTR2(KTR_PMAP, "pmap_promote_l2: failure for va %#lx"
3353 " in pmap %p", va, pmap);
3357 if ((newl2 & (ATTR_S1_AP_RW_BIT | ATTR_SW_DBM)) ==
3358 (ATTR_S1_AP(ATTR_S1_AP_RO) | ATTR_SW_DBM)) {
3359 if (!atomic_fcmpset_64(l2, &newl2, newl2 & ~ATTR_SW_DBM))
3361 newl2 &= ~ATTR_SW_DBM;
3364 pa = newl2 + L2_SIZE - PAGE_SIZE;
3365 for (l3 = firstl3 + NL3PG - 1; l3 > firstl3; l3--) {
3366 oldl3 = pmap_load(l3);
3368 if ((oldl3 & (ATTR_S1_AP_RW_BIT | ATTR_SW_DBM)) ==
3369 (ATTR_S1_AP(ATTR_S1_AP_RO) | ATTR_SW_DBM)) {
3370 if (!atomic_fcmpset_64(l3, &oldl3, oldl3 &
3373 oldl3 &= ~ATTR_SW_DBM;
3376 atomic_add_long(&pmap_l2_p_failures, 1);
3377 CTR2(KTR_PMAP, "pmap_promote_l2: failure for va %#lx"
3378 " in pmap %p", va, pmap);
3385 * Save the page table page in its current state until the L2
3386 * mapping the superpage is demoted by pmap_demote_l2() or
3387 * destroyed by pmap_remove_l3().
3389 mpte = PHYS_TO_VM_PAGE(pmap_load(l2) & ~ATTR_MASK);
3390 KASSERT(mpte >= vm_page_array &&
3391 mpte < &vm_page_array[vm_page_array_size],
3392 ("pmap_promote_l2: page table page is out of range"));
3393 KASSERT(mpte->pindex == pmap_l2_pindex(va),
3394 ("pmap_promote_l2: page table page's pindex is wrong"));
3395 if (pmap_insert_pt_page(pmap, mpte, true)) {
3396 atomic_add_long(&pmap_l2_p_failures, 1);
3398 "pmap_promote_l2: failure for va %#lx in pmap %p", va,
3403 if ((newl2 & ATTR_SW_MANAGED) != 0)
3404 pmap_pv_promote_l2(pmap, va, newl2 & ~ATTR_MASK, lockp);
3406 newl2 &= ~ATTR_DESCR_MASK;
3409 pmap_update_entry(pmap, l2, newl2, sva, L2_SIZE);
3411 atomic_add_long(&pmap_l2_promotions, 1);
3412 CTR2(KTR_PMAP, "pmap_promote_l2: success for va %#lx in pmap %p", va,
3415 #endif /* VM_NRESERVLEVEL > 0 */
3418 * Insert the given physical page (p) at
3419 * the specified virtual address (v) in the
3420 * target physical map with the protection requested.
3422 * If specified, the page will be wired down, meaning
3423 * that the related pte can not be reclaimed.
3425 * NB: This is the only routine which MAY NOT lazy-evaluate
3426 * or lose information. That is, this routine must actually
3427 * insert this page into the given map NOW.
3430 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
3431 u_int flags, int8_t psind)
3433 struct rwlock *lock;
3435 pt_entry_t new_l3, orig_l3;
3436 pt_entry_t *l2, *l3;
3443 va = trunc_page(va);
3444 if ((m->oflags & VPO_UNMANAGED) == 0)
3445 VM_PAGE_OBJECT_BUSY_ASSERT(m);
3446 pa = VM_PAGE_TO_PHYS(m);
3447 new_l3 = (pt_entry_t)(pa | ATTR_DEFAULT | L3_PAGE);
3448 new_l3 |= pmap_pte_memattr(pmap, m->md.pv_memattr);
3449 new_l3 |= pmap_pte_prot(pmap, prot);
3451 if ((flags & PMAP_ENTER_WIRED) != 0)
3452 new_l3 |= ATTR_SW_WIRED;
3453 if (pmap->pm_stage == PM_STAGE1) {
3454 if (va < VM_MAXUSER_ADDRESS)
3455 new_l3 |= ATTR_S1_AP(ATTR_S1_AP_USER) | ATTR_S1_PXN;
3457 new_l3 |= ATTR_S1_UXN;
3458 if (pmap != kernel_pmap)
3459 new_l3 |= ATTR_S1_nG;
3462 * Clear the access flag on executable mappings, this will be
3463 * set later when the page is accessed. The fault handler is
3464 * required to invalidate the I-cache.
3466 * TODO: Switch to the valid flag to allow hardware management
3467 * of the access flag. Much of the pmap code assumes the
3468 * valid flag is set and fails to destroy the old page tables
3469 * correctly if it is clear.
3471 if (prot & VM_PROT_EXECUTE)
3474 if ((m->oflags & VPO_UNMANAGED) == 0) {
3475 new_l3 |= ATTR_SW_MANAGED;
3476 if ((prot & VM_PROT_WRITE) != 0) {
3477 new_l3 |= ATTR_SW_DBM;
3478 if ((flags & VM_PROT_WRITE) == 0) {
3479 if (pmap->pm_stage == PM_STAGE1)
3480 new_l3 |= ATTR_S1_AP(ATTR_S1_AP_RO);
3483 ~ATTR_S2_S2AP(ATTR_S2_S2AP_WRITE);
3488 CTR2(KTR_PMAP, "pmap_enter: %.16lx -> %.16lx", va, pa);
3493 /* Assert the required virtual and physical alignment. */
3494 KASSERT((va & L2_OFFSET) == 0, ("pmap_enter: va unaligned"));
3495 KASSERT(m->psind > 0, ("pmap_enter: m->psind < psind"));
3496 rv = pmap_enter_l2(pmap, va, (new_l3 & ~L3_PAGE) | L2_BLOCK,
3503 * In the case that a page table page is not
3504 * resident, we are creating it here.
3507 pde = pmap_pde(pmap, va, &lvl);
3508 if (pde != NULL && lvl == 2) {
3509 l3 = pmap_l2_to_l3(pde, va);
3510 if (va < VM_MAXUSER_ADDRESS && mpte == NULL) {
3511 mpte = PHYS_TO_VM_PAGE(pmap_load(pde) & ~ATTR_MASK);
3515 } else if (pde != NULL && lvl == 1) {
3516 l2 = pmap_l1_to_l2(pde, va);
3517 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK &&
3518 (l3 = pmap_demote_l2_locked(pmap, l2, va, &lock)) != NULL) {
3519 l3 = &l3[pmap_l3_index(va)];
3520 if (va < VM_MAXUSER_ADDRESS) {
3521 mpte = PHYS_TO_VM_PAGE(
3522 pmap_load(l2) & ~ATTR_MASK);
3527 /* We need to allocate an L3 table. */
3529 if (va < VM_MAXUSER_ADDRESS) {
3530 nosleep = (flags & PMAP_ENTER_NOSLEEP) != 0;
3533 * We use _pmap_alloc_l3() instead of pmap_alloc_l3() in order
3534 * to handle the possibility that a superpage mapping for "va"
3535 * was created while we slept.
3537 mpte = _pmap_alloc_l3(pmap, pmap_l2_pindex(va),
3538 nosleep ? NULL : &lock);
3539 if (mpte == NULL && nosleep) {
3540 CTR0(KTR_PMAP, "pmap_enter: mpte == NULL");
3541 rv = KERN_RESOURCE_SHORTAGE;
3546 panic("pmap_enter: missing L3 table for kernel va %#lx", va);
3549 orig_l3 = pmap_load(l3);
3550 opa = orig_l3 & ~ATTR_MASK;
3554 * Is the specified virtual address already mapped?
3556 if (pmap_l3_valid(orig_l3)) {
3558 * Only allow adding new entries on stage 2 tables for now.
3559 * This simplifies cache invalidation as we may need to call
3560 * into EL2 to perform such actions.
3562 PMAP_ASSERT_STAGE1(pmap);
3564 * Wiring change, just update stats. We don't worry about
3565 * wiring PT pages as they remain resident as long as there
3566 * are valid mappings in them. Hence, if a user page is wired,
3567 * the PT page will be also.
3569 if ((flags & PMAP_ENTER_WIRED) != 0 &&
3570 (orig_l3 & ATTR_SW_WIRED) == 0)
3571 pmap->pm_stats.wired_count++;
3572 else if ((flags & PMAP_ENTER_WIRED) == 0 &&
3573 (orig_l3 & ATTR_SW_WIRED) != 0)
3574 pmap->pm_stats.wired_count--;
3577 * Remove the extra PT page reference.
3581 KASSERT(mpte->ref_count > 0,
3582 ("pmap_enter: missing reference to page table page,"
3587 * Has the physical page changed?
3591 * No, might be a protection or wiring change.
3593 if ((orig_l3 & ATTR_SW_MANAGED) != 0 &&
3594 (new_l3 & ATTR_SW_DBM) != 0)
3595 vm_page_aflag_set(m, PGA_WRITEABLE);
3600 * The physical page has changed. Temporarily invalidate
3603 orig_l3 = pmap_load_clear(l3);
3604 KASSERT((orig_l3 & ~ATTR_MASK) == opa,
3605 ("pmap_enter: unexpected pa update for %#lx", va));
3606 if ((orig_l3 & ATTR_SW_MANAGED) != 0) {
3607 om = PHYS_TO_VM_PAGE(opa);
3610 * The pmap lock is sufficient to synchronize with
3611 * concurrent calls to pmap_page_test_mappings() and
3612 * pmap_ts_referenced().
3614 if (pmap_pte_dirty(pmap, orig_l3))
3616 if ((orig_l3 & ATTR_AF) != 0) {
3617 pmap_invalidate_page(pmap, va);
3618 vm_page_aflag_set(om, PGA_REFERENCED);
3620 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, opa);
3621 pv = pmap_pvh_remove(&om->md, pmap, va);
3622 if ((m->oflags & VPO_UNMANAGED) != 0)
3623 free_pv_entry(pmap, pv);
3624 if ((om->a.flags & PGA_WRITEABLE) != 0 &&
3625 TAILQ_EMPTY(&om->md.pv_list) &&
3626 ((om->flags & PG_FICTITIOUS) != 0 ||
3627 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
3628 vm_page_aflag_clear(om, PGA_WRITEABLE);
3630 KASSERT((orig_l3 & ATTR_AF) != 0,
3631 ("pmap_enter: unmanaged mapping lacks ATTR_AF"));
3632 pmap_invalidate_page(pmap, va);
3637 * Increment the counters.
3639 if ((new_l3 & ATTR_SW_WIRED) != 0)
3640 pmap->pm_stats.wired_count++;
3641 pmap_resident_count_inc(pmap, 1);
3644 * Enter on the PV list if part of our managed memory.
3646 if ((m->oflags & VPO_UNMANAGED) == 0) {
3648 pv = get_pv_entry(pmap, &lock);
3651 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, pa);
3652 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3654 if ((new_l3 & ATTR_SW_DBM) != 0)
3655 vm_page_aflag_set(m, PGA_WRITEABLE);
3659 if (pmap->pm_stage == PM_STAGE1) {
3661 * Sync icache if exec permission and attribute
3662 * VM_MEMATTR_WRITE_BACK is set. Do it now, before the mapping
3663 * is stored and made valid for hardware table walk. If done
3664 * later, then other can access this page before caches are
3665 * properly synced. Don't do it for kernel memory which is
3666 * mapped with exec permission even if the memory isn't going
3667 * to hold executable code. The only time when icache sync is
3668 * needed is after kernel module is loaded and the relocation
3669 * info is processed. And it's done in elf_cpu_load_file().
3671 if ((prot & VM_PROT_EXECUTE) && pmap != kernel_pmap &&
3672 m->md.pv_memattr == VM_MEMATTR_WRITE_BACK &&
3673 (opa != pa || (orig_l3 & ATTR_S1_XN))) {
3674 PMAP_ASSERT_STAGE1(pmap);
3675 cpu_icache_sync_range(PHYS_TO_DMAP(pa), PAGE_SIZE);
3678 cpu_dcache_wb_range(PHYS_TO_DMAP(pa), PAGE_SIZE);
3682 * Update the L3 entry
3684 if (pmap_l3_valid(orig_l3)) {
3685 PMAP_ASSERT_STAGE1(pmap);
3686 KASSERT(opa == pa, ("pmap_enter: invalid update"));
3687 if ((orig_l3 & ~ATTR_AF) != (new_l3 & ~ATTR_AF)) {
3688 /* same PA, different attributes */
3689 orig_l3 = pmap_load_store(l3, new_l3);
3690 pmap_invalidate_page(pmap, va);
3691 if ((orig_l3 & ATTR_SW_MANAGED) != 0 &&
3692 pmap_pte_dirty(pmap, orig_l3))
3697 * This can happens if multiple threads simultaneously
3698 * access not yet mapped page. This bad for performance
3699 * since this can cause full demotion-NOP-promotion
3701 * Another possible reasons are:
3702 * - VM and pmap memory layout are diverged
3703 * - tlb flush is missing somewhere and CPU doesn't see
3706 CTR4(KTR_PMAP, "%s: already mapped page - "
3707 "pmap %p va 0x%#lx pte 0x%lx",
3708 __func__, pmap, va, new_l3);
3712 pmap_store(l3, new_l3);
3716 #if VM_NRESERVLEVEL > 0
3718 * Try to promote from level 3 pages to a level 2 superpage. This
3719 * currently only works on stage 1 pmaps as pmap_promote_l2 looks at
3720 * stage 1 specific fields and performs a break-before-make sequence
3721 * that is incorrect a stage 2 pmap.
3723 if ((mpte == NULL || mpte->ref_count == NL3PG) &&
3724 pmap_ps_enabled(pmap) && pmap->pm_stage == PM_STAGE1 &&
3725 (m->flags & PG_FICTITIOUS) == 0 &&
3726 vm_reserv_level_iffullpop(m) == 0) {
3727 pmap_promote_l2(pmap, pde, va, &lock);
3740 * Tries to create a read- and/or execute-only 2MB page mapping. Returns true
3741 * if successful. Returns false if (1) a page table page cannot be allocated
3742 * without sleeping, (2) a mapping already exists at the specified virtual
3743 * address, or (3) a PV entry cannot be allocated without reclaiming another
3747 pmap_enter_2mpage(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
3748 struct rwlock **lockp)
3752 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3753 PMAP_ASSERT_STAGE1(pmap);
3755 new_l2 = (pd_entry_t)(VM_PAGE_TO_PHYS(m) | ATTR_DEFAULT |
3756 ATTR_S1_IDX(m->md.pv_memattr) | ATTR_S1_AP(ATTR_S1_AP_RO) |
3758 if ((m->oflags & VPO_UNMANAGED) == 0) {
3759 new_l2 |= ATTR_SW_MANAGED;
3762 if ((prot & VM_PROT_EXECUTE) == 0 ||
3763 m->md.pv_memattr == VM_MEMATTR_DEVICE)
3764 new_l2 |= ATTR_S1_XN;
3765 if (va < VM_MAXUSER_ADDRESS)
3766 new_l2 |= ATTR_S1_AP(ATTR_S1_AP_USER) | ATTR_S1_PXN;
3768 new_l2 |= ATTR_S1_UXN;
3769 if (pmap != kernel_pmap)
3770 new_l2 |= ATTR_S1_nG;
3771 return (pmap_enter_l2(pmap, va, new_l2, PMAP_ENTER_NOSLEEP |
3772 PMAP_ENTER_NOREPLACE | PMAP_ENTER_NORECLAIM, NULL, lockp) ==
3777 * Returns true if every page table entry in the specified page table is
3781 pmap_every_pte_zero(vm_paddr_t pa)
3783 pt_entry_t *pt_end, *pte;
3785 KASSERT((pa & PAGE_MASK) == 0, ("pa is misaligned"));
3786 pte = (pt_entry_t *)PHYS_TO_DMAP(pa);
3787 for (pt_end = pte + Ln_ENTRIES; pte < pt_end; pte++) {
3795 * Tries to create the specified 2MB page mapping. Returns KERN_SUCCESS if
3796 * the mapping was created, and either KERN_FAILURE or KERN_RESOURCE_SHORTAGE
3797 * otherwise. Returns KERN_FAILURE if PMAP_ENTER_NOREPLACE was specified and
3798 * a mapping already exists at the specified virtual address. Returns
3799 * KERN_RESOURCE_SHORTAGE if PMAP_ENTER_NOSLEEP was specified and a page table
3800 * page allocation failed. Returns KERN_RESOURCE_SHORTAGE if
3801 * PMAP_ENTER_NORECLAIM was specified and a PV entry allocation failed.
3803 * The parameter "m" is only used when creating a managed, writeable mapping.
3806 pmap_enter_l2(pmap_t pmap, vm_offset_t va, pd_entry_t new_l2, u_int flags,
3807 vm_page_t m, struct rwlock **lockp)
3809 struct spglist free;
3810 pd_entry_t *l2, old_l2;
3813 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3815 if ((l2 = pmap_alloc_l2(pmap, va, &l2pg, (flags &
3816 PMAP_ENTER_NOSLEEP) != 0 ? NULL : lockp)) == NULL) {
3817 CTR2(KTR_PMAP, "pmap_enter_l2: failure for va %#lx in pmap %p",
3819 return (KERN_RESOURCE_SHORTAGE);
3823 * If there are existing mappings, either abort or remove them.
3825 if ((old_l2 = pmap_load(l2)) != 0) {
3826 KASSERT(l2pg == NULL || l2pg->ref_count > 1,
3827 ("pmap_enter_l2: l2pg's ref count is too low"));
3828 if ((flags & PMAP_ENTER_NOREPLACE) != 0 && (va <
3829 VM_MAXUSER_ADDRESS || (old_l2 & ATTR_DESCR_MASK) ==
3830 L2_BLOCK || !pmap_every_pte_zero(old_l2 & ~ATTR_MASK))) {
3833 CTR2(KTR_PMAP, "pmap_enter_l2: failure for va %#lx"
3834 " in pmap %p", va, pmap);
3835 return (KERN_FAILURE);
3838 if ((old_l2 & ATTR_DESCR_MASK) == L2_BLOCK)
3839 (void)pmap_remove_l2(pmap, l2, va,
3840 pmap_load(pmap_l1(pmap, va)), &free, lockp);
3842 pmap_remove_l3_range(pmap, old_l2, va, va + L2_SIZE,
3844 if (va < VM_MAXUSER_ADDRESS) {
3845 vm_page_free_pages_toq(&free, true);
3846 KASSERT(pmap_load(l2) == 0,
3847 ("pmap_enter_l2: non-zero L2 entry %p", l2));
3849 KASSERT(SLIST_EMPTY(&free),
3850 ("pmap_enter_l2: freed kernel page table page"));
3853 * Both pmap_remove_l2() and pmap_remove_l3_range()
3854 * will leave the kernel page table page zero filled.
3855 * Nonetheless, the TLB could have an intermediate
3856 * entry for the kernel page table page.
3858 mt = PHYS_TO_VM_PAGE(pmap_load(l2) & ~ATTR_MASK);
3859 if (pmap_insert_pt_page(pmap, mt, false))
3860 panic("pmap_enter_l2: trie insert failed");
3862 pmap_invalidate_page(pmap, va);
3866 if ((new_l2 & ATTR_SW_MANAGED) != 0) {
3868 * Abort this mapping if its PV entry could not be created.
3870 if (!pmap_pv_insert_l2(pmap, va, new_l2, flags, lockp)) {
3872 pmap_abort_ptp(pmap, va, l2pg);
3874 "pmap_enter_l2: failure for va %#lx in pmap %p",
3876 return (KERN_RESOURCE_SHORTAGE);
3878 if ((new_l2 & ATTR_SW_DBM) != 0)
3879 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
3880 vm_page_aflag_set(mt, PGA_WRITEABLE);
3884 * Increment counters.
3886 if ((new_l2 & ATTR_SW_WIRED) != 0)
3887 pmap->pm_stats.wired_count += L2_SIZE / PAGE_SIZE;
3888 pmap->pm_stats.resident_count += L2_SIZE / PAGE_SIZE;
3891 * Map the superpage.
3893 pmap_store(l2, new_l2);
3896 atomic_add_long(&pmap_l2_mappings, 1);
3897 CTR2(KTR_PMAP, "pmap_enter_l2: success for va %#lx in pmap %p",
3900 return (KERN_SUCCESS);
3904 * Maps a sequence of resident pages belonging to the same object.
3905 * The sequence begins with the given page m_start. This page is
3906 * mapped at the given virtual address start. Each subsequent page is
3907 * mapped at a virtual address that is offset from start by the same
3908 * amount as the page is offset from m_start within the object. The
3909 * last page in the sequence is the page with the largest offset from
3910 * m_start that can be mapped at a virtual address less than the given
3911 * virtual address end. Not every virtual page between start and end
3912 * is mapped; only those for which a resident page exists with the
3913 * corresponding offset from m_start are mapped.
3916 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
3917 vm_page_t m_start, vm_prot_t prot)
3919 struct rwlock *lock;
3922 vm_pindex_t diff, psize;
3924 VM_OBJECT_ASSERT_LOCKED(m_start->object);
3926 psize = atop(end - start);
3931 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
3932 va = start + ptoa(diff);
3933 if ((va & L2_OFFSET) == 0 && va + L2_SIZE <= end &&
3934 m->psind == 1 && pmap_ps_enabled(pmap) &&
3935 pmap_enter_2mpage(pmap, va, m, prot, &lock))
3936 m = &m[L2_SIZE / PAGE_SIZE - 1];
3938 mpte = pmap_enter_quick_locked(pmap, va, m, prot, mpte,
3940 m = TAILQ_NEXT(m, listq);
3948 * this code makes some *MAJOR* assumptions:
3949 * 1. Current pmap & pmap exists.
3952 * 4. No page table pages.
3953 * but is *MUCH* faster than pmap_enter...
3957 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3959 struct rwlock *lock;
3963 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL, &lock);
3970 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
3971 vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp)
3974 pt_entry_t *l2, *l3, l3_val;
3978 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
3979 (m->oflags & VPO_UNMANAGED) != 0,
3980 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
3981 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3982 PMAP_ASSERT_STAGE1(pmap);
3984 CTR2(KTR_PMAP, "pmap_enter_quick_locked: %p %lx", pmap, va);
3986 * In the case that a page table page is not
3987 * resident, we are creating it here.
3989 if (va < VM_MAXUSER_ADDRESS) {
3990 vm_pindex_t l2pindex;
3993 * Calculate pagetable page index
3995 l2pindex = pmap_l2_pindex(va);
3996 if (mpte && (mpte->pindex == l2pindex)) {
4002 pde = pmap_pde(pmap, va, &lvl);
4005 * If the page table page is mapped, we just increment
4006 * the hold count, and activate it. Otherwise, we
4007 * attempt to allocate a page table page. If this
4008 * attempt fails, we don't retry. Instead, we give up.
4011 l2 = pmap_l1_to_l2(pde, va);
4012 if ((pmap_load(l2) & ATTR_DESCR_MASK) ==
4016 if (lvl == 2 && pmap_load(pde) != 0) {
4018 PHYS_TO_VM_PAGE(pmap_load(pde) & ~ATTR_MASK);
4022 * Pass NULL instead of the PV list lock
4023 * pointer, because we don't intend to sleep.
4025 mpte = _pmap_alloc_l3(pmap, l2pindex, NULL);
4030 l3 = (pt_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpte));
4031 l3 = &l3[pmap_l3_index(va)];
4034 pde = pmap_pde(kernel_pmap, va, &lvl);
4035 KASSERT(pde != NULL,
4036 ("pmap_enter_quick_locked: Invalid page entry, va: 0x%lx",
4039 ("pmap_enter_quick_locked: Invalid level %d", lvl));
4040 l3 = pmap_l2_to_l3(pde, va);
4044 * Abort if a mapping already exists.
4046 if (pmap_load(l3) != 0) {
4053 * Enter on the PV list if part of our managed memory.
4055 if ((m->oflags & VPO_UNMANAGED) == 0 &&
4056 !pmap_try_insert_pv_entry(pmap, va, m, lockp)) {
4058 pmap_abort_ptp(pmap, va, mpte);
4063 * Increment counters
4065 pmap_resident_count_inc(pmap, 1);
4067 pa = VM_PAGE_TO_PHYS(m);
4068 l3_val = pa | ATTR_DEFAULT | ATTR_S1_IDX(m->md.pv_memattr) |
4069 ATTR_S1_AP(ATTR_S1_AP_RO) | L3_PAGE;
4070 if ((prot & VM_PROT_EXECUTE) == 0 ||
4071 m->md.pv_memattr == VM_MEMATTR_DEVICE)
4072 l3_val |= ATTR_S1_XN;
4073 if (va < VM_MAXUSER_ADDRESS)
4074 l3_val |= ATTR_S1_AP(ATTR_S1_AP_USER) | ATTR_S1_PXN;
4076 l3_val |= ATTR_S1_UXN;
4077 if (pmap != kernel_pmap)
4078 l3_val |= ATTR_S1_nG;
4081 * Now validate mapping with RO protection
4083 if ((m->oflags & VPO_UNMANAGED) == 0) {
4084 l3_val |= ATTR_SW_MANAGED;
4088 /* Sync icache before the mapping is stored to PTE */
4089 if ((prot & VM_PROT_EXECUTE) && pmap != kernel_pmap &&
4090 m->md.pv_memattr == VM_MEMATTR_WRITE_BACK)
4091 cpu_icache_sync_range(PHYS_TO_DMAP(pa), PAGE_SIZE);
4093 pmap_store(l3, l3_val);
4100 * This code maps large physical mmap regions into the
4101 * processor address space. Note that some shortcuts
4102 * are taken, but the code works.
4105 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
4106 vm_pindex_t pindex, vm_size_t size)
4109 VM_OBJECT_ASSERT_WLOCKED(object);
4110 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
4111 ("pmap_object_init_pt: non-device object"));
4115 * Clear the wired attribute from the mappings for the specified range of
4116 * addresses in the given pmap. Every valid mapping within that range
4117 * must have the wired attribute set. In contrast, invalid mappings
4118 * cannot have the wired attribute set, so they are ignored.
4120 * The wired attribute of the page table entry is not a hardware feature,
4121 * so there is no need to invalidate any TLB entries.
4124 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
4126 vm_offset_t va_next;
4127 pd_entry_t *l0, *l1, *l2;
4131 for (; sva < eva; sva = va_next) {
4132 l0 = pmap_l0(pmap, sva);
4133 if (pmap_load(l0) == 0) {
4134 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
4140 l1 = pmap_l0_to_l1(l0, sva);
4141 if (pmap_load(l1) == 0) {
4142 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
4148 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
4152 l2 = pmap_l1_to_l2(l1, sva);
4153 if (pmap_load(l2) == 0)
4156 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK) {
4157 if ((pmap_load(l2) & ATTR_SW_WIRED) == 0)
4158 panic("pmap_unwire: l2 %#jx is missing "
4159 "ATTR_SW_WIRED", (uintmax_t)pmap_load(l2));
4162 * Are we unwiring the entire large page? If not,
4163 * demote the mapping and fall through.
4165 if (sva + L2_SIZE == va_next && eva >= va_next) {
4166 pmap_clear_bits(l2, ATTR_SW_WIRED);
4167 pmap->pm_stats.wired_count -= L2_SIZE /
4170 } else if (pmap_demote_l2(pmap, l2, sva) == NULL)
4171 panic("pmap_unwire: demotion failed");
4173 KASSERT((pmap_load(l2) & ATTR_DESCR_MASK) == L2_TABLE,
4174 ("pmap_unwire: Invalid l2 entry after demotion"));
4178 for (l3 = pmap_l2_to_l3(l2, sva); sva != va_next; l3++,
4180 if (pmap_load(l3) == 0)
4182 if ((pmap_load(l3) & ATTR_SW_WIRED) == 0)
4183 panic("pmap_unwire: l3 %#jx is missing "
4184 "ATTR_SW_WIRED", (uintmax_t)pmap_load(l3));
4187 * ATTR_SW_WIRED must be cleared atomically. Although
4188 * the pmap lock synchronizes access to ATTR_SW_WIRED,
4189 * the System MMU may write to the entry concurrently.
4191 pmap_clear_bits(l3, ATTR_SW_WIRED);
4192 pmap->pm_stats.wired_count--;
4199 * Copy the range specified by src_addr/len
4200 * from the source map to the range dst_addr/len
4201 * in the destination map.
4203 * This routine is only advisory and need not do anything.
4205 * Because the executable mappings created by this routine are copied,
4206 * it should not have to flush the instruction cache.
4209 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
4210 vm_offset_t src_addr)
4212 struct rwlock *lock;
4213 pd_entry_t *l0, *l1, *l2, srcptepaddr;
4214 pt_entry_t *dst_pte, mask, nbits, ptetemp, *src_pte;
4215 vm_offset_t addr, end_addr, va_next;
4216 vm_page_t dst_l2pg, dstmpte, srcmpte;
4218 PMAP_ASSERT_STAGE1(dst_pmap);
4219 PMAP_ASSERT_STAGE1(src_pmap);
4221 if (dst_addr != src_addr)
4223 end_addr = src_addr + len;
4225 if (dst_pmap < src_pmap) {
4226 PMAP_LOCK(dst_pmap);
4227 PMAP_LOCK(src_pmap);
4229 PMAP_LOCK(src_pmap);
4230 PMAP_LOCK(dst_pmap);
4232 for (addr = src_addr; addr < end_addr; addr = va_next) {
4233 l0 = pmap_l0(src_pmap, addr);
4234 if (pmap_load(l0) == 0) {
4235 va_next = (addr + L0_SIZE) & ~L0_OFFSET;
4240 l1 = pmap_l0_to_l1(l0, addr);
4241 if (pmap_load(l1) == 0) {
4242 va_next = (addr + L1_SIZE) & ~L1_OFFSET;
4247 va_next = (addr + L2_SIZE) & ~L2_OFFSET;
4250 l2 = pmap_l1_to_l2(l1, addr);
4251 srcptepaddr = pmap_load(l2);
4252 if (srcptepaddr == 0)
4254 if ((srcptepaddr & ATTR_DESCR_MASK) == L2_BLOCK) {
4255 if ((addr & L2_OFFSET) != 0 ||
4256 addr + L2_SIZE > end_addr)
4258 l2 = pmap_alloc_l2(dst_pmap, addr, &dst_l2pg, NULL);
4261 if (pmap_load(l2) == 0 &&
4262 ((srcptepaddr & ATTR_SW_MANAGED) == 0 ||
4263 pmap_pv_insert_l2(dst_pmap, addr, srcptepaddr,
4264 PMAP_ENTER_NORECLAIM, &lock))) {
4265 mask = ATTR_AF | ATTR_SW_WIRED;
4267 if ((srcptepaddr & ATTR_SW_DBM) != 0)
4268 nbits |= ATTR_S1_AP_RW_BIT;
4269 pmap_store(l2, (srcptepaddr & ~mask) | nbits);
4270 pmap_resident_count_inc(dst_pmap, L2_SIZE /
4272 atomic_add_long(&pmap_l2_mappings, 1);
4274 pmap_abort_ptp(dst_pmap, addr, dst_l2pg);
4277 KASSERT((srcptepaddr & ATTR_DESCR_MASK) == L2_TABLE,
4278 ("pmap_copy: invalid L2 entry"));
4279 srcptepaddr &= ~ATTR_MASK;
4280 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr);
4281 KASSERT(srcmpte->ref_count > 0,
4282 ("pmap_copy: source page table page is unused"));
4283 if (va_next > end_addr)
4285 src_pte = (pt_entry_t *)PHYS_TO_DMAP(srcptepaddr);
4286 src_pte = &src_pte[pmap_l3_index(addr)];
4288 for (; addr < va_next; addr += PAGE_SIZE, src_pte++) {
4289 ptetemp = pmap_load(src_pte);
4292 * We only virtual copy managed pages.
4294 if ((ptetemp & ATTR_SW_MANAGED) == 0)
4297 if (dstmpte != NULL) {
4298 KASSERT(dstmpte->pindex == pmap_l2_pindex(addr),
4299 ("dstmpte pindex/addr mismatch"));
4300 dstmpte->ref_count++;
4301 } else if ((dstmpte = pmap_alloc_l3(dst_pmap, addr,
4304 dst_pte = (pt_entry_t *)
4305 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dstmpte));
4306 dst_pte = &dst_pte[pmap_l3_index(addr)];
4307 if (pmap_load(dst_pte) == 0 &&
4308 pmap_try_insert_pv_entry(dst_pmap, addr,
4309 PHYS_TO_VM_PAGE(ptetemp & ~ATTR_MASK), &lock)) {
4311 * Clear the wired, modified, and accessed
4312 * (referenced) bits during the copy.
4314 mask = ATTR_AF | ATTR_SW_WIRED;
4316 if ((ptetemp & ATTR_SW_DBM) != 0)
4317 nbits |= ATTR_S1_AP_RW_BIT;
4318 pmap_store(dst_pte, (ptetemp & ~mask) | nbits);
4319 pmap_resident_count_inc(dst_pmap, 1);
4321 pmap_abort_ptp(dst_pmap, addr, dstmpte);
4324 /* Have we copied all of the valid mappings? */
4325 if (dstmpte->ref_count >= srcmpte->ref_count)
4331 * XXX This barrier may not be needed because the destination pmap is
4338 PMAP_UNLOCK(src_pmap);
4339 PMAP_UNLOCK(dst_pmap);
4343 * pmap_zero_page zeros the specified hardware page by mapping
4344 * the page into KVM and using bzero to clear its contents.
4347 pmap_zero_page(vm_page_t m)
4349 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
4351 pagezero((void *)va);
4355 * pmap_zero_page_area zeros the specified hardware page by mapping
4356 * the page into KVM and using bzero to clear its contents.
4358 * off and size may not cover an area beyond a single hardware page.
4361 pmap_zero_page_area(vm_page_t m, int off, int size)
4363 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
4365 if (off == 0 && size == PAGE_SIZE)
4366 pagezero((void *)va);
4368 bzero((char *)va + off, size);
4372 * pmap_copy_page copies the specified (machine independent)
4373 * page by mapping the page into virtual memory and using
4374 * bcopy to copy the page, one machine dependent page at a
4378 pmap_copy_page(vm_page_t msrc, vm_page_t mdst)
4380 vm_offset_t src = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(msrc));
4381 vm_offset_t dst = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mdst));
4383 pagecopy((void *)src, (void *)dst);
4386 int unmapped_buf_allowed = 1;
4389 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
4390 vm_offset_t b_offset, int xfersize)
4394 vm_paddr_t p_a, p_b;
4395 vm_offset_t a_pg_offset, b_pg_offset;
4398 while (xfersize > 0) {
4399 a_pg_offset = a_offset & PAGE_MASK;
4400 m_a = ma[a_offset >> PAGE_SHIFT];
4401 p_a = m_a->phys_addr;
4402 b_pg_offset = b_offset & PAGE_MASK;
4403 m_b = mb[b_offset >> PAGE_SHIFT];
4404 p_b = m_b->phys_addr;
4405 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
4406 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
4407 if (__predict_false(!PHYS_IN_DMAP(p_a))) {
4408 panic("!DMAP a %lx", p_a);
4410 a_cp = (char *)PHYS_TO_DMAP(p_a) + a_pg_offset;
4412 if (__predict_false(!PHYS_IN_DMAP(p_b))) {
4413 panic("!DMAP b %lx", p_b);
4415 b_cp = (char *)PHYS_TO_DMAP(p_b) + b_pg_offset;
4417 bcopy(a_cp, b_cp, cnt);
4425 pmap_quick_enter_page(vm_page_t m)
4428 return (PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)));
4432 pmap_quick_remove_page(vm_offset_t addr)
4437 * Returns true if the pmap's pv is one of the first
4438 * 16 pvs linked to from this page. This count may
4439 * be changed upwards or downwards in the future; it
4440 * is only necessary that true be returned for a small
4441 * subset of pmaps for proper page aging.
4444 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
4446 struct md_page *pvh;
4447 struct rwlock *lock;
4452 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4453 ("pmap_page_exists_quick: page %p is not managed", m));
4455 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
4457 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4458 if (PV_PMAP(pv) == pmap) {
4466 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
4467 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4468 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4469 if (PV_PMAP(pv) == pmap) {
4483 * pmap_page_wired_mappings:
4485 * Return the number of managed mappings to the given physical page
4489 pmap_page_wired_mappings(vm_page_t m)
4491 struct rwlock *lock;
4492 struct md_page *pvh;
4496 int count, lvl, md_gen, pvh_gen;
4498 if ((m->oflags & VPO_UNMANAGED) != 0)
4500 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
4504 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4506 if (!PMAP_TRYLOCK(pmap)) {
4507 md_gen = m->md.pv_gen;
4511 if (md_gen != m->md.pv_gen) {
4516 pte = pmap_pte(pmap, pv->pv_va, &lvl);
4517 if (pte != NULL && (pmap_load(pte) & ATTR_SW_WIRED) != 0)
4521 if ((m->flags & PG_FICTITIOUS) == 0) {
4522 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4523 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4525 if (!PMAP_TRYLOCK(pmap)) {
4526 md_gen = m->md.pv_gen;
4527 pvh_gen = pvh->pv_gen;
4531 if (md_gen != m->md.pv_gen ||
4532 pvh_gen != pvh->pv_gen) {
4537 pte = pmap_pte(pmap, pv->pv_va, &lvl);
4539 (pmap_load(pte) & ATTR_SW_WIRED) != 0)
4549 * Returns true if the given page is mapped individually or as part of
4550 * a 2mpage. Otherwise, returns false.
4553 pmap_page_is_mapped(vm_page_t m)
4555 struct rwlock *lock;
4558 if ((m->oflags & VPO_UNMANAGED) != 0)
4560 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
4562 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
4563 ((m->flags & PG_FICTITIOUS) == 0 &&
4564 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
4570 * Destroy all managed, non-wired mappings in the given user-space
4571 * pmap. This pmap cannot be active on any processor besides the
4574 * This function cannot be applied to the kernel pmap. Moreover, it
4575 * is not intended for general use. It is only to be used during
4576 * process termination. Consequently, it can be implemented in ways
4577 * that make it faster than pmap_remove(). First, it can more quickly
4578 * destroy mappings by iterating over the pmap's collection of PV
4579 * entries, rather than searching the page table. Second, it doesn't
4580 * have to test and clear the page table entries atomically, because
4581 * no processor is currently accessing the user address space. In
4582 * particular, a page table entry's dirty bit won't change state once
4583 * this function starts.
4586 pmap_remove_pages(pmap_t pmap)
4589 pt_entry_t *pte, tpte;
4590 struct spglist free;
4591 vm_page_t m, ml3, mt;
4593 struct md_page *pvh;
4594 struct pv_chunk *pc, *npc;
4595 struct rwlock *lock;
4597 uint64_t inuse, bitmask;
4598 int allfree, field, freed, idx, lvl;
4601 KASSERT(pmap == PCPU_GET(curpmap), ("non-current pmap %p", pmap));
4607 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
4610 for (field = 0; field < _NPCM; field++) {
4611 inuse = ~pc->pc_map[field] & pc_freemask[field];
4612 while (inuse != 0) {
4613 bit = ffsl(inuse) - 1;
4614 bitmask = 1UL << bit;
4615 idx = field * 64 + bit;
4616 pv = &pc->pc_pventry[idx];
4619 pde = pmap_pde(pmap, pv->pv_va, &lvl);
4620 KASSERT(pde != NULL,
4621 ("Attempting to remove an unmapped page"));
4625 pte = pmap_l1_to_l2(pde, pv->pv_va);
4626 tpte = pmap_load(pte);
4627 KASSERT((tpte & ATTR_DESCR_MASK) ==
4629 ("Attempting to remove an invalid "
4630 "block: %lx", tpte));
4633 pte = pmap_l2_to_l3(pde, pv->pv_va);
4634 tpte = pmap_load(pte);
4635 KASSERT((tpte & ATTR_DESCR_MASK) ==
4637 ("Attempting to remove an invalid "
4638 "page: %lx", tpte));
4642 "Invalid page directory level: %d",
4647 * We cannot remove wired pages from a process' mapping at this time
4649 if (tpte & ATTR_SW_WIRED) {
4654 pa = tpte & ~ATTR_MASK;
4656 m = PHYS_TO_VM_PAGE(pa);
4657 KASSERT(m->phys_addr == pa,
4658 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
4659 m, (uintmax_t)m->phys_addr,
4662 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
4663 m < &vm_page_array[vm_page_array_size],
4664 ("pmap_remove_pages: bad pte %#jx",
4668 * Because this pmap is not active on other
4669 * processors, the dirty bit cannot have
4670 * changed state since we last loaded pte.
4675 * Update the vm_page_t clean/reference bits.
4677 if (pmap_pte_dirty(pmap, tpte)) {
4680 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
4689 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(&lock, m);
4692 pc->pc_map[field] |= bitmask;
4695 pmap_resident_count_dec(pmap,
4696 L2_SIZE / PAGE_SIZE);
4697 pvh = pa_to_pvh(tpte & ~ATTR_MASK);
4698 TAILQ_REMOVE(&pvh->pv_list, pv,pv_next);
4700 if (TAILQ_EMPTY(&pvh->pv_list)) {
4701 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
4702 if ((mt->a.flags & PGA_WRITEABLE) != 0 &&
4703 TAILQ_EMPTY(&mt->md.pv_list))
4704 vm_page_aflag_clear(mt, PGA_WRITEABLE);
4706 ml3 = pmap_remove_pt_page(pmap,
4709 KASSERT(ml3->valid == VM_PAGE_BITS_ALL,
4710 ("pmap_remove_pages: l3 page not promoted"));
4711 pmap_resident_count_dec(pmap,1);
4712 KASSERT(ml3->ref_count == NL3PG,
4713 ("pmap_remove_pages: l3 page ref count error"));
4715 pmap_add_delayed_free_list(ml3,
4720 pmap_resident_count_dec(pmap, 1);
4721 TAILQ_REMOVE(&m->md.pv_list, pv,
4724 if ((m->a.flags & PGA_WRITEABLE) != 0 &&
4725 TAILQ_EMPTY(&m->md.pv_list) &&
4726 (m->flags & PG_FICTITIOUS) == 0) {
4728 VM_PAGE_TO_PHYS(m));
4729 if (TAILQ_EMPTY(&pvh->pv_list))
4730 vm_page_aflag_clear(m,
4735 pmap_unuse_pt(pmap, pv->pv_va, pmap_load(pde),
4740 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
4741 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
4742 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
4744 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4750 pmap_invalidate_all(pmap);
4752 vm_page_free_pages_toq(&free, true);
4756 * This is used to check if a page has been accessed or modified.
4759 pmap_page_test_mappings(vm_page_t m, boolean_t accessed, boolean_t modified)
4761 struct rwlock *lock;
4763 struct md_page *pvh;
4764 pt_entry_t *pte, mask, value;
4766 int lvl, md_gen, pvh_gen;
4770 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
4773 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4775 PMAP_ASSERT_STAGE1(pmap);
4776 if (!PMAP_TRYLOCK(pmap)) {
4777 md_gen = m->md.pv_gen;
4781 if (md_gen != m->md.pv_gen) {
4786 pte = pmap_pte(pmap, pv->pv_va, &lvl);
4788 ("pmap_page_test_mappings: Invalid level %d", lvl));
4792 mask |= ATTR_S1_AP_RW_BIT;
4793 value |= ATTR_S1_AP(ATTR_S1_AP_RW);
4796 mask |= ATTR_AF | ATTR_DESCR_MASK;
4797 value |= ATTR_AF | L3_PAGE;
4799 rv = (pmap_load(pte) & mask) == value;
4804 if ((m->flags & PG_FICTITIOUS) == 0) {
4805 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4806 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4808 PMAP_ASSERT_STAGE1(pmap);
4809 if (!PMAP_TRYLOCK(pmap)) {
4810 md_gen = m->md.pv_gen;
4811 pvh_gen = pvh->pv_gen;
4815 if (md_gen != m->md.pv_gen ||
4816 pvh_gen != pvh->pv_gen) {
4821 pte = pmap_pte(pmap, pv->pv_va, &lvl);
4823 ("pmap_page_test_mappings: Invalid level %d", lvl));
4827 mask |= ATTR_S1_AP_RW_BIT;
4828 value |= ATTR_S1_AP(ATTR_S1_AP_RW);
4831 mask |= ATTR_AF | ATTR_DESCR_MASK;
4832 value |= ATTR_AF | L2_BLOCK;
4834 rv = (pmap_load(pte) & mask) == value;
4848 * Return whether or not the specified physical page was modified
4849 * in any physical maps.
4852 pmap_is_modified(vm_page_t m)
4855 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4856 ("pmap_is_modified: page %p is not managed", m));
4859 * If the page is not busied then this check is racy.
4861 if (!pmap_page_is_write_mapped(m))
4863 return (pmap_page_test_mappings(m, FALSE, TRUE));
4867 * pmap_is_prefaultable:
4869 * Return whether or not the specified virtual address is eligible
4873 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
4881 pte = pmap_pte(pmap, addr, &lvl);
4882 if (pte != NULL && pmap_load(pte) != 0) {
4890 * pmap_is_referenced:
4892 * Return whether or not the specified physical page was referenced
4893 * in any physical maps.
4896 pmap_is_referenced(vm_page_t m)
4899 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4900 ("pmap_is_referenced: page %p is not managed", m));
4901 return (pmap_page_test_mappings(m, TRUE, FALSE));
4905 * Clear the write and modified bits in each of the given page's mappings.
4908 pmap_remove_write(vm_page_t m)
4910 struct md_page *pvh;
4912 struct rwlock *lock;
4913 pv_entry_t next_pv, pv;
4914 pt_entry_t oldpte, *pte;
4916 int lvl, md_gen, pvh_gen;
4918 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4919 ("pmap_remove_write: page %p is not managed", m));
4920 vm_page_assert_busied(m);
4922 if (!pmap_page_is_write_mapped(m))
4924 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
4925 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
4926 pa_to_pvh(VM_PAGE_TO_PHYS(m));
4929 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
4931 PMAP_ASSERT_STAGE1(pmap);
4932 if (!PMAP_TRYLOCK(pmap)) {
4933 pvh_gen = pvh->pv_gen;
4937 if (pvh_gen != pvh->pv_gen) {
4944 pte = pmap_pte(pmap, pv->pv_va, &lvl);
4945 if ((pmap_load(pte) & ATTR_SW_DBM) != 0)
4946 (void)pmap_demote_l2_locked(pmap, pte, va, &lock);
4947 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
4948 ("inconsistent pv lock %p %p for page %p",
4949 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
4952 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4954 PMAP_ASSERT_STAGE1(pmap);
4955 if (!PMAP_TRYLOCK(pmap)) {
4956 pvh_gen = pvh->pv_gen;
4957 md_gen = m->md.pv_gen;
4961 if (pvh_gen != pvh->pv_gen ||
4962 md_gen != m->md.pv_gen) {
4968 pte = pmap_pte(pmap, pv->pv_va, &lvl);
4969 oldpte = pmap_load(pte);
4971 if ((oldpte & ATTR_SW_DBM) != 0) {
4972 if (!atomic_fcmpset_long(pte, &oldpte,
4973 (oldpte | ATTR_S1_AP_RW_BIT) & ~ATTR_SW_DBM))
4975 if ((oldpte & ATTR_S1_AP_RW_BIT) ==
4976 ATTR_S1_AP(ATTR_S1_AP_RW))
4978 pmap_invalidate_page(pmap, pv->pv_va);
4983 vm_page_aflag_clear(m, PGA_WRITEABLE);
4987 * pmap_ts_referenced:
4989 * Return a count of reference bits for a page, clearing those bits.
4990 * It is not necessary for every reference bit to be cleared, but it
4991 * is necessary that 0 only be returned when there are truly no
4992 * reference bits set.
4994 * As an optimization, update the page's dirty field if a modified bit is
4995 * found while counting reference bits. This opportunistic update can be
4996 * performed at low cost and can eliminate the need for some future calls
4997 * to pmap_is_modified(). However, since this function stops after
4998 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
4999 * dirty pages. Those dirty pages will only be detected by a future call
5000 * to pmap_is_modified().
5003 pmap_ts_referenced(vm_page_t m)
5005 struct md_page *pvh;
5008 struct rwlock *lock;
5009 pd_entry_t *pde, tpde;
5010 pt_entry_t *pte, tpte;
5013 int cleared, lvl, md_gen, not_cleared, pvh_gen;
5014 struct spglist free;
5016 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5017 ("pmap_ts_referenced: page %p is not managed", m));
5020 pa = VM_PAGE_TO_PHYS(m);
5021 lock = PHYS_TO_PV_LIST_LOCK(pa);
5022 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : pa_to_pvh(pa);
5026 if ((pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
5027 goto small_mappings;
5033 if (!PMAP_TRYLOCK(pmap)) {
5034 pvh_gen = pvh->pv_gen;
5038 if (pvh_gen != pvh->pv_gen) {
5044 pde = pmap_pde(pmap, pv->pv_va, &lvl);
5045 KASSERT(pde != NULL, ("pmap_ts_referenced: no l1 table found"));
5047 ("pmap_ts_referenced: invalid pde level %d", lvl));
5048 tpde = pmap_load(pde);
5049 KASSERT((tpde & ATTR_DESCR_MASK) == L1_TABLE,
5050 ("pmap_ts_referenced: found an invalid l1 table"));
5051 pte = pmap_l1_to_l2(pde, pv->pv_va);
5052 tpte = pmap_load(pte);
5053 if (pmap_pte_dirty(pmap, tpte)) {
5055 * Although "tpte" is mapping a 2MB page, because
5056 * this function is called at a 4KB page granularity,
5057 * we only update the 4KB page under test.
5062 if ((tpte & ATTR_AF) != 0) {
5064 * Since this reference bit is shared by 512 4KB pages,
5065 * it should not be cleared every time it is tested.
5066 * Apply a simple "hash" function on the physical page
5067 * number, the virtual superpage number, and the pmap
5068 * address to select one 4KB page out of the 512 on
5069 * which testing the reference bit will result in
5070 * clearing that reference bit. This function is
5071 * designed to avoid the selection of the same 4KB page
5072 * for every 2MB page mapping.
5074 * On demotion, a mapping that hasn't been referenced
5075 * is simply destroyed. To avoid the possibility of a
5076 * subsequent page fault on a demoted wired mapping,
5077 * always leave its reference bit set. Moreover,
5078 * since the superpage is wired, the current state of
5079 * its reference bit won't affect page replacement.
5081 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> L2_SHIFT) ^
5082 (uintptr_t)pmap) & (Ln_ENTRIES - 1)) == 0 &&
5083 (tpte & ATTR_SW_WIRED) == 0) {
5084 pmap_clear_bits(pte, ATTR_AF);
5085 pmap_invalidate_page(pmap, pv->pv_va);
5091 /* Rotate the PV list if it has more than one entry. */
5092 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
5093 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
5094 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
5097 if (cleared + not_cleared >= PMAP_TS_REFERENCED_MAX)
5099 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
5101 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
5108 if (!PMAP_TRYLOCK(pmap)) {
5109 pvh_gen = pvh->pv_gen;
5110 md_gen = m->md.pv_gen;
5114 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
5119 pde = pmap_pde(pmap, pv->pv_va, &lvl);
5120 KASSERT(pde != NULL, ("pmap_ts_referenced: no l2 table found"));
5122 ("pmap_ts_referenced: invalid pde level %d", lvl));
5123 tpde = pmap_load(pde);
5124 KASSERT((tpde & ATTR_DESCR_MASK) == L2_TABLE,
5125 ("pmap_ts_referenced: found an invalid l2 table"));
5126 pte = pmap_l2_to_l3(pde, pv->pv_va);
5127 tpte = pmap_load(pte);
5128 if (pmap_pte_dirty(pmap, tpte))
5130 if ((tpte & ATTR_AF) != 0) {
5131 if ((tpte & ATTR_SW_WIRED) == 0) {
5132 pmap_clear_bits(pte, ATTR_AF);
5133 pmap_invalidate_page(pmap, pv->pv_va);
5139 /* Rotate the PV list if it has more than one entry. */
5140 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
5141 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
5142 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
5145 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && cleared +
5146 not_cleared < PMAP_TS_REFERENCED_MAX);
5149 vm_page_free_pages_toq(&free, true);
5150 return (cleared + not_cleared);
5154 * Apply the given advice to the specified range of addresses within the
5155 * given pmap. Depending on the advice, clear the referenced and/or
5156 * modified flags in each mapping and set the mapped page's dirty field.
5159 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
5161 struct rwlock *lock;
5162 vm_offset_t va, va_next;
5164 pd_entry_t *l0, *l1, *l2, oldl2;
5165 pt_entry_t *l3, oldl3;
5167 PMAP_ASSERT_STAGE1(pmap);
5169 if (advice != MADV_DONTNEED && advice != MADV_FREE)
5173 for (; sva < eva; sva = va_next) {
5174 l0 = pmap_l0(pmap, sva);
5175 if (pmap_load(l0) == 0) {
5176 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
5181 l1 = pmap_l0_to_l1(l0, sva);
5182 if (pmap_load(l1) == 0) {
5183 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
5188 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
5191 l2 = pmap_l1_to_l2(l1, sva);
5192 oldl2 = pmap_load(l2);
5195 if ((oldl2 & ATTR_DESCR_MASK) == L2_BLOCK) {
5196 if ((oldl2 & ATTR_SW_MANAGED) == 0)
5199 if (!pmap_demote_l2_locked(pmap, l2, sva, &lock)) {
5204 * The 2MB page mapping was destroyed.
5210 * Unless the page mappings are wired, remove the
5211 * mapping to a single page so that a subsequent
5212 * access may repromote. Choosing the last page
5213 * within the address range [sva, min(va_next, eva))
5214 * generally results in more repromotions. Since the
5215 * underlying page table page is fully populated, this
5216 * removal never frees a page table page.
5218 if ((oldl2 & ATTR_SW_WIRED) == 0) {
5224 ("pmap_advise: no address gap"));
5225 l3 = pmap_l2_to_l3(l2, va);
5226 KASSERT(pmap_load(l3) != 0,
5227 ("pmap_advise: invalid PTE"));
5228 pmap_remove_l3(pmap, l3, va, pmap_load(l2),
5234 KASSERT((pmap_load(l2) & ATTR_DESCR_MASK) == L2_TABLE,
5235 ("pmap_advise: invalid L2 entry after demotion"));
5239 for (l3 = pmap_l2_to_l3(l2, sva); sva != va_next; l3++,
5241 oldl3 = pmap_load(l3);
5242 if ((oldl3 & (ATTR_SW_MANAGED | ATTR_DESCR_MASK)) !=
5243 (ATTR_SW_MANAGED | L3_PAGE))
5245 else if (pmap_pte_dirty(pmap, oldl3)) {
5246 if (advice == MADV_DONTNEED) {
5248 * Future calls to pmap_is_modified()
5249 * can be avoided by making the page
5252 m = PHYS_TO_VM_PAGE(oldl3 & ~ATTR_MASK);
5255 while (!atomic_fcmpset_long(l3, &oldl3,
5256 (oldl3 & ~ATTR_AF) |
5257 ATTR_S1_AP(ATTR_S1_AP_RO)))
5259 } else if ((oldl3 & ATTR_AF) != 0)
5260 pmap_clear_bits(l3, ATTR_AF);
5267 if (va != va_next) {
5268 pmap_invalidate_range(pmap, va, sva);
5273 pmap_invalidate_range(pmap, va, sva);
5279 * Clear the modify bits on the specified physical page.
5282 pmap_clear_modify(vm_page_t m)
5284 struct md_page *pvh;
5285 struct rwlock *lock;
5287 pv_entry_t next_pv, pv;
5288 pd_entry_t *l2, oldl2;
5289 pt_entry_t *l3, oldl3;
5291 int md_gen, pvh_gen;
5293 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5294 ("pmap_clear_modify: page %p is not managed", m));
5295 vm_page_assert_busied(m);
5297 if (!pmap_page_is_write_mapped(m))
5299 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
5300 pa_to_pvh(VM_PAGE_TO_PHYS(m));
5301 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5304 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
5306 PMAP_ASSERT_STAGE1(pmap);
5307 if (!PMAP_TRYLOCK(pmap)) {
5308 pvh_gen = pvh->pv_gen;
5312 if (pvh_gen != pvh->pv_gen) {
5318 l2 = pmap_l2(pmap, va);
5319 oldl2 = pmap_load(l2);
5320 /* If oldl2 has ATTR_SW_DBM set, then it is also dirty. */
5321 if ((oldl2 & ATTR_SW_DBM) != 0 &&
5322 pmap_demote_l2_locked(pmap, l2, va, &lock) &&
5323 (oldl2 & ATTR_SW_WIRED) == 0) {
5325 * Write protect the mapping to a single page so that
5326 * a subsequent write access may repromote.
5328 va += VM_PAGE_TO_PHYS(m) - (oldl2 & ~ATTR_MASK);
5329 l3 = pmap_l2_to_l3(l2, va);
5330 oldl3 = pmap_load(l3);
5331 while (!atomic_fcmpset_long(l3, &oldl3,
5332 (oldl3 & ~ATTR_SW_DBM) | ATTR_S1_AP(ATTR_S1_AP_RO)))
5335 pmap_invalidate_page(pmap, va);
5339 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5341 PMAP_ASSERT_STAGE1(pmap);
5342 if (!PMAP_TRYLOCK(pmap)) {
5343 md_gen = m->md.pv_gen;
5344 pvh_gen = pvh->pv_gen;
5348 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
5353 l2 = pmap_l2(pmap, pv->pv_va);
5354 l3 = pmap_l2_to_l3(l2, pv->pv_va);
5355 oldl3 = pmap_load(l3);
5356 if (pmap_l3_valid(oldl3) &&
5357 (oldl3 & (ATTR_S1_AP_RW_BIT | ATTR_SW_DBM)) == ATTR_SW_DBM){
5358 pmap_set_bits(l3, ATTR_S1_AP(ATTR_S1_AP_RO));
5359 pmap_invalidate_page(pmap, pv->pv_va);
5367 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
5369 struct pmap_preinit_mapping *ppim;
5370 vm_offset_t va, offset;
5373 int i, lvl, l2_blocks, free_l2_count, start_idx;
5375 if (!vm_initialized) {
5377 * No L3 ptables so map entire L2 blocks where start VA is:
5378 * preinit_map_va + start_idx * L2_SIZE
5379 * There may be duplicate mappings (multiple VA -> same PA) but
5380 * ARM64 dcache is always PIPT so that's acceptable.
5385 /* Calculate how many L2 blocks are needed for the mapping */
5386 l2_blocks = (roundup2(pa + size, L2_SIZE) -
5387 rounddown2(pa, L2_SIZE)) >> L2_SHIFT;
5389 offset = pa & L2_OFFSET;
5391 if (preinit_map_va == 0)
5394 /* Map 2MiB L2 blocks from reserved VA space */
5398 /* Find enough free contiguous VA space */
5399 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5400 ppim = pmap_preinit_mapping + i;
5401 if (free_l2_count > 0 && ppim->pa != 0) {
5402 /* Not enough space here */
5408 if (ppim->pa == 0) {
5410 if (start_idx == -1)
5413 if (free_l2_count == l2_blocks)
5417 if (free_l2_count != l2_blocks)
5418 panic("%s: too many preinit mappings", __func__);
5420 va = preinit_map_va + (start_idx * L2_SIZE);
5421 for (i = start_idx; i < start_idx + l2_blocks; i++) {
5422 /* Mark entries as allocated */
5423 ppim = pmap_preinit_mapping + i;
5425 ppim->va = va + offset;
5430 pa = rounddown2(pa, L2_SIZE);
5431 for (i = 0; i < l2_blocks; i++) {
5432 pde = pmap_pde(kernel_pmap, va, &lvl);
5433 KASSERT(pde != NULL,
5434 ("pmap_mapbios: Invalid page entry, va: 0x%lx",
5437 ("pmap_mapbios: Invalid level %d", lvl));
5439 /* Insert L2_BLOCK */
5440 l2 = pmap_l1_to_l2(pde, va);
5442 pa | ATTR_DEFAULT | ATTR_S1_XN |
5443 ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK) | L2_BLOCK);
5448 pmap_invalidate_all(kernel_pmap);
5450 va = preinit_map_va + (start_idx * L2_SIZE);
5453 /* kva_alloc may be used to map the pages */
5454 offset = pa & PAGE_MASK;
5455 size = round_page(offset + size);
5457 va = kva_alloc(size);
5459 panic("%s: Couldn't allocate KVA", __func__);
5461 pde = pmap_pde(kernel_pmap, va, &lvl);
5462 KASSERT(lvl == 2, ("pmap_mapbios: Invalid level %d", lvl));
5464 /* L3 table is linked */
5465 va = trunc_page(va);
5466 pa = trunc_page(pa);
5467 pmap_kenter(va, size, pa, memory_mapping_mode(pa));
5470 return ((void *)(va + offset));
5474 pmap_unmapbios(vm_offset_t va, vm_size_t size)
5476 struct pmap_preinit_mapping *ppim;
5477 vm_offset_t offset, tmpsize, va_trunc;
5480 int i, lvl, l2_blocks, block;
5484 (roundup2(va + size, L2_SIZE) - rounddown2(va, L2_SIZE)) >> L2_SHIFT;
5485 KASSERT(l2_blocks > 0, ("pmap_unmapbios: invalid size %lx", size));
5487 /* Remove preinit mapping */
5488 preinit_map = false;
5490 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5491 ppim = pmap_preinit_mapping + i;
5492 if (ppim->va == va) {
5493 KASSERT(ppim->size == size,
5494 ("pmap_unmapbios: size mismatch"));
5499 offset = block * L2_SIZE;
5500 va_trunc = rounddown2(va, L2_SIZE) + offset;
5502 /* Remove L2_BLOCK */
5503 pde = pmap_pde(kernel_pmap, va_trunc, &lvl);
5504 KASSERT(pde != NULL,
5505 ("pmap_unmapbios: Invalid page entry, va: 0x%lx",
5507 l2 = pmap_l1_to_l2(pde, va_trunc);
5510 if (block == (l2_blocks - 1))
5516 pmap_invalidate_all(kernel_pmap);
5520 /* Unmap the pages reserved with kva_alloc. */
5521 if (vm_initialized) {
5522 offset = va & PAGE_MASK;
5523 size = round_page(offset + size);
5524 va = trunc_page(va);
5526 pde = pmap_pde(kernel_pmap, va, &lvl);
5527 KASSERT(pde != NULL,
5528 ("pmap_unmapbios: Invalid page entry, va: 0x%lx", va));
5529 KASSERT(lvl == 2, ("pmap_unmapbios: Invalid level %d", lvl));
5531 /* Unmap and invalidate the pages */
5532 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
5533 pmap_kremove(va + tmpsize);
5540 * Sets the memory attribute for the specified page.
5543 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
5546 m->md.pv_memattr = ma;
5549 * If "m" is a normal page, update its direct mapping. This update
5550 * can be relied upon to perform any cache operations that are
5551 * required for data coherence.
5553 if ((m->flags & PG_FICTITIOUS) == 0 &&
5554 pmap_change_attr(PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)), PAGE_SIZE,
5555 m->md.pv_memattr) != 0)
5556 panic("memory attribute change on the direct map failed");
5560 * Changes the specified virtual address range's memory type to that given by
5561 * the parameter "mode". The specified virtual address range must be
5562 * completely contained within either the direct map or the kernel map. If
5563 * the virtual address range is contained within the kernel map, then the
5564 * memory type for each of the corresponding ranges of the direct map is also
5565 * changed. (The corresponding ranges of the direct map are those ranges that
5566 * map the same physical pages as the specified virtual address range.) These
5567 * changes to the direct map are necessary because Intel describes the
5568 * behavior of their processors as "undefined" if two or more mappings to the
5569 * same physical page have different memory types.
5571 * Returns zero if the change completed successfully, and either EINVAL or
5572 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
5573 * of the virtual address range was not mapped, and ENOMEM is returned if
5574 * there was insufficient memory available to complete the change. In the
5575 * latter case, the memory type may have been changed on some part of the
5576 * virtual address range or the direct map.
5579 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
5583 PMAP_LOCK(kernel_pmap);
5584 error = pmap_change_attr_locked(va, size, mode);
5585 PMAP_UNLOCK(kernel_pmap);
5590 pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode)
5592 vm_offset_t base, offset, tmpva;
5593 pt_entry_t l3, *pte, *newpte;
5596 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
5597 base = trunc_page(va);
5598 offset = va & PAGE_MASK;
5599 size = round_page(offset + size);
5601 if (!VIRT_IN_DMAP(base) &&
5602 !(base >= VM_MIN_KERNEL_ADDRESS && base < VM_MAX_KERNEL_ADDRESS))
5605 for (tmpva = base; tmpva < base + size; ) {
5606 pte = pmap_pte(kernel_pmap, tmpva, &lvl);
5610 if ((pmap_load(pte) & ATTR_S1_IDX_MASK) == ATTR_S1_IDX(mode)) {
5612 * We already have the correct attribute,
5613 * ignore this entry.
5617 panic("Invalid DMAP table level: %d\n", lvl);
5619 tmpva = (tmpva & ~L1_OFFSET) + L1_SIZE;
5622 tmpva = (tmpva & ~L2_OFFSET) + L2_SIZE;
5630 * Split the entry to an level 3 table, then
5631 * set the new attribute.
5635 panic("Invalid DMAP table level: %d\n", lvl);
5637 newpte = pmap_demote_l1(kernel_pmap, pte,
5638 tmpva & ~L1_OFFSET);
5641 pte = pmap_l1_to_l2(pte, tmpva);
5643 newpte = pmap_demote_l2(kernel_pmap, pte,
5647 pte = pmap_l2_to_l3(pte, tmpva);
5649 /* Update the entry */
5650 l3 = pmap_load(pte);
5651 l3 &= ~ATTR_S1_IDX_MASK;
5652 l3 |= ATTR_S1_IDX(mode);
5653 if (mode == VM_MEMATTR_DEVICE)
5656 pmap_update_entry(kernel_pmap, pte, l3, tmpva,
5660 * If moving to a non-cacheable entry flush
5663 if (mode == VM_MEMATTR_UNCACHEABLE)
5664 cpu_dcache_wbinv_range(tmpva, L3_SIZE);
5676 * Create an L2 table to map all addresses within an L1 mapping.
5679 pmap_demote_l1(pmap_t pmap, pt_entry_t *l1, vm_offset_t va)
5681 pt_entry_t *l2, newl2, oldl1;
5683 vm_paddr_t l2phys, phys;
5687 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5688 oldl1 = pmap_load(l1);
5689 KASSERT((oldl1 & ATTR_DESCR_MASK) == L1_BLOCK,
5690 ("pmap_demote_l1: Demoting a non-block entry"));
5691 KASSERT((va & L1_OFFSET) == 0,
5692 ("pmap_demote_l1: Invalid virtual address %#lx", va));
5693 KASSERT((oldl1 & ATTR_SW_MANAGED) == 0,
5694 ("pmap_demote_l1: Level 1 table shouldn't be managed"));
5697 if (va <= (vm_offset_t)l1 && va + L1_SIZE > (vm_offset_t)l1) {
5698 tmpl1 = kva_alloc(PAGE_SIZE);
5703 if ((ml2 = vm_page_alloc(NULL, 0, VM_ALLOC_INTERRUPT |
5704 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
5705 CTR2(KTR_PMAP, "pmap_demote_l1: failure for va %#lx"
5706 " in pmap %p", va, pmap);
5710 l2phys = VM_PAGE_TO_PHYS(ml2);
5711 l2 = (pt_entry_t *)PHYS_TO_DMAP(l2phys);
5713 /* Address the range points at */
5714 phys = oldl1 & ~ATTR_MASK;
5715 /* The attributed from the old l1 table to be copied */
5716 newl2 = oldl1 & ATTR_MASK;
5718 /* Create the new entries */
5719 for (i = 0; i < Ln_ENTRIES; i++) {
5720 l2[i] = newl2 | phys;
5723 KASSERT(l2[0] == ((oldl1 & ~ATTR_DESCR_MASK) | L2_BLOCK),
5724 ("Invalid l2 page (%lx != %lx)", l2[0],
5725 (oldl1 & ~ATTR_DESCR_MASK) | L2_BLOCK));
5728 pmap_kenter(tmpl1, PAGE_SIZE,
5729 DMAP_TO_PHYS((vm_offset_t)l1) & ~L3_OFFSET,
5730 VM_MEMATTR_WRITE_BACK);
5731 l1 = (pt_entry_t *)(tmpl1 + ((vm_offset_t)l1 & PAGE_MASK));
5734 pmap_update_entry(pmap, l1, l2phys | L1_TABLE, va, PAGE_SIZE);
5737 pmap_kremove(tmpl1);
5738 kva_free(tmpl1, PAGE_SIZE);
5745 pmap_fill_l3(pt_entry_t *firstl3, pt_entry_t newl3)
5749 for (l3 = firstl3; l3 - firstl3 < Ln_ENTRIES; l3++) {
5756 pmap_demote_l2_abort(pmap_t pmap, vm_offset_t va, pt_entry_t *l2,
5757 struct rwlock **lockp)
5759 struct spglist free;
5762 (void)pmap_remove_l2(pmap, l2, va, pmap_load(pmap_l1(pmap, va)), &free,
5764 vm_page_free_pages_toq(&free, true);
5768 * Create an L3 table to map all addresses within an L2 mapping.
5771 pmap_demote_l2_locked(pmap_t pmap, pt_entry_t *l2, vm_offset_t va,
5772 struct rwlock **lockp)
5774 pt_entry_t *l3, newl3, oldl2;
5779 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5780 PMAP_ASSERT_STAGE1(pmap);
5782 oldl2 = pmap_load(l2);
5783 KASSERT((oldl2 & ATTR_DESCR_MASK) == L2_BLOCK,
5784 ("pmap_demote_l2: Demoting a non-block entry"));
5788 if (va <= (vm_offset_t)l2 && va + L2_SIZE > (vm_offset_t)l2) {
5789 tmpl2 = kva_alloc(PAGE_SIZE);
5795 * Invalidate the 2MB page mapping and return "failure" if the
5796 * mapping was never accessed.
5798 if ((oldl2 & ATTR_AF) == 0) {
5799 KASSERT((oldl2 & ATTR_SW_WIRED) == 0,
5800 ("pmap_demote_l2: a wired mapping is missing ATTR_AF"));
5801 pmap_demote_l2_abort(pmap, va, l2, lockp);
5802 CTR2(KTR_PMAP, "pmap_demote_l2: failure for va %#lx in pmap %p",
5807 if ((ml3 = pmap_remove_pt_page(pmap, va)) == NULL) {
5808 KASSERT((oldl2 & ATTR_SW_WIRED) == 0,
5809 ("pmap_demote_l2: page table page for a wired mapping"
5813 * If the page table page is missing and the mapping
5814 * is for a kernel address, the mapping must belong to
5815 * the direct map. Page table pages are preallocated
5816 * for every other part of the kernel address space,
5817 * so the direct map region is the only part of the
5818 * kernel address space that must be handled here.
5820 KASSERT(va < VM_MAXUSER_ADDRESS || VIRT_IN_DMAP(va),
5821 ("pmap_demote_l2: No saved mpte for va %#lx", va));
5824 * If the 2MB page mapping belongs to the direct map
5825 * region of the kernel's address space, then the page
5826 * allocation request specifies the highest possible
5827 * priority (VM_ALLOC_INTERRUPT). Otherwise, the
5828 * priority is normal.
5830 ml3 = vm_page_alloc(NULL, pmap_l2_pindex(va),
5831 (VIRT_IN_DMAP(va) ? VM_ALLOC_INTERRUPT : VM_ALLOC_NORMAL) |
5832 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED);
5835 * If the allocation of the new page table page fails,
5836 * invalidate the 2MB page mapping and return "failure".
5839 pmap_demote_l2_abort(pmap, va, l2, lockp);
5840 CTR2(KTR_PMAP, "pmap_demote_l2: failure for va %#lx"
5841 " in pmap %p", va, pmap);
5845 if (va < VM_MAXUSER_ADDRESS) {
5846 ml3->ref_count = NL3PG;
5847 pmap_resident_count_inc(pmap, 1);
5850 l3phys = VM_PAGE_TO_PHYS(ml3);
5851 l3 = (pt_entry_t *)PHYS_TO_DMAP(l3phys);
5852 newl3 = (oldl2 & ~ATTR_DESCR_MASK) | L3_PAGE;
5853 KASSERT((oldl2 & (ATTR_S1_AP_RW_BIT | ATTR_SW_DBM)) !=
5854 (ATTR_S1_AP(ATTR_S1_AP_RO) | ATTR_SW_DBM),
5855 ("pmap_demote_l2: L2 entry is writeable but not dirty"));
5858 * If the page table page is not leftover from an earlier promotion,
5859 * or the mapping attributes have changed, (re)initialize the L3 table.
5861 * When pmap_update_entry() clears the old L2 mapping, it (indirectly)
5862 * performs a dsb(). That dsb() ensures that the stores for filling
5863 * "l3" are visible before "l3" is added to the page table.
5865 if (ml3->valid == 0 || (l3[0] & ATTR_MASK) != (newl3 & ATTR_MASK))
5866 pmap_fill_l3(l3, newl3);
5869 * Map the temporary page so we don't lose access to the l2 table.
5872 pmap_kenter(tmpl2, PAGE_SIZE,
5873 DMAP_TO_PHYS((vm_offset_t)l2) & ~L3_OFFSET,
5874 VM_MEMATTR_WRITE_BACK);
5875 l2 = (pt_entry_t *)(tmpl2 + ((vm_offset_t)l2 & PAGE_MASK));
5879 * The spare PV entries must be reserved prior to demoting the
5880 * mapping, that is, prior to changing the PDE. Otherwise, the state
5881 * of the L2 and the PV lists will be inconsistent, which can result
5882 * in reclaim_pv_chunk() attempting to remove a PV entry from the
5883 * wrong PV list and pmap_pv_demote_l2() failing to find the expected
5884 * PV entry for the 2MB page mapping that is being demoted.
5886 if ((oldl2 & ATTR_SW_MANAGED) != 0)
5887 reserve_pv_entries(pmap, Ln_ENTRIES - 1, lockp);
5890 * Pass PAGE_SIZE so that a single TLB invalidation is performed on
5891 * the 2MB page mapping.
5893 pmap_update_entry(pmap, l2, l3phys | L2_TABLE, va, PAGE_SIZE);
5896 * Demote the PV entry.
5898 if ((oldl2 & ATTR_SW_MANAGED) != 0)
5899 pmap_pv_demote_l2(pmap, va, oldl2 & ~ATTR_MASK, lockp);
5901 atomic_add_long(&pmap_l2_demotions, 1);
5902 CTR3(KTR_PMAP, "pmap_demote_l2: success for va %#lx"
5903 " in pmap %p %lx", va, pmap, l3[0]);
5907 pmap_kremove(tmpl2);
5908 kva_free(tmpl2, PAGE_SIZE);
5916 pmap_demote_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t va)
5918 struct rwlock *lock;
5922 l3 = pmap_demote_l2_locked(pmap, l2, va, &lock);
5929 * Perform the pmap work for mincore(2). If the page is not both referenced and
5930 * modified by this pmap, returns its physical address so that the caller can
5931 * find other mappings.
5934 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *pap)
5936 pt_entry_t *pte, tpte;
5937 vm_paddr_t mask, pa;
5941 PMAP_ASSERT_STAGE1(pmap);
5943 pte = pmap_pte(pmap, addr, &lvl);
5945 tpte = pmap_load(pte);
5958 panic("pmap_mincore: invalid level %d", lvl);
5961 managed = (tpte & ATTR_SW_MANAGED) != 0;
5962 val = MINCORE_INCORE;
5964 val |= MINCORE_SUPER;
5965 if ((managed && pmap_pte_dirty(pmap, tpte)) || (!managed &&
5966 (tpte & ATTR_S1_AP_RW_BIT) == ATTR_S1_AP(ATTR_S1_AP_RW)))
5967 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
5968 if ((tpte & ATTR_AF) == ATTR_AF)
5969 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
5971 pa = (tpte & ~ATTR_MASK) | (addr & mask);
5977 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
5978 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) && managed) {
5986 * Garbage collect every ASID that is neither active on a processor nor
5990 pmap_reset_asid_set(pmap_t pmap)
5993 int asid, cpuid, epoch;
5994 struct asid_set *set;
5995 enum pmap_stage stage;
5997 set = pmap->pm_asid_set;
5998 stage = pmap->pm_stage;
6000 set = pmap->pm_asid_set;
6001 KASSERT(set != NULL, ("%s: NULL asid set", __func__));
6002 mtx_assert(&set->asid_set_mutex, MA_OWNED);
6005 * Ensure that the store to asid_epoch is globally visible before the
6006 * loads from pc_curpmap are performed.
6008 epoch = set->asid_epoch + 1;
6009 if (epoch == INT_MAX)
6011 set->asid_epoch = epoch;
6013 if (stage == PM_STAGE1) {
6014 __asm __volatile("tlbi vmalle1is");
6016 KASSERT(pmap_clean_stage2_tlbi != NULL,
6017 ("%s: Unset stage 2 tlb invalidation callback\n",
6019 pmap_clean_stage2_tlbi();
6022 bit_nclear(set->asid_set, ASID_FIRST_AVAILABLE,
6023 set->asid_set_size - 1);
6024 CPU_FOREACH(cpuid) {
6025 if (cpuid == curcpu)
6027 if (stage == PM_STAGE1) {
6028 curpmap = pcpu_find(cpuid)->pc_curpmap;
6029 PMAP_ASSERT_STAGE1(pmap);
6031 curpmap = pcpu_find(cpuid)->pc_curvmpmap;
6032 if (curpmap == NULL)
6034 PMAP_ASSERT_STAGE2(pmap);
6036 KASSERT(curpmap->pm_asid_set == set, ("Incorrect set"));
6037 asid = COOKIE_TO_ASID(curpmap->pm_cookie);
6040 bit_set(set->asid_set, asid);
6041 curpmap->pm_cookie = COOKIE_FROM(asid, epoch);
6046 * Allocate a new ASID for the specified pmap.
6049 pmap_alloc_asid(pmap_t pmap)
6051 struct asid_set *set;
6054 set = pmap->pm_asid_set;
6055 KASSERT(set != NULL, ("%s: NULL asid set", __func__));
6057 mtx_lock_spin(&set->asid_set_mutex);
6060 * While this processor was waiting to acquire the asid set mutex,
6061 * pmap_reset_asid_set() running on another processor might have
6062 * updated this pmap's cookie to the current epoch. In which case, we
6063 * don't need to allocate a new ASID.
6065 if (COOKIE_TO_EPOCH(pmap->pm_cookie) == set->asid_epoch)
6068 bit_ffc_at(set->asid_set, set->asid_next, set->asid_set_size,
6070 if (new_asid == -1) {
6071 bit_ffc_at(set->asid_set, ASID_FIRST_AVAILABLE,
6072 set->asid_next, &new_asid);
6073 if (new_asid == -1) {
6074 pmap_reset_asid_set(pmap);
6075 bit_ffc_at(set->asid_set, ASID_FIRST_AVAILABLE,
6076 set->asid_set_size, &new_asid);
6077 KASSERT(new_asid != -1, ("ASID allocation failure"));
6080 bit_set(set->asid_set, new_asid);
6081 set->asid_next = new_asid + 1;
6082 pmap->pm_cookie = COOKIE_FROM(new_asid, set->asid_epoch);
6084 mtx_unlock_spin(&set->asid_set_mutex);
6088 * Compute the value that should be stored in ttbr0 to activate the specified
6089 * pmap. This value may change from time to time.
6092 pmap_to_ttbr0(pmap_t pmap)
6095 return (ASID_TO_OPERAND(COOKIE_TO_ASID(pmap->pm_cookie)) |
6100 pmap_activate_int(pmap_t pmap)
6102 struct asid_set *set;
6105 KASSERT(PCPU_GET(curpmap) != NULL, ("no active pmap"));
6106 KASSERT(pmap != kernel_pmap, ("kernel pmap activation"));
6108 if ((pmap->pm_stage == PM_STAGE1 && pmap == PCPU_GET(curpmap)) ||
6109 (pmap->pm_stage == PM_STAGE2 && pmap == PCPU_GET(curvmpmap))) {
6111 * Handle the possibility that the old thread was preempted
6112 * after an "ic" or "tlbi" instruction but before it performed
6113 * a "dsb" instruction. If the old thread migrates to a new
6114 * processor, its completion of a "dsb" instruction on that
6115 * new processor does not guarantee that the "ic" or "tlbi"
6116 * instructions performed on the old processor have completed.
6122 set = pmap->pm_asid_set;
6123 KASSERT(set != NULL, ("%s: NULL asid set", __func__));
6126 * Ensure that the store to curpmap is globally visible before the
6127 * load from asid_epoch is performed.
6129 if (pmap->pm_stage == PM_STAGE1)
6130 PCPU_SET(curpmap, pmap);
6132 PCPU_SET(curvmpmap, pmap);
6134 epoch = COOKIE_TO_EPOCH(pmap->pm_cookie);
6135 if (epoch >= 0 && epoch != set->asid_epoch)
6136 pmap_alloc_asid(pmap);
6138 if (pmap->pm_stage == PM_STAGE1) {
6139 set_ttbr0(pmap_to_ttbr0(pmap));
6140 if (PCPU_GET(bcast_tlbi_workaround) != 0)
6141 invalidate_local_icache();
6147 pmap_activate_vm(pmap_t pmap)
6150 PMAP_ASSERT_STAGE2(pmap);
6152 (void)pmap_activate_int(pmap);
6156 pmap_activate(struct thread *td)
6160 pmap = vmspace_pmap(td->td_proc->p_vmspace);
6161 PMAP_ASSERT_STAGE1(pmap);
6163 (void)pmap_activate_int(pmap);
6168 * To eliminate the unused parameter "old", we would have to add an instruction
6172 pmap_switch(struct thread *old __unused, struct thread *new)
6174 pcpu_bp_harden bp_harden;
6177 /* Store the new curthread */
6178 PCPU_SET(curthread, new);
6180 /* And the new pcb */
6182 PCPU_SET(curpcb, pcb);
6185 * TODO: We may need to flush the cache here if switching
6186 * to a user process.
6189 if (pmap_activate_int(vmspace_pmap(new->td_proc->p_vmspace))) {
6191 * Stop userspace from training the branch predictor against
6192 * other processes. This will call into a CPU specific
6193 * function that clears the branch predictor state.
6195 bp_harden = PCPU_GET(bp_harden);
6196 if (bp_harden != NULL)
6204 pmap_sync_icache(pmap_t pmap, vm_offset_t va, vm_size_t sz)
6207 PMAP_ASSERT_STAGE1(pmap);
6208 if (va >= VM_MIN_KERNEL_ADDRESS) {
6209 cpu_icache_sync_range(va, sz);
6214 /* Find the length of data in this page to flush */
6215 offset = va & PAGE_MASK;
6216 len = imin(PAGE_SIZE - offset, sz);
6219 /* Extract the physical address & find it in the DMAP */
6220 pa = pmap_extract(pmap, va);
6222 cpu_icache_sync_range(PHYS_TO_DMAP(pa), len);
6224 /* Move to the next page */
6227 /* Set the length for the next iteration */
6228 len = imin(PAGE_SIZE, sz);
6234 pmap_stage2_fault(pmap_t pmap, uint64_t esr, uint64_t far)
6237 pt_entry_t *ptep, pte;
6240 PMAP_ASSERT_STAGE2(pmap);
6243 /* Data and insn aborts use same encoding for FSC field. */
6244 dfsc = esr & ISS_DATA_DFSC_MASK;
6246 case ISS_DATA_DFSC_TF_L0:
6247 case ISS_DATA_DFSC_TF_L1:
6248 case ISS_DATA_DFSC_TF_L2:
6249 case ISS_DATA_DFSC_TF_L3:
6251 pdep = pmap_pde(pmap, far, &lvl);
6252 if (pdep == NULL || lvl != (dfsc - ISS_DATA_DFSC_TF_L1)) {
6259 ptep = pmap_l0_to_l1(pdep, far);
6262 ptep = pmap_l1_to_l2(pdep, far);
6265 ptep = pmap_l2_to_l3(pdep, far);
6268 panic("%s: Invalid pde level %d", __func__,lvl);
6272 case ISS_DATA_DFSC_AFF_L1:
6273 case ISS_DATA_DFSC_AFF_L2:
6274 case ISS_DATA_DFSC_AFF_L3:
6276 ptep = pmap_pte(pmap, far, &lvl);
6278 if (ptep != NULL && (pte = pmap_load(ptep)) != 0) {
6280 pmap_invalidate_vpipt_icache();
6283 * If accessing an executable page invalidate
6284 * the I-cache so it will be valid when we
6285 * continue execution in the guest. The D-cache
6286 * is assumed to already be clean to the Point
6289 if ((pte & ATTR_S2_XN_MASK) !=
6290 ATTR_S2_XN(ATTR_S2_XN_NONE)) {
6291 invalidate_icache();
6294 pmap_set_bits(ptep, ATTR_AF | ATTR_DESCR_VALID);
6305 pmap_fault(pmap_t pmap, uint64_t esr, uint64_t far)
6307 pt_entry_t pte, *ptep;
6314 ec = ESR_ELx_EXCEPTION(esr);
6316 case EXCP_INSN_ABORT_L:
6317 case EXCP_INSN_ABORT:
6318 case EXCP_DATA_ABORT_L:
6319 case EXCP_DATA_ABORT:
6325 if (pmap->pm_stage == PM_STAGE2)
6326 return (pmap_stage2_fault(pmap, esr, far));
6328 /* Data and insn aborts use same encoding for FSC field. */
6329 switch (esr & ISS_DATA_DFSC_MASK) {
6330 case ISS_DATA_DFSC_AFF_L1:
6331 case ISS_DATA_DFSC_AFF_L2:
6332 case ISS_DATA_DFSC_AFF_L3:
6334 ptep = pmap_pte(pmap, far, &lvl);
6336 pmap_set_bits(ptep, ATTR_AF);
6339 * XXXMJ as an optimization we could mark the entry
6340 * dirty if this is a write fault.
6345 case ISS_DATA_DFSC_PF_L1:
6346 case ISS_DATA_DFSC_PF_L2:
6347 case ISS_DATA_DFSC_PF_L3:
6348 if ((ec != EXCP_DATA_ABORT_L && ec != EXCP_DATA_ABORT) ||
6349 (esr & ISS_DATA_WnR) == 0)
6352 ptep = pmap_pte(pmap, far, &lvl);
6354 ((pte = pmap_load(ptep)) & ATTR_SW_DBM) != 0) {
6355 if ((pte & ATTR_S1_AP_RW_BIT) ==
6356 ATTR_S1_AP(ATTR_S1_AP_RO)) {
6357 pmap_clear_bits(ptep, ATTR_S1_AP_RW_BIT);
6358 pmap_invalidate_page(pmap, far);
6364 case ISS_DATA_DFSC_TF_L0:
6365 case ISS_DATA_DFSC_TF_L1:
6366 case ISS_DATA_DFSC_TF_L2:
6367 case ISS_DATA_DFSC_TF_L3:
6369 * Retry the translation. A break-before-make sequence can
6370 * produce a transient fault.
6372 if (pmap == kernel_pmap) {
6374 * The translation fault may have occurred within a
6375 * critical section. Therefore, we must check the
6376 * address without acquiring the kernel pmap's lock.
6378 if (pmap_kextract(far) != 0)
6382 /* Ask the MMU to check the address. */
6383 intr = intr_disable();
6384 par = arm64_address_translate_s1e0r(far);
6389 * If the translation was successful, then we can
6390 * return success to the trap handler.
6392 if (PAR_SUCCESS(par))
6402 * Increase the starting virtual address of the given mapping if a
6403 * different alignment might result in more superpage mappings.
6406 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
6407 vm_offset_t *addr, vm_size_t size)
6409 vm_offset_t superpage_offset;
6413 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
6414 offset += ptoa(object->pg_color);
6415 superpage_offset = offset & L2_OFFSET;
6416 if (size - ((L2_SIZE - superpage_offset) & L2_OFFSET) < L2_SIZE ||
6417 (*addr & L2_OFFSET) == superpage_offset)
6419 if ((*addr & L2_OFFSET) < superpage_offset)
6420 *addr = (*addr & ~L2_OFFSET) + superpage_offset;
6422 *addr = ((*addr + L2_OFFSET) & ~L2_OFFSET) + superpage_offset;
6426 * Get the kernel virtual address of a set of physical pages. If there are
6427 * physical addresses not covered by the DMAP perform a transient mapping
6428 * that will be removed when calling pmap_unmap_io_transient.
6430 * \param page The pages the caller wishes to obtain the virtual
6431 * address on the kernel memory map.
6432 * \param vaddr On return contains the kernel virtual memory address
6433 * of the pages passed in the page parameter.
6434 * \param count Number of pages passed in.
6435 * \param can_fault TRUE if the thread using the mapped pages can take
6436 * page faults, FALSE otherwise.
6438 * \returns TRUE if the caller must call pmap_unmap_io_transient when
6439 * finished or FALSE otherwise.
6443 pmap_map_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
6444 boolean_t can_fault)
6447 boolean_t needs_mapping;
6451 * Allocate any KVA space that we need, this is done in a separate
6452 * loop to prevent calling vmem_alloc while pinned.
6454 needs_mapping = FALSE;
6455 for (i = 0; i < count; i++) {
6456 paddr = VM_PAGE_TO_PHYS(page[i]);
6457 if (__predict_false(!PHYS_IN_DMAP(paddr))) {
6458 error = vmem_alloc(kernel_arena, PAGE_SIZE,
6459 M_BESTFIT | M_WAITOK, &vaddr[i]);
6460 KASSERT(error == 0, ("vmem_alloc failed: %d", error));
6461 needs_mapping = TRUE;
6463 vaddr[i] = PHYS_TO_DMAP(paddr);
6467 /* Exit early if everything is covered by the DMAP */
6473 for (i = 0; i < count; i++) {
6474 paddr = VM_PAGE_TO_PHYS(page[i]);
6475 if (!PHYS_IN_DMAP(paddr)) {
6477 "pmap_map_io_transient: TODO: Map out of DMAP data");
6481 return (needs_mapping);
6485 pmap_unmap_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
6486 boolean_t can_fault)
6493 for (i = 0; i < count; i++) {
6494 paddr = VM_PAGE_TO_PHYS(page[i]);
6495 if (!PHYS_IN_DMAP(paddr)) {
6496 panic("ARM64TODO: pmap_unmap_io_transient: Unmap data");
6502 pmap_is_valid_memattr(pmap_t pmap __unused, vm_memattr_t mode)
6505 return (mode >= VM_MEMATTR_DEVICE && mode <= VM_MEMATTR_WRITE_THROUGH);
6509 * Track a range of the kernel's virtual address space that is contiguous
6510 * in various mapping attributes.
6512 struct pmap_kernel_map_range {
6522 sysctl_kmaps_dump(struct sbuf *sb, struct pmap_kernel_map_range *range,
6528 if (eva <= range->sva)
6531 index = range->attrs & ATTR_S1_IDX_MASK;
6533 case ATTR_S1_IDX(VM_MEMATTR_DEVICE):
6536 case ATTR_S1_IDX(VM_MEMATTR_UNCACHEABLE):
6539 case ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK):
6542 case ATTR_S1_IDX(VM_MEMATTR_WRITE_THROUGH):
6547 "%s: unknown memory type %x for range 0x%016lx-0x%016lx\n",
6548 __func__, index, range->sva, eva);
6553 sbuf_printf(sb, "0x%016lx-0x%016lx r%c%c%c %3s %d %d %d %d\n",
6555 (range->attrs & ATTR_S1_AP_RW_BIT) == ATTR_S1_AP_RW ? 'w' : '-',
6556 (range->attrs & ATTR_S1_PXN) != 0 ? '-' : 'x',
6557 (range->attrs & ATTR_S1_AP_USER) != 0 ? 'u' : 's',
6558 mode, range->l1blocks, range->l2blocks, range->l3contig,
6561 /* Reset to sentinel value. */
6562 range->sva = 0xfffffffffffffffful;
6566 * Determine whether the attributes specified by a page table entry match those
6567 * being tracked by the current range.
6570 sysctl_kmaps_match(struct pmap_kernel_map_range *range, pt_entry_t attrs)
6573 return (range->attrs == attrs);
6577 sysctl_kmaps_reinit(struct pmap_kernel_map_range *range, vm_offset_t va,
6581 memset(range, 0, sizeof(*range));
6583 range->attrs = attrs;
6587 * Given a leaf PTE, derive the mapping's attributes. If they do not match
6588 * those of the current run, dump the address range and its attributes, and
6592 sysctl_kmaps_check(struct sbuf *sb, struct pmap_kernel_map_range *range,
6593 vm_offset_t va, pd_entry_t l0e, pd_entry_t l1e, pd_entry_t l2e,
6598 attrs = l0e & (ATTR_S1_AP_MASK | ATTR_S1_XN);
6599 attrs |= l1e & (ATTR_S1_AP_MASK | ATTR_S1_XN);
6600 if ((l1e & ATTR_DESCR_MASK) == L1_BLOCK)
6601 attrs |= l1e & ATTR_S1_IDX_MASK;
6602 attrs |= l2e & (ATTR_S1_AP_MASK | ATTR_S1_XN);
6603 if ((l2e & ATTR_DESCR_MASK) == L2_BLOCK)
6604 attrs |= l2e & ATTR_S1_IDX_MASK;
6605 attrs |= l3e & (ATTR_S1_AP_MASK | ATTR_S1_XN | ATTR_S1_IDX_MASK);
6607 if (range->sva > va || !sysctl_kmaps_match(range, attrs)) {
6608 sysctl_kmaps_dump(sb, range, va);
6609 sysctl_kmaps_reinit(range, va, attrs);
6614 sysctl_kmaps(SYSCTL_HANDLER_ARGS)
6616 struct pmap_kernel_map_range range;
6617 struct sbuf sbuf, *sb;
6618 pd_entry_t l0e, *l1, l1e, *l2, l2e;
6619 pt_entry_t *l3, l3e;
6622 int error, i, j, k, l;
6624 error = sysctl_wire_old_buffer(req, 0);
6628 sbuf_new_for_sysctl(sb, NULL, PAGE_SIZE, req);
6630 /* Sentinel value. */
6631 range.sva = 0xfffffffffffffffful;
6634 * Iterate over the kernel page tables without holding the kernel pmap
6635 * lock. Kernel page table pages are never freed, so at worst we will
6636 * observe inconsistencies in the output.
6638 for (sva = 0xffff000000000000ul, i = pmap_l0_index(sva); i < Ln_ENTRIES;
6640 if (i == pmap_l0_index(DMAP_MIN_ADDRESS))
6641 sbuf_printf(sb, "\nDirect map:\n");
6642 else if (i == pmap_l0_index(VM_MIN_KERNEL_ADDRESS))
6643 sbuf_printf(sb, "\nKernel map:\n");
6645 l0e = kernel_pmap->pm_l0[i];
6646 if ((l0e & ATTR_DESCR_VALID) == 0) {
6647 sysctl_kmaps_dump(sb, &range, sva);
6651 pa = l0e & ~ATTR_MASK;
6652 l1 = (pd_entry_t *)PHYS_TO_DMAP(pa);
6654 for (j = pmap_l1_index(sva); j < Ln_ENTRIES; j++) {
6656 if ((l1e & ATTR_DESCR_VALID) == 0) {
6657 sysctl_kmaps_dump(sb, &range, sva);
6661 if ((l1e & ATTR_DESCR_MASK) == L1_BLOCK) {
6662 sysctl_kmaps_check(sb, &range, sva, l0e, l1e,
6668 pa = l1e & ~ATTR_MASK;
6669 l2 = (pd_entry_t *)PHYS_TO_DMAP(pa);
6671 for (k = pmap_l2_index(sva); k < Ln_ENTRIES; k++) {
6673 if ((l2e & ATTR_DESCR_VALID) == 0) {
6674 sysctl_kmaps_dump(sb, &range, sva);
6678 if ((l2e & ATTR_DESCR_MASK) == L2_BLOCK) {
6679 sysctl_kmaps_check(sb, &range, sva,
6685 pa = l2e & ~ATTR_MASK;
6686 l3 = (pt_entry_t *)PHYS_TO_DMAP(pa);
6688 for (l = pmap_l3_index(sva); l < Ln_ENTRIES;
6689 l++, sva += L3_SIZE) {
6691 if ((l3e & ATTR_DESCR_VALID) == 0) {
6692 sysctl_kmaps_dump(sb, &range,
6696 sysctl_kmaps_check(sb, &range, sva,
6697 l0e, l1e, l2e, l3e);
6698 if ((l3e & ATTR_CONTIGUOUS) != 0)
6699 range.l3contig += l % 16 == 0 ?
6708 error = sbuf_finish(sb);
6712 SYSCTL_OID(_vm_pmap, OID_AUTO, kernel_maps,
6713 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE,
6714 NULL, 0, sysctl_kmaps, "A",
6715 "Dump kernel address layout");