2 * Copyright (c) 1991 Regents of the University of California.
4 * Copyright (c) 1994 John S. Dyson
6 * Copyright (c) 1994 David Greenman
8 * Copyright (c) 2003 Peter Wemm
10 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
11 * All rights reserved.
12 * Copyright (c) 2014 Andrew Turner
13 * All rights reserved.
14 * Copyright (c) 2014-2016 The FreeBSD Foundation
15 * All rights reserved.
17 * This code is derived from software contributed to Berkeley by
18 * the Systems Programming Group of the University of Utah Computer
19 * Science Department and William Jolitz of UUNET Technologies Inc.
21 * This software was developed by Andrew Turner under sponsorship from
22 * the FreeBSD Foundation.
24 * Redistribution and use in source and binary forms, with or without
25 * modification, are permitted provided that the following conditions
27 * 1. Redistributions of source code must retain the above copyright
28 * notice, this list of conditions and the following disclaimer.
29 * 2. Redistributions in binary form must reproduce the above copyright
30 * notice, this list of conditions and the following disclaimer in the
31 * documentation and/or other materials provided with the distribution.
32 * 3. All advertising materials mentioning features or use of this software
33 * must display the following acknowledgement:
34 * This product includes software developed by the University of
35 * California, Berkeley and its contributors.
36 * 4. Neither the name of the University nor the names of its contributors
37 * may be used to endorse or promote products derived from this software
38 * without specific prior written permission.
40 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
41 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
42 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
43 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
44 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
45 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
46 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
47 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
48 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
49 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
52 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
55 * Copyright (c) 2003 Networks Associates Technology, Inc.
56 * All rights reserved.
58 * This software was developed for the FreeBSD Project by Jake Burkholder,
59 * Safeport Network Services, and Network Associates Laboratories, the
60 * Security Research Division of Network Associates, Inc. under
61 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
62 * CHATS research program.
64 * Redistribution and use in source and binary forms, with or without
65 * modification, are permitted provided that the following conditions
67 * 1. Redistributions of source code must retain the above copyright
68 * notice, this list of conditions and the following disclaimer.
69 * 2. Redistributions in binary form must reproduce the above copyright
70 * notice, this list of conditions and the following disclaimer in the
71 * documentation and/or other materials provided with the distribution.
73 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
74 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
77 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
78 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
79 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
80 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
81 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
82 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
86 #include <sys/cdefs.h>
87 __FBSDID("$FreeBSD$");
90 * Manages physical address maps.
92 * Since the information managed by this module is
93 * also stored by the logical address mapping module,
94 * this module may throw away valid virtual-to-physical
95 * mappings at almost any time. However, invalidations
96 * of virtual-to-physical mappings must be done as
99 * In order to cope with hardware architectures which
100 * make virtual-to-physical map invalidates expensive,
101 * this module may delay invalidate or reduced protection
102 * operations until such time as they are actually
103 * necessary. This module is given full information as
104 * to which processors are currently using which maps,
105 * and to when physical maps must be made correct.
110 #include <sys/param.h>
111 #include <sys/bitstring.h>
113 #include <sys/systm.h>
114 #include <sys/kernel.h>
116 #include <sys/limits.h>
117 #include <sys/lock.h>
118 #include <sys/malloc.h>
119 #include <sys/mman.h>
120 #include <sys/msgbuf.h>
121 #include <sys/mutex.h>
122 #include <sys/physmem.h>
123 #include <sys/proc.h>
124 #include <sys/rwlock.h>
125 #include <sys/sbuf.h>
127 #include <sys/vmem.h>
128 #include <sys/vmmeter.h>
129 #include <sys/sched.h>
130 #include <sys/sysctl.h>
131 #include <sys/_unrhdr.h>
135 #include <vm/vm_param.h>
136 #include <vm/vm_kern.h>
137 #include <vm/vm_page.h>
138 #include <vm/vm_map.h>
139 #include <vm/vm_object.h>
140 #include <vm/vm_extern.h>
141 #include <vm/vm_pageout.h>
142 #include <vm/vm_pager.h>
143 #include <vm/vm_phys.h>
144 #include <vm/vm_radix.h>
145 #include <vm/vm_reserv.h>
148 #include <machine/machdep.h>
149 #include <machine/md_var.h>
150 #include <machine/pcb.h>
152 #define PMAP_ASSERT_STAGE1(pmap) MPASS((pmap)->pm_stage == PM_STAGE1)
153 #define PMAP_ASSERT_STAGE2(pmap) MPASS((pmap)->pm_stage == PM_STAGE2)
155 #define NL0PG (PAGE_SIZE/(sizeof (pd_entry_t)))
156 #define NL1PG (PAGE_SIZE/(sizeof (pd_entry_t)))
157 #define NL2PG (PAGE_SIZE/(sizeof (pd_entry_t)))
158 #define NL3PG (PAGE_SIZE/(sizeof (pt_entry_t)))
160 #define NUL0E L0_ENTRIES
161 #define NUL1E (NUL0E * NL1PG)
162 #define NUL2E (NUL1E * NL2PG)
164 #if !defined(DIAGNOSTIC)
165 #ifdef __GNUC_GNU_INLINE__
166 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
168 #define PMAP_INLINE extern inline
175 #define PV_STAT(x) do { x ; } while (0)
177 #define PV_STAT(x) do { } while (0)
180 #define pmap_l2_pindex(v) ((v) >> L2_SHIFT)
181 #define pa_to_pvh(pa) (&pv_table[pmap_l2_pindex(pa)])
183 #define NPV_LIST_LOCKS MAXCPU
185 #define PHYS_TO_PV_LIST_LOCK(pa) \
186 (&pv_list_locks[pa_index(pa) % NPV_LIST_LOCKS])
188 #define CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa) do { \
189 struct rwlock **_lockp = (lockp); \
190 struct rwlock *_new_lock; \
192 _new_lock = PHYS_TO_PV_LIST_LOCK(pa); \
193 if (_new_lock != *_lockp) { \
194 if (*_lockp != NULL) \
195 rw_wunlock(*_lockp); \
196 *_lockp = _new_lock; \
201 #define CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m) \
202 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, VM_PAGE_TO_PHYS(m))
204 #define RELEASE_PV_LIST_LOCK(lockp) do { \
205 struct rwlock **_lockp = (lockp); \
207 if (*_lockp != NULL) { \
208 rw_wunlock(*_lockp); \
213 #define VM_PAGE_TO_PV_LIST_LOCK(m) \
214 PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m))
217 * The presence of this flag indicates that the mapping is writeable.
218 * If the ATTR_S1_AP_RO bit is also set, then the mapping is clean, otherwise
219 * it is dirty. This flag may only be set on managed mappings.
221 * The DBM bit is reserved on ARMv8.0 but it seems we can safely treat it
222 * as a software managed bit.
224 #define ATTR_SW_DBM ATTR_DBM
226 struct pmap kernel_pmap_store;
228 /* Used for mapping ACPI memory before VM is initialized */
229 #define PMAP_PREINIT_MAPPING_COUNT 32
230 #define PMAP_PREINIT_MAPPING_SIZE (PMAP_PREINIT_MAPPING_COUNT * L2_SIZE)
231 static vm_offset_t preinit_map_va; /* Start VA of pre-init mapping space */
232 static int vm_initialized = 0; /* No need to use pre-init maps when set */
235 * Reserve a few L2 blocks starting from 'preinit_map_va' pointer.
236 * Always map entire L2 block for simplicity.
237 * VA of L2 block = preinit_map_va + i * L2_SIZE
239 static struct pmap_preinit_mapping {
243 } pmap_preinit_mapping[PMAP_PREINIT_MAPPING_COUNT];
245 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
246 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
247 vm_offset_t kernel_vm_end = 0;
250 * Data for the pv entry allocation mechanism.
252 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
253 static struct mtx pv_chunks_mutex;
254 static struct rwlock pv_list_locks[NPV_LIST_LOCKS];
255 static struct md_page *pv_table;
256 static struct md_page pv_dummy;
258 vm_paddr_t dmap_phys_base; /* The start of the dmap region */
259 vm_paddr_t dmap_phys_max; /* The limit of the dmap region */
260 vm_offset_t dmap_max_addr; /* The virtual address limit of the dmap */
262 /* This code assumes all L1 DMAP entries will be used */
263 CTASSERT((DMAP_MIN_ADDRESS & ~L0_OFFSET) == DMAP_MIN_ADDRESS);
264 CTASSERT((DMAP_MAX_ADDRESS & ~L0_OFFSET) == DMAP_MAX_ADDRESS);
266 #define DMAP_TABLES ((DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS) >> L0_SHIFT)
267 extern pt_entry_t pagetable_dmap[];
269 #define PHYSMAP_SIZE (2 * (VM_PHYSSEG_MAX - 1))
270 static vm_paddr_t physmap[PHYSMAP_SIZE];
271 static u_int physmap_idx;
273 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
274 "VM/pmap parameters");
277 * This ASID allocator uses a bit vector ("asid_set") to remember which ASIDs
278 * that it has currently allocated to a pmap, a cursor ("asid_next") to
279 * optimize its search for a free ASID in the bit vector, and an epoch number
280 * ("asid_epoch") to indicate when it has reclaimed all previously allocated
281 * ASIDs that are not currently active on a processor.
283 * The current epoch number is always in the range [0, INT_MAX). Negative
284 * numbers and INT_MAX are reserved for special cases that are described
293 struct mtx asid_set_mutex;
296 static struct asid_set asids;
297 static struct asid_set vmids;
299 static SYSCTL_NODE(_vm_pmap, OID_AUTO, asid, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
301 SYSCTL_INT(_vm_pmap_asid, OID_AUTO, bits, CTLFLAG_RD, &asids.asid_bits, 0,
302 "The number of bits in an ASID");
303 SYSCTL_INT(_vm_pmap_asid, OID_AUTO, next, CTLFLAG_RD, &asids.asid_next, 0,
304 "The last allocated ASID plus one");
305 SYSCTL_INT(_vm_pmap_asid, OID_AUTO, epoch, CTLFLAG_RD, &asids.asid_epoch, 0,
306 "The current epoch number");
308 static SYSCTL_NODE(_vm_pmap, OID_AUTO, vmid, CTLFLAG_RD, 0, "VMID allocator");
309 SYSCTL_INT(_vm_pmap_vmid, OID_AUTO, bits, CTLFLAG_RD, &vmids.asid_bits, 0,
310 "The number of bits in an VMID");
311 SYSCTL_INT(_vm_pmap_vmid, OID_AUTO, next, CTLFLAG_RD, &vmids.asid_next, 0,
312 "The last allocated VMID plus one");
313 SYSCTL_INT(_vm_pmap_vmid, OID_AUTO, epoch, CTLFLAG_RD, &vmids.asid_epoch, 0,
314 "The current epoch number");
316 void (*pmap_clean_stage2_tlbi)(void);
317 void (*pmap_invalidate_vpipt_icache)(void);
320 * A pmap's cookie encodes an ASID and epoch number. Cookies for reserved
321 * ASIDs have a negative epoch number, specifically, INT_MIN. Cookies for
322 * dynamically allocated ASIDs have a non-negative epoch number.
324 * An invalid ASID is represented by -1.
326 * There are two special-case cookie values: (1) COOKIE_FROM(-1, INT_MIN),
327 * which indicates that an ASID should never be allocated to the pmap, and
328 * (2) COOKIE_FROM(-1, INT_MAX), which indicates that an ASID should be
329 * allocated when the pmap is next activated.
331 #define COOKIE_FROM(asid, epoch) ((long)((u_int)(asid) | \
332 ((u_long)(epoch) << 32)))
333 #define COOKIE_TO_ASID(cookie) ((int)(cookie))
334 #define COOKIE_TO_EPOCH(cookie) ((int)((u_long)(cookie) >> 32))
336 static int superpages_enabled = 1;
337 SYSCTL_INT(_vm_pmap, OID_AUTO, superpages_enabled,
338 CTLFLAG_RDTUN | CTLFLAG_NOFETCH, &superpages_enabled, 0,
339 "Are large page mappings enabled?");
342 * Internal flags for pmap_enter()'s helper functions.
344 #define PMAP_ENTER_NORECLAIM 0x1000000 /* Don't reclaim PV entries. */
345 #define PMAP_ENTER_NOREPLACE 0x2000000 /* Don't replace mappings. */
347 static void free_pv_chunk(struct pv_chunk *pc);
348 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
349 static pv_entry_t get_pv_entry(pmap_t pmap, struct rwlock **lockp);
350 static vm_page_t reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp);
351 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
352 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
355 static void pmap_abort_ptp(pmap_t pmap, vm_offset_t va, vm_page_t mpte);
356 static bool pmap_activate_int(pmap_t pmap);
357 static void pmap_alloc_asid(pmap_t pmap);
358 static int pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode);
359 static pt_entry_t *pmap_demote_l1(pmap_t pmap, pt_entry_t *l1, vm_offset_t va);
360 static pt_entry_t *pmap_demote_l2_locked(pmap_t pmap, pt_entry_t *l2,
361 vm_offset_t va, struct rwlock **lockp);
362 static pt_entry_t *pmap_demote_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t va);
363 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
364 vm_page_t m, vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp);
365 static int pmap_enter_l2(pmap_t pmap, vm_offset_t va, pd_entry_t new_l2,
366 u_int flags, vm_page_t m, struct rwlock **lockp);
367 static int pmap_remove_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t sva,
368 pd_entry_t l1e, struct spglist *free, struct rwlock **lockp);
369 static int pmap_remove_l3(pmap_t pmap, pt_entry_t *l3, vm_offset_t sva,
370 pd_entry_t l2e, struct spglist *free, struct rwlock **lockp);
371 static void pmap_reset_asid_set(pmap_t pmap);
372 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
373 vm_page_t m, struct rwlock **lockp);
375 static vm_page_t _pmap_alloc_l3(pmap_t pmap, vm_pindex_t ptepindex,
376 struct rwlock **lockp);
378 static void _pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m,
379 struct spglist *free);
380 static int pmap_unuse_pt(pmap_t, vm_offset_t, pd_entry_t, struct spglist *);
381 static __inline vm_page_t pmap_remove_pt_page(pmap_t pmap, vm_offset_t va);
384 * These load the old table data and store the new value.
385 * They need to be atomic as the System MMU may write to the table at
386 * the same time as the CPU.
388 #define pmap_clear(table) atomic_store_64(table, 0)
389 #define pmap_clear_bits(table, bits) atomic_clear_64(table, bits)
390 #define pmap_load(table) (*table)
391 #define pmap_load_clear(table) atomic_swap_64(table, 0)
392 #define pmap_load_store(table, entry) atomic_swap_64(table, entry)
393 #define pmap_set_bits(table, bits) atomic_set_64(table, bits)
394 #define pmap_store(table, entry) atomic_store_64(table, entry)
396 /********************/
397 /* Inline functions */
398 /********************/
401 pagecopy(void *s, void *d)
404 memcpy(d, s, PAGE_SIZE);
407 static __inline pd_entry_t *
408 pmap_l0(pmap_t pmap, vm_offset_t va)
411 return (&pmap->pm_l0[pmap_l0_index(va)]);
414 static __inline pd_entry_t *
415 pmap_l0_to_l1(pd_entry_t *l0, vm_offset_t va)
419 l1 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l0) & ~ATTR_MASK);
420 return (&l1[pmap_l1_index(va)]);
423 static __inline pd_entry_t *
424 pmap_l1(pmap_t pmap, vm_offset_t va)
428 l0 = pmap_l0(pmap, va);
429 if ((pmap_load(l0) & ATTR_DESCR_MASK) != L0_TABLE)
432 return (pmap_l0_to_l1(l0, va));
435 static __inline pd_entry_t *
436 pmap_l1_to_l2(pd_entry_t *l1p, vm_offset_t va)
441 KASSERT((l1 & ATTR_DESCR_MASK) == L1_TABLE,
442 ("%s: L1 entry %#lx is a leaf", __func__, l1));
443 l2p = (pd_entry_t *)PHYS_TO_DMAP(l1 & ~ATTR_MASK);
444 return (&l2p[pmap_l2_index(va)]);
447 static __inline pd_entry_t *
448 pmap_l2(pmap_t pmap, vm_offset_t va)
452 l1 = pmap_l1(pmap, va);
453 if ((pmap_load(l1) & ATTR_DESCR_MASK) != L1_TABLE)
456 return (pmap_l1_to_l2(l1, va));
459 static __inline pt_entry_t *
460 pmap_l2_to_l3(pd_entry_t *l2p, vm_offset_t va)
466 KASSERT((l2 & ATTR_DESCR_MASK) == L2_TABLE,
467 ("%s: L2 entry %#lx is a leaf", __func__, l2));
468 l3p = (pt_entry_t *)PHYS_TO_DMAP(l2 & ~ATTR_MASK);
469 return (&l3p[pmap_l3_index(va)]);
473 * Returns the lowest valid pde for a given virtual address.
474 * The next level may or may not point to a valid page or block.
476 static __inline pd_entry_t *
477 pmap_pde(pmap_t pmap, vm_offset_t va, int *level)
479 pd_entry_t *l0, *l1, *l2, desc;
481 l0 = pmap_l0(pmap, va);
482 desc = pmap_load(l0) & ATTR_DESCR_MASK;
483 if (desc != L0_TABLE) {
488 l1 = pmap_l0_to_l1(l0, va);
489 desc = pmap_load(l1) & ATTR_DESCR_MASK;
490 if (desc != L1_TABLE) {
495 l2 = pmap_l1_to_l2(l1, va);
496 desc = pmap_load(l2) & ATTR_DESCR_MASK;
497 if (desc != L2_TABLE) {
507 * Returns the lowest valid pte block or table entry for a given virtual
508 * address. If there are no valid entries return NULL and set the level to
509 * the first invalid level.
511 static __inline pt_entry_t *
512 pmap_pte(pmap_t pmap, vm_offset_t va, int *level)
514 pd_entry_t *l1, *l2, desc;
517 l1 = pmap_l1(pmap, va);
522 desc = pmap_load(l1) & ATTR_DESCR_MASK;
523 if (desc == L1_BLOCK) {
528 if (desc != L1_TABLE) {
533 l2 = pmap_l1_to_l2(l1, va);
534 desc = pmap_load(l2) & ATTR_DESCR_MASK;
535 if (desc == L2_BLOCK) {
540 if (desc != L2_TABLE) {
546 l3 = pmap_l2_to_l3(l2, va);
547 if ((pmap_load(l3) & ATTR_DESCR_MASK) != L3_PAGE)
554 pmap_ps_enabled(pmap_t pmap __unused)
557 return (superpages_enabled != 0);
561 pmap_get_tables(pmap_t pmap, vm_offset_t va, pd_entry_t **l0, pd_entry_t **l1,
562 pd_entry_t **l2, pt_entry_t **l3)
564 pd_entry_t *l0p, *l1p, *l2p;
566 if (pmap->pm_l0 == NULL)
569 l0p = pmap_l0(pmap, va);
572 if ((pmap_load(l0p) & ATTR_DESCR_MASK) != L0_TABLE)
575 l1p = pmap_l0_to_l1(l0p, va);
578 if ((pmap_load(l1p) & ATTR_DESCR_MASK) == L1_BLOCK) {
584 if ((pmap_load(l1p) & ATTR_DESCR_MASK) != L1_TABLE)
587 l2p = pmap_l1_to_l2(l1p, va);
590 if ((pmap_load(l2p) & ATTR_DESCR_MASK) == L2_BLOCK) {
595 if ((pmap_load(l2p) & ATTR_DESCR_MASK) != L2_TABLE)
598 *l3 = pmap_l2_to_l3(l2p, va);
604 pmap_l3_valid(pt_entry_t l3)
607 return ((l3 & ATTR_DESCR_MASK) == L3_PAGE);
610 CTASSERT(L1_BLOCK == L2_BLOCK);
613 pmap_pte_memattr(pmap_t pmap, vm_memattr_t memattr)
617 if (pmap->pm_stage == PM_STAGE1) {
618 val = ATTR_S1_IDX(memattr);
619 if (memattr == VM_MEMATTR_DEVICE)
627 case VM_MEMATTR_DEVICE:
628 return (ATTR_S2_MEMATTR(ATTR_S2_MEMATTR_DEVICE_nGnRnE) |
629 ATTR_S2_XN(ATTR_S2_XN_ALL));
630 case VM_MEMATTR_UNCACHEABLE:
631 return (ATTR_S2_MEMATTR(ATTR_S2_MEMATTR_NC));
632 case VM_MEMATTR_WRITE_BACK:
633 return (ATTR_S2_MEMATTR(ATTR_S2_MEMATTR_WB));
634 case VM_MEMATTR_WRITE_THROUGH:
635 return (ATTR_S2_MEMATTR(ATTR_S2_MEMATTR_WT));
637 panic("%s: invalid memory attribute %x", __func__, memattr);
642 pmap_pte_prot(pmap_t pmap, vm_prot_t prot)
647 if (pmap->pm_stage == PM_STAGE1) {
648 if ((prot & VM_PROT_EXECUTE) == 0)
650 if ((prot & VM_PROT_WRITE) == 0)
651 val |= ATTR_S1_AP(ATTR_S1_AP_RO);
653 if ((prot & VM_PROT_WRITE) != 0)
654 val |= ATTR_S2_S2AP(ATTR_S2_S2AP_WRITE);
655 if ((prot & VM_PROT_READ) != 0)
656 val |= ATTR_S2_S2AP(ATTR_S2_S2AP_READ);
657 if ((prot & VM_PROT_EXECUTE) == 0)
658 val |= ATTR_S2_XN(ATTR_S2_XN_ALL);
665 * Checks if the PTE is dirty.
668 pmap_pte_dirty(pmap_t pmap, pt_entry_t pte)
671 KASSERT((pte & ATTR_SW_MANAGED) != 0, ("pte %#lx is unmanaged", pte));
673 if (pmap->pm_stage == PM_STAGE1) {
674 KASSERT((pte & (ATTR_S1_AP_RW_BIT | ATTR_SW_DBM)) != 0,
675 ("pte %#lx is writeable and missing ATTR_SW_DBM", pte));
677 return ((pte & (ATTR_S1_AP_RW_BIT | ATTR_SW_DBM)) ==
678 (ATTR_S1_AP(ATTR_S1_AP_RW) | ATTR_SW_DBM));
681 return ((pte & ATTR_S2_S2AP(ATTR_S2_S2AP_WRITE)) ==
682 ATTR_S2_S2AP(ATTR_S2_S2AP_WRITE));
686 pmap_resident_count_inc(pmap_t pmap, int count)
689 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
690 pmap->pm_stats.resident_count += count;
694 pmap_resident_count_dec(pmap_t pmap, int count)
697 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
698 KASSERT(pmap->pm_stats.resident_count >= count,
699 ("pmap %p resident count underflow %ld %d", pmap,
700 pmap->pm_stats.resident_count, count));
701 pmap->pm_stats.resident_count -= count;
705 pmap_early_page_idx(vm_offset_t l1pt, vm_offset_t va, u_int *l1_slot,
711 l1 = (pd_entry_t *)l1pt;
712 *l1_slot = (va >> L1_SHIFT) & Ln_ADDR_MASK;
714 /* Check locore has used a table L1 map */
715 KASSERT((l1[*l1_slot] & ATTR_DESCR_MASK) == L1_TABLE,
716 ("Invalid bootstrap L1 table"));
717 /* Find the address of the L2 table */
718 l2 = (pt_entry_t *)init_pt_va;
719 *l2_slot = pmap_l2_index(va);
725 pmap_early_vtophys(vm_offset_t l1pt, vm_offset_t va)
727 u_int l1_slot, l2_slot;
730 l2 = pmap_early_page_idx(l1pt, va, &l1_slot, &l2_slot);
732 return ((l2[l2_slot] & ~ATTR_MASK) + (va & L2_OFFSET));
736 pmap_bootstrap_dmap(vm_offset_t kern_l1, vm_paddr_t min_pa,
737 vm_offset_t freemempos)
741 vm_paddr_t l2_pa, pa;
742 u_int l1_slot, l2_slot, prev_l1_slot;
745 dmap_phys_base = min_pa & ~L1_OFFSET;
751 #define DMAP_TABLES ((DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS) >> L0_SHIFT)
752 memset(pagetable_dmap, 0, PAGE_SIZE * DMAP_TABLES);
754 for (i = 0; i < (physmap_idx * 2); i += 2) {
755 pa = physmap[i] & ~L2_OFFSET;
756 va = pa - dmap_phys_base + DMAP_MIN_ADDRESS;
758 /* Create L2 mappings at the start of the region */
759 if ((pa & L1_OFFSET) != 0) {
760 l1_slot = ((va - DMAP_MIN_ADDRESS) >> L1_SHIFT);
761 if (l1_slot != prev_l1_slot) {
762 prev_l1_slot = l1_slot;
763 l2 = (pt_entry_t *)freemempos;
764 l2_pa = pmap_early_vtophys(kern_l1,
766 freemempos += PAGE_SIZE;
768 pmap_store(&pagetable_dmap[l1_slot],
769 (l2_pa & ~Ln_TABLE_MASK) | L1_TABLE);
771 memset(l2, 0, PAGE_SIZE);
774 ("pmap_bootstrap_dmap: NULL l2 map"));
775 for (; va < DMAP_MAX_ADDRESS && pa < physmap[i + 1];
776 pa += L2_SIZE, va += L2_SIZE) {
778 * We are on a boundary, stop to
779 * create a level 1 block
781 if ((pa & L1_OFFSET) == 0)
784 l2_slot = pmap_l2_index(va);
785 KASSERT(l2_slot != 0, ("..."));
786 pmap_store(&l2[l2_slot],
787 (pa & ~L2_OFFSET) | ATTR_DEFAULT |
789 ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK) |
792 KASSERT(va == (pa - dmap_phys_base + DMAP_MIN_ADDRESS),
796 for (; va < DMAP_MAX_ADDRESS && pa < physmap[i + 1] &&
797 (physmap[i + 1] - pa) >= L1_SIZE;
798 pa += L1_SIZE, va += L1_SIZE) {
799 l1_slot = ((va - DMAP_MIN_ADDRESS) >> L1_SHIFT);
800 pmap_store(&pagetable_dmap[l1_slot],
801 (pa & ~L1_OFFSET) | ATTR_DEFAULT | ATTR_S1_XN |
802 ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK) | L1_BLOCK);
805 /* Create L2 mappings at the end of the region */
806 if (pa < physmap[i + 1]) {
807 l1_slot = ((va - DMAP_MIN_ADDRESS) >> L1_SHIFT);
808 if (l1_slot != prev_l1_slot) {
809 prev_l1_slot = l1_slot;
810 l2 = (pt_entry_t *)freemempos;
811 l2_pa = pmap_early_vtophys(kern_l1,
813 freemempos += PAGE_SIZE;
815 pmap_store(&pagetable_dmap[l1_slot],
816 (l2_pa & ~Ln_TABLE_MASK) | L1_TABLE);
818 memset(l2, 0, PAGE_SIZE);
821 ("pmap_bootstrap_dmap: NULL l2 map"));
822 for (; va < DMAP_MAX_ADDRESS && pa < physmap[i + 1];
823 pa += L2_SIZE, va += L2_SIZE) {
824 l2_slot = pmap_l2_index(va);
825 pmap_store(&l2[l2_slot],
826 (pa & ~L2_OFFSET) | ATTR_DEFAULT |
828 ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK) |
833 if (pa > dmap_phys_max) {
845 pmap_bootstrap_l2(vm_offset_t l1pt, vm_offset_t va, vm_offset_t l2_start)
852 KASSERT((va & L1_OFFSET) == 0, ("Invalid virtual address"));
854 l1 = (pd_entry_t *)l1pt;
855 l1_slot = pmap_l1_index(va);
858 for (; va < VM_MAX_KERNEL_ADDRESS; l1_slot++, va += L1_SIZE) {
859 KASSERT(l1_slot < Ln_ENTRIES, ("Invalid L1 index"));
861 pa = pmap_early_vtophys(l1pt, l2pt);
862 pmap_store(&l1[l1_slot],
863 (pa & ~Ln_TABLE_MASK) | L1_TABLE);
867 /* Clean the L2 page table */
868 memset((void *)l2_start, 0, l2pt - l2_start);
874 pmap_bootstrap_l3(vm_offset_t l1pt, vm_offset_t va, vm_offset_t l3_start)
881 KASSERT((va & L2_OFFSET) == 0, ("Invalid virtual address"));
883 l2 = pmap_l2(kernel_pmap, va);
884 l2 = (pd_entry_t *)rounddown2((uintptr_t)l2, PAGE_SIZE);
885 l2_slot = pmap_l2_index(va);
888 for (; va < VM_MAX_KERNEL_ADDRESS; l2_slot++, va += L2_SIZE) {
889 KASSERT(l2_slot < Ln_ENTRIES, ("Invalid L2 index"));
891 pa = pmap_early_vtophys(l1pt, l3pt);
892 pmap_store(&l2[l2_slot],
893 (pa & ~Ln_TABLE_MASK) | ATTR_S1_UXN | L2_TABLE);
897 /* Clean the L2 page table */
898 memset((void *)l3_start, 0, l3pt - l3_start);
904 * Bootstrap the system enough to run with virtual memory.
907 pmap_bootstrap(vm_offset_t l0pt, vm_offset_t l1pt, vm_paddr_t kernstart,
910 vm_offset_t freemempos;
911 vm_offset_t dpcpu, msgbufpv;
912 vm_paddr_t start_pa, pa, min_pa;
916 /* Verify that the ASID is set through TTBR0. */
917 KASSERT((READ_SPECIALREG(tcr_el1) & TCR_A1) == 0,
918 ("pmap_bootstrap: TCR_EL1.A1 != 0"));
920 kern_delta = KERNBASE - kernstart;
922 printf("pmap_bootstrap %lx %lx %lx\n", l1pt, kernstart, kernlen);
923 printf("%lx\n", l1pt);
924 printf("%lx\n", (KERNBASE >> L1_SHIFT) & Ln_ADDR_MASK);
926 /* Set this early so we can use the pagetable walking functions */
927 kernel_pmap_store.pm_l0 = (pd_entry_t *)l0pt;
928 PMAP_LOCK_INIT(kernel_pmap);
929 kernel_pmap->pm_l0_paddr = l0pt - kern_delta;
930 kernel_pmap->pm_cookie = COOKIE_FROM(-1, INT_MIN);
931 kernel_pmap->pm_stage = PM_STAGE1;
932 kernel_pmap->pm_asid_set = &asids;
934 /* Assume the address we were loaded to is a valid physical address */
935 min_pa = KERNBASE - kern_delta;
937 physmap_idx = physmem_avail(physmap, nitems(physmap));
941 * Find the minimum physical address. physmap is sorted,
942 * but may contain empty ranges.
944 for (i = 0; i < physmap_idx * 2; i += 2) {
945 if (physmap[i] == physmap[i + 1])
947 if (physmap[i] <= min_pa)
951 freemempos = KERNBASE + kernlen;
952 freemempos = roundup2(freemempos, PAGE_SIZE);
954 /* Create a direct map region early so we can use it for pa -> va */
955 freemempos = pmap_bootstrap_dmap(l1pt, min_pa, freemempos);
957 start_pa = pa = KERNBASE - kern_delta;
960 * Create the l2 tables up to VM_MAX_KERNEL_ADDRESS. We assume that the
961 * loader allocated the first and only l2 page table page used to map
962 * the kernel, preloaded files and module metadata.
964 freemempos = pmap_bootstrap_l2(l1pt, KERNBASE + L1_SIZE, freemempos);
965 /* And the l3 tables for the early devmap */
966 freemempos = pmap_bootstrap_l3(l1pt,
967 VM_MAX_KERNEL_ADDRESS - (PMAP_MAPDEV_EARLY_SIZE), freemempos);
971 #define alloc_pages(var, np) \
972 (var) = freemempos; \
973 freemempos += (np * PAGE_SIZE); \
974 memset((char *)(var), 0, ((np) * PAGE_SIZE));
976 /* Allocate dynamic per-cpu area. */
977 alloc_pages(dpcpu, DPCPU_SIZE / PAGE_SIZE);
978 dpcpu_init((void *)dpcpu, 0);
980 /* Allocate memory for the msgbuf, e.g. for /sbin/dmesg */
981 alloc_pages(msgbufpv, round_page(msgbufsize) / PAGE_SIZE);
982 msgbufp = (void *)msgbufpv;
984 /* Reserve some VA space for early BIOS/ACPI mapping */
985 preinit_map_va = roundup2(freemempos, L2_SIZE);
987 virtual_avail = preinit_map_va + PMAP_PREINIT_MAPPING_SIZE;
988 virtual_avail = roundup2(virtual_avail, L1_SIZE);
989 virtual_end = VM_MAX_KERNEL_ADDRESS - (PMAP_MAPDEV_EARLY_SIZE);
990 kernel_vm_end = virtual_avail;
992 pa = pmap_early_vtophys(l1pt, freemempos);
994 physmem_exclude_region(start_pa, pa - start_pa, EXFLAG_NOALLOC);
1000 * Initialize a vm_page's machine-dependent fields.
1003 pmap_page_init(vm_page_t m)
1006 TAILQ_INIT(&m->md.pv_list);
1007 m->md.pv_memattr = VM_MEMATTR_WRITE_BACK;
1011 pmap_init_asids(struct asid_set *set, int bits)
1015 set->asid_bits = bits;
1018 * We may be too early in the overall initialization process to use
1021 set->asid_set_size = 1 << set->asid_bits;
1022 set->asid_set = (bitstr_t *)kmem_malloc(bitstr_size(set->asid_set_size),
1024 for (i = 0; i < ASID_FIRST_AVAILABLE; i++)
1025 bit_set(set->asid_set, i);
1026 set->asid_next = ASID_FIRST_AVAILABLE;
1027 mtx_init(&set->asid_set_mutex, "asid set", NULL, MTX_SPIN);
1031 * Initialize the pmap module.
1032 * Called by vm_init, to initialize any structures that the pmap
1033 * system needs to map virtual memory.
1040 int i, pv_npg, vmid_bits;
1043 * Are large page mappings enabled?
1045 TUNABLE_INT_FETCH("vm.pmap.superpages_enabled", &superpages_enabled);
1046 if (superpages_enabled) {
1047 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
1048 ("pmap_init: can't assign to pagesizes[1]"));
1049 pagesizes[1] = L2_SIZE;
1053 * Initialize the ASID allocator.
1055 pmap_init_asids(&asids,
1056 (READ_SPECIALREG(tcr_el1) & TCR_ASID_16) != 0 ? 16 : 8);
1059 mmfr1 = READ_SPECIALREG(id_aa64mmfr1_el1);
1062 if (ID_AA64MMFR1_VMIDBits_VAL(mmfr1) ==
1063 ID_AA64MMFR1_VMIDBits_16)
1065 pmap_init_asids(&vmids, vmid_bits);
1069 * Initialize the pv chunk list mutex.
1071 mtx_init(&pv_chunks_mutex, "pmap pv chunk list", NULL, MTX_DEF);
1074 * Initialize the pool of pv list locks.
1076 for (i = 0; i < NPV_LIST_LOCKS; i++)
1077 rw_init(&pv_list_locks[i], "pmap pv list");
1080 * Calculate the size of the pv head table for superpages.
1082 pv_npg = howmany(vm_phys_segs[vm_phys_nsegs - 1].end, L2_SIZE);
1085 * Allocate memory for the pv head table for superpages.
1087 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
1089 pv_table = (struct md_page *)kmem_malloc(s, M_WAITOK | M_ZERO);
1090 for (i = 0; i < pv_npg; i++)
1091 TAILQ_INIT(&pv_table[i].pv_list);
1092 TAILQ_INIT(&pv_dummy.pv_list);
1097 static SYSCTL_NODE(_vm_pmap, OID_AUTO, l2, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
1098 "2MB page mapping counters");
1100 static u_long pmap_l2_demotions;
1101 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, demotions, CTLFLAG_RD,
1102 &pmap_l2_demotions, 0, "2MB page demotions");
1104 static u_long pmap_l2_mappings;
1105 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, mappings, CTLFLAG_RD,
1106 &pmap_l2_mappings, 0, "2MB page mappings");
1108 static u_long pmap_l2_p_failures;
1109 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, p_failures, CTLFLAG_RD,
1110 &pmap_l2_p_failures, 0, "2MB page promotion failures");
1112 static u_long pmap_l2_promotions;
1113 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, promotions, CTLFLAG_RD,
1114 &pmap_l2_promotions, 0, "2MB page promotions");
1117 * Invalidate a single TLB entry.
1119 static __inline void
1120 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
1124 PMAP_ASSERT_STAGE1(pmap);
1127 if (pmap == kernel_pmap) {
1129 __asm __volatile("tlbi vaae1is, %0" : : "r" (r));
1131 r = ASID_TO_OPERAND(COOKIE_TO_ASID(pmap->pm_cookie)) | atop(va);
1132 __asm __volatile("tlbi vae1is, %0" : : "r" (r));
1138 static __inline void
1139 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1141 uint64_t end, r, start;
1143 PMAP_ASSERT_STAGE1(pmap);
1146 if (pmap == kernel_pmap) {
1149 for (r = start; r < end; r++)
1150 __asm __volatile("tlbi vaae1is, %0" : : "r" (r));
1152 start = end = ASID_TO_OPERAND(COOKIE_TO_ASID(pmap->pm_cookie));
1155 for (r = start; r < end; r++)
1156 __asm __volatile("tlbi vae1is, %0" : : "r" (r));
1162 static __inline void
1163 pmap_invalidate_all(pmap_t pmap)
1167 PMAP_ASSERT_STAGE1(pmap);
1170 if (pmap == kernel_pmap) {
1171 __asm __volatile("tlbi vmalle1is");
1173 r = ASID_TO_OPERAND(COOKIE_TO_ASID(pmap->pm_cookie));
1174 __asm __volatile("tlbi aside1is, %0" : : "r" (r));
1181 * Routine: pmap_extract
1183 * Extract the physical page address associated
1184 * with the given map/virtual_address pair.
1187 pmap_extract(pmap_t pmap, vm_offset_t va)
1189 pt_entry_t *pte, tpte;
1196 * Find the block or page map for this virtual address. pmap_pte
1197 * will return either a valid block/page entry, or NULL.
1199 pte = pmap_pte(pmap, va, &lvl);
1201 tpte = pmap_load(pte);
1202 pa = tpte & ~ATTR_MASK;
1205 KASSERT((tpte & ATTR_DESCR_MASK) == L1_BLOCK,
1206 ("pmap_extract: Invalid L1 pte found: %lx",
1207 tpte & ATTR_DESCR_MASK));
1208 pa |= (va & L1_OFFSET);
1211 KASSERT((tpte & ATTR_DESCR_MASK) == L2_BLOCK,
1212 ("pmap_extract: Invalid L2 pte found: %lx",
1213 tpte & ATTR_DESCR_MASK));
1214 pa |= (va & L2_OFFSET);
1217 KASSERT((tpte & ATTR_DESCR_MASK) == L3_PAGE,
1218 ("pmap_extract: Invalid L3 pte found: %lx",
1219 tpte & ATTR_DESCR_MASK));
1220 pa |= (va & L3_OFFSET);
1229 * Routine: pmap_extract_and_hold
1231 * Atomically extract and hold the physical page
1232 * with the given pmap and virtual address pair
1233 * if that mapping permits the given protection.
1236 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1238 pt_entry_t *pte, tpte;
1246 pte = pmap_pte(pmap, va, &lvl);
1248 tpte = pmap_load(pte);
1250 KASSERT(lvl > 0 && lvl <= 3,
1251 ("pmap_extract_and_hold: Invalid level %d", lvl));
1252 CTASSERT(L1_BLOCK == L2_BLOCK);
1253 KASSERT((lvl == 3 && (tpte & ATTR_DESCR_MASK) == L3_PAGE) ||
1254 (lvl < 3 && (tpte & ATTR_DESCR_MASK) == L1_BLOCK),
1255 ("pmap_extract_and_hold: Invalid pte at L%d: %lx", lvl,
1256 tpte & ATTR_DESCR_MASK));
1259 if ((prot & VM_PROT_WRITE) == 0)
1261 else if (pmap->pm_stage == PM_STAGE1 &&
1262 (tpte & ATTR_S1_AP_RW_BIT) == ATTR_S1_AP(ATTR_S1_AP_RW))
1264 else if (pmap->pm_stage == PM_STAGE2 &&
1265 ((tpte & ATTR_S2_S2AP(ATTR_S2_S2AP_WRITE)) ==
1266 ATTR_S2_S2AP(ATTR_S2_S2AP_WRITE)))
1272 off = va & L1_OFFSET;
1275 off = va & L2_OFFSET;
1281 m = PHYS_TO_VM_PAGE((tpte & ~ATTR_MASK) | off);
1282 if (!vm_page_wire_mapped(m))
1291 pmap_kextract(vm_offset_t va)
1293 pt_entry_t *pte, tpte;
1295 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS)
1296 return (DMAP_TO_PHYS(va));
1297 pte = pmap_l1(kernel_pmap, va);
1302 * A concurrent pmap_update_entry() will clear the entry's valid bit
1303 * but leave the rest of the entry unchanged. Therefore, we treat a
1304 * non-zero entry as being valid, and we ignore the valid bit when
1305 * determining whether the entry maps a block, page, or table.
1307 tpte = pmap_load(pte);
1310 if ((tpte & ATTR_DESCR_TYPE_MASK) == ATTR_DESCR_TYPE_BLOCK)
1311 return ((tpte & ~ATTR_MASK) | (va & L1_OFFSET));
1312 pte = pmap_l1_to_l2(&tpte, va);
1313 tpte = pmap_load(pte);
1316 if ((tpte & ATTR_DESCR_TYPE_MASK) == ATTR_DESCR_TYPE_BLOCK)
1317 return ((tpte & ~ATTR_MASK) | (va & L2_OFFSET));
1318 pte = pmap_l2_to_l3(&tpte, va);
1319 tpte = pmap_load(pte);
1322 return ((tpte & ~ATTR_MASK) | (va & L3_OFFSET));
1325 /***************************************************
1326 * Low level mapping routines.....
1327 ***************************************************/
1330 pmap_kenter(vm_offset_t sva, vm_size_t size, vm_paddr_t pa, int mode)
1333 pt_entry_t *pte, attr;
1337 KASSERT((pa & L3_OFFSET) == 0,
1338 ("pmap_kenter: Invalid physical address"));
1339 KASSERT((sva & L3_OFFSET) == 0,
1340 ("pmap_kenter: Invalid virtual address"));
1341 KASSERT((size & PAGE_MASK) == 0,
1342 ("pmap_kenter: Mapping is not page-sized"));
1344 attr = ATTR_DEFAULT | ATTR_S1_AP(ATTR_S1_AP_RW) | ATTR_S1_XN |
1345 ATTR_S1_IDX(mode) | L3_PAGE;
1348 pde = pmap_pde(kernel_pmap, va, &lvl);
1349 KASSERT(pde != NULL,
1350 ("pmap_kenter: Invalid page entry, va: 0x%lx", va));
1351 KASSERT(lvl == 2, ("pmap_kenter: Invalid level %d", lvl));
1353 pte = pmap_l2_to_l3(pde, va);
1354 pmap_load_store(pte, (pa & ~L3_OFFSET) | attr);
1360 pmap_invalidate_range(kernel_pmap, sva, va);
1364 pmap_kenter_device(vm_offset_t sva, vm_size_t size, vm_paddr_t pa)
1367 pmap_kenter(sva, size, pa, VM_MEMATTR_DEVICE);
1371 * Remove a page from the kernel pagetables.
1374 pmap_kremove(vm_offset_t va)
1379 pte = pmap_pte(kernel_pmap, va, &lvl);
1380 KASSERT(pte != NULL, ("pmap_kremove: Invalid address"));
1381 KASSERT(lvl == 3, ("pmap_kremove: Invalid pte level %d", lvl));
1384 pmap_invalidate_page(kernel_pmap, va);
1388 pmap_kremove_device(vm_offset_t sva, vm_size_t size)
1394 KASSERT((sva & L3_OFFSET) == 0,
1395 ("pmap_kremove_device: Invalid virtual address"));
1396 KASSERT((size & PAGE_MASK) == 0,
1397 ("pmap_kremove_device: Mapping is not page-sized"));
1401 pte = pmap_pte(kernel_pmap, va, &lvl);
1402 KASSERT(pte != NULL, ("Invalid page table, va: 0x%lx", va));
1404 ("Invalid device pagetable level: %d != 3", lvl));
1410 pmap_invalidate_range(kernel_pmap, sva, va);
1414 * Used to map a range of physical addresses into kernel
1415 * virtual address space.
1417 * The value passed in '*virt' is a suggested virtual address for
1418 * the mapping. Architectures which can support a direct-mapped
1419 * physical to virtual region can return the appropriate address
1420 * within that region, leaving '*virt' unchanged. Other
1421 * architectures should map the pages starting at '*virt' and
1422 * update '*virt' with the first usable address after the mapped
1426 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
1428 return PHYS_TO_DMAP(start);
1432 * Add a list of wired pages to the kva
1433 * this routine is only used for temporary
1434 * kernel mappings that do not need to have
1435 * page modification or references recorded.
1436 * Note that old mappings are simply written
1437 * over. The page *must* be wired.
1438 * Note: SMP coherent. Uses a ranged shootdown IPI.
1441 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
1444 pt_entry_t *pte, pa;
1450 for (i = 0; i < count; i++) {
1451 pde = pmap_pde(kernel_pmap, va, &lvl);
1452 KASSERT(pde != NULL,
1453 ("pmap_qenter: Invalid page entry, va: 0x%lx", va));
1455 ("pmap_qenter: Invalid level %d", lvl));
1458 pa = VM_PAGE_TO_PHYS(m) | ATTR_DEFAULT |
1459 ATTR_S1_AP(ATTR_S1_AP_RW) | ATTR_S1_XN |
1460 ATTR_S1_IDX(m->md.pv_memattr) | L3_PAGE;
1461 pte = pmap_l2_to_l3(pde, va);
1462 pmap_load_store(pte, pa);
1466 pmap_invalidate_range(kernel_pmap, sva, va);
1470 * This routine tears out page mappings from the
1471 * kernel -- it is meant only for temporary mappings.
1474 pmap_qremove(vm_offset_t sva, int count)
1480 KASSERT(sva >= VM_MIN_KERNEL_ADDRESS, ("usermode va %lx", sva));
1483 while (count-- > 0) {
1484 pte = pmap_pte(kernel_pmap, va, &lvl);
1486 ("Invalid device pagetable level: %d != 3", lvl));
1493 pmap_invalidate_range(kernel_pmap, sva, va);
1496 /***************************************************
1497 * Page table page management routines.....
1498 ***************************************************/
1500 * Schedule the specified unused page table page to be freed. Specifically,
1501 * add the page to the specified list of pages that will be released to the
1502 * physical memory manager after the TLB has been updated.
1504 static __inline void
1505 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
1506 boolean_t set_PG_ZERO)
1510 m->flags |= PG_ZERO;
1512 m->flags &= ~PG_ZERO;
1513 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
1517 * Decrements a page table page's reference count, which is used to record the
1518 * number of valid page table entries within the page. If the reference count
1519 * drops to zero, then the page table page is unmapped. Returns TRUE if the
1520 * page table page was unmapped and FALSE otherwise.
1522 static inline boolean_t
1523 pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
1527 if (m->ref_count == 0) {
1528 _pmap_unwire_l3(pmap, va, m, free);
1535 _pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
1538 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1540 * unmap the page table page
1542 if (m->pindex >= (NUL2E + NUL1E)) {
1546 l0 = pmap_l0(pmap, va);
1548 } else if (m->pindex >= NUL2E) {
1552 l1 = pmap_l1(pmap, va);
1558 l2 = pmap_l2(pmap, va);
1561 pmap_resident_count_dec(pmap, 1);
1562 if (m->pindex < NUL2E) {
1563 /* We just released an l3, unhold the matching l2 */
1564 pd_entry_t *l1, tl1;
1567 l1 = pmap_l1(pmap, va);
1568 tl1 = pmap_load(l1);
1569 l2pg = PHYS_TO_VM_PAGE(tl1 & ~ATTR_MASK);
1570 pmap_unwire_l3(pmap, va, l2pg, free);
1571 } else if (m->pindex < (NUL2E + NUL1E)) {
1572 /* We just released an l2, unhold the matching l1 */
1573 pd_entry_t *l0, tl0;
1576 l0 = pmap_l0(pmap, va);
1577 tl0 = pmap_load(l0);
1578 l1pg = PHYS_TO_VM_PAGE(tl0 & ~ATTR_MASK);
1579 pmap_unwire_l3(pmap, va, l1pg, free);
1581 pmap_invalidate_page(pmap, va);
1584 * Put page on a list so that it is released after
1585 * *ALL* TLB shootdown is done
1587 pmap_add_delayed_free_list(m, free, TRUE);
1591 * After removing a page table entry, this routine is used to
1592 * conditionally free the page, and manage the reference count.
1595 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, pd_entry_t ptepde,
1596 struct spglist *free)
1600 if (va >= VM_MAXUSER_ADDRESS)
1602 KASSERT(ptepde != 0, ("pmap_unuse_pt: ptepde != 0"));
1603 mpte = PHYS_TO_VM_PAGE(ptepde & ~ATTR_MASK);
1604 return (pmap_unwire_l3(pmap, va, mpte, free));
1608 * Release a page table page reference after a failed attempt to create a
1612 pmap_abort_ptp(pmap_t pmap, vm_offset_t va, vm_page_t mpte)
1614 struct spglist free;
1617 if (pmap_unwire_l3(pmap, va, mpte, &free)) {
1619 * Although "va" was never mapped, the TLB could nonetheless
1620 * have intermediate entries that refer to the freed page
1621 * table pages. Invalidate those entries.
1623 * XXX redundant invalidation (See _pmap_unwire_l3().)
1625 pmap_invalidate_page(pmap, va);
1626 vm_page_free_pages_toq(&free, true);
1631 pmap_pinit0(pmap_t pmap)
1634 PMAP_LOCK_INIT(pmap);
1635 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats));
1636 pmap->pm_l0_paddr = READ_SPECIALREG(ttbr0_el1);
1637 pmap->pm_l0 = (pd_entry_t *)PHYS_TO_DMAP(pmap->pm_l0_paddr);
1638 pmap->pm_root.rt_root = 0;
1639 pmap->pm_cookie = COOKIE_FROM(ASID_RESERVED_FOR_PID_0, INT_MIN);
1640 pmap->pm_stage = PM_STAGE1;
1641 pmap->pm_asid_set = &asids;
1643 PCPU_SET(curpmap, pmap);
1647 pmap_pinit_stage(pmap_t pmap, enum pmap_stage stage)
1652 * allocate the l0 page
1654 while ((l0pt = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
1655 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL)
1658 pmap->pm_l0_paddr = VM_PAGE_TO_PHYS(l0pt);
1659 pmap->pm_l0 = (pd_entry_t *)PHYS_TO_DMAP(pmap->pm_l0_paddr);
1661 if ((l0pt->flags & PG_ZERO) == 0)
1662 pagezero(pmap->pm_l0);
1664 pmap->pm_root.rt_root = 0;
1665 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats));
1666 pmap->pm_cookie = COOKIE_FROM(-1, INT_MAX);
1668 pmap->pm_stage = stage;
1671 pmap->pm_asid_set = &asids;
1674 pmap->pm_asid_set = &vmids;
1677 panic("%s: Invalid pmap type %d", __func__, stage);
1681 /* XXX Temporarily disable deferred ASID allocation. */
1682 pmap_alloc_asid(pmap);
1688 pmap_pinit(pmap_t pmap)
1691 return (pmap_pinit_stage(pmap, PM_STAGE1));
1695 * This routine is called if the desired page table page does not exist.
1697 * If page table page allocation fails, this routine may sleep before
1698 * returning NULL. It sleeps only if a lock pointer was given.
1700 * Note: If a page allocation fails at page table level two or three,
1701 * one or two pages may be held during the wait, only to be released
1702 * afterwards. This conservative approach is easily argued to avoid
1706 _pmap_alloc_l3(pmap_t pmap, vm_pindex_t ptepindex, struct rwlock **lockp)
1708 vm_page_t m, l1pg, l2pg;
1710 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1713 * Allocate a page table page.
1715 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
1716 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
1717 if (lockp != NULL) {
1718 RELEASE_PV_LIST_LOCK(lockp);
1725 * Indicate the need to retry. While waiting, the page table
1726 * page may have been allocated.
1730 if ((m->flags & PG_ZERO) == 0)
1734 * Because of AArch64's weak memory consistency model, we must have a
1735 * barrier here to ensure that the stores for zeroing "m", whether by
1736 * pmap_zero_page() or an earlier function, are visible before adding
1737 * "m" to the page table. Otherwise, a page table walk by another
1738 * processor's MMU could see the mapping to "m" and a stale, non-zero
1744 * Map the pagetable page into the process address space, if
1745 * it isn't already there.
1748 if (ptepindex >= (NUL2E + NUL1E)) {
1750 vm_pindex_t l0index;
1752 l0index = ptepindex - (NUL2E + NUL1E);
1753 l0 = &pmap->pm_l0[l0index];
1754 pmap_store(l0, VM_PAGE_TO_PHYS(m) | L0_TABLE);
1755 } else if (ptepindex >= NUL2E) {
1756 vm_pindex_t l0index, l1index;
1757 pd_entry_t *l0, *l1;
1760 l1index = ptepindex - NUL2E;
1761 l0index = l1index >> L0_ENTRIES_SHIFT;
1763 l0 = &pmap->pm_l0[l0index];
1764 tl0 = pmap_load(l0);
1766 /* recurse for allocating page dir */
1767 if (_pmap_alloc_l3(pmap, NUL2E + NUL1E + l0index,
1769 vm_page_unwire_noq(m);
1770 vm_page_free_zero(m);
1774 l1pg = PHYS_TO_VM_PAGE(tl0 & ~ATTR_MASK);
1778 l1 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l0) & ~ATTR_MASK);
1779 l1 = &l1[ptepindex & Ln_ADDR_MASK];
1780 pmap_store(l1, VM_PAGE_TO_PHYS(m) | L1_TABLE);
1782 vm_pindex_t l0index, l1index;
1783 pd_entry_t *l0, *l1, *l2;
1784 pd_entry_t tl0, tl1;
1786 l1index = ptepindex >> Ln_ENTRIES_SHIFT;
1787 l0index = l1index >> L0_ENTRIES_SHIFT;
1789 l0 = &pmap->pm_l0[l0index];
1790 tl0 = pmap_load(l0);
1792 /* recurse for allocating page dir */
1793 if (_pmap_alloc_l3(pmap, NUL2E + l1index,
1795 vm_page_unwire_noq(m);
1796 vm_page_free_zero(m);
1799 tl0 = pmap_load(l0);
1800 l1 = (pd_entry_t *)PHYS_TO_DMAP(tl0 & ~ATTR_MASK);
1801 l1 = &l1[l1index & Ln_ADDR_MASK];
1803 l1 = (pd_entry_t *)PHYS_TO_DMAP(tl0 & ~ATTR_MASK);
1804 l1 = &l1[l1index & Ln_ADDR_MASK];
1805 tl1 = pmap_load(l1);
1807 /* recurse for allocating page dir */
1808 if (_pmap_alloc_l3(pmap, NUL2E + l1index,
1810 vm_page_unwire_noq(m);
1811 vm_page_free_zero(m);
1815 l2pg = PHYS_TO_VM_PAGE(tl1 & ~ATTR_MASK);
1820 l2 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l1) & ~ATTR_MASK);
1821 l2 = &l2[ptepindex & Ln_ADDR_MASK];
1822 pmap_store(l2, VM_PAGE_TO_PHYS(m) | L2_TABLE);
1825 pmap_resident_count_inc(pmap, 1);
1831 pmap_alloc_l2(pmap_t pmap, vm_offset_t va, vm_page_t *l2pgp,
1832 struct rwlock **lockp)
1834 pd_entry_t *l1, *l2;
1836 vm_pindex_t l2pindex;
1839 l1 = pmap_l1(pmap, va);
1840 if (l1 != NULL && (pmap_load(l1) & ATTR_DESCR_MASK) == L1_TABLE) {
1841 l2 = pmap_l1_to_l2(l1, va);
1842 if (va < VM_MAXUSER_ADDRESS) {
1843 /* Add a reference to the L2 page. */
1844 l2pg = PHYS_TO_VM_PAGE(pmap_load(l1) & ~ATTR_MASK);
1848 } else if (va < VM_MAXUSER_ADDRESS) {
1849 /* Allocate a L2 page. */
1850 l2pindex = pmap_l2_pindex(va) >> Ln_ENTRIES_SHIFT;
1851 l2pg = _pmap_alloc_l3(pmap, NUL2E + l2pindex, lockp);
1858 l2 = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(l2pg));
1859 l2 = &l2[pmap_l2_index(va)];
1861 panic("pmap_alloc_l2: missing page table page for va %#lx",
1868 pmap_alloc_l3(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
1870 vm_pindex_t ptepindex;
1871 pd_entry_t *pde, tpde;
1879 * Calculate pagetable page index
1881 ptepindex = pmap_l2_pindex(va);
1884 * Get the page directory entry
1886 pde = pmap_pde(pmap, va, &lvl);
1889 * If the page table page is mapped, we just increment the hold count,
1890 * and activate it. If we get a level 2 pde it will point to a level 3
1898 pte = pmap_l0_to_l1(pde, va);
1899 KASSERT(pmap_load(pte) == 0,
1900 ("pmap_alloc_l3: TODO: l0 superpages"));
1905 pte = pmap_l1_to_l2(pde, va);
1906 KASSERT(pmap_load(pte) == 0,
1907 ("pmap_alloc_l3: TODO: l1 superpages"));
1911 tpde = pmap_load(pde);
1913 m = PHYS_TO_VM_PAGE(tpde & ~ATTR_MASK);
1919 panic("pmap_alloc_l3: Invalid level %d", lvl);
1923 * Here if the pte page isn't mapped, or if it has been deallocated.
1925 m = _pmap_alloc_l3(pmap, ptepindex, lockp);
1926 if (m == NULL && lockp != NULL)
1932 /***************************************************
1933 * Pmap allocation/deallocation routines.
1934 ***************************************************/
1937 * Release any resources held by the given physical map.
1938 * Called when a pmap initialized by pmap_pinit is being released.
1939 * Should only be called if the map contains no valid mappings.
1942 pmap_release(pmap_t pmap)
1944 struct asid_set *set;
1948 KASSERT(pmap->pm_stats.resident_count == 0,
1949 ("pmap_release: pmap resident count %ld != 0",
1950 pmap->pm_stats.resident_count));
1951 KASSERT(vm_radix_is_empty(&pmap->pm_root),
1952 ("pmap_release: pmap has reserved page table page(s)"));
1954 set = pmap->pm_asid_set;
1955 KASSERT(set != NULL, ("%s: NULL asid set", __func__));
1958 * Allow the ASID to be reused. In stage 2 VMIDs we don't invalidate
1959 * the entries when removing them so rely on a later tlb invalidation.
1960 * this will happen when updating the VMID generation. Because of this
1961 * we don't reuse VMIDs within a generation.
1963 if (pmap->pm_stage == PM_STAGE1) {
1964 mtx_lock_spin(&set->asid_set_mutex);
1965 if (COOKIE_TO_EPOCH(pmap->pm_cookie) == set->asid_epoch) {
1966 asid = COOKIE_TO_ASID(pmap->pm_cookie);
1967 KASSERT(asid >= ASID_FIRST_AVAILABLE &&
1968 asid < set->asid_set_size,
1969 ("pmap_release: pmap cookie has out-of-range asid"));
1970 bit_clear(set->asid_set, asid);
1972 mtx_unlock_spin(&set->asid_set_mutex);
1975 m = PHYS_TO_VM_PAGE(pmap->pm_l0_paddr);
1976 vm_page_unwire_noq(m);
1977 vm_page_free_zero(m);
1981 kvm_size(SYSCTL_HANDLER_ARGS)
1983 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS;
1985 return sysctl_handle_long(oidp, &ksize, 0, req);
1987 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG | CTLFLAG_RD | CTLFLAG_MPSAFE,
1988 0, 0, kvm_size, "LU",
1992 kvm_free(SYSCTL_HANDLER_ARGS)
1994 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
1996 return sysctl_handle_long(oidp, &kfree, 0, req);
1998 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG | CTLFLAG_RD | CTLFLAG_MPSAFE,
1999 0, 0, kvm_free, "LU",
2000 "Amount of KVM free");
2003 * grow the number of kernel page table entries, if needed
2006 pmap_growkernel(vm_offset_t addr)
2010 pd_entry_t *l0, *l1, *l2;
2012 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
2014 addr = roundup2(addr, L2_SIZE);
2015 if (addr - 1 >= vm_map_max(kernel_map))
2016 addr = vm_map_max(kernel_map);
2017 while (kernel_vm_end < addr) {
2018 l0 = pmap_l0(kernel_pmap, kernel_vm_end);
2019 KASSERT(pmap_load(l0) != 0,
2020 ("pmap_growkernel: No level 0 kernel entry"));
2022 l1 = pmap_l0_to_l1(l0, kernel_vm_end);
2023 if (pmap_load(l1) == 0) {
2024 /* We need a new PDP entry */
2025 nkpg = vm_page_alloc(NULL, kernel_vm_end >> L1_SHIFT,
2026 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ |
2027 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
2029 panic("pmap_growkernel: no memory to grow kernel");
2030 if ((nkpg->flags & PG_ZERO) == 0)
2031 pmap_zero_page(nkpg);
2032 /* See the dmb() in _pmap_alloc_l3(). */
2034 paddr = VM_PAGE_TO_PHYS(nkpg);
2035 pmap_store(l1, paddr | L1_TABLE);
2036 continue; /* try again */
2038 l2 = pmap_l1_to_l2(l1, kernel_vm_end);
2039 if (pmap_load(l2) != 0) {
2040 kernel_vm_end = (kernel_vm_end + L2_SIZE) & ~L2_OFFSET;
2041 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
2042 kernel_vm_end = vm_map_max(kernel_map);
2048 nkpg = vm_page_alloc(NULL, kernel_vm_end >> L2_SHIFT,
2049 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
2052 panic("pmap_growkernel: no memory to grow kernel");
2053 if ((nkpg->flags & PG_ZERO) == 0)
2054 pmap_zero_page(nkpg);
2055 /* See the dmb() in _pmap_alloc_l3(). */
2057 paddr = VM_PAGE_TO_PHYS(nkpg);
2058 pmap_store(l2, paddr | L2_TABLE);
2060 kernel_vm_end = (kernel_vm_end + L2_SIZE) & ~L2_OFFSET;
2061 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
2062 kernel_vm_end = vm_map_max(kernel_map);
2068 /***************************************************
2069 * page management routines.
2070 ***************************************************/
2072 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
2073 CTASSERT(_NPCM == 3);
2074 CTASSERT(_NPCPV == 168);
2076 static __inline struct pv_chunk *
2077 pv_to_chunk(pv_entry_t pv)
2080 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
2083 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
2085 #define PC_FREE0 0xfffffffffffffffful
2086 #define PC_FREE1 0xfffffffffffffffful
2087 #define PC_FREE2 0x000000fffffffffful
2089 static const uint64_t pc_freemask[_NPCM] = { PC_FREE0, PC_FREE1, PC_FREE2 };
2093 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
2095 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
2096 "Current number of pv entry chunks");
2097 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
2098 "Current number of pv entry chunks allocated");
2099 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
2100 "Current number of pv entry chunks frees");
2101 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
2102 "Number of times tried to get a chunk page but failed.");
2104 static long pv_entry_frees, pv_entry_allocs, pv_entry_count;
2105 static int pv_entry_spare;
2107 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
2108 "Current number of pv entry frees");
2109 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
2110 "Current number of pv entry allocs");
2111 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
2112 "Current number of pv entries");
2113 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
2114 "Current number of spare pv entries");
2119 * We are in a serious low memory condition. Resort to
2120 * drastic measures to free some pages so we can allocate
2121 * another pv entry chunk.
2123 * Returns NULL if PV entries were reclaimed from the specified pmap.
2125 * We do not, however, unmap 2mpages because subsequent accesses will
2126 * allocate per-page pv entries until repromotion occurs, thereby
2127 * exacerbating the shortage of free pv entries.
2130 reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp)
2132 struct pv_chunk *pc, *pc_marker, *pc_marker_end;
2133 struct pv_chunk_header pc_marker_b, pc_marker_end_b;
2134 struct md_page *pvh;
2136 pmap_t next_pmap, pmap;
2137 pt_entry_t *pte, tpte;
2141 struct spglist free;
2143 int bit, field, freed, lvl;
2144 static int active_reclaims = 0;
2146 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
2147 KASSERT(lockp != NULL, ("reclaim_pv_chunk: lockp is NULL"));
2152 bzero(&pc_marker_b, sizeof(pc_marker_b));
2153 bzero(&pc_marker_end_b, sizeof(pc_marker_end_b));
2154 pc_marker = (struct pv_chunk *)&pc_marker_b;
2155 pc_marker_end = (struct pv_chunk *)&pc_marker_end_b;
2157 mtx_lock(&pv_chunks_mutex);
2159 TAILQ_INSERT_HEAD(&pv_chunks, pc_marker, pc_lru);
2160 TAILQ_INSERT_TAIL(&pv_chunks, pc_marker_end, pc_lru);
2161 while ((pc = TAILQ_NEXT(pc_marker, pc_lru)) != pc_marker_end &&
2162 SLIST_EMPTY(&free)) {
2163 next_pmap = pc->pc_pmap;
2164 if (next_pmap == NULL) {
2166 * The next chunk is a marker. However, it is
2167 * not our marker, so active_reclaims must be
2168 * > 1. Consequently, the next_chunk code
2169 * will not rotate the pv_chunks list.
2173 mtx_unlock(&pv_chunks_mutex);
2176 * A pv_chunk can only be removed from the pc_lru list
2177 * when both pv_chunks_mutex is owned and the
2178 * corresponding pmap is locked.
2180 if (pmap != next_pmap) {
2181 if (pmap != NULL && pmap != locked_pmap)
2184 /* Avoid deadlock and lock recursion. */
2185 if (pmap > locked_pmap) {
2186 RELEASE_PV_LIST_LOCK(lockp);
2188 mtx_lock(&pv_chunks_mutex);
2190 } else if (pmap != locked_pmap) {
2191 if (PMAP_TRYLOCK(pmap)) {
2192 mtx_lock(&pv_chunks_mutex);
2195 pmap = NULL; /* pmap is not locked */
2196 mtx_lock(&pv_chunks_mutex);
2197 pc = TAILQ_NEXT(pc_marker, pc_lru);
2199 pc->pc_pmap != next_pmap)
2207 * Destroy every non-wired, 4 KB page mapping in the chunk.
2210 for (field = 0; field < _NPCM; field++) {
2211 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
2212 inuse != 0; inuse &= ~(1UL << bit)) {
2213 bit = ffsl(inuse) - 1;
2214 pv = &pc->pc_pventry[field * 64 + bit];
2216 pde = pmap_pde(pmap, va, &lvl);
2219 pte = pmap_l2_to_l3(pde, va);
2220 tpte = pmap_load(pte);
2221 if ((tpte & ATTR_SW_WIRED) != 0)
2223 tpte = pmap_load_clear(pte);
2224 m = PHYS_TO_VM_PAGE(tpte & ~ATTR_MASK);
2225 if (pmap_pte_dirty(pmap, tpte))
2227 if ((tpte & ATTR_AF) != 0) {
2228 pmap_invalidate_page(pmap, va);
2229 vm_page_aflag_set(m, PGA_REFERENCED);
2231 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
2232 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
2234 if (TAILQ_EMPTY(&m->md.pv_list) &&
2235 (m->flags & PG_FICTITIOUS) == 0) {
2236 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2237 if (TAILQ_EMPTY(&pvh->pv_list)) {
2238 vm_page_aflag_clear(m,
2242 pc->pc_map[field] |= 1UL << bit;
2243 pmap_unuse_pt(pmap, va, pmap_load(pde), &free);
2248 mtx_lock(&pv_chunks_mutex);
2251 /* Every freed mapping is for a 4 KB page. */
2252 pmap_resident_count_dec(pmap, freed);
2253 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
2254 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
2255 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
2256 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2257 if (pc->pc_map[0] == PC_FREE0 && pc->pc_map[1] == PC_FREE1 &&
2258 pc->pc_map[2] == PC_FREE2) {
2259 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
2260 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
2261 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
2262 /* Entire chunk is free; return it. */
2263 m_pc = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
2264 dump_drop_page(m_pc->phys_addr);
2265 mtx_lock(&pv_chunks_mutex);
2266 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2269 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2270 mtx_lock(&pv_chunks_mutex);
2271 /* One freed pv entry in locked_pmap is sufficient. */
2272 if (pmap == locked_pmap)
2276 TAILQ_REMOVE(&pv_chunks, pc_marker, pc_lru);
2277 TAILQ_INSERT_AFTER(&pv_chunks, pc, pc_marker, pc_lru);
2278 if (active_reclaims == 1 && pmap != NULL) {
2280 * Rotate the pv chunks list so that we do not
2281 * scan the same pv chunks that could not be
2282 * freed (because they contained a wired
2283 * and/or superpage mapping) on every
2284 * invocation of reclaim_pv_chunk().
2286 while ((pc = TAILQ_FIRST(&pv_chunks)) != pc_marker) {
2287 MPASS(pc->pc_pmap != NULL);
2288 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2289 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
2293 TAILQ_REMOVE(&pv_chunks, pc_marker, pc_lru);
2294 TAILQ_REMOVE(&pv_chunks, pc_marker_end, pc_lru);
2296 mtx_unlock(&pv_chunks_mutex);
2297 if (pmap != NULL && pmap != locked_pmap)
2299 if (m_pc == NULL && !SLIST_EMPTY(&free)) {
2300 m_pc = SLIST_FIRST(&free);
2301 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
2302 /* Recycle a freed page table page. */
2303 m_pc->ref_count = 1;
2305 vm_page_free_pages_toq(&free, true);
2310 * free the pv_entry back to the free list
2313 free_pv_entry(pmap_t pmap, pv_entry_t pv)
2315 struct pv_chunk *pc;
2316 int idx, field, bit;
2318 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2319 PV_STAT(atomic_add_long(&pv_entry_frees, 1));
2320 PV_STAT(atomic_add_int(&pv_entry_spare, 1));
2321 PV_STAT(atomic_subtract_long(&pv_entry_count, 1));
2322 pc = pv_to_chunk(pv);
2323 idx = pv - &pc->pc_pventry[0];
2326 pc->pc_map[field] |= 1ul << bit;
2327 if (pc->pc_map[0] != PC_FREE0 || pc->pc_map[1] != PC_FREE1 ||
2328 pc->pc_map[2] != PC_FREE2) {
2329 /* 98% of the time, pc is already at the head of the list. */
2330 if (__predict_false(pc != TAILQ_FIRST(&pmap->pm_pvchunk))) {
2331 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2332 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2336 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2341 free_pv_chunk(struct pv_chunk *pc)
2345 mtx_lock(&pv_chunks_mutex);
2346 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2347 mtx_unlock(&pv_chunks_mutex);
2348 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
2349 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
2350 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
2351 /* entire chunk is free, return it */
2352 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
2353 dump_drop_page(m->phys_addr);
2354 vm_page_unwire_noq(m);
2359 * Returns a new PV entry, allocating a new PV chunk from the system when
2360 * needed. If this PV chunk allocation fails and a PV list lock pointer was
2361 * given, a PV chunk is reclaimed from an arbitrary pmap. Otherwise, NULL is
2364 * The given PV list lock may be released.
2367 get_pv_entry(pmap_t pmap, struct rwlock **lockp)
2371 struct pv_chunk *pc;
2374 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2375 PV_STAT(atomic_add_long(&pv_entry_allocs, 1));
2377 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2379 for (field = 0; field < _NPCM; field++) {
2380 if (pc->pc_map[field]) {
2381 bit = ffsl(pc->pc_map[field]) - 1;
2385 if (field < _NPCM) {
2386 pv = &pc->pc_pventry[field * 64 + bit];
2387 pc->pc_map[field] &= ~(1ul << bit);
2388 /* If this was the last item, move it to tail */
2389 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 &&
2390 pc->pc_map[2] == 0) {
2391 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2392 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc,
2395 PV_STAT(atomic_add_long(&pv_entry_count, 1));
2396 PV_STAT(atomic_subtract_int(&pv_entry_spare, 1));
2400 /* No free items, allocate another chunk */
2401 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
2404 if (lockp == NULL) {
2405 PV_STAT(pc_chunk_tryfail++);
2408 m = reclaim_pv_chunk(pmap, lockp);
2412 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
2413 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
2414 dump_add_page(m->phys_addr);
2415 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
2417 pc->pc_map[0] = PC_FREE0 & ~1ul; /* preallocated bit 0 */
2418 pc->pc_map[1] = PC_FREE1;
2419 pc->pc_map[2] = PC_FREE2;
2420 mtx_lock(&pv_chunks_mutex);
2421 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
2422 mtx_unlock(&pv_chunks_mutex);
2423 pv = &pc->pc_pventry[0];
2424 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2425 PV_STAT(atomic_add_long(&pv_entry_count, 1));
2426 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV - 1));
2431 * Ensure that the number of spare PV entries in the specified pmap meets or
2432 * exceeds the given count, "needed".
2434 * The given PV list lock may be released.
2437 reserve_pv_entries(pmap_t pmap, int needed, struct rwlock **lockp)
2439 struct pch new_tail;
2440 struct pv_chunk *pc;
2445 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2446 KASSERT(lockp != NULL, ("reserve_pv_entries: lockp is NULL"));
2449 * Newly allocated PV chunks must be stored in a private list until
2450 * the required number of PV chunks have been allocated. Otherwise,
2451 * reclaim_pv_chunk() could recycle one of these chunks. In
2452 * contrast, these chunks must be added to the pmap upon allocation.
2454 TAILQ_INIT(&new_tail);
2457 TAILQ_FOREACH(pc, &pmap->pm_pvchunk, pc_list) {
2458 bit_count((bitstr_t *)pc->pc_map, 0,
2459 sizeof(pc->pc_map) * NBBY, &free);
2463 if (avail >= needed)
2466 for (reclaimed = false; avail < needed; avail += _NPCPV) {
2467 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
2470 m = reclaim_pv_chunk(pmap, lockp);
2475 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
2476 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
2477 dump_add_page(m->phys_addr);
2478 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
2480 pc->pc_map[0] = PC_FREE0;
2481 pc->pc_map[1] = PC_FREE1;
2482 pc->pc_map[2] = PC_FREE2;
2483 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2484 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
2485 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV));
2488 * The reclaim might have freed a chunk from the current pmap.
2489 * If that chunk contained available entries, we need to
2490 * re-count the number of available entries.
2495 if (!TAILQ_EMPTY(&new_tail)) {
2496 mtx_lock(&pv_chunks_mutex);
2497 TAILQ_CONCAT(&pv_chunks, &new_tail, pc_lru);
2498 mtx_unlock(&pv_chunks_mutex);
2503 * First find and then remove the pv entry for the specified pmap and virtual
2504 * address from the specified pv list. Returns the pv entry if found and NULL
2505 * otherwise. This operation can be performed on pv lists for either 4KB or
2506 * 2MB page mappings.
2508 static __inline pv_entry_t
2509 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2513 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
2514 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
2515 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
2524 * After demotion from a 2MB page mapping to 512 4KB page mappings,
2525 * destroy the pv entry for the 2MB page mapping and reinstantiate the pv
2526 * entries for each of the 4KB page mappings.
2529 pmap_pv_demote_l2(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
2530 struct rwlock **lockp)
2532 struct md_page *pvh;
2533 struct pv_chunk *pc;
2535 vm_offset_t va_last;
2539 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2540 KASSERT((va & L2_OFFSET) == 0,
2541 ("pmap_pv_demote_l2: va is not 2mpage aligned"));
2542 KASSERT((pa & L2_OFFSET) == 0,
2543 ("pmap_pv_demote_l2: pa is not 2mpage aligned"));
2544 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
2547 * Transfer the 2mpage's pv entry for this mapping to the first
2548 * page's pv list. Once this transfer begins, the pv list lock
2549 * must not be released until the last pv entry is reinstantiated.
2551 pvh = pa_to_pvh(pa);
2552 pv = pmap_pvh_remove(pvh, pmap, va);
2553 KASSERT(pv != NULL, ("pmap_pv_demote_l2: pv not found"));
2554 m = PHYS_TO_VM_PAGE(pa);
2555 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2557 /* Instantiate the remaining Ln_ENTRIES - 1 pv entries. */
2558 PV_STAT(atomic_add_long(&pv_entry_allocs, Ln_ENTRIES - 1));
2559 va_last = va + L2_SIZE - PAGE_SIZE;
2561 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2562 KASSERT(pc->pc_map[0] != 0 || pc->pc_map[1] != 0 ||
2563 pc->pc_map[2] != 0, ("pmap_pv_demote_l2: missing spare"));
2564 for (field = 0; field < _NPCM; field++) {
2565 while (pc->pc_map[field]) {
2566 bit = ffsl(pc->pc_map[field]) - 1;
2567 pc->pc_map[field] &= ~(1ul << bit);
2568 pv = &pc->pc_pventry[field * 64 + bit];
2572 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2573 ("pmap_pv_demote_l2: page %p is not managed", m));
2574 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2580 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2581 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2584 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 && pc->pc_map[2] == 0) {
2585 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2586 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2588 PV_STAT(atomic_add_long(&pv_entry_count, Ln_ENTRIES - 1));
2589 PV_STAT(atomic_subtract_int(&pv_entry_spare, Ln_ENTRIES - 1));
2593 * First find and then destroy the pv entry for the specified pmap and virtual
2594 * address. This operation can be performed on pv lists for either 4KB or 2MB
2598 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2602 pv = pmap_pvh_remove(pvh, pmap, va);
2603 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
2604 free_pv_entry(pmap, pv);
2608 * Conditionally create the PV entry for a 4KB page mapping if the required
2609 * memory can be allocated without resorting to reclamation.
2612 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m,
2613 struct rwlock **lockp)
2617 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2618 /* Pass NULL instead of the lock pointer to disable reclamation. */
2619 if ((pv = get_pv_entry(pmap, NULL)) != NULL) {
2621 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
2622 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2630 * Create the PV entry for a 2MB page mapping. Always returns true unless the
2631 * flag PMAP_ENTER_NORECLAIM is specified. If that flag is specified, returns
2632 * false if the PV entry cannot be allocated without resorting to reclamation.
2635 pmap_pv_insert_l2(pmap_t pmap, vm_offset_t va, pd_entry_t l2e, u_int flags,
2636 struct rwlock **lockp)
2638 struct md_page *pvh;
2642 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2643 /* Pass NULL instead of the lock pointer to disable reclamation. */
2644 if ((pv = get_pv_entry(pmap, (flags & PMAP_ENTER_NORECLAIM) != 0 ?
2645 NULL : lockp)) == NULL)
2648 pa = l2e & ~ATTR_MASK;
2649 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
2650 pvh = pa_to_pvh(pa);
2651 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2657 pmap_remove_kernel_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t va)
2659 pt_entry_t newl2, oldl2;
2663 KASSERT(!VIRT_IN_DMAP(va), ("removing direct mapping of %#lx", va));
2664 KASSERT(pmap == kernel_pmap, ("pmap %p is not kernel_pmap", pmap));
2665 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2667 ml3 = pmap_remove_pt_page(pmap, va);
2669 panic("pmap_remove_kernel_l2: Missing pt page");
2671 ml3pa = VM_PAGE_TO_PHYS(ml3);
2672 newl2 = ml3pa | L2_TABLE;
2675 * If this page table page was unmapped by a promotion, then it
2676 * contains valid mappings. Zero it to invalidate those mappings.
2678 if (ml3->valid != 0)
2679 pagezero((void *)PHYS_TO_DMAP(ml3pa));
2682 * Demote the mapping. The caller must have already invalidated the
2683 * mapping (i.e., the "break" in break-before-make).
2685 oldl2 = pmap_load_store(l2, newl2);
2686 KASSERT(oldl2 == 0, ("%s: found existing mapping at %p: %#lx",
2687 __func__, l2, oldl2));
2691 * pmap_remove_l2: Do the things to unmap a level 2 superpage.
2694 pmap_remove_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t sva,
2695 pd_entry_t l1e, struct spglist *free, struct rwlock **lockp)
2697 struct md_page *pvh;
2699 vm_offset_t eva, va;
2702 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2703 KASSERT((sva & L2_OFFSET) == 0, ("pmap_remove_l2: sva is not aligned"));
2704 old_l2 = pmap_load_clear(l2);
2705 KASSERT((old_l2 & ATTR_DESCR_MASK) == L2_BLOCK,
2706 ("pmap_remove_l2: L2e %lx is not a block mapping", old_l2));
2709 * Since a promotion must break the 4KB page mappings before making
2710 * the 2MB page mapping, a pmap_invalidate_page() suffices.
2712 pmap_invalidate_page(pmap, sva);
2714 if (old_l2 & ATTR_SW_WIRED)
2715 pmap->pm_stats.wired_count -= L2_SIZE / PAGE_SIZE;
2716 pmap_resident_count_dec(pmap, L2_SIZE / PAGE_SIZE);
2717 if (old_l2 & ATTR_SW_MANAGED) {
2718 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, old_l2 & ~ATTR_MASK);
2719 pvh = pa_to_pvh(old_l2 & ~ATTR_MASK);
2720 pmap_pvh_free(pvh, pmap, sva);
2721 eva = sva + L2_SIZE;
2722 for (va = sva, m = PHYS_TO_VM_PAGE(old_l2 & ~ATTR_MASK);
2723 va < eva; va += PAGE_SIZE, m++) {
2724 if (pmap_pte_dirty(pmap, old_l2))
2726 if (old_l2 & ATTR_AF)
2727 vm_page_aflag_set(m, PGA_REFERENCED);
2728 if (TAILQ_EMPTY(&m->md.pv_list) &&
2729 TAILQ_EMPTY(&pvh->pv_list))
2730 vm_page_aflag_clear(m, PGA_WRITEABLE);
2733 if (pmap == kernel_pmap) {
2734 pmap_remove_kernel_l2(pmap, l2, sva);
2736 ml3 = pmap_remove_pt_page(pmap, sva);
2738 KASSERT(ml3->valid == VM_PAGE_BITS_ALL,
2739 ("pmap_remove_l2: l3 page not promoted"));
2740 pmap_resident_count_dec(pmap, 1);
2741 KASSERT(ml3->ref_count == NL3PG,
2742 ("pmap_remove_l2: l3 page ref count error"));
2744 pmap_add_delayed_free_list(ml3, free, FALSE);
2747 return (pmap_unuse_pt(pmap, sva, l1e, free));
2751 * pmap_remove_l3: do the things to unmap a page in a process
2754 pmap_remove_l3(pmap_t pmap, pt_entry_t *l3, vm_offset_t va,
2755 pd_entry_t l2e, struct spglist *free, struct rwlock **lockp)
2757 struct md_page *pvh;
2761 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2762 old_l3 = pmap_load_clear(l3);
2763 pmap_invalidate_page(pmap, va);
2764 if (old_l3 & ATTR_SW_WIRED)
2765 pmap->pm_stats.wired_count -= 1;
2766 pmap_resident_count_dec(pmap, 1);
2767 if (old_l3 & ATTR_SW_MANAGED) {
2768 m = PHYS_TO_VM_PAGE(old_l3 & ~ATTR_MASK);
2769 if (pmap_pte_dirty(pmap, old_l3))
2771 if (old_l3 & ATTR_AF)
2772 vm_page_aflag_set(m, PGA_REFERENCED);
2773 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
2774 pmap_pvh_free(&m->md, pmap, va);
2775 if (TAILQ_EMPTY(&m->md.pv_list) &&
2776 (m->flags & PG_FICTITIOUS) == 0) {
2777 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2778 if (TAILQ_EMPTY(&pvh->pv_list))
2779 vm_page_aflag_clear(m, PGA_WRITEABLE);
2782 return (pmap_unuse_pt(pmap, va, l2e, free));
2786 * Remove the specified range of addresses from the L3 page table that is
2787 * identified by the given L2 entry.
2790 pmap_remove_l3_range(pmap_t pmap, pd_entry_t l2e, vm_offset_t sva,
2791 vm_offset_t eva, struct spglist *free, struct rwlock **lockp)
2793 struct md_page *pvh;
2794 struct rwlock *new_lock;
2795 pt_entry_t *l3, old_l3;
2799 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2800 KASSERT(rounddown2(sva, L2_SIZE) + L2_SIZE == roundup2(eva, L2_SIZE),
2801 ("pmap_remove_l3_range: range crosses an L3 page table boundary"));
2802 l3pg = sva < VM_MAXUSER_ADDRESS ? PHYS_TO_VM_PAGE(l2e & ~ATTR_MASK) :
2805 for (l3 = pmap_l2_to_l3(&l2e, sva); sva != eva; l3++, sva += L3_SIZE) {
2806 if (!pmap_l3_valid(pmap_load(l3))) {
2808 pmap_invalidate_range(pmap, va, sva);
2813 old_l3 = pmap_load_clear(l3);
2814 if ((old_l3 & ATTR_SW_WIRED) != 0)
2815 pmap->pm_stats.wired_count--;
2816 pmap_resident_count_dec(pmap, 1);
2817 if ((old_l3 & ATTR_SW_MANAGED) != 0) {
2818 m = PHYS_TO_VM_PAGE(old_l3 & ~ATTR_MASK);
2819 if (pmap_pte_dirty(pmap, old_l3))
2821 if ((old_l3 & ATTR_AF) != 0)
2822 vm_page_aflag_set(m, PGA_REFERENCED);
2823 new_lock = PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m));
2824 if (new_lock != *lockp) {
2825 if (*lockp != NULL) {
2827 * Pending TLB invalidations must be
2828 * performed before the PV list lock is
2829 * released. Otherwise, a concurrent
2830 * pmap_remove_all() on a physical page
2831 * could return while a stale TLB entry
2832 * still provides access to that page.
2835 pmap_invalidate_range(pmap, va,
2844 pmap_pvh_free(&m->md, pmap, sva);
2845 if (TAILQ_EMPTY(&m->md.pv_list) &&
2846 (m->flags & PG_FICTITIOUS) == 0) {
2847 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2848 if (TAILQ_EMPTY(&pvh->pv_list))
2849 vm_page_aflag_clear(m, PGA_WRITEABLE);
2854 if (l3pg != NULL && pmap_unwire_l3(pmap, sva, l3pg, free)) {
2860 pmap_invalidate_range(pmap, va, sva);
2864 * Remove the given range of addresses from the specified map.
2866 * It is assumed that the start and end are properly
2867 * rounded to the page size.
2870 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2872 struct rwlock *lock;
2873 vm_offset_t va_next;
2874 pd_entry_t *l0, *l1, *l2;
2875 pt_entry_t l3_paddr;
2876 struct spglist free;
2879 * Perform an unsynchronized read. This is, however, safe.
2881 if (pmap->pm_stats.resident_count == 0)
2889 for (; sva < eva; sva = va_next) {
2890 if (pmap->pm_stats.resident_count == 0)
2893 l0 = pmap_l0(pmap, sva);
2894 if (pmap_load(l0) == 0) {
2895 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
2901 l1 = pmap_l0_to_l1(l0, sva);
2902 if (pmap_load(l1) == 0) {
2903 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
2910 * Calculate index for next page table.
2912 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
2916 l2 = pmap_l1_to_l2(l1, sva);
2920 l3_paddr = pmap_load(l2);
2922 if ((l3_paddr & ATTR_DESCR_MASK) == L2_BLOCK) {
2923 if (sva + L2_SIZE == va_next && eva >= va_next) {
2924 pmap_remove_l2(pmap, l2, sva, pmap_load(l1),
2927 } else if (pmap_demote_l2_locked(pmap, l2, sva,
2930 l3_paddr = pmap_load(l2);
2934 * Weed out invalid mappings.
2936 if ((l3_paddr & ATTR_DESCR_MASK) != L2_TABLE)
2940 * Limit our scan to either the end of the va represented
2941 * by the current page table page, or to the end of the
2942 * range being removed.
2947 pmap_remove_l3_range(pmap, l3_paddr, sva, va_next, &free,
2953 vm_page_free_pages_toq(&free, true);
2957 * Routine: pmap_remove_all
2959 * Removes this physical page from
2960 * all physical maps in which it resides.
2961 * Reflects back modify bits to the pager.
2964 * Original versions of this routine were very
2965 * inefficient because they iteratively called
2966 * pmap_remove (slow...)
2970 pmap_remove_all(vm_page_t m)
2972 struct md_page *pvh;
2975 struct rwlock *lock;
2976 pd_entry_t *pde, tpde;
2977 pt_entry_t *pte, tpte;
2979 struct spglist free;
2980 int lvl, pvh_gen, md_gen;
2982 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2983 ("pmap_remove_all: page %p is not managed", m));
2985 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
2986 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
2987 pa_to_pvh(VM_PAGE_TO_PHYS(m));
2990 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
2992 if (!PMAP_TRYLOCK(pmap)) {
2993 pvh_gen = pvh->pv_gen;
2997 if (pvh_gen != pvh->pv_gen) {
3004 pte = pmap_pte(pmap, va, &lvl);
3005 KASSERT(pte != NULL,
3006 ("pmap_remove_all: no page table entry found"));
3008 ("pmap_remove_all: invalid pte level %d", lvl));
3010 pmap_demote_l2_locked(pmap, pte, va, &lock);
3013 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
3015 PMAP_ASSERT_STAGE1(pmap);
3016 if (!PMAP_TRYLOCK(pmap)) {
3017 pvh_gen = pvh->pv_gen;
3018 md_gen = m->md.pv_gen;
3022 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
3028 pmap_resident_count_dec(pmap, 1);
3030 pde = pmap_pde(pmap, pv->pv_va, &lvl);
3031 KASSERT(pde != NULL,
3032 ("pmap_remove_all: no page directory entry found"));
3034 ("pmap_remove_all: invalid pde level %d", lvl));
3035 tpde = pmap_load(pde);
3037 pte = pmap_l2_to_l3(pde, pv->pv_va);
3038 tpte = pmap_load_clear(pte);
3039 if (tpte & ATTR_SW_WIRED)
3040 pmap->pm_stats.wired_count--;
3041 if ((tpte & ATTR_AF) != 0) {
3042 pmap_invalidate_page(pmap, pv->pv_va);
3043 vm_page_aflag_set(m, PGA_REFERENCED);
3047 * Update the vm_page_t clean and reference bits.
3049 if (pmap_pte_dirty(pmap, tpte))
3051 pmap_unuse_pt(pmap, pv->pv_va, tpde, &free);
3052 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
3054 free_pv_entry(pmap, pv);
3057 vm_page_aflag_clear(m, PGA_WRITEABLE);
3059 vm_page_free_pages_toq(&free, true);
3063 * pmap_protect_l2: do the things to protect a 2MB page in a pmap
3066 pmap_protect_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t sva, pt_entry_t mask,
3072 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3073 PMAP_ASSERT_STAGE1(pmap);
3074 KASSERT((sva & L2_OFFSET) == 0,
3075 ("pmap_protect_l2: sva is not 2mpage aligned"));
3076 old_l2 = pmap_load(l2);
3077 KASSERT((old_l2 & ATTR_DESCR_MASK) == L2_BLOCK,
3078 ("pmap_protect_l2: L2e %lx is not a block mapping", old_l2));
3081 * Return if the L2 entry already has the desired access restrictions
3085 if ((old_l2 & mask) == nbits)
3089 * When a dirty read/write superpage mapping is write protected,
3090 * update the dirty field of each of the superpage's constituent 4KB
3093 if ((old_l2 & ATTR_SW_MANAGED) != 0 &&
3094 (nbits & ATTR_S1_AP(ATTR_S1_AP_RO)) != 0 &&
3095 pmap_pte_dirty(pmap, old_l2)) {
3096 m = PHYS_TO_VM_PAGE(old_l2 & ~ATTR_MASK);
3097 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
3101 if (!atomic_fcmpset_64(l2, &old_l2, (old_l2 & ~mask) | nbits))
3105 * Since a promotion must break the 4KB page mappings before making
3106 * the 2MB page mapping, a pmap_invalidate_page() suffices.
3108 pmap_invalidate_page(pmap, sva);
3112 * Set the physical protection on the
3113 * specified range of this map as requested.
3116 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
3118 vm_offset_t va, va_next;
3119 pd_entry_t *l0, *l1, *l2;
3120 pt_entry_t *l3p, l3, mask, nbits;
3122 PMAP_ASSERT_STAGE1(pmap);
3123 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
3124 if (prot == VM_PROT_NONE) {
3125 pmap_remove(pmap, sva, eva);
3130 if ((prot & VM_PROT_WRITE) == 0) {
3131 mask |= ATTR_S1_AP_RW_BIT | ATTR_SW_DBM;
3132 nbits |= ATTR_S1_AP(ATTR_S1_AP_RO);
3134 if ((prot & VM_PROT_EXECUTE) == 0) {
3136 nbits |= ATTR_S1_XN;
3142 for (; sva < eva; sva = va_next) {
3143 l0 = pmap_l0(pmap, sva);
3144 if (pmap_load(l0) == 0) {
3145 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
3151 l1 = pmap_l0_to_l1(l0, sva);
3152 if (pmap_load(l1) == 0) {
3153 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
3159 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
3163 l2 = pmap_l1_to_l2(l1, sva);
3164 if (pmap_load(l2) == 0)
3167 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK) {
3168 if (sva + L2_SIZE == va_next && eva >= va_next) {
3169 pmap_protect_l2(pmap, l2, sva, mask, nbits);
3171 } else if (pmap_demote_l2(pmap, l2, sva) == NULL)
3174 KASSERT((pmap_load(l2) & ATTR_DESCR_MASK) == L2_TABLE,
3175 ("pmap_protect: Invalid L2 entry after demotion"));
3181 for (l3p = pmap_l2_to_l3(l2, sva); sva != va_next; l3p++,
3183 l3 = pmap_load(l3p);
3186 * Go to the next L3 entry if the current one is
3187 * invalid or already has the desired access
3188 * restrictions in place. (The latter case occurs
3189 * frequently. For example, in a "buildworld"
3190 * workload, almost 1 out of 4 L3 entries already
3191 * have the desired restrictions.)
3193 if (!pmap_l3_valid(l3) || (l3 & mask) == nbits) {
3194 if (va != va_next) {
3195 pmap_invalidate_range(pmap, va, sva);
3202 * When a dirty read/write mapping is write protected,
3203 * update the page's dirty field.
3205 if ((l3 & ATTR_SW_MANAGED) != 0 &&
3206 (nbits & ATTR_S1_AP(ATTR_S1_AP_RO)) != 0 &&
3207 pmap_pte_dirty(pmap, l3))
3208 vm_page_dirty(PHYS_TO_VM_PAGE(l3 & ~ATTR_MASK));
3210 if (!atomic_fcmpset_64(l3p, &l3, (l3 & ~mask) | nbits))
3216 pmap_invalidate_range(pmap, va, sva);
3222 * Inserts the specified page table page into the specified pmap's collection
3223 * of idle page table pages. Each of a pmap's page table pages is responsible
3224 * for mapping a distinct range of virtual addresses. The pmap's collection is
3225 * ordered by this virtual address range.
3227 * If "promoted" is false, then the page table page "mpte" must be zero filled.
3230 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte, bool promoted)
3233 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3234 mpte->valid = promoted ? VM_PAGE_BITS_ALL : 0;
3235 return (vm_radix_insert(&pmap->pm_root, mpte));
3239 * Removes the page table page mapping the specified virtual address from the
3240 * specified pmap's collection of idle page table pages, and returns it.
3241 * Otherwise, returns NULL if there is no page table page corresponding to the
3242 * specified virtual address.
3244 static __inline vm_page_t
3245 pmap_remove_pt_page(pmap_t pmap, vm_offset_t va)
3248 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3249 return (vm_radix_remove(&pmap->pm_root, pmap_l2_pindex(va)));
3253 * Performs a break-before-make update of a pmap entry. This is needed when
3254 * either promoting or demoting pages to ensure the TLB doesn't get into an
3255 * inconsistent state.
3258 pmap_update_entry(pmap_t pmap, pd_entry_t *pte, pd_entry_t newpte,
3259 vm_offset_t va, vm_size_t size)
3263 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3266 * Ensure we don't get switched out with the page table in an
3267 * inconsistent state. We also need to ensure no interrupts fire
3268 * as they may make use of an address we are about to invalidate.
3270 intr = intr_disable();
3273 * Clear the old mapping's valid bit, but leave the rest of the entry
3274 * unchanged, so that a lockless, concurrent pmap_kextract() can still
3275 * lookup the physical address.
3277 pmap_clear_bits(pte, ATTR_DESCR_VALID);
3278 pmap_invalidate_range(pmap, va, va + size);
3280 /* Create the new mapping */
3281 pmap_store(pte, newpte);
3287 #if VM_NRESERVLEVEL > 0
3289 * After promotion from 512 4KB page mappings to a single 2MB page mapping,
3290 * replace the many pv entries for the 4KB page mappings by a single pv entry
3291 * for the 2MB page mapping.
3294 pmap_pv_promote_l2(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
3295 struct rwlock **lockp)
3297 struct md_page *pvh;
3299 vm_offset_t va_last;
3302 KASSERT((pa & L2_OFFSET) == 0,
3303 ("pmap_pv_promote_l2: pa is not 2mpage aligned"));
3304 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
3307 * Transfer the first page's pv entry for this mapping to the 2mpage's
3308 * pv list. Aside from avoiding the cost of a call to get_pv_entry(),
3309 * a transfer avoids the possibility that get_pv_entry() calls
3310 * reclaim_pv_chunk() and that reclaim_pv_chunk() removes one of the
3311 * mappings that is being promoted.
3313 m = PHYS_TO_VM_PAGE(pa);
3314 va = va & ~L2_OFFSET;
3315 pv = pmap_pvh_remove(&m->md, pmap, va);
3316 KASSERT(pv != NULL, ("pmap_pv_promote_l2: pv not found"));
3317 pvh = pa_to_pvh(pa);
3318 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
3320 /* Free the remaining NPTEPG - 1 pv entries. */
3321 va_last = va + L2_SIZE - PAGE_SIZE;
3325 pmap_pvh_free(&m->md, pmap, va);
3326 } while (va < va_last);
3330 * Tries to promote the 512, contiguous 4KB page mappings that are within a
3331 * single level 2 table entry to a single 2MB page mapping. For promotion
3332 * to occur, two conditions must be met: (1) the 4KB page mappings must map
3333 * aligned, contiguous physical memory and (2) the 4KB page mappings must have
3334 * identical characteristics.
3337 pmap_promote_l2(pmap_t pmap, pd_entry_t *l2, vm_offset_t va,
3338 struct rwlock **lockp)
3340 pt_entry_t *firstl3, *l3, newl2, oldl3, pa;
3344 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3345 PMAP_ASSERT_STAGE1(pmap);
3347 sva = va & ~L2_OFFSET;
3348 firstl3 = pmap_l2_to_l3(l2, sva);
3349 newl2 = pmap_load(firstl3);
3352 if (((newl2 & (~ATTR_MASK | ATTR_AF)) & L2_OFFSET) != ATTR_AF) {
3353 atomic_add_long(&pmap_l2_p_failures, 1);
3354 CTR2(KTR_PMAP, "pmap_promote_l2: failure for va %#lx"
3355 " in pmap %p", va, pmap);
3359 if ((newl2 & (ATTR_S1_AP_RW_BIT | ATTR_SW_DBM)) ==
3360 (ATTR_S1_AP(ATTR_S1_AP_RO) | ATTR_SW_DBM)) {
3361 if (!atomic_fcmpset_64(l2, &newl2, newl2 & ~ATTR_SW_DBM))
3363 newl2 &= ~ATTR_SW_DBM;
3366 pa = newl2 + L2_SIZE - PAGE_SIZE;
3367 for (l3 = firstl3 + NL3PG - 1; l3 > firstl3; l3--) {
3368 oldl3 = pmap_load(l3);
3370 if ((oldl3 & (ATTR_S1_AP_RW_BIT | ATTR_SW_DBM)) ==
3371 (ATTR_S1_AP(ATTR_S1_AP_RO) | ATTR_SW_DBM)) {
3372 if (!atomic_fcmpset_64(l3, &oldl3, oldl3 &
3375 oldl3 &= ~ATTR_SW_DBM;
3378 atomic_add_long(&pmap_l2_p_failures, 1);
3379 CTR2(KTR_PMAP, "pmap_promote_l2: failure for va %#lx"
3380 " in pmap %p", va, pmap);
3387 * Save the page table page in its current state until the L2
3388 * mapping the superpage is demoted by pmap_demote_l2() or
3389 * destroyed by pmap_remove_l3().
3391 mpte = PHYS_TO_VM_PAGE(pmap_load(l2) & ~ATTR_MASK);
3392 KASSERT(mpte >= vm_page_array &&
3393 mpte < &vm_page_array[vm_page_array_size],
3394 ("pmap_promote_l2: page table page is out of range"));
3395 KASSERT(mpte->pindex == pmap_l2_pindex(va),
3396 ("pmap_promote_l2: page table page's pindex is wrong"));
3397 if (pmap_insert_pt_page(pmap, mpte, true)) {
3398 atomic_add_long(&pmap_l2_p_failures, 1);
3400 "pmap_promote_l2: failure for va %#lx in pmap %p", va,
3405 if ((newl2 & ATTR_SW_MANAGED) != 0)
3406 pmap_pv_promote_l2(pmap, va, newl2 & ~ATTR_MASK, lockp);
3408 newl2 &= ~ATTR_DESCR_MASK;
3411 pmap_update_entry(pmap, l2, newl2, sva, L2_SIZE);
3413 atomic_add_long(&pmap_l2_promotions, 1);
3414 CTR2(KTR_PMAP, "pmap_promote_l2: success for va %#lx in pmap %p", va,
3417 #endif /* VM_NRESERVLEVEL > 0 */
3420 * Insert the given physical page (p) at
3421 * the specified virtual address (v) in the
3422 * target physical map with the protection requested.
3424 * If specified, the page will be wired down, meaning
3425 * that the related pte can not be reclaimed.
3427 * NB: This is the only routine which MAY NOT lazy-evaluate
3428 * or lose information. That is, this routine must actually
3429 * insert this page into the given map NOW.
3432 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
3433 u_int flags, int8_t psind)
3435 struct rwlock *lock;
3437 pt_entry_t new_l3, orig_l3;
3438 pt_entry_t *l2, *l3;
3445 va = trunc_page(va);
3446 if ((m->oflags & VPO_UNMANAGED) == 0)
3447 VM_PAGE_OBJECT_BUSY_ASSERT(m);
3448 pa = VM_PAGE_TO_PHYS(m);
3449 new_l3 = (pt_entry_t)(pa | ATTR_DEFAULT | L3_PAGE);
3450 new_l3 |= pmap_pte_memattr(pmap, m->md.pv_memattr);
3451 new_l3 |= pmap_pte_prot(pmap, prot);
3453 if ((flags & PMAP_ENTER_WIRED) != 0)
3454 new_l3 |= ATTR_SW_WIRED;
3455 if (pmap->pm_stage == PM_STAGE1) {
3456 if (va < VM_MAXUSER_ADDRESS)
3457 new_l3 |= ATTR_S1_AP(ATTR_S1_AP_USER) | ATTR_S1_PXN;
3459 new_l3 |= ATTR_S1_UXN;
3460 if (pmap != kernel_pmap)
3461 new_l3 |= ATTR_S1_nG;
3464 * Clear the access flag on executable mappings, this will be
3465 * set later when the page is accessed. The fault handler is
3466 * required to invalidate the I-cache.
3468 * TODO: Switch to the valid flag to allow hardware management
3469 * of the access flag. Much of the pmap code assumes the
3470 * valid flag is set and fails to destroy the old page tables
3471 * correctly if it is clear.
3473 if (prot & VM_PROT_EXECUTE)
3476 if ((m->oflags & VPO_UNMANAGED) == 0) {
3477 new_l3 |= ATTR_SW_MANAGED;
3478 if ((prot & VM_PROT_WRITE) != 0) {
3479 new_l3 |= ATTR_SW_DBM;
3480 if ((flags & VM_PROT_WRITE) == 0) {
3481 if (pmap->pm_stage == PM_STAGE1)
3482 new_l3 |= ATTR_S1_AP(ATTR_S1_AP_RO);
3485 ~ATTR_S2_S2AP(ATTR_S2_S2AP_WRITE);
3490 CTR2(KTR_PMAP, "pmap_enter: %.16lx -> %.16lx", va, pa);
3495 /* Assert the required virtual and physical alignment. */
3496 KASSERT((va & L2_OFFSET) == 0, ("pmap_enter: va unaligned"));
3497 KASSERT(m->psind > 0, ("pmap_enter: m->psind < psind"));
3498 rv = pmap_enter_l2(pmap, va, (new_l3 & ~L3_PAGE) | L2_BLOCK,
3505 * In the case that a page table page is not
3506 * resident, we are creating it here.
3509 pde = pmap_pde(pmap, va, &lvl);
3510 if (pde != NULL && lvl == 2) {
3511 l3 = pmap_l2_to_l3(pde, va);
3512 if (va < VM_MAXUSER_ADDRESS && mpte == NULL) {
3513 mpte = PHYS_TO_VM_PAGE(pmap_load(pde) & ~ATTR_MASK);
3517 } else if (pde != NULL && lvl == 1) {
3518 l2 = pmap_l1_to_l2(pde, va);
3519 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK &&
3520 (l3 = pmap_demote_l2_locked(pmap, l2, va, &lock)) != NULL) {
3521 l3 = &l3[pmap_l3_index(va)];
3522 if (va < VM_MAXUSER_ADDRESS) {
3523 mpte = PHYS_TO_VM_PAGE(
3524 pmap_load(l2) & ~ATTR_MASK);
3529 /* We need to allocate an L3 table. */
3531 if (va < VM_MAXUSER_ADDRESS) {
3532 nosleep = (flags & PMAP_ENTER_NOSLEEP) != 0;
3535 * We use _pmap_alloc_l3() instead of pmap_alloc_l3() in order
3536 * to handle the possibility that a superpage mapping for "va"
3537 * was created while we slept.
3539 mpte = _pmap_alloc_l3(pmap, pmap_l2_pindex(va),
3540 nosleep ? NULL : &lock);
3541 if (mpte == NULL && nosleep) {
3542 CTR0(KTR_PMAP, "pmap_enter: mpte == NULL");
3543 rv = KERN_RESOURCE_SHORTAGE;
3548 panic("pmap_enter: missing L3 table for kernel va %#lx", va);
3551 orig_l3 = pmap_load(l3);
3552 opa = orig_l3 & ~ATTR_MASK;
3556 * Is the specified virtual address already mapped?
3558 if (pmap_l3_valid(orig_l3)) {
3560 * Only allow adding new entries on stage 2 tables for now.
3561 * This simplifies cache invalidation as we may need to call
3562 * into EL2 to perform such actions.
3564 PMAP_ASSERT_STAGE1(pmap);
3566 * Wiring change, just update stats. We don't worry about
3567 * wiring PT pages as they remain resident as long as there
3568 * are valid mappings in them. Hence, if a user page is wired,
3569 * the PT page will be also.
3571 if ((flags & PMAP_ENTER_WIRED) != 0 &&
3572 (orig_l3 & ATTR_SW_WIRED) == 0)
3573 pmap->pm_stats.wired_count++;
3574 else if ((flags & PMAP_ENTER_WIRED) == 0 &&
3575 (orig_l3 & ATTR_SW_WIRED) != 0)
3576 pmap->pm_stats.wired_count--;
3579 * Remove the extra PT page reference.
3583 KASSERT(mpte->ref_count > 0,
3584 ("pmap_enter: missing reference to page table page,"
3589 * Has the physical page changed?
3593 * No, might be a protection or wiring change.
3595 if ((orig_l3 & ATTR_SW_MANAGED) != 0 &&
3596 (new_l3 & ATTR_SW_DBM) != 0)
3597 vm_page_aflag_set(m, PGA_WRITEABLE);
3602 * The physical page has changed. Temporarily invalidate
3605 orig_l3 = pmap_load_clear(l3);
3606 KASSERT((orig_l3 & ~ATTR_MASK) == opa,
3607 ("pmap_enter: unexpected pa update for %#lx", va));
3608 if ((orig_l3 & ATTR_SW_MANAGED) != 0) {
3609 om = PHYS_TO_VM_PAGE(opa);
3612 * The pmap lock is sufficient to synchronize with
3613 * concurrent calls to pmap_page_test_mappings() and
3614 * pmap_ts_referenced().
3616 if (pmap_pte_dirty(pmap, orig_l3))
3618 if ((orig_l3 & ATTR_AF) != 0) {
3619 pmap_invalidate_page(pmap, va);
3620 vm_page_aflag_set(om, PGA_REFERENCED);
3622 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, opa);
3623 pv = pmap_pvh_remove(&om->md, pmap, va);
3624 if ((m->oflags & VPO_UNMANAGED) != 0)
3625 free_pv_entry(pmap, pv);
3626 if ((om->a.flags & PGA_WRITEABLE) != 0 &&
3627 TAILQ_EMPTY(&om->md.pv_list) &&
3628 ((om->flags & PG_FICTITIOUS) != 0 ||
3629 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
3630 vm_page_aflag_clear(om, PGA_WRITEABLE);
3632 KASSERT((orig_l3 & ATTR_AF) != 0,
3633 ("pmap_enter: unmanaged mapping lacks ATTR_AF"));
3634 pmap_invalidate_page(pmap, va);
3639 * Increment the counters.
3641 if ((new_l3 & ATTR_SW_WIRED) != 0)
3642 pmap->pm_stats.wired_count++;
3643 pmap_resident_count_inc(pmap, 1);
3646 * Enter on the PV list if part of our managed memory.
3648 if ((m->oflags & VPO_UNMANAGED) == 0) {
3650 pv = get_pv_entry(pmap, &lock);
3653 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, pa);
3654 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3656 if ((new_l3 & ATTR_SW_DBM) != 0)
3657 vm_page_aflag_set(m, PGA_WRITEABLE);
3661 if (pmap->pm_stage == PM_STAGE1) {
3663 * Sync icache if exec permission and attribute
3664 * VM_MEMATTR_WRITE_BACK is set. Do it now, before the mapping
3665 * is stored and made valid for hardware table walk. If done
3666 * later, then other can access this page before caches are
3667 * properly synced. Don't do it for kernel memory which is
3668 * mapped with exec permission even if the memory isn't going
3669 * to hold executable code. The only time when icache sync is
3670 * needed is after kernel module is loaded and the relocation
3671 * info is processed. And it's done in elf_cpu_load_file().
3673 if ((prot & VM_PROT_EXECUTE) && pmap != kernel_pmap &&
3674 m->md.pv_memattr == VM_MEMATTR_WRITE_BACK &&
3675 (opa != pa || (orig_l3 & ATTR_S1_XN))) {
3676 PMAP_ASSERT_STAGE1(pmap);
3677 cpu_icache_sync_range(PHYS_TO_DMAP(pa), PAGE_SIZE);
3680 cpu_dcache_wb_range(PHYS_TO_DMAP(pa), PAGE_SIZE);
3684 * Update the L3 entry
3686 if (pmap_l3_valid(orig_l3)) {
3687 PMAP_ASSERT_STAGE1(pmap);
3688 KASSERT(opa == pa, ("pmap_enter: invalid update"));
3689 if ((orig_l3 & ~ATTR_AF) != (new_l3 & ~ATTR_AF)) {
3690 /* same PA, different attributes */
3691 orig_l3 = pmap_load_store(l3, new_l3);
3692 pmap_invalidate_page(pmap, va);
3693 if ((orig_l3 & ATTR_SW_MANAGED) != 0 &&
3694 pmap_pte_dirty(pmap, orig_l3))
3699 * This can happens if multiple threads simultaneously
3700 * access not yet mapped page. This bad for performance
3701 * since this can cause full demotion-NOP-promotion
3703 * Another possible reasons are:
3704 * - VM and pmap memory layout are diverged
3705 * - tlb flush is missing somewhere and CPU doesn't see
3708 CTR4(KTR_PMAP, "%s: already mapped page - "
3709 "pmap %p va 0x%#lx pte 0x%lx",
3710 __func__, pmap, va, new_l3);
3714 pmap_store(l3, new_l3);
3718 #if VM_NRESERVLEVEL > 0
3720 * Try to promote from level 3 pages to a level 2 superpage. This
3721 * currently only works on stage 1 pmaps as pmap_promote_l2 looks at
3722 * stage 1 specific fields and performs a break-before-make sequence
3723 * that is incorrect a stage 2 pmap.
3725 if ((mpte == NULL || mpte->ref_count == NL3PG) &&
3726 pmap_ps_enabled(pmap) && pmap->pm_stage == PM_STAGE1 &&
3727 (m->flags & PG_FICTITIOUS) == 0 &&
3728 vm_reserv_level_iffullpop(m) == 0) {
3729 pmap_promote_l2(pmap, pde, va, &lock);
3742 * Tries to create a read- and/or execute-only 2MB page mapping. Returns true
3743 * if successful. Returns false if (1) a page table page cannot be allocated
3744 * without sleeping, (2) a mapping already exists at the specified virtual
3745 * address, or (3) a PV entry cannot be allocated without reclaiming another
3749 pmap_enter_2mpage(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
3750 struct rwlock **lockp)
3754 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3755 PMAP_ASSERT_STAGE1(pmap);
3757 new_l2 = (pd_entry_t)(VM_PAGE_TO_PHYS(m) | ATTR_DEFAULT |
3758 ATTR_S1_IDX(m->md.pv_memattr) | ATTR_S1_AP(ATTR_S1_AP_RO) |
3760 if ((m->oflags & VPO_UNMANAGED) == 0) {
3761 new_l2 |= ATTR_SW_MANAGED;
3764 if ((prot & VM_PROT_EXECUTE) == 0 ||
3765 m->md.pv_memattr == VM_MEMATTR_DEVICE)
3766 new_l2 |= ATTR_S1_XN;
3767 if (va < VM_MAXUSER_ADDRESS)
3768 new_l2 |= ATTR_S1_AP(ATTR_S1_AP_USER) | ATTR_S1_PXN;
3770 new_l2 |= ATTR_S1_UXN;
3771 if (pmap != kernel_pmap)
3772 new_l2 |= ATTR_S1_nG;
3773 return (pmap_enter_l2(pmap, va, new_l2, PMAP_ENTER_NOSLEEP |
3774 PMAP_ENTER_NOREPLACE | PMAP_ENTER_NORECLAIM, NULL, lockp) ==
3779 * Returns true if every page table entry in the specified page table is
3783 pmap_every_pte_zero(vm_paddr_t pa)
3785 pt_entry_t *pt_end, *pte;
3787 KASSERT((pa & PAGE_MASK) == 0, ("pa is misaligned"));
3788 pte = (pt_entry_t *)PHYS_TO_DMAP(pa);
3789 for (pt_end = pte + Ln_ENTRIES; pte < pt_end; pte++) {
3797 * Tries to create the specified 2MB page mapping. Returns KERN_SUCCESS if
3798 * the mapping was created, and either KERN_FAILURE or KERN_RESOURCE_SHORTAGE
3799 * otherwise. Returns KERN_FAILURE if PMAP_ENTER_NOREPLACE was specified and
3800 * a mapping already exists at the specified virtual address. Returns
3801 * KERN_RESOURCE_SHORTAGE if PMAP_ENTER_NOSLEEP was specified and a page table
3802 * page allocation failed. Returns KERN_RESOURCE_SHORTAGE if
3803 * PMAP_ENTER_NORECLAIM was specified and a PV entry allocation failed.
3805 * The parameter "m" is only used when creating a managed, writeable mapping.
3808 pmap_enter_l2(pmap_t pmap, vm_offset_t va, pd_entry_t new_l2, u_int flags,
3809 vm_page_t m, struct rwlock **lockp)
3811 struct spglist free;
3812 pd_entry_t *l2, old_l2;
3815 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3817 if ((l2 = pmap_alloc_l2(pmap, va, &l2pg, (flags &
3818 PMAP_ENTER_NOSLEEP) != 0 ? NULL : lockp)) == NULL) {
3819 CTR2(KTR_PMAP, "pmap_enter_l2: failure for va %#lx in pmap %p",
3821 return (KERN_RESOURCE_SHORTAGE);
3825 * If there are existing mappings, either abort or remove them.
3827 if ((old_l2 = pmap_load(l2)) != 0) {
3828 KASSERT(l2pg == NULL || l2pg->ref_count > 1,
3829 ("pmap_enter_l2: l2pg's ref count is too low"));
3830 if ((flags & PMAP_ENTER_NOREPLACE) != 0 && (va <
3831 VM_MAXUSER_ADDRESS || (old_l2 & ATTR_DESCR_MASK) ==
3832 L2_BLOCK || !pmap_every_pte_zero(old_l2 & ~ATTR_MASK))) {
3835 CTR2(KTR_PMAP, "pmap_enter_l2: failure for va %#lx"
3836 " in pmap %p", va, pmap);
3837 return (KERN_FAILURE);
3840 if ((old_l2 & ATTR_DESCR_MASK) == L2_BLOCK)
3841 (void)pmap_remove_l2(pmap, l2, va,
3842 pmap_load(pmap_l1(pmap, va)), &free, lockp);
3844 pmap_remove_l3_range(pmap, old_l2, va, va + L2_SIZE,
3846 if (va < VM_MAXUSER_ADDRESS) {
3847 vm_page_free_pages_toq(&free, true);
3848 KASSERT(pmap_load(l2) == 0,
3849 ("pmap_enter_l2: non-zero L2 entry %p", l2));
3851 KASSERT(SLIST_EMPTY(&free),
3852 ("pmap_enter_l2: freed kernel page table page"));
3855 * Both pmap_remove_l2() and pmap_remove_l3_range()
3856 * will leave the kernel page table page zero filled.
3857 * Nonetheless, the TLB could have an intermediate
3858 * entry for the kernel page table page.
3860 mt = PHYS_TO_VM_PAGE(pmap_load(l2) & ~ATTR_MASK);
3861 if (pmap_insert_pt_page(pmap, mt, false))
3862 panic("pmap_enter_l2: trie insert failed");
3864 pmap_invalidate_page(pmap, va);
3868 if ((new_l2 & ATTR_SW_MANAGED) != 0) {
3870 * Abort this mapping if its PV entry could not be created.
3872 if (!pmap_pv_insert_l2(pmap, va, new_l2, flags, lockp)) {
3874 pmap_abort_ptp(pmap, va, l2pg);
3876 "pmap_enter_l2: failure for va %#lx in pmap %p",
3878 return (KERN_RESOURCE_SHORTAGE);
3880 if ((new_l2 & ATTR_SW_DBM) != 0)
3881 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
3882 vm_page_aflag_set(mt, PGA_WRITEABLE);
3886 * Increment counters.
3888 if ((new_l2 & ATTR_SW_WIRED) != 0)
3889 pmap->pm_stats.wired_count += L2_SIZE / PAGE_SIZE;
3890 pmap->pm_stats.resident_count += L2_SIZE / PAGE_SIZE;
3893 * Map the superpage.
3895 pmap_store(l2, new_l2);
3898 atomic_add_long(&pmap_l2_mappings, 1);
3899 CTR2(KTR_PMAP, "pmap_enter_l2: success for va %#lx in pmap %p",
3902 return (KERN_SUCCESS);
3906 * Maps a sequence of resident pages belonging to the same object.
3907 * The sequence begins with the given page m_start. This page is
3908 * mapped at the given virtual address start. Each subsequent page is
3909 * mapped at a virtual address that is offset from start by the same
3910 * amount as the page is offset from m_start within the object. The
3911 * last page in the sequence is the page with the largest offset from
3912 * m_start that can be mapped at a virtual address less than the given
3913 * virtual address end. Not every virtual page between start and end
3914 * is mapped; only those for which a resident page exists with the
3915 * corresponding offset from m_start are mapped.
3918 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
3919 vm_page_t m_start, vm_prot_t prot)
3921 struct rwlock *lock;
3924 vm_pindex_t diff, psize;
3926 VM_OBJECT_ASSERT_LOCKED(m_start->object);
3928 psize = atop(end - start);
3933 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
3934 va = start + ptoa(diff);
3935 if ((va & L2_OFFSET) == 0 && va + L2_SIZE <= end &&
3936 m->psind == 1 && pmap_ps_enabled(pmap) &&
3937 pmap_enter_2mpage(pmap, va, m, prot, &lock))
3938 m = &m[L2_SIZE / PAGE_SIZE - 1];
3940 mpte = pmap_enter_quick_locked(pmap, va, m, prot, mpte,
3942 m = TAILQ_NEXT(m, listq);
3950 * this code makes some *MAJOR* assumptions:
3951 * 1. Current pmap & pmap exists.
3954 * 4. No page table pages.
3955 * but is *MUCH* faster than pmap_enter...
3959 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3961 struct rwlock *lock;
3965 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL, &lock);
3972 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
3973 vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp)
3976 pt_entry_t *l2, *l3, l3_val;
3980 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
3981 (m->oflags & VPO_UNMANAGED) != 0,
3982 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
3983 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3984 PMAP_ASSERT_STAGE1(pmap);
3986 CTR2(KTR_PMAP, "pmap_enter_quick_locked: %p %lx", pmap, va);
3988 * In the case that a page table page is not
3989 * resident, we are creating it here.
3991 if (va < VM_MAXUSER_ADDRESS) {
3992 vm_pindex_t l2pindex;
3995 * Calculate pagetable page index
3997 l2pindex = pmap_l2_pindex(va);
3998 if (mpte && (mpte->pindex == l2pindex)) {
4004 pde = pmap_pde(pmap, va, &lvl);
4007 * If the page table page is mapped, we just increment
4008 * the hold count, and activate it. Otherwise, we
4009 * attempt to allocate a page table page. If this
4010 * attempt fails, we don't retry. Instead, we give up.
4013 l2 = pmap_l1_to_l2(pde, va);
4014 if ((pmap_load(l2) & ATTR_DESCR_MASK) ==
4018 if (lvl == 2 && pmap_load(pde) != 0) {
4020 PHYS_TO_VM_PAGE(pmap_load(pde) & ~ATTR_MASK);
4024 * Pass NULL instead of the PV list lock
4025 * pointer, because we don't intend to sleep.
4027 mpte = _pmap_alloc_l3(pmap, l2pindex, NULL);
4032 l3 = (pt_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpte));
4033 l3 = &l3[pmap_l3_index(va)];
4036 pde = pmap_pde(kernel_pmap, va, &lvl);
4037 KASSERT(pde != NULL,
4038 ("pmap_enter_quick_locked: Invalid page entry, va: 0x%lx",
4041 ("pmap_enter_quick_locked: Invalid level %d", lvl));
4042 l3 = pmap_l2_to_l3(pde, va);
4046 * Abort if a mapping already exists.
4048 if (pmap_load(l3) != 0) {
4055 * Enter on the PV list if part of our managed memory.
4057 if ((m->oflags & VPO_UNMANAGED) == 0 &&
4058 !pmap_try_insert_pv_entry(pmap, va, m, lockp)) {
4060 pmap_abort_ptp(pmap, va, mpte);
4065 * Increment counters
4067 pmap_resident_count_inc(pmap, 1);
4069 pa = VM_PAGE_TO_PHYS(m);
4070 l3_val = pa | ATTR_DEFAULT | ATTR_S1_IDX(m->md.pv_memattr) |
4071 ATTR_S1_AP(ATTR_S1_AP_RO) | L3_PAGE;
4072 if ((prot & VM_PROT_EXECUTE) == 0 ||
4073 m->md.pv_memattr == VM_MEMATTR_DEVICE)
4074 l3_val |= ATTR_S1_XN;
4075 if (va < VM_MAXUSER_ADDRESS)
4076 l3_val |= ATTR_S1_AP(ATTR_S1_AP_USER) | ATTR_S1_PXN;
4078 l3_val |= ATTR_S1_UXN;
4079 if (pmap != kernel_pmap)
4080 l3_val |= ATTR_S1_nG;
4083 * Now validate mapping with RO protection
4085 if ((m->oflags & VPO_UNMANAGED) == 0) {
4086 l3_val |= ATTR_SW_MANAGED;
4090 /* Sync icache before the mapping is stored to PTE */
4091 if ((prot & VM_PROT_EXECUTE) && pmap != kernel_pmap &&
4092 m->md.pv_memattr == VM_MEMATTR_WRITE_BACK)
4093 cpu_icache_sync_range(PHYS_TO_DMAP(pa), PAGE_SIZE);
4095 pmap_store(l3, l3_val);
4102 * This code maps large physical mmap regions into the
4103 * processor address space. Note that some shortcuts
4104 * are taken, but the code works.
4107 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
4108 vm_pindex_t pindex, vm_size_t size)
4111 VM_OBJECT_ASSERT_WLOCKED(object);
4112 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
4113 ("pmap_object_init_pt: non-device object"));
4117 * Clear the wired attribute from the mappings for the specified range of
4118 * addresses in the given pmap. Every valid mapping within that range
4119 * must have the wired attribute set. In contrast, invalid mappings
4120 * cannot have the wired attribute set, so they are ignored.
4122 * The wired attribute of the page table entry is not a hardware feature,
4123 * so there is no need to invalidate any TLB entries.
4126 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
4128 vm_offset_t va_next;
4129 pd_entry_t *l0, *l1, *l2;
4133 for (; sva < eva; sva = va_next) {
4134 l0 = pmap_l0(pmap, sva);
4135 if (pmap_load(l0) == 0) {
4136 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
4142 l1 = pmap_l0_to_l1(l0, sva);
4143 if (pmap_load(l1) == 0) {
4144 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
4150 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
4154 l2 = pmap_l1_to_l2(l1, sva);
4155 if (pmap_load(l2) == 0)
4158 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK) {
4159 if ((pmap_load(l2) & ATTR_SW_WIRED) == 0)
4160 panic("pmap_unwire: l2 %#jx is missing "
4161 "ATTR_SW_WIRED", (uintmax_t)pmap_load(l2));
4164 * Are we unwiring the entire large page? If not,
4165 * demote the mapping and fall through.
4167 if (sva + L2_SIZE == va_next && eva >= va_next) {
4168 pmap_clear_bits(l2, ATTR_SW_WIRED);
4169 pmap->pm_stats.wired_count -= L2_SIZE /
4172 } else if (pmap_demote_l2(pmap, l2, sva) == NULL)
4173 panic("pmap_unwire: demotion failed");
4175 KASSERT((pmap_load(l2) & ATTR_DESCR_MASK) == L2_TABLE,
4176 ("pmap_unwire: Invalid l2 entry after demotion"));
4180 for (l3 = pmap_l2_to_l3(l2, sva); sva != va_next; l3++,
4182 if (pmap_load(l3) == 0)
4184 if ((pmap_load(l3) & ATTR_SW_WIRED) == 0)
4185 panic("pmap_unwire: l3 %#jx is missing "
4186 "ATTR_SW_WIRED", (uintmax_t)pmap_load(l3));
4189 * ATTR_SW_WIRED must be cleared atomically. Although
4190 * the pmap lock synchronizes access to ATTR_SW_WIRED,
4191 * the System MMU may write to the entry concurrently.
4193 pmap_clear_bits(l3, ATTR_SW_WIRED);
4194 pmap->pm_stats.wired_count--;
4201 * Copy the range specified by src_addr/len
4202 * from the source map to the range dst_addr/len
4203 * in the destination map.
4205 * This routine is only advisory and need not do anything.
4207 * Because the executable mappings created by this routine are copied,
4208 * it should not have to flush the instruction cache.
4211 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
4212 vm_offset_t src_addr)
4214 struct rwlock *lock;
4215 pd_entry_t *l0, *l1, *l2, srcptepaddr;
4216 pt_entry_t *dst_pte, mask, nbits, ptetemp, *src_pte;
4217 vm_offset_t addr, end_addr, va_next;
4218 vm_page_t dst_l2pg, dstmpte, srcmpte;
4220 PMAP_ASSERT_STAGE1(dst_pmap);
4221 PMAP_ASSERT_STAGE1(src_pmap);
4223 if (dst_addr != src_addr)
4225 end_addr = src_addr + len;
4227 if (dst_pmap < src_pmap) {
4228 PMAP_LOCK(dst_pmap);
4229 PMAP_LOCK(src_pmap);
4231 PMAP_LOCK(src_pmap);
4232 PMAP_LOCK(dst_pmap);
4234 for (addr = src_addr; addr < end_addr; addr = va_next) {
4235 l0 = pmap_l0(src_pmap, addr);
4236 if (pmap_load(l0) == 0) {
4237 va_next = (addr + L0_SIZE) & ~L0_OFFSET;
4242 l1 = pmap_l0_to_l1(l0, addr);
4243 if (pmap_load(l1) == 0) {
4244 va_next = (addr + L1_SIZE) & ~L1_OFFSET;
4249 va_next = (addr + L2_SIZE) & ~L2_OFFSET;
4252 l2 = pmap_l1_to_l2(l1, addr);
4253 srcptepaddr = pmap_load(l2);
4254 if (srcptepaddr == 0)
4256 if ((srcptepaddr & ATTR_DESCR_MASK) == L2_BLOCK) {
4257 if ((addr & L2_OFFSET) != 0 ||
4258 addr + L2_SIZE > end_addr)
4260 l2 = pmap_alloc_l2(dst_pmap, addr, &dst_l2pg, NULL);
4263 if (pmap_load(l2) == 0 &&
4264 ((srcptepaddr & ATTR_SW_MANAGED) == 0 ||
4265 pmap_pv_insert_l2(dst_pmap, addr, srcptepaddr,
4266 PMAP_ENTER_NORECLAIM, &lock))) {
4267 mask = ATTR_AF | ATTR_SW_WIRED;
4269 if ((srcptepaddr & ATTR_SW_DBM) != 0)
4270 nbits |= ATTR_S1_AP_RW_BIT;
4271 pmap_store(l2, (srcptepaddr & ~mask) | nbits);
4272 pmap_resident_count_inc(dst_pmap, L2_SIZE /
4274 atomic_add_long(&pmap_l2_mappings, 1);
4276 pmap_abort_ptp(dst_pmap, addr, dst_l2pg);
4279 KASSERT((srcptepaddr & ATTR_DESCR_MASK) == L2_TABLE,
4280 ("pmap_copy: invalid L2 entry"));
4281 srcptepaddr &= ~ATTR_MASK;
4282 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr);
4283 KASSERT(srcmpte->ref_count > 0,
4284 ("pmap_copy: source page table page is unused"));
4285 if (va_next > end_addr)
4287 src_pte = (pt_entry_t *)PHYS_TO_DMAP(srcptepaddr);
4288 src_pte = &src_pte[pmap_l3_index(addr)];
4290 for (; addr < va_next; addr += PAGE_SIZE, src_pte++) {
4291 ptetemp = pmap_load(src_pte);
4294 * We only virtual copy managed pages.
4296 if ((ptetemp & ATTR_SW_MANAGED) == 0)
4299 if (dstmpte != NULL) {
4300 KASSERT(dstmpte->pindex == pmap_l2_pindex(addr),
4301 ("dstmpte pindex/addr mismatch"));
4302 dstmpte->ref_count++;
4303 } else if ((dstmpte = pmap_alloc_l3(dst_pmap, addr,
4306 dst_pte = (pt_entry_t *)
4307 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dstmpte));
4308 dst_pte = &dst_pte[pmap_l3_index(addr)];
4309 if (pmap_load(dst_pte) == 0 &&
4310 pmap_try_insert_pv_entry(dst_pmap, addr,
4311 PHYS_TO_VM_PAGE(ptetemp & ~ATTR_MASK), &lock)) {
4313 * Clear the wired, modified, and accessed
4314 * (referenced) bits during the copy.
4316 mask = ATTR_AF | ATTR_SW_WIRED;
4318 if ((ptetemp & ATTR_SW_DBM) != 0)
4319 nbits |= ATTR_S1_AP_RW_BIT;
4320 pmap_store(dst_pte, (ptetemp & ~mask) | nbits);
4321 pmap_resident_count_inc(dst_pmap, 1);
4323 pmap_abort_ptp(dst_pmap, addr, dstmpte);
4326 /* Have we copied all of the valid mappings? */
4327 if (dstmpte->ref_count >= srcmpte->ref_count)
4333 * XXX This barrier may not be needed because the destination pmap is
4340 PMAP_UNLOCK(src_pmap);
4341 PMAP_UNLOCK(dst_pmap);
4345 * pmap_zero_page zeros the specified hardware page by mapping
4346 * the page into KVM and using bzero to clear its contents.
4349 pmap_zero_page(vm_page_t m)
4351 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
4353 pagezero((void *)va);
4357 * pmap_zero_page_area zeros the specified hardware page by mapping
4358 * the page into KVM and using bzero to clear its contents.
4360 * off and size may not cover an area beyond a single hardware page.
4363 pmap_zero_page_area(vm_page_t m, int off, int size)
4365 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
4367 if (off == 0 && size == PAGE_SIZE)
4368 pagezero((void *)va);
4370 bzero((char *)va + off, size);
4374 * pmap_copy_page copies the specified (machine independent)
4375 * page by mapping the page into virtual memory and using
4376 * bcopy to copy the page, one machine dependent page at a
4380 pmap_copy_page(vm_page_t msrc, vm_page_t mdst)
4382 vm_offset_t src = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(msrc));
4383 vm_offset_t dst = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mdst));
4385 pagecopy((void *)src, (void *)dst);
4388 int unmapped_buf_allowed = 1;
4391 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
4392 vm_offset_t b_offset, int xfersize)
4396 vm_paddr_t p_a, p_b;
4397 vm_offset_t a_pg_offset, b_pg_offset;
4400 while (xfersize > 0) {
4401 a_pg_offset = a_offset & PAGE_MASK;
4402 m_a = ma[a_offset >> PAGE_SHIFT];
4403 p_a = m_a->phys_addr;
4404 b_pg_offset = b_offset & PAGE_MASK;
4405 m_b = mb[b_offset >> PAGE_SHIFT];
4406 p_b = m_b->phys_addr;
4407 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
4408 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
4409 if (__predict_false(!PHYS_IN_DMAP(p_a))) {
4410 panic("!DMAP a %lx", p_a);
4412 a_cp = (char *)PHYS_TO_DMAP(p_a) + a_pg_offset;
4414 if (__predict_false(!PHYS_IN_DMAP(p_b))) {
4415 panic("!DMAP b %lx", p_b);
4417 b_cp = (char *)PHYS_TO_DMAP(p_b) + b_pg_offset;
4419 bcopy(a_cp, b_cp, cnt);
4427 pmap_quick_enter_page(vm_page_t m)
4430 return (PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)));
4434 pmap_quick_remove_page(vm_offset_t addr)
4439 * Returns true if the pmap's pv is one of the first
4440 * 16 pvs linked to from this page. This count may
4441 * be changed upwards or downwards in the future; it
4442 * is only necessary that true be returned for a small
4443 * subset of pmaps for proper page aging.
4446 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
4448 struct md_page *pvh;
4449 struct rwlock *lock;
4454 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4455 ("pmap_page_exists_quick: page %p is not managed", m));
4457 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
4459 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4460 if (PV_PMAP(pv) == pmap) {
4468 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
4469 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4470 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4471 if (PV_PMAP(pv) == pmap) {
4485 * pmap_page_wired_mappings:
4487 * Return the number of managed mappings to the given physical page
4491 pmap_page_wired_mappings(vm_page_t m)
4493 struct rwlock *lock;
4494 struct md_page *pvh;
4498 int count, lvl, md_gen, pvh_gen;
4500 if ((m->oflags & VPO_UNMANAGED) != 0)
4502 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
4506 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4508 if (!PMAP_TRYLOCK(pmap)) {
4509 md_gen = m->md.pv_gen;
4513 if (md_gen != m->md.pv_gen) {
4518 pte = pmap_pte(pmap, pv->pv_va, &lvl);
4519 if (pte != NULL && (pmap_load(pte) & ATTR_SW_WIRED) != 0)
4523 if ((m->flags & PG_FICTITIOUS) == 0) {
4524 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4525 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4527 if (!PMAP_TRYLOCK(pmap)) {
4528 md_gen = m->md.pv_gen;
4529 pvh_gen = pvh->pv_gen;
4533 if (md_gen != m->md.pv_gen ||
4534 pvh_gen != pvh->pv_gen) {
4539 pte = pmap_pte(pmap, pv->pv_va, &lvl);
4541 (pmap_load(pte) & ATTR_SW_WIRED) != 0)
4551 * Returns true if the given page is mapped individually or as part of
4552 * a 2mpage. Otherwise, returns false.
4555 pmap_page_is_mapped(vm_page_t m)
4557 struct rwlock *lock;
4560 if ((m->oflags & VPO_UNMANAGED) != 0)
4562 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
4564 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
4565 ((m->flags & PG_FICTITIOUS) == 0 &&
4566 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
4572 * Destroy all managed, non-wired mappings in the given user-space
4573 * pmap. This pmap cannot be active on any processor besides the
4576 * This function cannot be applied to the kernel pmap. Moreover, it
4577 * is not intended for general use. It is only to be used during
4578 * process termination. Consequently, it can be implemented in ways
4579 * that make it faster than pmap_remove(). First, it can more quickly
4580 * destroy mappings by iterating over the pmap's collection of PV
4581 * entries, rather than searching the page table. Second, it doesn't
4582 * have to test and clear the page table entries atomically, because
4583 * no processor is currently accessing the user address space. In
4584 * particular, a page table entry's dirty bit won't change state once
4585 * this function starts.
4588 pmap_remove_pages(pmap_t pmap)
4591 pt_entry_t *pte, tpte;
4592 struct spglist free;
4593 vm_page_t m, ml3, mt;
4595 struct md_page *pvh;
4596 struct pv_chunk *pc, *npc;
4597 struct rwlock *lock;
4599 uint64_t inuse, bitmask;
4600 int allfree, field, freed, idx, lvl;
4603 KASSERT(pmap == PCPU_GET(curpmap), ("non-current pmap %p", pmap));
4609 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
4612 for (field = 0; field < _NPCM; field++) {
4613 inuse = ~pc->pc_map[field] & pc_freemask[field];
4614 while (inuse != 0) {
4615 bit = ffsl(inuse) - 1;
4616 bitmask = 1UL << bit;
4617 idx = field * 64 + bit;
4618 pv = &pc->pc_pventry[idx];
4621 pde = pmap_pde(pmap, pv->pv_va, &lvl);
4622 KASSERT(pde != NULL,
4623 ("Attempting to remove an unmapped page"));
4627 pte = pmap_l1_to_l2(pde, pv->pv_va);
4628 tpte = pmap_load(pte);
4629 KASSERT((tpte & ATTR_DESCR_MASK) ==
4631 ("Attempting to remove an invalid "
4632 "block: %lx", tpte));
4635 pte = pmap_l2_to_l3(pde, pv->pv_va);
4636 tpte = pmap_load(pte);
4637 KASSERT((tpte & ATTR_DESCR_MASK) ==
4639 ("Attempting to remove an invalid "
4640 "page: %lx", tpte));
4644 "Invalid page directory level: %d",
4649 * We cannot remove wired pages from a process' mapping at this time
4651 if (tpte & ATTR_SW_WIRED) {
4656 pa = tpte & ~ATTR_MASK;
4658 m = PHYS_TO_VM_PAGE(pa);
4659 KASSERT(m->phys_addr == pa,
4660 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
4661 m, (uintmax_t)m->phys_addr,
4664 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
4665 m < &vm_page_array[vm_page_array_size],
4666 ("pmap_remove_pages: bad pte %#jx",
4670 * Because this pmap is not active on other
4671 * processors, the dirty bit cannot have
4672 * changed state since we last loaded pte.
4677 * Update the vm_page_t clean/reference bits.
4679 if (pmap_pte_dirty(pmap, tpte)) {
4682 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
4691 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(&lock, m);
4694 pc->pc_map[field] |= bitmask;
4697 pmap_resident_count_dec(pmap,
4698 L2_SIZE / PAGE_SIZE);
4699 pvh = pa_to_pvh(tpte & ~ATTR_MASK);
4700 TAILQ_REMOVE(&pvh->pv_list, pv,pv_next);
4702 if (TAILQ_EMPTY(&pvh->pv_list)) {
4703 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
4704 if ((mt->a.flags & PGA_WRITEABLE) != 0 &&
4705 TAILQ_EMPTY(&mt->md.pv_list))
4706 vm_page_aflag_clear(mt, PGA_WRITEABLE);
4708 ml3 = pmap_remove_pt_page(pmap,
4711 KASSERT(ml3->valid == VM_PAGE_BITS_ALL,
4712 ("pmap_remove_pages: l3 page not promoted"));
4713 pmap_resident_count_dec(pmap,1);
4714 KASSERT(ml3->ref_count == NL3PG,
4715 ("pmap_remove_pages: l3 page ref count error"));
4717 pmap_add_delayed_free_list(ml3,
4722 pmap_resident_count_dec(pmap, 1);
4723 TAILQ_REMOVE(&m->md.pv_list, pv,
4726 if ((m->a.flags & PGA_WRITEABLE) != 0 &&
4727 TAILQ_EMPTY(&m->md.pv_list) &&
4728 (m->flags & PG_FICTITIOUS) == 0) {
4730 VM_PAGE_TO_PHYS(m));
4731 if (TAILQ_EMPTY(&pvh->pv_list))
4732 vm_page_aflag_clear(m,
4737 pmap_unuse_pt(pmap, pv->pv_va, pmap_load(pde),
4742 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
4743 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
4744 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
4746 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4752 pmap_invalidate_all(pmap);
4754 vm_page_free_pages_toq(&free, true);
4758 * This is used to check if a page has been accessed or modified.
4761 pmap_page_test_mappings(vm_page_t m, boolean_t accessed, boolean_t modified)
4763 struct rwlock *lock;
4765 struct md_page *pvh;
4766 pt_entry_t *pte, mask, value;
4768 int lvl, md_gen, pvh_gen;
4772 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
4775 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4777 PMAP_ASSERT_STAGE1(pmap);
4778 if (!PMAP_TRYLOCK(pmap)) {
4779 md_gen = m->md.pv_gen;
4783 if (md_gen != m->md.pv_gen) {
4788 pte = pmap_pte(pmap, pv->pv_va, &lvl);
4790 ("pmap_page_test_mappings: Invalid level %d", lvl));
4794 mask |= ATTR_S1_AP_RW_BIT;
4795 value |= ATTR_S1_AP(ATTR_S1_AP_RW);
4798 mask |= ATTR_AF | ATTR_DESCR_MASK;
4799 value |= ATTR_AF | L3_PAGE;
4801 rv = (pmap_load(pte) & mask) == value;
4806 if ((m->flags & PG_FICTITIOUS) == 0) {
4807 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4808 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4810 PMAP_ASSERT_STAGE1(pmap);
4811 if (!PMAP_TRYLOCK(pmap)) {
4812 md_gen = m->md.pv_gen;
4813 pvh_gen = pvh->pv_gen;
4817 if (md_gen != m->md.pv_gen ||
4818 pvh_gen != pvh->pv_gen) {
4823 pte = pmap_pte(pmap, pv->pv_va, &lvl);
4825 ("pmap_page_test_mappings: Invalid level %d", lvl));
4829 mask |= ATTR_S1_AP_RW_BIT;
4830 value |= ATTR_S1_AP(ATTR_S1_AP_RW);
4833 mask |= ATTR_AF | ATTR_DESCR_MASK;
4834 value |= ATTR_AF | L2_BLOCK;
4836 rv = (pmap_load(pte) & mask) == value;
4850 * Return whether or not the specified physical page was modified
4851 * in any physical maps.
4854 pmap_is_modified(vm_page_t m)
4857 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4858 ("pmap_is_modified: page %p is not managed", m));
4861 * If the page is not busied then this check is racy.
4863 if (!pmap_page_is_write_mapped(m))
4865 return (pmap_page_test_mappings(m, FALSE, TRUE));
4869 * pmap_is_prefaultable:
4871 * Return whether or not the specified virtual address is eligible
4875 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
4883 pte = pmap_pte(pmap, addr, &lvl);
4884 if (pte != NULL && pmap_load(pte) != 0) {
4892 * pmap_is_referenced:
4894 * Return whether or not the specified physical page was referenced
4895 * in any physical maps.
4898 pmap_is_referenced(vm_page_t m)
4901 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4902 ("pmap_is_referenced: page %p is not managed", m));
4903 return (pmap_page_test_mappings(m, TRUE, FALSE));
4907 * Clear the write and modified bits in each of the given page's mappings.
4910 pmap_remove_write(vm_page_t m)
4912 struct md_page *pvh;
4914 struct rwlock *lock;
4915 pv_entry_t next_pv, pv;
4916 pt_entry_t oldpte, *pte;
4918 int lvl, md_gen, pvh_gen;
4920 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4921 ("pmap_remove_write: page %p is not managed", m));
4922 vm_page_assert_busied(m);
4924 if (!pmap_page_is_write_mapped(m))
4926 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
4927 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
4928 pa_to_pvh(VM_PAGE_TO_PHYS(m));
4931 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
4933 PMAP_ASSERT_STAGE1(pmap);
4934 if (!PMAP_TRYLOCK(pmap)) {
4935 pvh_gen = pvh->pv_gen;
4939 if (pvh_gen != pvh->pv_gen) {
4946 pte = pmap_pte(pmap, pv->pv_va, &lvl);
4947 if ((pmap_load(pte) & ATTR_SW_DBM) != 0)
4948 (void)pmap_demote_l2_locked(pmap, pte, va, &lock);
4949 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
4950 ("inconsistent pv lock %p %p for page %p",
4951 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
4954 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4956 PMAP_ASSERT_STAGE1(pmap);
4957 if (!PMAP_TRYLOCK(pmap)) {
4958 pvh_gen = pvh->pv_gen;
4959 md_gen = m->md.pv_gen;
4963 if (pvh_gen != pvh->pv_gen ||
4964 md_gen != m->md.pv_gen) {
4970 pte = pmap_pte(pmap, pv->pv_va, &lvl);
4971 oldpte = pmap_load(pte);
4973 if ((oldpte & ATTR_SW_DBM) != 0) {
4974 if (!atomic_fcmpset_long(pte, &oldpte,
4975 (oldpte | ATTR_S1_AP_RW_BIT) & ~ATTR_SW_DBM))
4977 if ((oldpte & ATTR_S1_AP_RW_BIT) ==
4978 ATTR_S1_AP(ATTR_S1_AP_RW))
4980 pmap_invalidate_page(pmap, pv->pv_va);
4985 vm_page_aflag_clear(m, PGA_WRITEABLE);
4989 * pmap_ts_referenced:
4991 * Return a count of reference bits for a page, clearing those bits.
4992 * It is not necessary for every reference bit to be cleared, but it
4993 * is necessary that 0 only be returned when there are truly no
4994 * reference bits set.
4996 * As an optimization, update the page's dirty field if a modified bit is
4997 * found while counting reference bits. This opportunistic update can be
4998 * performed at low cost and can eliminate the need for some future calls
4999 * to pmap_is_modified(). However, since this function stops after
5000 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
5001 * dirty pages. Those dirty pages will only be detected by a future call
5002 * to pmap_is_modified().
5005 pmap_ts_referenced(vm_page_t m)
5007 struct md_page *pvh;
5010 struct rwlock *lock;
5011 pd_entry_t *pde, tpde;
5012 pt_entry_t *pte, tpte;
5015 int cleared, lvl, md_gen, not_cleared, pvh_gen;
5016 struct spglist free;
5018 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5019 ("pmap_ts_referenced: page %p is not managed", m));
5022 pa = VM_PAGE_TO_PHYS(m);
5023 lock = PHYS_TO_PV_LIST_LOCK(pa);
5024 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : pa_to_pvh(pa);
5028 if ((pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
5029 goto small_mappings;
5035 if (!PMAP_TRYLOCK(pmap)) {
5036 pvh_gen = pvh->pv_gen;
5040 if (pvh_gen != pvh->pv_gen) {
5046 pde = pmap_pde(pmap, pv->pv_va, &lvl);
5047 KASSERT(pde != NULL, ("pmap_ts_referenced: no l1 table found"));
5049 ("pmap_ts_referenced: invalid pde level %d", lvl));
5050 tpde = pmap_load(pde);
5051 KASSERT((tpde & ATTR_DESCR_MASK) == L1_TABLE,
5052 ("pmap_ts_referenced: found an invalid l1 table"));
5053 pte = pmap_l1_to_l2(pde, pv->pv_va);
5054 tpte = pmap_load(pte);
5055 if (pmap_pte_dirty(pmap, tpte)) {
5057 * Although "tpte" is mapping a 2MB page, because
5058 * this function is called at a 4KB page granularity,
5059 * we only update the 4KB page under test.
5064 if ((tpte & ATTR_AF) != 0) {
5066 * Since this reference bit is shared by 512 4KB pages,
5067 * it should not be cleared every time it is tested.
5068 * Apply a simple "hash" function on the physical page
5069 * number, the virtual superpage number, and the pmap
5070 * address to select one 4KB page out of the 512 on
5071 * which testing the reference bit will result in
5072 * clearing that reference bit. This function is
5073 * designed to avoid the selection of the same 4KB page
5074 * for every 2MB page mapping.
5076 * On demotion, a mapping that hasn't been referenced
5077 * is simply destroyed. To avoid the possibility of a
5078 * subsequent page fault on a demoted wired mapping,
5079 * always leave its reference bit set. Moreover,
5080 * since the superpage is wired, the current state of
5081 * its reference bit won't affect page replacement.
5083 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> L2_SHIFT) ^
5084 (uintptr_t)pmap) & (Ln_ENTRIES - 1)) == 0 &&
5085 (tpte & ATTR_SW_WIRED) == 0) {
5086 pmap_clear_bits(pte, ATTR_AF);
5087 pmap_invalidate_page(pmap, pv->pv_va);
5093 /* Rotate the PV list if it has more than one entry. */
5094 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
5095 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
5096 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
5099 if (cleared + not_cleared >= PMAP_TS_REFERENCED_MAX)
5101 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
5103 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
5110 if (!PMAP_TRYLOCK(pmap)) {
5111 pvh_gen = pvh->pv_gen;
5112 md_gen = m->md.pv_gen;
5116 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
5121 pde = pmap_pde(pmap, pv->pv_va, &lvl);
5122 KASSERT(pde != NULL, ("pmap_ts_referenced: no l2 table found"));
5124 ("pmap_ts_referenced: invalid pde level %d", lvl));
5125 tpde = pmap_load(pde);
5126 KASSERT((tpde & ATTR_DESCR_MASK) == L2_TABLE,
5127 ("pmap_ts_referenced: found an invalid l2 table"));
5128 pte = pmap_l2_to_l3(pde, pv->pv_va);
5129 tpte = pmap_load(pte);
5130 if (pmap_pte_dirty(pmap, tpte))
5132 if ((tpte & ATTR_AF) != 0) {
5133 if ((tpte & ATTR_SW_WIRED) == 0) {
5134 pmap_clear_bits(pte, ATTR_AF);
5135 pmap_invalidate_page(pmap, pv->pv_va);
5141 /* Rotate the PV list if it has more than one entry. */
5142 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
5143 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
5144 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
5147 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && cleared +
5148 not_cleared < PMAP_TS_REFERENCED_MAX);
5151 vm_page_free_pages_toq(&free, true);
5152 return (cleared + not_cleared);
5156 * Apply the given advice to the specified range of addresses within the
5157 * given pmap. Depending on the advice, clear the referenced and/or
5158 * modified flags in each mapping and set the mapped page's dirty field.
5161 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
5163 struct rwlock *lock;
5164 vm_offset_t va, va_next;
5166 pd_entry_t *l0, *l1, *l2, oldl2;
5167 pt_entry_t *l3, oldl3;
5169 PMAP_ASSERT_STAGE1(pmap);
5171 if (advice != MADV_DONTNEED && advice != MADV_FREE)
5175 for (; sva < eva; sva = va_next) {
5176 l0 = pmap_l0(pmap, sva);
5177 if (pmap_load(l0) == 0) {
5178 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
5183 l1 = pmap_l0_to_l1(l0, sva);
5184 if (pmap_load(l1) == 0) {
5185 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
5190 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
5193 l2 = pmap_l1_to_l2(l1, sva);
5194 oldl2 = pmap_load(l2);
5197 if ((oldl2 & ATTR_DESCR_MASK) == L2_BLOCK) {
5198 if ((oldl2 & ATTR_SW_MANAGED) == 0)
5201 if (!pmap_demote_l2_locked(pmap, l2, sva, &lock)) {
5206 * The 2MB page mapping was destroyed.
5212 * Unless the page mappings are wired, remove the
5213 * mapping to a single page so that a subsequent
5214 * access may repromote. Choosing the last page
5215 * within the address range [sva, min(va_next, eva))
5216 * generally results in more repromotions. Since the
5217 * underlying page table page is fully populated, this
5218 * removal never frees a page table page.
5220 if ((oldl2 & ATTR_SW_WIRED) == 0) {
5226 ("pmap_advise: no address gap"));
5227 l3 = pmap_l2_to_l3(l2, va);
5228 KASSERT(pmap_load(l3) != 0,
5229 ("pmap_advise: invalid PTE"));
5230 pmap_remove_l3(pmap, l3, va, pmap_load(l2),
5236 KASSERT((pmap_load(l2) & ATTR_DESCR_MASK) == L2_TABLE,
5237 ("pmap_advise: invalid L2 entry after demotion"));
5241 for (l3 = pmap_l2_to_l3(l2, sva); sva != va_next; l3++,
5243 oldl3 = pmap_load(l3);
5244 if ((oldl3 & (ATTR_SW_MANAGED | ATTR_DESCR_MASK)) !=
5245 (ATTR_SW_MANAGED | L3_PAGE))
5247 else if (pmap_pte_dirty(pmap, oldl3)) {
5248 if (advice == MADV_DONTNEED) {
5250 * Future calls to pmap_is_modified()
5251 * can be avoided by making the page
5254 m = PHYS_TO_VM_PAGE(oldl3 & ~ATTR_MASK);
5257 while (!atomic_fcmpset_long(l3, &oldl3,
5258 (oldl3 & ~ATTR_AF) |
5259 ATTR_S1_AP(ATTR_S1_AP_RO)))
5261 } else if ((oldl3 & ATTR_AF) != 0)
5262 pmap_clear_bits(l3, ATTR_AF);
5269 if (va != va_next) {
5270 pmap_invalidate_range(pmap, va, sva);
5275 pmap_invalidate_range(pmap, va, sva);
5281 * Clear the modify bits on the specified physical page.
5284 pmap_clear_modify(vm_page_t m)
5286 struct md_page *pvh;
5287 struct rwlock *lock;
5289 pv_entry_t next_pv, pv;
5290 pd_entry_t *l2, oldl2;
5291 pt_entry_t *l3, oldl3;
5293 int md_gen, pvh_gen;
5295 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5296 ("pmap_clear_modify: page %p is not managed", m));
5297 vm_page_assert_busied(m);
5299 if (!pmap_page_is_write_mapped(m))
5301 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
5302 pa_to_pvh(VM_PAGE_TO_PHYS(m));
5303 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5306 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
5308 PMAP_ASSERT_STAGE1(pmap);
5309 if (!PMAP_TRYLOCK(pmap)) {
5310 pvh_gen = pvh->pv_gen;
5314 if (pvh_gen != pvh->pv_gen) {
5320 l2 = pmap_l2(pmap, va);
5321 oldl2 = pmap_load(l2);
5322 /* If oldl2 has ATTR_SW_DBM set, then it is also dirty. */
5323 if ((oldl2 & ATTR_SW_DBM) != 0 &&
5324 pmap_demote_l2_locked(pmap, l2, va, &lock) &&
5325 (oldl2 & ATTR_SW_WIRED) == 0) {
5327 * Write protect the mapping to a single page so that
5328 * a subsequent write access may repromote.
5330 va += VM_PAGE_TO_PHYS(m) - (oldl2 & ~ATTR_MASK);
5331 l3 = pmap_l2_to_l3(l2, va);
5332 oldl3 = pmap_load(l3);
5333 while (!atomic_fcmpset_long(l3, &oldl3,
5334 (oldl3 & ~ATTR_SW_DBM) | ATTR_S1_AP(ATTR_S1_AP_RO)))
5337 pmap_invalidate_page(pmap, va);
5341 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5343 PMAP_ASSERT_STAGE1(pmap);
5344 if (!PMAP_TRYLOCK(pmap)) {
5345 md_gen = m->md.pv_gen;
5346 pvh_gen = pvh->pv_gen;
5350 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
5355 l2 = pmap_l2(pmap, pv->pv_va);
5356 l3 = pmap_l2_to_l3(l2, pv->pv_va);
5357 oldl3 = pmap_load(l3);
5358 if (pmap_l3_valid(oldl3) &&
5359 (oldl3 & (ATTR_S1_AP_RW_BIT | ATTR_SW_DBM)) == ATTR_SW_DBM){
5360 pmap_set_bits(l3, ATTR_S1_AP(ATTR_S1_AP_RO));
5361 pmap_invalidate_page(pmap, pv->pv_va);
5369 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
5371 struct pmap_preinit_mapping *ppim;
5372 vm_offset_t va, offset;
5375 int i, lvl, l2_blocks, free_l2_count, start_idx;
5377 if (!vm_initialized) {
5379 * No L3 ptables so map entire L2 blocks where start VA is:
5380 * preinit_map_va + start_idx * L2_SIZE
5381 * There may be duplicate mappings (multiple VA -> same PA) but
5382 * ARM64 dcache is always PIPT so that's acceptable.
5387 /* Calculate how many L2 blocks are needed for the mapping */
5388 l2_blocks = (roundup2(pa + size, L2_SIZE) -
5389 rounddown2(pa, L2_SIZE)) >> L2_SHIFT;
5391 offset = pa & L2_OFFSET;
5393 if (preinit_map_va == 0)
5396 /* Map 2MiB L2 blocks from reserved VA space */
5400 /* Find enough free contiguous VA space */
5401 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5402 ppim = pmap_preinit_mapping + i;
5403 if (free_l2_count > 0 && ppim->pa != 0) {
5404 /* Not enough space here */
5410 if (ppim->pa == 0) {
5412 if (start_idx == -1)
5415 if (free_l2_count == l2_blocks)
5419 if (free_l2_count != l2_blocks)
5420 panic("%s: too many preinit mappings", __func__);
5422 va = preinit_map_va + (start_idx * L2_SIZE);
5423 for (i = start_idx; i < start_idx + l2_blocks; i++) {
5424 /* Mark entries as allocated */
5425 ppim = pmap_preinit_mapping + i;
5427 ppim->va = va + offset;
5432 pa = rounddown2(pa, L2_SIZE);
5433 for (i = 0; i < l2_blocks; i++) {
5434 pde = pmap_pde(kernel_pmap, va, &lvl);
5435 KASSERT(pde != NULL,
5436 ("pmap_mapbios: Invalid page entry, va: 0x%lx",
5439 ("pmap_mapbios: Invalid level %d", lvl));
5441 /* Insert L2_BLOCK */
5442 l2 = pmap_l1_to_l2(pde, va);
5444 pa | ATTR_DEFAULT | ATTR_S1_XN |
5445 ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK) | L2_BLOCK);
5450 pmap_invalidate_all(kernel_pmap);
5452 va = preinit_map_va + (start_idx * L2_SIZE);
5455 /* kva_alloc may be used to map the pages */
5456 offset = pa & PAGE_MASK;
5457 size = round_page(offset + size);
5459 va = kva_alloc(size);
5461 panic("%s: Couldn't allocate KVA", __func__);
5463 pde = pmap_pde(kernel_pmap, va, &lvl);
5464 KASSERT(lvl == 2, ("pmap_mapbios: Invalid level %d", lvl));
5466 /* L3 table is linked */
5467 va = trunc_page(va);
5468 pa = trunc_page(pa);
5469 pmap_kenter(va, size, pa, memory_mapping_mode(pa));
5472 return ((void *)(va + offset));
5476 pmap_unmapbios(vm_offset_t va, vm_size_t size)
5478 struct pmap_preinit_mapping *ppim;
5479 vm_offset_t offset, tmpsize, va_trunc;
5482 int i, lvl, l2_blocks, block;
5486 (roundup2(va + size, L2_SIZE) - rounddown2(va, L2_SIZE)) >> L2_SHIFT;
5487 KASSERT(l2_blocks > 0, ("pmap_unmapbios: invalid size %lx", size));
5489 /* Remove preinit mapping */
5490 preinit_map = false;
5492 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5493 ppim = pmap_preinit_mapping + i;
5494 if (ppim->va == va) {
5495 KASSERT(ppim->size == size,
5496 ("pmap_unmapbios: size mismatch"));
5501 offset = block * L2_SIZE;
5502 va_trunc = rounddown2(va, L2_SIZE) + offset;
5504 /* Remove L2_BLOCK */
5505 pde = pmap_pde(kernel_pmap, va_trunc, &lvl);
5506 KASSERT(pde != NULL,
5507 ("pmap_unmapbios: Invalid page entry, va: 0x%lx",
5509 l2 = pmap_l1_to_l2(pde, va_trunc);
5512 if (block == (l2_blocks - 1))
5518 pmap_invalidate_all(kernel_pmap);
5522 /* Unmap the pages reserved with kva_alloc. */
5523 if (vm_initialized) {
5524 offset = va & PAGE_MASK;
5525 size = round_page(offset + size);
5526 va = trunc_page(va);
5528 pde = pmap_pde(kernel_pmap, va, &lvl);
5529 KASSERT(pde != NULL,
5530 ("pmap_unmapbios: Invalid page entry, va: 0x%lx", va));
5531 KASSERT(lvl == 2, ("pmap_unmapbios: Invalid level %d", lvl));
5533 /* Unmap and invalidate the pages */
5534 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
5535 pmap_kremove(va + tmpsize);
5542 * Sets the memory attribute for the specified page.
5545 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
5548 m->md.pv_memattr = ma;
5551 * If "m" is a normal page, update its direct mapping. This update
5552 * can be relied upon to perform any cache operations that are
5553 * required for data coherence.
5555 if ((m->flags & PG_FICTITIOUS) == 0 &&
5556 pmap_change_attr(PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)), PAGE_SIZE,
5557 m->md.pv_memattr) != 0)
5558 panic("memory attribute change on the direct map failed");
5562 * Changes the specified virtual address range's memory type to that given by
5563 * the parameter "mode". The specified virtual address range must be
5564 * completely contained within either the direct map or the kernel map. If
5565 * the virtual address range is contained within the kernel map, then the
5566 * memory type for each of the corresponding ranges of the direct map is also
5567 * changed. (The corresponding ranges of the direct map are those ranges that
5568 * map the same physical pages as the specified virtual address range.) These
5569 * changes to the direct map are necessary because Intel describes the
5570 * behavior of their processors as "undefined" if two or more mappings to the
5571 * same physical page have different memory types.
5573 * Returns zero if the change completed successfully, and either EINVAL or
5574 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
5575 * of the virtual address range was not mapped, and ENOMEM is returned if
5576 * there was insufficient memory available to complete the change. In the
5577 * latter case, the memory type may have been changed on some part of the
5578 * virtual address range or the direct map.
5581 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
5585 PMAP_LOCK(kernel_pmap);
5586 error = pmap_change_attr_locked(va, size, mode);
5587 PMAP_UNLOCK(kernel_pmap);
5592 pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode)
5594 vm_offset_t base, offset, tmpva;
5595 pt_entry_t l3, *pte, *newpte;
5598 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
5599 base = trunc_page(va);
5600 offset = va & PAGE_MASK;
5601 size = round_page(offset + size);
5603 if (!VIRT_IN_DMAP(base) &&
5604 !(base >= VM_MIN_KERNEL_ADDRESS && base < VM_MAX_KERNEL_ADDRESS))
5607 for (tmpva = base; tmpva < base + size; ) {
5608 pte = pmap_pte(kernel_pmap, tmpva, &lvl);
5612 if ((pmap_load(pte) & ATTR_S1_IDX_MASK) == ATTR_S1_IDX(mode)) {
5614 * We already have the correct attribute,
5615 * ignore this entry.
5619 panic("Invalid DMAP table level: %d\n", lvl);
5621 tmpva = (tmpva & ~L1_OFFSET) + L1_SIZE;
5624 tmpva = (tmpva & ~L2_OFFSET) + L2_SIZE;
5632 * Split the entry to an level 3 table, then
5633 * set the new attribute.
5637 panic("Invalid DMAP table level: %d\n", lvl);
5639 newpte = pmap_demote_l1(kernel_pmap, pte,
5640 tmpva & ~L1_OFFSET);
5643 pte = pmap_l1_to_l2(pte, tmpva);
5645 newpte = pmap_demote_l2(kernel_pmap, pte,
5649 pte = pmap_l2_to_l3(pte, tmpva);
5651 /* Update the entry */
5652 l3 = pmap_load(pte);
5653 l3 &= ~ATTR_S1_IDX_MASK;
5654 l3 |= ATTR_S1_IDX(mode);
5655 if (mode == VM_MEMATTR_DEVICE)
5658 pmap_update_entry(kernel_pmap, pte, l3, tmpva,
5662 * If moving to a non-cacheable entry flush
5665 if (mode == VM_MEMATTR_UNCACHEABLE)
5666 cpu_dcache_wbinv_range(tmpva, L3_SIZE);
5678 * Create an L2 table to map all addresses within an L1 mapping.
5681 pmap_demote_l1(pmap_t pmap, pt_entry_t *l1, vm_offset_t va)
5683 pt_entry_t *l2, newl2, oldl1;
5685 vm_paddr_t l2phys, phys;
5689 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5690 oldl1 = pmap_load(l1);
5691 KASSERT((oldl1 & ATTR_DESCR_MASK) == L1_BLOCK,
5692 ("pmap_demote_l1: Demoting a non-block entry"));
5693 KASSERT((va & L1_OFFSET) == 0,
5694 ("pmap_demote_l1: Invalid virtual address %#lx", va));
5695 KASSERT((oldl1 & ATTR_SW_MANAGED) == 0,
5696 ("pmap_demote_l1: Level 1 table shouldn't be managed"));
5699 if (va <= (vm_offset_t)l1 && va + L1_SIZE > (vm_offset_t)l1) {
5700 tmpl1 = kva_alloc(PAGE_SIZE);
5705 if ((ml2 = vm_page_alloc(NULL, 0, VM_ALLOC_INTERRUPT |
5706 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
5707 CTR2(KTR_PMAP, "pmap_demote_l1: failure for va %#lx"
5708 " in pmap %p", va, pmap);
5712 l2phys = VM_PAGE_TO_PHYS(ml2);
5713 l2 = (pt_entry_t *)PHYS_TO_DMAP(l2phys);
5715 /* Address the range points at */
5716 phys = oldl1 & ~ATTR_MASK;
5717 /* The attributed from the old l1 table to be copied */
5718 newl2 = oldl1 & ATTR_MASK;
5720 /* Create the new entries */
5721 for (i = 0; i < Ln_ENTRIES; i++) {
5722 l2[i] = newl2 | phys;
5725 KASSERT(l2[0] == ((oldl1 & ~ATTR_DESCR_MASK) | L2_BLOCK),
5726 ("Invalid l2 page (%lx != %lx)", l2[0],
5727 (oldl1 & ~ATTR_DESCR_MASK) | L2_BLOCK));
5730 pmap_kenter(tmpl1, PAGE_SIZE,
5731 DMAP_TO_PHYS((vm_offset_t)l1) & ~L3_OFFSET,
5732 VM_MEMATTR_WRITE_BACK);
5733 l1 = (pt_entry_t *)(tmpl1 + ((vm_offset_t)l1 & PAGE_MASK));
5736 pmap_update_entry(pmap, l1, l2phys | L1_TABLE, va, PAGE_SIZE);
5739 pmap_kremove(tmpl1);
5740 kva_free(tmpl1, PAGE_SIZE);
5747 pmap_fill_l3(pt_entry_t *firstl3, pt_entry_t newl3)
5751 for (l3 = firstl3; l3 - firstl3 < Ln_ENTRIES; l3++) {
5758 pmap_demote_l2_abort(pmap_t pmap, vm_offset_t va, pt_entry_t *l2,
5759 struct rwlock **lockp)
5761 struct spglist free;
5764 (void)pmap_remove_l2(pmap, l2, va, pmap_load(pmap_l1(pmap, va)), &free,
5766 vm_page_free_pages_toq(&free, true);
5770 * Create an L3 table to map all addresses within an L2 mapping.
5773 pmap_demote_l2_locked(pmap_t pmap, pt_entry_t *l2, vm_offset_t va,
5774 struct rwlock **lockp)
5776 pt_entry_t *l3, newl3, oldl2;
5781 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5782 PMAP_ASSERT_STAGE1(pmap);
5784 oldl2 = pmap_load(l2);
5785 KASSERT((oldl2 & ATTR_DESCR_MASK) == L2_BLOCK,
5786 ("pmap_demote_l2: Demoting a non-block entry"));
5790 if (va <= (vm_offset_t)l2 && va + L2_SIZE > (vm_offset_t)l2) {
5791 tmpl2 = kva_alloc(PAGE_SIZE);
5797 * Invalidate the 2MB page mapping and return "failure" if the
5798 * mapping was never accessed.
5800 if ((oldl2 & ATTR_AF) == 0) {
5801 KASSERT((oldl2 & ATTR_SW_WIRED) == 0,
5802 ("pmap_demote_l2: a wired mapping is missing ATTR_AF"));
5803 pmap_demote_l2_abort(pmap, va, l2, lockp);
5804 CTR2(KTR_PMAP, "pmap_demote_l2: failure for va %#lx in pmap %p",
5809 if ((ml3 = pmap_remove_pt_page(pmap, va)) == NULL) {
5810 KASSERT((oldl2 & ATTR_SW_WIRED) == 0,
5811 ("pmap_demote_l2: page table page for a wired mapping"
5815 * If the page table page is missing and the mapping
5816 * is for a kernel address, the mapping must belong to
5817 * the direct map. Page table pages are preallocated
5818 * for every other part of the kernel address space,
5819 * so the direct map region is the only part of the
5820 * kernel address space that must be handled here.
5822 KASSERT(va < VM_MAXUSER_ADDRESS || VIRT_IN_DMAP(va),
5823 ("pmap_demote_l2: No saved mpte for va %#lx", va));
5826 * If the 2MB page mapping belongs to the direct map
5827 * region of the kernel's address space, then the page
5828 * allocation request specifies the highest possible
5829 * priority (VM_ALLOC_INTERRUPT). Otherwise, the
5830 * priority is normal.
5832 ml3 = vm_page_alloc(NULL, pmap_l2_pindex(va),
5833 (VIRT_IN_DMAP(va) ? VM_ALLOC_INTERRUPT : VM_ALLOC_NORMAL) |
5834 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED);
5837 * If the allocation of the new page table page fails,
5838 * invalidate the 2MB page mapping and return "failure".
5841 pmap_demote_l2_abort(pmap, va, l2, lockp);
5842 CTR2(KTR_PMAP, "pmap_demote_l2: failure for va %#lx"
5843 " in pmap %p", va, pmap);
5847 if (va < VM_MAXUSER_ADDRESS) {
5848 ml3->ref_count = NL3PG;
5849 pmap_resident_count_inc(pmap, 1);
5852 l3phys = VM_PAGE_TO_PHYS(ml3);
5853 l3 = (pt_entry_t *)PHYS_TO_DMAP(l3phys);
5854 newl3 = (oldl2 & ~ATTR_DESCR_MASK) | L3_PAGE;
5855 KASSERT((oldl2 & (ATTR_S1_AP_RW_BIT | ATTR_SW_DBM)) !=
5856 (ATTR_S1_AP(ATTR_S1_AP_RO) | ATTR_SW_DBM),
5857 ("pmap_demote_l2: L2 entry is writeable but not dirty"));
5860 * If the page table page is not leftover from an earlier promotion,
5861 * or the mapping attributes have changed, (re)initialize the L3 table.
5863 * When pmap_update_entry() clears the old L2 mapping, it (indirectly)
5864 * performs a dsb(). That dsb() ensures that the stores for filling
5865 * "l3" are visible before "l3" is added to the page table.
5867 if (ml3->valid == 0 || (l3[0] & ATTR_MASK) != (newl3 & ATTR_MASK))
5868 pmap_fill_l3(l3, newl3);
5871 * Map the temporary page so we don't lose access to the l2 table.
5874 pmap_kenter(tmpl2, PAGE_SIZE,
5875 DMAP_TO_PHYS((vm_offset_t)l2) & ~L3_OFFSET,
5876 VM_MEMATTR_WRITE_BACK);
5877 l2 = (pt_entry_t *)(tmpl2 + ((vm_offset_t)l2 & PAGE_MASK));
5881 * The spare PV entries must be reserved prior to demoting the
5882 * mapping, that is, prior to changing the PDE. Otherwise, the state
5883 * of the L2 and the PV lists will be inconsistent, which can result
5884 * in reclaim_pv_chunk() attempting to remove a PV entry from the
5885 * wrong PV list and pmap_pv_demote_l2() failing to find the expected
5886 * PV entry for the 2MB page mapping that is being demoted.
5888 if ((oldl2 & ATTR_SW_MANAGED) != 0)
5889 reserve_pv_entries(pmap, Ln_ENTRIES - 1, lockp);
5892 * Pass PAGE_SIZE so that a single TLB invalidation is performed on
5893 * the 2MB page mapping.
5895 pmap_update_entry(pmap, l2, l3phys | L2_TABLE, va, PAGE_SIZE);
5898 * Demote the PV entry.
5900 if ((oldl2 & ATTR_SW_MANAGED) != 0)
5901 pmap_pv_demote_l2(pmap, va, oldl2 & ~ATTR_MASK, lockp);
5903 atomic_add_long(&pmap_l2_demotions, 1);
5904 CTR3(KTR_PMAP, "pmap_demote_l2: success for va %#lx"
5905 " in pmap %p %lx", va, pmap, l3[0]);
5909 pmap_kremove(tmpl2);
5910 kva_free(tmpl2, PAGE_SIZE);
5918 pmap_demote_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t va)
5920 struct rwlock *lock;
5924 l3 = pmap_demote_l2_locked(pmap, l2, va, &lock);
5931 * Perform the pmap work for mincore(2). If the page is not both referenced and
5932 * modified by this pmap, returns its physical address so that the caller can
5933 * find other mappings.
5936 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *pap)
5938 pt_entry_t *pte, tpte;
5939 vm_paddr_t mask, pa;
5943 PMAP_ASSERT_STAGE1(pmap);
5945 pte = pmap_pte(pmap, addr, &lvl);
5947 tpte = pmap_load(pte);
5960 panic("pmap_mincore: invalid level %d", lvl);
5963 managed = (tpte & ATTR_SW_MANAGED) != 0;
5964 val = MINCORE_INCORE;
5966 val |= MINCORE_PSIND(3 - lvl);
5967 if ((managed && pmap_pte_dirty(pmap, tpte)) || (!managed &&
5968 (tpte & ATTR_S1_AP_RW_BIT) == ATTR_S1_AP(ATTR_S1_AP_RW)))
5969 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
5970 if ((tpte & ATTR_AF) == ATTR_AF)
5971 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
5973 pa = (tpte & ~ATTR_MASK) | (addr & mask);
5979 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
5980 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) && managed) {
5988 * Garbage collect every ASID that is neither active on a processor nor
5992 pmap_reset_asid_set(pmap_t pmap)
5995 int asid, cpuid, epoch;
5996 struct asid_set *set;
5997 enum pmap_stage stage;
5999 set = pmap->pm_asid_set;
6000 stage = pmap->pm_stage;
6002 set = pmap->pm_asid_set;
6003 KASSERT(set != NULL, ("%s: NULL asid set", __func__));
6004 mtx_assert(&set->asid_set_mutex, MA_OWNED);
6007 * Ensure that the store to asid_epoch is globally visible before the
6008 * loads from pc_curpmap are performed.
6010 epoch = set->asid_epoch + 1;
6011 if (epoch == INT_MAX)
6013 set->asid_epoch = epoch;
6015 if (stage == PM_STAGE1) {
6016 __asm __volatile("tlbi vmalle1is");
6018 KASSERT(pmap_clean_stage2_tlbi != NULL,
6019 ("%s: Unset stage 2 tlb invalidation callback\n",
6021 pmap_clean_stage2_tlbi();
6024 bit_nclear(set->asid_set, ASID_FIRST_AVAILABLE,
6025 set->asid_set_size - 1);
6026 CPU_FOREACH(cpuid) {
6027 if (cpuid == curcpu)
6029 if (stage == PM_STAGE1) {
6030 curpmap = pcpu_find(cpuid)->pc_curpmap;
6031 PMAP_ASSERT_STAGE1(pmap);
6033 curpmap = pcpu_find(cpuid)->pc_curvmpmap;
6034 if (curpmap == NULL)
6036 PMAP_ASSERT_STAGE2(pmap);
6038 KASSERT(curpmap->pm_asid_set == set, ("Incorrect set"));
6039 asid = COOKIE_TO_ASID(curpmap->pm_cookie);
6042 bit_set(set->asid_set, asid);
6043 curpmap->pm_cookie = COOKIE_FROM(asid, epoch);
6048 * Allocate a new ASID for the specified pmap.
6051 pmap_alloc_asid(pmap_t pmap)
6053 struct asid_set *set;
6056 set = pmap->pm_asid_set;
6057 KASSERT(set != NULL, ("%s: NULL asid set", __func__));
6059 mtx_lock_spin(&set->asid_set_mutex);
6062 * While this processor was waiting to acquire the asid set mutex,
6063 * pmap_reset_asid_set() running on another processor might have
6064 * updated this pmap's cookie to the current epoch. In which case, we
6065 * don't need to allocate a new ASID.
6067 if (COOKIE_TO_EPOCH(pmap->pm_cookie) == set->asid_epoch)
6070 bit_ffc_at(set->asid_set, set->asid_next, set->asid_set_size,
6072 if (new_asid == -1) {
6073 bit_ffc_at(set->asid_set, ASID_FIRST_AVAILABLE,
6074 set->asid_next, &new_asid);
6075 if (new_asid == -1) {
6076 pmap_reset_asid_set(pmap);
6077 bit_ffc_at(set->asid_set, ASID_FIRST_AVAILABLE,
6078 set->asid_set_size, &new_asid);
6079 KASSERT(new_asid != -1, ("ASID allocation failure"));
6082 bit_set(set->asid_set, new_asid);
6083 set->asid_next = new_asid + 1;
6084 pmap->pm_cookie = COOKIE_FROM(new_asid, set->asid_epoch);
6086 mtx_unlock_spin(&set->asid_set_mutex);
6090 * Compute the value that should be stored in ttbr0 to activate the specified
6091 * pmap. This value may change from time to time.
6094 pmap_to_ttbr0(pmap_t pmap)
6097 return (ASID_TO_OPERAND(COOKIE_TO_ASID(pmap->pm_cookie)) |
6102 pmap_activate_int(pmap_t pmap)
6104 struct asid_set *set;
6107 KASSERT(PCPU_GET(curpmap) != NULL, ("no active pmap"));
6108 KASSERT(pmap != kernel_pmap, ("kernel pmap activation"));
6110 if ((pmap->pm_stage == PM_STAGE1 && pmap == PCPU_GET(curpmap)) ||
6111 (pmap->pm_stage == PM_STAGE2 && pmap == PCPU_GET(curvmpmap))) {
6113 * Handle the possibility that the old thread was preempted
6114 * after an "ic" or "tlbi" instruction but before it performed
6115 * a "dsb" instruction. If the old thread migrates to a new
6116 * processor, its completion of a "dsb" instruction on that
6117 * new processor does not guarantee that the "ic" or "tlbi"
6118 * instructions performed on the old processor have completed.
6124 set = pmap->pm_asid_set;
6125 KASSERT(set != NULL, ("%s: NULL asid set", __func__));
6128 * Ensure that the store to curpmap is globally visible before the
6129 * load from asid_epoch is performed.
6131 if (pmap->pm_stage == PM_STAGE1)
6132 PCPU_SET(curpmap, pmap);
6134 PCPU_SET(curvmpmap, pmap);
6136 epoch = COOKIE_TO_EPOCH(pmap->pm_cookie);
6137 if (epoch >= 0 && epoch != set->asid_epoch)
6138 pmap_alloc_asid(pmap);
6140 if (pmap->pm_stage == PM_STAGE1) {
6141 set_ttbr0(pmap_to_ttbr0(pmap));
6142 if (PCPU_GET(bcast_tlbi_workaround) != 0)
6143 invalidate_local_icache();
6149 pmap_activate_vm(pmap_t pmap)
6152 PMAP_ASSERT_STAGE2(pmap);
6154 (void)pmap_activate_int(pmap);
6158 pmap_activate(struct thread *td)
6162 pmap = vmspace_pmap(td->td_proc->p_vmspace);
6163 PMAP_ASSERT_STAGE1(pmap);
6165 (void)pmap_activate_int(pmap);
6170 * To eliminate the unused parameter "old", we would have to add an instruction
6174 pmap_switch(struct thread *old __unused, struct thread *new)
6176 pcpu_bp_harden bp_harden;
6179 /* Store the new curthread */
6180 PCPU_SET(curthread, new);
6182 /* And the new pcb */
6184 PCPU_SET(curpcb, pcb);
6187 * TODO: We may need to flush the cache here if switching
6188 * to a user process.
6191 if (pmap_activate_int(vmspace_pmap(new->td_proc->p_vmspace))) {
6193 * Stop userspace from training the branch predictor against
6194 * other processes. This will call into a CPU specific
6195 * function that clears the branch predictor state.
6197 bp_harden = PCPU_GET(bp_harden);
6198 if (bp_harden != NULL)
6206 pmap_sync_icache(pmap_t pmap, vm_offset_t va, vm_size_t sz)
6209 PMAP_ASSERT_STAGE1(pmap);
6210 if (va >= VM_MIN_KERNEL_ADDRESS) {
6211 cpu_icache_sync_range(va, sz);
6216 /* Find the length of data in this page to flush */
6217 offset = va & PAGE_MASK;
6218 len = imin(PAGE_SIZE - offset, sz);
6221 /* Extract the physical address & find it in the DMAP */
6222 pa = pmap_extract(pmap, va);
6224 cpu_icache_sync_range(PHYS_TO_DMAP(pa), len);
6226 /* Move to the next page */
6229 /* Set the length for the next iteration */
6230 len = imin(PAGE_SIZE, sz);
6236 pmap_stage2_fault(pmap_t pmap, uint64_t esr, uint64_t far)
6239 pt_entry_t *ptep, pte;
6242 PMAP_ASSERT_STAGE2(pmap);
6245 /* Data and insn aborts use same encoding for FSC field. */
6246 dfsc = esr & ISS_DATA_DFSC_MASK;
6248 case ISS_DATA_DFSC_TF_L0:
6249 case ISS_DATA_DFSC_TF_L1:
6250 case ISS_DATA_DFSC_TF_L2:
6251 case ISS_DATA_DFSC_TF_L3:
6253 pdep = pmap_pde(pmap, far, &lvl);
6254 if (pdep == NULL || lvl != (dfsc - ISS_DATA_DFSC_TF_L1)) {
6261 ptep = pmap_l0_to_l1(pdep, far);
6264 ptep = pmap_l1_to_l2(pdep, far);
6267 ptep = pmap_l2_to_l3(pdep, far);
6270 panic("%s: Invalid pde level %d", __func__,lvl);
6274 case ISS_DATA_DFSC_AFF_L1:
6275 case ISS_DATA_DFSC_AFF_L2:
6276 case ISS_DATA_DFSC_AFF_L3:
6278 ptep = pmap_pte(pmap, far, &lvl);
6280 if (ptep != NULL && (pte = pmap_load(ptep)) != 0) {
6282 pmap_invalidate_vpipt_icache();
6285 * If accessing an executable page invalidate
6286 * the I-cache so it will be valid when we
6287 * continue execution in the guest. The D-cache
6288 * is assumed to already be clean to the Point
6291 if ((pte & ATTR_S2_XN_MASK) !=
6292 ATTR_S2_XN(ATTR_S2_XN_NONE)) {
6293 invalidate_icache();
6296 pmap_set_bits(ptep, ATTR_AF | ATTR_DESCR_VALID);
6307 pmap_fault(pmap_t pmap, uint64_t esr, uint64_t far)
6309 pt_entry_t pte, *ptep;
6316 ec = ESR_ELx_EXCEPTION(esr);
6318 case EXCP_INSN_ABORT_L:
6319 case EXCP_INSN_ABORT:
6320 case EXCP_DATA_ABORT_L:
6321 case EXCP_DATA_ABORT:
6327 if (pmap->pm_stage == PM_STAGE2)
6328 return (pmap_stage2_fault(pmap, esr, far));
6330 /* Data and insn aborts use same encoding for FSC field. */
6331 switch (esr & ISS_DATA_DFSC_MASK) {
6332 case ISS_DATA_DFSC_AFF_L1:
6333 case ISS_DATA_DFSC_AFF_L2:
6334 case ISS_DATA_DFSC_AFF_L3:
6336 ptep = pmap_pte(pmap, far, &lvl);
6338 pmap_set_bits(ptep, ATTR_AF);
6341 * XXXMJ as an optimization we could mark the entry
6342 * dirty if this is a write fault.
6347 case ISS_DATA_DFSC_PF_L1:
6348 case ISS_DATA_DFSC_PF_L2:
6349 case ISS_DATA_DFSC_PF_L3:
6350 if ((ec != EXCP_DATA_ABORT_L && ec != EXCP_DATA_ABORT) ||
6351 (esr & ISS_DATA_WnR) == 0)
6354 ptep = pmap_pte(pmap, far, &lvl);
6356 ((pte = pmap_load(ptep)) & ATTR_SW_DBM) != 0) {
6357 if ((pte & ATTR_S1_AP_RW_BIT) ==
6358 ATTR_S1_AP(ATTR_S1_AP_RO)) {
6359 pmap_clear_bits(ptep, ATTR_S1_AP_RW_BIT);
6360 pmap_invalidate_page(pmap, far);
6366 case ISS_DATA_DFSC_TF_L0:
6367 case ISS_DATA_DFSC_TF_L1:
6368 case ISS_DATA_DFSC_TF_L2:
6369 case ISS_DATA_DFSC_TF_L3:
6371 * Retry the translation. A break-before-make sequence can
6372 * produce a transient fault.
6374 if (pmap == kernel_pmap) {
6376 * The translation fault may have occurred within a
6377 * critical section. Therefore, we must check the
6378 * address without acquiring the kernel pmap's lock.
6380 if (pmap_kextract(far) != 0)
6384 /* Ask the MMU to check the address. */
6385 intr = intr_disable();
6386 par = arm64_address_translate_s1e0r(far);
6391 * If the translation was successful, then we can
6392 * return success to the trap handler.
6394 if (PAR_SUCCESS(par))
6404 * Increase the starting virtual address of the given mapping if a
6405 * different alignment might result in more superpage mappings.
6408 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
6409 vm_offset_t *addr, vm_size_t size)
6411 vm_offset_t superpage_offset;
6415 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
6416 offset += ptoa(object->pg_color);
6417 superpage_offset = offset & L2_OFFSET;
6418 if (size - ((L2_SIZE - superpage_offset) & L2_OFFSET) < L2_SIZE ||
6419 (*addr & L2_OFFSET) == superpage_offset)
6421 if ((*addr & L2_OFFSET) < superpage_offset)
6422 *addr = (*addr & ~L2_OFFSET) + superpage_offset;
6424 *addr = ((*addr + L2_OFFSET) & ~L2_OFFSET) + superpage_offset;
6428 * Get the kernel virtual address of a set of physical pages. If there are
6429 * physical addresses not covered by the DMAP perform a transient mapping
6430 * that will be removed when calling pmap_unmap_io_transient.
6432 * \param page The pages the caller wishes to obtain the virtual
6433 * address on the kernel memory map.
6434 * \param vaddr On return contains the kernel virtual memory address
6435 * of the pages passed in the page parameter.
6436 * \param count Number of pages passed in.
6437 * \param can_fault TRUE if the thread using the mapped pages can take
6438 * page faults, FALSE otherwise.
6440 * \returns TRUE if the caller must call pmap_unmap_io_transient when
6441 * finished or FALSE otherwise.
6445 pmap_map_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
6446 boolean_t can_fault)
6449 boolean_t needs_mapping;
6453 * Allocate any KVA space that we need, this is done in a separate
6454 * loop to prevent calling vmem_alloc while pinned.
6456 needs_mapping = FALSE;
6457 for (i = 0; i < count; i++) {
6458 paddr = VM_PAGE_TO_PHYS(page[i]);
6459 if (__predict_false(!PHYS_IN_DMAP(paddr))) {
6460 error = vmem_alloc(kernel_arena, PAGE_SIZE,
6461 M_BESTFIT | M_WAITOK, &vaddr[i]);
6462 KASSERT(error == 0, ("vmem_alloc failed: %d", error));
6463 needs_mapping = TRUE;
6465 vaddr[i] = PHYS_TO_DMAP(paddr);
6469 /* Exit early if everything is covered by the DMAP */
6475 for (i = 0; i < count; i++) {
6476 paddr = VM_PAGE_TO_PHYS(page[i]);
6477 if (!PHYS_IN_DMAP(paddr)) {
6479 "pmap_map_io_transient: TODO: Map out of DMAP data");
6483 return (needs_mapping);
6487 pmap_unmap_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
6488 boolean_t can_fault)
6495 for (i = 0; i < count; i++) {
6496 paddr = VM_PAGE_TO_PHYS(page[i]);
6497 if (!PHYS_IN_DMAP(paddr)) {
6498 panic("ARM64TODO: pmap_unmap_io_transient: Unmap data");
6504 pmap_is_valid_memattr(pmap_t pmap __unused, vm_memattr_t mode)
6507 return (mode >= VM_MEMATTR_DEVICE && mode <= VM_MEMATTR_WRITE_THROUGH);
6511 * Track a range of the kernel's virtual address space that is contiguous
6512 * in various mapping attributes.
6514 struct pmap_kernel_map_range {
6524 sysctl_kmaps_dump(struct sbuf *sb, struct pmap_kernel_map_range *range,
6530 if (eva <= range->sva)
6533 index = range->attrs & ATTR_S1_IDX_MASK;
6535 case ATTR_S1_IDX(VM_MEMATTR_DEVICE):
6538 case ATTR_S1_IDX(VM_MEMATTR_UNCACHEABLE):
6541 case ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK):
6544 case ATTR_S1_IDX(VM_MEMATTR_WRITE_THROUGH):
6549 "%s: unknown memory type %x for range 0x%016lx-0x%016lx\n",
6550 __func__, index, range->sva, eva);
6555 sbuf_printf(sb, "0x%016lx-0x%016lx r%c%c%c %3s %d %d %d %d\n",
6557 (range->attrs & ATTR_S1_AP_RW_BIT) == ATTR_S1_AP_RW ? 'w' : '-',
6558 (range->attrs & ATTR_S1_PXN) != 0 ? '-' : 'x',
6559 (range->attrs & ATTR_S1_AP_USER) != 0 ? 'u' : 's',
6560 mode, range->l1blocks, range->l2blocks, range->l3contig,
6563 /* Reset to sentinel value. */
6564 range->sva = 0xfffffffffffffffful;
6568 * Determine whether the attributes specified by a page table entry match those
6569 * being tracked by the current range.
6572 sysctl_kmaps_match(struct pmap_kernel_map_range *range, pt_entry_t attrs)
6575 return (range->attrs == attrs);
6579 sysctl_kmaps_reinit(struct pmap_kernel_map_range *range, vm_offset_t va,
6583 memset(range, 0, sizeof(*range));
6585 range->attrs = attrs;
6589 * Given a leaf PTE, derive the mapping's attributes. If they do not match
6590 * those of the current run, dump the address range and its attributes, and
6594 sysctl_kmaps_check(struct sbuf *sb, struct pmap_kernel_map_range *range,
6595 vm_offset_t va, pd_entry_t l0e, pd_entry_t l1e, pd_entry_t l2e,
6600 attrs = l0e & (ATTR_S1_AP_MASK | ATTR_S1_XN);
6601 attrs |= l1e & (ATTR_S1_AP_MASK | ATTR_S1_XN);
6602 if ((l1e & ATTR_DESCR_MASK) == L1_BLOCK)
6603 attrs |= l1e & ATTR_S1_IDX_MASK;
6604 attrs |= l2e & (ATTR_S1_AP_MASK | ATTR_S1_XN);
6605 if ((l2e & ATTR_DESCR_MASK) == L2_BLOCK)
6606 attrs |= l2e & ATTR_S1_IDX_MASK;
6607 attrs |= l3e & (ATTR_S1_AP_MASK | ATTR_S1_XN | ATTR_S1_IDX_MASK);
6609 if (range->sva > va || !sysctl_kmaps_match(range, attrs)) {
6610 sysctl_kmaps_dump(sb, range, va);
6611 sysctl_kmaps_reinit(range, va, attrs);
6616 sysctl_kmaps(SYSCTL_HANDLER_ARGS)
6618 struct pmap_kernel_map_range range;
6619 struct sbuf sbuf, *sb;
6620 pd_entry_t l0e, *l1, l1e, *l2, l2e;
6621 pt_entry_t *l3, l3e;
6624 int error, i, j, k, l;
6626 error = sysctl_wire_old_buffer(req, 0);
6630 sbuf_new_for_sysctl(sb, NULL, PAGE_SIZE, req);
6632 /* Sentinel value. */
6633 range.sva = 0xfffffffffffffffful;
6636 * Iterate over the kernel page tables without holding the kernel pmap
6637 * lock. Kernel page table pages are never freed, so at worst we will
6638 * observe inconsistencies in the output.
6640 for (sva = 0xffff000000000000ul, i = pmap_l0_index(sva); i < Ln_ENTRIES;
6642 if (i == pmap_l0_index(DMAP_MIN_ADDRESS))
6643 sbuf_printf(sb, "\nDirect map:\n");
6644 else if (i == pmap_l0_index(VM_MIN_KERNEL_ADDRESS))
6645 sbuf_printf(sb, "\nKernel map:\n");
6647 l0e = kernel_pmap->pm_l0[i];
6648 if ((l0e & ATTR_DESCR_VALID) == 0) {
6649 sysctl_kmaps_dump(sb, &range, sva);
6653 pa = l0e & ~ATTR_MASK;
6654 l1 = (pd_entry_t *)PHYS_TO_DMAP(pa);
6656 for (j = pmap_l1_index(sva); j < Ln_ENTRIES; j++) {
6658 if ((l1e & ATTR_DESCR_VALID) == 0) {
6659 sysctl_kmaps_dump(sb, &range, sva);
6663 if ((l1e & ATTR_DESCR_MASK) == L1_BLOCK) {
6664 sysctl_kmaps_check(sb, &range, sva, l0e, l1e,
6670 pa = l1e & ~ATTR_MASK;
6671 l2 = (pd_entry_t *)PHYS_TO_DMAP(pa);
6673 for (k = pmap_l2_index(sva); k < Ln_ENTRIES; k++) {
6675 if ((l2e & ATTR_DESCR_VALID) == 0) {
6676 sysctl_kmaps_dump(sb, &range, sva);
6680 if ((l2e & ATTR_DESCR_MASK) == L2_BLOCK) {
6681 sysctl_kmaps_check(sb, &range, sva,
6687 pa = l2e & ~ATTR_MASK;
6688 l3 = (pt_entry_t *)PHYS_TO_DMAP(pa);
6690 for (l = pmap_l3_index(sva); l < Ln_ENTRIES;
6691 l++, sva += L3_SIZE) {
6693 if ((l3e & ATTR_DESCR_VALID) == 0) {
6694 sysctl_kmaps_dump(sb, &range,
6698 sysctl_kmaps_check(sb, &range, sva,
6699 l0e, l1e, l2e, l3e);
6700 if ((l3e & ATTR_CONTIGUOUS) != 0)
6701 range.l3contig += l % 16 == 0 ?
6710 error = sbuf_finish(sb);
6714 SYSCTL_OID(_vm_pmap, OID_AUTO, kernel_maps,
6715 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE,
6716 NULL, 0, sysctl_kmaps, "A",
6717 "Dump kernel address layout");