2 * Copyright (c) 1991 Regents of the University of California.
4 * Copyright (c) 1994 John S. Dyson
6 * Copyright (c) 1994 David Greenman
8 * Copyright (c) 2003 Peter Wemm
10 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
11 * All rights reserved.
12 * Copyright (c) 2014 Andrew Turner
13 * All rights reserved.
14 * Copyright (c) 2014-2016 The FreeBSD Foundation
15 * All rights reserved.
17 * This code is derived from software contributed to Berkeley by
18 * the Systems Programming Group of the University of Utah Computer
19 * Science Department and William Jolitz of UUNET Technologies Inc.
21 * This software was developed by Andrew Turner under sponsorship from
22 * the FreeBSD Foundation.
24 * Redistribution and use in source and binary forms, with or without
25 * modification, are permitted provided that the following conditions
27 * 1. Redistributions of source code must retain the above copyright
28 * notice, this list of conditions and the following disclaimer.
29 * 2. Redistributions in binary form must reproduce the above copyright
30 * notice, this list of conditions and the following disclaimer in the
31 * documentation and/or other materials provided with the distribution.
32 * 3. All advertising materials mentioning features or use of this software
33 * must display the following acknowledgement:
34 * This product includes software developed by the University of
35 * California, Berkeley and its contributors.
36 * 4. Neither the name of the University nor the names of its contributors
37 * may be used to endorse or promote products derived from this software
38 * without specific prior written permission.
40 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
41 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
42 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
43 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
44 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
45 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
46 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
47 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
48 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
49 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
52 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
55 * Copyright (c) 2003 Networks Associates Technology, Inc.
56 * All rights reserved.
58 * This software was developed for the FreeBSD Project by Jake Burkholder,
59 * Safeport Network Services, and Network Associates Laboratories, the
60 * Security Research Division of Network Associates, Inc. under
61 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
62 * CHATS research program.
64 * Redistribution and use in source and binary forms, with or without
65 * modification, are permitted provided that the following conditions
67 * 1. Redistributions of source code must retain the above copyright
68 * notice, this list of conditions and the following disclaimer.
69 * 2. Redistributions in binary form must reproduce the above copyright
70 * notice, this list of conditions and the following disclaimer in the
71 * documentation and/or other materials provided with the distribution.
73 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
74 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
77 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
78 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
79 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
80 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
81 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
82 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
86 #include <sys/cdefs.h>
87 __FBSDID("$FreeBSD$");
90 * Manages physical address maps.
92 * Since the information managed by this module is
93 * also stored by the logical address mapping module,
94 * this module may throw away valid virtual-to-physical
95 * mappings at almost any time. However, invalidations
96 * of virtual-to-physical mappings must be done as
99 * In order to cope with hardware architectures which
100 * make virtual-to-physical map invalidates expensive,
101 * this module may delay invalidate or reduced protection
102 * operations until such time as they are actually
103 * necessary. This module is given full information as
104 * to which processors are currently using which maps,
105 * and to when physical maps must be made correct.
110 #include <sys/param.h>
111 #include <sys/bitstring.h>
113 #include <sys/systm.h>
114 #include <sys/kernel.h>
116 #include <sys/limits.h>
117 #include <sys/lock.h>
118 #include <sys/malloc.h>
119 #include <sys/mman.h>
120 #include <sys/msgbuf.h>
121 #include <sys/mutex.h>
122 #include <sys/proc.h>
123 #include <sys/rwlock.h>
124 #include <sys/sbuf.h>
126 #include <sys/vmem.h>
127 #include <sys/vmmeter.h>
128 #include <sys/sched.h>
129 #include <sys/sysctl.h>
130 #include <sys/_unrhdr.h>
134 #include <vm/vm_param.h>
135 #include <vm/vm_kern.h>
136 #include <vm/vm_page.h>
137 #include <vm/vm_map.h>
138 #include <vm/vm_object.h>
139 #include <vm/vm_extern.h>
140 #include <vm/vm_pageout.h>
141 #include <vm/vm_pager.h>
142 #include <vm/vm_phys.h>
143 #include <vm/vm_radix.h>
144 #include <vm/vm_reserv.h>
147 #include <machine/machdep.h>
148 #include <machine/md_var.h>
149 #include <machine/pcb.h>
151 #include <arm/include/physmem.h>
153 #define NL0PG (PAGE_SIZE/(sizeof (pd_entry_t)))
154 #define NL1PG (PAGE_SIZE/(sizeof (pd_entry_t)))
155 #define NL2PG (PAGE_SIZE/(sizeof (pd_entry_t)))
156 #define NL3PG (PAGE_SIZE/(sizeof (pt_entry_t)))
158 #define NUL0E L0_ENTRIES
159 #define NUL1E (NUL0E * NL1PG)
160 #define NUL2E (NUL1E * NL2PG)
162 #if !defined(DIAGNOSTIC)
163 #ifdef __GNUC_GNU_INLINE__
164 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
166 #define PMAP_INLINE extern inline
173 #define PV_STAT(x) do { x ; } while (0)
175 #define PV_STAT(x) do { } while (0)
178 #define pmap_l2_pindex(v) ((v) >> L2_SHIFT)
179 #define pa_to_pvh(pa) (&pv_table[pmap_l2_pindex(pa)])
181 #define NPV_LIST_LOCKS MAXCPU
183 #define PHYS_TO_PV_LIST_LOCK(pa) \
184 (&pv_list_locks[pa_index(pa) % NPV_LIST_LOCKS])
186 #define CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa) do { \
187 struct rwlock **_lockp = (lockp); \
188 struct rwlock *_new_lock; \
190 _new_lock = PHYS_TO_PV_LIST_LOCK(pa); \
191 if (_new_lock != *_lockp) { \
192 if (*_lockp != NULL) \
193 rw_wunlock(*_lockp); \
194 *_lockp = _new_lock; \
199 #define CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m) \
200 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, VM_PAGE_TO_PHYS(m))
202 #define RELEASE_PV_LIST_LOCK(lockp) do { \
203 struct rwlock **_lockp = (lockp); \
205 if (*_lockp != NULL) { \
206 rw_wunlock(*_lockp); \
211 #define VM_PAGE_TO_PV_LIST_LOCK(m) \
212 PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m))
215 * The presence of this flag indicates that the mapping is writeable.
216 * If the ATTR_AP_RO bit is also set, then the mapping is clean, otherwise it is
217 * dirty. This flag may only be set on managed mappings.
219 * The DBM bit is reserved on ARMv8.0 but it seems we can safely treat it
220 * as a software managed bit.
222 #define ATTR_SW_DBM ATTR_DBM
224 struct pmap kernel_pmap_store;
226 /* Used for mapping ACPI memory before VM is initialized */
227 #define PMAP_PREINIT_MAPPING_COUNT 32
228 #define PMAP_PREINIT_MAPPING_SIZE (PMAP_PREINIT_MAPPING_COUNT * L2_SIZE)
229 static vm_offset_t preinit_map_va; /* Start VA of pre-init mapping space */
230 static int vm_initialized = 0; /* No need to use pre-init maps when set */
233 * Reserve a few L2 blocks starting from 'preinit_map_va' pointer.
234 * Always map entire L2 block for simplicity.
235 * VA of L2 block = preinit_map_va + i * L2_SIZE
237 static struct pmap_preinit_mapping {
241 } pmap_preinit_mapping[PMAP_PREINIT_MAPPING_COUNT];
243 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
244 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
245 vm_offset_t kernel_vm_end = 0;
248 * Data for the pv entry allocation mechanism.
250 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
251 static struct mtx pv_chunks_mutex;
252 static struct rwlock pv_list_locks[NPV_LIST_LOCKS];
253 static struct md_page *pv_table;
254 static struct md_page pv_dummy;
256 vm_paddr_t dmap_phys_base; /* The start of the dmap region */
257 vm_paddr_t dmap_phys_max; /* The limit of the dmap region */
258 vm_offset_t dmap_max_addr; /* The virtual address limit of the dmap */
260 /* This code assumes all L1 DMAP entries will be used */
261 CTASSERT((DMAP_MIN_ADDRESS & ~L0_OFFSET) == DMAP_MIN_ADDRESS);
262 CTASSERT((DMAP_MAX_ADDRESS & ~L0_OFFSET) == DMAP_MAX_ADDRESS);
264 #define DMAP_TABLES ((DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS) >> L0_SHIFT)
265 extern pt_entry_t pagetable_dmap[];
267 #define PHYSMAP_SIZE (2 * (VM_PHYSSEG_MAX - 1))
268 static vm_paddr_t physmap[PHYSMAP_SIZE];
269 static u_int physmap_idx;
271 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters");
274 * This ASID allocator uses a bit vector ("asid_set") to remember which ASIDs
275 * that it has currently allocated to a pmap, a cursor ("asid_next") to
276 * optimize its search for a free ASID in the bit vector, and an epoch number
277 * ("asid_epoch") to indicate when it has reclaimed all previously allocated
278 * ASIDs that are not currently active on a processor.
280 * The current epoch number is always in the range [0, INT_MAX). Negative
281 * numbers and INT_MAX are reserved for special cases that are described
284 static SYSCTL_NODE(_vm_pmap, OID_AUTO, asid, CTLFLAG_RD, 0, "ASID allocator");
285 static int asid_bits;
286 SYSCTL_INT(_vm_pmap_asid, OID_AUTO, bits, CTLFLAG_RD, &asid_bits, 0,
287 "The number of bits in an ASID");
288 static bitstr_t *asid_set;
289 static int asid_set_size;
290 static int asid_next;
291 SYSCTL_INT(_vm_pmap_asid, OID_AUTO, next, CTLFLAG_RD, &asid_next, 0,
292 "The last allocated ASID plus one");
293 static int asid_epoch;
294 SYSCTL_INT(_vm_pmap_asid, OID_AUTO, epoch, CTLFLAG_RD, &asid_epoch, 0,
295 "The current epoch number");
296 static struct mtx asid_set_mutex;
299 * A pmap's cookie encodes an ASID and epoch number. Cookies for reserved
300 * ASIDs have a negative epoch number, specifically, INT_MIN. Cookies for
301 * dynamically allocated ASIDs have a non-negative epoch number.
303 * An invalid ASID is represented by -1.
305 * There are two special-case cookie values: (1) COOKIE_FROM(-1, INT_MIN),
306 * which indicates that an ASID should never be allocated to the pmap, and
307 * (2) COOKIE_FROM(-1, INT_MAX), which indicates that an ASID should be
308 * allocated when the pmap is next activated.
310 #define COOKIE_FROM(asid, epoch) ((long)((u_int)(asid) | \
311 ((u_long)(epoch) << 32)))
312 #define COOKIE_TO_ASID(cookie) ((int)(cookie))
313 #define COOKIE_TO_EPOCH(cookie) ((int)((u_long)(cookie) >> 32))
315 static int superpages_enabled = 1;
316 SYSCTL_INT(_vm_pmap, OID_AUTO, superpages_enabled,
317 CTLFLAG_RDTUN | CTLFLAG_NOFETCH, &superpages_enabled, 0,
318 "Are large page mappings enabled?");
321 * Internal flags for pmap_enter()'s helper functions.
323 #define PMAP_ENTER_NORECLAIM 0x1000000 /* Don't reclaim PV entries. */
324 #define PMAP_ENTER_NOREPLACE 0x2000000 /* Don't replace mappings. */
326 static void free_pv_chunk(struct pv_chunk *pc);
327 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
328 static pv_entry_t get_pv_entry(pmap_t pmap, struct rwlock **lockp);
329 static vm_page_t reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp);
330 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
331 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
334 static void pmap_abort_ptp(pmap_t pmap, vm_offset_t va, vm_page_t mpte);
335 static bool pmap_activate_int(pmap_t pmap);
336 static void pmap_alloc_asid(pmap_t pmap);
337 static int pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode);
338 static pt_entry_t *pmap_demote_l1(pmap_t pmap, pt_entry_t *l1, vm_offset_t va);
339 static pt_entry_t *pmap_demote_l2_locked(pmap_t pmap, pt_entry_t *l2,
340 vm_offset_t va, struct rwlock **lockp);
341 static pt_entry_t *pmap_demote_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t va);
342 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
343 vm_page_t m, vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp);
344 static int pmap_enter_l2(pmap_t pmap, vm_offset_t va, pd_entry_t new_l2,
345 u_int flags, vm_page_t m, struct rwlock **lockp);
346 static int pmap_remove_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t sva,
347 pd_entry_t l1e, struct spglist *free, struct rwlock **lockp);
348 static int pmap_remove_l3(pmap_t pmap, pt_entry_t *l3, vm_offset_t sva,
349 pd_entry_t l2e, struct spglist *free, struct rwlock **lockp);
350 static void pmap_reset_asid_set(void);
351 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
352 vm_page_t m, struct rwlock **lockp);
354 static vm_page_t _pmap_alloc_l3(pmap_t pmap, vm_pindex_t ptepindex,
355 struct rwlock **lockp);
357 static void _pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m,
358 struct spglist *free);
359 static int pmap_unuse_pt(pmap_t, vm_offset_t, pd_entry_t, struct spglist *);
360 static __inline vm_page_t pmap_remove_pt_page(pmap_t pmap, vm_offset_t va);
363 * These load the old table data and store the new value.
364 * They need to be atomic as the System MMU may write to the table at
365 * the same time as the CPU.
367 #define pmap_clear(table) atomic_store_64(table, 0)
368 #define pmap_clear_bits(table, bits) atomic_clear_64(table, bits)
369 #define pmap_load(table) (*table)
370 #define pmap_load_clear(table) atomic_swap_64(table, 0)
371 #define pmap_load_store(table, entry) atomic_swap_64(table, entry)
372 #define pmap_set_bits(table, bits) atomic_set_64(table, bits)
373 #define pmap_store(table, entry) atomic_store_64(table, entry)
375 /********************/
376 /* Inline functions */
377 /********************/
380 pagecopy(void *s, void *d)
383 memcpy(d, s, PAGE_SIZE);
386 static __inline pd_entry_t *
387 pmap_l0(pmap_t pmap, vm_offset_t va)
390 return (&pmap->pm_l0[pmap_l0_index(va)]);
393 static __inline pd_entry_t *
394 pmap_l0_to_l1(pd_entry_t *l0, vm_offset_t va)
398 l1 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l0) & ~ATTR_MASK);
399 return (&l1[pmap_l1_index(va)]);
402 static __inline pd_entry_t *
403 pmap_l1(pmap_t pmap, vm_offset_t va)
407 l0 = pmap_l0(pmap, va);
408 if ((pmap_load(l0) & ATTR_DESCR_MASK) != L0_TABLE)
411 return (pmap_l0_to_l1(l0, va));
414 static __inline pd_entry_t *
415 pmap_l1_to_l2(pd_entry_t *l1, vm_offset_t va)
419 l2 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l1) & ~ATTR_MASK);
420 return (&l2[pmap_l2_index(va)]);
423 static __inline pd_entry_t *
424 pmap_l2(pmap_t pmap, vm_offset_t va)
428 l1 = pmap_l1(pmap, va);
429 if ((pmap_load(l1) & ATTR_DESCR_MASK) != L1_TABLE)
432 return (pmap_l1_to_l2(l1, va));
435 static __inline pt_entry_t *
436 pmap_l2_to_l3(pd_entry_t *l2, vm_offset_t va)
440 l3 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l2) & ~ATTR_MASK);
441 return (&l3[pmap_l3_index(va)]);
445 * Returns the lowest valid pde for a given virtual address.
446 * The next level may or may not point to a valid page or block.
448 static __inline pd_entry_t *
449 pmap_pde(pmap_t pmap, vm_offset_t va, int *level)
451 pd_entry_t *l0, *l1, *l2, desc;
453 l0 = pmap_l0(pmap, va);
454 desc = pmap_load(l0) & ATTR_DESCR_MASK;
455 if (desc != L0_TABLE) {
460 l1 = pmap_l0_to_l1(l0, va);
461 desc = pmap_load(l1) & ATTR_DESCR_MASK;
462 if (desc != L1_TABLE) {
467 l2 = pmap_l1_to_l2(l1, va);
468 desc = pmap_load(l2) & ATTR_DESCR_MASK;
469 if (desc != L2_TABLE) {
479 * Returns the lowest valid pte block or table entry for a given virtual
480 * address. If there are no valid entries return NULL and set the level to
481 * the first invalid level.
483 static __inline pt_entry_t *
484 pmap_pte(pmap_t pmap, vm_offset_t va, int *level)
486 pd_entry_t *l1, *l2, desc;
489 l1 = pmap_l1(pmap, va);
494 desc = pmap_load(l1) & ATTR_DESCR_MASK;
495 if (desc == L1_BLOCK) {
500 if (desc != L1_TABLE) {
505 l2 = pmap_l1_to_l2(l1, va);
506 desc = pmap_load(l2) & ATTR_DESCR_MASK;
507 if (desc == L2_BLOCK) {
512 if (desc != L2_TABLE) {
518 l3 = pmap_l2_to_l3(l2, va);
519 if ((pmap_load(l3) & ATTR_DESCR_MASK) != L3_PAGE)
526 pmap_ps_enabled(pmap_t pmap __unused)
529 return (superpages_enabled != 0);
533 pmap_get_tables(pmap_t pmap, vm_offset_t va, pd_entry_t **l0, pd_entry_t **l1,
534 pd_entry_t **l2, pt_entry_t **l3)
536 pd_entry_t *l0p, *l1p, *l2p;
538 if (pmap->pm_l0 == NULL)
541 l0p = pmap_l0(pmap, va);
544 if ((pmap_load(l0p) & ATTR_DESCR_MASK) != L0_TABLE)
547 l1p = pmap_l0_to_l1(l0p, va);
550 if ((pmap_load(l1p) & ATTR_DESCR_MASK) == L1_BLOCK) {
556 if ((pmap_load(l1p) & ATTR_DESCR_MASK) != L1_TABLE)
559 l2p = pmap_l1_to_l2(l1p, va);
562 if ((pmap_load(l2p) & ATTR_DESCR_MASK) == L2_BLOCK) {
567 if ((pmap_load(l2p) & ATTR_DESCR_MASK) != L2_TABLE)
570 *l3 = pmap_l2_to_l3(l2p, va);
576 pmap_l3_valid(pt_entry_t l3)
579 return ((l3 & ATTR_DESCR_MASK) == L3_PAGE);
583 CTASSERT(L1_BLOCK == L2_BLOCK);
586 * Checks if the PTE is dirty.
589 pmap_pte_dirty(pt_entry_t pte)
592 KASSERT((pte & ATTR_SW_MANAGED) != 0, ("pte %#lx is unmanaged", pte));
593 KASSERT((pte & (ATTR_AP_RW_BIT | ATTR_SW_DBM)) != 0,
594 ("pte %#lx is writeable and missing ATTR_SW_DBM", pte));
596 return ((pte & (ATTR_AP_RW_BIT | ATTR_SW_DBM)) ==
597 (ATTR_AP(ATTR_AP_RW) | ATTR_SW_DBM));
601 pmap_resident_count_inc(pmap_t pmap, int count)
604 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
605 pmap->pm_stats.resident_count += count;
609 pmap_resident_count_dec(pmap_t pmap, int count)
612 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
613 KASSERT(pmap->pm_stats.resident_count >= count,
614 ("pmap %p resident count underflow %ld %d", pmap,
615 pmap->pm_stats.resident_count, count));
616 pmap->pm_stats.resident_count -= count;
620 pmap_early_page_idx(vm_offset_t l1pt, vm_offset_t va, u_int *l1_slot,
626 l1 = (pd_entry_t *)l1pt;
627 *l1_slot = (va >> L1_SHIFT) & Ln_ADDR_MASK;
629 /* Check locore has used a table L1 map */
630 KASSERT((l1[*l1_slot] & ATTR_DESCR_MASK) == L1_TABLE,
631 ("Invalid bootstrap L1 table"));
632 /* Find the address of the L2 table */
633 l2 = (pt_entry_t *)init_pt_va;
634 *l2_slot = pmap_l2_index(va);
640 pmap_early_vtophys(vm_offset_t l1pt, vm_offset_t va)
642 u_int l1_slot, l2_slot;
645 l2 = pmap_early_page_idx(l1pt, va, &l1_slot, &l2_slot);
647 return ((l2[l2_slot] & ~ATTR_MASK) + (va & L2_OFFSET));
651 pmap_bootstrap_dmap(vm_offset_t kern_l1, vm_paddr_t min_pa,
652 vm_offset_t freemempos)
656 vm_paddr_t l2_pa, pa;
657 u_int l1_slot, l2_slot, prev_l1_slot;
660 dmap_phys_base = min_pa & ~L1_OFFSET;
666 #define DMAP_TABLES ((DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS) >> L0_SHIFT)
667 memset(pagetable_dmap, 0, PAGE_SIZE * DMAP_TABLES);
669 for (i = 0; i < (physmap_idx * 2); i += 2) {
670 pa = physmap[i] & ~L2_OFFSET;
671 va = pa - dmap_phys_base + DMAP_MIN_ADDRESS;
673 /* Create L2 mappings at the start of the region */
674 if ((pa & L1_OFFSET) != 0) {
675 l1_slot = ((va - DMAP_MIN_ADDRESS) >> L1_SHIFT);
676 if (l1_slot != prev_l1_slot) {
677 prev_l1_slot = l1_slot;
678 l2 = (pt_entry_t *)freemempos;
679 l2_pa = pmap_early_vtophys(kern_l1,
681 freemempos += PAGE_SIZE;
683 pmap_store(&pagetable_dmap[l1_slot],
684 (l2_pa & ~Ln_TABLE_MASK) | L1_TABLE);
686 memset(l2, 0, PAGE_SIZE);
689 ("pmap_bootstrap_dmap: NULL l2 map"));
690 for (; va < DMAP_MAX_ADDRESS && pa < physmap[i + 1];
691 pa += L2_SIZE, va += L2_SIZE) {
693 * We are on a boundary, stop to
694 * create a level 1 block
696 if ((pa & L1_OFFSET) == 0)
699 l2_slot = pmap_l2_index(va);
700 KASSERT(l2_slot != 0, ("..."));
701 pmap_store(&l2[l2_slot],
702 (pa & ~L2_OFFSET) | ATTR_DEFAULT | ATTR_XN |
703 ATTR_IDX(VM_MEMATTR_WRITE_BACK) | L2_BLOCK);
705 KASSERT(va == (pa - dmap_phys_base + DMAP_MIN_ADDRESS),
709 for (; va < DMAP_MAX_ADDRESS && pa < physmap[i + 1] &&
710 (physmap[i + 1] - pa) >= L1_SIZE;
711 pa += L1_SIZE, va += L1_SIZE) {
712 l1_slot = ((va - DMAP_MIN_ADDRESS) >> L1_SHIFT);
713 pmap_store(&pagetable_dmap[l1_slot],
714 (pa & ~L1_OFFSET) | ATTR_DEFAULT | ATTR_XN |
715 ATTR_IDX(VM_MEMATTR_WRITE_BACK) | L1_BLOCK);
718 /* Create L2 mappings at the end of the region */
719 if (pa < physmap[i + 1]) {
720 l1_slot = ((va - DMAP_MIN_ADDRESS) >> L1_SHIFT);
721 if (l1_slot != prev_l1_slot) {
722 prev_l1_slot = l1_slot;
723 l2 = (pt_entry_t *)freemempos;
724 l2_pa = pmap_early_vtophys(kern_l1,
726 freemempos += PAGE_SIZE;
728 pmap_store(&pagetable_dmap[l1_slot],
729 (l2_pa & ~Ln_TABLE_MASK) | L1_TABLE);
731 memset(l2, 0, PAGE_SIZE);
734 ("pmap_bootstrap_dmap: NULL l2 map"));
735 for (; va < DMAP_MAX_ADDRESS && pa < physmap[i + 1];
736 pa += L2_SIZE, va += L2_SIZE) {
737 l2_slot = pmap_l2_index(va);
738 pmap_store(&l2[l2_slot],
739 (pa & ~L2_OFFSET) | ATTR_DEFAULT | ATTR_XN |
740 ATTR_IDX(VM_MEMATTR_WRITE_BACK) | L2_BLOCK);
744 if (pa > dmap_phys_max) {
756 pmap_bootstrap_l2(vm_offset_t l1pt, vm_offset_t va, vm_offset_t l2_start)
763 KASSERT((va & L1_OFFSET) == 0, ("Invalid virtual address"));
765 l1 = (pd_entry_t *)l1pt;
766 l1_slot = pmap_l1_index(va);
769 for (; va < VM_MAX_KERNEL_ADDRESS; l1_slot++, va += L1_SIZE) {
770 KASSERT(l1_slot < Ln_ENTRIES, ("Invalid L1 index"));
772 pa = pmap_early_vtophys(l1pt, l2pt);
773 pmap_store(&l1[l1_slot],
774 (pa & ~Ln_TABLE_MASK) | L1_TABLE);
778 /* Clean the L2 page table */
779 memset((void *)l2_start, 0, l2pt - l2_start);
785 pmap_bootstrap_l3(vm_offset_t l1pt, vm_offset_t va, vm_offset_t l3_start)
792 KASSERT((va & L2_OFFSET) == 0, ("Invalid virtual address"));
794 l2 = pmap_l2(kernel_pmap, va);
795 l2 = (pd_entry_t *)rounddown2((uintptr_t)l2, PAGE_SIZE);
796 l2_slot = pmap_l2_index(va);
799 for (; va < VM_MAX_KERNEL_ADDRESS; l2_slot++, va += L2_SIZE) {
800 KASSERT(l2_slot < Ln_ENTRIES, ("Invalid L2 index"));
802 pa = pmap_early_vtophys(l1pt, l3pt);
803 pmap_store(&l2[l2_slot],
804 (pa & ~Ln_TABLE_MASK) | ATTR_UXN | L2_TABLE);
808 /* Clean the L2 page table */
809 memset((void *)l3_start, 0, l3pt - l3_start);
815 * Bootstrap the system enough to run with virtual memory.
818 pmap_bootstrap(vm_offset_t l0pt, vm_offset_t l1pt, vm_paddr_t kernstart,
821 u_int l1_slot, l2_slot;
823 vm_offset_t va, freemempos;
824 vm_offset_t dpcpu, msgbufpv;
825 vm_paddr_t start_pa, pa, min_pa;
829 /* Verify that the ASID is set through TTBR0. */
830 KASSERT((READ_SPECIALREG(tcr_el1) & TCR_A1) == 0,
831 ("pmap_bootstrap: TCR_EL1.A1 != 0"));
833 kern_delta = KERNBASE - kernstart;
835 printf("pmap_bootstrap %lx %lx %lx\n", l1pt, kernstart, kernlen);
836 printf("%lx\n", l1pt);
837 printf("%lx\n", (KERNBASE >> L1_SHIFT) & Ln_ADDR_MASK);
839 /* Set this early so we can use the pagetable walking functions */
840 kernel_pmap_store.pm_l0 = (pd_entry_t *)l0pt;
841 PMAP_LOCK_INIT(kernel_pmap);
842 kernel_pmap->pm_l0_paddr = l0pt - kern_delta;
843 kernel_pmap->pm_cookie = COOKIE_FROM(-1, INT_MIN);
845 /* Assume the address we were loaded to is a valid physical address */
846 min_pa = KERNBASE - kern_delta;
848 physmap_idx = arm_physmem_avail(physmap, nitems(physmap));
852 * Find the minimum physical address. physmap is sorted,
853 * but may contain empty ranges.
855 for (i = 0; i < (physmap_idx * 2); i += 2) {
856 if (physmap[i] == physmap[i + 1])
858 if (physmap[i] <= min_pa)
862 freemempos = KERNBASE + kernlen;
863 freemempos = roundup2(freemempos, PAGE_SIZE);
865 /* Create a direct map region early so we can use it for pa -> va */
866 freemempos = pmap_bootstrap_dmap(l1pt, min_pa, freemempos);
869 start_pa = pa = KERNBASE - kern_delta;
872 * Read the page table to find out what is already mapped.
873 * This assumes we have mapped a block of memory from KERNBASE
874 * using a single L1 entry.
876 l2 = pmap_early_page_idx(l1pt, KERNBASE, &l1_slot, &l2_slot);
878 /* Sanity check the index, KERNBASE should be the first VA */
879 KASSERT(l2_slot == 0, ("The L2 index is non-zero"));
881 /* Find how many pages we have mapped */
882 for (; l2_slot < Ln_ENTRIES; l2_slot++) {
883 if ((l2[l2_slot] & ATTR_DESCR_MASK) == 0)
886 /* Check locore used L2 blocks */
887 KASSERT((l2[l2_slot] & ATTR_DESCR_MASK) == L2_BLOCK,
888 ("Invalid bootstrap L2 table"));
889 KASSERT((l2[l2_slot] & ~ATTR_MASK) == pa,
890 ("Incorrect PA in L2 table"));
896 va = roundup2(va, L1_SIZE);
898 /* Create the l2 tables up to VM_MAX_KERNEL_ADDRESS */
899 freemempos = pmap_bootstrap_l2(l1pt, va, freemempos);
900 /* And the l3 tables for the early devmap */
901 freemempos = pmap_bootstrap_l3(l1pt,
902 VM_MAX_KERNEL_ADDRESS - (PMAP_MAPDEV_EARLY_SIZE), freemempos);
906 #define alloc_pages(var, np) \
907 (var) = freemempos; \
908 freemempos += (np * PAGE_SIZE); \
909 memset((char *)(var), 0, ((np) * PAGE_SIZE));
911 /* Allocate dynamic per-cpu area. */
912 alloc_pages(dpcpu, DPCPU_SIZE / PAGE_SIZE);
913 dpcpu_init((void *)dpcpu, 0);
915 /* Allocate memory for the msgbuf, e.g. for /sbin/dmesg */
916 alloc_pages(msgbufpv, round_page(msgbufsize) / PAGE_SIZE);
917 msgbufp = (void *)msgbufpv;
919 /* Reserve some VA space for early BIOS/ACPI mapping */
920 preinit_map_va = roundup2(freemempos, L2_SIZE);
922 virtual_avail = preinit_map_va + PMAP_PREINIT_MAPPING_SIZE;
923 virtual_avail = roundup2(virtual_avail, L1_SIZE);
924 virtual_end = VM_MAX_KERNEL_ADDRESS - (PMAP_MAPDEV_EARLY_SIZE);
925 kernel_vm_end = virtual_avail;
927 pa = pmap_early_vtophys(l1pt, freemempos);
929 arm_physmem_exclude_region(start_pa, pa - start_pa, EXFLAG_NOALLOC);
935 * Initialize a vm_page's machine-dependent fields.
938 pmap_page_init(vm_page_t m)
941 TAILQ_INIT(&m->md.pv_list);
942 m->md.pv_memattr = VM_MEMATTR_WRITE_BACK;
946 * Initialize the pmap module.
947 * Called by vm_init, to initialize any structures that the pmap
948 * system needs to map virtual memory.
957 * Determine whether an ASID is 8 or 16 bits in size.
959 asid_bits = (READ_SPECIALREG(tcr_el1) & TCR_ASID_16) != 0 ? 16 : 8;
962 * Are large page mappings enabled?
964 TUNABLE_INT_FETCH("vm.pmap.superpages_enabled", &superpages_enabled);
965 if (superpages_enabled) {
966 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
967 ("pmap_init: can't assign to pagesizes[1]"));
968 pagesizes[1] = L2_SIZE;
972 * Initialize the ASID allocator. At this point, we are still too
973 * early in the overall initialization process to use bit_alloc().
975 asid_set_size = 1 << asid_bits;
976 asid_set = (bitstr_t *)kmem_malloc(bitstr_size(asid_set_size),
978 for (i = 0; i < ASID_FIRST_AVAILABLE; i++)
979 bit_set(asid_set, i);
980 asid_next = ASID_FIRST_AVAILABLE;
981 mtx_init(&asid_set_mutex, "asid set", NULL, MTX_SPIN);
984 * Initialize the pv chunk list mutex.
986 mtx_init(&pv_chunks_mutex, "pmap pv chunk list", NULL, MTX_DEF);
989 * Initialize the pool of pv list locks.
991 for (i = 0; i < NPV_LIST_LOCKS; i++)
992 rw_init(&pv_list_locks[i], "pmap pv list");
995 * Calculate the size of the pv head table for superpages.
997 pv_npg = howmany(vm_phys_segs[vm_phys_nsegs - 1].end, L2_SIZE);
1000 * Allocate memory for the pv head table for superpages.
1002 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
1004 pv_table = (struct md_page *)kmem_malloc(s, M_WAITOK | M_ZERO);
1005 for (i = 0; i < pv_npg; i++)
1006 TAILQ_INIT(&pv_table[i].pv_list);
1007 TAILQ_INIT(&pv_dummy.pv_list);
1012 static SYSCTL_NODE(_vm_pmap, OID_AUTO, l2, CTLFLAG_RD, 0,
1013 "2MB page mapping counters");
1015 static u_long pmap_l2_demotions;
1016 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, demotions, CTLFLAG_RD,
1017 &pmap_l2_demotions, 0, "2MB page demotions");
1019 static u_long pmap_l2_mappings;
1020 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, mappings, CTLFLAG_RD,
1021 &pmap_l2_mappings, 0, "2MB page mappings");
1023 static u_long pmap_l2_p_failures;
1024 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, p_failures, CTLFLAG_RD,
1025 &pmap_l2_p_failures, 0, "2MB page promotion failures");
1027 static u_long pmap_l2_promotions;
1028 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, promotions, CTLFLAG_RD,
1029 &pmap_l2_promotions, 0, "2MB page promotions");
1032 * Invalidate a single TLB entry.
1034 static __inline void
1035 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
1040 if (pmap == kernel_pmap) {
1042 __asm __volatile("tlbi vaae1is, %0" : : "r" (r));
1044 r = ASID_TO_OPERAND(COOKIE_TO_ASID(pmap->pm_cookie)) | atop(va);
1045 __asm __volatile("tlbi vae1is, %0" : : "r" (r));
1051 static __inline void
1052 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1054 uint64_t end, r, start;
1057 if (pmap == kernel_pmap) {
1060 for (r = start; r < end; r++)
1061 __asm __volatile("tlbi vaae1is, %0" : : "r" (r));
1063 start = end = ASID_TO_OPERAND(COOKIE_TO_ASID(pmap->pm_cookie));
1066 for (r = start; r < end; r++)
1067 __asm __volatile("tlbi vae1is, %0" : : "r" (r));
1073 static __inline void
1074 pmap_invalidate_all(pmap_t pmap)
1079 if (pmap == kernel_pmap) {
1080 __asm __volatile("tlbi vmalle1is");
1082 r = ASID_TO_OPERAND(COOKIE_TO_ASID(pmap->pm_cookie));
1083 __asm __volatile("tlbi aside1is, %0" : : "r" (r));
1090 * Routine: pmap_extract
1092 * Extract the physical page address associated
1093 * with the given map/virtual_address pair.
1096 pmap_extract(pmap_t pmap, vm_offset_t va)
1098 pt_entry_t *pte, tpte;
1105 * Find the block or page map for this virtual address. pmap_pte
1106 * will return either a valid block/page entry, or NULL.
1108 pte = pmap_pte(pmap, va, &lvl);
1110 tpte = pmap_load(pte);
1111 pa = tpte & ~ATTR_MASK;
1114 KASSERT((tpte & ATTR_DESCR_MASK) == L1_BLOCK,
1115 ("pmap_extract: Invalid L1 pte found: %lx",
1116 tpte & ATTR_DESCR_MASK));
1117 pa |= (va & L1_OFFSET);
1120 KASSERT((tpte & ATTR_DESCR_MASK) == L2_BLOCK,
1121 ("pmap_extract: Invalid L2 pte found: %lx",
1122 tpte & ATTR_DESCR_MASK));
1123 pa |= (va & L2_OFFSET);
1126 KASSERT((tpte & ATTR_DESCR_MASK) == L3_PAGE,
1127 ("pmap_extract: Invalid L3 pte found: %lx",
1128 tpte & ATTR_DESCR_MASK));
1129 pa |= (va & L3_OFFSET);
1138 * Routine: pmap_extract_and_hold
1140 * Atomically extract and hold the physical page
1141 * with the given pmap and virtual address pair
1142 * if that mapping permits the given protection.
1145 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1147 pt_entry_t *pte, tpte;
1154 pte = pmap_pte(pmap, va, &lvl);
1156 tpte = pmap_load(pte);
1158 KASSERT(lvl > 0 && lvl <= 3,
1159 ("pmap_extract_and_hold: Invalid level %d", lvl));
1160 CTASSERT(L1_BLOCK == L2_BLOCK);
1161 KASSERT((lvl == 3 && (tpte & ATTR_DESCR_MASK) == L3_PAGE) ||
1162 (lvl < 3 && (tpte & ATTR_DESCR_MASK) == L1_BLOCK),
1163 ("pmap_extract_and_hold: Invalid pte at L%d: %lx", lvl,
1164 tpte & ATTR_DESCR_MASK));
1165 if (((tpte & ATTR_AP_RW_BIT) == ATTR_AP(ATTR_AP_RW)) ||
1166 ((prot & VM_PROT_WRITE) == 0)) {
1169 off = va & L1_OFFSET;
1172 off = va & L2_OFFSET;
1178 m = PHYS_TO_VM_PAGE((tpte & ~ATTR_MASK) | off);
1179 if (!vm_page_wire_mapped(m))
1188 pmap_kextract(vm_offset_t va)
1190 pt_entry_t *pte, tpte;
1192 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS)
1193 return (DMAP_TO_PHYS(va));
1194 pte = pmap_l1(kernel_pmap, va);
1199 * A concurrent pmap_update_entry() will clear the entry's valid bit
1200 * but leave the rest of the entry unchanged. Therefore, we treat a
1201 * non-zero entry as being valid, and we ignore the valid bit when
1202 * determining whether the entry maps a block, page, or table.
1204 tpte = pmap_load(pte);
1207 if ((tpte & ATTR_DESCR_TYPE_MASK) == ATTR_DESCR_TYPE_BLOCK)
1208 return ((tpte & ~ATTR_MASK) | (va & L1_OFFSET));
1209 pte = pmap_l1_to_l2(&tpte, va);
1210 tpte = pmap_load(pte);
1213 if ((tpte & ATTR_DESCR_TYPE_MASK) == ATTR_DESCR_TYPE_BLOCK)
1214 return ((tpte & ~ATTR_MASK) | (va & L2_OFFSET));
1215 pte = pmap_l2_to_l3(&tpte, va);
1216 tpte = pmap_load(pte);
1219 return ((tpte & ~ATTR_MASK) | (va & L3_OFFSET));
1222 /***************************************************
1223 * Low level mapping routines.....
1224 ***************************************************/
1227 pmap_kenter(vm_offset_t sva, vm_size_t size, vm_paddr_t pa, int mode)
1230 pt_entry_t *pte, attr;
1234 KASSERT((pa & L3_OFFSET) == 0,
1235 ("pmap_kenter: Invalid physical address"));
1236 KASSERT((sva & L3_OFFSET) == 0,
1237 ("pmap_kenter: Invalid virtual address"));
1238 KASSERT((size & PAGE_MASK) == 0,
1239 ("pmap_kenter: Mapping is not page-sized"));
1241 attr = ATTR_DEFAULT | ATTR_AP(ATTR_AP_RW) | ATTR_XN | ATTR_IDX(mode) |
1245 pde = pmap_pde(kernel_pmap, va, &lvl);
1246 KASSERT(pde != NULL,
1247 ("pmap_kenter: Invalid page entry, va: 0x%lx", va));
1248 KASSERT(lvl == 2, ("pmap_kenter: Invalid level %d", lvl));
1250 pte = pmap_l2_to_l3(pde, va);
1251 pmap_load_store(pte, (pa & ~L3_OFFSET) | attr);
1257 pmap_invalidate_range(kernel_pmap, sva, va);
1261 pmap_kenter_device(vm_offset_t sva, vm_size_t size, vm_paddr_t pa)
1264 pmap_kenter(sva, size, pa, VM_MEMATTR_DEVICE);
1268 * Remove a page from the kernel pagetables.
1271 pmap_kremove(vm_offset_t va)
1276 pte = pmap_pte(kernel_pmap, va, &lvl);
1277 KASSERT(pte != NULL, ("pmap_kremove: Invalid address"));
1278 KASSERT(lvl == 3, ("pmap_kremove: Invalid pte level %d", lvl));
1281 pmap_invalidate_page(kernel_pmap, va);
1285 pmap_kremove_device(vm_offset_t sva, vm_size_t size)
1291 KASSERT((sva & L3_OFFSET) == 0,
1292 ("pmap_kremove_device: Invalid virtual address"));
1293 KASSERT((size & PAGE_MASK) == 0,
1294 ("pmap_kremove_device: Mapping is not page-sized"));
1298 pte = pmap_pte(kernel_pmap, va, &lvl);
1299 KASSERT(pte != NULL, ("Invalid page table, va: 0x%lx", va));
1301 ("Invalid device pagetable level: %d != 3", lvl));
1307 pmap_invalidate_range(kernel_pmap, sva, va);
1311 * Used to map a range of physical addresses into kernel
1312 * virtual address space.
1314 * The value passed in '*virt' is a suggested virtual address for
1315 * the mapping. Architectures which can support a direct-mapped
1316 * physical to virtual region can return the appropriate address
1317 * within that region, leaving '*virt' unchanged. Other
1318 * architectures should map the pages starting at '*virt' and
1319 * update '*virt' with the first usable address after the mapped
1323 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
1325 return PHYS_TO_DMAP(start);
1330 * Add a list of wired pages to the kva
1331 * this routine is only used for temporary
1332 * kernel mappings that do not need to have
1333 * page modification or references recorded.
1334 * Note that old mappings are simply written
1335 * over. The page *must* be wired.
1336 * Note: SMP coherent. Uses a ranged shootdown IPI.
1339 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
1342 pt_entry_t *pte, pa;
1348 for (i = 0; i < count; i++) {
1349 pde = pmap_pde(kernel_pmap, va, &lvl);
1350 KASSERT(pde != NULL,
1351 ("pmap_qenter: Invalid page entry, va: 0x%lx", va));
1353 ("pmap_qenter: Invalid level %d", lvl));
1356 pa = VM_PAGE_TO_PHYS(m) | ATTR_DEFAULT | ATTR_AP(ATTR_AP_RW) |
1357 ATTR_XN | ATTR_IDX(m->md.pv_memattr) | L3_PAGE;
1358 pte = pmap_l2_to_l3(pde, va);
1359 pmap_load_store(pte, pa);
1363 pmap_invalidate_range(kernel_pmap, sva, va);
1367 * This routine tears out page mappings from the
1368 * kernel -- it is meant only for temporary mappings.
1371 pmap_qremove(vm_offset_t sva, int count)
1377 KASSERT(sva >= VM_MIN_KERNEL_ADDRESS, ("usermode va %lx", sva));
1380 while (count-- > 0) {
1381 pte = pmap_pte(kernel_pmap, va, &lvl);
1383 ("Invalid device pagetable level: %d != 3", lvl));
1390 pmap_invalidate_range(kernel_pmap, sva, va);
1393 /***************************************************
1394 * Page table page management routines.....
1395 ***************************************************/
1397 * Schedule the specified unused page table page to be freed. Specifically,
1398 * add the page to the specified list of pages that will be released to the
1399 * physical memory manager after the TLB has been updated.
1401 static __inline void
1402 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
1403 boolean_t set_PG_ZERO)
1407 m->flags |= PG_ZERO;
1409 m->flags &= ~PG_ZERO;
1410 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
1414 * Decrements a page table page's reference count, which is used to record the
1415 * number of valid page table entries within the page. If the reference count
1416 * drops to zero, then the page table page is unmapped. Returns TRUE if the
1417 * page table page was unmapped and FALSE otherwise.
1419 static inline boolean_t
1420 pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
1424 if (m->ref_count == 0) {
1425 _pmap_unwire_l3(pmap, va, m, free);
1432 _pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
1435 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1437 * unmap the page table page
1439 if (m->pindex >= (NUL2E + NUL1E)) {
1443 l0 = pmap_l0(pmap, va);
1445 } else if (m->pindex >= NUL2E) {
1449 l1 = pmap_l1(pmap, va);
1455 l2 = pmap_l2(pmap, va);
1458 pmap_resident_count_dec(pmap, 1);
1459 if (m->pindex < NUL2E) {
1460 /* We just released an l3, unhold the matching l2 */
1461 pd_entry_t *l1, tl1;
1464 l1 = pmap_l1(pmap, va);
1465 tl1 = pmap_load(l1);
1466 l2pg = PHYS_TO_VM_PAGE(tl1 & ~ATTR_MASK);
1467 pmap_unwire_l3(pmap, va, l2pg, free);
1468 } else if (m->pindex < (NUL2E + NUL1E)) {
1469 /* We just released an l2, unhold the matching l1 */
1470 pd_entry_t *l0, tl0;
1473 l0 = pmap_l0(pmap, va);
1474 tl0 = pmap_load(l0);
1475 l1pg = PHYS_TO_VM_PAGE(tl0 & ~ATTR_MASK);
1476 pmap_unwire_l3(pmap, va, l1pg, free);
1478 pmap_invalidate_page(pmap, va);
1481 * Put page on a list so that it is released after
1482 * *ALL* TLB shootdown is done
1484 pmap_add_delayed_free_list(m, free, TRUE);
1488 * After removing a page table entry, this routine is used to
1489 * conditionally free the page, and manage the reference count.
1492 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, pd_entry_t ptepde,
1493 struct spglist *free)
1497 if (va >= VM_MAXUSER_ADDRESS)
1499 KASSERT(ptepde != 0, ("pmap_unuse_pt: ptepde != 0"));
1500 mpte = PHYS_TO_VM_PAGE(ptepde & ~ATTR_MASK);
1501 return (pmap_unwire_l3(pmap, va, mpte, free));
1505 * Release a page table page reference after a failed attempt to create a
1509 pmap_abort_ptp(pmap_t pmap, vm_offset_t va, vm_page_t mpte)
1511 struct spglist free;
1514 if (pmap_unwire_l3(pmap, va, mpte, &free)) {
1516 * Although "va" was never mapped, the TLB could nonetheless
1517 * have intermediate entries that refer to the freed page
1518 * table pages. Invalidate those entries.
1520 * XXX redundant invalidation (See _pmap_unwire_l3().)
1522 pmap_invalidate_page(pmap, va);
1523 vm_page_free_pages_toq(&free, true);
1528 pmap_pinit0(pmap_t pmap)
1531 PMAP_LOCK_INIT(pmap);
1532 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats));
1533 pmap->pm_l0_paddr = READ_SPECIALREG(ttbr0_el1);
1534 pmap->pm_l0 = (pd_entry_t *)PHYS_TO_DMAP(pmap->pm_l0_paddr);
1535 pmap->pm_root.rt_root = 0;
1536 pmap->pm_cookie = COOKIE_FROM(ASID_RESERVED_FOR_PID_0, INT_MIN);
1538 PCPU_SET(curpmap, pmap);
1542 pmap_pinit(pmap_t pmap)
1547 * allocate the l0 page
1549 while ((l0pt = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
1550 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL)
1553 pmap->pm_l0_paddr = VM_PAGE_TO_PHYS(l0pt);
1554 pmap->pm_l0 = (pd_entry_t *)PHYS_TO_DMAP(pmap->pm_l0_paddr);
1556 if ((l0pt->flags & PG_ZERO) == 0)
1557 pagezero(pmap->pm_l0);
1559 pmap->pm_root.rt_root = 0;
1560 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats));
1561 pmap->pm_cookie = COOKIE_FROM(-1, INT_MAX);
1562 /* XXX Temporarily disable deferred ASID allocation. */
1563 pmap_alloc_asid(pmap);
1569 * This routine is called if the desired page table page does not exist.
1571 * If page table page allocation fails, this routine may sleep before
1572 * returning NULL. It sleeps only if a lock pointer was given.
1574 * Note: If a page allocation fails at page table level two or three,
1575 * one or two pages may be held during the wait, only to be released
1576 * afterwards. This conservative approach is easily argued to avoid
1580 _pmap_alloc_l3(pmap_t pmap, vm_pindex_t ptepindex, struct rwlock **lockp)
1582 vm_page_t m, l1pg, l2pg;
1584 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1587 * Allocate a page table page.
1589 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
1590 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
1591 if (lockp != NULL) {
1592 RELEASE_PV_LIST_LOCK(lockp);
1599 * Indicate the need to retry. While waiting, the page table
1600 * page may have been allocated.
1604 if ((m->flags & PG_ZERO) == 0)
1608 * Because of AArch64's weak memory consistency model, we must have a
1609 * barrier here to ensure that the stores for zeroing "m", whether by
1610 * pmap_zero_page() or an earlier function, are visible before adding
1611 * "m" to the page table. Otherwise, a page table walk by another
1612 * processor's MMU could see the mapping to "m" and a stale, non-zero
1618 * Map the pagetable page into the process address space, if
1619 * it isn't already there.
1622 if (ptepindex >= (NUL2E + NUL1E)) {
1624 vm_pindex_t l0index;
1626 l0index = ptepindex - (NUL2E + NUL1E);
1627 l0 = &pmap->pm_l0[l0index];
1628 pmap_store(l0, VM_PAGE_TO_PHYS(m) | L0_TABLE);
1629 } else if (ptepindex >= NUL2E) {
1630 vm_pindex_t l0index, l1index;
1631 pd_entry_t *l0, *l1;
1634 l1index = ptepindex - NUL2E;
1635 l0index = l1index >> L0_ENTRIES_SHIFT;
1637 l0 = &pmap->pm_l0[l0index];
1638 tl0 = pmap_load(l0);
1640 /* recurse for allocating page dir */
1641 if (_pmap_alloc_l3(pmap, NUL2E + NUL1E + l0index,
1643 vm_page_unwire_noq(m);
1644 vm_page_free_zero(m);
1648 l1pg = PHYS_TO_VM_PAGE(tl0 & ~ATTR_MASK);
1652 l1 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l0) & ~ATTR_MASK);
1653 l1 = &l1[ptepindex & Ln_ADDR_MASK];
1654 pmap_store(l1, VM_PAGE_TO_PHYS(m) | L1_TABLE);
1656 vm_pindex_t l0index, l1index;
1657 pd_entry_t *l0, *l1, *l2;
1658 pd_entry_t tl0, tl1;
1660 l1index = ptepindex >> Ln_ENTRIES_SHIFT;
1661 l0index = l1index >> L0_ENTRIES_SHIFT;
1663 l0 = &pmap->pm_l0[l0index];
1664 tl0 = pmap_load(l0);
1666 /* recurse for allocating page dir */
1667 if (_pmap_alloc_l3(pmap, NUL2E + l1index,
1669 vm_page_unwire_noq(m);
1670 vm_page_free_zero(m);
1673 tl0 = pmap_load(l0);
1674 l1 = (pd_entry_t *)PHYS_TO_DMAP(tl0 & ~ATTR_MASK);
1675 l1 = &l1[l1index & Ln_ADDR_MASK];
1677 l1 = (pd_entry_t *)PHYS_TO_DMAP(tl0 & ~ATTR_MASK);
1678 l1 = &l1[l1index & Ln_ADDR_MASK];
1679 tl1 = pmap_load(l1);
1681 /* recurse for allocating page dir */
1682 if (_pmap_alloc_l3(pmap, NUL2E + l1index,
1684 vm_page_unwire_noq(m);
1685 vm_page_free_zero(m);
1689 l2pg = PHYS_TO_VM_PAGE(tl1 & ~ATTR_MASK);
1694 l2 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l1) & ~ATTR_MASK);
1695 l2 = &l2[ptepindex & Ln_ADDR_MASK];
1696 pmap_store(l2, VM_PAGE_TO_PHYS(m) | L2_TABLE);
1699 pmap_resident_count_inc(pmap, 1);
1705 pmap_alloc_l2(pmap_t pmap, vm_offset_t va, vm_page_t *l2pgp,
1706 struct rwlock **lockp)
1708 pd_entry_t *l1, *l2;
1710 vm_pindex_t l2pindex;
1713 l1 = pmap_l1(pmap, va);
1714 if (l1 != NULL && (pmap_load(l1) & ATTR_DESCR_MASK) == L1_TABLE) {
1715 l2 = pmap_l1_to_l2(l1, va);
1716 if (va < VM_MAXUSER_ADDRESS) {
1717 /* Add a reference to the L2 page. */
1718 l2pg = PHYS_TO_VM_PAGE(pmap_load(l1) & ~ATTR_MASK);
1722 } else if (va < VM_MAXUSER_ADDRESS) {
1723 /* Allocate a L2 page. */
1724 l2pindex = pmap_l2_pindex(va) >> Ln_ENTRIES_SHIFT;
1725 l2pg = _pmap_alloc_l3(pmap, NUL2E + l2pindex, lockp);
1732 l2 = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(l2pg));
1733 l2 = &l2[pmap_l2_index(va)];
1735 panic("pmap_alloc_l2: missing page table page for va %#lx",
1742 pmap_alloc_l3(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
1744 vm_pindex_t ptepindex;
1745 pd_entry_t *pde, tpde;
1753 * Calculate pagetable page index
1755 ptepindex = pmap_l2_pindex(va);
1758 * Get the page directory entry
1760 pde = pmap_pde(pmap, va, &lvl);
1763 * If the page table page is mapped, we just increment the hold count,
1764 * and activate it. If we get a level 2 pde it will point to a level 3
1772 pte = pmap_l0_to_l1(pde, va);
1773 KASSERT(pmap_load(pte) == 0,
1774 ("pmap_alloc_l3: TODO: l0 superpages"));
1779 pte = pmap_l1_to_l2(pde, va);
1780 KASSERT(pmap_load(pte) == 0,
1781 ("pmap_alloc_l3: TODO: l1 superpages"));
1785 tpde = pmap_load(pde);
1787 m = PHYS_TO_VM_PAGE(tpde & ~ATTR_MASK);
1793 panic("pmap_alloc_l3: Invalid level %d", lvl);
1797 * Here if the pte page isn't mapped, or if it has been deallocated.
1799 m = _pmap_alloc_l3(pmap, ptepindex, lockp);
1800 if (m == NULL && lockp != NULL)
1806 /***************************************************
1807 * Pmap allocation/deallocation routines.
1808 ***************************************************/
1811 * Release any resources held by the given physical map.
1812 * Called when a pmap initialized by pmap_pinit is being released.
1813 * Should only be called if the map contains no valid mappings.
1816 pmap_release(pmap_t pmap)
1821 KASSERT(pmap->pm_stats.resident_count == 0,
1822 ("pmap_release: pmap resident count %ld != 0",
1823 pmap->pm_stats.resident_count));
1824 KASSERT(vm_radix_is_empty(&pmap->pm_root),
1825 ("pmap_release: pmap has reserved page table page(s)"));
1827 mtx_lock_spin(&asid_set_mutex);
1828 if (COOKIE_TO_EPOCH(pmap->pm_cookie) == asid_epoch) {
1829 asid = COOKIE_TO_ASID(pmap->pm_cookie);
1830 KASSERT(asid >= ASID_FIRST_AVAILABLE && asid < asid_set_size,
1831 ("pmap_release: pmap cookie has out-of-range asid"));
1832 bit_clear(asid_set, asid);
1834 mtx_unlock_spin(&asid_set_mutex);
1836 m = PHYS_TO_VM_PAGE(pmap->pm_l0_paddr);
1837 vm_page_unwire_noq(m);
1838 vm_page_free_zero(m);
1842 kvm_size(SYSCTL_HANDLER_ARGS)
1844 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS;
1846 return sysctl_handle_long(oidp, &ksize, 0, req);
1848 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG | CTLFLAG_RD | CTLFLAG_MPSAFE,
1849 0, 0, kvm_size, "LU",
1853 kvm_free(SYSCTL_HANDLER_ARGS)
1855 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
1857 return sysctl_handle_long(oidp, &kfree, 0, req);
1859 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG | CTLFLAG_RD | CTLFLAG_MPSAFE,
1860 0, 0, kvm_free, "LU",
1861 "Amount of KVM free");
1864 * grow the number of kernel page table entries, if needed
1867 pmap_growkernel(vm_offset_t addr)
1871 pd_entry_t *l0, *l1, *l2;
1873 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
1875 addr = roundup2(addr, L2_SIZE);
1876 if (addr - 1 >= vm_map_max(kernel_map))
1877 addr = vm_map_max(kernel_map);
1878 while (kernel_vm_end < addr) {
1879 l0 = pmap_l0(kernel_pmap, kernel_vm_end);
1880 KASSERT(pmap_load(l0) != 0,
1881 ("pmap_growkernel: No level 0 kernel entry"));
1883 l1 = pmap_l0_to_l1(l0, kernel_vm_end);
1884 if (pmap_load(l1) == 0) {
1885 /* We need a new PDP entry */
1886 nkpg = vm_page_alloc(NULL, kernel_vm_end >> L1_SHIFT,
1887 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ |
1888 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
1890 panic("pmap_growkernel: no memory to grow kernel");
1891 if ((nkpg->flags & PG_ZERO) == 0)
1892 pmap_zero_page(nkpg);
1893 /* See the dmb() in _pmap_alloc_l3(). */
1895 paddr = VM_PAGE_TO_PHYS(nkpg);
1896 pmap_store(l1, paddr | L1_TABLE);
1897 continue; /* try again */
1899 l2 = pmap_l1_to_l2(l1, kernel_vm_end);
1900 if (pmap_load(l2) != 0) {
1901 kernel_vm_end = (kernel_vm_end + L2_SIZE) & ~L2_OFFSET;
1902 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
1903 kernel_vm_end = vm_map_max(kernel_map);
1909 nkpg = vm_page_alloc(NULL, kernel_vm_end >> L2_SHIFT,
1910 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
1913 panic("pmap_growkernel: no memory to grow kernel");
1914 if ((nkpg->flags & PG_ZERO) == 0)
1915 pmap_zero_page(nkpg);
1916 /* See the dmb() in _pmap_alloc_l3(). */
1918 paddr = VM_PAGE_TO_PHYS(nkpg);
1919 pmap_store(l2, paddr | L2_TABLE);
1921 kernel_vm_end = (kernel_vm_end + L2_SIZE) & ~L2_OFFSET;
1922 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
1923 kernel_vm_end = vm_map_max(kernel_map);
1930 /***************************************************
1931 * page management routines.
1932 ***************************************************/
1934 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
1935 CTASSERT(_NPCM == 3);
1936 CTASSERT(_NPCPV == 168);
1938 static __inline struct pv_chunk *
1939 pv_to_chunk(pv_entry_t pv)
1942 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
1945 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
1947 #define PC_FREE0 0xfffffffffffffffful
1948 #define PC_FREE1 0xfffffffffffffffful
1949 #define PC_FREE2 0x000000fffffffffful
1951 static const uint64_t pc_freemask[_NPCM] = { PC_FREE0, PC_FREE1, PC_FREE2 };
1955 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
1957 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
1958 "Current number of pv entry chunks");
1959 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
1960 "Current number of pv entry chunks allocated");
1961 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
1962 "Current number of pv entry chunks frees");
1963 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
1964 "Number of times tried to get a chunk page but failed.");
1966 static long pv_entry_frees, pv_entry_allocs, pv_entry_count;
1967 static int pv_entry_spare;
1969 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
1970 "Current number of pv entry frees");
1971 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
1972 "Current number of pv entry allocs");
1973 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
1974 "Current number of pv entries");
1975 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
1976 "Current number of spare pv entries");
1981 * We are in a serious low memory condition. Resort to
1982 * drastic measures to free some pages so we can allocate
1983 * another pv entry chunk.
1985 * Returns NULL if PV entries were reclaimed from the specified pmap.
1987 * We do not, however, unmap 2mpages because subsequent accesses will
1988 * allocate per-page pv entries until repromotion occurs, thereby
1989 * exacerbating the shortage of free pv entries.
1992 reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp)
1994 struct pv_chunk *pc, *pc_marker, *pc_marker_end;
1995 struct pv_chunk_header pc_marker_b, pc_marker_end_b;
1996 struct md_page *pvh;
1998 pmap_t next_pmap, pmap;
1999 pt_entry_t *pte, tpte;
2003 struct spglist free;
2005 int bit, field, freed, lvl;
2006 static int active_reclaims = 0;
2008 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
2009 KASSERT(lockp != NULL, ("reclaim_pv_chunk: lockp is NULL"));
2014 bzero(&pc_marker_b, sizeof(pc_marker_b));
2015 bzero(&pc_marker_end_b, sizeof(pc_marker_end_b));
2016 pc_marker = (struct pv_chunk *)&pc_marker_b;
2017 pc_marker_end = (struct pv_chunk *)&pc_marker_end_b;
2019 mtx_lock(&pv_chunks_mutex);
2021 TAILQ_INSERT_HEAD(&pv_chunks, pc_marker, pc_lru);
2022 TAILQ_INSERT_TAIL(&pv_chunks, pc_marker_end, pc_lru);
2023 while ((pc = TAILQ_NEXT(pc_marker, pc_lru)) != pc_marker_end &&
2024 SLIST_EMPTY(&free)) {
2025 next_pmap = pc->pc_pmap;
2026 if (next_pmap == NULL) {
2028 * The next chunk is a marker. However, it is
2029 * not our marker, so active_reclaims must be
2030 * > 1. Consequently, the next_chunk code
2031 * will not rotate the pv_chunks list.
2035 mtx_unlock(&pv_chunks_mutex);
2038 * A pv_chunk can only be removed from the pc_lru list
2039 * when both pv_chunks_mutex is owned and the
2040 * corresponding pmap is locked.
2042 if (pmap != next_pmap) {
2043 if (pmap != NULL && pmap != locked_pmap)
2046 /* Avoid deadlock and lock recursion. */
2047 if (pmap > locked_pmap) {
2048 RELEASE_PV_LIST_LOCK(lockp);
2050 mtx_lock(&pv_chunks_mutex);
2052 } else if (pmap != locked_pmap) {
2053 if (PMAP_TRYLOCK(pmap)) {
2054 mtx_lock(&pv_chunks_mutex);
2057 pmap = NULL; /* pmap is not locked */
2058 mtx_lock(&pv_chunks_mutex);
2059 pc = TAILQ_NEXT(pc_marker, pc_lru);
2061 pc->pc_pmap != next_pmap)
2069 * Destroy every non-wired, 4 KB page mapping in the chunk.
2072 for (field = 0; field < _NPCM; field++) {
2073 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
2074 inuse != 0; inuse &= ~(1UL << bit)) {
2075 bit = ffsl(inuse) - 1;
2076 pv = &pc->pc_pventry[field * 64 + bit];
2078 pde = pmap_pde(pmap, va, &lvl);
2081 pte = pmap_l2_to_l3(pde, va);
2082 tpte = pmap_load(pte);
2083 if ((tpte & ATTR_SW_WIRED) != 0)
2085 tpte = pmap_load_clear(pte);
2086 m = PHYS_TO_VM_PAGE(tpte & ~ATTR_MASK);
2087 if (pmap_pte_dirty(tpte))
2089 if ((tpte & ATTR_AF) != 0) {
2090 pmap_invalidate_page(pmap, va);
2091 vm_page_aflag_set(m, PGA_REFERENCED);
2093 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
2094 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
2096 if (TAILQ_EMPTY(&m->md.pv_list) &&
2097 (m->flags & PG_FICTITIOUS) == 0) {
2098 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2099 if (TAILQ_EMPTY(&pvh->pv_list)) {
2100 vm_page_aflag_clear(m,
2104 pc->pc_map[field] |= 1UL << bit;
2105 pmap_unuse_pt(pmap, va, pmap_load(pde), &free);
2110 mtx_lock(&pv_chunks_mutex);
2113 /* Every freed mapping is for a 4 KB page. */
2114 pmap_resident_count_dec(pmap, freed);
2115 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
2116 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
2117 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
2118 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2119 if (pc->pc_map[0] == PC_FREE0 && pc->pc_map[1] == PC_FREE1 &&
2120 pc->pc_map[2] == PC_FREE2) {
2121 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
2122 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
2123 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
2124 /* Entire chunk is free; return it. */
2125 m_pc = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
2126 dump_drop_page(m_pc->phys_addr);
2127 mtx_lock(&pv_chunks_mutex);
2128 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2131 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2132 mtx_lock(&pv_chunks_mutex);
2133 /* One freed pv entry in locked_pmap is sufficient. */
2134 if (pmap == locked_pmap)
2138 TAILQ_REMOVE(&pv_chunks, pc_marker, pc_lru);
2139 TAILQ_INSERT_AFTER(&pv_chunks, pc, pc_marker, pc_lru);
2140 if (active_reclaims == 1 && pmap != NULL) {
2142 * Rotate the pv chunks list so that we do not
2143 * scan the same pv chunks that could not be
2144 * freed (because they contained a wired
2145 * and/or superpage mapping) on every
2146 * invocation of reclaim_pv_chunk().
2148 while ((pc = TAILQ_FIRST(&pv_chunks)) != pc_marker) {
2149 MPASS(pc->pc_pmap != NULL);
2150 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2151 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
2155 TAILQ_REMOVE(&pv_chunks, pc_marker, pc_lru);
2156 TAILQ_REMOVE(&pv_chunks, pc_marker_end, pc_lru);
2158 mtx_unlock(&pv_chunks_mutex);
2159 if (pmap != NULL && pmap != locked_pmap)
2161 if (m_pc == NULL && !SLIST_EMPTY(&free)) {
2162 m_pc = SLIST_FIRST(&free);
2163 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
2164 /* Recycle a freed page table page. */
2165 m_pc->ref_count = 1;
2167 vm_page_free_pages_toq(&free, true);
2172 * free the pv_entry back to the free list
2175 free_pv_entry(pmap_t pmap, pv_entry_t pv)
2177 struct pv_chunk *pc;
2178 int idx, field, bit;
2180 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2181 PV_STAT(atomic_add_long(&pv_entry_frees, 1));
2182 PV_STAT(atomic_add_int(&pv_entry_spare, 1));
2183 PV_STAT(atomic_subtract_long(&pv_entry_count, 1));
2184 pc = pv_to_chunk(pv);
2185 idx = pv - &pc->pc_pventry[0];
2188 pc->pc_map[field] |= 1ul << bit;
2189 if (pc->pc_map[0] != PC_FREE0 || pc->pc_map[1] != PC_FREE1 ||
2190 pc->pc_map[2] != PC_FREE2) {
2191 /* 98% of the time, pc is already at the head of the list. */
2192 if (__predict_false(pc != TAILQ_FIRST(&pmap->pm_pvchunk))) {
2193 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2194 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2198 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2203 free_pv_chunk(struct pv_chunk *pc)
2207 mtx_lock(&pv_chunks_mutex);
2208 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2209 mtx_unlock(&pv_chunks_mutex);
2210 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
2211 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
2212 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
2213 /* entire chunk is free, return it */
2214 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
2215 dump_drop_page(m->phys_addr);
2216 vm_page_unwire_noq(m);
2221 * Returns a new PV entry, allocating a new PV chunk from the system when
2222 * needed. If this PV chunk allocation fails and a PV list lock pointer was
2223 * given, a PV chunk is reclaimed from an arbitrary pmap. Otherwise, NULL is
2226 * The given PV list lock may be released.
2229 get_pv_entry(pmap_t pmap, struct rwlock **lockp)
2233 struct pv_chunk *pc;
2236 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2237 PV_STAT(atomic_add_long(&pv_entry_allocs, 1));
2239 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2241 for (field = 0; field < _NPCM; field++) {
2242 if (pc->pc_map[field]) {
2243 bit = ffsl(pc->pc_map[field]) - 1;
2247 if (field < _NPCM) {
2248 pv = &pc->pc_pventry[field * 64 + bit];
2249 pc->pc_map[field] &= ~(1ul << bit);
2250 /* If this was the last item, move it to tail */
2251 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 &&
2252 pc->pc_map[2] == 0) {
2253 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2254 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc,
2257 PV_STAT(atomic_add_long(&pv_entry_count, 1));
2258 PV_STAT(atomic_subtract_int(&pv_entry_spare, 1));
2262 /* No free items, allocate another chunk */
2263 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
2266 if (lockp == NULL) {
2267 PV_STAT(pc_chunk_tryfail++);
2270 m = reclaim_pv_chunk(pmap, lockp);
2274 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
2275 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
2276 dump_add_page(m->phys_addr);
2277 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
2279 pc->pc_map[0] = PC_FREE0 & ~1ul; /* preallocated bit 0 */
2280 pc->pc_map[1] = PC_FREE1;
2281 pc->pc_map[2] = PC_FREE2;
2282 mtx_lock(&pv_chunks_mutex);
2283 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
2284 mtx_unlock(&pv_chunks_mutex);
2285 pv = &pc->pc_pventry[0];
2286 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2287 PV_STAT(atomic_add_long(&pv_entry_count, 1));
2288 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV - 1));
2293 * Ensure that the number of spare PV entries in the specified pmap meets or
2294 * exceeds the given count, "needed".
2296 * The given PV list lock may be released.
2299 reserve_pv_entries(pmap_t pmap, int needed, struct rwlock **lockp)
2301 struct pch new_tail;
2302 struct pv_chunk *pc;
2307 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2308 KASSERT(lockp != NULL, ("reserve_pv_entries: lockp is NULL"));
2311 * Newly allocated PV chunks must be stored in a private list until
2312 * the required number of PV chunks have been allocated. Otherwise,
2313 * reclaim_pv_chunk() could recycle one of these chunks. In
2314 * contrast, these chunks must be added to the pmap upon allocation.
2316 TAILQ_INIT(&new_tail);
2319 TAILQ_FOREACH(pc, &pmap->pm_pvchunk, pc_list) {
2320 bit_count((bitstr_t *)pc->pc_map, 0,
2321 sizeof(pc->pc_map) * NBBY, &free);
2325 if (avail >= needed)
2328 for (reclaimed = false; avail < needed; avail += _NPCPV) {
2329 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
2332 m = reclaim_pv_chunk(pmap, lockp);
2337 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
2338 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
2339 dump_add_page(m->phys_addr);
2340 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
2342 pc->pc_map[0] = PC_FREE0;
2343 pc->pc_map[1] = PC_FREE1;
2344 pc->pc_map[2] = PC_FREE2;
2345 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2346 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
2347 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV));
2350 * The reclaim might have freed a chunk from the current pmap.
2351 * If that chunk contained available entries, we need to
2352 * re-count the number of available entries.
2357 if (!TAILQ_EMPTY(&new_tail)) {
2358 mtx_lock(&pv_chunks_mutex);
2359 TAILQ_CONCAT(&pv_chunks, &new_tail, pc_lru);
2360 mtx_unlock(&pv_chunks_mutex);
2365 * First find and then remove the pv entry for the specified pmap and virtual
2366 * address from the specified pv list. Returns the pv entry if found and NULL
2367 * otherwise. This operation can be performed on pv lists for either 4KB or
2368 * 2MB page mappings.
2370 static __inline pv_entry_t
2371 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2375 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
2376 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
2377 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
2386 * After demotion from a 2MB page mapping to 512 4KB page mappings,
2387 * destroy the pv entry for the 2MB page mapping and reinstantiate the pv
2388 * entries for each of the 4KB page mappings.
2391 pmap_pv_demote_l2(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
2392 struct rwlock **lockp)
2394 struct md_page *pvh;
2395 struct pv_chunk *pc;
2397 vm_offset_t va_last;
2401 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2402 KASSERT((va & L2_OFFSET) == 0,
2403 ("pmap_pv_demote_l2: va is not 2mpage aligned"));
2404 KASSERT((pa & L2_OFFSET) == 0,
2405 ("pmap_pv_demote_l2: pa is not 2mpage aligned"));
2406 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
2409 * Transfer the 2mpage's pv entry for this mapping to the first
2410 * page's pv list. Once this transfer begins, the pv list lock
2411 * must not be released until the last pv entry is reinstantiated.
2413 pvh = pa_to_pvh(pa);
2414 pv = pmap_pvh_remove(pvh, pmap, va);
2415 KASSERT(pv != NULL, ("pmap_pv_demote_l2: pv not found"));
2416 m = PHYS_TO_VM_PAGE(pa);
2417 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2419 /* Instantiate the remaining Ln_ENTRIES - 1 pv entries. */
2420 PV_STAT(atomic_add_long(&pv_entry_allocs, Ln_ENTRIES - 1));
2421 va_last = va + L2_SIZE - PAGE_SIZE;
2423 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2424 KASSERT(pc->pc_map[0] != 0 || pc->pc_map[1] != 0 ||
2425 pc->pc_map[2] != 0, ("pmap_pv_demote_l2: missing spare"));
2426 for (field = 0; field < _NPCM; field++) {
2427 while (pc->pc_map[field]) {
2428 bit = ffsl(pc->pc_map[field]) - 1;
2429 pc->pc_map[field] &= ~(1ul << bit);
2430 pv = &pc->pc_pventry[field * 64 + bit];
2434 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2435 ("pmap_pv_demote_l2: page %p is not managed", m));
2436 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2442 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2443 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2446 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 && pc->pc_map[2] == 0) {
2447 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2448 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2450 PV_STAT(atomic_add_long(&pv_entry_count, Ln_ENTRIES - 1));
2451 PV_STAT(atomic_subtract_int(&pv_entry_spare, Ln_ENTRIES - 1));
2455 * First find and then destroy the pv entry for the specified pmap and virtual
2456 * address. This operation can be performed on pv lists for either 4KB or 2MB
2460 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2464 pv = pmap_pvh_remove(pvh, pmap, va);
2465 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
2466 free_pv_entry(pmap, pv);
2470 * Conditionally create the PV entry for a 4KB page mapping if the required
2471 * memory can be allocated without resorting to reclamation.
2474 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m,
2475 struct rwlock **lockp)
2479 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2480 /* Pass NULL instead of the lock pointer to disable reclamation. */
2481 if ((pv = get_pv_entry(pmap, NULL)) != NULL) {
2483 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
2484 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2492 * Create the PV entry for a 2MB page mapping. Always returns true unless the
2493 * flag PMAP_ENTER_NORECLAIM is specified. If that flag is specified, returns
2494 * false if the PV entry cannot be allocated without resorting to reclamation.
2497 pmap_pv_insert_l2(pmap_t pmap, vm_offset_t va, pd_entry_t l2e, u_int flags,
2498 struct rwlock **lockp)
2500 struct md_page *pvh;
2504 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2505 /* Pass NULL instead of the lock pointer to disable reclamation. */
2506 if ((pv = get_pv_entry(pmap, (flags & PMAP_ENTER_NORECLAIM) != 0 ?
2507 NULL : lockp)) == NULL)
2510 pa = l2e & ~ATTR_MASK;
2511 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
2512 pvh = pa_to_pvh(pa);
2513 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2519 pmap_remove_kernel_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t va)
2521 pt_entry_t newl2, oldl2;
2525 KASSERT(!VIRT_IN_DMAP(va), ("removing direct mapping of %#lx", va));
2526 KASSERT(pmap == kernel_pmap, ("pmap %p is not kernel_pmap", pmap));
2527 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2529 ml3 = pmap_remove_pt_page(pmap, va);
2531 panic("pmap_remove_kernel_l2: Missing pt page");
2533 ml3pa = VM_PAGE_TO_PHYS(ml3);
2534 newl2 = ml3pa | L2_TABLE;
2537 * If this page table page was unmapped by a promotion, then it
2538 * contains valid mappings. Zero it to invalidate those mappings.
2540 if (ml3->valid != 0)
2541 pagezero((void *)PHYS_TO_DMAP(ml3pa));
2544 * Demote the mapping. The caller must have already invalidated the
2545 * mapping (i.e., the "break" in break-before-make).
2547 oldl2 = pmap_load_store(l2, newl2);
2548 KASSERT(oldl2 == 0, ("%s: found existing mapping at %p: %#lx",
2549 __func__, l2, oldl2));
2553 * pmap_remove_l2: Do the things to unmap a level 2 superpage.
2556 pmap_remove_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t sva,
2557 pd_entry_t l1e, struct spglist *free, struct rwlock **lockp)
2559 struct md_page *pvh;
2561 vm_offset_t eva, va;
2564 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2565 KASSERT((sva & L2_OFFSET) == 0, ("pmap_remove_l2: sva is not aligned"));
2566 old_l2 = pmap_load_clear(l2);
2567 KASSERT((old_l2 & ATTR_DESCR_MASK) == L2_BLOCK,
2568 ("pmap_remove_l2: L2e %lx is not a block mapping", old_l2));
2571 * Since a promotion must break the 4KB page mappings before making
2572 * the 2MB page mapping, a pmap_invalidate_page() suffices.
2574 pmap_invalidate_page(pmap, sva);
2576 if (old_l2 & ATTR_SW_WIRED)
2577 pmap->pm_stats.wired_count -= L2_SIZE / PAGE_SIZE;
2578 pmap_resident_count_dec(pmap, L2_SIZE / PAGE_SIZE);
2579 if (old_l2 & ATTR_SW_MANAGED) {
2580 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, old_l2 & ~ATTR_MASK);
2581 pvh = pa_to_pvh(old_l2 & ~ATTR_MASK);
2582 pmap_pvh_free(pvh, pmap, sva);
2583 eva = sva + L2_SIZE;
2584 for (va = sva, m = PHYS_TO_VM_PAGE(old_l2 & ~ATTR_MASK);
2585 va < eva; va += PAGE_SIZE, m++) {
2586 if (pmap_pte_dirty(old_l2))
2588 if (old_l2 & ATTR_AF)
2589 vm_page_aflag_set(m, PGA_REFERENCED);
2590 if (TAILQ_EMPTY(&m->md.pv_list) &&
2591 TAILQ_EMPTY(&pvh->pv_list))
2592 vm_page_aflag_clear(m, PGA_WRITEABLE);
2595 if (pmap == kernel_pmap) {
2596 pmap_remove_kernel_l2(pmap, l2, sva);
2598 ml3 = pmap_remove_pt_page(pmap, sva);
2600 KASSERT(ml3->valid == VM_PAGE_BITS_ALL,
2601 ("pmap_remove_l2: l3 page not promoted"));
2602 pmap_resident_count_dec(pmap, 1);
2603 KASSERT(ml3->ref_count == NL3PG,
2604 ("pmap_remove_l2: l3 page ref count error"));
2606 pmap_add_delayed_free_list(ml3, free, FALSE);
2609 return (pmap_unuse_pt(pmap, sva, l1e, free));
2613 * pmap_remove_l3: do the things to unmap a page in a process
2616 pmap_remove_l3(pmap_t pmap, pt_entry_t *l3, vm_offset_t va,
2617 pd_entry_t l2e, struct spglist *free, struct rwlock **lockp)
2619 struct md_page *pvh;
2623 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2624 old_l3 = pmap_load_clear(l3);
2625 pmap_invalidate_page(pmap, va);
2626 if (old_l3 & ATTR_SW_WIRED)
2627 pmap->pm_stats.wired_count -= 1;
2628 pmap_resident_count_dec(pmap, 1);
2629 if (old_l3 & ATTR_SW_MANAGED) {
2630 m = PHYS_TO_VM_PAGE(old_l3 & ~ATTR_MASK);
2631 if (pmap_pte_dirty(old_l3))
2633 if (old_l3 & ATTR_AF)
2634 vm_page_aflag_set(m, PGA_REFERENCED);
2635 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
2636 pmap_pvh_free(&m->md, pmap, va);
2637 if (TAILQ_EMPTY(&m->md.pv_list) &&
2638 (m->flags & PG_FICTITIOUS) == 0) {
2639 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2640 if (TAILQ_EMPTY(&pvh->pv_list))
2641 vm_page_aflag_clear(m, PGA_WRITEABLE);
2644 return (pmap_unuse_pt(pmap, va, l2e, free));
2648 * Remove the specified range of addresses from the L3 page table that is
2649 * identified by the given L2 entry.
2652 pmap_remove_l3_range(pmap_t pmap, pd_entry_t l2e, vm_offset_t sva,
2653 vm_offset_t eva, struct spglist *free, struct rwlock **lockp)
2655 struct md_page *pvh;
2656 struct rwlock *new_lock;
2657 pt_entry_t *l3, old_l3;
2661 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2662 KASSERT(rounddown2(sva, L2_SIZE) + L2_SIZE == roundup2(eva, L2_SIZE),
2663 ("pmap_remove_l3_range: range crosses an L3 page table boundary"));
2664 l3pg = sva < VM_MAXUSER_ADDRESS ? PHYS_TO_VM_PAGE(l2e & ~ATTR_MASK) :
2667 for (l3 = pmap_l2_to_l3(&l2e, sva); sva != eva; l3++, sva += L3_SIZE) {
2668 if (!pmap_l3_valid(pmap_load(l3))) {
2670 pmap_invalidate_range(pmap, va, sva);
2675 old_l3 = pmap_load_clear(l3);
2676 if ((old_l3 & ATTR_SW_WIRED) != 0)
2677 pmap->pm_stats.wired_count--;
2678 pmap_resident_count_dec(pmap, 1);
2679 if ((old_l3 & ATTR_SW_MANAGED) != 0) {
2680 m = PHYS_TO_VM_PAGE(old_l3 & ~ATTR_MASK);
2681 if (pmap_pte_dirty(old_l3))
2683 if ((old_l3 & ATTR_AF) != 0)
2684 vm_page_aflag_set(m, PGA_REFERENCED);
2685 new_lock = PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m));
2686 if (new_lock != *lockp) {
2687 if (*lockp != NULL) {
2689 * Pending TLB invalidations must be
2690 * performed before the PV list lock is
2691 * released. Otherwise, a concurrent
2692 * pmap_remove_all() on a physical page
2693 * could return while a stale TLB entry
2694 * still provides access to that page.
2697 pmap_invalidate_range(pmap, va,
2706 pmap_pvh_free(&m->md, pmap, sva);
2707 if (TAILQ_EMPTY(&m->md.pv_list) &&
2708 (m->flags & PG_FICTITIOUS) == 0) {
2709 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2710 if (TAILQ_EMPTY(&pvh->pv_list))
2711 vm_page_aflag_clear(m, PGA_WRITEABLE);
2716 if (l3pg != NULL && pmap_unwire_l3(pmap, sva, l3pg, free)) {
2722 pmap_invalidate_range(pmap, va, sva);
2726 * Remove the given range of addresses from the specified map.
2728 * It is assumed that the start and end are properly
2729 * rounded to the page size.
2732 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2734 struct rwlock *lock;
2735 vm_offset_t va_next;
2736 pd_entry_t *l0, *l1, *l2;
2737 pt_entry_t l3_paddr;
2738 struct spglist free;
2741 * Perform an unsynchronized read. This is, however, safe.
2743 if (pmap->pm_stats.resident_count == 0)
2751 for (; sva < eva; sva = va_next) {
2753 if (pmap->pm_stats.resident_count == 0)
2756 l0 = pmap_l0(pmap, sva);
2757 if (pmap_load(l0) == 0) {
2758 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
2764 l1 = pmap_l0_to_l1(l0, sva);
2765 if (pmap_load(l1) == 0) {
2766 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
2773 * Calculate index for next page table.
2775 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
2779 l2 = pmap_l1_to_l2(l1, sva);
2783 l3_paddr = pmap_load(l2);
2785 if ((l3_paddr & ATTR_DESCR_MASK) == L2_BLOCK) {
2786 if (sva + L2_SIZE == va_next && eva >= va_next) {
2787 pmap_remove_l2(pmap, l2, sva, pmap_load(l1),
2790 } else if (pmap_demote_l2_locked(pmap, l2, sva,
2793 l3_paddr = pmap_load(l2);
2797 * Weed out invalid mappings.
2799 if ((l3_paddr & ATTR_DESCR_MASK) != L2_TABLE)
2803 * Limit our scan to either the end of the va represented
2804 * by the current page table page, or to the end of the
2805 * range being removed.
2810 pmap_remove_l3_range(pmap, l3_paddr, sva, va_next, &free,
2816 vm_page_free_pages_toq(&free, true);
2820 * Routine: pmap_remove_all
2822 * Removes this physical page from
2823 * all physical maps in which it resides.
2824 * Reflects back modify bits to the pager.
2827 * Original versions of this routine were very
2828 * inefficient because they iteratively called
2829 * pmap_remove (slow...)
2833 pmap_remove_all(vm_page_t m)
2835 struct md_page *pvh;
2838 struct rwlock *lock;
2839 pd_entry_t *pde, tpde;
2840 pt_entry_t *pte, tpte;
2842 struct spglist free;
2843 int lvl, pvh_gen, md_gen;
2845 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2846 ("pmap_remove_all: page %p is not managed", m));
2848 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
2849 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
2850 pa_to_pvh(VM_PAGE_TO_PHYS(m));
2853 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
2855 if (!PMAP_TRYLOCK(pmap)) {
2856 pvh_gen = pvh->pv_gen;
2860 if (pvh_gen != pvh->pv_gen) {
2867 pte = pmap_pte(pmap, va, &lvl);
2868 KASSERT(pte != NULL,
2869 ("pmap_remove_all: no page table entry found"));
2871 ("pmap_remove_all: invalid pte level %d", lvl));
2873 pmap_demote_l2_locked(pmap, pte, va, &lock);
2876 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
2878 if (!PMAP_TRYLOCK(pmap)) {
2879 pvh_gen = pvh->pv_gen;
2880 md_gen = m->md.pv_gen;
2884 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
2890 pmap_resident_count_dec(pmap, 1);
2892 pde = pmap_pde(pmap, pv->pv_va, &lvl);
2893 KASSERT(pde != NULL,
2894 ("pmap_remove_all: no page directory entry found"));
2896 ("pmap_remove_all: invalid pde level %d", lvl));
2897 tpde = pmap_load(pde);
2899 pte = pmap_l2_to_l3(pde, pv->pv_va);
2900 tpte = pmap_load_clear(pte);
2901 if (tpte & ATTR_SW_WIRED)
2902 pmap->pm_stats.wired_count--;
2903 if ((tpte & ATTR_AF) != 0) {
2904 pmap_invalidate_page(pmap, pv->pv_va);
2905 vm_page_aflag_set(m, PGA_REFERENCED);
2909 * Update the vm_page_t clean and reference bits.
2911 if (pmap_pte_dirty(tpte))
2913 pmap_unuse_pt(pmap, pv->pv_va, tpde, &free);
2914 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
2916 free_pv_entry(pmap, pv);
2919 vm_page_aflag_clear(m, PGA_WRITEABLE);
2921 vm_page_free_pages_toq(&free, true);
2925 * pmap_protect_l2: do the things to protect a 2MB page in a pmap
2928 pmap_protect_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t sva, pt_entry_t mask,
2934 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2935 KASSERT((sva & L2_OFFSET) == 0,
2936 ("pmap_protect_l2: sva is not 2mpage aligned"));
2937 old_l2 = pmap_load(l2);
2938 KASSERT((old_l2 & ATTR_DESCR_MASK) == L2_BLOCK,
2939 ("pmap_protect_l2: L2e %lx is not a block mapping", old_l2));
2942 * Return if the L2 entry already has the desired access restrictions
2946 if ((old_l2 & mask) == nbits)
2950 * When a dirty read/write superpage mapping is write protected,
2951 * update the dirty field of each of the superpage's constituent 4KB
2954 if ((old_l2 & ATTR_SW_MANAGED) != 0 &&
2955 (nbits & ATTR_AP(ATTR_AP_RO)) != 0 && pmap_pte_dirty(old_l2)) {
2956 m = PHYS_TO_VM_PAGE(old_l2 & ~ATTR_MASK);
2957 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
2961 if (!atomic_fcmpset_64(l2, &old_l2, (old_l2 & ~mask) | nbits))
2965 * Since a promotion must break the 4KB page mappings before making
2966 * the 2MB page mapping, a pmap_invalidate_page() suffices.
2968 pmap_invalidate_page(pmap, sva);
2972 * Set the physical protection on the
2973 * specified range of this map as requested.
2976 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
2978 vm_offset_t va, va_next;
2979 pd_entry_t *l0, *l1, *l2;
2980 pt_entry_t *l3p, l3, mask, nbits;
2982 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
2983 if (prot == VM_PROT_NONE) {
2984 pmap_remove(pmap, sva, eva);
2989 if ((prot & VM_PROT_WRITE) == 0) {
2990 mask |= ATTR_AP_RW_BIT | ATTR_SW_DBM;
2991 nbits |= ATTR_AP(ATTR_AP_RO);
2993 if ((prot & VM_PROT_EXECUTE) == 0) {
3001 for (; sva < eva; sva = va_next) {
3003 l0 = pmap_l0(pmap, sva);
3004 if (pmap_load(l0) == 0) {
3005 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
3011 l1 = pmap_l0_to_l1(l0, sva);
3012 if (pmap_load(l1) == 0) {
3013 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
3019 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
3023 l2 = pmap_l1_to_l2(l1, sva);
3024 if (pmap_load(l2) == 0)
3027 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK) {
3028 if (sva + L2_SIZE == va_next && eva >= va_next) {
3029 pmap_protect_l2(pmap, l2, sva, mask, nbits);
3031 } else if (pmap_demote_l2(pmap, l2, sva) == NULL)
3034 KASSERT((pmap_load(l2) & ATTR_DESCR_MASK) == L2_TABLE,
3035 ("pmap_protect: Invalid L2 entry after demotion"));
3041 for (l3p = pmap_l2_to_l3(l2, sva); sva != va_next; l3p++,
3043 l3 = pmap_load(l3p);
3046 * Go to the next L3 entry if the current one is
3047 * invalid or already has the desired access
3048 * restrictions in place. (The latter case occurs
3049 * frequently. For example, in a "buildworld"
3050 * workload, almost 1 out of 4 L3 entries already
3051 * have the desired restrictions.)
3053 if (!pmap_l3_valid(l3) || (l3 & mask) == nbits) {
3054 if (va != va_next) {
3055 pmap_invalidate_range(pmap, va, sva);
3062 * When a dirty read/write mapping is write protected,
3063 * update the page's dirty field.
3065 if ((l3 & ATTR_SW_MANAGED) != 0 &&
3066 (nbits & ATTR_AP(ATTR_AP_RO)) != 0 &&
3068 vm_page_dirty(PHYS_TO_VM_PAGE(l3 & ~ATTR_MASK));
3070 if (!atomic_fcmpset_64(l3p, &l3, (l3 & ~mask) | nbits))
3076 pmap_invalidate_range(pmap, va, sva);
3082 * Inserts the specified page table page into the specified pmap's collection
3083 * of idle page table pages. Each of a pmap's page table pages is responsible
3084 * for mapping a distinct range of virtual addresses. The pmap's collection is
3085 * ordered by this virtual address range.
3087 * If "promoted" is false, then the page table page "mpte" must be zero filled.
3090 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte, bool promoted)
3093 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3094 mpte->valid = promoted ? VM_PAGE_BITS_ALL : 0;
3095 return (vm_radix_insert(&pmap->pm_root, mpte));
3099 * Removes the page table page mapping the specified virtual address from the
3100 * specified pmap's collection of idle page table pages, and returns it.
3101 * Otherwise, returns NULL if there is no page table page corresponding to the
3102 * specified virtual address.
3104 static __inline vm_page_t
3105 pmap_remove_pt_page(pmap_t pmap, vm_offset_t va)
3108 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3109 return (vm_radix_remove(&pmap->pm_root, pmap_l2_pindex(va)));
3113 * Performs a break-before-make update of a pmap entry. This is needed when
3114 * either promoting or demoting pages to ensure the TLB doesn't get into an
3115 * inconsistent state.
3118 pmap_update_entry(pmap_t pmap, pd_entry_t *pte, pd_entry_t newpte,
3119 vm_offset_t va, vm_size_t size)
3123 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3126 * Ensure we don't get switched out with the page table in an
3127 * inconsistent state. We also need to ensure no interrupts fire
3128 * as they may make use of an address we are about to invalidate.
3130 intr = intr_disable();
3133 * Clear the old mapping's valid bit, but leave the rest of the entry
3134 * unchanged, so that a lockless, concurrent pmap_kextract() can still
3135 * lookup the physical address.
3137 pmap_clear_bits(pte, ATTR_DESCR_VALID);
3138 pmap_invalidate_range(pmap, va, va + size);
3140 /* Create the new mapping */
3141 pmap_store(pte, newpte);
3147 #if VM_NRESERVLEVEL > 0
3149 * After promotion from 512 4KB page mappings to a single 2MB page mapping,
3150 * replace the many pv entries for the 4KB page mappings by a single pv entry
3151 * for the 2MB page mapping.
3154 pmap_pv_promote_l2(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
3155 struct rwlock **lockp)
3157 struct md_page *pvh;
3159 vm_offset_t va_last;
3162 KASSERT((pa & L2_OFFSET) == 0,
3163 ("pmap_pv_promote_l2: pa is not 2mpage aligned"));
3164 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
3167 * Transfer the first page's pv entry for this mapping to the 2mpage's
3168 * pv list. Aside from avoiding the cost of a call to get_pv_entry(),
3169 * a transfer avoids the possibility that get_pv_entry() calls
3170 * reclaim_pv_chunk() and that reclaim_pv_chunk() removes one of the
3171 * mappings that is being promoted.
3173 m = PHYS_TO_VM_PAGE(pa);
3174 va = va & ~L2_OFFSET;
3175 pv = pmap_pvh_remove(&m->md, pmap, va);
3176 KASSERT(pv != NULL, ("pmap_pv_promote_l2: pv not found"));
3177 pvh = pa_to_pvh(pa);
3178 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
3180 /* Free the remaining NPTEPG - 1 pv entries. */
3181 va_last = va + L2_SIZE - PAGE_SIZE;
3185 pmap_pvh_free(&m->md, pmap, va);
3186 } while (va < va_last);
3190 * Tries to promote the 512, contiguous 4KB page mappings that are within a
3191 * single level 2 table entry to a single 2MB page mapping. For promotion
3192 * to occur, two conditions must be met: (1) the 4KB page mappings must map
3193 * aligned, contiguous physical memory and (2) the 4KB page mappings must have
3194 * identical characteristics.
3197 pmap_promote_l2(pmap_t pmap, pd_entry_t *l2, vm_offset_t va,
3198 struct rwlock **lockp)
3200 pt_entry_t *firstl3, *l3, newl2, oldl3, pa;
3204 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3206 sva = va & ~L2_OFFSET;
3207 firstl3 = pmap_l2_to_l3(l2, sva);
3208 newl2 = pmap_load(firstl3);
3211 if (((newl2 & (~ATTR_MASK | ATTR_AF)) & L2_OFFSET) != ATTR_AF) {
3212 atomic_add_long(&pmap_l2_p_failures, 1);
3213 CTR2(KTR_PMAP, "pmap_promote_l2: failure for va %#lx"
3214 " in pmap %p", va, pmap);
3218 if ((newl2 & (ATTR_AP_RW_BIT | ATTR_SW_DBM)) ==
3219 (ATTR_AP(ATTR_AP_RO) | ATTR_SW_DBM)) {
3220 if (!atomic_fcmpset_64(l2, &newl2, newl2 & ~ATTR_SW_DBM))
3222 newl2 &= ~ATTR_SW_DBM;
3225 pa = newl2 + L2_SIZE - PAGE_SIZE;
3226 for (l3 = firstl3 + NL3PG - 1; l3 > firstl3; l3--) {
3227 oldl3 = pmap_load(l3);
3229 if ((oldl3 & (ATTR_AP_RW_BIT | ATTR_SW_DBM)) ==
3230 (ATTR_AP(ATTR_AP_RO) | ATTR_SW_DBM)) {
3231 if (!atomic_fcmpset_64(l3, &oldl3, oldl3 &
3234 oldl3 &= ~ATTR_SW_DBM;
3237 atomic_add_long(&pmap_l2_p_failures, 1);
3238 CTR2(KTR_PMAP, "pmap_promote_l2: failure for va %#lx"
3239 " in pmap %p", va, pmap);
3246 * Save the page table page in its current state until the L2
3247 * mapping the superpage is demoted by pmap_demote_l2() or
3248 * destroyed by pmap_remove_l3().
3250 mpte = PHYS_TO_VM_PAGE(pmap_load(l2) & ~ATTR_MASK);
3251 KASSERT(mpte >= vm_page_array &&
3252 mpte < &vm_page_array[vm_page_array_size],
3253 ("pmap_promote_l2: page table page is out of range"));
3254 KASSERT(mpte->pindex == pmap_l2_pindex(va),
3255 ("pmap_promote_l2: page table page's pindex is wrong"));
3256 if (pmap_insert_pt_page(pmap, mpte, true)) {
3257 atomic_add_long(&pmap_l2_p_failures, 1);
3259 "pmap_promote_l2: failure for va %#lx in pmap %p", va,
3264 if ((newl2 & ATTR_SW_MANAGED) != 0)
3265 pmap_pv_promote_l2(pmap, va, newl2 & ~ATTR_MASK, lockp);
3267 newl2 &= ~ATTR_DESCR_MASK;
3270 pmap_update_entry(pmap, l2, newl2, sva, L2_SIZE);
3272 atomic_add_long(&pmap_l2_promotions, 1);
3273 CTR2(KTR_PMAP, "pmap_promote_l2: success for va %#lx in pmap %p", va,
3276 #endif /* VM_NRESERVLEVEL > 0 */
3279 * Insert the given physical page (p) at
3280 * the specified virtual address (v) in the
3281 * target physical map with the protection requested.
3283 * If specified, the page will be wired down, meaning
3284 * that the related pte can not be reclaimed.
3286 * NB: This is the only routine which MAY NOT lazy-evaluate
3287 * or lose information. That is, this routine must actually
3288 * insert this page into the given map NOW.
3291 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
3292 u_int flags, int8_t psind)
3294 struct rwlock *lock;
3296 pt_entry_t new_l3, orig_l3;
3297 pt_entry_t *l2, *l3;
3304 va = trunc_page(va);
3305 if ((m->oflags & VPO_UNMANAGED) == 0)
3306 VM_PAGE_OBJECT_BUSY_ASSERT(m);
3307 pa = VM_PAGE_TO_PHYS(m);
3308 new_l3 = (pt_entry_t)(pa | ATTR_DEFAULT | ATTR_IDX(m->md.pv_memattr) |
3310 if ((prot & VM_PROT_WRITE) == 0)
3311 new_l3 |= ATTR_AP(ATTR_AP_RO);
3312 if ((prot & VM_PROT_EXECUTE) == 0 ||
3313 m->md.pv_memattr == VM_MEMATTR_DEVICE)
3315 if ((flags & PMAP_ENTER_WIRED) != 0)
3316 new_l3 |= ATTR_SW_WIRED;
3317 if (va < VM_MAXUSER_ADDRESS)
3318 new_l3 |= ATTR_AP(ATTR_AP_USER) | ATTR_PXN;
3321 if (pmap != kernel_pmap)
3323 if ((m->oflags & VPO_UNMANAGED) == 0) {
3324 new_l3 |= ATTR_SW_MANAGED;
3325 if ((prot & VM_PROT_WRITE) != 0) {
3326 new_l3 |= ATTR_SW_DBM;
3327 if ((flags & VM_PROT_WRITE) == 0)
3328 new_l3 |= ATTR_AP(ATTR_AP_RO);
3332 CTR2(KTR_PMAP, "pmap_enter: %.16lx -> %.16lx", va, pa);
3337 /* Assert the required virtual and physical alignment. */
3338 KASSERT((va & L2_OFFSET) == 0, ("pmap_enter: va unaligned"));
3339 KASSERT(m->psind > 0, ("pmap_enter: m->psind < psind"));
3340 rv = pmap_enter_l2(pmap, va, (new_l3 & ~L3_PAGE) | L2_BLOCK,
3347 * In the case that a page table page is not
3348 * resident, we are creating it here.
3351 pde = pmap_pde(pmap, va, &lvl);
3352 if (pde != NULL && lvl == 2) {
3353 l3 = pmap_l2_to_l3(pde, va);
3354 if (va < VM_MAXUSER_ADDRESS && mpte == NULL) {
3355 mpte = PHYS_TO_VM_PAGE(pmap_load(pde) & ~ATTR_MASK);
3359 } else if (pde != NULL && lvl == 1) {
3360 l2 = pmap_l1_to_l2(pde, va);
3361 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK &&
3362 (l3 = pmap_demote_l2_locked(pmap, l2, va, &lock)) != NULL) {
3363 l3 = &l3[pmap_l3_index(va)];
3364 if (va < VM_MAXUSER_ADDRESS) {
3365 mpte = PHYS_TO_VM_PAGE(
3366 pmap_load(l2) & ~ATTR_MASK);
3371 /* We need to allocate an L3 table. */
3373 if (va < VM_MAXUSER_ADDRESS) {
3374 nosleep = (flags & PMAP_ENTER_NOSLEEP) != 0;
3377 * We use _pmap_alloc_l3() instead of pmap_alloc_l3() in order
3378 * to handle the possibility that a superpage mapping for "va"
3379 * was created while we slept.
3381 mpte = _pmap_alloc_l3(pmap, pmap_l2_pindex(va),
3382 nosleep ? NULL : &lock);
3383 if (mpte == NULL && nosleep) {
3384 CTR0(KTR_PMAP, "pmap_enter: mpte == NULL");
3385 rv = KERN_RESOURCE_SHORTAGE;
3390 panic("pmap_enter: missing L3 table for kernel va %#lx", va);
3393 orig_l3 = pmap_load(l3);
3394 opa = orig_l3 & ~ATTR_MASK;
3398 * Is the specified virtual address already mapped?
3400 if (pmap_l3_valid(orig_l3)) {
3402 * Wiring change, just update stats. We don't worry about
3403 * wiring PT pages as they remain resident as long as there
3404 * are valid mappings in them. Hence, if a user page is wired,
3405 * the PT page will be also.
3407 if ((flags & PMAP_ENTER_WIRED) != 0 &&
3408 (orig_l3 & ATTR_SW_WIRED) == 0)
3409 pmap->pm_stats.wired_count++;
3410 else if ((flags & PMAP_ENTER_WIRED) == 0 &&
3411 (orig_l3 & ATTR_SW_WIRED) != 0)
3412 pmap->pm_stats.wired_count--;
3415 * Remove the extra PT page reference.
3419 KASSERT(mpte->ref_count > 0,
3420 ("pmap_enter: missing reference to page table page,"
3425 * Has the physical page changed?
3429 * No, might be a protection or wiring change.
3431 if ((orig_l3 & ATTR_SW_MANAGED) != 0 &&
3432 (new_l3 & ATTR_SW_DBM) != 0)
3433 vm_page_aflag_set(m, PGA_WRITEABLE);
3438 * The physical page has changed. Temporarily invalidate
3441 orig_l3 = pmap_load_clear(l3);
3442 KASSERT((orig_l3 & ~ATTR_MASK) == opa,
3443 ("pmap_enter: unexpected pa update for %#lx", va));
3444 if ((orig_l3 & ATTR_SW_MANAGED) != 0) {
3445 om = PHYS_TO_VM_PAGE(opa);
3448 * The pmap lock is sufficient to synchronize with
3449 * concurrent calls to pmap_page_test_mappings() and
3450 * pmap_ts_referenced().
3452 if (pmap_pte_dirty(orig_l3))
3454 if ((orig_l3 & ATTR_AF) != 0) {
3455 pmap_invalidate_page(pmap, va);
3456 vm_page_aflag_set(om, PGA_REFERENCED);
3458 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, opa);
3459 pv = pmap_pvh_remove(&om->md, pmap, va);
3460 if ((m->oflags & VPO_UNMANAGED) != 0)
3461 free_pv_entry(pmap, pv);
3462 if ((om->a.flags & PGA_WRITEABLE) != 0 &&
3463 TAILQ_EMPTY(&om->md.pv_list) &&
3464 ((om->flags & PG_FICTITIOUS) != 0 ||
3465 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
3466 vm_page_aflag_clear(om, PGA_WRITEABLE);
3468 KASSERT((orig_l3 & ATTR_AF) != 0,
3469 ("pmap_enter: unmanaged mapping lacks ATTR_AF"));
3470 pmap_invalidate_page(pmap, va);
3475 * Increment the counters.
3477 if ((new_l3 & ATTR_SW_WIRED) != 0)
3478 pmap->pm_stats.wired_count++;
3479 pmap_resident_count_inc(pmap, 1);
3482 * Enter on the PV list if part of our managed memory.
3484 if ((m->oflags & VPO_UNMANAGED) == 0) {
3486 pv = get_pv_entry(pmap, &lock);
3489 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, pa);
3490 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3492 if ((new_l3 & ATTR_SW_DBM) != 0)
3493 vm_page_aflag_set(m, PGA_WRITEABLE);
3498 * Sync icache if exec permission and attribute VM_MEMATTR_WRITE_BACK
3499 * is set. Do it now, before the mapping is stored and made
3500 * valid for hardware table walk. If done later, then other can
3501 * access this page before caches are properly synced.
3502 * Don't do it for kernel memory which is mapped with exec
3503 * permission even if the memory isn't going to hold executable
3504 * code. The only time when icache sync is needed is after
3505 * kernel module is loaded and the relocation info is processed.
3506 * And it's done in elf_cpu_load_file().
3508 if ((prot & VM_PROT_EXECUTE) && pmap != kernel_pmap &&
3509 m->md.pv_memattr == VM_MEMATTR_WRITE_BACK &&
3510 (opa != pa || (orig_l3 & ATTR_XN)))
3511 cpu_icache_sync_range(PHYS_TO_DMAP(pa), PAGE_SIZE);
3514 * Update the L3 entry
3516 if (pmap_l3_valid(orig_l3)) {
3517 KASSERT(opa == pa, ("pmap_enter: invalid update"));
3518 if ((orig_l3 & ~ATTR_AF) != (new_l3 & ~ATTR_AF)) {
3519 /* same PA, different attributes */
3520 orig_l3 = pmap_load_store(l3, new_l3);
3521 pmap_invalidate_page(pmap, va);
3522 if ((orig_l3 & ATTR_SW_MANAGED) != 0 &&
3523 pmap_pte_dirty(orig_l3))
3528 * This can happens if multiple threads simultaneously
3529 * access not yet mapped page. This bad for performance
3530 * since this can cause full demotion-NOP-promotion
3532 * Another possible reasons are:
3533 * - VM and pmap memory layout are diverged
3534 * - tlb flush is missing somewhere and CPU doesn't see
3537 CTR4(KTR_PMAP, "%s: already mapped page - "
3538 "pmap %p va 0x%#lx pte 0x%lx",
3539 __func__, pmap, va, new_l3);
3543 pmap_store(l3, new_l3);
3547 #if VM_NRESERVLEVEL > 0
3548 if ((mpte == NULL || mpte->ref_count == NL3PG) &&
3549 pmap_ps_enabled(pmap) &&
3550 (m->flags & PG_FICTITIOUS) == 0 &&
3551 vm_reserv_level_iffullpop(m) == 0) {
3552 pmap_promote_l2(pmap, pde, va, &lock);
3565 * Tries to create a read- and/or execute-only 2MB page mapping. Returns true
3566 * if successful. Returns false if (1) a page table page cannot be allocated
3567 * without sleeping, (2) a mapping already exists at the specified virtual
3568 * address, or (3) a PV entry cannot be allocated without reclaiming another
3572 pmap_enter_2mpage(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
3573 struct rwlock **lockp)
3577 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3579 new_l2 = (pd_entry_t)(VM_PAGE_TO_PHYS(m) | ATTR_DEFAULT |
3580 ATTR_IDX(m->md.pv_memattr) | ATTR_AP(ATTR_AP_RO) | L2_BLOCK);
3581 if ((m->oflags & VPO_UNMANAGED) == 0) {
3582 new_l2 |= ATTR_SW_MANAGED;
3585 if ((prot & VM_PROT_EXECUTE) == 0 ||
3586 m->md.pv_memattr == VM_MEMATTR_DEVICE)
3588 if (va < VM_MAXUSER_ADDRESS)
3589 new_l2 |= ATTR_AP(ATTR_AP_USER) | ATTR_PXN;
3592 if (pmap != kernel_pmap)
3594 return (pmap_enter_l2(pmap, va, new_l2, PMAP_ENTER_NOSLEEP |
3595 PMAP_ENTER_NOREPLACE | PMAP_ENTER_NORECLAIM, NULL, lockp) ==
3600 * Returns true if every page table entry in the specified page table is
3604 pmap_every_pte_zero(vm_paddr_t pa)
3606 pt_entry_t *pt_end, *pte;
3608 KASSERT((pa & PAGE_MASK) == 0, ("pa is misaligned"));
3609 pte = (pt_entry_t *)PHYS_TO_DMAP(pa);
3610 for (pt_end = pte + Ln_ENTRIES; pte < pt_end; pte++) {
3618 * Tries to create the specified 2MB page mapping. Returns KERN_SUCCESS if
3619 * the mapping was created, and either KERN_FAILURE or KERN_RESOURCE_SHORTAGE
3620 * otherwise. Returns KERN_FAILURE if PMAP_ENTER_NOREPLACE was specified and
3621 * a mapping already exists at the specified virtual address. Returns
3622 * KERN_RESOURCE_SHORTAGE if PMAP_ENTER_NOSLEEP was specified and a page table
3623 * page allocation failed. Returns KERN_RESOURCE_SHORTAGE if
3624 * PMAP_ENTER_NORECLAIM was specified and a PV entry allocation failed.
3626 * The parameter "m" is only used when creating a managed, writeable mapping.
3629 pmap_enter_l2(pmap_t pmap, vm_offset_t va, pd_entry_t new_l2, u_int flags,
3630 vm_page_t m, struct rwlock **lockp)
3632 struct spglist free;
3633 pd_entry_t *l2, old_l2;
3636 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3638 if ((l2 = pmap_alloc_l2(pmap, va, &l2pg, (flags &
3639 PMAP_ENTER_NOSLEEP) != 0 ? NULL : lockp)) == NULL) {
3640 CTR2(KTR_PMAP, "pmap_enter_l2: failure for va %#lx in pmap %p",
3642 return (KERN_RESOURCE_SHORTAGE);
3646 * If there are existing mappings, either abort or remove them.
3648 if ((old_l2 = pmap_load(l2)) != 0) {
3649 KASSERT(l2pg == NULL || l2pg->ref_count > 1,
3650 ("pmap_enter_l2: l2pg's ref count is too low"));
3651 if ((flags & PMAP_ENTER_NOREPLACE) != 0 && (va <
3652 VM_MAXUSER_ADDRESS || (old_l2 & ATTR_DESCR_MASK) ==
3653 L2_BLOCK || !pmap_every_pte_zero(old_l2 & ~ATTR_MASK))) {
3656 CTR2(KTR_PMAP, "pmap_enter_l2: failure for va %#lx"
3657 " in pmap %p", va, pmap);
3658 return (KERN_FAILURE);
3661 if ((old_l2 & ATTR_DESCR_MASK) == L2_BLOCK)
3662 (void)pmap_remove_l2(pmap, l2, va,
3663 pmap_load(pmap_l1(pmap, va)), &free, lockp);
3665 pmap_remove_l3_range(pmap, old_l2, va, va + L2_SIZE,
3667 if (va < VM_MAXUSER_ADDRESS) {
3668 vm_page_free_pages_toq(&free, true);
3669 KASSERT(pmap_load(l2) == 0,
3670 ("pmap_enter_l2: non-zero L2 entry %p", l2));
3672 KASSERT(SLIST_EMPTY(&free),
3673 ("pmap_enter_l2: freed kernel page table page"));
3676 * Both pmap_remove_l2() and pmap_remove_l3_range()
3677 * will leave the kernel page table page zero filled.
3678 * Nonetheless, the TLB could have an intermediate
3679 * entry for the kernel page table page.
3681 mt = PHYS_TO_VM_PAGE(pmap_load(l2) & ~ATTR_MASK);
3682 if (pmap_insert_pt_page(pmap, mt, false))
3683 panic("pmap_enter_l2: trie insert failed");
3685 pmap_invalidate_page(pmap, va);
3689 if ((new_l2 & ATTR_SW_MANAGED) != 0) {
3691 * Abort this mapping if its PV entry could not be created.
3693 if (!pmap_pv_insert_l2(pmap, va, new_l2, flags, lockp)) {
3695 pmap_abort_ptp(pmap, va, l2pg);
3697 "pmap_enter_l2: failure for va %#lx in pmap %p",
3699 return (KERN_RESOURCE_SHORTAGE);
3701 if ((new_l2 & ATTR_SW_DBM) != 0)
3702 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
3703 vm_page_aflag_set(mt, PGA_WRITEABLE);
3707 * Increment counters.
3709 if ((new_l2 & ATTR_SW_WIRED) != 0)
3710 pmap->pm_stats.wired_count += L2_SIZE / PAGE_SIZE;
3711 pmap->pm_stats.resident_count += L2_SIZE / PAGE_SIZE;
3714 * Map the superpage.
3716 pmap_store(l2, new_l2);
3719 atomic_add_long(&pmap_l2_mappings, 1);
3720 CTR2(KTR_PMAP, "pmap_enter_l2: success for va %#lx in pmap %p",
3723 return (KERN_SUCCESS);
3727 * Maps a sequence of resident pages belonging to the same object.
3728 * The sequence begins with the given page m_start. This page is
3729 * mapped at the given virtual address start. Each subsequent page is
3730 * mapped at a virtual address that is offset from start by the same
3731 * amount as the page is offset from m_start within the object. The
3732 * last page in the sequence is the page with the largest offset from
3733 * m_start that can be mapped at a virtual address less than the given
3734 * virtual address end. Not every virtual page between start and end
3735 * is mapped; only those for which a resident page exists with the
3736 * corresponding offset from m_start are mapped.
3739 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
3740 vm_page_t m_start, vm_prot_t prot)
3742 struct rwlock *lock;
3745 vm_pindex_t diff, psize;
3747 VM_OBJECT_ASSERT_LOCKED(m_start->object);
3749 psize = atop(end - start);
3754 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
3755 va = start + ptoa(diff);
3756 if ((va & L2_OFFSET) == 0 && va + L2_SIZE <= end &&
3757 m->psind == 1 && pmap_ps_enabled(pmap) &&
3758 pmap_enter_2mpage(pmap, va, m, prot, &lock))
3759 m = &m[L2_SIZE / PAGE_SIZE - 1];
3761 mpte = pmap_enter_quick_locked(pmap, va, m, prot, mpte,
3763 m = TAILQ_NEXT(m, listq);
3771 * this code makes some *MAJOR* assumptions:
3772 * 1. Current pmap & pmap exists.
3775 * 4. No page table pages.
3776 * but is *MUCH* faster than pmap_enter...
3780 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3782 struct rwlock *lock;
3786 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL, &lock);
3793 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
3794 vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp)
3797 pt_entry_t *l2, *l3, l3_val;
3801 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
3802 (m->oflags & VPO_UNMANAGED) != 0,
3803 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
3804 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3806 CTR2(KTR_PMAP, "pmap_enter_quick_locked: %p %lx", pmap, va);
3808 * In the case that a page table page is not
3809 * resident, we are creating it here.
3811 if (va < VM_MAXUSER_ADDRESS) {
3812 vm_pindex_t l2pindex;
3815 * Calculate pagetable page index
3817 l2pindex = pmap_l2_pindex(va);
3818 if (mpte && (mpte->pindex == l2pindex)) {
3824 pde = pmap_pde(pmap, va, &lvl);
3827 * If the page table page is mapped, we just increment
3828 * the hold count, and activate it. Otherwise, we
3829 * attempt to allocate a page table page. If this
3830 * attempt fails, we don't retry. Instead, we give up.
3833 l2 = pmap_l1_to_l2(pde, va);
3834 if ((pmap_load(l2) & ATTR_DESCR_MASK) ==
3838 if (lvl == 2 && pmap_load(pde) != 0) {
3840 PHYS_TO_VM_PAGE(pmap_load(pde) & ~ATTR_MASK);
3844 * Pass NULL instead of the PV list lock
3845 * pointer, because we don't intend to sleep.
3847 mpte = _pmap_alloc_l3(pmap, l2pindex, NULL);
3852 l3 = (pt_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpte));
3853 l3 = &l3[pmap_l3_index(va)];
3856 pde = pmap_pde(kernel_pmap, va, &lvl);
3857 KASSERT(pde != NULL,
3858 ("pmap_enter_quick_locked: Invalid page entry, va: 0x%lx",
3861 ("pmap_enter_quick_locked: Invalid level %d", lvl));
3862 l3 = pmap_l2_to_l3(pde, va);
3866 * Abort if a mapping already exists.
3868 if (pmap_load(l3) != 0) {
3875 * Enter on the PV list if part of our managed memory.
3877 if ((m->oflags & VPO_UNMANAGED) == 0 &&
3878 !pmap_try_insert_pv_entry(pmap, va, m, lockp)) {
3880 pmap_abort_ptp(pmap, va, mpte);
3885 * Increment counters
3887 pmap_resident_count_inc(pmap, 1);
3889 pa = VM_PAGE_TO_PHYS(m);
3890 l3_val = pa | ATTR_DEFAULT | ATTR_IDX(m->md.pv_memattr) |
3891 ATTR_AP(ATTR_AP_RO) | L3_PAGE;
3892 if ((prot & VM_PROT_EXECUTE) == 0 ||
3893 m->md.pv_memattr == VM_MEMATTR_DEVICE)
3895 if (va < VM_MAXUSER_ADDRESS)
3896 l3_val |= ATTR_AP(ATTR_AP_USER) | ATTR_PXN;
3899 if (pmap != kernel_pmap)
3903 * Now validate mapping with RO protection
3905 if ((m->oflags & VPO_UNMANAGED) == 0) {
3906 l3_val |= ATTR_SW_MANAGED;
3910 /* Sync icache before the mapping is stored to PTE */
3911 if ((prot & VM_PROT_EXECUTE) && pmap != kernel_pmap &&
3912 m->md.pv_memattr == VM_MEMATTR_WRITE_BACK)
3913 cpu_icache_sync_range(PHYS_TO_DMAP(pa), PAGE_SIZE);
3915 pmap_store(l3, l3_val);
3922 * This code maps large physical mmap regions into the
3923 * processor address space. Note that some shortcuts
3924 * are taken, but the code works.
3927 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
3928 vm_pindex_t pindex, vm_size_t size)
3931 VM_OBJECT_ASSERT_WLOCKED(object);
3932 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
3933 ("pmap_object_init_pt: non-device object"));
3937 * Clear the wired attribute from the mappings for the specified range of
3938 * addresses in the given pmap. Every valid mapping within that range
3939 * must have the wired attribute set. In contrast, invalid mappings
3940 * cannot have the wired attribute set, so they are ignored.
3942 * The wired attribute of the page table entry is not a hardware feature,
3943 * so there is no need to invalidate any TLB entries.
3946 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
3948 vm_offset_t va_next;
3949 pd_entry_t *l0, *l1, *l2;
3953 for (; sva < eva; sva = va_next) {
3954 l0 = pmap_l0(pmap, sva);
3955 if (pmap_load(l0) == 0) {
3956 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
3962 l1 = pmap_l0_to_l1(l0, sva);
3963 if (pmap_load(l1) == 0) {
3964 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
3970 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
3974 l2 = pmap_l1_to_l2(l1, sva);
3975 if (pmap_load(l2) == 0)
3978 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK) {
3979 if ((pmap_load(l2) & ATTR_SW_WIRED) == 0)
3980 panic("pmap_unwire: l2 %#jx is missing "
3981 "ATTR_SW_WIRED", (uintmax_t)pmap_load(l2));
3984 * Are we unwiring the entire large page? If not,
3985 * demote the mapping and fall through.
3987 if (sva + L2_SIZE == va_next && eva >= va_next) {
3988 pmap_clear_bits(l2, ATTR_SW_WIRED);
3989 pmap->pm_stats.wired_count -= L2_SIZE /
3992 } else if (pmap_demote_l2(pmap, l2, sva) == NULL)
3993 panic("pmap_unwire: demotion failed");
3995 KASSERT((pmap_load(l2) & ATTR_DESCR_MASK) == L2_TABLE,
3996 ("pmap_unwire: Invalid l2 entry after demotion"));
4000 for (l3 = pmap_l2_to_l3(l2, sva); sva != va_next; l3++,
4002 if (pmap_load(l3) == 0)
4004 if ((pmap_load(l3) & ATTR_SW_WIRED) == 0)
4005 panic("pmap_unwire: l3 %#jx is missing "
4006 "ATTR_SW_WIRED", (uintmax_t)pmap_load(l3));
4009 * ATTR_SW_WIRED must be cleared atomically. Although
4010 * the pmap lock synchronizes access to ATTR_SW_WIRED,
4011 * the System MMU may write to the entry concurrently.
4013 pmap_clear_bits(l3, ATTR_SW_WIRED);
4014 pmap->pm_stats.wired_count--;
4021 * Copy the range specified by src_addr/len
4022 * from the source map to the range dst_addr/len
4023 * in the destination map.
4025 * This routine is only advisory and need not do anything.
4027 * Because the executable mappings created by this routine are copied,
4028 * it should not have to flush the instruction cache.
4031 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
4032 vm_offset_t src_addr)
4034 struct rwlock *lock;
4035 pd_entry_t *l0, *l1, *l2, srcptepaddr;
4036 pt_entry_t *dst_pte, mask, nbits, ptetemp, *src_pte;
4037 vm_offset_t addr, end_addr, va_next;
4038 vm_page_t dst_l2pg, dstmpte, srcmpte;
4040 if (dst_addr != src_addr)
4042 end_addr = src_addr + len;
4044 if (dst_pmap < src_pmap) {
4045 PMAP_LOCK(dst_pmap);
4046 PMAP_LOCK(src_pmap);
4048 PMAP_LOCK(src_pmap);
4049 PMAP_LOCK(dst_pmap);
4051 for (addr = src_addr; addr < end_addr; addr = va_next) {
4052 l0 = pmap_l0(src_pmap, addr);
4053 if (pmap_load(l0) == 0) {
4054 va_next = (addr + L0_SIZE) & ~L0_OFFSET;
4059 l1 = pmap_l0_to_l1(l0, addr);
4060 if (pmap_load(l1) == 0) {
4061 va_next = (addr + L1_SIZE) & ~L1_OFFSET;
4066 va_next = (addr + L2_SIZE) & ~L2_OFFSET;
4069 l2 = pmap_l1_to_l2(l1, addr);
4070 srcptepaddr = pmap_load(l2);
4071 if (srcptepaddr == 0)
4073 if ((srcptepaddr & ATTR_DESCR_MASK) == L2_BLOCK) {
4074 if ((addr & L2_OFFSET) != 0 ||
4075 addr + L2_SIZE > end_addr)
4077 l2 = pmap_alloc_l2(dst_pmap, addr, &dst_l2pg, NULL);
4080 if (pmap_load(l2) == 0 &&
4081 ((srcptepaddr & ATTR_SW_MANAGED) == 0 ||
4082 pmap_pv_insert_l2(dst_pmap, addr, srcptepaddr,
4083 PMAP_ENTER_NORECLAIM, &lock))) {
4084 mask = ATTR_AF | ATTR_SW_WIRED;
4086 if ((srcptepaddr & ATTR_SW_DBM) != 0)
4087 nbits |= ATTR_AP_RW_BIT;
4088 pmap_store(l2, (srcptepaddr & ~mask) | nbits);
4089 pmap_resident_count_inc(dst_pmap, L2_SIZE /
4091 atomic_add_long(&pmap_l2_mappings, 1);
4093 pmap_abort_ptp(dst_pmap, addr, dst_l2pg);
4096 KASSERT((srcptepaddr & ATTR_DESCR_MASK) == L2_TABLE,
4097 ("pmap_copy: invalid L2 entry"));
4098 srcptepaddr &= ~ATTR_MASK;
4099 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr);
4100 KASSERT(srcmpte->ref_count > 0,
4101 ("pmap_copy: source page table page is unused"));
4102 if (va_next > end_addr)
4104 src_pte = (pt_entry_t *)PHYS_TO_DMAP(srcptepaddr);
4105 src_pte = &src_pte[pmap_l3_index(addr)];
4107 for (; addr < va_next; addr += PAGE_SIZE, src_pte++) {
4108 ptetemp = pmap_load(src_pte);
4111 * We only virtual copy managed pages.
4113 if ((ptetemp & ATTR_SW_MANAGED) == 0)
4116 if (dstmpte != NULL) {
4117 KASSERT(dstmpte->pindex == pmap_l2_pindex(addr),
4118 ("dstmpte pindex/addr mismatch"));
4119 dstmpte->ref_count++;
4120 } else if ((dstmpte = pmap_alloc_l3(dst_pmap, addr,
4123 dst_pte = (pt_entry_t *)
4124 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dstmpte));
4125 dst_pte = &dst_pte[pmap_l3_index(addr)];
4126 if (pmap_load(dst_pte) == 0 &&
4127 pmap_try_insert_pv_entry(dst_pmap, addr,
4128 PHYS_TO_VM_PAGE(ptetemp & ~ATTR_MASK), &lock)) {
4130 * Clear the wired, modified, and accessed
4131 * (referenced) bits during the copy.
4133 mask = ATTR_AF | ATTR_SW_WIRED;
4135 if ((ptetemp & ATTR_SW_DBM) != 0)
4136 nbits |= ATTR_AP_RW_BIT;
4137 pmap_store(dst_pte, (ptetemp & ~mask) | nbits);
4138 pmap_resident_count_inc(dst_pmap, 1);
4140 pmap_abort_ptp(dst_pmap, addr, dstmpte);
4143 /* Have we copied all of the valid mappings? */
4144 if (dstmpte->ref_count >= srcmpte->ref_count)
4150 * XXX This barrier may not be needed because the destination pmap is
4157 PMAP_UNLOCK(src_pmap);
4158 PMAP_UNLOCK(dst_pmap);
4162 * pmap_zero_page zeros the specified hardware page by mapping
4163 * the page into KVM and using bzero to clear its contents.
4166 pmap_zero_page(vm_page_t m)
4168 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
4170 pagezero((void *)va);
4174 * pmap_zero_page_area zeros the specified hardware page by mapping
4175 * the page into KVM and using bzero to clear its contents.
4177 * off and size may not cover an area beyond a single hardware page.
4180 pmap_zero_page_area(vm_page_t m, int off, int size)
4182 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
4184 if (off == 0 && size == PAGE_SIZE)
4185 pagezero((void *)va);
4187 bzero((char *)va + off, size);
4191 * pmap_copy_page copies the specified (machine independent)
4192 * page by mapping the page into virtual memory and using
4193 * bcopy to copy the page, one machine dependent page at a
4197 pmap_copy_page(vm_page_t msrc, vm_page_t mdst)
4199 vm_offset_t src = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(msrc));
4200 vm_offset_t dst = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mdst));
4202 pagecopy((void *)src, (void *)dst);
4205 int unmapped_buf_allowed = 1;
4208 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
4209 vm_offset_t b_offset, int xfersize)
4213 vm_paddr_t p_a, p_b;
4214 vm_offset_t a_pg_offset, b_pg_offset;
4217 while (xfersize > 0) {
4218 a_pg_offset = a_offset & PAGE_MASK;
4219 m_a = ma[a_offset >> PAGE_SHIFT];
4220 p_a = m_a->phys_addr;
4221 b_pg_offset = b_offset & PAGE_MASK;
4222 m_b = mb[b_offset >> PAGE_SHIFT];
4223 p_b = m_b->phys_addr;
4224 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
4225 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
4226 if (__predict_false(!PHYS_IN_DMAP(p_a))) {
4227 panic("!DMAP a %lx", p_a);
4229 a_cp = (char *)PHYS_TO_DMAP(p_a) + a_pg_offset;
4231 if (__predict_false(!PHYS_IN_DMAP(p_b))) {
4232 panic("!DMAP b %lx", p_b);
4234 b_cp = (char *)PHYS_TO_DMAP(p_b) + b_pg_offset;
4236 bcopy(a_cp, b_cp, cnt);
4244 pmap_quick_enter_page(vm_page_t m)
4247 return (PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)));
4251 pmap_quick_remove_page(vm_offset_t addr)
4256 * Returns true if the pmap's pv is one of the first
4257 * 16 pvs linked to from this page. This count may
4258 * be changed upwards or downwards in the future; it
4259 * is only necessary that true be returned for a small
4260 * subset of pmaps for proper page aging.
4263 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
4265 struct md_page *pvh;
4266 struct rwlock *lock;
4271 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4272 ("pmap_page_exists_quick: page %p is not managed", m));
4274 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
4276 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4277 if (PV_PMAP(pv) == pmap) {
4285 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
4286 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4287 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4288 if (PV_PMAP(pv) == pmap) {
4302 * pmap_page_wired_mappings:
4304 * Return the number of managed mappings to the given physical page
4308 pmap_page_wired_mappings(vm_page_t m)
4310 struct rwlock *lock;
4311 struct md_page *pvh;
4315 int count, lvl, md_gen, pvh_gen;
4317 if ((m->oflags & VPO_UNMANAGED) != 0)
4319 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
4323 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4325 if (!PMAP_TRYLOCK(pmap)) {
4326 md_gen = m->md.pv_gen;
4330 if (md_gen != m->md.pv_gen) {
4335 pte = pmap_pte(pmap, pv->pv_va, &lvl);
4336 if (pte != NULL && (pmap_load(pte) & ATTR_SW_WIRED) != 0)
4340 if ((m->flags & PG_FICTITIOUS) == 0) {
4341 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4342 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4344 if (!PMAP_TRYLOCK(pmap)) {
4345 md_gen = m->md.pv_gen;
4346 pvh_gen = pvh->pv_gen;
4350 if (md_gen != m->md.pv_gen ||
4351 pvh_gen != pvh->pv_gen) {
4356 pte = pmap_pte(pmap, pv->pv_va, &lvl);
4358 (pmap_load(pte) & ATTR_SW_WIRED) != 0)
4368 * Returns true if the given page is mapped individually or as part of
4369 * a 2mpage. Otherwise, returns false.
4372 pmap_page_is_mapped(vm_page_t m)
4374 struct rwlock *lock;
4377 if ((m->oflags & VPO_UNMANAGED) != 0)
4379 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
4381 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
4382 ((m->flags & PG_FICTITIOUS) == 0 &&
4383 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
4389 * Destroy all managed, non-wired mappings in the given user-space
4390 * pmap. This pmap cannot be active on any processor besides the
4393 * This function cannot be applied to the kernel pmap. Moreover, it
4394 * is not intended for general use. It is only to be used during
4395 * process termination. Consequently, it can be implemented in ways
4396 * that make it faster than pmap_remove(). First, it can more quickly
4397 * destroy mappings by iterating over the pmap's collection of PV
4398 * entries, rather than searching the page table. Second, it doesn't
4399 * have to test and clear the page table entries atomically, because
4400 * no processor is currently accessing the user address space. In
4401 * particular, a page table entry's dirty bit won't change state once
4402 * this function starts.
4405 pmap_remove_pages(pmap_t pmap)
4408 pt_entry_t *pte, tpte;
4409 struct spglist free;
4410 vm_page_t m, ml3, mt;
4412 struct md_page *pvh;
4413 struct pv_chunk *pc, *npc;
4414 struct rwlock *lock;
4416 uint64_t inuse, bitmask;
4417 int allfree, field, freed, idx, lvl;
4420 KASSERT(pmap == PCPU_GET(curpmap), ("non-current pmap %p", pmap));
4426 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
4429 for (field = 0; field < _NPCM; field++) {
4430 inuse = ~pc->pc_map[field] & pc_freemask[field];
4431 while (inuse != 0) {
4432 bit = ffsl(inuse) - 1;
4433 bitmask = 1UL << bit;
4434 idx = field * 64 + bit;
4435 pv = &pc->pc_pventry[idx];
4438 pde = pmap_pde(pmap, pv->pv_va, &lvl);
4439 KASSERT(pde != NULL,
4440 ("Attempting to remove an unmapped page"));
4444 pte = pmap_l1_to_l2(pde, pv->pv_va);
4445 tpte = pmap_load(pte);
4446 KASSERT((tpte & ATTR_DESCR_MASK) ==
4448 ("Attempting to remove an invalid "
4449 "block: %lx", tpte));
4452 pte = pmap_l2_to_l3(pde, pv->pv_va);
4453 tpte = pmap_load(pte);
4454 KASSERT((tpte & ATTR_DESCR_MASK) ==
4456 ("Attempting to remove an invalid "
4457 "page: %lx", tpte));
4461 "Invalid page directory level: %d",
4466 * We cannot remove wired pages from a process' mapping at this time
4468 if (tpte & ATTR_SW_WIRED) {
4473 pa = tpte & ~ATTR_MASK;
4475 m = PHYS_TO_VM_PAGE(pa);
4476 KASSERT(m->phys_addr == pa,
4477 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
4478 m, (uintmax_t)m->phys_addr,
4481 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
4482 m < &vm_page_array[vm_page_array_size],
4483 ("pmap_remove_pages: bad pte %#jx",
4487 * Because this pmap is not active on other
4488 * processors, the dirty bit cannot have
4489 * changed state since we last loaded pte.
4494 * Update the vm_page_t clean/reference bits.
4496 if (pmap_pte_dirty(tpte)) {
4499 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
4508 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(&lock, m);
4511 pc->pc_map[field] |= bitmask;
4514 pmap_resident_count_dec(pmap,
4515 L2_SIZE / PAGE_SIZE);
4516 pvh = pa_to_pvh(tpte & ~ATTR_MASK);
4517 TAILQ_REMOVE(&pvh->pv_list, pv,pv_next);
4519 if (TAILQ_EMPTY(&pvh->pv_list)) {
4520 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
4521 if ((mt->a.flags & PGA_WRITEABLE) != 0 &&
4522 TAILQ_EMPTY(&mt->md.pv_list))
4523 vm_page_aflag_clear(mt, PGA_WRITEABLE);
4525 ml3 = pmap_remove_pt_page(pmap,
4528 KASSERT(ml3->valid == VM_PAGE_BITS_ALL,
4529 ("pmap_remove_pages: l3 page not promoted"));
4530 pmap_resident_count_dec(pmap,1);
4531 KASSERT(ml3->ref_count == NL3PG,
4532 ("pmap_remove_pages: l3 page ref count error"));
4534 pmap_add_delayed_free_list(ml3,
4539 pmap_resident_count_dec(pmap, 1);
4540 TAILQ_REMOVE(&m->md.pv_list, pv,
4543 if ((m->a.flags & PGA_WRITEABLE) != 0 &&
4544 TAILQ_EMPTY(&m->md.pv_list) &&
4545 (m->flags & PG_FICTITIOUS) == 0) {
4547 VM_PAGE_TO_PHYS(m));
4548 if (TAILQ_EMPTY(&pvh->pv_list))
4549 vm_page_aflag_clear(m,
4554 pmap_unuse_pt(pmap, pv->pv_va, pmap_load(pde),
4559 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
4560 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
4561 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
4563 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4569 pmap_invalidate_all(pmap);
4571 vm_page_free_pages_toq(&free, true);
4575 * This is used to check if a page has been accessed or modified.
4578 pmap_page_test_mappings(vm_page_t m, boolean_t accessed, boolean_t modified)
4580 struct rwlock *lock;
4582 struct md_page *pvh;
4583 pt_entry_t *pte, mask, value;
4585 int lvl, md_gen, pvh_gen;
4589 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
4592 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4594 if (!PMAP_TRYLOCK(pmap)) {
4595 md_gen = m->md.pv_gen;
4599 if (md_gen != m->md.pv_gen) {
4604 pte = pmap_pte(pmap, pv->pv_va, &lvl);
4606 ("pmap_page_test_mappings: Invalid level %d", lvl));
4610 mask |= ATTR_AP_RW_BIT;
4611 value |= ATTR_AP(ATTR_AP_RW);
4614 mask |= ATTR_AF | ATTR_DESCR_MASK;
4615 value |= ATTR_AF | L3_PAGE;
4617 rv = (pmap_load(pte) & mask) == value;
4622 if ((m->flags & PG_FICTITIOUS) == 0) {
4623 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4624 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4626 if (!PMAP_TRYLOCK(pmap)) {
4627 md_gen = m->md.pv_gen;
4628 pvh_gen = pvh->pv_gen;
4632 if (md_gen != m->md.pv_gen ||
4633 pvh_gen != pvh->pv_gen) {
4638 pte = pmap_pte(pmap, pv->pv_va, &lvl);
4640 ("pmap_page_test_mappings: Invalid level %d", lvl));
4644 mask |= ATTR_AP_RW_BIT;
4645 value |= ATTR_AP(ATTR_AP_RW);
4648 mask |= ATTR_AF | ATTR_DESCR_MASK;
4649 value |= ATTR_AF | L2_BLOCK;
4651 rv = (pmap_load(pte) & mask) == value;
4665 * Return whether or not the specified physical page was modified
4666 * in any physical maps.
4669 pmap_is_modified(vm_page_t m)
4672 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4673 ("pmap_is_modified: page %p is not managed", m));
4676 * If the page is not busied then this check is racy.
4678 if (!pmap_page_is_write_mapped(m))
4680 return (pmap_page_test_mappings(m, FALSE, TRUE));
4684 * pmap_is_prefaultable:
4686 * Return whether or not the specified virtual address is eligible
4690 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
4698 pte = pmap_pte(pmap, addr, &lvl);
4699 if (pte != NULL && pmap_load(pte) != 0) {
4707 * pmap_is_referenced:
4709 * Return whether or not the specified physical page was referenced
4710 * in any physical maps.
4713 pmap_is_referenced(vm_page_t m)
4716 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4717 ("pmap_is_referenced: page %p is not managed", m));
4718 return (pmap_page_test_mappings(m, TRUE, FALSE));
4722 * Clear the write and modified bits in each of the given page's mappings.
4725 pmap_remove_write(vm_page_t m)
4727 struct md_page *pvh;
4729 struct rwlock *lock;
4730 pv_entry_t next_pv, pv;
4731 pt_entry_t oldpte, *pte;
4733 int lvl, md_gen, pvh_gen;
4735 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4736 ("pmap_remove_write: page %p is not managed", m));
4737 vm_page_assert_busied(m);
4739 if (!pmap_page_is_write_mapped(m))
4741 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
4742 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
4743 pa_to_pvh(VM_PAGE_TO_PHYS(m));
4746 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
4748 if (!PMAP_TRYLOCK(pmap)) {
4749 pvh_gen = pvh->pv_gen;
4753 if (pvh_gen != pvh->pv_gen) {
4760 pte = pmap_pte(pmap, pv->pv_va, &lvl);
4761 if ((pmap_load(pte) & ATTR_SW_DBM) != 0)
4762 (void)pmap_demote_l2_locked(pmap, pte, va, &lock);
4763 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
4764 ("inconsistent pv lock %p %p for page %p",
4765 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
4768 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4770 if (!PMAP_TRYLOCK(pmap)) {
4771 pvh_gen = pvh->pv_gen;
4772 md_gen = m->md.pv_gen;
4776 if (pvh_gen != pvh->pv_gen ||
4777 md_gen != m->md.pv_gen) {
4783 pte = pmap_pte(pmap, pv->pv_va, &lvl);
4784 oldpte = pmap_load(pte);
4786 if ((oldpte & ATTR_SW_DBM) != 0) {
4787 if (!atomic_fcmpset_long(pte, &oldpte,
4788 (oldpte | ATTR_AP_RW_BIT) & ~ATTR_SW_DBM))
4790 if ((oldpte & ATTR_AP_RW_BIT) ==
4791 ATTR_AP(ATTR_AP_RW))
4793 pmap_invalidate_page(pmap, pv->pv_va);
4798 vm_page_aflag_clear(m, PGA_WRITEABLE);
4802 * pmap_ts_referenced:
4804 * Return a count of reference bits for a page, clearing those bits.
4805 * It is not necessary for every reference bit to be cleared, but it
4806 * is necessary that 0 only be returned when there are truly no
4807 * reference bits set.
4809 * As an optimization, update the page's dirty field if a modified bit is
4810 * found while counting reference bits. This opportunistic update can be
4811 * performed at low cost and can eliminate the need for some future calls
4812 * to pmap_is_modified(). However, since this function stops after
4813 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
4814 * dirty pages. Those dirty pages will only be detected by a future call
4815 * to pmap_is_modified().
4818 pmap_ts_referenced(vm_page_t m)
4820 struct md_page *pvh;
4823 struct rwlock *lock;
4824 pd_entry_t *pde, tpde;
4825 pt_entry_t *pte, tpte;
4828 int cleared, lvl, md_gen, not_cleared, pvh_gen;
4829 struct spglist free;
4831 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4832 ("pmap_ts_referenced: page %p is not managed", m));
4835 pa = VM_PAGE_TO_PHYS(m);
4836 lock = PHYS_TO_PV_LIST_LOCK(pa);
4837 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : pa_to_pvh(pa);
4841 if ((pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
4842 goto small_mappings;
4848 if (!PMAP_TRYLOCK(pmap)) {
4849 pvh_gen = pvh->pv_gen;
4853 if (pvh_gen != pvh->pv_gen) {
4859 pde = pmap_pde(pmap, pv->pv_va, &lvl);
4860 KASSERT(pde != NULL, ("pmap_ts_referenced: no l1 table found"));
4862 ("pmap_ts_referenced: invalid pde level %d", lvl));
4863 tpde = pmap_load(pde);
4864 KASSERT((tpde & ATTR_DESCR_MASK) == L1_TABLE,
4865 ("pmap_ts_referenced: found an invalid l1 table"));
4866 pte = pmap_l1_to_l2(pde, pv->pv_va);
4867 tpte = pmap_load(pte);
4868 if (pmap_pte_dirty(tpte)) {
4870 * Although "tpte" is mapping a 2MB page, because
4871 * this function is called at a 4KB page granularity,
4872 * we only update the 4KB page under test.
4877 if ((tpte & ATTR_AF) != 0) {
4879 * Since this reference bit is shared by 512 4KB pages,
4880 * it should not be cleared every time it is tested.
4881 * Apply a simple "hash" function on the physical page
4882 * number, the virtual superpage number, and the pmap
4883 * address to select one 4KB page out of the 512 on
4884 * which testing the reference bit will result in
4885 * clearing that reference bit. This function is
4886 * designed to avoid the selection of the same 4KB page
4887 * for every 2MB page mapping.
4889 * On demotion, a mapping that hasn't been referenced
4890 * is simply destroyed. To avoid the possibility of a
4891 * subsequent page fault on a demoted wired mapping,
4892 * always leave its reference bit set. Moreover,
4893 * since the superpage is wired, the current state of
4894 * its reference bit won't affect page replacement.
4896 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> L2_SHIFT) ^
4897 (uintptr_t)pmap) & (Ln_ENTRIES - 1)) == 0 &&
4898 (tpte & ATTR_SW_WIRED) == 0) {
4899 pmap_clear_bits(pte, ATTR_AF);
4900 pmap_invalidate_page(pmap, pv->pv_va);
4906 /* Rotate the PV list if it has more than one entry. */
4907 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
4908 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
4909 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
4912 if (cleared + not_cleared >= PMAP_TS_REFERENCED_MAX)
4914 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
4916 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
4923 if (!PMAP_TRYLOCK(pmap)) {
4924 pvh_gen = pvh->pv_gen;
4925 md_gen = m->md.pv_gen;
4929 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
4934 pde = pmap_pde(pmap, pv->pv_va, &lvl);
4935 KASSERT(pde != NULL, ("pmap_ts_referenced: no l2 table found"));
4937 ("pmap_ts_referenced: invalid pde level %d", lvl));
4938 tpde = pmap_load(pde);
4939 KASSERT((tpde & ATTR_DESCR_MASK) == L2_TABLE,
4940 ("pmap_ts_referenced: found an invalid l2 table"));
4941 pte = pmap_l2_to_l3(pde, pv->pv_va);
4942 tpte = pmap_load(pte);
4943 if (pmap_pte_dirty(tpte))
4945 if ((tpte & ATTR_AF) != 0) {
4946 if ((tpte & ATTR_SW_WIRED) == 0) {
4947 pmap_clear_bits(pte, ATTR_AF);
4948 pmap_invalidate_page(pmap, pv->pv_va);
4954 /* Rotate the PV list if it has more than one entry. */
4955 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
4956 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4957 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4960 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && cleared +
4961 not_cleared < PMAP_TS_REFERENCED_MAX);
4964 vm_page_free_pages_toq(&free, true);
4965 return (cleared + not_cleared);
4969 * Apply the given advice to the specified range of addresses within the
4970 * given pmap. Depending on the advice, clear the referenced and/or
4971 * modified flags in each mapping and set the mapped page's dirty field.
4974 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
4976 struct rwlock *lock;
4977 vm_offset_t va, va_next;
4979 pd_entry_t *l0, *l1, *l2, oldl2;
4980 pt_entry_t *l3, oldl3;
4982 if (advice != MADV_DONTNEED && advice != MADV_FREE)
4986 for (; sva < eva; sva = va_next) {
4987 l0 = pmap_l0(pmap, sva);
4988 if (pmap_load(l0) == 0) {
4989 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
4994 l1 = pmap_l0_to_l1(l0, sva);
4995 if (pmap_load(l1) == 0) {
4996 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
5001 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
5004 l2 = pmap_l1_to_l2(l1, sva);
5005 oldl2 = pmap_load(l2);
5008 if ((oldl2 & ATTR_DESCR_MASK) == L2_BLOCK) {
5009 if ((oldl2 & ATTR_SW_MANAGED) == 0)
5012 if (!pmap_demote_l2_locked(pmap, l2, sva, &lock)) {
5017 * The 2MB page mapping was destroyed.
5023 * Unless the page mappings are wired, remove the
5024 * mapping to a single page so that a subsequent
5025 * access may repromote. Choosing the last page
5026 * within the address range [sva, min(va_next, eva))
5027 * generally results in more repromotions. Since the
5028 * underlying page table page is fully populated, this
5029 * removal never frees a page table page.
5031 if ((oldl2 & ATTR_SW_WIRED) == 0) {
5037 ("pmap_advise: no address gap"));
5038 l3 = pmap_l2_to_l3(l2, va);
5039 KASSERT(pmap_load(l3) != 0,
5040 ("pmap_advise: invalid PTE"));
5041 pmap_remove_l3(pmap, l3, va, pmap_load(l2),
5047 KASSERT((pmap_load(l2) & ATTR_DESCR_MASK) == L2_TABLE,
5048 ("pmap_advise: invalid L2 entry after demotion"));
5052 for (l3 = pmap_l2_to_l3(l2, sva); sva != va_next; l3++,
5054 oldl3 = pmap_load(l3);
5055 if ((oldl3 & (ATTR_SW_MANAGED | ATTR_DESCR_MASK)) !=
5056 (ATTR_SW_MANAGED | L3_PAGE))
5058 else if (pmap_pte_dirty(oldl3)) {
5059 if (advice == MADV_DONTNEED) {
5061 * Future calls to pmap_is_modified()
5062 * can be avoided by making the page
5065 m = PHYS_TO_VM_PAGE(oldl3 & ~ATTR_MASK);
5068 while (!atomic_fcmpset_long(l3, &oldl3,
5069 (oldl3 & ~ATTR_AF) | ATTR_AP(ATTR_AP_RO)))
5071 } else if ((oldl3 & ATTR_AF) != 0)
5072 pmap_clear_bits(l3, ATTR_AF);
5079 if (va != va_next) {
5080 pmap_invalidate_range(pmap, va, sva);
5085 pmap_invalidate_range(pmap, va, sva);
5091 * Clear the modify bits on the specified physical page.
5094 pmap_clear_modify(vm_page_t m)
5096 struct md_page *pvh;
5097 struct rwlock *lock;
5099 pv_entry_t next_pv, pv;
5100 pd_entry_t *l2, oldl2;
5101 pt_entry_t *l3, oldl3;
5103 int md_gen, pvh_gen;
5105 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5106 ("pmap_clear_modify: page %p is not managed", m));
5107 vm_page_assert_busied(m);
5109 if (!pmap_page_is_write_mapped(m))
5111 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
5112 pa_to_pvh(VM_PAGE_TO_PHYS(m));
5113 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5116 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
5118 if (!PMAP_TRYLOCK(pmap)) {
5119 pvh_gen = pvh->pv_gen;
5123 if (pvh_gen != pvh->pv_gen) {
5129 l2 = pmap_l2(pmap, va);
5130 oldl2 = pmap_load(l2);
5131 /* If oldl2 has ATTR_SW_DBM set, then it is also dirty. */
5132 if ((oldl2 & ATTR_SW_DBM) != 0 &&
5133 pmap_demote_l2_locked(pmap, l2, va, &lock) &&
5134 (oldl2 & ATTR_SW_WIRED) == 0) {
5136 * Write protect the mapping to a single page so that
5137 * a subsequent write access may repromote.
5139 va += VM_PAGE_TO_PHYS(m) - (oldl2 & ~ATTR_MASK);
5140 l3 = pmap_l2_to_l3(l2, va);
5141 oldl3 = pmap_load(l3);
5142 while (!atomic_fcmpset_long(l3, &oldl3,
5143 (oldl3 & ~ATTR_SW_DBM) | ATTR_AP(ATTR_AP_RO)))
5146 pmap_invalidate_page(pmap, va);
5150 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5152 if (!PMAP_TRYLOCK(pmap)) {
5153 md_gen = m->md.pv_gen;
5154 pvh_gen = pvh->pv_gen;
5158 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
5163 l2 = pmap_l2(pmap, pv->pv_va);
5164 l3 = pmap_l2_to_l3(l2, pv->pv_va);
5165 oldl3 = pmap_load(l3);
5166 if (pmap_l3_valid(oldl3) &&
5167 (oldl3 & (ATTR_AP_RW_BIT | ATTR_SW_DBM)) == ATTR_SW_DBM) {
5168 pmap_set_bits(l3, ATTR_AP(ATTR_AP_RO));
5169 pmap_invalidate_page(pmap, pv->pv_va);
5177 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
5179 struct pmap_preinit_mapping *ppim;
5180 vm_offset_t va, offset;
5183 int i, lvl, l2_blocks, free_l2_count, start_idx;
5185 if (!vm_initialized) {
5187 * No L3 ptables so map entire L2 blocks where start VA is:
5188 * preinit_map_va + start_idx * L2_SIZE
5189 * There may be duplicate mappings (multiple VA -> same PA) but
5190 * ARM64 dcache is always PIPT so that's acceptable.
5195 /* Calculate how many L2 blocks are needed for the mapping */
5196 l2_blocks = (roundup2(pa + size, L2_SIZE) -
5197 rounddown2(pa, L2_SIZE)) >> L2_SHIFT;
5199 offset = pa & L2_OFFSET;
5201 if (preinit_map_va == 0)
5204 /* Map 2MiB L2 blocks from reserved VA space */
5208 /* Find enough free contiguous VA space */
5209 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5210 ppim = pmap_preinit_mapping + i;
5211 if (free_l2_count > 0 && ppim->pa != 0) {
5212 /* Not enough space here */
5218 if (ppim->pa == 0) {
5220 if (start_idx == -1)
5223 if (free_l2_count == l2_blocks)
5227 if (free_l2_count != l2_blocks)
5228 panic("%s: too many preinit mappings", __func__);
5230 va = preinit_map_va + (start_idx * L2_SIZE);
5231 for (i = start_idx; i < start_idx + l2_blocks; i++) {
5232 /* Mark entries as allocated */
5233 ppim = pmap_preinit_mapping + i;
5235 ppim->va = va + offset;
5240 pa = rounddown2(pa, L2_SIZE);
5241 for (i = 0; i < l2_blocks; i++) {
5242 pde = pmap_pde(kernel_pmap, va, &lvl);
5243 KASSERT(pde != NULL,
5244 ("pmap_mapbios: Invalid page entry, va: 0x%lx",
5247 ("pmap_mapbios: Invalid level %d", lvl));
5249 /* Insert L2_BLOCK */
5250 l2 = pmap_l1_to_l2(pde, va);
5252 pa | ATTR_DEFAULT | ATTR_XN |
5253 ATTR_IDX(VM_MEMATTR_WRITE_BACK) | L2_BLOCK);
5258 pmap_invalidate_all(kernel_pmap);
5260 va = preinit_map_va + (start_idx * L2_SIZE);
5263 /* kva_alloc may be used to map the pages */
5264 offset = pa & PAGE_MASK;
5265 size = round_page(offset + size);
5267 va = kva_alloc(size);
5269 panic("%s: Couldn't allocate KVA", __func__);
5271 pde = pmap_pde(kernel_pmap, va, &lvl);
5272 KASSERT(lvl == 2, ("pmap_mapbios: Invalid level %d", lvl));
5274 /* L3 table is linked */
5275 va = trunc_page(va);
5276 pa = trunc_page(pa);
5277 pmap_kenter(va, size, pa, VM_MEMATTR_WRITE_BACK);
5280 return ((void *)(va + offset));
5284 pmap_unmapbios(vm_offset_t va, vm_size_t size)
5286 struct pmap_preinit_mapping *ppim;
5287 vm_offset_t offset, tmpsize, va_trunc;
5290 int i, lvl, l2_blocks, block;
5294 (roundup2(va + size, L2_SIZE) - rounddown2(va, L2_SIZE)) >> L2_SHIFT;
5295 KASSERT(l2_blocks > 0, ("pmap_unmapbios: invalid size %lx", size));
5297 /* Remove preinit mapping */
5298 preinit_map = false;
5300 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5301 ppim = pmap_preinit_mapping + i;
5302 if (ppim->va == va) {
5303 KASSERT(ppim->size == size,
5304 ("pmap_unmapbios: size mismatch"));
5309 offset = block * L2_SIZE;
5310 va_trunc = rounddown2(va, L2_SIZE) + offset;
5312 /* Remove L2_BLOCK */
5313 pde = pmap_pde(kernel_pmap, va_trunc, &lvl);
5314 KASSERT(pde != NULL,
5315 ("pmap_unmapbios: Invalid page entry, va: 0x%lx",
5317 l2 = pmap_l1_to_l2(pde, va_trunc);
5320 if (block == (l2_blocks - 1))
5326 pmap_invalidate_all(kernel_pmap);
5330 /* Unmap the pages reserved with kva_alloc. */
5331 if (vm_initialized) {
5332 offset = va & PAGE_MASK;
5333 size = round_page(offset + size);
5334 va = trunc_page(va);
5336 pde = pmap_pde(kernel_pmap, va, &lvl);
5337 KASSERT(pde != NULL,
5338 ("pmap_unmapbios: Invalid page entry, va: 0x%lx", va));
5339 KASSERT(lvl == 2, ("pmap_unmapbios: Invalid level %d", lvl));
5341 /* Unmap and invalidate the pages */
5342 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
5343 pmap_kremove(va + tmpsize);
5350 * Sets the memory attribute for the specified page.
5353 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
5356 m->md.pv_memattr = ma;
5359 * If "m" is a normal page, update its direct mapping. This update
5360 * can be relied upon to perform any cache operations that are
5361 * required for data coherence.
5363 if ((m->flags & PG_FICTITIOUS) == 0 &&
5364 pmap_change_attr(PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)), PAGE_SIZE,
5365 m->md.pv_memattr) != 0)
5366 panic("memory attribute change on the direct map failed");
5370 * Changes the specified virtual address range's memory type to that given by
5371 * the parameter "mode". The specified virtual address range must be
5372 * completely contained within either the direct map or the kernel map. If
5373 * the virtual address range is contained within the kernel map, then the
5374 * memory type for each of the corresponding ranges of the direct map is also
5375 * changed. (The corresponding ranges of the direct map are those ranges that
5376 * map the same physical pages as the specified virtual address range.) These
5377 * changes to the direct map are necessary because Intel describes the
5378 * behavior of their processors as "undefined" if two or more mappings to the
5379 * same physical page have different memory types.
5381 * Returns zero if the change completed successfully, and either EINVAL or
5382 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
5383 * of the virtual address range was not mapped, and ENOMEM is returned if
5384 * there was insufficient memory available to complete the change. In the
5385 * latter case, the memory type may have been changed on some part of the
5386 * virtual address range or the direct map.
5389 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
5393 PMAP_LOCK(kernel_pmap);
5394 error = pmap_change_attr_locked(va, size, mode);
5395 PMAP_UNLOCK(kernel_pmap);
5400 pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode)
5402 vm_offset_t base, offset, tmpva;
5403 pt_entry_t l3, *pte, *newpte;
5406 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
5407 base = trunc_page(va);
5408 offset = va & PAGE_MASK;
5409 size = round_page(offset + size);
5411 if (!VIRT_IN_DMAP(base) &&
5412 !(base >= VM_MIN_KERNEL_ADDRESS && base < VM_MAX_KERNEL_ADDRESS))
5415 for (tmpva = base; tmpva < base + size; ) {
5416 pte = pmap_pte(kernel_pmap, tmpva, &lvl);
5420 if ((pmap_load(pte) & ATTR_IDX_MASK) == ATTR_IDX(mode)) {
5422 * We already have the correct attribute,
5423 * ignore this entry.
5427 panic("Invalid DMAP table level: %d\n", lvl);
5429 tmpva = (tmpva & ~L1_OFFSET) + L1_SIZE;
5432 tmpva = (tmpva & ~L2_OFFSET) + L2_SIZE;
5440 * Split the entry to an level 3 table, then
5441 * set the new attribute.
5445 panic("Invalid DMAP table level: %d\n", lvl);
5447 newpte = pmap_demote_l1(kernel_pmap, pte,
5448 tmpva & ~L1_OFFSET);
5451 pte = pmap_l1_to_l2(pte, tmpva);
5453 newpte = pmap_demote_l2(kernel_pmap, pte,
5457 pte = pmap_l2_to_l3(pte, tmpva);
5459 /* Update the entry */
5460 l3 = pmap_load(pte);
5461 l3 &= ~ATTR_IDX_MASK;
5462 l3 |= ATTR_IDX(mode);
5463 if (mode == VM_MEMATTR_DEVICE)
5466 pmap_update_entry(kernel_pmap, pte, l3, tmpva,
5470 * If moving to a non-cacheable entry flush
5473 if (mode == VM_MEMATTR_UNCACHEABLE)
5474 cpu_dcache_wbinv_range(tmpva, L3_SIZE);
5486 * Create an L2 table to map all addresses within an L1 mapping.
5489 pmap_demote_l1(pmap_t pmap, pt_entry_t *l1, vm_offset_t va)
5491 pt_entry_t *l2, newl2, oldl1;
5493 vm_paddr_t l2phys, phys;
5497 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5498 oldl1 = pmap_load(l1);
5499 KASSERT((oldl1 & ATTR_DESCR_MASK) == L1_BLOCK,
5500 ("pmap_demote_l1: Demoting a non-block entry"));
5501 KASSERT((va & L1_OFFSET) == 0,
5502 ("pmap_demote_l1: Invalid virtual address %#lx", va));
5503 KASSERT((oldl1 & ATTR_SW_MANAGED) == 0,
5504 ("pmap_demote_l1: Level 1 table shouldn't be managed"));
5507 if (va <= (vm_offset_t)l1 && va + L1_SIZE > (vm_offset_t)l1) {
5508 tmpl1 = kva_alloc(PAGE_SIZE);
5513 if ((ml2 = vm_page_alloc(NULL, 0, VM_ALLOC_INTERRUPT |
5514 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
5515 CTR2(KTR_PMAP, "pmap_demote_l1: failure for va %#lx"
5516 " in pmap %p", va, pmap);
5520 l2phys = VM_PAGE_TO_PHYS(ml2);
5521 l2 = (pt_entry_t *)PHYS_TO_DMAP(l2phys);
5523 /* Address the range points at */
5524 phys = oldl1 & ~ATTR_MASK;
5525 /* The attributed from the old l1 table to be copied */
5526 newl2 = oldl1 & ATTR_MASK;
5528 /* Create the new entries */
5529 for (i = 0; i < Ln_ENTRIES; i++) {
5530 l2[i] = newl2 | phys;
5533 KASSERT(l2[0] == ((oldl1 & ~ATTR_DESCR_MASK) | L2_BLOCK),
5534 ("Invalid l2 page (%lx != %lx)", l2[0],
5535 (oldl1 & ~ATTR_DESCR_MASK) | L2_BLOCK));
5538 pmap_kenter(tmpl1, PAGE_SIZE,
5539 DMAP_TO_PHYS((vm_offset_t)l1) & ~L3_OFFSET,
5540 VM_MEMATTR_WRITE_BACK);
5541 l1 = (pt_entry_t *)(tmpl1 + ((vm_offset_t)l1 & PAGE_MASK));
5544 pmap_update_entry(pmap, l1, l2phys | L1_TABLE, va, PAGE_SIZE);
5547 pmap_kremove(tmpl1);
5548 kva_free(tmpl1, PAGE_SIZE);
5555 pmap_fill_l3(pt_entry_t *firstl3, pt_entry_t newl3)
5559 for (l3 = firstl3; l3 - firstl3 < Ln_ENTRIES; l3++) {
5566 pmap_demote_l2_abort(pmap_t pmap, vm_offset_t va, pt_entry_t *l2,
5567 struct rwlock **lockp)
5569 struct spglist free;
5572 (void)pmap_remove_l2(pmap, l2, va, pmap_load(pmap_l1(pmap, va)), &free,
5574 vm_page_free_pages_toq(&free, true);
5578 * Create an L3 table to map all addresses within an L2 mapping.
5581 pmap_demote_l2_locked(pmap_t pmap, pt_entry_t *l2, vm_offset_t va,
5582 struct rwlock **lockp)
5584 pt_entry_t *l3, newl3, oldl2;
5589 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5591 oldl2 = pmap_load(l2);
5592 KASSERT((oldl2 & ATTR_DESCR_MASK) == L2_BLOCK,
5593 ("pmap_demote_l2: Demoting a non-block entry"));
5597 if (va <= (vm_offset_t)l2 && va + L2_SIZE > (vm_offset_t)l2) {
5598 tmpl2 = kva_alloc(PAGE_SIZE);
5604 * Invalidate the 2MB page mapping and return "failure" if the
5605 * mapping was never accessed.
5607 if ((oldl2 & ATTR_AF) == 0) {
5608 KASSERT((oldl2 & ATTR_SW_WIRED) == 0,
5609 ("pmap_demote_l2: a wired mapping is missing ATTR_AF"));
5610 pmap_demote_l2_abort(pmap, va, l2, lockp);
5611 CTR2(KTR_PMAP, "pmap_demote_l2: failure for va %#lx in pmap %p",
5616 if ((ml3 = pmap_remove_pt_page(pmap, va)) == NULL) {
5617 KASSERT((oldl2 & ATTR_SW_WIRED) == 0,
5618 ("pmap_demote_l2: page table page for a wired mapping"
5622 * If the page table page is missing and the mapping
5623 * is for a kernel address, the mapping must belong to
5624 * the direct map. Page table pages are preallocated
5625 * for every other part of the kernel address space,
5626 * so the direct map region is the only part of the
5627 * kernel address space that must be handled here.
5629 KASSERT(va < VM_MAXUSER_ADDRESS || VIRT_IN_DMAP(va),
5630 ("pmap_demote_l2: No saved mpte for va %#lx", va));
5633 * If the 2MB page mapping belongs to the direct map
5634 * region of the kernel's address space, then the page
5635 * allocation request specifies the highest possible
5636 * priority (VM_ALLOC_INTERRUPT). Otherwise, the
5637 * priority is normal.
5639 ml3 = vm_page_alloc(NULL, pmap_l2_pindex(va),
5640 (VIRT_IN_DMAP(va) ? VM_ALLOC_INTERRUPT : VM_ALLOC_NORMAL) |
5641 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED);
5644 * If the allocation of the new page table page fails,
5645 * invalidate the 2MB page mapping and return "failure".
5648 pmap_demote_l2_abort(pmap, va, l2, lockp);
5649 CTR2(KTR_PMAP, "pmap_demote_l2: failure for va %#lx"
5650 " in pmap %p", va, pmap);
5654 if (va < VM_MAXUSER_ADDRESS) {
5655 ml3->ref_count = NL3PG;
5656 pmap_resident_count_inc(pmap, 1);
5659 l3phys = VM_PAGE_TO_PHYS(ml3);
5660 l3 = (pt_entry_t *)PHYS_TO_DMAP(l3phys);
5661 newl3 = (oldl2 & ~ATTR_DESCR_MASK) | L3_PAGE;
5662 KASSERT((oldl2 & (ATTR_AP_RW_BIT | ATTR_SW_DBM)) !=
5663 (ATTR_AP(ATTR_AP_RO) | ATTR_SW_DBM),
5664 ("pmap_demote_l2: L2 entry is writeable but not dirty"));
5667 * If the page table page is not leftover from an earlier promotion,
5668 * or the mapping attributes have changed, (re)initialize the L3 table.
5670 * When pmap_update_entry() clears the old L2 mapping, it (indirectly)
5671 * performs a dsb(). That dsb() ensures that the stores for filling
5672 * "l3" are visible before "l3" is added to the page table.
5674 if (ml3->valid == 0 || (l3[0] & ATTR_MASK) != (newl3 & ATTR_MASK))
5675 pmap_fill_l3(l3, newl3);
5678 * Map the temporary page so we don't lose access to the l2 table.
5681 pmap_kenter(tmpl2, PAGE_SIZE,
5682 DMAP_TO_PHYS((vm_offset_t)l2) & ~L3_OFFSET,
5683 VM_MEMATTR_WRITE_BACK);
5684 l2 = (pt_entry_t *)(tmpl2 + ((vm_offset_t)l2 & PAGE_MASK));
5688 * The spare PV entries must be reserved prior to demoting the
5689 * mapping, that is, prior to changing the PDE. Otherwise, the state
5690 * of the L2 and the PV lists will be inconsistent, which can result
5691 * in reclaim_pv_chunk() attempting to remove a PV entry from the
5692 * wrong PV list and pmap_pv_demote_l2() failing to find the expected
5693 * PV entry for the 2MB page mapping that is being demoted.
5695 if ((oldl2 & ATTR_SW_MANAGED) != 0)
5696 reserve_pv_entries(pmap, Ln_ENTRIES - 1, lockp);
5699 * Pass PAGE_SIZE so that a single TLB invalidation is performed on
5700 * the 2MB page mapping.
5702 pmap_update_entry(pmap, l2, l3phys | L2_TABLE, va, PAGE_SIZE);
5705 * Demote the PV entry.
5707 if ((oldl2 & ATTR_SW_MANAGED) != 0)
5708 pmap_pv_demote_l2(pmap, va, oldl2 & ~ATTR_MASK, lockp);
5710 atomic_add_long(&pmap_l2_demotions, 1);
5711 CTR3(KTR_PMAP, "pmap_demote_l2: success for va %#lx"
5712 " in pmap %p %lx", va, pmap, l3[0]);
5716 pmap_kremove(tmpl2);
5717 kva_free(tmpl2, PAGE_SIZE);
5725 pmap_demote_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t va)
5727 struct rwlock *lock;
5731 l3 = pmap_demote_l2_locked(pmap, l2, va, &lock);
5738 * Perform the pmap work for mincore(2). If the page is not both referenced and
5739 * modified by this pmap, returns its physical address so that the caller can
5740 * find other mappings.
5743 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *pap)
5745 pt_entry_t *pte, tpte;
5746 vm_paddr_t mask, pa;
5751 pte = pmap_pte(pmap, addr, &lvl);
5753 tpte = pmap_load(pte);
5766 panic("pmap_mincore: invalid level %d", lvl);
5769 managed = (tpte & ATTR_SW_MANAGED) != 0;
5770 val = MINCORE_INCORE;
5772 val |= MINCORE_SUPER;
5773 if ((managed && pmap_pte_dirty(tpte)) || (!managed &&
5774 (tpte & ATTR_AP_RW_BIT) == ATTR_AP(ATTR_AP_RW)))
5775 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
5776 if ((tpte & ATTR_AF) == ATTR_AF)
5777 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
5779 pa = (tpte & ~ATTR_MASK) | (addr & mask);
5785 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
5786 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) && managed) {
5794 * Garbage collect every ASID that is neither active on a processor nor
5798 pmap_reset_asid_set(void)
5801 int asid, cpuid, epoch;
5803 mtx_assert(&asid_set_mutex, MA_OWNED);
5806 * Ensure that the store to asid_epoch is globally visible before the
5807 * loads from pc_curpmap are performed.
5809 epoch = asid_epoch + 1;
5810 if (epoch == INT_MAX)
5814 __asm __volatile("tlbi vmalle1is");
5816 bit_nclear(asid_set, ASID_FIRST_AVAILABLE, asid_set_size - 1);
5817 CPU_FOREACH(cpuid) {
5818 if (cpuid == curcpu)
5820 pmap = pcpu_find(cpuid)->pc_curpmap;
5821 asid = COOKIE_TO_ASID(pmap->pm_cookie);
5824 bit_set(asid_set, asid);
5825 pmap->pm_cookie = COOKIE_FROM(asid, epoch);
5830 * Allocate a new ASID for the specified pmap.
5833 pmap_alloc_asid(pmap_t pmap)
5837 mtx_lock_spin(&asid_set_mutex);
5840 * While this processor was waiting to acquire the asid set mutex,
5841 * pmap_reset_asid_set() running on another processor might have
5842 * updated this pmap's cookie to the current epoch. In which case, we
5843 * don't need to allocate a new ASID.
5845 if (COOKIE_TO_EPOCH(pmap->pm_cookie) == asid_epoch)
5848 bit_ffc_at(asid_set, asid_next, asid_set_size, &new_asid);
5849 if (new_asid == -1) {
5850 bit_ffc_at(asid_set, ASID_FIRST_AVAILABLE, asid_next,
5852 if (new_asid == -1) {
5853 pmap_reset_asid_set();
5854 bit_ffc_at(asid_set, ASID_FIRST_AVAILABLE,
5855 asid_set_size, &new_asid);
5856 KASSERT(new_asid != -1, ("ASID allocation failure"));
5859 bit_set(asid_set, new_asid);
5860 asid_next = new_asid + 1;
5861 pmap->pm_cookie = COOKIE_FROM(new_asid, asid_epoch);
5863 mtx_unlock_spin(&asid_set_mutex);
5867 * Compute the value that should be stored in ttbr0 to activate the specified
5868 * pmap. This value may change from time to time.
5871 pmap_to_ttbr0(pmap_t pmap)
5874 return (ASID_TO_OPERAND(COOKIE_TO_ASID(pmap->pm_cookie)) |
5879 pmap_activate_int(pmap_t pmap)
5883 KASSERT(PCPU_GET(curpmap) != NULL, ("no active pmap"));
5884 KASSERT(pmap != kernel_pmap, ("kernel pmap activation"));
5885 if (pmap == PCPU_GET(curpmap)) {
5887 * Handle the possibility that the old thread was preempted
5888 * after an "ic" or "tlbi" instruction but before it performed
5889 * a "dsb" instruction. If the old thread migrates to a new
5890 * processor, its completion of a "dsb" instruction on that
5891 * new processor does not guarantee that the "ic" or "tlbi"
5892 * instructions performed on the old processor have completed.
5899 * Ensure that the store to curpmap is globally visible before the
5900 * load from asid_epoch is performed.
5902 PCPU_SET(curpmap, pmap);
5904 epoch = COOKIE_TO_EPOCH(pmap->pm_cookie);
5905 if (epoch >= 0 && epoch != asid_epoch)
5906 pmap_alloc_asid(pmap);
5908 set_ttbr0(pmap_to_ttbr0(pmap));
5909 if (PCPU_GET(bcast_tlbi_workaround) != 0)
5910 invalidate_local_icache();
5915 pmap_activate(struct thread *td)
5919 pmap = vmspace_pmap(td->td_proc->p_vmspace);
5921 (void)pmap_activate_int(pmap);
5926 * To eliminate the unused parameter "old", we would have to add an instruction
5930 pmap_switch(struct thread *old __unused, struct thread *new)
5932 pcpu_bp_harden bp_harden;
5935 /* Store the new curthread */
5936 PCPU_SET(curthread, new);
5938 /* And the new pcb */
5940 PCPU_SET(curpcb, pcb);
5943 * TODO: We may need to flush the cache here if switching
5944 * to a user process.
5947 if (pmap_activate_int(vmspace_pmap(new->td_proc->p_vmspace))) {
5949 * Stop userspace from training the branch predictor against
5950 * other processes. This will call into a CPU specific
5951 * function that clears the branch predictor state.
5953 bp_harden = PCPU_GET(bp_harden);
5954 if (bp_harden != NULL)
5962 pmap_sync_icache(pmap_t pmap, vm_offset_t va, vm_size_t sz)
5965 if (va >= VM_MIN_KERNEL_ADDRESS) {
5966 cpu_icache_sync_range(va, sz);
5971 /* Find the length of data in this page to flush */
5972 offset = va & PAGE_MASK;
5973 len = imin(PAGE_SIZE - offset, sz);
5976 /* Extract the physical address & find it in the DMAP */
5977 pa = pmap_extract(pmap, va);
5979 cpu_icache_sync_range(PHYS_TO_DMAP(pa), len);
5981 /* Move to the next page */
5984 /* Set the length for the next iteration */
5985 len = imin(PAGE_SIZE, sz);
5991 pmap_fault(pmap_t pmap, uint64_t esr, uint64_t far)
5993 pt_entry_t pte, *ptep;
6000 ec = ESR_ELx_EXCEPTION(esr);
6002 case EXCP_INSN_ABORT_L:
6003 case EXCP_INSN_ABORT:
6004 case EXCP_DATA_ABORT_L:
6005 case EXCP_DATA_ABORT:
6011 /* Data and insn aborts use same encoding for FSC field. */
6012 switch (esr & ISS_DATA_DFSC_MASK) {
6013 case ISS_DATA_DFSC_AFF_L1:
6014 case ISS_DATA_DFSC_AFF_L2:
6015 case ISS_DATA_DFSC_AFF_L3:
6017 ptep = pmap_pte(pmap, far, &lvl);
6019 pmap_set_bits(ptep, ATTR_AF);
6022 * XXXMJ as an optimization we could mark the entry
6023 * dirty if this is a write fault.
6028 case ISS_DATA_DFSC_PF_L1:
6029 case ISS_DATA_DFSC_PF_L2:
6030 case ISS_DATA_DFSC_PF_L3:
6031 if ((ec != EXCP_DATA_ABORT_L && ec != EXCP_DATA_ABORT) ||
6032 (esr & ISS_DATA_WnR) == 0)
6035 ptep = pmap_pte(pmap, far, &lvl);
6037 ((pte = pmap_load(ptep)) & ATTR_SW_DBM) != 0) {
6038 if ((pte & ATTR_AP_RW_BIT) == ATTR_AP(ATTR_AP_RO)) {
6039 pmap_clear_bits(ptep, ATTR_AP_RW_BIT);
6040 pmap_invalidate_page(pmap, far);
6046 case ISS_DATA_DFSC_TF_L0:
6047 case ISS_DATA_DFSC_TF_L1:
6048 case ISS_DATA_DFSC_TF_L2:
6049 case ISS_DATA_DFSC_TF_L3:
6051 * Retry the translation. A break-before-make sequence can
6052 * produce a transient fault.
6054 if (pmap == kernel_pmap) {
6056 * The translation fault may have occurred within a
6057 * critical section. Therefore, we must check the
6058 * address without acquiring the kernel pmap's lock.
6060 if (pmap_kextract(far) != 0)
6064 /* Ask the MMU to check the address. */
6065 intr = intr_disable();
6066 par = arm64_address_translate_s1e0r(far);
6071 * If the translation was successful, then we can
6072 * return success to the trap handler.
6074 if (PAR_SUCCESS(par))
6084 * Increase the starting virtual address of the given mapping if a
6085 * different alignment might result in more superpage mappings.
6088 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
6089 vm_offset_t *addr, vm_size_t size)
6091 vm_offset_t superpage_offset;
6095 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
6096 offset += ptoa(object->pg_color);
6097 superpage_offset = offset & L2_OFFSET;
6098 if (size - ((L2_SIZE - superpage_offset) & L2_OFFSET) < L2_SIZE ||
6099 (*addr & L2_OFFSET) == superpage_offset)
6101 if ((*addr & L2_OFFSET) < superpage_offset)
6102 *addr = (*addr & ~L2_OFFSET) + superpage_offset;
6104 *addr = ((*addr + L2_OFFSET) & ~L2_OFFSET) + superpage_offset;
6108 * Get the kernel virtual address of a set of physical pages. If there are
6109 * physical addresses not covered by the DMAP perform a transient mapping
6110 * that will be removed when calling pmap_unmap_io_transient.
6112 * \param page The pages the caller wishes to obtain the virtual
6113 * address on the kernel memory map.
6114 * \param vaddr On return contains the kernel virtual memory address
6115 * of the pages passed in the page parameter.
6116 * \param count Number of pages passed in.
6117 * \param can_fault TRUE if the thread using the mapped pages can take
6118 * page faults, FALSE otherwise.
6120 * \returns TRUE if the caller must call pmap_unmap_io_transient when
6121 * finished or FALSE otherwise.
6125 pmap_map_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
6126 boolean_t can_fault)
6129 boolean_t needs_mapping;
6133 * Allocate any KVA space that we need, this is done in a separate
6134 * loop to prevent calling vmem_alloc while pinned.
6136 needs_mapping = FALSE;
6137 for (i = 0; i < count; i++) {
6138 paddr = VM_PAGE_TO_PHYS(page[i]);
6139 if (__predict_false(!PHYS_IN_DMAP(paddr))) {
6140 error = vmem_alloc(kernel_arena, PAGE_SIZE,
6141 M_BESTFIT | M_WAITOK, &vaddr[i]);
6142 KASSERT(error == 0, ("vmem_alloc failed: %d", error));
6143 needs_mapping = TRUE;
6145 vaddr[i] = PHYS_TO_DMAP(paddr);
6149 /* Exit early if everything is covered by the DMAP */
6155 for (i = 0; i < count; i++) {
6156 paddr = VM_PAGE_TO_PHYS(page[i]);
6157 if (!PHYS_IN_DMAP(paddr)) {
6159 "pmap_map_io_transient: TODO: Map out of DMAP data");
6163 return (needs_mapping);
6167 pmap_unmap_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
6168 boolean_t can_fault)
6175 for (i = 0; i < count; i++) {
6176 paddr = VM_PAGE_TO_PHYS(page[i]);
6177 if (!PHYS_IN_DMAP(paddr)) {
6178 panic("ARM64TODO: pmap_unmap_io_transient: Unmap data");
6184 pmap_is_valid_memattr(pmap_t pmap __unused, vm_memattr_t mode)
6187 return (mode >= VM_MEMATTR_DEVICE && mode <= VM_MEMATTR_WRITE_THROUGH);
6191 * Track a range of the kernel's virtual address space that is contiguous
6192 * in various mapping attributes.
6194 struct pmap_kernel_map_range {
6204 sysctl_kmaps_dump(struct sbuf *sb, struct pmap_kernel_map_range *range,
6210 if (eva <= range->sva)
6213 index = range->attrs & ATTR_IDX_MASK;
6215 case ATTR_IDX(VM_MEMATTR_DEVICE):
6218 case ATTR_IDX(VM_MEMATTR_UNCACHEABLE):
6221 case ATTR_IDX(VM_MEMATTR_WRITE_BACK):
6224 case ATTR_IDX(VM_MEMATTR_WRITE_THROUGH):
6229 "%s: unknown memory type %x for range 0x%016lx-0x%016lx\n",
6230 __func__, index, range->sva, eva);
6235 sbuf_printf(sb, "0x%016lx-0x%016lx r%c%c%c %3s %d %d %d %d\n",
6237 (range->attrs & ATTR_AP_RW_BIT) == ATTR_AP_RW ? 'w' : '-',
6238 (range->attrs & ATTR_PXN) != 0 ? '-' : 'x',
6239 (range->attrs & ATTR_AP_USER) != 0 ? 'u' : 's',
6240 mode, range->l1blocks, range->l2blocks, range->l3contig,
6243 /* Reset to sentinel value. */
6244 range->sva = 0xfffffffffffffffful;
6248 * Determine whether the attributes specified by a page table entry match those
6249 * being tracked by the current range.
6252 sysctl_kmaps_match(struct pmap_kernel_map_range *range, pt_entry_t attrs)
6255 return (range->attrs == attrs);
6259 sysctl_kmaps_reinit(struct pmap_kernel_map_range *range, vm_offset_t va,
6263 memset(range, 0, sizeof(*range));
6265 range->attrs = attrs;
6269 * Given a leaf PTE, derive the mapping's attributes. If they do not match
6270 * those of the current run, dump the address range and its attributes, and
6274 sysctl_kmaps_check(struct sbuf *sb, struct pmap_kernel_map_range *range,
6275 vm_offset_t va, pd_entry_t l0e, pd_entry_t l1e, pd_entry_t l2e,
6280 attrs = l0e & (ATTR_AP_MASK | ATTR_XN);
6281 attrs |= l1e & (ATTR_AP_MASK | ATTR_XN);
6282 if ((l1e & ATTR_DESCR_MASK) == L1_BLOCK)
6283 attrs |= l1e & ATTR_IDX_MASK;
6284 attrs |= l2e & (ATTR_AP_MASK | ATTR_XN);
6285 if ((l2e & ATTR_DESCR_MASK) == L2_BLOCK)
6286 attrs |= l2e & ATTR_IDX_MASK;
6287 attrs |= l3e & (ATTR_AP_MASK | ATTR_XN | ATTR_IDX_MASK);
6289 if (range->sva > va || !sysctl_kmaps_match(range, attrs)) {
6290 sysctl_kmaps_dump(sb, range, va);
6291 sysctl_kmaps_reinit(range, va, attrs);
6296 sysctl_kmaps(SYSCTL_HANDLER_ARGS)
6298 struct pmap_kernel_map_range range;
6299 struct sbuf sbuf, *sb;
6300 pd_entry_t l0e, *l1, l1e, *l2, l2e;
6301 pt_entry_t *l3, l3e;
6304 int error, i, j, k, l;
6306 error = sysctl_wire_old_buffer(req, 0);
6310 sbuf_new_for_sysctl(sb, NULL, PAGE_SIZE, req);
6312 /* Sentinel value. */
6313 range.sva = 0xfffffffffffffffful;
6316 * Iterate over the kernel page tables without holding the kernel pmap
6317 * lock. Kernel page table pages are never freed, so at worst we will
6318 * observe inconsistencies in the output.
6320 for (sva = 0xffff000000000000ul, i = pmap_l0_index(sva); i < Ln_ENTRIES;
6322 if (i == pmap_l0_index(DMAP_MIN_ADDRESS))
6323 sbuf_printf(sb, "\nDirect map:\n");
6324 else if (i == pmap_l0_index(VM_MIN_KERNEL_ADDRESS))
6325 sbuf_printf(sb, "\nKernel map:\n");
6327 l0e = kernel_pmap->pm_l0[i];
6328 if ((l0e & ATTR_DESCR_VALID) == 0) {
6329 sysctl_kmaps_dump(sb, &range, sva);
6333 pa = l0e & ~ATTR_MASK;
6334 l1 = (pd_entry_t *)PHYS_TO_DMAP(pa);
6336 for (j = pmap_l1_index(sva); j < Ln_ENTRIES; j++) {
6338 if ((l1e & ATTR_DESCR_VALID) == 0) {
6339 sysctl_kmaps_dump(sb, &range, sva);
6343 if ((l1e & ATTR_DESCR_MASK) == L1_BLOCK) {
6344 sysctl_kmaps_check(sb, &range, sva, l0e, l1e,
6350 pa = l1e & ~ATTR_MASK;
6351 l2 = (pd_entry_t *)PHYS_TO_DMAP(pa);
6353 for (k = pmap_l2_index(sva); k < Ln_ENTRIES; k++) {
6355 if ((l2e & ATTR_DESCR_VALID) == 0) {
6356 sysctl_kmaps_dump(sb, &range, sva);
6360 if ((l2e & ATTR_DESCR_MASK) == L2_BLOCK) {
6361 sysctl_kmaps_check(sb, &range, sva,
6367 pa = l2e & ~ATTR_MASK;
6368 l3 = (pt_entry_t *)PHYS_TO_DMAP(pa);
6370 for (l = pmap_l3_index(sva); l < Ln_ENTRIES;
6371 l++, sva += L3_SIZE) {
6373 if ((l3e & ATTR_DESCR_VALID) == 0) {
6374 sysctl_kmaps_dump(sb, &range,
6378 sysctl_kmaps_check(sb, &range, sva,
6379 l0e, l1e, l2e, l3e);
6380 if ((l3e & ATTR_CONTIGUOUS) != 0)
6381 range.l3contig += l % 16 == 0 ?
6390 error = sbuf_finish(sb);
6394 SYSCTL_OID(_vm_pmap, OID_AUTO, kernel_maps,
6395 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE,
6396 NULL, 0, sysctl_kmaps, "A",
6397 "Dump kernel address layout");