2 * Copyright (c) 1991 Regents of the University of California.
4 * Copyright (c) 1994 John S. Dyson
6 * Copyright (c) 1994 David Greenman
8 * Copyright (c) 2003 Peter Wemm
10 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
11 * All rights reserved.
12 * Copyright (c) 2014 Andrew Turner
13 * All rights reserved.
14 * Copyright (c) 2014-2016 The FreeBSD Foundation
15 * All rights reserved.
17 * This code is derived from software contributed to Berkeley by
18 * the Systems Programming Group of the University of Utah Computer
19 * Science Department and William Jolitz of UUNET Technologies Inc.
21 * This software was developed by Andrew Turner under sponsorship from
22 * the FreeBSD Foundation.
24 * Redistribution and use in source and binary forms, with or without
25 * modification, are permitted provided that the following conditions
27 * 1. Redistributions of source code must retain the above copyright
28 * notice, this list of conditions and the following disclaimer.
29 * 2. Redistributions in binary form must reproduce the above copyright
30 * notice, this list of conditions and the following disclaimer in the
31 * documentation and/or other materials provided with the distribution.
32 * 3. All advertising materials mentioning features or use of this software
33 * must display the following acknowledgement:
34 * This product includes software developed by the University of
35 * California, Berkeley and its contributors.
36 * 4. Neither the name of the University nor the names of its contributors
37 * may be used to endorse or promote products derived from this software
38 * without specific prior written permission.
40 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
41 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
42 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
43 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
44 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
45 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
46 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
47 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
48 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
49 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
52 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
55 * Copyright (c) 2003 Networks Associates Technology, Inc.
56 * All rights reserved.
58 * This software was developed for the FreeBSD Project by Jake Burkholder,
59 * Safeport Network Services, and Network Associates Laboratories, the
60 * Security Research Division of Network Associates, Inc. under
61 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
62 * CHATS research program.
64 * Redistribution and use in source and binary forms, with or without
65 * modification, are permitted provided that the following conditions
67 * 1. Redistributions of source code must retain the above copyright
68 * notice, this list of conditions and the following disclaimer.
69 * 2. Redistributions in binary form must reproduce the above copyright
70 * notice, this list of conditions and the following disclaimer in the
71 * documentation and/or other materials provided with the distribution.
73 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
74 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
77 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
78 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
79 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
80 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
81 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
82 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
86 #include <sys/cdefs.h>
87 __FBSDID("$FreeBSD$");
90 * Manages physical address maps.
92 * Since the information managed by this module is
93 * also stored by the logical address mapping module,
94 * this module may throw away valid virtual-to-physical
95 * mappings at almost any time. However, invalidations
96 * of virtual-to-physical mappings must be done as
99 * In order to cope with hardware architectures which
100 * make virtual-to-physical map invalidates expensive,
101 * this module may delay invalidate or reduced protection
102 * operations until such time as they are actually
103 * necessary. This module is given full information as
104 * to which processors are currently using which maps,
105 * and to when physical maps must be made correct.
110 #include <sys/param.h>
111 #include <sys/bitstring.h>
113 #include <sys/systm.h>
114 #include <sys/kernel.h>
116 #include <sys/limits.h>
117 #include <sys/lock.h>
118 #include <sys/malloc.h>
119 #include <sys/mman.h>
120 #include <sys/msgbuf.h>
121 #include <sys/mutex.h>
122 #include <sys/proc.h>
123 #include <sys/rwlock.h>
124 #include <sys/sbuf.h>
126 #include <sys/vmem.h>
127 #include <sys/vmmeter.h>
128 #include <sys/sched.h>
129 #include <sys/sysctl.h>
130 #include <sys/_unrhdr.h>
134 #include <vm/vm_param.h>
135 #include <vm/vm_kern.h>
136 #include <vm/vm_page.h>
137 #include <vm/vm_map.h>
138 #include <vm/vm_object.h>
139 #include <vm/vm_extern.h>
140 #include <vm/vm_pageout.h>
141 #include <vm/vm_pager.h>
142 #include <vm/vm_phys.h>
143 #include <vm/vm_radix.h>
144 #include <vm/vm_reserv.h>
147 #include <machine/machdep.h>
148 #include <machine/md_var.h>
149 #include <machine/pcb.h>
151 #include <arm/include/physmem.h>
153 #define NL0PG (PAGE_SIZE/(sizeof (pd_entry_t)))
154 #define NL1PG (PAGE_SIZE/(sizeof (pd_entry_t)))
155 #define NL2PG (PAGE_SIZE/(sizeof (pd_entry_t)))
156 #define NL3PG (PAGE_SIZE/(sizeof (pt_entry_t)))
158 #define NUL0E L0_ENTRIES
159 #define NUL1E (NUL0E * NL1PG)
160 #define NUL2E (NUL1E * NL2PG)
162 #if !defined(DIAGNOSTIC)
163 #ifdef __GNUC_GNU_INLINE__
164 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
166 #define PMAP_INLINE extern inline
173 #define PV_STAT(x) do { x ; } while (0)
175 #define PV_STAT(x) do { } while (0)
178 #define pmap_l2_pindex(v) ((v) >> L2_SHIFT)
179 #define pa_to_pvh(pa) (&pv_table[pmap_l2_pindex(pa)])
181 #define NPV_LIST_LOCKS MAXCPU
183 #define PHYS_TO_PV_LIST_LOCK(pa) \
184 (&pv_list_locks[pa_index(pa) % NPV_LIST_LOCKS])
186 #define CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa) do { \
187 struct rwlock **_lockp = (lockp); \
188 struct rwlock *_new_lock; \
190 _new_lock = PHYS_TO_PV_LIST_LOCK(pa); \
191 if (_new_lock != *_lockp) { \
192 if (*_lockp != NULL) \
193 rw_wunlock(*_lockp); \
194 *_lockp = _new_lock; \
199 #define CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m) \
200 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, VM_PAGE_TO_PHYS(m))
202 #define RELEASE_PV_LIST_LOCK(lockp) do { \
203 struct rwlock **_lockp = (lockp); \
205 if (*_lockp != NULL) { \
206 rw_wunlock(*_lockp); \
211 #define VM_PAGE_TO_PV_LIST_LOCK(m) \
212 PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m))
215 * The presence of this flag indicates that the mapping is writeable.
216 * If the ATTR_AP_RO bit is also set, then the mapping is clean, otherwise it is
217 * dirty. This flag may only be set on managed mappings.
219 * The DBM bit is reserved on ARMv8.0 but it seems we can safely treat it
220 * as a software managed bit.
222 #define ATTR_SW_DBM ATTR_DBM
224 struct pmap kernel_pmap_store;
226 /* Used for mapping ACPI memory before VM is initialized */
227 #define PMAP_PREINIT_MAPPING_COUNT 32
228 #define PMAP_PREINIT_MAPPING_SIZE (PMAP_PREINIT_MAPPING_COUNT * L2_SIZE)
229 static vm_offset_t preinit_map_va; /* Start VA of pre-init mapping space */
230 static int vm_initialized = 0; /* No need to use pre-init maps when set */
233 * Reserve a few L2 blocks starting from 'preinit_map_va' pointer.
234 * Always map entire L2 block for simplicity.
235 * VA of L2 block = preinit_map_va + i * L2_SIZE
237 static struct pmap_preinit_mapping {
241 } pmap_preinit_mapping[PMAP_PREINIT_MAPPING_COUNT];
243 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
244 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
245 vm_offset_t kernel_vm_end = 0;
248 * Data for the pv entry allocation mechanism.
250 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
251 static struct mtx pv_chunks_mutex;
252 static struct rwlock pv_list_locks[NPV_LIST_LOCKS];
253 static struct md_page *pv_table;
254 static struct md_page pv_dummy;
256 vm_paddr_t dmap_phys_base; /* The start of the dmap region */
257 vm_paddr_t dmap_phys_max; /* The limit of the dmap region */
258 vm_offset_t dmap_max_addr; /* The virtual address limit of the dmap */
260 /* This code assumes all L1 DMAP entries will be used */
261 CTASSERT((DMAP_MIN_ADDRESS & ~L0_OFFSET) == DMAP_MIN_ADDRESS);
262 CTASSERT((DMAP_MAX_ADDRESS & ~L0_OFFSET) == DMAP_MAX_ADDRESS);
264 #define DMAP_TABLES ((DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS) >> L0_SHIFT)
265 extern pt_entry_t pagetable_dmap[];
267 #define PHYSMAP_SIZE (2 * (VM_PHYSSEG_MAX - 1))
268 static vm_paddr_t physmap[PHYSMAP_SIZE];
269 static u_int physmap_idx;
271 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters");
274 * This ASID allocator uses a bit vector ("asid_set") to remember which ASIDs
275 * that it has currently allocated to a pmap, a cursor ("asid_next") to
276 * optimize its search for a free ASID in the bit vector, and an epoch number
277 * ("asid_epoch") to indicate when it has reclaimed all previously allocated
278 * ASIDs that are not currently active on a processor.
280 * The current epoch number is always in the range [0, INT_MAX). Negative
281 * numbers and INT_MAX are reserved for special cases that are described
284 static SYSCTL_NODE(_vm_pmap, OID_AUTO, asid, CTLFLAG_RD, 0, "ASID allocator");
285 static int asid_bits;
286 SYSCTL_INT(_vm_pmap_asid, OID_AUTO, bits, CTLFLAG_RD, &asid_bits, 0,
287 "The number of bits in an ASID");
288 static bitstr_t *asid_set;
289 static int asid_set_size;
290 static int asid_next;
291 SYSCTL_INT(_vm_pmap_asid, OID_AUTO, next, CTLFLAG_RD, &asid_next, 0,
292 "The last allocated ASID plus one");
293 static int asid_epoch;
294 SYSCTL_INT(_vm_pmap_asid, OID_AUTO, epoch, CTLFLAG_RD, &asid_epoch, 0,
295 "The current epoch number");
296 static struct mtx asid_set_mutex;
299 * A pmap's cookie encodes an ASID and epoch number. Cookies for reserved
300 * ASIDs have a negative epoch number, specifically, INT_MIN. Cookies for
301 * dynamically allocated ASIDs have a non-negative epoch number.
303 * An invalid ASID is represented by -1.
305 * There are two special-case cookie values: (1) COOKIE_FROM(-1, INT_MIN),
306 * which indicates that an ASID should never be allocated to the pmap, and
307 * (2) COOKIE_FROM(-1, INT_MAX), which indicates that an ASID should be
308 * allocated when the pmap is next activated.
310 #define COOKIE_FROM(asid, epoch) ((long)((u_int)(asid) | \
311 ((u_long)(epoch) << 32)))
312 #define COOKIE_TO_ASID(cookie) ((int)(cookie))
313 #define COOKIE_TO_EPOCH(cookie) ((int)((u_long)(cookie) >> 32))
315 static int superpages_enabled = 1;
316 SYSCTL_INT(_vm_pmap, OID_AUTO, superpages_enabled,
317 CTLFLAG_RDTUN | CTLFLAG_NOFETCH, &superpages_enabled, 0,
318 "Are large page mappings enabled?");
321 * Internal flags for pmap_enter()'s helper functions.
323 #define PMAP_ENTER_NORECLAIM 0x1000000 /* Don't reclaim PV entries. */
324 #define PMAP_ENTER_NOREPLACE 0x2000000 /* Don't replace mappings. */
326 static void free_pv_chunk(struct pv_chunk *pc);
327 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
328 static pv_entry_t get_pv_entry(pmap_t pmap, struct rwlock **lockp);
329 static vm_page_t reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp);
330 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
331 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
334 static bool pmap_activate_int(pmap_t pmap);
335 static void pmap_alloc_asid(pmap_t pmap);
336 static int pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode);
337 static pt_entry_t *pmap_demote_l1(pmap_t pmap, pt_entry_t *l1, vm_offset_t va);
338 static pt_entry_t *pmap_demote_l2_locked(pmap_t pmap, pt_entry_t *l2,
339 vm_offset_t va, struct rwlock **lockp);
340 static pt_entry_t *pmap_demote_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t va);
341 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
342 vm_page_t m, vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp);
343 static int pmap_enter_l2(pmap_t pmap, vm_offset_t va, pd_entry_t new_l2,
344 u_int flags, vm_page_t m, struct rwlock **lockp);
345 static int pmap_remove_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t sva,
346 pd_entry_t l1e, struct spglist *free, struct rwlock **lockp);
347 static int pmap_remove_l3(pmap_t pmap, pt_entry_t *l3, vm_offset_t sva,
348 pd_entry_t l2e, struct spglist *free, struct rwlock **lockp);
349 static void pmap_reset_asid_set(void);
350 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
351 vm_page_t m, struct rwlock **lockp);
353 static vm_page_t _pmap_alloc_l3(pmap_t pmap, vm_pindex_t ptepindex,
354 struct rwlock **lockp);
356 static void _pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m,
357 struct spglist *free);
358 static int pmap_unuse_pt(pmap_t, vm_offset_t, pd_entry_t, struct spglist *);
359 static __inline vm_page_t pmap_remove_pt_page(pmap_t pmap, vm_offset_t va);
362 * These load the old table data and store the new value.
363 * They need to be atomic as the System MMU may write to the table at
364 * the same time as the CPU.
366 #define pmap_clear(table) atomic_store_64(table, 0)
367 #define pmap_clear_bits(table, bits) atomic_clear_64(table, bits)
368 #define pmap_load(table) (*table)
369 #define pmap_load_clear(table) atomic_swap_64(table, 0)
370 #define pmap_load_store(table, entry) atomic_swap_64(table, entry)
371 #define pmap_set_bits(table, bits) atomic_set_64(table, bits)
372 #define pmap_store(table, entry) atomic_store_64(table, entry)
374 /********************/
375 /* Inline functions */
376 /********************/
379 pagecopy(void *s, void *d)
382 memcpy(d, s, PAGE_SIZE);
385 static __inline pd_entry_t *
386 pmap_l0(pmap_t pmap, vm_offset_t va)
389 return (&pmap->pm_l0[pmap_l0_index(va)]);
392 static __inline pd_entry_t *
393 pmap_l0_to_l1(pd_entry_t *l0, vm_offset_t va)
397 l1 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l0) & ~ATTR_MASK);
398 return (&l1[pmap_l1_index(va)]);
401 static __inline pd_entry_t *
402 pmap_l1(pmap_t pmap, vm_offset_t va)
406 l0 = pmap_l0(pmap, va);
407 if ((pmap_load(l0) & ATTR_DESCR_MASK) != L0_TABLE)
410 return (pmap_l0_to_l1(l0, va));
413 static __inline pd_entry_t *
414 pmap_l1_to_l2(pd_entry_t *l1, vm_offset_t va)
418 l2 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l1) & ~ATTR_MASK);
419 return (&l2[pmap_l2_index(va)]);
422 static __inline pd_entry_t *
423 pmap_l2(pmap_t pmap, vm_offset_t va)
427 l1 = pmap_l1(pmap, va);
428 if ((pmap_load(l1) & ATTR_DESCR_MASK) != L1_TABLE)
431 return (pmap_l1_to_l2(l1, va));
434 static __inline pt_entry_t *
435 pmap_l2_to_l3(pd_entry_t *l2, vm_offset_t va)
439 l3 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l2) & ~ATTR_MASK);
440 return (&l3[pmap_l3_index(va)]);
444 * Returns the lowest valid pde for a given virtual address.
445 * The next level may or may not point to a valid page or block.
447 static __inline pd_entry_t *
448 pmap_pde(pmap_t pmap, vm_offset_t va, int *level)
450 pd_entry_t *l0, *l1, *l2, desc;
452 l0 = pmap_l0(pmap, va);
453 desc = pmap_load(l0) & ATTR_DESCR_MASK;
454 if (desc != L0_TABLE) {
459 l1 = pmap_l0_to_l1(l0, va);
460 desc = pmap_load(l1) & ATTR_DESCR_MASK;
461 if (desc != L1_TABLE) {
466 l2 = pmap_l1_to_l2(l1, va);
467 desc = pmap_load(l2) & ATTR_DESCR_MASK;
468 if (desc != L2_TABLE) {
478 * Returns the lowest valid pte block or table entry for a given virtual
479 * address. If there are no valid entries return NULL and set the level to
480 * the first invalid level.
482 static __inline pt_entry_t *
483 pmap_pte(pmap_t pmap, vm_offset_t va, int *level)
485 pd_entry_t *l1, *l2, desc;
488 l1 = pmap_l1(pmap, va);
493 desc = pmap_load(l1) & ATTR_DESCR_MASK;
494 if (desc == L1_BLOCK) {
499 if (desc != L1_TABLE) {
504 l2 = pmap_l1_to_l2(l1, va);
505 desc = pmap_load(l2) & ATTR_DESCR_MASK;
506 if (desc == L2_BLOCK) {
511 if (desc != L2_TABLE) {
517 l3 = pmap_l2_to_l3(l2, va);
518 if ((pmap_load(l3) & ATTR_DESCR_MASK) != L3_PAGE)
525 pmap_ps_enabled(pmap_t pmap __unused)
528 return (superpages_enabled != 0);
532 pmap_get_tables(pmap_t pmap, vm_offset_t va, pd_entry_t **l0, pd_entry_t **l1,
533 pd_entry_t **l2, pt_entry_t **l3)
535 pd_entry_t *l0p, *l1p, *l2p;
537 if (pmap->pm_l0 == NULL)
540 l0p = pmap_l0(pmap, va);
543 if ((pmap_load(l0p) & ATTR_DESCR_MASK) != L0_TABLE)
546 l1p = pmap_l0_to_l1(l0p, va);
549 if ((pmap_load(l1p) & ATTR_DESCR_MASK) == L1_BLOCK) {
555 if ((pmap_load(l1p) & ATTR_DESCR_MASK) != L1_TABLE)
558 l2p = pmap_l1_to_l2(l1p, va);
561 if ((pmap_load(l2p) & ATTR_DESCR_MASK) == L2_BLOCK) {
566 if ((pmap_load(l2p) & ATTR_DESCR_MASK) != L2_TABLE)
569 *l3 = pmap_l2_to_l3(l2p, va);
575 pmap_l3_valid(pt_entry_t l3)
578 return ((l3 & ATTR_DESCR_MASK) == L3_PAGE);
582 CTASSERT(L1_BLOCK == L2_BLOCK);
585 * Checks if the PTE is dirty.
588 pmap_pte_dirty(pt_entry_t pte)
591 KASSERT((pte & ATTR_SW_MANAGED) != 0, ("pte %#lx is unmanaged", pte));
592 KASSERT((pte & (ATTR_AP_RW_BIT | ATTR_SW_DBM)) != 0,
593 ("pte %#lx is writeable and missing ATTR_SW_DBM", pte));
595 return ((pte & (ATTR_AP_RW_BIT | ATTR_SW_DBM)) ==
596 (ATTR_AP(ATTR_AP_RW) | ATTR_SW_DBM));
600 pmap_resident_count_inc(pmap_t pmap, int count)
603 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
604 pmap->pm_stats.resident_count += count;
608 pmap_resident_count_dec(pmap_t pmap, int count)
611 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
612 KASSERT(pmap->pm_stats.resident_count >= count,
613 ("pmap %p resident count underflow %ld %d", pmap,
614 pmap->pm_stats.resident_count, count));
615 pmap->pm_stats.resident_count -= count;
619 pmap_early_page_idx(vm_offset_t l1pt, vm_offset_t va, u_int *l1_slot,
625 l1 = (pd_entry_t *)l1pt;
626 *l1_slot = (va >> L1_SHIFT) & Ln_ADDR_MASK;
628 /* Check locore has used a table L1 map */
629 KASSERT((l1[*l1_slot] & ATTR_DESCR_MASK) == L1_TABLE,
630 ("Invalid bootstrap L1 table"));
631 /* Find the address of the L2 table */
632 l2 = (pt_entry_t *)init_pt_va;
633 *l2_slot = pmap_l2_index(va);
639 pmap_early_vtophys(vm_offset_t l1pt, vm_offset_t va)
641 u_int l1_slot, l2_slot;
644 l2 = pmap_early_page_idx(l1pt, va, &l1_slot, &l2_slot);
646 return ((l2[l2_slot] & ~ATTR_MASK) + (va & L2_OFFSET));
650 pmap_bootstrap_dmap(vm_offset_t kern_l1, vm_paddr_t min_pa,
651 vm_offset_t freemempos)
655 vm_paddr_t l2_pa, pa;
656 u_int l1_slot, l2_slot, prev_l1_slot;
659 dmap_phys_base = min_pa & ~L1_OFFSET;
665 #define DMAP_TABLES ((DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS) >> L0_SHIFT)
666 memset(pagetable_dmap, 0, PAGE_SIZE * DMAP_TABLES);
668 for (i = 0; i < (physmap_idx * 2); i += 2) {
669 pa = physmap[i] & ~L2_OFFSET;
670 va = pa - dmap_phys_base + DMAP_MIN_ADDRESS;
672 /* Create L2 mappings at the start of the region */
673 if ((pa & L1_OFFSET) != 0) {
674 l1_slot = ((va - DMAP_MIN_ADDRESS) >> L1_SHIFT);
675 if (l1_slot != prev_l1_slot) {
676 prev_l1_slot = l1_slot;
677 l2 = (pt_entry_t *)freemempos;
678 l2_pa = pmap_early_vtophys(kern_l1,
680 freemempos += PAGE_SIZE;
682 pmap_store(&pagetable_dmap[l1_slot],
683 (l2_pa & ~Ln_TABLE_MASK) | L1_TABLE);
685 memset(l2, 0, PAGE_SIZE);
688 ("pmap_bootstrap_dmap: NULL l2 map"));
689 for (; va < DMAP_MAX_ADDRESS && pa < physmap[i + 1];
690 pa += L2_SIZE, va += L2_SIZE) {
692 * We are on a boundary, stop to
693 * create a level 1 block
695 if ((pa & L1_OFFSET) == 0)
698 l2_slot = pmap_l2_index(va);
699 KASSERT(l2_slot != 0, ("..."));
700 pmap_store(&l2[l2_slot],
701 (pa & ~L2_OFFSET) | ATTR_DEFAULT | ATTR_XN |
702 ATTR_IDX(VM_MEMATTR_WRITE_BACK) | L2_BLOCK);
704 KASSERT(va == (pa - dmap_phys_base + DMAP_MIN_ADDRESS),
708 for (; va < DMAP_MAX_ADDRESS && pa < physmap[i + 1] &&
709 (physmap[i + 1] - pa) >= L1_SIZE;
710 pa += L1_SIZE, va += L1_SIZE) {
711 l1_slot = ((va - DMAP_MIN_ADDRESS) >> L1_SHIFT);
712 pmap_store(&pagetable_dmap[l1_slot],
713 (pa & ~L1_OFFSET) | ATTR_DEFAULT | ATTR_XN |
714 ATTR_IDX(VM_MEMATTR_WRITE_BACK) | L1_BLOCK);
717 /* Create L2 mappings at the end of the region */
718 if (pa < physmap[i + 1]) {
719 l1_slot = ((va - DMAP_MIN_ADDRESS) >> L1_SHIFT);
720 if (l1_slot != prev_l1_slot) {
721 prev_l1_slot = l1_slot;
722 l2 = (pt_entry_t *)freemempos;
723 l2_pa = pmap_early_vtophys(kern_l1,
725 freemempos += PAGE_SIZE;
727 pmap_store(&pagetable_dmap[l1_slot],
728 (l2_pa & ~Ln_TABLE_MASK) | L1_TABLE);
730 memset(l2, 0, PAGE_SIZE);
733 ("pmap_bootstrap_dmap: NULL l2 map"));
734 for (; va < DMAP_MAX_ADDRESS && pa < physmap[i + 1];
735 pa += L2_SIZE, va += L2_SIZE) {
736 l2_slot = pmap_l2_index(va);
737 pmap_store(&l2[l2_slot],
738 (pa & ~L2_OFFSET) | ATTR_DEFAULT | ATTR_XN |
739 ATTR_IDX(VM_MEMATTR_WRITE_BACK) | L2_BLOCK);
743 if (pa > dmap_phys_max) {
755 pmap_bootstrap_l2(vm_offset_t l1pt, vm_offset_t va, vm_offset_t l2_start)
762 KASSERT((va & L1_OFFSET) == 0, ("Invalid virtual address"));
764 l1 = (pd_entry_t *)l1pt;
765 l1_slot = pmap_l1_index(va);
768 for (; va < VM_MAX_KERNEL_ADDRESS; l1_slot++, va += L1_SIZE) {
769 KASSERT(l1_slot < Ln_ENTRIES, ("Invalid L1 index"));
771 pa = pmap_early_vtophys(l1pt, l2pt);
772 pmap_store(&l1[l1_slot],
773 (pa & ~Ln_TABLE_MASK) | L1_TABLE);
777 /* Clean the L2 page table */
778 memset((void *)l2_start, 0, l2pt - l2_start);
784 pmap_bootstrap_l3(vm_offset_t l1pt, vm_offset_t va, vm_offset_t l3_start)
791 KASSERT((va & L2_OFFSET) == 0, ("Invalid virtual address"));
793 l2 = pmap_l2(kernel_pmap, va);
794 l2 = (pd_entry_t *)rounddown2((uintptr_t)l2, PAGE_SIZE);
795 l2_slot = pmap_l2_index(va);
798 for (; va < VM_MAX_KERNEL_ADDRESS; l2_slot++, va += L2_SIZE) {
799 KASSERT(l2_slot < Ln_ENTRIES, ("Invalid L2 index"));
801 pa = pmap_early_vtophys(l1pt, l3pt);
802 pmap_store(&l2[l2_slot],
803 (pa & ~Ln_TABLE_MASK) | ATTR_UXN | L2_TABLE);
807 /* Clean the L2 page table */
808 memset((void *)l3_start, 0, l3pt - l3_start);
814 * Bootstrap the system enough to run with virtual memory.
817 pmap_bootstrap(vm_offset_t l0pt, vm_offset_t l1pt, vm_paddr_t kernstart,
820 u_int l1_slot, l2_slot;
822 vm_offset_t va, freemempos;
823 vm_offset_t dpcpu, msgbufpv;
824 vm_paddr_t start_pa, pa, min_pa;
828 /* Verify that the ASID is set through TTBR0. */
829 KASSERT((READ_SPECIALREG(tcr_el1) & TCR_A1) == 0,
830 ("pmap_bootstrap: TCR_EL1.A1 != 0"));
832 kern_delta = KERNBASE - kernstart;
834 printf("pmap_bootstrap %lx %lx %lx\n", l1pt, kernstart, kernlen);
835 printf("%lx\n", l1pt);
836 printf("%lx\n", (KERNBASE >> L1_SHIFT) & Ln_ADDR_MASK);
838 /* Set this early so we can use the pagetable walking functions */
839 kernel_pmap_store.pm_l0 = (pd_entry_t *)l0pt;
840 PMAP_LOCK_INIT(kernel_pmap);
841 kernel_pmap->pm_l0_paddr = l0pt - kern_delta;
842 kernel_pmap->pm_cookie = COOKIE_FROM(-1, INT_MIN);
844 /* Assume the address we were loaded to is a valid physical address */
845 min_pa = KERNBASE - kern_delta;
847 physmap_idx = arm_physmem_avail(physmap, nitems(physmap));
851 * Find the minimum physical address. physmap is sorted,
852 * but may contain empty ranges.
854 for (i = 0; i < (physmap_idx * 2); i += 2) {
855 if (physmap[i] == physmap[i + 1])
857 if (physmap[i] <= min_pa)
861 freemempos = KERNBASE + kernlen;
862 freemempos = roundup2(freemempos, PAGE_SIZE);
864 /* Create a direct map region early so we can use it for pa -> va */
865 freemempos = pmap_bootstrap_dmap(l1pt, min_pa, freemempos);
868 start_pa = pa = KERNBASE - kern_delta;
871 * Read the page table to find out what is already mapped.
872 * This assumes we have mapped a block of memory from KERNBASE
873 * using a single L1 entry.
875 l2 = pmap_early_page_idx(l1pt, KERNBASE, &l1_slot, &l2_slot);
877 /* Sanity check the index, KERNBASE should be the first VA */
878 KASSERT(l2_slot == 0, ("The L2 index is non-zero"));
880 /* Find how many pages we have mapped */
881 for (; l2_slot < Ln_ENTRIES; l2_slot++) {
882 if ((l2[l2_slot] & ATTR_DESCR_MASK) == 0)
885 /* Check locore used L2 blocks */
886 KASSERT((l2[l2_slot] & ATTR_DESCR_MASK) == L2_BLOCK,
887 ("Invalid bootstrap L2 table"));
888 KASSERT((l2[l2_slot] & ~ATTR_MASK) == pa,
889 ("Incorrect PA in L2 table"));
895 va = roundup2(va, L1_SIZE);
897 /* Create the l2 tables up to VM_MAX_KERNEL_ADDRESS */
898 freemempos = pmap_bootstrap_l2(l1pt, va, freemempos);
899 /* And the l3 tables for the early devmap */
900 freemempos = pmap_bootstrap_l3(l1pt,
901 VM_MAX_KERNEL_ADDRESS - (PMAP_MAPDEV_EARLY_SIZE), freemempos);
905 #define alloc_pages(var, np) \
906 (var) = freemempos; \
907 freemempos += (np * PAGE_SIZE); \
908 memset((char *)(var), 0, ((np) * PAGE_SIZE));
910 /* Allocate dynamic per-cpu area. */
911 alloc_pages(dpcpu, DPCPU_SIZE / PAGE_SIZE);
912 dpcpu_init((void *)dpcpu, 0);
914 /* Allocate memory for the msgbuf, e.g. for /sbin/dmesg */
915 alloc_pages(msgbufpv, round_page(msgbufsize) / PAGE_SIZE);
916 msgbufp = (void *)msgbufpv;
918 /* Reserve some VA space for early BIOS/ACPI mapping */
919 preinit_map_va = roundup2(freemempos, L2_SIZE);
921 virtual_avail = preinit_map_va + PMAP_PREINIT_MAPPING_SIZE;
922 virtual_avail = roundup2(virtual_avail, L1_SIZE);
923 virtual_end = VM_MAX_KERNEL_ADDRESS - (PMAP_MAPDEV_EARLY_SIZE);
924 kernel_vm_end = virtual_avail;
926 pa = pmap_early_vtophys(l1pt, freemempos);
928 arm_physmem_exclude_region(start_pa, pa - start_pa, EXFLAG_NOALLOC);
934 * Initialize a vm_page's machine-dependent fields.
937 pmap_page_init(vm_page_t m)
940 TAILQ_INIT(&m->md.pv_list);
941 m->md.pv_memattr = VM_MEMATTR_WRITE_BACK;
945 * Initialize the pmap module.
946 * Called by vm_init, to initialize any structures that the pmap
947 * system needs to map virtual memory.
956 * Determine whether an ASID is 8 or 16 bits in size.
958 asid_bits = (READ_SPECIALREG(tcr_el1) & TCR_ASID_16) != 0 ? 16 : 8;
961 * Are large page mappings enabled?
963 TUNABLE_INT_FETCH("vm.pmap.superpages_enabled", &superpages_enabled);
964 if (superpages_enabled) {
965 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
966 ("pmap_init: can't assign to pagesizes[1]"));
967 pagesizes[1] = L2_SIZE;
971 * Initialize the ASID allocator. At this point, we are still too
972 * early in the overall initialization process to use bit_alloc().
974 asid_set_size = 1 << asid_bits;
975 asid_set = (bitstr_t *)kmem_malloc(bitstr_size(asid_set_size),
977 for (i = 0; i < ASID_FIRST_AVAILABLE; i++)
978 bit_set(asid_set, i);
979 asid_next = ASID_FIRST_AVAILABLE;
980 mtx_init(&asid_set_mutex, "asid set", NULL, MTX_SPIN);
983 * Initialize the pv chunk list mutex.
985 mtx_init(&pv_chunks_mutex, "pmap pv chunk list", NULL, MTX_DEF);
988 * Initialize the pool of pv list locks.
990 for (i = 0; i < NPV_LIST_LOCKS; i++)
991 rw_init(&pv_list_locks[i], "pmap pv list");
994 * Calculate the size of the pv head table for superpages.
996 pv_npg = howmany(vm_phys_segs[vm_phys_nsegs - 1].end, L2_SIZE);
999 * Allocate memory for the pv head table for superpages.
1001 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
1003 pv_table = (struct md_page *)kmem_malloc(s, M_WAITOK | M_ZERO);
1004 for (i = 0; i < pv_npg; i++)
1005 TAILQ_INIT(&pv_table[i].pv_list);
1006 TAILQ_INIT(&pv_dummy.pv_list);
1011 static SYSCTL_NODE(_vm_pmap, OID_AUTO, l2, CTLFLAG_RD, 0,
1012 "2MB page mapping counters");
1014 static u_long pmap_l2_demotions;
1015 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, demotions, CTLFLAG_RD,
1016 &pmap_l2_demotions, 0, "2MB page demotions");
1018 static u_long pmap_l2_mappings;
1019 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, mappings, CTLFLAG_RD,
1020 &pmap_l2_mappings, 0, "2MB page mappings");
1022 static u_long pmap_l2_p_failures;
1023 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, p_failures, CTLFLAG_RD,
1024 &pmap_l2_p_failures, 0, "2MB page promotion failures");
1026 static u_long pmap_l2_promotions;
1027 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, promotions, CTLFLAG_RD,
1028 &pmap_l2_promotions, 0, "2MB page promotions");
1031 * Invalidate a single TLB entry.
1033 static __inline void
1034 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
1039 if (pmap == kernel_pmap) {
1041 __asm __volatile("tlbi vaae1is, %0" : : "r" (r));
1043 r = ASID_TO_OPERAND(COOKIE_TO_ASID(pmap->pm_cookie)) | atop(va);
1044 __asm __volatile("tlbi vae1is, %0" : : "r" (r));
1050 static __inline void
1051 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1053 uint64_t end, r, start;
1056 if (pmap == kernel_pmap) {
1059 for (r = start; r < end; r++)
1060 __asm __volatile("tlbi vaae1is, %0" : : "r" (r));
1062 start = end = ASID_TO_OPERAND(COOKIE_TO_ASID(pmap->pm_cookie));
1065 for (r = start; r < end; r++)
1066 __asm __volatile("tlbi vae1is, %0" : : "r" (r));
1072 static __inline void
1073 pmap_invalidate_all(pmap_t pmap)
1078 if (pmap == kernel_pmap) {
1079 __asm __volatile("tlbi vmalle1is");
1081 r = ASID_TO_OPERAND(COOKIE_TO_ASID(pmap->pm_cookie));
1082 __asm __volatile("tlbi aside1is, %0" : : "r" (r));
1089 * Routine: pmap_extract
1091 * Extract the physical page address associated
1092 * with the given map/virtual_address pair.
1095 pmap_extract(pmap_t pmap, vm_offset_t va)
1097 pt_entry_t *pte, tpte;
1104 * Find the block or page map for this virtual address. pmap_pte
1105 * will return either a valid block/page entry, or NULL.
1107 pte = pmap_pte(pmap, va, &lvl);
1109 tpte = pmap_load(pte);
1110 pa = tpte & ~ATTR_MASK;
1113 KASSERT((tpte & ATTR_DESCR_MASK) == L1_BLOCK,
1114 ("pmap_extract: Invalid L1 pte found: %lx",
1115 tpte & ATTR_DESCR_MASK));
1116 pa |= (va & L1_OFFSET);
1119 KASSERT((tpte & ATTR_DESCR_MASK) == L2_BLOCK,
1120 ("pmap_extract: Invalid L2 pte found: %lx",
1121 tpte & ATTR_DESCR_MASK));
1122 pa |= (va & L2_OFFSET);
1125 KASSERT((tpte & ATTR_DESCR_MASK) == L3_PAGE,
1126 ("pmap_extract: Invalid L3 pte found: %lx",
1127 tpte & ATTR_DESCR_MASK));
1128 pa |= (va & L3_OFFSET);
1137 * Routine: pmap_extract_and_hold
1139 * Atomically extract and hold the physical page
1140 * with the given pmap and virtual address pair
1141 * if that mapping permits the given protection.
1144 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1146 pt_entry_t *pte, tpte;
1153 pte = pmap_pte(pmap, va, &lvl);
1155 tpte = pmap_load(pte);
1157 KASSERT(lvl > 0 && lvl <= 3,
1158 ("pmap_extract_and_hold: Invalid level %d", lvl));
1159 CTASSERT(L1_BLOCK == L2_BLOCK);
1160 KASSERT((lvl == 3 && (tpte & ATTR_DESCR_MASK) == L3_PAGE) ||
1161 (lvl < 3 && (tpte & ATTR_DESCR_MASK) == L1_BLOCK),
1162 ("pmap_extract_and_hold: Invalid pte at L%d: %lx", lvl,
1163 tpte & ATTR_DESCR_MASK));
1164 if (((tpte & ATTR_AP_RW_BIT) == ATTR_AP(ATTR_AP_RW)) ||
1165 ((prot & VM_PROT_WRITE) == 0)) {
1168 off = va & L1_OFFSET;
1171 off = va & L2_OFFSET;
1177 m = PHYS_TO_VM_PAGE((tpte & ~ATTR_MASK) | off);
1178 if (!vm_page_wire_mapped(m))
1187 pmap_kextract(vm_offset_t va)
1189 pt_entry_t *pte, tpte;
1191 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS)
1192 return (DMAP_TO_PHYS(va));
1193 pte = pmap_l1(kernel_pmap, va);
1198 * A concurrent pmap_update_entry() will clear the entry's valid bit
1199 * but leave the rest of the entry unchanged. Therefore, we treat a
1200 * non-zero entry as being valid, and we ignore the valid bit when
1201 * determining whether the entry maps a block, page, or table.
1203 tpte = pmap_load(pte);
1206 if ((tpte & ATTR_DESCR_TYPE_MASK) == ATTR_DESCR_TYPE_BLOCK)
1207 return ((tpte & ~ATTR_MASK) | (va & L1_OFFSET));
1208 pte = pmap_l1_to_l2(&tpte, va);
1209 tpte = pmap_load(pte);
1212 if ((tpte & ATTR_DESCR_TYPE_MASK) == ATTR_DESCR_TYPE_BLOCK)
1213 return ((tpte & ~ATTR_MASK) | (va & L2_OFFSET));
1214 pte = pmap_l2_to_l3(&tpte, va);
1215 tpte = pmap_load(pte);
1218 return ((tpte & ~ATTR_MASK) | (va & L3_OFFSET));
1221 /***************************************************
1222 * Low level mapping routines.....
1223 ***************************************************/
1226 pmap_kenter(vm_offset_t sva, vm_size_t size, vm_paddr_t pa, int mode)
1229 pt_entry_t *pte, attr;
1233 KASSERT((pa & L3_OFFSET) == 0,
1234 ("pmap_kenter: Invalid physical address"));
1235 KASSERT((sva & L3_OFFSET) == 0,
1236 ("pmap_kenter: Invalid virtual address"));
1237 KASSERT((size & PAGE_MASK) == 0,
1238 ("pmap_kenter: Mapping is not page-sized"));
1240 attr = ATTR_DEFAULT | ATTR_AP(ATTR_AP_RW) | ATTR_XN | ATTR_IDX(mode) |
1244 pde = pmap_pde(kernel_pmap, va, &lvl);
1245 KASSERT(pde != NULL,
1246 ("pmap_kenter: Invalid page entry, va: 0x%lx", va));
1247 KASSERT(lvl == 2, ("pmap_kenter: Invalid level %d", lvl));
1249 pte = pmap_l2_to_l3(pde, va);
1250 pmap_load_store(pte, (pa & ~L3_OFFSET) | attr);
1256 pmap_invalidate_range(kernel_pmap, sva, va);
1260 pmap_kenter_device(vm_offset_t sva, vm_size_t size, vm_paddr_t pa)
1263 pmap_kenter(sva, size, pa, VM_MEMATTR_DEVICE);
1267 * Remove a page from the kernel pagetables.
1270 pmap_kremove(vm_offset_t va)
1275 pte = pmap_pte(kernel_pmap, va, &lvl);
1276 KASSERT(pte != NULL, ("pmap_kremove: Invalid address"));
1277 KASSERT(lvl == 3, ("pmap_kremove: Invalid pte level %d", lvl));
1280 pmap_invalidate_page(kernel_pmap, va);
1284 pmap_kremove_device(vm_offset_t sva, vm_size_t size)
1290 KASSERT((sva & L3_OFFSET) == 0,
1291 ("pmap_kremove_device: Invalid virtual address"));
1292 KASSERT((size & PAGE_MASK) == 0,
1293 ("pmap_kremove_device: Mapping is not page-sized"));
1297 pte = pmap_pte(kernel_pmap, va, &lvl);
1298 KASSERT(pte != NULL, ("Invalid page table, va: 0x%lx", va));
1300 ("Invalid device pagetable level: %d != 3", lvl));
1306 pmap_invalidate_range(kernel_pmap, sva, va);
1310 * Used to map a range of physical addresses into kernel
1311 * virtual address space.
1313 * The value passed in '*virt' is a suggested virtual address for
1314 * the mapping. Architectures which can support a direct-mapped
1315 * physical to virtual region can return the appropriate address
1316 * within that region, leaving '*virt' unchanged. Other
1317 * architectures should map the pages starting at '*virt' and
1318 * update '*virt' with the first usable address after the mapped
1322 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
1324 return PHYS_TO_DMAP(start);
1329 * Add a list of wired pages to the kva
1330 * this routine is only used for temporary
1331 * kernel mappings that do not need to have
1332 * page modification or references recorded.
1333 * Note that old mappings are simply written
1334 * over. The page *must* be wired.
1335 * Note: SMP coherent. Uses a ranged shootdown IPI.
1338 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
1341 pt_entry_t *pte, pa;
1347 for (i = 0; i < count; i++) {
1348 pde = pmap_pde(kernel_pmap, va, &lvl);
1349 KASSERT(pde != NULL,
1350 ("pmap_qenter: Invalid page entry, va: 0x%lx", va));
1352 ("pmap_qenter: Invalid level %d", lvl));
1355 pa = VM_PAGE_TO_PHYS(m) | ATTR_DEFAULT | ATTR_AP(ATTR_AP_RW) |
1356 ATTR_XN | ATTR_IDX(m->md.pv_memattr) | L3_PAGE;
1357 pte = pmap_l2_to_l3(pde, va);
1358 pmap_load_store(pte, pa);
1362 pmap_invalidate_range(kernel_pmap, sva, va);
1366 * This routine tears out page mappings from the
1367 * kernel -- it is meant only for temporary mappings.
1370 pmap_qremove(vm_offset_t sva, int count)
1376 KASSERT(sva >= VM_MIN_KERNEL_ADDRESS, ("usermode va %lx", sva));
1379 while (count-- > 0) {
1380 pte = pmap_pte(kernel_pmap, va, &lvl);
1382 ("Invalid device pagetable level: %d != 3", lvl));
1389 pmap_invalidate_range(kernel_pmap, sva, va);
1392 /***************************************************
1393 * Page table page management routines.....
1394 ***************************************************/
1396 * Schedule the specified unused page table page to be freed. Specifically,
1397 * add the page to the specified list of pages that will be released to the
1398 * physical memory manager after the TLB has been updated.
1400 static __inline void
1401 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
1402 boolean_t set_PG_ZERO)
1406 m->flags |= PG_ZERO;
1408 m->flags &= ~PG_ZERO;
1409 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
1413 * Decrements a page table page's reference count, which is used to record the
1414 * number of valid page table entries within the page. If the reference count
1415 * drops to zero, then the page table page is unmapped. Returns TRUE if the
1416 * page table page was unmapped and FALSE otherwise.
1418 static inline boolean_t
1419 pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
1423 if (m->ref_count == 0) {
1424 _pmap_unwire_l3(pmap, va, m, free);
1431 _pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
1434 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1436 * unmap the page table page
1438 if (m->pindex >= (NUL2E + NUL1E)) {
1442 l0 = pmap_l0(pmap, va);
1444 } else if (m->pindex >= NUL2E) {
1448 l1 = pmap_l1(pmap, va);
1454 l2 = pmap_l2(pmap, va);
1457 pmap_resident_count_dec(pmap, 1);
1458 if (m->pindex < NUL2E) {
1459 /* We just released an l3, unhold the matching l2 */
1460 pd_entry_t *l1, tl1;
1463 l1 = pmap_l1(pmap, va);
1464 tl1 = pmap_load(l1);
1465 l2pg = PHYS_TO_VM_PAGE(tl1 & ~ATTR_MASK);
1466 pmap_unwire_l3(pmap, va, l2pg, free);
1467 } else if (m->pindex < (NUL2E + NUL1E)) {
1468 /* We just released an l2, unhold the matching l1 */
1469 pd_entry_t *l0, tl0;
1472 l0 = pmap_l0(pmap, va);
1473 tl0 = pmap_load(l0);
1474 l1pg = PHYS_TO_VM_PAGE(tl0 & ~ATTR_MASK);
1475 pmap_unwire_l3(pmap, va, l1pg, free);
1477 pmap_invalidate_page(pmap, va);
1480 * Put page on a list so that it is released after
1481 * *ALL* TLB shootdown is done
1483 pmap_add_delayed_free_list(m, free, TRUE);
1487 * After removing a page table entry, this routine is used to
1488 * conditionally free the page, and manage the reference count.
1491 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, pd_entry_t ptepde,
1492 struct spglist *free)
1496 if (va >= VM_MAXUSER_ADDRESS)
1498 KASSERT(ptepde != 0, ("pmap_unuse_pt: ptepde != 0"));
1499 mpte = PHYS_TO_VM_PAGE(ptepde & ~ATTR_MASK);
1500 return (pmap_unwire_l3(pmap, va, mpte, free));
1504 pmap_pinit0(pmap_t pmap)
1507 PMAP_LOCK_INIT(pmap);
1508 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats));
1509 pmap->pm_l0_paddr = READ_SPECIALREG(ttbr0_el1);
1510 pmap->pm_l0 = (pd_entry_t *)PHYS_TO_DMAP(pmap->pm_l0_paddr);
1511 pmap->pm_root.rt_root = 0;
1512 pmap->pm_cookie = COOKIE_FROM(ASID_RESERVED_FOR_PID_0, INT_MIN);
1514 PCPU_SET(curpmap, pmap);
1518 pmap_pinit(pmap_t pmap)
1523 * allocate the l0 page
1525 while ((l0pt = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
1526 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL)
1529 pmap->pm_l0_paddr = VM_PAGE_TO_PHYS(l0pt);
1530 pmap->pm_l0 = (pd_entry_t *)PHYS_TO_DMAP(pmap->pm_l0_paddr);
1532 if ((l0pt->flags & PG_ZERO) == 0)
1533 pagezero(pmap->pm_l0);
1535 pmap->pm_root.rt_root = 0;
1536 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats));
1537 pmap->pm_cookie = COOKIE_FROM(-1, INT_MAX);
1538 /* XXX Temporarily disable deferred ASID allocation. */
1539 pmap_alloc_asid(pmap);
1545 * This routine is called if the desired page table page does not exist.
1547 * If page table page allocation fails, this routine may sleep before
1548 * returning NULL. It sleeps only if a lock pointer was given.
1550 * Note: If a page allocation fails at page table level two or three,
1551 * one or two pages may be held during the wait, only to be released
1552 * afterwards. This conservative approach is easily argued to avoid
1556 _pmap_alloc_l3(pmap_t pmap, vm_pindex_t ptepindex, struct rwlock **lockp)
1558 vm_page_t m, l1pg, l2pg;
1560 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1563 * Allocate a page table page.
1565 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
1566 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
1567 if (lockp != NULL) {
1568 RELEASE_PV_LIST_LOCK(lockp);
1575 * Indicate the need to retry. While waiting, the page table
1576 * page may have been allocated.
1580 if ((m->flags & PG_ZERO) == 0)
1584 * Because of AArch64's weak memory consistency model, we must have a
1585 * barrier here to ensure that the stores for zeroing "m", whether by
1586 * pmap_zero_page() or an earlier function, are visible before adding
1587 * "m" to the page table. Otherwise, a page table walk by another
1588 * processor's MMU could see the mapping to "m" and a stale, non-zero
1594 * Map the pagetable page into the process address space, if
1595 * it isn't already there.
1598 if (ptepindex >= (NUL2E + NUL1E)) {
1600 vm_pindex_t l0index;
1602 l0index = ptepindex - (NUL2E + NUL1E);
1603 l0 = &pmap->pm_l0[l0index];
1604 pmap_store(l0, VM_PAGE_TO_PHYS(m) | L0_TABLE);
1605 } else if (ptepindex >= NUL2E) {
1606 vm_pindex_t l0index, l1index;
1607 pd_entry_t *l0, *l1;
1610 l1index = ptepindex - NUL2E;
1611 l0index = l1index >> L0_ENTRIES_SHIFT;
1613 l0 = &pmap->pm_l0[l0index];
1614 tl0 = pmap_load(l0);
1616 /* recurse for allocating page dir */
1617 if (_pmap_alloc_l3(pmap, NUL2E + NUL1E + l0index,
1619 vm_page_unwire_noq(m);
1620 vm_page_free_zero(m);
1624 l1pg = PHYS_TO_VM_PAGE(tl0 & ~ATTR_MASK);
1628 l1 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l0) & ~ATTR_MASK);
1629 l1 = &l1[ptepindex & Ln_ADDR_MASK];
1630 pmap_store(l1, VM_PAGE_TO_PHYS(m) | L1_TABLE);
1632 vm_pindex_t l0index, l1index;
1633 pd_entry_t *l0, *l1, *l2;
1634 pd_entry_t tl0, tl1;
1636 l1index = ptepindex >> Ln_ENTRIES_SHIFT;
1637 l0index = l1index >> L0_ENTRIES_SHIFT;
1639 l0 = &pmap->pm_l0[l0index];
1640 tl0 = pmap_load(l0);
1642 /* recurse for allocating page dir */
1643 if (_pmap_alloc_l3(pmap, NUL2E + l1index,
1645 vm_page_unwire_noq(m);
1646 vm_page_free_zero(m);
1649 tl0 = pmap_load(l0);
1650 l1 = (pd_entry_t *)PHYS_TO_DMAP(tl0 & ~ATTR_MASK);
1651 l1 = &l1[l1index & Ln_ADDR_MASK];
1653 l1 = (pd_entry_t *)PHYS_TO_DMAP(tl0 & ~ATTR_MASK);
1654 l1 = &l1[l1index & Ln_ADDR_MASK];
1655 tl1 = pmap_load(l1);
1657 /* recurse for allocating page dir */
1658 if (_pmap_alloc_l3(pmap, NUL2E + l1index,
1660 vm_page_unwire_noq(m);
1661 vm_page_free_zero(m);
1665 l2pg = PHYS_TO_VM_PAGE(tl1 & ~ATTR_MASK);
1670 l2 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l1) & ~ATTR_MASK);
1671 l2 = &l2[ptepindex & Ln_ADDR_MASK];
1672 pmap_store(l2, VM_PAGE_TO_PHYS(m) | L2_TABLE);
1675 pmap_resident_count_inc(pmap, 1);
1681 pmap_alloc_l2(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
1685 vm_pindex_t l2pindex;
1688 l1 = pmap_l1(pmap, va);
1689 if (l1 != NULL && (pmap_load(l1) & ATTR_DESCR_MASK) == L1_TABLE) {
1690 /* Add a reference to the L2 page. */
1691 l2pg = PHYS_TO_VM_PAGE(pmap_load(l1) & ~ATTR_MASK);
1694 /* Allocate a L2 page. */
1695 l2pindex = pmap_l2_pindex(va) >> Ln_ENTRIES_SHIFT;
1696 l2pg = _pmap_alloc_l3(pmap, NUL2E + l2pindex, lockp);
1697 if (l2pg == NULL && lockp != NULL)
1704 pmap_alloc_l3(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
1706 vm_pindex_t ptepindex;
1707 pd_entry_t *pde, tpde;
1715 * Calculate pagetable page index
1717 ptepindex = pmap_l2_pindex(va);
1720 * Get the page directory entry
1722 pde = pmap_pde(pmap, va, &lvl);
1725 * If the page table page is mapped, we just increment the hold count,
1726 * and activate it. If we get a level 2 pde it will point to a level 3
1734 pte = pmap_l0_to_l1(pde, va);
1735 KASSERT(pmap_load(pte) == 0,
1736 ("pmap_alloc_l3: TODO: l0 superpages"));
1741 pte = pmap_l1_to_l2(pde, va);
1742 KASSERT(pmap_load(pte) == 0,
1743 ("pmap_alloc_l3: TODO: l1 superpages"));
1747 tpde = pmap_load(pde);
1749 m = PHYS_TO_VM_PAGE(tpde & ~ATTR_MASK);
1755 panic("pmap_alloc_l3: Invalid level %d", lvl);
1759 * Here if the pte page isn't mapped, or if it has been deallocated.
1761 m = _pmap_alloc_l3(pmap, ptepindex, lockp);
1762 if (m == NULL && lockp != NULL)
1768 /***************************************************
1769 * Pmap allocation/deallocation routines.
1770 ***************************************************/
1773 * Release any resources held by the given physical map.
1774 * Called when a pmap initialized by pmap_pinit is being released.
1775 * Should only be called if the map contains no valid mappings.
1778 pmap_release(pmap_t pmap)
1783 KASSERT(pmap->pm_stats.resident_count == 0,
1784 ("pmap_release: pmap resident count %ld != 0",
1785 pmap->pm_stats.resident_count));
1786 KASSERT(vm_radix_is_empty(&pmap->pm_root),
1787 ("pmap_release: pmap has reserved page table page(s)"));
1789 mtx_lock_spin(&asid_set_mutex);
1790 if (COOKIE_TO_EPOCH(pmap->pm_cookie) == asid_epoch) {
1791 asid = COOKIE_TO_ASID(pmap->pm_cookie);
1792 KASSERT(asid >= ASID_FIRST_AVAILABLE && asid < asid_set_size,
1793 ("pmap_release: pmap cookie has out-of-range asid"));
1794 bit_clear(asid_set, asid);
1796 mtx_unlock_spin(&asid_set_mutex);
1798 m = PHYS_TO_VM_PAGE(pmap->pm_l0_paddr);
1799 vm_page_unwire_noq(m);
1800 vm_page_free_zero(m);
1804 kvm_size(SYSCTL_HANDLER_ARGS)
1806 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS;
1808 return sysctl_handle_long(oidp, &ksize, 0, req);
1810 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD,
1811 0, 0, kvm_size, "LU", "Size of KVM");
1814 kvm_free(SYSCTL_HANDLER_ARGS)
1816 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
1818 return sysctl_handle_long(oidp, &kfree, 0, req);
1820 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD,
1821 0, 0, kvm_free, "LU", "Amount of KVM free");
1824 * grow the number of kernel page table entries, if needed
1827 pmap_growkernel(vm_offset_t addr)
1831 pd_entry_t *l0, *l1, *l2;
1833 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
1835 addr = roundup2(addr, L2_SIZE);
1836 if (addr - 1 >= vm_map_max(kernel_map))
1837 addr = vm_map_max(kernel_map);
1838 while (kernel_vm_end < addr) {
1839 l0 = pmap_l0(kernel_pmap, kernel_vm_end);
1840 KASSERT(pmap_load(l0) != 0,
1841 ("pmap_growkernel: No level 0 kernel entry"));
1843 l1 = pmap_l0_to_l1(l0, kernel_vm_end);
1844 if (pmap_load(l1) == 0) {
1845 /* We need a new PDP entry */
1846 nkpg = vm_page_alloc(NULL, kernel_vm_end >> L1_SHIFT,
1847 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ |
1848 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
1850 panic("pmap_growkernel: no memory to grow kernel");
1851 if ((nkpg->flags & PG_ZERO) == 0)
1852 pmap_zero_page(nkpg);
1853 /* See the dmb() in _pmap_alloc_l3(). */
1855 paddr = VM_PAGE_TO_PHYS(nkpg);
1856 pmap_store(l1, paddr | L1_TABLE);
1857 continue; /* try again */
1859 l2 = pmap_l1_to_l2(l1, kernel_vm_end);
1860 if (pmap_load(l2) != 0) {
1861 kernel_vm_end = (kernel_vm_end + L2_SIZE) & ~L2_OFFSET;
1862 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
1863 kernel_vm_end = vm_map_max(kernel_map);
1869 nkpg = vm_page_alloc(NULL, kernel_vm_end >> L2_SHIFT,
1870 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
1873 panic("pmap_growkernel: no memory to grow kernel");
1874 if ((nkpg->flags & PG_ZERO) == 0)
1875 pmap_zero_page(nkpg);
1876 /* See the dmb() in _pmap_alloc_l3(). */
1878 paddr = VM_PAGE_TO_PHYS(nkpg);
1879 pmap_store(l2, paddr | L2_TABLE);
1881 kernel_vm_end = (kernel_vm_end + L2_SIZE) & ~L2_OFFSET;
1882 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
1883 kernel_vm_end = vm_map_max(kernel_map);
1890 /***************************************************
1891 * page management routines.
1892 ***************************************************/
1894 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
1895 CTASSERT(_NPCM == 3);
1896 CTASSERT(_NPCPV == 168);
1898 static __inline struct pv_chunk *
1899 pv_to_chunk(pv_entry_t pv)
1902 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
1905 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
1907 #define PC_FREE0 0xfffffffffffffffful
1908 #define PC_FREE1 0xfffffffffffffffful
1909 #define PC_FREE2 0x000000fffffffffful
1911 static const uint64_t pc_freemask[_NPCM] = { PC_FREE0, PC_FREE1, PC_FREE2 };
1915 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
1917 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
1918 "Current number of pv entry chunks");
1919 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
1920 "Current number of pv entry chunks allocated");
1921 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
1922 "Current number of pv entry chunks frees");
1923 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
1924 "Number of times tried to get a chunk page but failed.");
1926 static long pv_entry_frees, pv_entry_allocs, pv_entry_count;
1927 static int pv_entry_spare;
1929 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
1930 "Current number of pv entry frees");
1931 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
1932 "Current number of pv entry allocs");
1933 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
1934 "Current number of pv entries");
1935 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
1936 "Current number of spare pv entries");
1941 * We are in a serious low memory condition. Resort to
1942 * drastic measures to free some pages so we can allocate
1943 * another pv entry chunk.
1945 * Returns NULL if PV entries were reclaimed from the specified pmap.
1947 * We do not, however, unmap 2mpages because subsequent accesses will
1948 * allocate per-page pv entries until repromotion occurs, thereby
1949 * exacerbating the shortage of free pv entries.
1952 reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp)
1954 struct pv_chunk *pc, *pc_marker, *pc_marker_end;
1955 struct pv_chunk_header pc_marker_b, pc_marker_end_b;
1956 struct md_page *pvh;
1958 pmap_t next_pmap, pmap;
1959 pt_entry_t *pte, tpte;
1963 struct spglist free;
1965 int bit, field, freed, lvl;
1966 static int active_reclaims = 0;
1968 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
1969 KASSERT(lockp != NULL, ("reclaim_pv_chunk: lockp is NULL"));
1974 bzero(&pc_marker_b, sizeof(pc_marker_b));
1975 bzero(&pc_marker_end_b, sizeof(pc_marker_end_b));
1976 pc_marker = (struct pv_chunk *)&pc_marker_b;
1977 pc_marker_end = (struct pv_chunk *)&pc_marker_end_b;
1979 mtx_lock(&pv_chunks_mutex);
1981 TAILQ_INSERT_HEAD(&pv_chunks, pc_marker, pc_lru);
1982 TAILQ_INSERT_TAIL(&pv_chunks, pc_marker_end, pc_lru);
1983 while ((pc = TAILQ_NEXT(pc_marker, pc_lru)) != pc_marker_end &&
1984 SLIST_EMPTY(&free)) {
1985 next_pmap = pc->pc_pmap;
1986 if (next_pmap == NULL) {
1988 * The next chunk is a marker. However, it is
1989 * not our marker, so active_reclaims must be
1990 * > 1. Consequently, the next_chunk code
1991 * will not rotate the pv_chunks list.
1995 mtx_unlock(&pv_chunks_mutex);
1998 * A pv_chunk can only be removed from the pc_lru list
1999 * when both pv_chunks_mutex is owned and the
2000 * corresponding pmap is locked.
2002 if (pmap != next_pmap) {
2003 if (pmap != NULL && pmap != locked_pmap)
2006 /* Avoid deadlock and lock recursion. */
2007 if (pmap > locked_pmap) {
2008 RELEASE_PV_LIST_LOCK(lockp);
2010 mtx_lock(&pv_chunks_mutex);
2012 } else if (pmap != locked_pmap) {
2013 if (PMAP_TRYLOCK(pmap)) {
2014 mtx_lock(&pv_chunks_mutex);
2017 pmap = NULL; /* pmap is not locked */
2018 mtx_lock(&pv_chunks_mutex);
2019 pc = TAILQ_NEXT(pc_marker, pc_lru);
2021 pc->pc_pmap != next_pmap)
2029 * Destroy every non-wired, 4 KB page mapping in the chunk.
2032 for (field = 0; field < _NPCM; field++) {
2033 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
2034 inuse != 0; inuse &= ~(1UL << bit)) {
2035 bit = ffsl(inuse) - 1;
2036 pv = &pc->pc_pventry[field * 64 + bit];
2038 pde = pmap_pde(pmap, va, &lvl);
2041 pte = pmap_l2_to_l3(pde, va);
2042 tpte = pmap_load(pte);
2043 if ((tpte & ATTR_SW_WIRED) != 0)
2045 tpte = pmap_load_clear(pte);
2046 m = PHYS_TO_VM_PAGE(tpte & ~ATTR_MASK);
2047 if (pmap_pte_dirty(tpte))
2049 if ((tpte & ATTR_AF) != 0) {
2050 pmap_invalidate_page(pmap, va);
2051 vm_page_aflag_set(m, PGA_REFERENCED);
2053 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
2054 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
2056 if (TAILQ_EMPTY(&m->md.pv_list) &&
2057 (m->flags & PG_FICTITIOUS) == 0) {
2058 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2059 if (TAILQ_EMPTY(&pvh->pv_list)) {
2060 vm_page_aflag_clear(m,
2064 pc->pc_map[field] |= 1UL << bit;
2065 pmap_unuse_pt(pmap, va, pmap_load(pde), &free);
2070 mtx_lock(&pv_chunks_mutex);
2073 /* Every freed mapping is for a 4 KB page. */
2074 pmap_resident_count_dec(pmap, freed);
2075 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
2076 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
2077 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
2078 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2079 if (pc->pc_map[0] == PC_FREE0 && pc->pc_map[1] == PC_FREE1 &&
2080 pc->pc_map[2] == PC_FREE2) {
2081 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
2082 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
2083 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
2084 /* Entire chunk is free; return it. */
2085 m_pc = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
2086 dump_drop_page(m_pc->phys_addr);
2087 mtx_lock(&pv_chunks_mutex);
2088 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2091 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2092 mtx_lock(&pv_chunks_mutex);
2093 /* One freed pv entry in locked_pmap is sufficient. */
2094 if (pmap == locked_pmap)
2098 TAILQ_REMOVE(&pv_chunks, pc_marker, pc_lru);
2099 TAILQ_INSERT_AFTER(&pv_chunks, pc, pc_marker, pc_lru);
2100 if (active_reclaims == 1 && pmap != NULL) {
2102 * Rotate the pv chunks list so that we do not
2103 * scan the same pv chunks that could not be
2104 * freed (because they contained a wired
2105 * and/or superpage mapping) on every
2106 * invocation of reclaim_pv_chunk().
2108 while ((pc = TAILQ_FIRST(&pv_chunks)) != pc_marker) {
2109 MPASS(pc->pc_pmap != NULL);
2110 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2111 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
2115 TAILQ_REMOVE(&pv_chunks, pc_marker, pc_lru);
2116 TAILQ_REMOVE(&pv_chunks, pc_marker_end, pc_lru);
2118 mtx_unlock(&pv_chunks_mutex);
2119 if (pmap != NULL && pmap != locked_pmap)
2121 if (m_pc == NULL && !SLIST_EMPTY(&free)) {
2122 m_pc = SLIST_FIRST(&free);
2123 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
2124 /* Recycle a freed page table page. */
2125 m_pc->ref_count = 1;
2127 vm_page_free_pages_toq(&free, true);
2132 * free the pv_entry back to the free list
2135 free_pv_entry(pmap_t pmap, pv_entry_t pv)
2137 struct pv_chunk *pc;
2138 int idx, field, bit;
2140 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2141 PV_STAT(atomic_add_long(&pv_entry_frees, 1));
2142 PV_STAT(atomic_add_int(&pv_entry_spare, 1));
2143 PV_STAT(atomic_subtract_long(&pv_entry_count, 1));
2144 pc = pv_to_chunk(pv);
2145 idx = pv - &pc->pc_pventry[0];
2148 pc->pc_map[field] |= 1ul << bit;
2149 if (pc->pc_map[0] != PC_FREE0 || pc->pc_map[1] != PC_FREE1 ||
2150 pc->pc_map[2] != PC_FREE2) {
2151 /* 98% of the time, pc is already at the head of the list. */
2152 if (__predict_false(pc != TAILQ_FIRST(&pmap->pm_pvchunk))) {
2153 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2154 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2158 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2163 free_pv_chunk(struct pv_chunk *pc)
2167 mtx_lock(&pv_chunks_mutex);
2168 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2169 mtx_unlock(&pv_chunks_mutex);
2170 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
2171 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
2172 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
2173 /* entire chunk is free, return it */
2174 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
2175 dump_drop_page(m->phys_addr);
2176 vm_page_unwire_noq(m);
2181 * Returns a new PV entry, allocating a new PV chunk from the system when
2182 * needed. If this PV chunk allocation fails and a PV list lock pointer was
2183 * given, a PV chunk is reclaimed from an arbitrary pmap. Otherwise, NULL is
2186 * The given PV list lock may be released.
2189 get_pv_entry(pmap_t pmap, struct rwlock **lockp)
2193 struct pv_chunk *pc;
2196 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2197 PV_STAT(atomic_add_long(&pv_entry_allocs, 1));
2199 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2201 for (field = 0; field < _NPCM; field++) {
2202 if (pc->pc_map[field]) {
2203 bit = ffsl(pc->pc_map[field]) - 1;
2207 if (field < _NPCM) {
2208 pv = &pc->pc_pventry[field * 64 + bit];
2209 pc->pc_map[field] &= ~(1ul << bit);
2210 /* If this was the last item, move it to tail */
2211 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 &&
2212 pc->pc_map[2] == 0) {
2213 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2214 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc,
2217 PV_STAT(atomic_add_long(&pv_entry_count, 1));
2218 PV_STAT(atomic_subtract_int(&pv_entry_spare, 1));
2222 /* No free items, allocate another chunk */
2223 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
2226 if (lockp == NULL) {
2227 PV_STAT(pc_chunk_tryfail++);
2230 m = reclaim_pv_chunk(pmap, lockp);
2234 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
2235 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
2236 dump_add_page(m->phys_addr);
2237 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
2239 pc->pc_map[0] = PC_FREE0 & ~1ul; /* preallocated bit 0 */
2240 pc->pc_map[1] = PC_FREE1;
2241 pc->pc_map[2] = PC_FREE2;
2242 mtx_lock(&pv_chunks_mutex);
2243 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
2244 mtx_unlock(&pv_chunks_mutex);
2245 pv = &pc->pc_pventry[0];
2246 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2247 PV_STAT(atomic_add_long(&pv_entry_count, 1));
2248 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV - 1));
2253 * Ensure that the number of spare PV entries in the specified pmap meets or
2254 * exceeds the given count, "needed".
2256 * The given PV list lock may be released.
2259 reserve_pv_entries(pmap_t pmap, int needed, struct rwlock **lockp)
2261 struct pch new_tail;
2262 struct pv_chunk *pc;
2267 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2268 KASSERT(lockp != NULL, ("reserve_pv_entries: lockp is NULL"));
2271 * Newly allocated PV chunks must be stored in a private list until
2272 * the required number of PV chunks have been allocated. Otherwise,
2273 * reclaim_pv_chunk() could recycle one of these chunks. In
2274 * contrast, these chunks must be added to the pmap upon allocation.
2276 TAILQ_INIT(&new_tail);
2279 TAILQ_FOREACH(pc, &pmap->pm_pvchunk, pc_list) {
2280 bit_count((bitstr_t *)pc->pc_map, 0,
2281 sizeof(pc->pc_map) * NBBY, &free);
2285 if (avail >= needed)
2288 for (reclaimed = false; avail < needed; avail += _NPCPV) {
2289 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
2292 m = reclaim_pv_chunk(pmap, lockp);
2297 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
2298 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
2299 dump_add_page(m->phys_addr);
2300 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
2302 pc->pc_map[0] = PC_FREE0;
2303 pc->pc_map[1] = PC_FREE1;
2304 pc->pc_map[2] = PC_FREE2;
2305 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2306 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
2307 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV));
2310 * The reclaim might have freed a chunk from the current pmap.
2311 * If that chunk contained available entries, we need to
2312 * re-count the number of available entries.
2317 if (!TAILQ_EMPTY(&new_tail)) {
2318 mtx_lock(&pv_chunks_mutex);
2319 TAILQ_CONCAT(&pv_chunks, &new_tail, pc_lru);
2320 mtx_unlock(&pv_chunks_mutex);
2325 * First find and then remove the pv entry for the specified pmap and virtual
2326 * address from the specified pv list. Returns the pv entry if found and NULL
2327 * otherwise. This operation can be performed on pv lists for either 4KB or
2328 * 2MB page mappings.
2330 static __inline pv_entry_t
2331 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2335 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
2336 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
2337 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
2346 * After demotion from a 2MB page mapping to 512 4KB page mappings,
2347 * destroy the pv entry for the 2MB page mapping and reinstantiate the pv
2348 * entries for each of the 4KB page mappings.
2351 pmap_pv_demote_l2(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
2352 struct rwlock **lockp)
2354 struct md_page *pvh;
2355 struct pv_chunk *pc;
2357 vm_offset_t va_last;
2361 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2362 KASSERT((va & L2_OFFSET) == 0,
2363 ("pmap_pv_demote_l2: va is not 2mpage aligned"));
2364 KASSERT((pa & L2_OFFSET) == 0,
2365 ("pmap_pv_demote_l2: pa is not 2mpage aligned"));
2366 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
2369 * Transfer the 2mpage's pv entry for this mapping to the first
2370 * page's pv list. Once this transfer begins, the pv list lock
2371 * must not be released until the last pv entry is reinstantiated.
2373 pvh = pa_to_pvh(pa);
2374 pv = pmap_pvh_remove(pvh, pmap, va);
2375 KASSERT(pv != NULL, ("pmap_pv_demote_l2: pv not found"));
2376 m = PHYS_TO_VM_PAGE(pa);
2377 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2379 /* Instantiate the remaining Ln_ENTRIES - 1 pv entries. */
2380 PV_STAT(atomic_add_long(&pv_entry_allocs, Ln_ENTRIES - 1));
2381 va_last = va + L2_SIZE - PAGE_SIZE;
2383 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2384 KASSERT(pc->pc_map[0] != 0 || pc->pc_map[1] != 0 ||
2385 pc->pc_map[2] != 0, ("pmap_pv_demote_l2: missing spare"));
2386 for (field = 0; field < _NPCM; field++) {
2387 while (pc->pc_map[field]) {
2388 bit = ffsl(pc->pc_map[field]) - 1;
2389 pc->pc_map[field] &= ~(1ul << bit);
2390 pv = &pc->pc_pventry[field * 64 + bit];
2394 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2395 ("pmap_pv_demote_l2: page %p is not managed", m));
2396 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2402 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2403 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2406 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 && pc->pc_map[2] == 0) {
2407 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2408 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2410 PV_STAT(atomic_add_long(&pv_entry_count, Ln_ENTRIES - 1));
2411 PV_STAT(atomic_subtract_int(&pv_entry_spare, Ln_ENTRIES - 1));
2415 * First find and then destroy the pv entry for the specified pmap and virtual
2416 * address. This operation can be performed on pv lists for either 4KB or 2MB
2420 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2424 pv = pmap_pvh_remove(pvh, pmap, va);
2425 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
2426 free_pv_entry(pmap, pv);
2430 * Conditionally create the PV entry for a 4KB page mapping if the required
2431 * memory can be allocated without resorting to reclamation.
2434 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m,
2435 struct rwlock **lockp)
2439 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2440 /* Pass NULL instead of the lock pointer to disable reclamation. */
2441 if ((pv = get_pv_entry(pmap, NULL)) != NULL) {
2443 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
2444 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2452 * Create the PV entry for a 2MB page mapping. Always returns true unless the
2453 * flag PMAP_ENTER_NORECLAIM is specified. If that flag is specified, returns
2454 * false if the PV entry cannot be allocated without resorting to reclamation.
2457 pmap_pv_insert_l2(pmap_t pmap, vm_offset_t va, pd_entry_t l2e, u_int flags,
2458 struct rwlock **lockp)
2460 struct md_page *pvh;
2464 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2465 /* Pass NULL instead of the lock pointer to disable reclamation. */
2466 if ((pv = get_pv_entry(pmap, (flags & PMAP_ENTER_NORECLAIM) != 0 ?
2467 NULL : lockp)) == NULL)
2470 pa = l2e & ~ATTR_MASK;
2471 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
2472 pvh = pa_to_pvh(pa);
2473 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2479 pmap_remove_kernel_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t va)
2481 pt_entry_t newl2, oldl2;
2485 KASSERT(!VIRT_IN_DMAP(va), ("removing direct mapping of %#lx", va));
2486 KASSERT(pmap == kernel_pmap, ("pmap %p is not kernel_pmap", pmap));
2487 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2489 ml3 = pmap_remove_pt_page(pmap, va);
2491 panic("pmap_remove_kernel_l2: Missing pt page");
2493 ml3pa = VM_PAGE_TO_PHYS(ml3);
2494 newl2 = ml3pa | L2_TABLE;
2497 * If this page table page was unmapped by a promotion, then it
2498 * contains valid mappings. Zero it to invalidate those mappings.
2500 if (ml3->valid != 0)
2501 pagezero((void *)PHYS_TO_DMAP(ml3pa));
2504 * Demote the mapping. The caller must have already invalidated the
2505 * mapping (i.e., the "break" in break-before-make).
2507 oldl2 = pmap_load_store(l2, newl2);
2508 KASSERT(oldl2 == 0, ("%s: found existing mapping at %p: %#lx",
2509 __func__, l2, oldl2));
2513 * pmap_remove_l2: Do the things to unmap a level 2 superpage.
2516 pmap_remove_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t sva,
2517 pd_entry_t l1e, struct spglist *free, struct rwlock **lockp)
2519 struct md_page *pvh;
2521 vm_offset_t eva, va;
2524 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2525 KASSERT((sva & L2_OFFSET) == 0, ("pmap_remove_l2: sva is not aligned"));
2526 old_l2 = pmap_load_clear(l2);
2527 KASSERT((old_l2 & ATTR_DESCR_MASK) == L2_BLOCK,
2528 ("pmap_remove_l2: L2e %lx is not a block mapping", old_l2));
2531 * Since a promotion must break the 4KB page mappings before making
2532 * the 2MB page mapping, a pmap_invalidate_page() suffices.
2534 pmap_invalidate_page(pmap, sva);
2536 if (old_l2 & ATTR_SW_WIRED)
2537 pmap->pm_stats.wired_count -= L2_SIZE / PAGE_SIZE;
2538 pmap_resident_count_dec(pmap, L2_SIZE / PAGE_SIZE);
2539 if (old_l2 & ATTR_SW_MANAGED) {
2540 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, old_l2 & ~ATTR_MASK);
2541 pvh = pa_to_pvh(old_l2 & ~ATTR_MASK);
2542 pmap_pvh_free(pvh, pmap, sva);
2543 eva = sva + L2_SIZE;
2544 for (va = sva, m = PHYS_TO_VM_PAGE(old_l2 & ~ATTR_MASK);
2545 va < eva; va += PAGE_SIZE, m++) {
2546 if (pmap_pte_dirty(old_l2))
2548 if (old_l2 & ATTR_AF)
2549 vm_page_aflag_set(m, PGA_REFERENCED);
2550 if (TAILQ_EMPTY(&m->md.pv_list) &&
2551 TAILQ_EMPTY(&pvh->pv_list))
2552 vm_page_aflag_clear(m, PGA_WRITEABLE);
2555 if (pmap == kernel_pmap) {
2556 pmap_remove_kernel_l2(pmap, l2, sva);
2558 ml3 = pmap_remove_pt_page(pmap, sva);
2560 KASSERT(ml3->valid == VM_PAGE_BITS_ALL,
2561 ("pmap_remove_l2: l3 page not promoted"));
2562 pmap_resident_count_dec(pmap, 1);
2563 KASSERT(ml3->ref_count == NL3PG,
2564 ("pmap_remove_l2: l3 page ref count error"));
2566 pmap_add_delayed_free_list(ml3, free, FALSE);
2569 return (pmap_unuse_pt(pmap, sva, l1e, free));
2573 * pmap_remove_l3: do the things to unmap a page in a process
2576 pmap_remove_l3(pmap_t pmap, pt_entry_t *l3, vm_offset_t va,
2577 pd_entry_t l2e, struct spglist *free, struct rwlock **lockp)
2579 struct md_page *pvh;
2583 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2584 old_l3 = pmap_load_clear(l3);
2585 pmap_invalidate_page(pmap, va);
2586 if (old_l3 & ATTR_SW_WIRED)
2587 pmap->pm_stats.wired_count -= 1;
2588 pmap_resident_count_dec(pmap, 1);
2589 if (old_l3 & ATTR_SW_MANAGED) {
2590 m = PHYS_TO_VM_PAGE(old_l3 & ~ATTR_MASK);
2591 if (pmap_pte_dirty(old_l3))
2593 if (old_l3 & ATTR_AF)
2594 vm_page_aflag_set(m, PGA_REFERENCED);
2595 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
2596 pmap_pvh_free(&m->md, pmap, va);
2597 if (TAILQ_EMPTY(&m->md.pv_list) &&
2598 (m->flags & PG_FICTITIOUS) == 0) {
2599 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2600 if (TAILQ_EMPTY(&pvh->pv_list))
2601 vm_page_aflag_clear(m, PGA_WRITEABLE);
2604 return (pmap_unuse_pt(pmap, va, l2e, free));
2608 * Remove the specified range of addresses from the L3 page table that is
2609 * identified by the given L2 entry.
2612 pmap_remove_l3_range(pmap_t pmap, pd_entry_t l2e, vm_offset_t sva,
2613 vm_offset_t eva, struct spglist *free, struct rwlock **lockp)
2615 struct md_page *pvh;
2616 struct rwlock *new_lock;
2617 pt_entry_t *l3, old_l3;
2621 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2622 KASSERT(rounddown2(sva, L2_SIZE) + L2_SIZE == roundup2(eva, L2_SIZE),
2623 ("pmap_remove_l3_range: range crosses an L3 page table boundary"));
2625 for (l3 = pmap_l2_to_l3(&l2e, sva); sva != eva; l3++, sva += L3_SIZE) {
2626 if (!pmap_l3_valid(pmap_load(l3))) {
2628 pmap_invalidate_range(pmap, va, sva);
2633 old_l3 = pmap_load_clear(l3);
2634 if ((old_l3 & ATTR_SW_WIRED) != 0)
2635 pmap->pm_stats.wired_count--;
2636 pmap_resident_count_dec(pmap, 1);
2637 if ((old_l3 & ATTR_SW_MANAGED) != 0) {
2638 m = PHYS_TO_VM_PAGE(old_l3 & ~ATTR_MASK);
2639 if (pmap_pte_dirty(old_l3))
2641 if ((old_l3 & ATTR_AF) != 0)
2642 vm_page_aflag_set(m, PGA_REFERENCED);
2643 new_lock = PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m));
2644 if (new_lock != *lockp) {
2645 if (*lockp != NULL) {
2647 * Pending TLB invalidations must be
2648 * performed before the PV list lock is
2649 * released. Otherwise, a concurrent
2650 * pmap_remove_all() on a physical page
2651 * could return while a stale TLB entry
2652 * still provides access to that page.
2655 pmap_invalidate_range(pmap, va,
2664 pmap_pvh_free(&m->md, pmap, sva);
2665 if (TAILQ_EMPTY(&m->md.pv_list) &&
2666 (m->flags & PG_FICTITIOUS) == 0) {
2667 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2668 if (TAILQ_EMPTY(&pvh->pv_list))
2669 vm_page_aflag_clear(m, PGA_WRITEABLE);
2674 if (pmap_unuse_pt(pmap, sva, l2e, free)) {
2680 pmap_invalidate_range(pmap, va, sva);
2684 * Remove the given range of addresses from the specified map.
2686 * It is assumed that the start and end are properly
2687 * rounded to the page size.
2690 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2692 struct rwlock *lock;
2693 vm_offset_t va_next;
2694 pd_entry_t *l0, *l1, *l2;
2695 pt_entry_t l3_paddr;
2696 struct spglist free;
2699 * Perform an unsynchronized read. This is, however, safe.
2701 if (pmap->pm_stats.resident_count == 0)
2709 for (; sva < eva; sva = va_next) {
2711 if (pmap->pm_stats.resident_count == 0)
2714 l0 = pmap_l0(pmap, sva);
2715 if (pmap_load(l0) == 0) {
2716 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
2722 l1 = pmap_l0_to_l1(l0, sva);
2723 if (pmap_load(l1) == 0) {
2724 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
2731 * Calculate index for next page table.
2733 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
2737 l2 = pmap_l1_to_l2(l1, sva);
2741 l3_paddr = pmap_load(l2);
2743 if ((l3_paddr & ATTR_DESCR_MASK) == L2_BLOCK) {
2744 if (sva + L2_SIZE == va_next && eva >= va_next) {
2745 pmap_remove_l2(pmap, l2, sva, pmap_load(l1),
2748 } else if (pmap_demote_l2_locked(pmap, l2, sva,
2751 l3_paddr = pmap_load(l2);
2755 * Weed out invalid mappings.
2757 if ((l3_paddr & ATTR_DESCR_MASK) != L2_TABLE)
2761 * Limit our scan to either the end of the va represented
2762 * by the current page table page, or to the end of the
2763 * range being removed.
2768 pmap_remove_l3_range(pmap, l3_paddr, sva, va_next, &free,
2774 vm_page_free_pages_toq(&free, true);
2778 * Routine: pmap_remove_all
2780 * Removes this physical page from
2781 * all physical maps in which it resides.
2782 * Reflects back modify bits to the pager.
2785 * Original versions of this routine were very
2786 * inefficient because they iteratively called
2787 * pmap_remove (slow...)
2791 pmap_remove_all(vm_page_t m)
2793 struct md_page *pvh;
2796 struct rwlock *lock;
2797 pd_entry_t *pde, tpde;
2798 pt_entry_t *pte, tpte;
2800 struct spglist free;
2801 int lvl, pvh_gen, md_gen;
2803 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2804 ("pmap_remove_all: page %p is not managed", m));
2806 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
2807 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
2808 pa_to_pvh(VM_PAGE_TO_PHYS(m));
2811 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
2813 if (!PMAP_TRYLOCK(pmap)) {
2814 pvh_gen = pvh->pv_gen;
2818 if (pvh_gen != pvh->pv_gen) {
2825 pte = pmap_pte(pmap, va, &lvl);
2826 KASSERT(pte != NULL,
2827 ("pmap_remove_all: no page table entry found"));
2829 ("pmap_remove_all: invalid pte level %d", lvl));
2831 pmap_demote_l2_locked(pmap, pte, va, &lock);
2834 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
2836 if (!PMAP_TRYLOCK(pmap)) {
2837 pvh_gen = pvh->pv_gen;
2838 md_gen = m->md.pv_gen;
2842 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
2848 pmap_resident_count_dec(pmap, 1);
2850 pde = pmap_pde(pmap, pv->pv_va, &lvl);
2851 KASSERT(pde != NULL,
2852 ("pmap_remove_all: no page directory entry found"));
2854 ("pmap_remove_all: invalid pde level %d", lvl));
2855 tpde = pmap_load(pde);
2857 pte = pmap_l2_to_l3(pde, pv->pv_va);
2858 tpte = pmap_load_clear(pte);
2859 if (tpte & ATTR_SW_WIRED)
2860 pmap->pm_stats.wired_count--;
2861 if ((tpte & ATTR_AF) != 0) {
2862 pmap_invalidate_page(pmap, pv->pv_va);
2863 vm_page_aflag_set(m, PGA_REFERENCED);
2867 * Update the vm_page_t clean and reference bits.
2869 if (pmap_pte_dirty(tpte))
2871 pmap_unuse_pt(pmap, pv->pv_va, tpde, &free);
2872 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
2874 free_pv_entry(pmap, pv);
2877 vm_page_aflag_clear(m, PGA_WRITEABLE);
2879 vm_page_free_pages_toq(&free, true);
2883 * pmap_protect_l2: do the things to protect a 2MB page in a pmap
2886 pmap_protect_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t sva, pt_entry_t mask,
2892 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2893 KASSERT((sva & L2_OFFSET) == 0,
2894 ("pmap_protect_l2: sva is not 2mpage aligned"));
2895 old_l2 = pmap_load(l2);
2896 KASSERT((old_l2 & ATTR_DESCR_MASK) == L2_BLOCK,
2897 ("pmap_protect_l2: L2e %lx is not a block mapping", old_l2));
2900 * Return if the L2 entry already has the desired access restrictions
2904 if ((old_l2 & mask) == nbits)
2908 * When a dirty read/write superpage mapping is write protected,
2909 * update the dirty field of each of the superpage's constituent 4KB
2912 if ((old_l2 & ATTR_SW_MANAGED) != 0 &&
2913 (nbits & ATTR_AP(ATTR_AP_RO)) != 0 && pmap_pte_dirty(old_l2)) {
2914 m = PHYS_TO_VM_PAGE(old_l2 & ~ATTR_MASK);
2915 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
2919 if (!atomic_fcmpset_64(l2, &old_l2, (old_l2 & ~mask) | nbits))
2923 * Since a promotion must break the 4KB page mappings before making
2924 * the 2MB page mapping, a pmap_invalidate_page() suffices.
2926 pmap_invalidate_page(pmap, sva);
2930 * Set the physical protection on the
2931 * specified range of this map as requested.
2934 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
2936 vm_offset_t va, va_next;
2937 pd_entry_t *l0, *l1, *l2;
2938 pt_entry_t *l3p, l3, mask, nbits;
2940 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
2941 if (prot == VM_PROT_NONE) {
2942 pmap_remove(pmap, sva, eva);
2947 if ((prot & VM_PROT_WRITE) == 0) {
2948 mask |= ATTR_AP_RW_BIT | ATTR_SW_DBM;
2949 nbits |= ATTR_AP(ATTR_AP_RO);
2951 if ((prot & VM_PROT_EXECUTE) == 0) {
2959 for (; sva < eva; sva = va_next) {
2961 l0 = pmap_l0(pmap, sva);
2962 if (pmap_load(l0) == 0) {
2963 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
2969 l1 = pmap_l0_to_l1(l0, sva);
2970 if (pmap_load(l1) == 0) {
2971 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
2977 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
2981 l2 = pmap_l1_to_l2(l1, sva);
2982 if (pmap_load(l2) == 0)
2985 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK) {
2986 if (sva + L2_SIZE == va_next && eva >= va_next) {
2987 pmap_protect_l2(pmap, l2, sva, mask, nbits);
2989 } else if (pmap_demote_l2(pmap, l2, sva) == NULL)
2992 KASSERT((pmap_load(l2) & ATTR_DESCR_MASK) == L2_TABLE,
2993 ("pmap_protect: Invalid L2 entry after demotion"));
2999 for (l3p = pmap_l2_to_l3(l2, sva); sva != va_next; l3p++,
3001 l3 = pmap_load(l3p);
3004 * Go to the next L3 entry if the current one is
3005 * invalid or already has the desired access
3006 * restrictions in place. (The latter case occurs
3007 * frequently. For example, in a "buildworld"
3008 * workload, almost 1 out of 4 L3 entries already
3009 * have the desired restrictions.)
3011 if (!pmap_l3_valid(l3) || (l3 & mask) == nbits) {
3012 if (va != va_next) {
3013 pmap_invalidate_range(pmap, va, sva);
3020 * When a dirty read/write mapping is write protected,
3021 * update the page's dirty field.
3023 if ((l3 & ATTR_SW_MANAGED) != 0 &&
3024 (nbits & ATTR_AP(ATTR_AP_RO)) != 0 &&
3026 vm_page_dirty(PHYS_TO_VM_PAGE(l3 & ~ATTR_MASK));
3028 if (!atomic_fcmpset_64(l3p, &l3, (l3 & ~mask) | nbits))
3034 pmap_invalidate_range(pmap, va, sva);
3040 * Inserts the specified page table page into the specified pmap's collection
3041 * of idle page table pages. Each of a pmap's page table pages is responsible
3042 * for mapping a distinct range of virtual addresses. The pmap's collection is
3043 * ordered by this virtual address range.
3045 * If "promoted" is false, then the page table page "mpte" must be zero filled.
3048 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte, bool promoted)
3051 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3052 mpte->valid = promoted ? VM_PAGE_BITS_ALL : 0;
3053 return (vm_radix_insert(&pmap->pm_root, mpte));
3057 * Removes the page table page mapping the specified virtual address from the
3058 * specified pmap's collection of idle page table pages, and returns it.
3059 * Otherwise, returns NULL if there is no page table page corresponding to the
3060 * specified virtual address.
3062 static __inline vm_page_t
3063 pmap_remove_pt_page(pmap_t pmap, vm_offset_t va)
3066 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3067 return (vm_radix_remove(&pmap->pm_root, pmap_l2_pindex(va)));
3071 * Performs a break-before-make update of a pmap entry. This is needed when
3072 * either promoting or demoting pages to ensure the TLB doesn't get into an
3073 * inconsistent state.
3076 pmap_update_entry(pmap_t pmap, pd_entry_t *pte, pd_entry_t newpte,
3077 vm_offset_t va, vm_size_t size)
3081 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3084 * Ensure we don't get switched out with the page table in an
3085 * inconsistent state. We also need to ensure no interrupts fire
3086 * as they may make use of an address we are about to invalidate.
3088 intr = intr_disable();
3091 * Clear the old mapping's valid bit, but leave the rest of the entry
3092 * unchanged, so that a lockless, concurrent pmap_kextract() can still
3093 * lookup the physical address.
3095 pmap_clear_bits(pte, ATTR_DESCR_VALID);
3096 pmap_invalidate_range(pmap, va, va + size);
3098 /* Create the new mapping */
3099 pmap_store(pte, newpte);
3105 #if VM_NRESERVLEVEL > 0
3107 * After promotion from 512 4KB page mappings to a single 2MB page mapping,
3108 * replace the many pv entries for the 4KB page mappings by a single pv entry
3109 * for the 2MB page mapping.
3112 pmap_pv_promote_l2(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
3113 struct rwlock **lockp)
3115 struct md_page *pvh;
3117 vm_offset_t va_last;
3120 KASSERT((pa & L2_OFFSET) == 0,
3121 ("pmap_pv_promote_l2: pa is not 2mpage aligned"));
3122 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
3125 * Transfer the first page's pv entry for this mapping to the 2mpage's
3126 * pv list. Aside from avoiding the cost of a call to get_pv_entry(),
3127 * a transfer avoids the possibility that get_pv_entry() calls
3128 * reclaim_pv_chunk() and that reclaim_pv_chunk() removes one of the
3129 * mappings that is being promoted.
3131 m = PHYS_TO_VM_PAGE(pa);
3132 va = va & ~L2_OFFSET;
3133 pv = pmap_pvh_remove(&m->md, pmap, va);
3134 KASSERT(pv != NULL, ("pmap_pv_promote_l2: pv not found"));
3135 pvh = pa_to_pvh(pa);
3136 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
3138 /* Free the remaining NPTEPG - 1 pv entries. */
3139 va_last = va + L2_SIZE - PAGE_SIZE;
3143 pmap_pvh_free(&m->md, pmap, va);
3144 } while (va < va_last);
3148 * Tries to promote the 512, contiguous 4KB page mappings that are within a
3149 * single level 2 table entry to a single 2MB page mapping. For promotion
3150 * to occur, two conditions must be met: (1) the 4KB page mappings must map
3151 * aligned, contiguous physical memory and (2) the 4KB page mappings must have
3152 * identical characteristics.
3155 pmap_promote_l2(pmap_t pmap, pd_entry_t *l2, vm_offset_t va,
3156 struct rwlock **lockp)
3158 pt_entry_t *firstl3, *l3, newl2, oldl3, pa;
3162 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3164 sva = va & ~L2_OFFSET;
3165 firstl3 = pmap_l2_to_l3(l2, sva);
3166 newl2 = pmap_load(firstl3);
3169 if (((newl2 & (~ATTR_MASK | ATTR_AF)) & L2_OFFSET) != ATTR_AF) {
3170 atomic_add_long(&pmap_l2_p_failures, 1);
3171 CTR2(KTR_PMAP, "pmap_promote_l2: failure for va %#lx"
3172 " in pmap %p", va, pmap);
3176 if ((newl2 & (ATTR_AP_RW_BIT | ATTR_SW_DBM)) ==
3177 (ATTR_AP(ATTR_AP_RO) | ATTR_SW_DBM)) {
3178 if (!atomic_fcmpset_64(l2, &newl2, newl2 & ~ATTR_SW_DBM))
3180 newl2 &= ~ATTR_SW_DBM;
3183 pa = newl2 + L2_SIZE - PAGE_SIZE;
3184 for (l3 = firstl3 + NL3PG - 1; l3 > firstl3; l3--) {
3185 oldl3 = pmap_load(l3);
3187 if ((oldl3 & (ATTR_AP_RW_BIT | ATTR_SW_DBM)) ==
3188 (ATTR_AP(ATTR_AP_RO) | ATTR_SW_DBM)) {
3189 if (!atomic_fcmpset_64(l3, &oldl3, oldl3 &
3192 oldl3 &= ~ATTR_SW_DBM;
3195 atomic_add_long(&pmap_l2_p_failures, 1);
3196 CTR2(KTR_PMAP, "pmap_promote_l2: failure for va %#lx"
3197 " in pmap %p", va, pmap);
3204 * Save the page table page in its current state until the L2
3205 * mapping the superpage is demoted by pmap_demote_l2() or
3206 * destroyed by pmap_remove_l3().
3208 mpte = PHYS_TO_VM_PAGE(pmap_load(l2) & ~ATTR_MASK);
3209 KASSERT(mpte >= vm_page_array &&
3210 mpte < &vm_page_array[vm_page_array_size],
3211 ("pmap_promote_l2: page table page is out of range"));
3212 KASSERT(mpte->pindex == pmap_l2_pindex(va),
3213 ("pmap_promote_l2: page table page's pindex is wrong"));
3214 if (pmap_insert_pt_page(pmap, mpte, true)) {
3215 atomic_add_long(&pmap_l2_p_failures, 1);
3217 "pmap_promote_l2: failure for va %#lx in pmap %p", va,
3222 if ((newl2 & ATTR_SW_MANAGED) != 0)
3223 pmap_pv_promote_l2(pmap, va, newl2 & ~ATTR_MASK, lockp);
3225 newl2 &= ~ATTR_DESCR_MASK;
3228 pmap_update_entry(pmap, l2, newl2, sva, L2_SIZE);
3230 atomic_add_long(&pmap_l2_promotions, 1);
3231 CTR2(KTR_PMAP, "pmap_promote_l2: success for va %#lx in pmap %p", va,
3234 #endif /* VM_NRESERVLEVEL > 0 */
3237 * Insert the given physical page (p) at
3238 * the specified virtual address (v) in the
3239 * target physical map with the protection requested.
3241 * If specified, the page will be wired down, meaning
3242 * that the related pte can not be reclaimed.
3244 * NB: This is the only routine which MAY NOT lazy-evaluate
3245 * or lose information. That is, this routine must actually
3246 * insert this page into the given map NOW.
3249 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
3250 u_int flags, int8_t psind)
3252 struct rwlock *lock;
3254 pt_entry_t new_l3, orig_l3;
3255 pt_entry_t *l2, *l3;
3262 va = trunc_page(va);
3263 if ((m->oflags & VPO_UNMANAGED) == 0)
3264 VM_PAGE_OBJECT_BUSY_ASSERT(m);
3265 pa = VM_PAGE_TO_PHYS(m);
3266 new_l3 = (pt_entry_t)(pa | ATTR_DEFAULT | ATTR_IDX(m->md.pv_memattr) |
3268 if ((prot & VM_PROT_WRITE) == 0)
3269 new_l3 |= ATTR_AP(ATTR_AP_RO);
3270 if ((prot & VM_PROT_EXECUTE) == 0 ||
3271 m->md.pv_memattr == VM_MEMATTR_DEVICE)
3273 if ((flags & PMAP_ENTER_WIRED) != 0)
3274 new_l3 |= ATTR_SW_WIRED;
3275 if (va < VM_MAXUSER_ADDRESS)
3276 new_l3 |= ATTR_AP(ATTR_AP_USER) | ATTR_PXN;
3279 if (pmap != kernel_pmap)
3281 if ((m->oflags & VPO_UNMANAGED) == 0) {
3282 new_l3 |= ATTR_SW_MANAGED;
3283 if ((prot & VM_PROT_WRITE) != 0) {
3284 new_l3 |= ATTR_SW_DBM;
3285 if ((flags & VM_PROT_WRITE) == 0)
3286 new_l3 |= ATTR_AP(ATTR_AP_RO);
3290 CTR2(KTR_PMAP, "pmap_enter: %.16lx -> %.16lx", va, pa);
3295 /* Assert the required virtual and physical alignment. */
3296 KASSERT((va & L2_OFFSET) == 0, ("pmap_enter: va unaligned"));
3297 KASSERT(m->psind > 0, ("pmap_enter: m->psind < psind"));
3298 rv = pmap_enter_l2(pmap, va, (new_l3 & ~L3_PAGE) | L2_BLOCK,
3305 * In the case that a page table page is not
3306 * resident, we are creating it here.
3309 pde = pmap_pde(pmap, va, &lvl);
3310 if (pde != NULL && lvl == 2) {
3311 l3 = pmap_l2_to_l3(pde, va);
3312 if (va < VM_MAXUSER_ADDRESS && mpte == NULL) {
3313 mpte = PHYS_TO_VM_PAGE(pmap_load(pde) & ~ATTR_MASK);
3317 } else if (pde != NULL && lvl == 1) {
3318 l2 = pmap_l1_to_l2(pde, va);
3319 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK &&
3320 (l3 = pmap_demote_l2_locked(pmap, l2, va, &lock)) != NULL) {
3321 l3 = &l3[pmap_l3_index(va)];
3322 if (va < VM_MAXUSER_ADDRESS) {
3323 mpte = PHYS_TO_VM_PAGE(
3324 pmap_load(l2) & ~ATTR_MASK);
3329 /* We need to allocate an L3 table. */
3331 if (va < VM_MAXUSER_ADDRESS) {
3332 nosleep = (flags & PMAP_ENTER_NOSLEEP) != 0;
3335 * We use _pmap_alloc_l3() instead of pmap_alloc_l3() in order
3336 * to handle the possibility that a superpage mapping for "va"
3337 * was created while we slept.
3339 mpte = _pmap_alloc_l3(pmap, pmap_l2_pindex(va),
3340 nosleep ? NULL : &lock);
3341 if (mpte == NULL && nosleep) {
3342 CTR0(KTR_PMAP, "pmap_enter: mpte == NULL");
3343 rv = KERN_RESOURCE_SHORTAGE;
3348 panic("pmap_enter: missing L3 table for kernel va %#lx", va);
3351 orig_l3 = pmap_load(l3);
3352 opa = orig_l3 & ~ATTR_MASK;
3356 * Is the specified virtual address already mapped?
3358 if (pmap_l3_valid(orig_l3)) {
3360 * Wiring change, just update stats. We don't worry about
3361 * wiring PT pages as they remain resident as long as there
3362 * are valid mappings in them. Hence, if a user page is wired,
3363 * the PT page will be also.
3365 if ((flags & PMAP_ENTER_WIRED) != 0 &&
3366 (orig_l3 & ATTR_SW_WIRED) == 0)
3367 pmap->pm_stats.wired_count++;
3368 else if ((flags & PMAP_ENTER_WIRED) == 0 &&
3369 (orig_l3 & ATTR_SW_WIRED) != 0)
3370 pmap->pm_stats.wired_count--;
3373 * Remove the extra PT page reference.
3377 KASSERT(mpte->ref_count > 0,
3378 ("pmap_enter: missing reference to page table page,"
3383 * Has the physical page changed?
3387 * No, might be a protection or wiring change.
3389 if ((orig_l3 & ATTR_SW_MANAGED) != 0 &&
3390 (new_l3 & ATTR_SW_DBM) != 0)
3391 vm_page_aflag_set(m, PGA_WRITEABLE);
3396 * The physical page has changed. Temporarily invalidate
3399 orig_l3 = pmap_load_clear(l3);
3400 KASSERT((orig_l3 & ~ATTR_MASK) == opa,
3401 ("pmap_enter: unexpected pa update for %#lx", va));
3402 if ((orig_l3 & ATTR_SW_MANAGED) != 0) {
3403 om = PHYS_TO_VM_PAGE(opa);
3406 * The pmap lock is sufficient to synchronize with
3407 * concurrent calls to pmap_page_test_mappings() and
3408 * pmap_ts_referenced().
3410 if (pmap_pte_dirty(orig_l3))
3412 if ((orig_l3 & ATTR_AF) != 0)
3413 vm_page_aflag_set(om, PGA_REFERENCED);
3414 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, opa);
3415 pv = pmap_pvh_remove(&om->md, pmap, va);
3416 if ((m->oflags & VPO_UNMANAGED) != 0)
3417 free_pv_entry(pmap, pv);
3418 if ((om->a.flags & PGA_WRITEABLE) != 0 &&
3419 TAILQ_EMPTY(&om->md.pv_list) &&
3420 ((om->flags & PG_FICTITIOUS) != 0 ||
3421 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
3422 vm_page_aflag_clear(om, PGA_WRITEABLE);
3424 pmap_invalidate_page(pmap, va);
3428 * Increment the counters.
3430 if ((new_l3 & ATTR_SW_WIRED) != 0)
3431 pmap->pm_stats.wired_count++;
3432 pmap_resident_count_inc(pmap, 1);
3435 * Enter on the PV list if part of our managed memory.
3437 if ((m->oflags & VPO_UNMANAGED) == 0) {
3439 pv = get_pv_entry(pmap, &lock);
3442 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, pa);
3443 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3445 if ((new_l3 & ATTR_SW_DBM) != 0)
3446 vm_page_aflag_set(m, PGA_WRITEABLE);
3451 * Sync icache if exec permission and attribute VM_MEMATTR_WRITE_BACK
3452 * is set. Do it now, before the mapping is stored and made
3453 * valid for hardware table walk. If done later, then other can
3454 * access this page before caches are properly synced.
3455 * Don't do it for kernel memory which is mapped with exec
3456 * permission even if the memory isn't going to hold executable
3457 * code. The only time when icache sync is needed is after
3458 * kernel module is loaded and the relocation info is processed.
3459 * And it's done in elf_cpu_load_file().
3461 if ((prot & VM_PROT_EXECUTE) && pmap != kernel_pmap &&
3462 m->md.pv_memattr == VM_MEMATTR_WRITE_BACK &&
3463 (opa != pa || (orig_l3 & ATTR_XN)))
3464 cpu_icache_sync_range(PHYS_TO_DMAP(pa), PAGE_SIZE);
3467 * Update the L3 entry
3469 if (pmap_l3_valid(orig_l3)) {
3470 KASSERT(opa == pa, ("pmap_enter: invalid update"));
3471 if ((orig_l3 & ~ATTR_AF) != (new_l3 & ~ATTR_AF)) {
3472 /* same PA, different attributes */
3473 /* XXXMJ need to reload orig_l3 for hardware DBM. */
3474 pmap_load_store(l3, new_l3);
3475 pmap_invalidate_page(pmap, va);
3476 if ((orig_l3 & ATTR_SW_MANAGED) != 0 &&
3477 pmap_pte_dirty(orig_l3))
3482 * This can happens if multiple threads simultaneously
3483 * access not yet mapped page. This bad for performance
3484 * since this can cause full demotion-NOP-promotion
3486 * Another possible reasons are:
3487 * - VM and pmap memory layout are diverged
3488 * - tlb flush is missing somewhere and CPU doesn't see
3491 CTR4(KTR_PMAP, "%s: already mapped page - "
3492 "pmap %p va 0x%#lx pte 0x%lx",
3493 __func__, pmap, va, new_l3);
3497 pmap_store(l3, new_l3);
3501 #if VM_NRESERVLEVEL > 0
3502 if ((mpte == NULL || mpte->ref_count == NL3PG) &&
3503 pmap_ps_enabled(pmap) &&
3504 (m->flags & PG_FICTITIOUS) == 0 &&
3505 vm_reserv_level_iffullpop(m) == 0) {
3506 pmap_promote_l2(pmap, pde, va, &lock);
3519 * Tries to create a read- and/or execute-only 2MB page mapping. Returns true
3520 * if successful. Returns false if (1) a page table page cannot be allocated
3521 * without sleeping, (2) a mapping already exists at the specified virtual
3522 * address, or (3) a PV entry cannot be allocated without reclaiming another
3526 pmap_enter_2mpage(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
3527 struct rwlock **lockp)
3531 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3533 new_l2 = (pd_entry_t)(VM_PAGE_TO_PHYS(m) | ATTR_DEFAULT |
3534 ATTR_IDX(m->md.pv_memattr) | ATTR_AP(ATTR_AP_RO) | L2_BLOCK);
3535 if ((m->oflags & VPO_UNMANAGED) == 0) {
3536 new_l2 |= ATTR_SW_MANAGED;
3539 if ((prot & VM_PROT_EXECUTE) == 0 ||
3540 m->md.pv_memattr == VM_MEMATTR_DEVICE)
3542 if (va < VM_MAXUSER_ADDRESS)
3543 new_l2 |= ATTR_AP(ATTR_AP_USER) | ATTR_PXN;
3546 if (pmap != kernel_pmap)
3548 return (pmap_enter_l2(pmap, va, new_l2, PMAP_ENTER_NOSLEEP |
3549 PMAP_ENTER_NOREPLACE | PMAP_ENTER_NORECLAIM, NULL, lockp) ==
3554 * Tries to create the specified 2MB page mapping. Returns KERN_SUCCESS if
3555 * the mapping was created, and either KERN_FAILURE or KERN_RESOURCE_SHORTAGE
3556 * otherwise. Returns KERN_FAILURE if PMAP_ENTER_NOREPLACE was specified and
3557 * a mapping already exists at the specified virtual address. Returns
3558 * KERN_RESOURCE_SHORTAGE if PMAP_ENTER_NOSLEEP was specified and a page table
3559 * page allocation failed. Returns KERN_RESOURCE_SHORTAGE if
3560 * PMAP_ENTER_NORECLAIM was specified and a PV entry allocation failed.
3562 * The parameter "m" is only used when creating a managed, writeable mapping.
3565 pmap_enter_l2(pmap_t pmap, vm_offset_t va, pd_entry_t new_l2, u_int flags,
3566 vm_page_t m, struct rwlock **lockp)
3568 struct spglist free;
3569 pd_entry_t *l2, old_l2;
3572 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3574 if ((l2pg = pmap_alloc_l2(pmap, va, (flags & PMAP_ENTER_NOSLEEP) != 0 ?
3575 NULL : lockp)) == NULL) {
3576 CTR2(KTR_PMAP, "pmap_enter_l2: failure for va %#lx in pmap %p",
3578 return (KERN_RESOURCE_SHORTAGE);
3581 l2 = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(l2pg));
3582 l2 = &l2[pmap_l2_index(va)];
3583 if ((old_l2 = pmap_load(l2)) != 0) {
3584 KASSERT(l2pg->ref_count > 1,
3585 ("pmap_enter_l2: l2pg's ref count is too low"));
3586 if ((flags & PMAP_ENTER_NOREPLACE) != 0) {
3589 "pmap_enter_l2: failure for va %#lx in pmap %p",
3591 return (KERN_FAILURE);
3594 if ((old_l2 & ATTR_DESCR_MASK) == L2_BLOCK)
3595 (void)pmap_remove_l2(pmap, l2, va,
3596 pmap_load(pmap_l1(pmap, va)), &free, lockp);
3598 pmap_remove_l3_range(pmap, old_l2, va, va + L2_SIZE,
3600 vm_page_free_pages_toq(&free, true);
3601 if (va >= VM_MAXUSER_ADDRESS) {
3603 * Both pmap_remove_l2() and pmap_remove_l3_range()
3604 * will leave the kernel page table page zero filled.
3605 * Nonetheless, the TLB could have an intermediate
3606 * entry for the kernel page table page.
3608 mt = PHYS_TO_VM_PAGE(pmap_load(l2) & ~ATTR_MASK);
3609 if (pmap_insert_pt_page(pmap, mt, false))
3610 panic("pmap_enter_l2: trie insert failed");
3612 pmap_invalidate_page(pmap, va);
3614 KASSERT(pmap_load(l2) == 0,
3615 ("pmap_enter_l2: non-zero L2 entry %p", l2));
3618 if ((new_l2 & ATTR_SW_MANAGED) != 0) {
3620 * Abort this mapping if its PV entry could not be created.
3622 if (!pmap_pv_insert_l2(pmap, va, new_l2, flags, lockp)) {
3624 if (pmap_unwire_l3(pmap, va, l2pg, &free)) {
3626 * Although "va" is not mapped, the TLB could
3627 * nonetheless have intermediate entries that
3628 * refer to the freed page table pages.
3629 * Invalidate those entries.
3631 * XXX redundant invalidation (See
3632 * _pmap_unwire_l3().)
3634 pmap_invalidate_page(pmap, va);
3635 vm_page_free_pages_toq(&free, true);
3638 "pmap_enter_l2: failure for va %#lx in pmap %p",
3640 return (KERN_RESOURCE_SHORTAGE);
3642 if ((new_l2 & ATTR_SW_DBM) != 0)
3643 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
3644 vm_page_aflag_set(mt, PGA_WRITEABLE);
3648 * Increment counters.
3650 if ((new_l2 & ATTR_SW_WIRED) != 0)
3651 pmap->pm_stats.wired_count += L2_SIZE / PAGE_SIZE;
3652 pmap->pm_stats.resident_count += L2_SIZE / PAGE_SIZE;
3655 * Map the superpage.
3657 pmap_store(l2, new_l2);
3660 atomic_add_long(&pmap_l2_mappings, 1);
3661 CTR2(KTR_PMAP, "pmap_enter_l2: success for va %#lx in pmap %p",
3664 return (KERN_SUCCESS);
3668 * Maps a sequence of resident pages belonging to the same object.
3669 * The sequence begins with the given page m_start. This page is
3670 * mapped at the given virtual address start. Each subsequent page is
3671 * mapped at a virtual address that is offset from start by the same
3672 * amount as the page is offset from m_start within the object. The
3673 * last page in the sequence is the page with the largest offset from
3674 * m_start that can be mapped at a virtual address less than the given
3675 * virtual address end. Not every virtual page between start and end
3676 * is mapped; only those for which a resident page exists with the
3677 * corresponding offset from m_start are mapped.
3680 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
3681 vm_page_t m_start, vm_prot_t prot)
3683 struct rwlock *lock;
3686 vm_pindex_t diff, psize;
3688 VM_OBJECT_ASSERT_LOCKED(m_start->object);
3690 psize = atop(end - start);
3695 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
3696 va = start + ptoa(diff);
3697 if ((va & L2_OFFSET) == 0 && va + L2_SIZE <= end &&
3698 m->psind == 1 && pmap_ps_enabled(pmap) &&
3699 pmap_enter_2mpage(pmap, va, m, prot, &lock))
3700 m = &m[L2_SIZE / PAGE_SIZE - 1];
3702 mpte = pmap_enter_quick_locked(pmap, va, m, prot, mpte,
3704 m = TAILQ_NEXT(m, listq);
3712 * this code makes some *MAJOR* assumptions:
3713 * 1. Current pmap & pmap exists.
3716 * 4. No page table pages.
3717 * but is *MUCH* faster than pmap_enter...
3721 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3723 struct rwlock *lock;
3727 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL, &lock);
3734 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
3735 vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp)
3737 struct spglist free;
3739 pt_entry_t *l2, *l3, l3_val;
3743 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
3744 (m->oflags & VPO_UNMANAGED) != 0,
3745 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
3746 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3748 CTR2(KTR_PMAP, "pmap_enter_quick_locked: %p %lx", pmap, va);
3750 * In the case that a page table page is not
3751 * resident, we are creating it here.
3753 if (va < VM_MAXUSER_ADDRESS) {
3754 vm_pindex_t l2pindex;
3757 * Calculate pagetable page index
3759 l2pindex = pmap_l2_pindex(va);
3760 if (mpte && (mpte->pindex == l2pindex)) {
3766 pde = pmap_pde(pmap, va, &lvl);
3769 * If the page table page is mapped, we just increment
3770 * the hold count, and activate it. Otherwise, we
3771 * attempt to allocate a page table page. If this
3772 * attempt fails, we don't retry. Instead, we give up.
3775 l2 = pmap_l1_to_l2(pde, va);
3776 if ((pmap_load(l2) & ATTR_DESCR_MASK) ==
3780 if (lvl == 2 && pmap_load(pde) != 0) {
3782 PHYS_TO_VM_PAGE(pmap_load(pde) & ~ATTR_MASK);
3786 * Pass NULL instead of the PV list lock
3787 * pointer, because we don't intend to sleep.
3789 mpte = _pmap_alloc_l3(pmap, l2pindex, NULL);
3794 l3 = (pt_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpte));
3795 l3 = &l3[pmap_l3_index(va)];
3798 pde = pmap_pde(kernel_pmap, va, &lvl);
3799 KASSERT(pde != NULL,
3800 ("pmap_enter_quick_locked: Invalid page entry, va: 0x%lx",
3803 ("pmap_enter_quick_locked: Invalid level %d", lvl));
3804 l3 = pmap_l2_to_l3(pde, va);
3808 * Abort if a mapping already exists.
3810 if (pmap_load(l3) != 0) {
3819 * Enter on the PV list if part of our managed memory.
3821 if ((m->oflags & VPO_UNMANAGED) == 0 &&
3822 !pmap_try_insert_pv_entry(pmap, va, m, lockp)) {
3825 if (pmap_unwire_l3(pmap, va, mpte, &free)) {
3826 pmap_invalidate_page(pmap, va);
3827 vm_page_free_pages_toq(&free, true);
3835 * Increment counters
3837 pmap_resident_count_inc(pmap, 1);
3839 pa = VM_PAGE_TO_PHYS(m);
3840 l3_val = pa | ATTR_DEFAULT | ATTR_IDX(m->md.pv_memattr) |
3841 ATTR_AP(ATTR_AP_RO) | L3_PAGE;
3842 if ((prot & VM_PROT_EXECUTE) == 0 ||
3843 m->md.pv_memattr == VM_MEMATTR_DEVICE)
3845 if (va < VM_MAXUSER_ADDRESS)
3846 l3_val |= ATTR_AP(ATTR_AP_USER) | ATTR_PXN;
3849 if (pmap != kernel_pmap)
3853 * Now validate mapping with RO protection
3855 if ((m->oflags & VPO_UNMANAGED) == 0) {
3856 l3_val |= ATTR_SW_MANAGED;
3860 /* Sync icache before the mapping is stored to PTE */
3861 if ((prot & VM_PROT_EXECUTE) && pmap != kernel_pmap &&
3862 m->md.pv_memattr == VM_MEMATTR_WRITE_BACK)
3863 cpu_icache_sync_range(PHYS_TO_DMAP(pa), PAGE_SIZE);
3865 pmap_store(l3, l3_val);
3872 * This code maps large physical mmap regions into the
3873 * processor address space. Note that some shortcuts
3874 * are taken, but the code works.
3877 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
3878 vm_pindex_t pindex, vm_size_t size)
3881 VM_OBJECT_ASSERT_WLOCKED(object);
3882 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
3883 ("pmap_object_init_pt: non-device object"));
3887 * Clear the wired attribute from the mappings for the specified range of
3888 * addresses in the given pmap. Every valid mapping within that range
3889 * must have the wired attribute set. In contrast, invalid mappings
3890 * cannot have the wired attribute set, so they are ignored.
3892 * The wired attribute of the page table entry is not a hardware feature,
3893 * so there is no need to invalidate any TLB entries.
3896 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
3898 vm_offset_t va_next;
3899 pd_entry_t *l0, *l1, *l2;
3903 for (; sva < eva; sva = va_next) {
3904 l0 = pmap_l0(pmap, sva);
3905 if (pmap_load(l0) == 0) {
3906 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
3912 l1 = pmap_l0_to_l1(l0, sva);
3913 if (pmap_load(l1) == 0) {
3914 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
3920 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
3924 l2 = pmap_l1_to_l2(l1, sva);
3925 if (pmap_load(l2) == 0)
3928 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK) {
3929 if ((pmap_load(l2) & ATTR_SW_WIRED) == 0)
3930 panic("pmap_unwire: l2 %#jx is missing "
3931 "ATTR_SW_WIRED", (uintmax_t)pmap_load(l2));
3934 * Are we unwiring the entire large page? If not,
3935 * demote the mapping and fall through.
3937 if (sva + L2_SIZE == va_next && eva >= va_next) {
3938 pmap_clear_bits(l2, ATTR_SW_WIRED);
3939 pmap->pm_stats.wired_count -= L2_SIZE /
3942 } else if (pmap_demote_l2(pmap, l2, sva) == NULL)
3943 panic("pmap_unwire: demotion failed");
3945 KASSERT((pmap_load(l2) & ATTR_DESCR_MASK) == L2_TABLE,
3946 ("pmap_unwire: Invalid l2 entry after demotion"));
3950 for (l3 = pmap_l2_to_l3(l2, sva); sva != va_next; l3++,
3952 if (pmap_load(l3) == 0)
3954 if ((pmap_load(l3) & ATTR_SW_WIRED) == 0)
3955 panic("pmap_unwire: l3 %#jx is missing "
3956 "ATTR_SW_WIRED", (uintmax_t)pmap_load(l3));
3959 * ATTR_SW_WIRED must be cleared atomically. Although
3960 * the pmap lock synchronizes access to ATTR_SW_WIRED,
3961 * the System MMU may write to the entry concurrently.
3963 pmap_clear_bits(l3, ATTR_SW_WIRED);
3964 pmap->pm_stats.wired_count--;
3971 * Copy the range specified by src_addr/len
3972 * from the source map to the range dst_addr/len
3973 * in the destination map.
3975 * This routine is only advisory and need not do anything.
3977 * Because the executable mappings created by this routine are copied,
3978 * it should not have to flush the instruction cache.
3981 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
3982 vm_offset_t src_addr)
3984 struct rwlock *lock;
3985 struct spglist free;
3986 pd_entry_t *l0, *l1, *l2, srcptepaddr;
3987 pt_entry_t *dst_pte, mask, nbits, ptetemp, *src_pte;
3988 vm_offset_t addr, end_addr, va_next;
3989 vm_page_t dst_l2pg, dstmpte, srcmpte;
3991 if (dst_addr != src_addr)
3993 end_addr = src_addr + len;
3995 if (dst_pmap < src_pmap) {
3996 PMAP_LOCK(dst_pmap);
3997 PMAP_LOCK(src_pmap);
3999 PMAP_LOCK(src_pmap);
4000 PMAP_LOCK(dst_pmap);
4002 for (addr = src_addr; addr < end_addr; addr = va_next) {
4003 l0 = pmap_l0(src_pmap, addr);
4004 if (pmap_load(l0) == 0) {
4005 va_next = (addr + L0_SIZE) & ~L0_OFFSET;
4010 l1 = pmap_l0_to_l1(l0, addr);
4011 if (pmap_load(l1) == 0) {
4012 va_next = (addr + L1_SIZE) & ~L1_OFFSET;
4017 va_next = (addr + L2_SIZE) & ~L2_OFFSET;
4020 l2 = pmap_l1_to_l2(l1, addr);
4021 srcptepaddr = pmap_load(l2);
4022 if (srcptepaddr == 0)
4024 if ((srcptepaddr & ATTR_DESCR_MASK) == L2_BLOCK) {
4025 if ((addr & L2_OFFSET) != 0 ||
4026 addr + L2_SIZE > end_addr)
4028 dst_l2pg = pmap_alloc_l2(dst_pmap, addr, NULL);
4029 if (dst_l2pg == NULL)
4032 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dst_l2pg));
4033 l2 = &l2[pmap_l2_index(addr)];
4034 if (pmap_load(l2) == 0 &&
4035 ((srcptepaddr & ATTR_SW_MANAGED) == 0 ||
4036 pmap_pv_insert_l2(dst_pmap, addr, srcptepaddr,
4037 PMAP_ENTER_NORECLAIM, &lock))) {
4038 mask = ATTR_AF | ATTR_SW_WIRED;
4040 if ((srcptepaddr & ATTR_SW_DBM) != 0)
4041 nbits |= ATTR_AP_RW_BIT;
4042 pmap_store(l2, (srcptepaddr & ~mask) | nbits);
4043 pmap_resident_count_inc(dst_pmap, L2_SIZE /
4045 atomic_add_long(&pmap_l2_mappings, 1);
4047 dst_l2pg->ref_count--;
4050 KASSERT((srcptepaddr & ATTR_DESCR_MASK) == L2_TABLE,
4051 ("pmap_copy: invalid L2 entry"));
4052 srcptepaddr &= ~ATTR_MASK;
4053 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr);
4054 KASSERT(srcmpte->ref_count > 0,
4055 ("pmap_copy: source page table page is unused"));
4056 if (va_next > end_addr)
4058 src_pte = (pt_entry_t *)PHYS_TO_DMAP(srcptepaddr);
4059 src_pte = &src_pte[pmap_l3_index(addr)];
4061 for (; addr < va_next; addr += PAGE_SIZE, src_pte++) {
4062 ptetemp = pmap_load(src_pte);
4065 * We only virtual copy managed pages.
4067 if ((ptetemp & ATTR_SW_MANAGED) == 0)
4070 if (dstmpte != NULL) {
4071 KASSERT(dstmpte->pindex == pmap_l2_pindex(addr),
4072 ("dstmpte pindex/addr mismatch"));
4073 dstmpte->ref_count++;
4074 } else if ((dstmpte = pmap_alloc_l3(dst_pmap, addr,
4077 dst_pte = (pt_entry_t *)
4078 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dstmpte));
4079 dst_pte = &dst_pte[pmap_l3_index(addr)];
4080 if (pmap_load(dst_pte) == 0 &&
4081 pmap_try_insert_pv_entry(dst_pmap, addr,
4082 PHYS_TO_VM_PAGE(ptetemp & ~ATTR_MASK), &lock)) {
4084 * Clear the wired, modified, and accessed
4085 * (referenced) bits during the copy.
4087 mask = ATTR_AF | ATTR_SW_WIRED;
4089 if ((ptetemp & ATTR_SW_DBM) != 0)
4090 nbits |= ATTR_AP_RW_BIT;
4091 pmap_store(dst_pte, (ptetemp & ~mask) | nbits);
4092 pmap_resident_count_inc(dst_pmap, 1);
4095 if (pmap_unwire_l3(dst_pmap, addr, dstmpte,
4098 * Although "addr" is not mapped,
4099 * the TLB could nonetheless have
4100 * intermediate entries that refer
4101 * to the freed page table pages.
4102 * Invalidate those entries.
4104 * XXX redundant invalidation
4106 pmap_invalidate_page(dst_pmap, addr);
4107 vm_page_free_pages_toq(&free, true);
4111 /* Have we copied all of the valid mappings? */
4112 if (dstmpte->ref_count >= srcmpte->ref_count)
4118 * XXX This barrier may not be needed because the destination pmap is
4125 PMAP_UNLOCK(src_pmap);
4126 PMAP_UNLOCK(dst_pmap);
4130 * pmap_zero_page zeros the specified hardware page by mapping
4131 * the page into KVM and using bzero to clear its contents.
4134 pmap_zero_page(vm_page_t m)
4136 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
4138 pagezero((void *)va);
4142 * pmap_zero_page_area zeros the specified hardware page by mapping
4143 * the page into KVM and using bzero to clear its contents.
4145 * off and size may not cover an area beyond a single hardware page.
4148 pmap_zero_page_area(vm_page_t m, int off, int size)
4150 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
4152 if (off == 0 && size == PAGE_SIZE)
4153 pagezero((void *)va);
4155 bzero((char *)va + off, size);
4159 * pmap_copy_page copies the specified (machine independent)
4160 * page by mapping the page into virtual memory and using
4161 * bcopy to copy the page, one machine dependent page at a
4165 pmap_copy_page(vm_page_t msrc, vm_page_t mdst)
4167 vm_offset_t src = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(msrc));
4168 vm_offset_t dst = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mdst));
4170 pagecopy((void *)src, (void *)dst);
4173 int unmapped_buf_allowed = 1;
4176 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
4177 vm_offset_t b_offset, int xfersize)
4181 vm_paddr_t p_a, p_b;
4182 vm_offset_t a_pg_offset, b_pg_offset;
4185 while (xfersize > 0) {
4186 a_pg_offset = a_offset & PAGE_MASK;
4187 m_a = ma[a_offset >> PAGE_SHIFT];
4188 p_a = m_a->phys_addr;
4189 b_pg_offset = b_offset & PAGE_MASK;
4190 m_b = mb[b_offset >> PAGE_SHIFT];
4191 p_b = m_b->phys_addr;
4192 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
4193 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
4194 if (__predict_false(!PHYS_IN_DMAP(p_a))) {
4195 panic("!DMAP a %lx", p_a);
4197 a_cp = (char *)PHYS_TO_DMAP(p_a) + a_pg_offset;
4199 if (__predict_false(!PHYS_IN_DMAP(p_b))) {
4200 panic("!DMAP b %lx", p_b);
4202 b_cp = (char *)PHYS_TO_DMAP(p_b) + b_pg_offset;
4204 bcopy(a_cp, b_cp, cnt);
4212 pmap_quick_enter_page(vm_page_t m)
4215 return (PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)));
4219 pmap_quick_remove_page(vm_offset_t addr)
4224 * Returns true if the pmap's pv is one of the first
4225 * 16 pvs linked to from this page. This count may
4226 * be changed upwards or downwards in the future; it
4227 * is only necessary that true be returned for a small
4228 * subset of pmaps for proper page aging.
4231 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
4233 struct md_page *pvh;
4234 struct rwlock *lock;
4239 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4240 ("pmap_page_exists_quick: page %p is not managed", m));
4242 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
4244 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4245 if (PV_PMAP(pv) == pmap) {
4253 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
4254 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4255 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4256 if (PV_PMAP(pv) == pmap) {
4270 * pmap_page_wired_mappings:
4272 * Return the number of managed mappings to the given physical page
4276 pmap_page_wired_mappings(vm_page_t m)
4278 struct rwlock *lock;
4279 struct md_page *pvh;
4283 int count, lvl, md_gen, pvh_gen;
4285 if ((m->oflags & VPO_UNMANAGED) != 0)
4287 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
4291 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4293 if (!PMAP_TRYLOCK(pmap)) {
4294 md_gen = m->md.pv_gen;
4298 if (md_gen != m->md.pv_gen) {
4303 pte = pmap_pte(pmap, pv->pv_va, &lvl);
4304 if (pte != NULL && (pmap_load(pte) & ATTR_SW_WIRED) != 0)
4308 if ((m->flags & PG_FICTITIOUS) == 0) {
4309 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4310 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4312 if (!PMAP_TRYLOCK(pmap)) {
4313 md_gen = m->md.pv_gen;
4314 pvh_gen = pvh->pv_gen;
4318 if (md_gen != m->md.pv_gen ||
4319 pvh_gen != pvh->pv_gen) {
4324 pte = pmap_pte(pmap, pv->pv_va, &lvl);
4326 (pmap_load(pte) & ATTR_SW_WIRED) != 0)
4336 * Returns true if the given page is mapped individually or as part of
4337 * a 2mpage. Otherwise, returns false.
4340 pmap_page_is_mapped(vm_page_t m)
4342 struct rwlock *lock;
4345 if ((m->oflags & VPO_UNMANAGED) != 0)
4347 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
4349 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
4350 ((m->flags & PG_FICTITIOUS) == 0 &&
4351 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
4357 * Destroy all managed, non-wired mappings in the given user-space
4358 * pmap. This pmap cannot be active on any processor besides the
4361 * This function cannot be applied to the kernel pmap. Moreover, it
4362 * is not intended for general use. It is only to be used during
4363 * process termination. Consequently, it can be implemented in ways
4364 * that make it faster than pmap_remove(). First, it can more quickly
4365 * destroy mappings by iterating over the pmap's collection of PV
4366 * entries, rather than searching the page table. Second, it doesn't
4367 * have to test and clear the page table entries atomically, because
4368 * no processor is currently accessing the user address space. In
4369 * particular, a page table entry's dirty bit won't change state once
4370 * this function starts.
4373 pmap_remove_pages(pmap_t pmap)
4376 pt_entry_t *pte, tpte;
4377 struct spglist free;
4378 vm_page_t m, ml3, mt;
4380 struct md_page *pvh;
4381 struct pv_chunk *pc, *npc;
4382 struct rwlock *lock;
4384 uint64_t inuse, bitmask;
4385 int allfree, field, freed, idx, lvl;
4388 KASSERT(pmap == PCPU_GET(curpmap), ("non-current pmap %p", pmap));
4394 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
4397 for (field = 0; field < _NPCM; field++) {
4398 inuse = ~pc->pc_map[field] & pc_freemask[field];
4399 while (inuse != 0) {
4400 bit = ffsl(inuse) - 1;
4401 bitmask = 1UL << bit;
4402 idx = field * 64 + bit;
4403 pv = &pc->pc_pventry[idx];
4406 pde = pmap_pde(pmap, pv->pv_va, &lvl);
4407 KASSERT(pde != NULL,
4408 ("Attempting to remove an unmapped page"));
4412 pte = pmap_l1_to_l2(pde, pv->pv_va);
4413 tpte = pmap_load(pte);
4414 KASSERT((tpte & ATTR_DESCR_MASK) ==
4416 ("Attempting to remove an invalid "
4417 "block: %lx", tpte));
4420 pte = pmap_l2_to_l3(pde, pv->pv_va);
4421 tpte = pmap_load(pte);
4422 KASSERT((tpte & ATTR_DESCR_MASK) ==
4424 ("Attempting to remove an invalid "
4425 "page: %lx", tpte));
4429 "Invalid page directory level: %d",
4434 * We cannot remove wired pages from a process' mapping at this time
4436 if (tpte & ATTR_SW_WIRED) {
4441 pa = tpte & ~ATTR_MASK;
4443 m = PHYS_TO_VM_PAGE(pa);
4444 KASSERT(m->phys_addr == pa,
4445 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
4446 m, (uintmax_t)m->phys_addr,
4449 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
4450 m < &vm_page_array[vm_page_array_size],
4451 ("pmap_remove_pages: bad pte %#jx",
4455 * Because this pmap is not active on other
4456 * processors, the dirty bit cannot have
4457 * changed state since we last loaded pte.
4462 * Update the vm_page_t clean/reference bits.
4464 if (pmap_pte_dirty(tpte)) {
4467 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
4476 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(&lock, m);
4479 pc->pc_map[field] |= bitmask;
4482 pmap_resident_count_dec(pmap,
4483 L2_SIZE / PAGE_SIZE);
4484 pvh = pa_to_pvh(tpte & ~ATTR_MASK);
4485 TAILQ_REMOVE(&pvh->pv_list, pv,pv_next);
4487 if (TAILQ_EMPTY(&pvh->pv_list)) {
4488 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
4489 if ((mt->a.flags & PGA_WRITEABLE) != 0 &&
4490 TAILQ_EMPTY(&mt->md.pv_list))
4491 vm_page_aflag_clear(mt, PGA_WRITEABLE);
4493 ml3 = pmap_remove_pt_page(pmap,
4496 KASSERT(ml3->valid == VM_PAGE_BITS_ALL,
4497 ("pmap_remove_pages: l3 page not promoted"));
4498 pmap_resident_count_dec(pmap,1);
4499 KASSERT(ml3->ref_count == NL3PG,
4500 ("pmap_remove_pages: l3 page ref count error"));
4502 pmap_add_delayed_free_list(ml3,
4507 pmap_resident_count_dec(pmap, 1);
4508 TAILQ_REMOVE(&m->md.pv_list, pv,
4511 if ((m->a.flags & PGA_WRITEABLE) != 0 &&
4512 TAILQ_EMPTY(&m->md.pv_list) &&
4513 (m->flags & PG_FICTITIOUS) == 0) {
4515 VM_PAGE_TO_PHYS(m));
4516 if (TAILQ_EMPTY(&pvh->pv_list))
4517 vm_page_aflag_clear(m,
4522 pmap_unuse_pt(pmap, pv->pv_va, pmap_load(pde),
4527 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
4528 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
4529 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
4531 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4537 pmap_invalidate_all(pmap);
4539 vm_page_free_pages_toq(&free, true);
4543 * This is used to check if a page has been accessed or modified.
4546 pmap_page_test_mappings(vm_page_t m, boolean_t accessed, boolean_t modified)
4548 struct rwlock *lock;
4550 struct md_page *pvh;
4551 pt_entry_t *pte, mask, value;
4553 int lvl, md_gen, pvh_gen;
4557 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
4560 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4562 if (!PMAP_TRYLOCK(pmap)) {
4563 md_gen = m->md.pv_gen;
4567 if (md_gen != m->md.pv_gen) {
4572 pte = pmap_pte(pmap, pv->pv_va, &lvl);
4574 ("pmap_page_test_mappings: Invalid level %d", lvl));
4578 mask |= ATTR_AP_RW_BIT;
4579 value |= ATTR_AP(ATTR_AP_RW);
4582 mask |= ATTR_AF | ATTR_DESCR_MASK;
4583 value |= ATTR_AF | L3_PAGE;
4585 rv = (pmap_load(pte) & mask) == value;
4590 if ((m->flags & PG_FICTITIOUS) == 0) {
4591 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4592 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4594 if (!PMAP_TRYLOCK(pmap)) {
4595 md_gen = m->md.pv_gen;
4596 pvh_gen = pvh->pv_gen;
4600 if (md_gen != m->md.pv_gen ||
4601 pvh_gen != pvh->pv_gen) {
4606 pte = pmap_pte(pmap, pv->pv_va, &lvl);
4608 ("pmap_page_test_mappings: Invalid level %d", lvl));
4612 mask |= ATTR_AP_RW_BIT;
4613 value |= ATTR_AP(ATTR_AP_RW);
4616 mask |= ATTR_AF | ATTR_DESCR_MASK;
4617 value |= ATTR_AF | L2_BLOCK;
4619 rv = (pmap_load(pte) & mask) == value;
4633 * Return whether or not the specified physical page was modified
4634 * in any physical maps.
4637 pmap_is_modified(vm_page_t m)
4640 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4641 ("pmap_is_modified: page %p is not managed", m));
4644 * If the page is not busied then this check is racy.
4646 if (!pmap_page_is_write_mapped(m))
4648 return (pmap_page_test_mappings(m, FALSE, TRUE));
4652 * pmap_is_prefaultable:
4654 * Return whether or not the specified virtual address is eligible
4658 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
4666 pte = pmap_pte(pmap, addr, &lvl);
4667 if (pte != NULL && pmap_load(pte) != 0) {
4675 * pmap_is_referenced:
4677 * Return whether or not the specified physical page was referenced
4678 * in any physical maps.
4681 pmap_is_referenced(vm_page_t m)
4684 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4685 ("pmap_is_referenced: page %p is not managed", m));
4686 return (pmap_page_test_mappings(m, TRUE, FALSE));
4690 * Clear the write and modified bits in each of the given page's mappings.
4693 pmap_remove_write(vm_page_t m)
4695 struct md_page *pvh;
4697 struct rwlock *lock;
4698 pv_entry_t next_pv, pv;
4699 pt_entry_t oldpte, *pte;
4701 int lvl, md_gen, pvh_gen;
4703 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4704 ("pmap_remove_write: page %p is not managed", m));
4705 vm_page_assert_busied(m);
4707 if (!pmap_page_is_write_mapped(m))
4709 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
4710 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
4711 pa_to_pvh(VM_PAGE_TO_PHYS(m));
4714 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
4716 if (!PMAP_TRYLOCK(pmap)) {
4717 pvh_gen = pvh->pv_gen;
4721 if (pvh_gen != pvh->pv_gen) {
4728 pte = pmap_pte(pmap, pv->pv_va, &lvl);
4729 if ((pmap_load(pte) & ATTR_SW_DBM) != 0)
4730 (void)pmap_demote_l2_locked(pmap, pte, va, &lock);
4731 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
4732 ("inconsistent pv lock %p %p for page %p",
4733 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
4736 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4738 if (!PMAP_TRYLOCK(pmap)) {
4739 pvh_gen = pvh->pv_gen;
4740 md_gen = m->md.pv_gen;
4744 if (pvh_gen != pvh->pv_gen ||
4745 md_gen != m->md.pv_gen) {
4751 pte = pmap_pte(pmap, pv->pv_va, &lvl);
4752 oldpte = pmap_load(pte);
4754 if ((oldpte & ATTR_SW_DBM) != 0) {
4755 if (!atomic_fcmpset_long(pte, &oldpte,
4756 (oldpte | ATTR_AP_RW_BIT) & ~ATTR_SW_DBM))
4758 if ((oldpte & ATTR_AP_RW_BIT) ==
4759 ATTR_AP(ATTR_AP_RW))
4761 pmap_invalidate_page(pmap, pv->pv_va);
4766 vm_page_aflag_clear(m, PGA_WRITEABLE);
4770 * pmap_ts_referenced:
4772 * Return a count of reference bits for a page, clearing those bits.
4773 * It is not necessary for every reference bit to be cleared, but it
4774 * is necessary that 0 only be returned when there are truly no
4775 * reference bits set.
4777 * As an optimization, update the page's dirty field if a modified bit is
4778 * found while counting reference bits. This opportunistic update can be
4779 * performed at low cost and can eliminate the need for some future calls
4780 * to pmap_is_modified(). However, since this function stops after
4781 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
4782 * dirty pages. Those dirty pages will only be detected by a future call
4783 * to pmap_is_modified().
4786 pmap_ts_referenced(vm_page_t m)
4788 struct md_page *pvh;
4791 struct rwlock *lock;
4792 pd_entry_t *pde, tpde;
4793 pt_entry_t *pte, tpte;
4796 int cleared, lvl, md_gen, not_cleared, pvh_gen;
4797 struct spglist free;
4799 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4800 ("pmap_ts_referenced: page %p is not managed", m));
4803 pa = VM_PAGE_TO_PHYS(m);
4804 lock = PHYS_TO_PV_LIST_LOCK(pa);
4805 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : pa_to_pvh(pa);
4809 if ((pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
4810 goto small_mappings;
4816 if (!PMAP_TRYLOCK(pmap)) {
4817 pvh_gen = pvh->pv_gen;
4821 if (pvh_gen != pvh->pv_gen) {
4827 pde = pmap_pde(pmap, pv->pv_va, &lvl);
4828 KASSERT(pde != NULL, ("pmap_ts_referenced: no l1 table found"));
4830 ("pmap_ts_referenced: invalid pde level %d", lvl));
4831 tpde = pmap_load(pde);
4832 KASSERT((tpde & ATTR_DESCR_MASK) == L1_TABLE,
4833 ("pmap_ts_referenced: found an invalid l1 table"));
4834 pte = pmap_l1_to_l2(pde, pv->pv_va);
4835 tpte = pmap_load(pte);
4836 if (pmap_pte_dirty(tpte)) {
4838 * Although "tpte" is mapping a 2MB page, because
4839 * this function is called at a 4KB page granularity,
4840 * we only update the 4KB page under test.
4845 if ((tpte & ATTR_AF) != 0) {
4847 * Since this reference bit is shared by 512 4KB pages,
4848 * it should not be cleared every time it is tested.
4849 * Apply a simple "hash" function on the physical page
4850 * number, the virtual superpage number, and the pmap
4851 * address to select one 4KB page out of the 512 on
4852 * which testing the reference bit will result in
4853 * clearing that reference bit. This function is
4854 * designed to avoid the selection of the same 4KB page
4855 * for every 2MB page mapping.
4857 * On demotion, a mapping that hasn't been referenced
4858 * is simply destroyed. To avoid the possibility of a
4859 * subsequent page fault on a demoted wired mapping,
4860 * always leave its reference bit set. Moreover,
4861 * since the superpage is wired, the current state of
4862 * its reference bit won't affect page replacement.
4864 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> L2_SHIFT) ^
4865 (uintptr_t)pmap) & (Ln_ENTRIES - 1)) == 0 &&
4866 (tpte & ATTR_SW_WIRED) == 0) {
4867 pmap_clear_bits(pte, ATTR_AF);
4868 pmap_invalidate_page(pmap, pv->pv_va);
4874 /* Rotate the PV list if it has more than one entry. */
4875 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
4876 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
4877 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
4880 if (cleared + not_cleared >= PMAP_TS_REFERENCED_MAX)
4882 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
4884 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
4891 if (!PMAP_TRYLOCK(pmap)) {
4892 pvh_gen = pvh->pv_gen;
4893 md_gen = m->md.pv_gen;
4897 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
4902 pde = pmap_pde(pmap, pv->pv_va, &lvl);
4903 KASSERT(pde != NULL, ("pmap_ts_referenced: no l2 table found"));
4905 ("pmap_ts_referenced: invalid pde level %d", lvl));
4906 tpde = pmap_load(pde);
4907 KASSERT((tpde & ATTR_DESCR_MASK) == L2_TABLE,
4908 ("pmap_ts_referenced: found an invalid l2 table"));
4909 pte = pmap_l2_to_l3(pde, pv->pv_va);
4910 tpte = pmap_load(pte);
4911 if (pmap_pte_dirty(tpte))
4913 if ((tpte & ATTR_AF) != 0) {
4914 if ((tpte & ATTR_SW_WIRED) == 0) {
4915 pmap_clear_bits(pte, ATTR_AF);
4916 pmap_invalidate_page(pmap, pv->pv_va);
4922 /* Rotate the PV list if it has more than one entry. */
4923 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
4924 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4925 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4928 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && cleared +
4929 not_cleared < PMAP_TS_REFERENCED_MAX);
4932 vm_page_free_pages_toq(&free, true);
4933 return (cleared + not_cleared);
4937 * Apply the given advice to the specified range of addresses within the
4938 * given pmap. Depending on the advice, clear the referenced and/or
4939 * modified flags in each mapping and set the mapped page's dirty field.
4942 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
4944 struct rwlock *lock;
4945 vm_offset_t va, va_next;
4947 pd_entry_t *l0, *l1, *l2, oldl2;
4948 pt_entry_t *l3, oldl3;
4950 if (advice != MADV_DONTNEED && advice != MADV_FREE)
4954 for (; sva < eva; sva = va_next) {
4955 l0 = pmap_l0(pmap, sva);
4956 if (pmap_load(l0) == 0) {
4957 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
4962 l1 = pmap_l0_to_l1(l0, sva);
4963 if (pmap_load(l1) == 0) {
4964 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
4969 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
4972 l2 = pmap_l1_to_l2(l1, sva);
4973 oldl2 = pmap_load(l2);
4976 if ((oldl2 & ATTR_DESCR_MASK) == L2_BLOCK) {
4977 if ((oldl2 & ATTR_SW_MANAGED) == 0)
4980 if (!pmap_demote_l2_locked(pmap, l2, sva, &lock)) {
4985 * The 2MB page mapping was destroyed.
4991 * Unless the page mappings are wired, remove the
4992 * mapping to a single page so that a subsequent
4993 * access may repromote. Choosing the last page
4994 * within the address range [sva, min(va_next, eva))
4995 * generally results in more repromotions. Since the
4996 * underlying page table page is fully populated, this
4997 * removal never frees a page table page.
4999 if ((oldl2 & ATTR_SW_WIRED) == 0) {
5005 ("pmap_advise: no address gap"));
5006 l3 = pmap_l2_to_l3(l2, va);
5007 KASSERT(pmap_load(l3) != 0,
5008 ("pmap_advise: invalid PTE"));
5009 pmap_remove_l3(pmap, l3, va, pmap_load(l2),
5015 KASSERT((pmap_load(l2) & ATTR_DESCR_MASK) == L2_TABLE,
5016 ("pmap_advise: invalid L2 entry after demotion"));
5020 for (l3 = pmap_l2_to_l3(l2, sva); sva != va_next; l3++,
5022 oldl3 = pmap_load(l3);
5023 if ((oldl3 & (ATTR_SW_MANAGED | ATTR_DESCR_MASK)) !=
5024 (ATTR_SW_MANAGED | L3_PAGE))
5026 else if (pmap_pte_dirty(oldl3)) {
5027 if (advice == MADV_DONTNEED) {
5029 * Future calls to pmap_is_modified()
5030 * can be avoided by making the page
5033 m = PHYS_TO_VM_PAGE(oldl3 & ~ATTR_MASK);
5036 while (!atomic_fcmpset_long(l3, &oldl3,
5037 (oldl3 & ~ATTR_AF) | ATTR_AP(ATTR_AP_RO)))
5039 } else if ((oldl3 & ATTR_AF) != 0)
5040 pmap_clear_bits(l3, ATTR_AF);
5047 if (va != va_next) {
5048 pmap_invalidate_range(pmap, va, sva);
5053 pmap_invalidate_range(pmap, va, sva);
5059 * Clear the modify bits on the specified physical page.
5062 pmap_clear_modify(vm_page_t m)
5064 struct md_page *pvh;
5065 struct rwlock *lock;
5067 pv_entry_t next_pv, pv;
5068 pd_entry_t *l2, oldl2;
5069 pt_entry_t *l3, oldl3;
5071 int md_gen, pvh_gen;
5073 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5074 ("pmap_clear_modify: page %p is not managed", m));
5075 vm_page_assert_busied(m);
5077 if (!pmap_page_is_write_mapped(m))
5079 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
5080 pa_to_pvh(VM_PAGE_TO_PHYS(m));
5081 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5084 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
5086 if (!PMAP_TRYLOCK(pmap)) {
5087 pvh_gen = pvh->pv_gen;
5091 if (pvh_gen != pvh->pv_gen) {
5097 l2 = pmap_l2(pmap, va);
5098 oldl2 = pmap_load(l2);
5099 /* If oldl2 has ATTR_SW_DBM set, then it is also dirty. */
5100 if ((oldl2 & ATTR_SW_DBM) != 0 &&
5101 pmap_demote_l2_locked(pmap, l2, va, &lock) &&
5102 (oldl2 & ATTR_SW_WIRED) == 0) {
5104 * Write protect the mapping to a single page so that
5105 * a subsequent write access may repromote.
5107 va += VM_PAGE_TO_PHYS(m) - (oldl2 & ~ATTR_MASK);
5108 l3 = pmap_l2_to_l3(l2, va);
5109 oldl3 = pmap_load(l3);
5110 while (!atomic_fcmpset_long(l3, &oldl3,
5111 (oldl3 & ~ATTR_SW_DBM) | ATTR_AP(ATTR_AP_RO)))
5114 pmap_invalidate_page(pmap, va);
5118 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5120 if (!PMAP_TRYLOCK(pmap)) {
5121 md_gen = m->md.pv_gen;
5122 pvh_gen = pvh->pv_gen;
5126 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
5131 l2 = pmap_l2(pmap, pv->pv_va);
5132 l3 = pmap_l2_to_l3(l2, pv->pv_va);
5133 oldl3 = pmap_load(l3);
5134 if (pmap_l3_valid(oldl3) &&
5135 (oldl3 & (ATTR_AP_RW_BIT | ATTR_SW_DBM)) == ATTR_SW_DBM) {
5136 pmap_set_bits(l3, ATTR_AP(ATTR_AP_RO));
5137 pmap_invalidate_page(pmap, pv->pv_va);
5145 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
5147 struct pmap_preinit_mapping *ppim;
5148 vm_offset_t va, offset;
5151 int i, lvl, l2_blocks, free_l2_count, start_idx;
5153 if (!vm_initialized) {
5155 * No L3 ptables so map entire L2 blocks where start VA is:
5156 * preinit_map_va + start_idx * L2_SIZE
5157 * There may be duplicate mappings (multiple VA -> same PA) but
5158 * ARM64 dcache is always PIPT so that's acceptable.
5163 /* Calculate how many L2 blocks are needed for the mapping */
5164 l2_blocks = (roundup2(pa + size, L2_SIZE) -
5165 rounddown2(pa, L2_SIZE)) >> L2_SHIFT;
5167 offset = pa & L2_OFFSET;
5169 if (preinit_map_va == 0)
5172 /* Map 2MiB L2 blocks from reserved VA space */
5176 /* Find enough free contiguous VA space */
5177 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5178 ppim = pmap_preinit_mapping + i;
5179 if (free_l2_count > 0 && ppim->pa != 0) {
5180 /* Not enough space here */
5186 if (ppim->pa == 0) {
5188 if (start_idx == -1)
5191 if (free_l2_count == l2_blocks)
5195 if (free_l2_count != l2_blocks)
5196 panic("%s: too many preinit mappings", __func__);
5198 va = preinit_map_va + (start_idx * L2_SIZE);
5199 for (i = start_idx; i < start_idx + l2_blocks; i++) {
5200 /* Mark entries as allocated */
5201 ppim = pmap_preinit_mapping + i;
5203 ppim->va = va + offset;
5208 pa = rounddown2(pa, L2_SIZE);
5209 for (i = 0; i < l2_blocks; i++) {
5210 pde = pmap_pde(kernel_pmap, va, &lvl);
5211 KASSERT(pde != NULL,
5212 ("pmap_mapbios: Invalid page entry, va: 0x%lx",
5215 ("pmap_mapbios: Invalid level %d", lvl));
5217 /* Insert L2_BLOCK */
5218 l2 = pmap_l1_to_l2(pde, va);
5220 pa | ATTR_DEFAULT | ATTR_XN |
5221 ATTR_IDX(VM_MEMATTR_WRITE_BACK) | L2_BLOCK);
5226 pmap_invalidate_all(kernel_pmap);
5228 va = preinit_map_va + (start_idx * L2_SIZE);
5231 /* kva_alloc may be used to map the pages */
5232 offset = pa & PAGE_MASK;
5233 size = round_page(offset + size);
5235 va = kva_alloc(size);
5237 panic("%s: Couldn't allocate KVA", __func__);
5239 pde = pmap_pde(kernel_pmap, va, &lvl);
5240 KASSERT(lvl == 2, ("pmap_mapbios: Invalid level %d", lvl));
5242 /* L3 table is linked */
5243 va = trunc_page(va);
5244 pa = trunc_page(pa);
5245 pmap_kenter(va, size, pa, VM_MEMATTR_WRITE_BACK);
5248 return ((void *)(va + offset));
5252 pmap_unmapbios(vm_offset_t va, vm_size_t size)
5254 struct pmap_preinit_mapping *ppim;
5255 vm_offset_t offset, tmpsize, va_trunc;
5258 int i, lvl, l2_blocks, block;
5262 (roundup2(va + size, L2_SIZE) - rounddown2(va, L2_SIZE)) >> L2_SHIFT;
5263 KASSERT(l2_blocks > 0, ("pmap_unmapbios: invalid size %lx", size));
5265 /* Remove preinit mapping */
5266 preinit_map = false;
5268 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5269 ppim = pmap_preinit_mapping + i;
5270 if (ppim->va == va) {
5271 KASSERT(ppim->size == size,
5272 ("pmap_unmapbios: size mismatch"));
5277 offset = block * L2_SIZE;
5278 va_trunc = rounddown2(va, L2_SIZE) + offset;
5280 /* Remove L2_BLOCK */
5281 pde = pmap_pde(kernel_pmap, va_trunc, &lvl);
5282 KASSERT(pde != NULL,
5283 ("pmap_unmapbios: Invalid page entry, va: 0x%lx",
5285 l2 = pmap_l1_to_l2(pde, va_trunc);
5288 if (block == (l2_blocks - 1))
5294 pmap_invalidate_all(kernel_pmap);
5298 /* Unmap the pages reserved with kva_alloc. */
5299 if (vm_initialized) {
5300 offset = va & PAGE_MASK;
5301 size = round_page(offset + size);
5302 va = trunc_page(va);
5304 pde = pmap_pde(kernel_pmap, va, &lvl);
5305 KASSERT(pde != NULL,
5306 ("pmap_unmapbios: Invalid page entry, va: 0x%lx", va));
5307 KASSERT(lvl == 2, ("pmap_unmapbios: Invalid level %d", lvl));
5309 /* Unmap and invalidate the pages */
5310 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
5311 pmap_kremove(va + tmpsize);
5318 * Sets the memory attribute for the specified page.
5321 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
5324 m->md.pv_memattr = ma;
5327 * If "m" is a normal page, update its direct mapping. This update
5328 * can be relied upon to perform any cache operations that are
5329 * required for data coherence.
5331 if ((m->flags & PG_FICTITIOUS) == 0 &&
5332 pmap_change_attr(PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)), PAGE_SIZE,
5333 m->md.pv_memattr) != 0)
5334 panic("memory attribute change on the direct map failed");
5338 * Changes the specified virtual address range's memory type to that given by
5339 * the parameter "mode". The specified virtual address range must be
5340 * completely contained within either the direct map or the kernel map. If
5341 * the virtual address range is contained within the kernel map, then the
5342 * memory type for each of the corresponding ranges of the direct map is also
5343 * changed. (The corresponding ranges of the direct map are those ranges that
5344 * map the same physical pages as the specified virtual address range.) These
5345 * changes to the direct map are necessary because Intel describes the
5346 * behavior of their processors as "undefined" if two or more mappings to the
5347 * same physical page have different memory types.
5349 * Returns zero if the change completed successfully, and either EINVAL or
5350 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
5351 * of the virtual address range was not mapped, and ENOMEM is returned if
5352 * there was insufficient memory available to complete the change. In the
5353 * latter case, the memory type may have been changed on some part of the
5354 * virtual address range or the direct map.
5357 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
5361 PMAP_LOCK(kernel_pmap);
5362 error = pmap_change_attr_locked(va, size, mode);
5363 PMAP_UNLOCK(kernel_pmap);
5368 pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode)
5370 vm_offset_t base, offset, tmpva;
5371 pt_entry_t l3, *pte, *newpte;
5374 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
5375 base = trunc_page(va);
5376 offset = va & PAGE_MASK;
5377 size = round_page(offset + size);
5379 if (!VIRT_IN_DMAP(base) &&
5380 !(base >= VM_MIN_KERNEL_ADDRESS && base < VM_MAX_KERNEL_ADDRESS))
5383 for (tmpva = base; tmpva < base + size; ) {
5384 pte = pmap_pte(kernel_pmap, tmpva, &lvl);
5388 if ((pmap_load(pte) & ATTR_IDX_MASK) == ATTR_IDX(mode)) {
5390 * We already have the correct attribute,
5391 * ignore this entry.
5395 panic("Invalid DMAP table level: %d\n", lvl);
5397 tmpva = (tmpva & ~L1_OFFSET) + L1_SIZE;
5400 tmpva = (tmpva & ~L2_OFFSET) + L2_SIZE;
5408 * Split the entry to an level 3 table, then
5409 * set the new attribute.
5413 panic("Invalid DMAP table level: %d\n", lvl);
5415 newpte = pmap_demote_l1(kernel_pmap, pte,
5416 tmpva & ~L1_OFFSET);
5419 pte = pmap_l1_to_l2(pte, tmpva);
5421 newpte = pmap_demote_l2(kernel_pmap, pte,
5425 pte = pmap_l2_to_l3(pte, tmpva);
5427 /* Update the entry */
5428 l3 = pmap_load(pte);
5429 l3 &= ~ATTR_IDX_MASK;
5430 l3 |= ATTR_IDX(mode);
5431 if (mode == VM_MEMATTR_DEVICE)
5434 pmap_update_entry(kernel_pmap, pte, l3, tmpva,
5438 * If moving to a non-cacheable entry flush
5441 if (mode == VM_MEMATTR_UNCACHEABLE)
5442 cpu_dcache_wbinv_range(tmpva, L3_SIZE);
5454 * Create an L2 table to map all addresses within an L1 mapping.
5457 pmap_demote_l1(pmap_t pmap, pt_entry_t *l1, vm_offset_t va)
5459 pt_entry_t *l2, newl2, oldl1;
5461 vm_paddr_t l2phys, phys;
5465 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5466 oldl1 = pmap_load(l1);
5467 KASSERT((oldl1 & ATTR_DESCR_MASK) == L1_BLOCK,
5468 ("pmap_demote_l1: Demoting a non-block entry"));
5469 KASSERT((va & L1_OFFSET) == 0,
5470 ("pmap_demote_l1: Invalid virtual address %#lx", va));
5471 KASSERT((oldl1 & ATTR_SW_MANAGED) == 0,
5472 ("pmap_demote_l1: Level 1 table shouldn't be managed"));
5475 if (va <= (vm_offset_t)l1 && va + L1_SIZE > (vm_offset_t)l1) {
5476 tmpl1 = kva_alloc(PAGE_SIZE);
5481 if ((ml2 = vm_page_alloc(NULL, 0, VM_ALLOC_INTERRUPT |
5482 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
5483 CTR2(KTR_PMAP, "pmap_demote_l1: failure for va %#lx"
5484 " in pmap %p", va, pmap);
5488 l2phys = VM_PAGE_TO_PHYS(ml2);
5489 l2 = (pt_entry_t *)PHYS_TO_DMAP(l2phys);
5491 /* Address the range points at */
5492 phys = oldl1 & ~ATTR_MASK;
5493 /* The attributed from the old l1 table to be copied */
5494 newl2 = oldl1 & ATTR_MASK;
5496 /* Create the new entries */
5497 for (i = 0; i < Ln_ENTRIES; i++) {
5498 l2[i] = newl2 | phys;
5501 KASSERT(l2[0] == ((oldl1 & ~ATTR_DESCR_MASK) | L2_BLOCK),
5502 ("Invalid l2 page (%lx != %lx)", l2[0],
5503 (oldl1 & ~ATTR_DESCR_MASK) | L2_BLOCK));
5506 pmap_kenter(tmpl1, PAGE_SIZE,
5507 DMAP_TO_PHYS((vm_offset_t)l1) & ~L3_OFFSET,
5508 VM_MEMATTR_WRITE_BACK);
5509 l1 = (pt_entry_t *)(tmpl1 + ((vm_offset_t)l1 & PAGE_MASK));
5512 pmap_update_entry(pmap, l1, l2phys | L1_TABLE, va, PAGE_SIZE);
5515 pmap_kremove(tmpl1);
5516 kva_free(tmpl1, PAGE_SIZE);
5523 pmap_fill_l3(pt_entry_t *firstl3, pt_entry_t newl3)
5527 for (l3 = firstl3; l3 - firstl3 < Ln_ENTRIES; l3++) {
5534 pmap_demote_l2_abort(pmap_t pmap, vm_offset_t va, pt_entry_t *l2,
5535 struct rwlock **lockp)
5537 struct spglist free;
5540 (void)pmap_remove_l2(pmap, l2, va, pmap_load(pmap_l1(pmap, va)), &free,
5542 vm_page_free_pages_toq(&free, true);
5546 * Create an L3 table to map all addresses within an L2 mapping.
5549 pmap_demote_l2_locked(pmap_t pmap, pt_entry_t *l2, vm_offset_t va,
5550 struct rwlock **lockp)
5552 pt_entry_t *l3, newl3, oldl2;
5557 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5559 oldl2 = pmap_load(l2);
5560 KASSERT((oldl2 & ATTR_DESCR_MASK) == L2_BLOCK,
5561 ("pmap_demote_l2: Demoting a non-block entry"));
5565 if (va <= (vm_offset_t)l2 && va + L2_SIZE > (vm_offset_t)l2) {
5566 tmpl2 = kva_alloc(PAGE_SIZE);
5572 * Invalidate the 2MB page mapping and return "failure" if the
5573 * mapping was never accessed.
5575 if ((oldl2 & ATTR_AF) == 0) {
5576 KASSERT((oldl2 & ATTR_SW_WIRED) == 0,
5577 ("pmap_demote_l2: a wired mapping is missing ATTR_AF"));
5578 pmap_demote_l2_abort(pmap, va, l2, lockp);
5579 CTR2(KTR_PMAP, "pmap_demote_l2: failure for va %#lx in pmap %p",
5584 if ((ml3 = pmap_remove_pt_page(pmap, va)) == NULL) {
5585 KASSERT((oldl2 & ATTR_SW_WIRED) == 0,
5586 ("pmap_demote_l2: page table page for a wired mapping"
5590 * If the page table page is missing and the mapping
5591 * is for a kernel address, the mapping must belong to
5592 * the direct map. Page table pages are preallocated
5593 * for every other part of the kernel address space,
5594 * so the direct map region is the only part of the
5595 * kernel address space that must be handled here.
5597 KASSERT(va < VM_MAXUSER_ADDRESS || VIRT_IN_DMAP(va),
5598 ("pmap_demote_l2: No saved mpte for va %#lx", va));
5601 * If the 2MB page mapping belongs to the direct map
5602 * region of the kernel's address space, then the page
5603 * allocation request specifies the highest possible
5604 * priority (VM_ALLOC_INTERRUPT). Otherwise, the
5605 * priority is normal.
5607 ml3 = vm_page_alloc(NULL, pmap_l2_pindex(va),
5608 (VIRT_IN_DMAP(va) ? VM_ALLOC_INTERRUPT : VM_ALLOC_NORMAL) |
5609 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED);
5612 * If the allocation of the new page table page fails,
5613 * invalidate the 2MB page mapping and return "failure".
5616 pmap_demote_l2_abort(pmap, va, l2, lockp);
5617 CTR2(KTR_PMAP, "pmap_demote_l2: failure for va %#lx"
5618 " in pmap %p", va, pmap);
5622 if (va < VM_MAXUSER_ADDRESS) {
5623 ml3->ref_count = NL3PG;
5624 pmap_resident_count_inc(pmap, 1);
5627 l3phys = VM_PAGE_TO_PHYS(ml3);
5628 l3 = (pt_entry_t *)PHYS_TO_DMAP(l3phys);
5629 newl3 = (oldl2 & ~ATTR_DESCR_MASK) | L3_PAGE;
5630 KASSERT((oldl2 & (ATTR_AP_RW_BIT | ATTR_SW_DBM)) !=
5631 (ATTR_AP(ATTR_AP_RO) | ATTR_SW_DBM),
5632 ("pmap_demote_l2: L2 entry is writeable but not dirty"));
5635 * If the page table page is not leftover from an earlier promotion,
5636 * or the mapping attributes have changed, (re)initialize the L3 table.
5638 * When pmap_update_entry() clears the old L2 mapping, it (indirectly)
5639 * performs a dsb(). That dsb() ensures that the stores for filling
5640 * "l3" are visible before "l3" is added to the page table.
5642 if (ml3->valid == 0 || (l3[0] & ATTR_MASK) != (newl3 & ATTR_MASK))
5643 pmap_fill_l3(l3, newl3);
5646 * Map the temporary page so we don't lose access to the l2 table.
5649 pmap_kenter(tmpl2, PAGE_SIZE,
5650 DMAP_TO_PHYS((vm_offset_t)l2) & ~L3_OFFSET,
5651 VM_MEMATTR_WRITE_BACK);
5652 l2 = (pt_entry_t *)(tmpl2 + ((vm_offset_t)l2 & PAGE_MASK));
5656 * The spare PV entries must be reserved prior to demoting the
5657 * mapping, that is, prior to changing the PDE. Otherwise, the state
5658 * of the L2 and the PV lists will be inconsistent, which can result
5659 * in reclaim_pv_chunk() attempting to remove a PV entry from the
5660 * wrong PV list and pmap_pv_demote_l2() failing to find the expected
5661 * PV entry for the 2MB page mapping that is being demoted.
5663 if ((oldl2 & ATTR_SW_MANAGED) != 0)
5664 reserve_pv_entries(pmap, Ln_ENTRIES - 1, lockp);
5667 * Pass PAGE_SIZE so that a single TLB invalidation is performed on
5668 * the 2MB page mapping.
5670 pmap_update_entry(pmap, l2, l3phys | L2_TABLE, va, PAGE_SIZE);
5673 * Demote the PV entry.
5675 if ((oldl2 & ATTR_SW_MANAGED) != 0)
5676 pmap_pv_demote_l2(pmap, va, oldl2 & ~ATTR_MASK, lockp);
5678 atomic_add_long(&pmap_l2_demotions, 1);
5679 CTR3(KTR_PMAP, "pmap_demote_l2: success for va %#lx"
5680 " in pmap %p %lx", va, pmap, l3[0]);
5684 pmap_kremove(tmpl2);
5685 kva_free(tmpl2, PAGE_SIZE);
5693 pmap_demote_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t va)
5695 struct rwlock *lock;
5699 l3 = pmap_demote_l2_locked(pmap, l2, va, &lock);
5706 * Perform the pmap work for mincore(2). If the page is not both referenced and
5707 * modified by this pmap, returns its physical address so that the caller can
5708 * find other mappings.
5711 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *pap)
5713 pt_entry_t *pte, tpte;
5714 vm_paddr_t mask, pa;
5719 pte = pmap_pte(pmap, addr, &lvl);
5721 tpte = pmap_load(pte);
5734 panic("pmap_mincore: invalid level %d", lvl);
5737 managed = (tpte & ATTR_SW_MANAGED) != 0;
5738 val = MINCORE_INCORE;
5740 val |= MINCORE_SUPER;
5741 if ((managed && pmap_pte_dirty(tpte)) || (!managed &&
5742 (tpte & ATTR_AP_RW_BIT) == ATTR_AP(ATTR_AP_RW)))
5743 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
5744 if ((tpte & ATTR_AF) == ATTR_AF)
5745 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
5747 pa = (tpte & ~ATTR_MASK) | (addr & mask);
5753 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
5754 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) && managed) {
5762 * Garbage collect every ASID that is neither active on a processor nor
5766 pmap_reset_asid_set(void)
5769 int asid, cpuid, epoch;
5771 mtx_assert(&asid_set_mutex, MA_OWNED);
5774 * Ensure that the store to asid_epoch is globally visible before the
5775 * loads from pc_curpmap are performed.
5777 epoch = asid_epoch + 1;
5778 if (epoch == INT_MAX)
5782 __asm __volatile("tlbi vmalle1is");
5784 bit_nclear(asid_set, ASID_FIRST_AVAILABLE, asid_set_size - 1);
5785 CPU_FOREACH(cpuid) {
5786 if (cpuid == curcpu)
5788 pmap = pcpu_find(cpuid)->pc_curpmap;
5789 asid = COOKIE_TO_ASID(pmap->pm_cookie);
5792 bit_set(asid_set, asid);
5793 pmap->pm_cookie = COOKIE_FROM(asid, epoch);
5798 * Allocate a new ASID for the specified pmap.
5801 pmap_alloc_asid(pmap_t pmap)
5805 mtx_lock_spin(&asid_set_mutex);
5808 * While this processor was waiting to acquire the asid set mutex,
5809 * pmap_reset_asid_set() running on another processor might have
5810 * updated this pmap's cookie to the current epoch. In which case, we
5811 * don't need to allocate a new ASID.
5813 if (COOKIE_TO_EPOCH(pmap->pm_cookie) == asid_epoch)
5816 bit_ffc_at(asid_set, asid_next, asid_set_size, &new_asid);
5817 if (new_asid == -1) {
5818 bit_ffc_at(asid_set, ASID_FIRST_AVAILABLE, asid_next,
5820 if (new_asid == -1) {
5821 pmap_reset_asid_set();
5822 bit_ffc_at(asid_set, ASID_FIRST_AVAILABLE,
5823 asid_set_size, &new_asid);
5824 KASSERT(new_asid != -1, ("ASID allocation failure"));
5827 bit_set(asid_set, new_asid);
5828 asid_next = new_asid + 1;
5829 pmap->pm_cookie = COOKIE_FROM(new_asid, asid_epoch);
5831 mtx_unlock_spin(&asid_set_mutex);
5835 * Compute the value that should be stored in ttbr0 to activate the specified
5836 * pmap. This value may change from time to time.
5839 pmap_to_ttbr0(pmap_t pmap)
5842 return (ASID_TO_OPERAND(COOKIE_TO_ASID(pmap->pm_cookie)) |
5847 pmap_activate_int(pmap_t pmap)
5851 KASSERT(PCPU_GET(curpmap) != NULL, ("no active pmap"));
5852 KASSERT(pmap != kernel_pmap, ("kernel pmap activation"));
5853 if (pmap == PCPU_GET(curpmap)) {
5855 * Handle the possibility that the old thread was preempted
5856 * after an "ic" or "tlbi" instruction but before it performed
5857 * a "dsb" instruction. If the old thread migrates to a new
5858 * processor, its completion of a "dsb" instruction on that
5859 * new processor does not guarantee that the "ic" or "tlbi"
5860 * instructions performed on the old processor have completed.
5867 * Ensure that the store to curpmap is globally visible before the
5868 * load from asid_epoch is performed.
5870 PCPU_SET(curpmap, pmap);
5872 epoch = COOKIE_TO_EPOCH(pmap->pm_cookie);
5873 if (epoch >= 0 && epoch != asid_epoch)
5874 pmap_alloc_asid(pmap);
5876 set_ttbr0(pmap_to_ttbr0(pmap));
5877 if (PCPU_GET(bcast_tlbi_workaround) != 0)
5878 invalidate_local_icache();
5883 pmap_activate(struct thread *td)
5887 pmap = vmspace_pmap(td->td_proc->p_vmspace);
5889 (void)pmap_activate_int(pmap);
5894 * To eliminate the unused parameter "old", we would have to add an instruction
5898 pmap_switch(struct thread *old __unused, struct thread *new)
5900 pcpu_bp_harden bp_harden;
5903 /* Store the new curthread */
5904 PCPU_SET(curthread, new);
5906 /* And the new pcb */
5908 PCPU_SET(curpcb, pcb);
5911 * TODO: We may need to flush the cache here if switching
5912 * to a user process.
5915 if (pmap_activate_int(vmspace_pmap(new->td_proc->p_vmspace))) {
5917 * Stop userspace from training the branch predictor against
5918 * other processes. This will call into a CPU specific
5919 * function that clears the branch predictor state.
5921 bp_harden = PCPU_GET(bp_harden);
5922 if (bp_harden != NULL)
5930 pmap_sync_icache(pmap_t pmap, vm_offset_t va, vm_size_t sz)
5933 if (va >= VM_MIN_KERNEL_ADDRESS) {
5934 cpu_icache_sync_range(va, sz);
5939 /* Find the length of data in this page to flush */
5940 offset = va & PAGE_MASK;
5941 len = imin(PAGE_SIZE - offset, sz);
5944 /* Extract the physical address & find it in the DMAP */
5945 pa = pmap_extract(pmap, va);
5947 cpu_icache_sync_range(PHYS_TO_DMAP(pa), len);
5949 /* Move to the next page */
5952 /* Set the length for the next iteration */
5953 len = imin(PAGE_SIZE, sz);
5959 pmap_fault(pmap_t pmap, uint64_t esr, uint64_t far)
5961 pt_entry_t pte, *ptep;
5968 ec = ESR_ELx_EXCEPTION(esr);
5970 case EXCP_INSN_ABORT_L:
5971 case EXCP_INSN_ABORT:
5972 case EXCP_DATA_ABORT_L:
5973 case EXCP_DATA_ABORT:
5979 /* Data and insn aborts use same encoding for FSC field. */
5980 switch (esr & ISS_DATA_DFSC_MASK) {
5981 case ISS_DATA_DFSC_AFF_L1:
5982 case ISS_DATA_DFSC_AFF_L2:
5983 case ISS_DATA_DFSC_AFF_L3:
5985 ptep = pmap_pte(pmap, far, &lvl);
5987 pmap_set_bits(ptep, ATTR_AF);
5990 * XXXMJ as an optimization we could mark the entry
5991 * dirty if this is a write fault.
5996 case ISS_DATA_DFSC_PF_L1:
5997 case ISS_DATA_DFSC_PF_L2:
5998 case ISS_DATA_DFSC_PF_L3:
5999 if ((ec != EXCP_DATA_ABORT_L && ec != EXCP_DATA_ABORT) ||
6000 (esr & ISS_DATA_WnR) == 0)
6003 ptep = pmap_pte(pmap, far, &lvl);
6005 ((pte = pmap_load(ptep)) & ATTR_SW_DBM) != 0) {
6006 if ((pte & ATTR_AP_RW_BIT) == ATTR_AP(ATTR_AP_RO)) {
6007 pmap_clear_bits(ptep, ATTR_AP_RW_BIT);
6008 pmap_invalidate_page(pmap, far);
6014 case ISS_DATA_DFSC_TF_L0:
6015 case ISS_DATA_DFSC_TF_L1:
6016 case ISS_DATA_DFSC_TF_L2:
6017 case ISS_DATA_DFSC_TF_L3:
6019 * Retry the translation. A break-before-make sequence can
6020 * produce a transient fault.
6022 if (pmap == kernel_pmap) {
6024 * The translation fault may have occurred within a
6025 * critical section. Therefore, we must check the
6026 * address without acquiring the kernel pmap's lock.
6028 if (pmap_kextract(far) != 0)
6032 /* Ask the MMU to check the address. */
6033 intr = intr_disable();
6034 par = arm64_address_translate_s1e0r(far);
6039 * If the translation was successful, then we can
6040 * return success to the trap handler.
6042 if (PAR_SUCCESS(par))
6052 * Increase the starting virtual address of the given mapping if a
6053 * different alignment might result in more superpage mappings.
6056 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
6057 vm_offset_t *addr, vm_size_t size)
6059 vm_offset_t superpage_offset;
6063 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
6064 offset += ptoa(object->pg_color);
6065 superpage_offset = offset & L2_OFFSET;
6066 if (size - ((L2_SIZE - superpage_offset) & L2_OFFSET) < L2_SIZE ||
6067 (*addr & L2_OFFSET) == superpage_offset)
6069 if ((*addr & L2_OFFSET) < superpage_offset)
6070 *addr = (*addr & ~L2_OFFSET) + superpage_offset;
6072 *addr = ((*addr + L2_OFFSET) & ~L2_OFFSET) + superpage_offset;
6076 * Get the kernel virtual address of a set of physical pages. If there are
6077 * physical addresses not covered by the DMAP perform a transient mapping
6078 * that will be removed when calling pmap_unmap_io_transient.
6080 * \param page The pages the caller wishes to obtain the virtual
6081 * address on the kernel memory map.
6082 * \param vaddr On return contains the kernel virtual memory address
6083 * of the pages passed in the page parameter.
6084 * \param count Number of pages passed in.
6085 * \param can_fault TRUE if the thread using the mapped pages can take
6086 * page faults, FALSE otherwise.
6088 * \returns TRUE if the caller must call pmap_unmap_io_transient when
6089 * finished or FALSE otherwise.
6093 pmap_map_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
6094 boolean_t can_fault)
6097 boolean_t needs_mapping;
6101 * Allocate any KVA space that we need, this is done in a separate
6102 * loop to prevent calling vmem_alloc while pinned.
6104 needs_mapping = FALSE;
6105 for (i = 0; i < count; i++) {
6106 paddr = VM_PAGE_TO_PHYS(page[i]);
6107 if (__predict_false(!PHYS_IN_DMAP(paddr))) {
6108 error = vmem_alloc(kernel_arena, PAGE_SIZE,
6109 M_BESTFIT | M_WAITOK, &vaddr[i]);
6110 KASSERT(error == 0, ("vmem_alloc failed: %d", error));
6111 needs_mapping = TRUE;
6113 vaddr[i] = PHYS_TO_DMAP(paddr);
6117 /* Exit early if everything is covered by the DMAP */
6123 for (i = 0; i < count; i++) {
6124 paddr = VM_PAGE_TO_PHYS(page[i]);
6125 if (!PHYS_IN_DMAP(paddr)) {
6127 "pmap_map_io_transient: TODO: Map out of DMAP data");
6131 return (needs_mapping);
6135 pmap_unmap_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
6136 boolean_t can_fault)
6143 for (i = 0; i < count; i++) {
6144 paddr = VM_PAGE_TO_PHYS(page[i]);
6145 if (!PHYS_IN_DMAP(paddr)) {
6146 panic("ARM64TODO: pmap_unmap_io_transient: Unmap data");
6152 pmap_is_valid_memattr(pmap_t pmap __unused, vm_memattr_t mode)
6155 return (mode >= VM_MEMATTR_DEVICE && mode <= VM_MEMATTR_WRITE_THROUGH);
6159 * Track a range of the kernel's virtual address space that is contiguous
6160 * in various mapping attributes.
6162 struct pmap_kernel_map_range {
6172 sysctl_kmaps_dump(struct sbuf *sb, struct pmap_kernel_map_range *range,
6178 if (eva <= range->sva)
6181 index = range->attrs & ATTR_IDX_MASK;
6183 case ATTR_IDX(VM_MEMATTR_DEVICE):
6186 case ATTR_IDX(VM_MEMATTR_UNCACHEABLE):
6189 case ATTR_IDX(VM_MEMATTR_WRITE_BACK):
6192 case ATTR_IDX(VM_MEMATTR_WRITE_THROUGH):
6197 "%s: unknown memory type %x for range 0x%016lx-0x%016lx\n",
6198 __func__, index, range->sva, eva);
6203 sbuf_printf(sb, "0x%016lx-0x%016lx r%c%c%c %3s %d %d %d %d\n",
6205 (range->attrs & ATTR_AP_RW_BIT) == ATTR_AP_RW ? 'w' : '-',
6206 (range->attrs & ATTR_PXN) != 0 ? '-' : 'x',
6207 (range->attrs & ATTR_AP_USER) != 0 ? 'u' : 's',
6208 mode, range->l1blocks, range->l2blocks, range->l3contig,
6211 /* Reset to sentinel value. */
6212 range->sva = 0xfffffffffffffffful;
6216 * Determine whether the attributes specified by a page table entry match those
6217 * being tracked by the current range.
6220 sysctl_kmaps_match(struct pmap_kernel_map_range *range, pt_entry_t attrs)
6223 return (range->attrs == attrs);
6227 sysctl_kmaps_reinit(struct pmap_kernel_map_range *range, vm_offset_t va,
6231 memset(range, 0, sizeof(*range));
6233 range->attrs = attrs;
6237 * Given a leaf PTE, derive the mapping's attributes. If they do not match
6238 * those of the current run, dump the address range and its attributes, and
6242 sysctl_kmaps_check(struct sbuf *sb, struct pmap_kernel_map_range *range,
6243 vm_offset_t va, pd_entry_t l0e, pd_entry_t l1e, pd_entry_t l2e,
6248 attrs = l0e & (ATTR_AP_MASK | ATTR_XN);
6249 attrs |= l1e & (ATTR_AP_MASK | ATTR_XN);
6250 if ((l1e & ATTR_DESCR_MASK) == L1_BLOCK)
6251 attrs |= l1e & ATTR_IDX_MASK;
6252 attrs |= l2e & (ATTR_AP_MASK | ATTR_XN);
6253 if ((l2e & ATTR_DESCR_MASK) == L2_BLOCK)
6254 attrs |= l2e & ATTR_IDX_MASK;
6255 attrs |= l3e & (ATTR_AP_MASK | ATTR_XN | ATTR_IDX_MASK);
6257 if (range->sva > va || !sysctl_kmaps_match(range, attrs)) {
6258 sysctl_kmaps_dump(sb, range, va);
6259 sysctl_kmaps_reinit(range, va, attrs);
6264 sysctl_kmaps(SYSCTL_HANDLER_ARGS)
6266 struct pmap_kernel_map_range range;
6267 struct sbuf sbuf, *sb;
6268 pd_entry_t l0e, *l1, l1e, *l2, l2e;
6269 pt_entry_t *l3, l3e;
6272 int error, i, j, k, l;
6274 error = sysctl_wire_old_buffer(req, 0);
6278 sbuf_new_for_sysctl(sb, NULL, PAGE_SIZE, req);
6280 /* Sentinel value. */
6281 range.sva = 0xfffffffffffffffful;
6284 * Iterate over the kernel page tables without holding the kernel pmap
6285 * lock. Kernel page table pages are never freed, so at worst we will
6286 * observe inconsistencies in the output.
6288 for (sva = 0xffff000000000000ul, i = pmap_l0_index(sva); i < Ln_ENTRIES;
6290 if (i == pmap_l0_index(DMAP_MIN_ADDRESS))
6291 sbuf_printf(sb, "\nDirect map:\n");
6292 else if (i == pmap_l0_index(VM_MIN_KERNEL_ADDRESS))
6293 sbuf_printf(sb, "\nKernel map:\n");
6295 l0e = kernel_pmap->pm_l0[i];
6296 if ((l0e & ATTR_DESCR_VALID) == 0) {
6297 sysctl_kmaps_dump(sb, &range, sva);
6301 pa = l0e & ~ATTR_MASK;
6302 l1 = (pd_entry_t *)PHYS_TO_DMAP(pa);
6304 for (j = pmap_l1_index(sva); j < Ln_ENTRIES; j++) {
6306 if ((l1e & ATTR_DESCR_VALID) == 0) {
6307 sysctl_kmaps_dump(sb, &range, sva);
6311 if ((l1e & ATTR_DESCR_MASK) == L1_BLOCK) {
6312 sysctl_kmaps_check(sb, &range, sva, l0e, l1e,
6318 pa = l1e & ~ATTR_MASK;
6319 l2 = (pd_entry_t *)PHYS_TO_DMAP(pa);
6321 for (k = pmap_l2_index(sva); k < Ln_ENTRIES; k++) {
6323 if ((l2e & ATTR_DESCR_VALID) == 0) {
6324 sysctl_kmaps_dump(sb, &range, sva);
6328 if ((l2e & ATTR_DESCR_MASK) == L2_BLOCK) {
6329 sysctl_kmaps_check(sb, &range, sva,
6335 pa = l2e & ~ATTR_MASK;
6336 l3 = (pt_entry_t *)PHYS_TO_DMAP(pa);
6338 for (l = pmap_l3_index(sva); l < Ln_ENTRIES;
6339 l++, sva += L3_SIZE) {
6341 if ((l3e & ATTR_DESCR_VALID) == 0) {
6342 sysctl_kmaps_dump(sb, &range,
6346 sysctl_kmaps_check(sb, &range, sva,
6347 l0e, l1e, l2e, l3e);
6348 if ((l3e & ATTR_CONTIGUOUS) != 0)
6349 range.l3contig += l % 16 == 0 ?
6358 error = sbuf_finish(sb);
6362 SYSCTL_OID(_vm_pmap, OID_AUTO, kernel_maps,
6363 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE,
6364 NULL, 0, sysctl_kmaps, "A",
6365 "Dump kernel address layout");