sys/arm64/rockchip/clk/rk3399_cru.c

   1 /*-
   2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
   3  *
   4  * Copyright (c) 2018 Emmanuel Vadot <manu@freebsd.org>
   5  * Copyright (c) 2018 Greg V <greg@unrelenting.technology>
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  17  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  18  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  19  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  20  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  21  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  23  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  24  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  26  * SUCH DAMAGE.
  27  *
  28  * $FreeBSD$
  29  */
  30
  31 #include <sys/cdefs.h>
  32 __FBSDID("$FreeBSD$");
  33
  34 #include <sys/param.h>
  35 #include <sys/systm.h>
  36 #include <sys/bus.h>
  37 #include <sys/rman.h>
  38 #include <sys/kernel.h>
  39 #include <sys/module.h>
  40 #include <machine/bus.h>
  41
  42 #include <dev/fdt/simplebus.h>
  43
  44 #include <dev/ofw/ofw_bus.h>
  45 #include <dev/ofw/ofw_bus_subr.h>
  46
  47 #include <dev/extres/clk/clk_div.h>
  48 #include <dev/extres/clk/clk_fixed.h>
  49 #include <dev/extres/clk/clk_mux.h>
  50
  51 #include <arm64/rockchip/clk/rk_cru.h>
  52
  53 /* GATES */
  54
  55 #define ACLK_EMMC_CORE          241
  56 #define ACLK_EMMC_NOC           242
  57 #define ACLK_EMMC_GRF           243
  58 #define PCLK_GPIO2              336
  59 #define PCLK_GPIO3              337
  60 #define PCLK_GPIO4              338
  61 #define PCLK_I2C1               341
  62 #define PCLK_I2C2               342
  63 #define PCLK_I2C3               343
  64 #define PCLK_I2C5               344
  65 #define PCLK_I2C6               345
  66 #define PCLK_I2C7               346
  67 #define HCLK_SDMMC              462
  68
  69 static struct rk_cru_gate rk3399_gates[] = {
  70         /* CRU_CLKGATE_CON0 */
  71         CRU_GATE(0, "clk_core_l_lpll_src", "lpll", 0x300, 0)
  72         CRU_GATE(0, "clk_core_l_bpll_src", "bpll", 0x300, 1)
  73         CRU_GATE(0, "clk_core_l_dpll_src", "dpll", 0x300, 2)
  74         CRU_GATE(0, "clk_core_l_gpll_src", "gpll", 0x300, 3)
  75
  76         /* CRU_CLKGATE_CON1 */
  77         CRU_GATE(0, "clk_core_b_lpll_src", "lpll", 0x304, 0)
  78         CRU_GATE(0, "clk_core_b_bpll_src", "bpll", 0x304, 1)
  79         CRU_GATE(0, "clk_core_b_dpll_src", "dpll", 0x304, 2)
  80         CRU_GATE(0, "clk_core_b_gpll_src", "gpll", 0x304, 3)
  81
  82         /* CRU_CLKGATE_CON5 */
  83         CRU_GATE(0, "cpll_aclk_perihp_src", "cpll", 0x314, 0)
  84         CRU_GATE(0, "gpll_aclk_perihp_src", "gpll", 0x314, 1)
  85
  86         /* CRU_CLKGATE_CON6 */
  87         CRU_GATE(0, "gpll_aclk_emmc_src", "gpll", 0x318, 12)
  88         CRU_GATE(0, "cpll_aclk_emmc_src", "cpll", 0x318, 13)
  89
  90         /* CRU_CLKGATE_CON7 */
  91         CRU_GATE(0, "gpll_aclk_perilp0_src", "gpll", 0x31C, 0)
  92         CRU_GATE(0, "cpll_aclk_perilp0_src", "cpll", 0x31C, 1)
  93
  94         /* CRU_CLKGATE_CON8 */
  95         CRU_GATE(0, "hclk_perilp1_cpll_src", "cpll", 0x320, 1)
  96         CRU_GATE(0, "hclk_perilp1_gpll_src", "gpll", 0x320, 0)
  97
  98         /* CRU_CLKGATE_CON22 */
  99         CRU_GATE(PCLK_I2C7, "pclk_rki2c7", "pclk_perilp1", 0x358, 5)
 100         CRU_GATE(PCLK_I2C1, "pclk_rki2c1", "pclk_perilp1", 0x358, 6)
 101         CRU_GATE(PCLK_I2C5, "pclk_rki2c5", "pclk_perilp1", 0x358, 7)
 102         CRU_GATE(PCLK_I2C6, "pclk_rki2c6", "pclk_perilp1", 0x358, 8)
 103         CRU_GATE(PCLK_I2C2, "pclk_rki2c2", "pclk_perilp1", 0x358, 9)
 104         CRU_GATE(PCLK_I2C3, "pclk_rki2c3", "pclk_perilp1", 0x358, 10)
 105
 106         /* CRU_CLKGATE_CON31 */
 107         CRU_GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_alive", 0x37c, 3)
 108         CRU_GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_alive", 0x37c, 4)
 109         CRU_GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_alive", 0x37c, 5)
 110
 111         /* CRU_CLKGATE_CON32 */
 112         CRU_GATE(ACLK_EMMC_CORE, "aclk_emmccore", "aclk_emmc", 0x380, 8)
 113         CRU_GATE(ACLK_EMMC_NOC, "aclk_emmc_noc", "aclk_emmc", 0x380, 9)
 114         CRU_GATE(ACLK_EMMC_GRF, "aclk_emmcgrf", "aclk_emmc", 0x380, 10)
 115
 116         /* CRU_CLKGATE_CON33 */
 117         CRU_GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_sd", 0x384, 8)
 118 };
 119
 120
 121 /*
 122  * PLLs
 123  */
 124
 125 #define PLL_APLLL                       1
 126 #define PLL_APLLB                       2
 127 #define PLL_DPLL                        3
 128 #define PLL_CPLL                        4
 129 #define PLL_GPLL                        5
 130 #define PLL_NPLL                        6
 131 #define PLL_VPLL                        7
 132
 133 static struct rk_clk_pll_rate rk3399_pll_rates[] = {
 134         {
 135                 .freq = 2208000000,
 136                 .refdiv = 1,
 137                 .fbdiv = 92,
 138                 .postdiv1 = 1,
 139                 .postdiv2 = 1,
 140                 .dsmpd = 1,
 141         },
 142         {
 143                 .freq = 2184000000,
 144                 .refdiv = 1,
 145                 .fbdiv = 91,
 146                 .postdiv1 = 1,
 147                 .postdiv2 = 1,
 148                 .dsmpd = 1,
 149         },
 150         {
 151                 .freq = 2160000000,
 152                 .refdiv = 1,
 153                 .fbdiv = 90,
 154                 .postdiv1 = 1,
 155                 .postdiv2 = 1,
 156                 .dsmpd = 1,
 157         },
 158         {
 159                 .freq = 2136000000,
 160                 .refdiv = 1,
 161                 .fbdiv = 89,
 162                 .postdiv1 = 1,
 163                 .postdiv2 = 1,
 164                 .dsmpd = 1,
 165         },
 166         {
 167                 .freq = 2112000000,
 168                 .refdiv = 1,
 169                 .fbdiv = 88,
 170                 .postdiv1 = 1,
 171                 .postdiv2 = 1,
 172                 .dsmpd = 1,
 173         },
 174         {
 175                 .freq = 2088000000,
 176                 .refdiv = 1,
 177                 .fbdiv = 87,
 178                 .postdiv1 = 1,
 179                 .postdiv2 = 1,
 180                 .dsmpd = 1,
 181         },
 182         {
 183                 .freq = 2064000000,
 184                 .refdiv = 1,
 185                 .fbdiv = 86,
 186                 .postdiv1 = 1,
 187                 .postdiv2 = 1,
 188                 .dsmpd = 1,
 189         },
 190         {
 191                 .freq = 2040000000,
 192                 .refdiv = 1,
 193                 .fbdiv = 85,
 194                 .postdiv1 = 1,
 195                 .postdiv2 = 1,
 196                 .dsmpd = 1,
 197         },
 198         {
 199                 .freq = 2016000000,
 200                 .refdiv = 1,
 201                 .fbdiv = 84,
 202                 .postdiv1 = 1,
 203                 .postdiv2 = 1,
 204                 .dsmpd = 1,
 205         },
 206         {
 207                 .freq = 1992000000,
 208                 .refdiv = 1,
 209                 .fbdiv = 83,
 210                 .postdiv1 = 1,
 211                 .postdiv2 = 1,
 212                 .dsmpd = 1,
 213         },
 214         {
 215                 .freq = 1968000000,
 216                 .refdiv = 1,
 217                 .fbdiv = 82,
 218                 .postdiv1 = 1,
 219                 .postdiv2 = 1,
 220                 .dsmpd = 1,
 221         },
 222         {
 223                 .freq = 1944000000,
 224                 .refdiv = 1,
 225                 .fbdiv = 81,
 226                 .postdiv1 = 1,
 227                 .postdiv2 = 1,
 228                 .dsmpd = 1,
 229         },
 230         {
 231                 .freq = 1920000000,
 232                 .refdiv = 1,
 233                 .fbdiv = 80,
 234                 .postdiv1 = 1,
 235                 .postdiv2 = 1,
 236                 .dsmpd = 1,
 237         },
 238         {
 239                 .freq = 1896000000,
 240                 .refdiv = 1,
 241                 .fbdiv = 79,
 242                 .postdiv1 = 1,
 243                 .postdiv2 = 1,
 244                 .dsmpd = 1,
 245         },
 246         {
 247                 .freq = 1872000000,
 248                 .refdiv = 1,
 249                 .fbdiv = 78,
 250                 .postdiv1 = 1,
 251                 .postdiv2 = 1,
 252                 .dsmpd = 1,
 253         },
 254         {
 255                 .freq = 1848000000,
 256                 .refdiv = 1,
 257                 .fbdiv = 77,
 258                 .postdiv1 = 1,
 259                 .postdiv2 = 1,
 260                 .dsmpd = 1,
 261         },
 262         {
 263                 .freq = 1824000000,
 264                 .refdiv = 1,
 265                 .fbdiv = 76,
 266                 .postdiv1 = 1,
 267                 .postdiv2 = 1,
 268                 .dsmpd = 1,
 269         },
 270         {
 271                 .freq = 1800000000,
 272                 .refdiv = 1,
 273                 .fbdiv = 75,
 274                 .postdiv1 = 1,
 275                 .postdiv2 = 1,
 276                 .dsmpd = 1,
 277         },
 278         {
 279                 .freq = 1776000000,
 280                 .refdiv = 1,
 281                 .fbdiv = 74,
 282                 .postdiv1 = 1,
 283                 .postdiv2 = 1,
 284                 .dsmpd = 1,
 285         },
 286         {
 287                 .freq = 1752000000,
 288                 .refdiv = 1,
 289                 .fbdiv = 73,
 290                 .postdiv1 = 1,
 291                 .postdiv2 = 1,
 292                 .dsmpd = 1,
 293         },
 294         {
 295                 .freq = 1728000000,
 296                 .refdiv = 1,
 297                 .fbdiv = 72,
 298                 .postdiv1 = 1,
 299                 .postdiv2 = 1,
 300                 .dsmpd = 1,
 301         },
 302         {
 303                 .freq = 1704000000,
 304                 .refdiv = 1,
 305                 .fbdiv = 71,
 306                 .postdiv1 = 1,
 307                 .postdiv2 = 1,
 308                 .dsmpd = 1,
 309         },
 310         {
 311                 .freq = 1680000000,
 312                 .refdiv = 1,
 313                 .fbdiv = 70,
 314                 .postdiv1 = 1,
 315                 .postdiv2 = 1,
 316                 .dsmpd = 1,
 317         },
 318         {
 319                 .freq = 1656000000,
 320                 .refdiv = 1,
 321                 .fbdiv = 69,
 322                 .postdiv1 = 1,
 323                 .postdiv2 = 1,
 324                 .dsmpd = 1,
 325         },
 326         {
 327                 .freq = 1632000000,
 328                 .refdiv = 1,
 329                 .fbdiv = 68,
 330                 .postdiv1 = 1,
 331                 .postdiv2 = 1,
 332                 .dsmpd = 1,
 333         },
 334         {
 335                 .freq = 1608000000,
 336                 .refdiv = 1,
 337                 .fbdiv = 67,
 338                 .postdiv1 = 1,
 339                 .postdiv2 = 1,
 340                 .dsmpd = 1,
 341         },
 342         {
 343                 .freq = 1600000000,
 344                 .refdiv = 3,
 345                 .fbdiv = 200,
 346                 .postdiv1 = 1,
 347                 .postdiv2 = 1,
 348                 .dsmpd = 1,
 349         },
 350         {
 351                 .freq = 1584000000,
 352                 .refdiv = 1,
 353                 .fbdiv = 66,
 354                 .postdiv1 = 1,
 355                 .postdiv2 = 1,
 356                 .dsmpd = 1,
 357         },
 358         {
 359                 .freq = 1560000000,
 360                 .refdiv = 1,
 361                 .fbdiv = 65,
 362                 .postdiv1 = 1,
 363                 .postdiv2 = 1,
 364                 .dsmpd = 1,
 365         },
 366         {
 367                 .freq = 1536000000,
 368                 .refdiv = 1,
 369                 .fbdiv = 64,
 370                 .postdiv1 = 1,
 371                 .postdiv2 = 1,
 372                 .dsmpd = 1,
 373         },
 374         {
 375                 .freq = 1512000000,
 376                 .refdiv = 1,
 377                 .fbdiv = 63,
 378                 .postdiv1 = 1,
 379                 .postdiv2 = 1,
 380                 .dsmpd = 1,
 381         },
 382         {
 383                 .freq = 1488000000,
 384                 .refdiv = 1,
 385                 .fbdiv = 62,
 386                 .postdiv1 = 1,
 387                 .postdiv2 = 1,
 388                 .dsmpd = 1,
 389         },
 390         {
 391                 .freq = 1464000000,
 392                 .refdiv = 1,
 393                 .fbdiv = 61,
 394                 .postdiv1 = 1,
 395                 .postdiv2 = 1,
 396                 .dsmpd = 1,
 397         },
 398         {
 399                 .freq = 1440000000,
 400                 .refdiv = 1,
 401                 .fbdiv = 60,
 402                 .postdiv1 = 1,
 403                 .postdiv2 = 1,
 404                 .dsmpd = 1,
 405         },
 406         {
 407                 .freq = 1416000000,
 408                 .refdiv = 1,
 409                 .fbdiv = 59,
 410                 .postdiv1 = 1,
 411                 .postdiv2 = 1,
 412                 .dsmpd = 1,
 413         },
 414         {
 415                 .freq = 1392000000,
 416                 .refdiv = 1,
 417                 .fbdiv = 58,
 418                 .postdiv1 = 1,
 419                 .postdiv2 = 1,
 420                 .dsmpd = 1,
 421         },
 422         {
 423                 .freq = 1368000000,
 424                 .refdiv = 1,
 425                 .fbdiv = 57,
 426                 .postdiv1 = 1,
 427                 .postdiv2 = 1,
 428                 .dsmpd = 1,
 429         },
 430         {
 431                 .freq = 1344000000,
 432                 .refdiv = 1,
 433                 .fbdiv = 56,
 434                 .postdiv1 = 1,
 435                 .postdiv2 = 1,
 436                 .dsmpd = 1,
 437         },
 438         {
 439                 .freq = 1320000000,
 440                 .refdiv = 1,
 441                 .fbdiv = 55,
 442                 .postdiv1 = 1,
 443                 .postdiv2 = 1,
 444                 .dsmpd = 1,
 445         },
 446         {
 447                 .freq = 1296000000,
 448                 .refdiv = 1,
 449                 .fbdiv = 54,
 450                 .postdiv1 = 1,
 451                 .postdiv2 = 1,
 452                 .dsmpd = 1,
 453         },
 454         {
 455                 .freq = 1272000000,
 456                 .refdiv = 1,
 457                 .fbdiv = 53,
 458                 .postdiv1 = 1,
 459                 .postdiv2 = 1,
 460                 .dsmpd = 1,
 461         },
 462         {
 463                 .freq = 1248000000,
 464                 .refdiv = 1,
 465                 .fbdiv = 52,
 466                 .postdiv1 = 1,
 467                 .postdiv2 = 1,
 468                 .dsmpd = 1,
 469         },
 470         {
 471                 .freq = 1200000000,
 472                 .refdiv = 1,
 473                 .fbdiv = 50,
 474                 .postdiv1 = 1,
 475                 .postdiv2 = 1,
 476                 .dsmpd = 1,
 477         },
 478         {
 479                 .freq = 1188000000,
 480                 .refdiv = 2,
 481                 .fbdiv = 99,
 482                 .postdiv1 = 1,
 483                 .postdiv2 = 1,
 484                 .dsmpd = 1,
 485         },
 486         {
 487                 .freq = 1104000000,
 488                 .refdiv = 1,
 489                 .fbdiv = 46,
 490                 .postdiv1 = 1,
 491                 .postdiv2 = 1,
 492                 .dsmpd = 1,
 493         },
 494         {
 495                 .freq = 1100000000,
 496                 .refdiv = 12,
 497                 .fbdiv = 550,
 498                 .postdiv1 = 1,
 499                 .postdiv2 = 1,
 500                 .dsmpd = 1,
 501         },
 502         {
 503                 .freq = 1008000000,
 504                 .refdiv = 1,
 505                 .fbdiv = 84,
 506                 .postdiv1 = 2,
 507                 .postdiv2 = 1,
 508                 .dsmpd = 1,
 509         },
 510         {
 511                 .freq = 1000000000,
 512                 .refdiv = 1,
 513                 .fbdiv = 125,
 514                 .postdiv1 = 3,
 515                 .postdiv2 = 1,
 516                 .dsmpd = 1,
 517         },
 518         {
 519                 .freq = 984000000,
 520                 .refdiv = 1,
 521                 .fbdiv = 82,
 522                 .postdiv1 = 2,
 523                 .postdiv2 = 1,
 524                 .dsmpd = 1,
 525         },
 526         {
 527                 .freq = 960000000,
 528                 .refdiv = 1,
 529                 .fbdiv = 80,
 530                 .postdiv1 = 2,
 531                 .postdiv2 = 1,
 532                 .dsmpd = 1,
 533         },
 534         {
 535                 .freq = 936000000,
 536                 .refdiv = 1,
 537                 .fbdiv = 78,
 538                 .postdiv1 = 2,
 539                 .postdiv2 = 1,
 540                 .dsmpd = 1,
 541         },
 542         {
 543                 .freq = 912000000,
 544                 .refdiv = 1,
 545                 .fbdiv = 76,
 546                 .postdiv1 = 2,
 547                 .postdiv2 = 1,
 548                 .dsmpd = 1,
 549         },
 550         {
 551                 .freq = 900000000,
 552                 .refdiv = 4,
 553                 .fbdiv = 300,
 554                 .postdiv1 = 2,
 555                 .postdiv2 = 1,
 556                 .dsmpd = 1,
 557         },
 558         {
 559                 .freq = 888000000,
 560                 .refdiv = 1,
 561                 .fbdiv = 74,
 562                 .postdiv1 = 2,
 563                 .postdiv2 = 1,
 564                 .dsmpd = 1,
 565         },
 566         {
 567                 .freq = 864000000,
 568                 .refdiv = 1,
 569                 .fbdiv = 72,
 570                 .postdiv1 = 2,
 571                 .postdiv2 = 1,
 572                 .dsmpd = 1,
 573         },
 574         {
 575                 .freq = 840000000,
 576                 .refdiv = 1,
 577                 .fbdiv = 70,
 578                 .postdiv1 = 2,
 579                 .postdiv2 = 1,
 580                 .dsmpd = 1,
 581         },
 582         {
 583                 .freq = 816000000,
 584                 .refdiv = 1,
 585                 .fbdiv = 68,
 586                 .postdiv1 = 2,
 587                 .postdiv2 = 1,
 588                 .dsmpd = 1,
 589         },
 590         {
 591                 .freq = 800000000,
 592                 .refdiv = 1,
 593                 .fbdiv = 100,
 594                 .postdiv1 = 3,
 595                 .postdiv2 = 1,
 596                 .dsmpd = 1,
 597         },
 598         {
 599                 .freq = 700000000,
 600                 .refdiv = 6,
 601                 .fbdiv = 350,
 602                 .postdiv1 = 2,
 603                 .postdiv2 = 1,
 604                 .dsmpd = 1,
 605         },
 606         {
 607                 .freq = 696000000,
 608                 .refdiv = 1,
 609                 .fbdiv = 58,
 610                 .postdiv1 = 2,
 611                 .postdiv2 = 1,
 612                 .dsmpd = 1,
 613         },
 614         {
 615                 .freq = 676000000,
 616                 .refdiv = 3,
 617                 .fbdiv = 169,
 618                 .postdiv1 = 2,
 619                 .postdiv2 = 1,
 620                 .dsmpd = 1,
 621         },
 622         {
 623                 .freq = 600000000,
 624                 .refdiv = 1,
 625                 .fbdiv = 75,
 626                 .postdiv1 = 3,
 627                 .postdiv2 = 1,
 628                 .dsmpd = 1,
 629         },
 630         {
 631                 .freq = 594000000,
 632                 .refdiv = 1,
 633                 .fbdiv = 99,
 634                 .postdiv1 = 4,
 635                 .postdiv2 = 1,
 636                 .dsmpd = 1,
 637         },
 638         {
 639                 .freq = 533250000,
 640                 .refdiv = 8,
 641                 .fbdiv = 711,
 642                 .postdiv1 = 4,
 643                 .postdiv2 = 1,
 644                 .dsmpd = 1,
 645         },
 646         {
 647                 .freq = 504000000,
 648                 .refdiv = 1,
 649                 .fbdiv = 63,
 650                 .postdiv1 = 3,
 651                 .postdiv2 = 1,
 652                 .dsmpd = 1,
 653         },
 654         {
 655                 .freq = 500000000,
 656                 .refdiv = 6,
 657                 .fbdiv = 250,
 658                 .postdiv1 = 2,
 659                 .postdiv2 = 1,
 660                 .dsmpd = 1,
 661         },
 662         {
 663                 .freq = 408000000,
 664                 .refdiv = 1,
 665                 .fbdiv = 68,
 666                 .postdiv1 = 2,
 667                 .postdiv2 = 2,
 668                 .dsmpd = 1,
 669         },
 670         {
 671                 .freq = 312000000,
 672                 .refdiv = 1,
 673                 .fbdiv = 52,
 674                 .postdiv1 = 2,
 675                 .postdiv2 = 2,
 676                 .dsmpd = 1,
 677         },
 678         {
 679                 .freq = 297000000,
 680                 .refdiv = 1,
 681                 .fbdiv = 99,
 682                 .postdiv1 = 4,
 683                 .postdiv2 = 2,
 684                 .dsmpd = 1,
 685         },
 686         {
 687                 .freq = 216000000,
 688                 .refdiv = 1,
 689                 .fbdiv = 72,
 690                 .postdiv1 = 4,
 691                 .postdiv2 = 2,
 692                 .dsmpd = 1,
 693         },
 694         {
 695                 .freq = 148500000,
 696                 .refdiv = 1,
 697                 .fbdiv = 99,
 698                 .postdiv1 = 4,
 699                 .postdiv2 = 4,
 700                 .dsmpd = 1,
 701         },
 702         {
 703                 .freq = 106500000,
 704                 .refdiv = 1,
 705                 .fbdiv = 71,
 706                 .postdiv1 = 4,
 707                 .postdiv2 = 4,
 708                 .dsmpd = 1,
 709         },
 710         {
 711                 .freq = 96000000,
 712                 .refdiv = 1,
 713                 .fbdiv = 64,
 714                 .postdiv1 = 4,
 715                 .postdiv2 = 4,
 716                 .dsmpd = 1,
 717         },
 718         {
 719                 .freq = 74250000,
 720                 .refdiv = 2,
 721                 .fbdiv = 99,
 722                 .postdiv1 = 4,
 723                 .postdiv2 = 4,
 724                 .dsmpd = 1,
 725         },
 726         {
 727                 .freq = 65000000,
 728                 .refdiv = 1,
 729                 .fbdiv = 65,
 730                 .postdiv1 = 6,
 731                 .postdiv2 = 4,
 732                 .dsmpd = 1,
 733         },
 734         {
 735                 .freq = 54000000,
 736                 .refdiv = 1,
 737                 .fbdiv = 54,
 738                 .postdiv1 = 6,
 739                 .postdiv2 = 4,
 740                 .dsmpd = 1,
 741         },
 742         {
 743                 .freq = 27000000,
 744                 .refdiv = 1,
 745                 .fbdiv = 27,
 746                 .postdiv1 = 6,
 747                 .postdiv2 = 4,
 748                 .dsmpd = 1,
 749         },
 750         {},
 751 };
 752
 753 static const char *pll_parents[] = {"xin24m"};
 754
 755 static struct rk_clk_pll_def lpll = {
 756         .clkdef = {
 757                 .id = PLL_APLLL,
 758                 .name = "lpll",
 759                 .parent_names = pll_parents,
 760                 .parent_cnt = nitems(pll_parents),
 761         },
 762         .base_offset = 0x00,
 763         .gate_offset = 0x300,
 764         .gate_shift = 0,
 765         .flags = RK_CLK_PLL_HAVE_GATE,
 766         .rates = rk3399_pll_rates,
 767         .normal_mode = true,
 768 };
 769
 770 static struct rk_clk_pll_def bpll = {
 771         .clkdef = {
 772                 .id = PLL_APLLB,
 773                 .name = "bpll",
 774                 .parent_names = pll_parents,
 775                 .parent_cnt = nitems(pll_parents),
 776         },
 777         .base_offset = 0x20,
 778         .gate_offset = 0x300,
 779         .gate_shift = 1,
 780         .flags = RK_CLK_PLL_HAVE_GATE,
 781         .rates = rk3399_pll_rates,
 782         .normal_mode = true,
 783 };
 784
 785 static struct rk_clk_pll_def dpll = {
 786         .clkdef = {
 787                 .id = PLL_DPLL,
 788                 .name = "dpll",
 789                 .parent_names = pll_parents,
 790                 .parent_cnt = nitems(pll_parents),
 791         },
 792         .base_offset = 0x40,
 793         .gate_offset = 0x300,
 794         .gate_shift = 2,
 795         .flags = RK_CLK_PLL_HAVE_GATE,
 796         .rates = rk3399_pll_rates,
 797 };
 798
 799
 800 static struct rk_clk_pll_def cpll = {
 801         .clkdef = {
 802                 .id = PLL_CPLL,
 803                 .name = "cpll",
 804                 .parent_names = pll_parents,
 805                 .parent_cnt = nitems(pll_parents),
 806         },
 807         .base_offset = 0x60,
 808         .rates = rk3399_pll_rates,
 809 };
 810
 811 static struct rk_clk_pll_def gpll = {
 812         .clkdef = {
 813                 .id = PLL_GPLL,
 814                 .name = "gpll",
 815                 .parent_names = pll_parents,
 816                 .parent_cnt = nitems(pll_parents),
 817         },
 818         .base_offset = 0x80,
 819         .gate_offset = 0x300,
 820         .gate_shift = 3,
 821         .flags = RK_CLK_PLL_HAVE_GATE,
 822         .rates = rk3399_pll_rates,
 823 };
 824
 825 static struct rk_clk_pll_def npll = {
 826         .clkdef = {
 827                 .id = PLL_NPLL,
 828                 .name = "npll",
 829                 .parent_names = pll_parents,
 830                 .parent_cnt = nitems(pll_parents),
 831         },
 832         .base_offset = 0xa0,
 833         .rates = rk3399_pll_rates,
 834 };
 835
 836 static struct rk_clk_pll_def vpll = {
 837         .clkdef = {
 838                 .id = PLL_VPLL,
 839                 .name = "vpll",
 840                 .parent_names = pll_parents,
 841                 .parent_cnt = nitems(pll_parents),
 842         },
 843         .base_offset = 0xc0,
 844         .rates = rk3399_pll_rates,
 845 };
 846
 847 #define ACLK_PERIHP     192
 848 #define HCLK_PERIHP     448
 849 #define PCLK_PERIHP     320
 850
 851 static const char *aclk_perihp_parents[] = {"cpll_aclk_perihp_src", "gpll_aclk_perihp_src"};
 852
 853 static struct rk_clk_composite_def aclk_perihp = {
 854         .clkdef = {
 855                 .id = ACLK_PERIHP,
 856                 .name = "aclk_perihp",
 857                 .parent_names = aclk_perihp_parents,
 858                 .parent_cnt = nitems(aclk_perihp_parents),
 859         },
 860         /* CRU_CLKSEL_CON14 */
 861         .muxdiv_offset = 0x138,
 862
 863         .mux_shift = 7,
 864         .mux_width = 1,
 865
 866         .div_shift = 0,
 867         .div_width = 5,
 868
 869         /* CRU_CLKGATE_CON5 */
 870         .gate_offset = 0x314,
 871         .gate_shift = 2,
 872
 873         .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
 874 };
 875
 876 static const char *hclk_pclk_perihp_parents[] = {"aclk_perihp"};
 877
 878 static struct rk_clk_composite_def hclk_perihp = {
 879         .clkdef = {
 880                 .id = HCLK_PERIHP,
 881                 .name = "hclk_perihp",
 882                 .parent_names = hclk_pclk_perihp_parents,
 883                 .parent_cnt = nitems(hclk_pclk_perihp_parents),
 884         },
 885         /* CRU_CLKSEL_CON14 */
 886         .muxdiv_offset = 0x138,
 887
 888         .div_shift = 8,
 889         .div_width = 2,
 890
 891         /* CRU_CLKGATE_CON5 */
 892         .gate_offset = 0x314,
 893         .gate_shift = 3,
 894
 895         .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
 896 };
 897
 898 static struct rk_clk_composite_def pclk_perihp = {
 899         .clkdef = {
 900                 .id = PCLK_PERIHP,
 901                 .name = "pclk_perihp",
 902                 .parent_names = hclk_pclk_perihp_parents,
 903                 .parent_cnt = nitems(hclk_pclk_perihp_parents),
 904         },
 905         /* CRU_CLKSEL_CON14 */
 906         .muxdiv_offset = 0x138,
 907
 908         .div_shift = 12,
 909         .div_width = 3,
 910
 911         /* CRU_CLKGATE_CON5 */
 912         .gate_offset = 0x314,
 913         .gate_shift = 4,
 914
 915         .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
 916 };
 917
 918 #define ACLK_PERILP0    194
 919 #define HCLK_PERILP0    449
 920 #define PCLK_PERILP0    322
 921
 922 static const char *aclk_perilp0_parents[] = {"cpll_aclk_perilp0_src", "gpll_aclk_perilp0_src"};
 923
 924 static struct rk_clk_composite_def aclk_perilp0 = {
 925         .clkdef = {
 926                 .id = ACLK_PERILP0,
 927                 .name = "aclk_perilp0",
 928                 .parent_names = aclk_perilp0_parents,
 929                 .parent_cnt = nitems(aclk_perilp0_parents),
 930         },
 931         /* CRU_CLKSEL_CON14 */
 932         .muxdiv_offset = 0x15C,
 933
 934         .mux_shift = 7,
 935         .mux_width = 1,
 936
 937         .div_shift = 0,
 938         .div_width = 5,
 939
 940         /* CRU_CLKGATE_CON7 */
 941         .gate_offset = 0x31C,
 942         .gate_shift = 2,
 943
 944         .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
 945 };
 946
 947 static const char *hclk_pclk_perilp0_parents[] = {"aclk_perilp0"};
 948
 949 static struct rk_clk_composite_def hclk_perilp0 = {
 950         .clkdef = {
 951                 .id = HCLK_PERILP0,
 952                 .name = "hclk_perilp0",
 953                 .parent_names = hclk_pclk_perilp0_parents,
 954                 .parent_cnt = nitems(hclk_pclk_perilp0_parents),
 955         },
 956         /* CRU_CLKSEL_CON23 */
 957         .muxdiv_offset = 0x15C,
 958
 959         .div_shift = 8,
 960         .div_width = 2,
 961
 962         /* CRU_CLKGATE_CON7 */
 963         .gate_offset = 0x31C,
 964         .gate_shift = 3,
 965
 966         .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
 967 };
 968
 969 static struct rk_clk_composite_def pclk_perilp0 = {
 970         .clkdef = {
 971                 .id = PCLK_PERILP0,
 972                 .name = "pclk_perilp0",
 973                 .parent_names = hclk_pclk_perilp0_parents,
 974                 .parent_cnt = nitems(hclk_pclk_perilp0_parents),
 975         },
 976         /* CRU_CLKSEL_CON23 */
 977         .muxdiv_offset = 0x15C,
 978
 979         .div_shift = 12,
 980         .div_width = 3,
 981
 982         /* CRU_CLKGATE_CON7 */
 983         .gate_offset = 0x31C,
 984         .gate_shift = 4,
 985
 986         .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
 987 };
 988
 989 /*
 990  * misc
 991  */
 992 #define PCLK_ALIVE              390
 993
 994 static const char *alive_parents[] = {"gpll"};
 995
 996 static struct rk_clk_composite_def pclk_alive = {
 997         .clkdef = {
 998                 .id = PCLK_ALIVE,
 999                 .name = "pclk_alive",
1000                 .parent_names = alive_parents,
1001                 .parent_cnt = nitems(alive_parents),
1002         },
1003         /* CRU_CLKSEL_CON57 */
1004         .muxdiv_offset = 0x01e4,
1005
1006         .div_shift = 0,
1007         .div_width = 5,
1008 };
1009
1010 #define HCLK_PERILP1            450
1011 #define PCLK_PERILP1            323
1012
1013 static const char *hclk_perilp1_parents[] = {"cpll", "gpll"};
1014
1015 static struct rk_clk_composite_def hclk_perilp1 = {
1016         .clkdef = {
1017                 .id = HCLK_PERILP1,
1018                 .name = "hclk_perilp1",
1019                 .parent_names = hclk_perilp1_parents,
1020                 .parent_cnt = nitems(hclk_perilp1_parents),
1021         },
1022         /* CRU_CLKSEL_CON25 */
1023         .muxdiv_offset = 0x164,
1024         .mux_shift = 7,
1025         .mux_width = 1,
1026
1027         .div_shift = 0,
1028         .div_width = 5,
1029
1030         .flags = RK_CLK_COMPOSITE_HAVE_MUX,
1031 };
1032
1033 static const char *pclk_perilp1_parents[] = {"hclk_perilp1"};
1034
1035 static struct rk_clk_composite_def pclk_perilp1 = {
1036         .clkdef = {
1037                 .id = PCLK_PERILP1,
1038                 .name = "pclk_perilp1",
1039                 .parent_names = pclk_perilp1_parents,
1040                 .parent_cnt = nitems(pclk_perilp1_parents),
1041         },
1042         /* CRU_CLKSEL_CON25 */
1043         .muxdiv_offset = 0x164,
1044
1045         .div_shift = 8,
1046         .div_width = 3,
1047
1048         /* CRU_CLKGATE_CON8 */
1049         .gate_offset = 0x320,
1050         .gate_shift = 2,
1051
1052         .flags = RK_CLK_COMPOSITE_HAVE_GATE,
1053 };
1054
1055 /*
1056  * i2c
1057  */
1058 static const char *i2c_parents[] = {"cpll", "gpll"};
1059
1060 #define SCLK_I2C1       65
1061 #define SCLK_I2C2       66
1062 #define SCLK_I2C3       67
1063 #define SCLK_I2C5       68
1064 #define SCLK_I2C6       69
1065 #define SCLK_I2C7       70
1066
1067 static struct rk_clk_composite_def i2c1 = {
1068         .clkdef = {
1069                 .id = SCLK_I2C1,
1070                 .name = "clk_i2c1",
1071                 .parent_names = i2c_parents,
1072                 .parent_cnt = nitems(i2c_parents),
1073         },
1074         /* CRU_CLKSEL_CON61 */
1075         .muxdiv_offset = 0x01f4,
1076         .mux_shift = 7,
1077         .mux_width = 1,
1078
1079         .div_shift = 0,
1080         .div_width = 7,
1081
1082         /* CRU_CLKGATE_CON10 */
1083         .gate_offset = 0x0328,
1084         .gate_shift = 0,
1085
1086         .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
1087 };
1088
1089 static struct rk_clk_composite_def i2c2 = {
1090         .clkdef = {
1091                 .id = SCLK_I2C2,
1092                 .name = "clk_i2c2",
1093                 .parent_names = i2c_parents,
1094                 .parent_cnt = nitems(i2c_parents),
1095         },
1096         /* CRU_CLKSEL_CON62 */
1097         .muxdiv_offset = 0x01f8,
1098         .mux_shift = 7,
1099         .mux_width = 1,
1100
1101         .div_shift = 0,
1102         .div_width = 7,
1103
1104         /* CRU_CLKGATE_CON10 */
1105         .gate_offset = 0x0328,
1106         .gate_shift = 2,
1107
1108         .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
1109 };
1110
1111 static struct rk_clk_composite_def i2c3 = {
1112         .clkdef = {
1113                 .id = SCLK_I2C3,
1114                 .name = "clk_i2c3",
1115                 .parent_names = i2c_parents,
1116                 .parent_cnt = nitems(i2c_parents),
1117         },
1118         /* CRU_CLKSEL_CON63 */
1119         .muxdiv_offset = 0x01fc,
1120         .mux_shift = 7,
1121         .mux_width = 1,
1122
1123         .div_shift = 0,
1124         .div_width = 7,
1125
1126         /* CRU_CLKGATE_CON10 */
1127         .gate_offset = 0x0328,
1128         .gate_shift = 4,
1129
1130         .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
1131 };
1132
1133 static struct rk_clk_composite_def i2c5 = {
1134         .clkdef = {
1135                 .id = SCLK_I2C5,
1136                 .name = "clk_i2c5",
1137                 .parent_names = i2c_parents,
1138                 .parent_cnt = nitems(i2c_parents),
1139         },
1140         /* CRU_CLKSEL_CON61 */
1141         .muxdiv_offset = 0x01f4,
1142         .mux_shift = 15,
1143         .mux_width = 1,
1144
1145         .div_shift = 8,
1146         .div_width = 7,
1147
1148         /* CRU_CLKGATE_CON10 */
1149         .gate_offset = 0x0328,
1150         .gate_shift = 1,
1151
1152         .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
1153 };
1154
1155 static struct rk_clk_composite_def i2c6 = {
1156         .clkdef = {
1157                 .id = SCLK_I2C6,
1158                 .name = "clk_i2c6",
1159                 .parent_names = i2c_parents,
1160                 .parent_cnt = nitems(i2c_parents),
1161         },
1162         /* CRU_CLKSEL_CON62 */
1163         .muxdiv_offset = 0x01f8,
1164         .mux_shift = 15,
1165         .mux_width = 1,
1166
1167         .div_shift = 8,
1168         .div_width = 7,
1169
1170         /* CRU_CLKGATE_CON10 */
1171         .gate_offset = 0x0328,
1172         .gate_shift = 3,
1173
1174         .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
1175 };
1176
1177 static struct rk_clk_composite_def i2c7 = {
1178         .clkdef = {
1179                 .id = SCLK_I2C7,
1180                 .name = "clk_i2c7",
1181                 .parent_names = i2c_parents,
1182                 .parent_cnt = nitems(i2c_parents),
1183         },
1184         /* CRU_CLKSEL_CON63 */
1185         .muxdiv_offset = 0x01fc,
1186         .mux_shift = 15,
1187         .mux_width = 1,
1188
1189         .div_shift = 8,
1190         .div_width = 7,
1191
1192         /* CRU_CLKGATE_CON10 */
1193         .gate_offset = 0x0328,
1194         .gate_shift = 5,
1195
1196         .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
1197 };
1198
1199 /*
1200  * ARM CPU clocks (LITTLE and big)
1201  */
1202 #define ARMCLKL                         8
1203 #define ARMCLKB                         9
1204
1205 static const char *armclk_parents[] = {"lpll", "bpll", "dpll", "gpll"};
1206
1207 static struct rk_clk_armclk_rates rk3399_armclkl_rates[] = {
1208         {
1209                 .freq = 1800000000,
1210                 .div = 1,
1211         },
1212         {
1213                 .freq = 1704000000,
1214                 .div = 1,
1215         },
1216         {
1217                 .freq = 1608000000,
1218                 .div = 1,
1219         },
1220         {
1221                 .freq = 1512000000,
1222                 .div = 1,
1223         },
1224         {
1225                 .freq = 1488000000,
1226                 .div = 1,
1227         },
1228         {
1229                 .freq = 1416000000,
1230                 .div = 1,
1231         },
1232         {
1233                 .freq = 1200000000,
1234                 .div = 1,
1235         },
1236         {
1237                 .freq = 1008000000,
1238                 .div = 1,
1239         },
1240         {
1241                 .freq = 816000000,
1242                 .div = 1,
1243         },
1244         {
1245                 .freq = 696000000,
1246                 .div = 1,
1247         },
1248         {
1249                 .freq = 600000000,
1250                 .div = 1,
1251         },
1252         {
1253                 .freq = 408000000,
1254                 .div = 1,
1255         },
1256         {
1257                 .freq = 312000000,
1258                 .div = 1,
1259         },
1260         {
1261                 .freq = 216000000,
1262                 .div = 1,
1263         },
1264         {
1265                 .freq = 96000000,
1266                 .div = 1,
1267         },
1268 };
1269
1270 static struct rk_clk_armclk_def armclk_l = {
1271         .clkdef = {
1272                 .id = ARMCLKL,
1273                 .name = "armclkl",
1274                 .parent_names = armclk_parents,
1275                 .parent_cnt = nitems(armclk_parents),
1276         },
1277         /* CRU_CLKSEL_CON0 */
1278         .muxdiv_offset = 0x100,
1279         .mux_shift = 6,
1280         .mux_width = 2,
1281
1282         .div_shift = 0,
1283         .div_width = 5,
1284
1285         .flags = RK_CLK_COMPOSITE_HAVE_MUX,
1286         .main_parent = 0,
1287         .alt_parent = 3,
1288
1289         .rates = rk3399_armclkl_rates,
1290         .nrates = nitems(rk3399_armclkl_rates),
1291 };
1292
1293 static struct rk_clk_armclk_rates rk3399_armclkb_rates[] = {
1294         {
1295                 .freq = 2208000000,
1296                 .div = 1,
1297         },
1298         {
1299                 .freq = 2184000000,
1300                 .div = 1,
1301         },
1302         {
1303                 .freq = 2088000000,
1304                 .div = 1,
1305         },
1306         {
1307                 .freq = 2040000000,
1308                 .div = 1,
1309         },
1310         {
1311                 .freq = 2016000000,
1312                 .div = 1,
1313         },
1314         {
1315                 .freq = 1992000000,
1316                 .div = 1,
1317         },
1318         {
1319                 .freq = 1896000000,
1320                 .div = 1,
1321         },
1322         {
1323                 .freq = 1800000000,
1324                 .div = 1,
1325         },
1326         {
1327                 .freq = 1704000000,
1328                 .div = 1,
1329         },
1330         {
1331                 .freq = 1608000000,
1332                 .div = 1,
1333         },
1334         {
1335                 .freq = 1512000000,
1336                 .div = 1,
1337         },
1338         {
1339                 .freq = 1488000000,
1340                 .div = 1,
1341         },
1342         {
1343                 .freq = 1416000000,
1344                 .div = 1,
1345         },
1346         {
1347                 .freq = 1200000000,
1348                 .div = 1,
1349         },
1350         {
1351                 .freq = 1008000000,
1352                 .div = 1,
1353         },
1354         {
1355                 .freq = 816000000,
1356                 .div = 1,
1357         },
1358         {
1359                 .freq = 696000000,
1360                 .div = 1,
1361         },
1362         {
1363                 .freq = 600000000,
1364                 .div = 1,
1365         },
1366         {
1367                 .freq = 408000000,
1368                 .div = 1,
1369         },
1370         {
1371                 .freq = 312000000,
1372                 .div = 1,
1373         },
1374         {
1375                 .freq = 216000000,
1376                 .div = 1,
1377         },
1378         {
1379                 .freq = 96000000,
1380                 .div = 1,
1381         },
1382 };
1383
1384 static struct rk_clk_armclk_def armclk_b = {
1385         .clkdef = {
1386                 .id = ARMCLKB,
1387                 .name = "armclkb",
1388                 .parent_names = armclk_parents,
1389                 .parent_cnt = nitems(armclk_parents),
1390         },
1391         .muxdiv_offset = 0x108,
1392         .mux_shift = 6,
1393         .mux_width = 2,
1394
1395         .div_shift = 0,
1396         .div_width = 5,
1397
1398         .flags = RK_CLK_COMPOSITE_HAVE_MUX,
1399         .main_parent = 1,
1400         .alt_parent = 3,
1401
1402         .rates = rk3399_armclkb_rates,
1403         .nrates = nitems(rk3399_armclkb_rates),
1404 };
1405
1406 /*
1407  * sdmmc
1408  */
1409
1410 #define HCLK_SD         461
1411
1412 static const char *hclk_sd_parents[] = {"cpll", "gpll"};
1413
1414 static struct rk_clk_composite_def hclk_sd = {
1415         .clkdef = {
1416                 .id = HCLK_SD,
1417                 .name = "hclk_sd",
1418                 .parent_names = hclk_sd_parents,
1419                 .parent_cnt = nitems(hclk_sd_parents),
1420         },
1421
1422         .muxdiv_offset = 0x134,
1423         .mux_shift = 15,
1424         .mux_width = 1,
1425
1426         .div_shift = 8,
1427         .div_width = 5,
1428
1429         .gate_offset = 0x330,
1430         .gate_shift = 13,
1431
1432         .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
1433 };
1434
1435 #define SCLK_SDMMC              76
1436
1437 static const char *sclk_sdmmc_parents[] = {"cpll", "gpll", "npll", "ppll"};
1438
1439 static struct rk_clk_composite_def sclk_sdmmc = {
1440         .clkdef = {
1441                 .id = SCLK_SDMMC,
1442                 .name = "sclk_sdmmc",
1443                 .parent_names = sclk_sdmmc_parents,
1444                 .parent_cnt = nitems(sclk_sdmmc_parents),
1445         },
1446
1447         .muxdiv_offset = 0x140,
1448         .mux_shift = 8,
1449         .mux_width = 3,
1450
1451         .div_shift = 0,
1452         .div_width = 7,
1453
1454         .gate_offset = 0x318,
1455         .gate_shift = 1,
1456
1457         .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
1458 };
1459
1460 /*
1461  * emmc
1462  */
1463
1464 #define SCLK_EMMC               78
1465
1466 static const char *sclk_emmc_parents[] = {"cpll", "gpll", "npll"};
1467
1468 static struct rk_clk_composite_def sclk_emmc = {
1469         .clkdef = {
1470                 .id = SCLK_EMMC,
1471                 .name = "sclk_emmc",
1472                 .parent_names = sclk_emmc_parents,
1473                 .parent_cnt = nitems(sclk_emmc_parents),
1474         },
1475
1476         .muxdiv_offset = 0x158,
1477         .mux_shift = 8,
1478         .mux_width = 3,
1479
1480         .div_shift = 0,
1481         .div_width = 7,
1482
1483         .gate_offset = 0x318,
1484         .gate_shift = 14,
1485
1486         .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
1487 };
1488
1489 #define ACLK_EMMC               240
1490
1491 static const char *aclk_emmc_parents[] = {
1492         "cpll_aclk_emmc_src",
1493         "gpll_aclk_emmc_src"
1494 };
1495
1496 static struct rk_clk_composite_def aclk_emmc = {
1497         .clkdef = {
1498                 .id = ACLK_EMMC,
1499                 .name = "aclk_emmc",
1500                 .parent_names = aclk_emmc_parents,
1501                 .parent_cnt = nitems(aclk_emmc_parents),
1502         },
1503
1504         .muxdiv_offset = 0x154,
1505         .mux_shift = 7,
1506         .mux_width = 1,
1507
1508         .div_shift = 0,
1509         .div_width = 5,
1510
1511         .flags = RK_CLK_COMPOSITE_HAVE_MUX,
1512 };
1513
1514 static struct rk_clk rk3399_clks[] = {
1515         {
1516                 .type = RK3399_CLK_PLL,
1517                 .clk.pll = &lpll
1518         },
1519         {
1520                 .type = RK3399_CLK_PLL,
1521                 .clk.pll = &bpll
1522         },
1523         {
1524                 .type = RK3399_CLK_PLL,
1525                 .clk.pll = &dpll
1526         },
1527         {
1528                 .type = RK3399_CLK_PLL,
1529                 .clk.pll = &cpll
1530         },
1531         {
1532                 .type = RK3399_CLK_PLL,
1533                 .clk.pll = &gpll
1534         },
1535         {
1536                 .type = RK3399_CLK_PLL,
1537                 .clk.pll = &npll
1538         },
1539         {
1540                 .type = RK3399_CLK_PLL,
1541                 .clk.pll = &vpll
1542         },
1543
1544         {
1545                 .type = RK_CLK_COMPOSITE,
1546                 .clk.composite = &aclk_perihp,
1547         },
1548         {
1549                 .type = RK_CLK_COMPOSITE,
1550                 .clk.composite = &hclk_perihp,
1551         },
1552         {
1553                 .type = RK_CLK_COMPOSITE,
1554                 .clk.composite = &pclk_perihp,
1555         },
1556         {
1557                 .type = RK_CLK_COMPOSITE,
1558                 .clk.composite = &aclk_perilp0,
1559         },
1560         {
1561                 .type = RK_CLK_COMPOSITE,
1562                 .clk.composite = &hclk_perilp0,
1563         },
1564         {
1565                 .type = RK_CLK_COMPOSITE,
1566                 .clk.composite = &pclk_perilp0,
1567         },
1568         {
1569                 .type = RK_CLK_COMPOSITE,
1570                 .clk.composite = &pclk_alive,
1571         },
1572         {
1573                 .type = RK_CLK_COMPOSITE,
1574                 .clk.composite = &hclk_perilp1,
1575         },
1576         {
1577                 .type = RK_CLK_COMPOSITE,
1578                 .clk.composite = &pclk_perilp1,
1579         },
1580         {
1581                 .type = RK_CLK_COMPOSITE,
1582                 .clk.composite = &i2c1,
1583         },
1584         {
1585                 .type = RK_CLK_COMPOSITE,
1586                 .clk.composite = &i2c2,
1587         },
1588         {
1589                 .type = RK_CLK_COMPOSITE,
1590                 .clk.composite = &i2c3,
1591         },
1592         {
1593                 .type = RK_CLK_COMPOSITE,
1594                 .clk.composite = &i2c5,
1595         },
1596         {
1597                 .type = RK_CLK_COMPOSITE,
1598                 .clk.composite = &i2c6,
1599         },
1600         {
1601                 .type = RK_CLK_COMPOSITE,
1602                 .clk.composite = &i2c7,
1603         },
1604
1605         {
1606                 .type = RK_CLK_ARMCLK,
1607                 .clk.armclk = &armclk_l,
1608         },
1609         {
1610                 .type = RK_CLK_ARMCLK,
1611                 .clk.armclk = &armclk_b,
1612         },
1613
1614         {
1615                 .type = RK_CLK_COMPOSITE,
1616                 .clk.composite = &hclk_sd,
1617         },
1618         {
1619                 .type = RK_CLK_COMPOSITE,
1620                 .clk.composite = &sclk_sdmmc,
1621         },
1622
1623         {
1624                 .type = RK_CLK_COMPOSITE,
1625                 .clk.composite = &sclk_emmc,
1626         },
1627         {
1628                 .type = RK_CLK_COMPOSITE,
1629                 .clk.composite = &aclk_emmc,
1630         },
1631 };
1632
1633 static int
1634 rk3399_cru_probe(device_t dev)
1635 {
1636
1637         if (!ofw_bus_status_okay(dev))
1638                 return (ENXIO);
1639
1640         if (ofw_bus_is_compatible(dev, "rockchip,rk3399-cru")) {
1641                 device_set_desc(dev, "Rockchip RK3399 Clock and Reset Unit");
1642                 return (BUS_PROBE_DEFAULT);
1643         }
1644
1645         return (ENXIO);
1646 }
1647
1648 static int
1649 rk3399_cru_attach(device_t dev)
1650 {
1651         struct rk_cru_softc *sc;
1652
1653         sc = device_get_softc(dev);
1654         sc->dev = dev;
1655
1656         sc->gates = rk3399_gates;
1657         sc->ngates = nitems(rk3399_gates);
1658
1659         sc->clks = rk3399_clks;
1660         sc->nclks = nitems(rk3399_clks);
1661
1662         return (rk_cru_attach(dev));
1663 }
1664
1665 static device_method_t rk3399_cru_methods[] = {
1666         /* Device interface */
1667         DEVMETHOD(device_probe,         rk3399_cru_probe),
1668         DEVMETHOD(device_attach,        rk3399_cru_attach),
1669
1670         DEVMETHOD_END
1671 };
1672
1673 static devclass_t rk3399_cru_devclass;
1674
1675 DEFINE_CLASS_1(rk3399_cru, rk3399_cru_driver, rk3399_cru_methods,
1676   sizeof(struct rk_cru_softc), rk_cru_driver);
1677
1678 EARLY_DRIVER_MODULE(rk3399_cru, simplebus, rk3399_cru_driver,
1679     rk3399_cru_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE);