sys/arm64/rockchip/clk/rk3399_cru.c

   1 /*-
   2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
   3  *
   4  * Copyright (c) 2018 Emmanuel Vadot <manu@freebsd.org>
   5  * Copyright (c) 2018 Greg V <greg@unrelenting.technology>
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  17  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  18  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  19  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  20  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  21  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  23  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  24  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  26  * SUCH DAMAGE.
  27  *
  28  * $FreeBSD$
  29  */
  30
  31 #include <sys/cdefs.h>
  32 __FBSDID("$FreeBSD$");
  33
  34 #include <sys/param.h>
  35 #include <sys/systm.h>
  36 #include <sys/bus.h>
  37 #include <sys/rman.h>
  38 #include <sys/kernel.h>
  39 #include <sys/module.h>
  40 #include <machine/bus.h>
  41
  42 #include <dev/fdt/simplebus.h>
  43
  44 #include <dev/ofw/ofw_bus.h>
  45 #include <dev/ofw/ofw_bus_subr.h>
  46
  47 #include <dev/extres/clk/clk_div.h>
  48 #include <dev/extres/clk/clk_fixed.h>
  49 #include <dev/extres/clk/clk_mux.h>
  50
  51 #include <arm64/rockchip/clk/rk_cru.h>
  52
  53 /* GATES */
  54
  55 #define SCLK_USB2PHY0_REF       123
  56 #define SCLK_USB2PHY1_REF       124
  57 #define SCLK_USB3OTG0_REF       129
  58 #define SCLK_USB3OTG1_REF       130
  59 #define SCLK_USB3OTG0_SUSPEND   131
  60 #define SCLK_USB3OTG1_SUSPEND   132
  61 #define ACLK_EMMC_CORE          241
  62 #define ACLK_EMMC_NOC           242
  63 #define ACLK_EMMC_GRF           243
  64 #define ACLK_USB3_NOC           245
  65 #define ACLK_USB3OTG0           246
  66 #define ACLK_USB3OTG1           247
  67 #define ACLK_USB3_RKSOC_AXI_PERF        248
  68 #define ACLK_USB3_GRF           249
  69 #define PCLK_GPIO2              336
  70 #define PCLK_GPIO3              337
  71 #define PCLK_GPIO4              338
  72 #define PCLK_I2C1               341
  73 #define PCLK_I2C2               342
  74 #define PCLK_I2C3               343
  75 #define PCLK_I2C5               344
  76 #define PCLK_I2C6               345
  77 #define PCLK_I2C7               346
  78 #define PCLK_SPI0               347
  79 #define PCLK_SPI1               348
  80 #define PCLK_SPI2               349
  81 #define PCLK_SPI4               350
  82 #define PCLK_SPI5               351
  83 #define HCLK_HOST0              456
  84 #define HCLK_HOST0_ARB          457
  85 #define HCLK_HOST1              458
  86 #define HCLK_HOST1_ARB          459
  87 #define HCLK_SDMMC              462
  88
  89 static struct rk_cru_gate rk3399_gates[] = {
  90         /* CRU_CLKGATE_CON0 */
  91         CRU_GATE(0, "clk_core_l_lpll_src", "lpll", 0x300, 0)
  92         CRU_GATE(0, "clk_core_l_bpll_src", "bpll", 0x300, 1)
  93         CRU_GATE(0, "clk_core_l_dpll_src", "dpll", 0x300, 2)
  94         CRU_GATE(0, "clk_core_l_gpll_src", "gpll", 0x300, 3)
  95
  96         /* CRU_CLKGATE_CON1 */
  97         CRU_GATE(0, "clk_core_b_lpll_src", "lpll", 0x304, 0)
  98         CRU_GATE(0, "clk_core_b_bpll_src", "bpll", 0x304, 1)
  99         CRU_GATE(0, "clk_core_b_dpll_src", "dpll", 0x304, 2)
 100         CRU_GATE(0, "clk_core_b_gpll_src", "gpll", 0x304, 3)
 101
 102         /* CRU_CLKGATE_CON5 */
 103         CRU_GATE(0, "cpll_aclk_perihp_src", "cpll", 0x314, 0)
 104         CRU_GATE(0, "gpll_aclk_perihp_src", "gpll", 0x314, 1)
 105
 106         /* CRU_CLKGATE_CON6 */
 107         CRU_GATE(0, "gpll_aclk_emmc_src", "gpll", 0x318, 12)
 108         CRU_GATE(0, "cpll_aclk_emmc_src", "cpll", 0x318, 13)
 109         CRU_GATE(SCLK_USB2PHY0_REF, "clk_usb2phy0_ref", "xin24m", 0x318, 5)
 110         CRU_GATE(SCLK_USB2PHY1_REF, "clk_usb2phy1_ref", "xin24m", 0x318, 6)
 111
 112         /* CRU_CLKGATE_CON7 */
 113         CRU_GATE(0, "gpll_aclk_perilp0_src", "gpll", 0x31C, 0)
 114         CRU_GATE(0, "cpll_aclk_perilp0_src", "cpll", 0x31C, 1)
 115
 116         /* CRU_CLKGATE_CON8 */
 117         CRU_GATE(0, "hclk_perilp1_cpll_src", "cpll", 0x320, 1)
 118         CRU_GATE(0, "hclk_perilp1_gpll_src", "gpll", 0x320, 0)
 119
 120         /* CRU_CLKGATE_CON12 */
 121         CRU_GATE(SCLK_USB3OTG0_REF, "sclk_usb3otg0_ref", "xin24m", 0x330, 1)
 122         CRU_GATE(SCLK_USB3OTG1_REF, "sclk_usb3otg1_ref", "xin24m", 0x330, 2)
 123         CRU_GATE(SCLK_USB3OTG0_SUSPEND, "sclk_usb3otg0_suspend", "xin24m", 0x330, 3)
 124         CRU_GATE(SCLK_USB3OTG1_SUSPEND, "sclk_usb3otg1_suspend", "xin24m", 0x330, 4)
 125
 126         /* CRU_CLKGATE_CON20 */
 127         CRU_GATE(HCLK_HOST0, "hclk_host0", "hclk_perihp", 0x350, 5)
 128         CRU_GATE(HCLK_HOST0_ARB, "hclk_host0_arb", "hclk_perihp", 0x350, 6)
 129         CRU_GATE(HCLK_HOST1, "hclk_host1", "hclk_perihp", 0x350, 7)
 130         CRU_GATE(HCLK_HOST1_ARB, "hclk_host1_arb", "hclk_perihp", 0x350, 8)
 131
 132         /* CRU_CLKGATE_CON22 */
 133         CRU_GATE(PCLK_I2C7, "pclk_rki2c7", "pclk_perilp1", 0x358, 5)
 134         CRU_GATE(PCLK_I2C1, "pclk_rki2c1", "pclk_perilp1", 0x358, 6)
 135         CRU_GATE(PCLK_I2C5, "pclk_rki2c5", "pclk_perilp1", 0x358, 7)
 136         CRU_GATE(PCLK_I2C6, "pclk_rki2c6", "pclk_perilp1", 0x358, 8)
 137         CRU_GATE(PCLK_I2C2, "pclk_rki2c2", "pclk_perilp1", 0x358, 9)
 138         CRU_GATE(PCLK_I2C3, "pclk_rki2c3", "pclk_perilp1", 0x358, 10)
 139
 140         /* CRU_CLKGATE_CON23 */
 141         CRU_GATE(PCLK_SPI0, "pclk_spi0", "pclk_perilp1", 0x35C, 10)
 142         CRU_GATE(PCLK_SPI1, "pclk_spi1", "pclk_perilp1", 0x35C, 11)
 143         CRU_GATE(PCLK_SPI2, "pclk_spi2", "pclk_perilp1", 0x35C, 12)
 144         CRU_GATE(PCLK_SPI4, "pclk_spi4", "pclk_perilp1", 0x35C, 13)
 145
 146         /* CRU_CLKGATE_CON30 */
 147         CRU_GATE(ACLK_USB3_NOC, "aclk_usb3_noc", "aclk_usb3", 0x378, 0)
 148         CRU_GATE(ACLK_USB3OTG0, "aclk_usb3otg0", "aclk_usb3", 0x378, 1)
 149         CRU_GATE(ACLK_USB3OTG1, "aclk_usb3otg1", "aclk_usb3", 0x378, 2)
 150         CRU_GATE(ACLK_USB3_RKSOC_AXI_PERF, "aclk_usb3_rksoc_axi_perf", "aclk_usb3", 0x378, 3)
 151         CRU_GATE(ACLK_USB3_GRF, "aclk_usb3_grf", "aclk_usb3", 0x378, 4)
 152
 153         /* CRU_CLKGATE_CON31 */
 154         CRU_GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_alive", 0x37c, 3)
 155         CRU_GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_alive", 0x37c, 4)
 156         CRU_GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_alive", 0x37c, 5)
 157
 158         /* CRU_CLKGATE_CON32 */
 159         CRU_GATE(ACLK_EMMC_CORE, "aclk_emmccore", "aclk_emmc", 0x380, 8)
 160         CRU_GATE(ACLK_EMMC_NOC, "aclk_emmc_noc", "aclk_emmc", 0x380, 9)
 161         CRU_GATE(ACLK_EMMC_GRF, "aclk_emmcgrf", "aclk_emmc", 0x380, 10)
 162
 163         /* CRU_CLKGATE_CON33 */
 164         CRU_GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_sd", 0x384, 8)
 165
 166         /* CRU_CLKGATE_CON34 */
 167         CRU_GATE(PCLK_SPI4, "pclk_spi5", "pclk_perilp1", 0x388, 5)
 168 };
 169
 170
 171 /*
 172  * PLLs
 173  */
 174
 175 #define PLL_APLLL                       1
 176 #define PLL_APLLB                       2
 177 #define PLL_DPLL                        3
 178 #define PLL_CPLL                        4
 179 #define PLL_GPLL                        5
 180 #define PLL_NPLL                        6
 181 #define PLL_VPLL                        7
 182
 183 static struct rk_clk_pll_rate rk3399_pll_rates[] = {
 184         {
 185                 .freq = 2208000000,
 186                 .refdiv = 1,
 187                 .fbdiv = 92,
 188                 .postdiv1 = 1,
 189                 .postdiv2 = 1,
 190                 .dsmpd = 1,
 191         },
 192         {
 193                 .freq = 2184000000,
 194                 .refdiv = 1,
 195                 .fbdiv = 91,
 196                 .postdiv1 = 1,
 197                 .postdiv2 = 1,
 198                 .dsmpd = 1,
 199         },
 200         {
 201                 .freq = 2160000000,
 202                 .refdiv = 1,
 203                 .fbdiv = 90,
 204                 .postdiv1 = 1,
 205                 .postdiv2 = 1,
 206                 .dsmpd = 1,
 207         },
 208         {
 209                 .freq = 2136000000,
 210                 .refdiv = 1,
 211                 .fbdiv = 89,
 212                 .postdiv1 = 1,
 213                 .postdiv2 = 1,
 214                 .dsmpd = 1,
 215         },
 216         {
 217                 .freq = 2112000000,
 218                 .refdiv = 1,
 219                 .fbdiv = 88,
 220                 .postdiv1 = 1,
 221                 .postdiv2 = 1,
 222                 .dsmpd = 1,
 223         },
 224         {
 225                 .freq = 2088000000,
 226                 .refdiv = 1,
 227                 .fbdiv = 87,
 228                 .postdiv1 = 1,
 229                 .postdiv2 = 1,
 230                 .dsmpd = 1,
 231         },
 232         {
 233                 .freq = 2064000000,
 234                 .refdiv = 1,
 235                 .fbdiv = 86,
 236                 .postdiv1 = 1,
 237                 .postdiv2 = 1,
 238                 .dsmpd = 1,
 239         },
 240         {
 241                 .freq = 2040000000,
 242                 .refdiv = 1,
 243                 .fbdiv = 85,
 244                 .postdiv1 = 1,
 245                 .postdiv2 = 1,
 246                 .dsmpd = 1,
 247         },
 248         {
 249                 .freq = 2016000000,
 250                 .refdiv = 1,
 251                 .fbdiv = 84,
 252                 .postdiv1 = 1,
 253                 .postdiv2 = 1,
 254                 .dsmpd = 1,
 255         },
 256         {
 257                 .freq = 1992000000,
 258                 .refdiv = 1,
 259                 .fbdiv = 83,
 260                 .postdiv1 = 1,
 261                 .postdiv2 = 1,
 262                 .dsmpd = 1,
 263         },
 264         {
 265                 .freq = 1968000000,
 266                 .refdiv = 1,
 267                 .fbdiv = 82,
 268                 .postdiv1 = 1,
 269                 .postdiv2 = 1,
 270                 .dsmpd = 1,
 271         },
 272         {
 273                 .freq = 1944000000,
 274                 .refdiv = 1,
 275                 .fbdiv = 81,
 276                 .postdiv1 = 1,
 277                 .postdiv2 = 1,
 278                 .dsmpd = 1,
 279         },
 280         {
 281                 .freq = 1920000000,
 282                 .refdiv = 1,
 283                 .fbdiv = 80,
 284                 .postdiv1 = 1,
 285                 .postdiv2 = 1,
 286                 .dsmpd = 1,
 287         },
 288         {
 289                 .freq = 1896000000,
 290                 .refdiv = 1,
 291                 .fbdiv = 79,
 292                 .postdiv1 = 1,
 293                 .postdiv2 = 1,
 294                 .dsmpd = 1,
 295         },
 296         {
 297                 .freq = 1872000000,
 298                 .refdiv = 1,
 299                 .fbdiv = 78,
 300                 .postdiv1 = 1,
 301                 .postdiv2 = 1,
 302                 .dsmpd = 1,
 303         },
 304         {
 305                 .freq = 1848000000,
 306                 .refdiv = 1,
 307                 .fbdiv = 77,
 308                 .postdiv1 = 1,
 309                 .postdiv2 = 1,
 310                 .dsmpd = 1,
 311         },
 312         {
 313                 .freq = 1824000000,
 314                 .refdiv = 1,
 315                 .fbdiv = 76,
 316                 .postdiv1 = 1,
 317                 .postdiv2 = 1,
 318                 .dsmpd = 1,
 319         },
 320         {
 321                 .freq = 1800000000,
 322                 .refdiv = 1,
 323                 .fbdiv = 75,
 324                 .postdiv1 = 1,
 325                 .postdiv2 = 1,
 326                 .dsmpd = 1,
 327         },
 328         {
 329                 .freq = 1776000000,
 330                 .refdiv = 1,
 331                 .fbdiv = 74,
 332                 .postdiv1 = 1,
 333                 .postdiv2 = 1,
 334                 .dsmpd = 1,
 335         },
 336         {
 337                 .freq = 1752000000,
 338                 .refdiv = 1,
 339                 .fbdiv = 73,
 340                 .postdiv1 = 1,
 341                 .postdiv2 = 1,
 342                 .dsmpd = 1,
 343         },
 344         {
 345                 .freq = 1728000000,
 346                 .refdiv = 1,
 347                 .fbdiv = 72,
 348                 .postdiv1 = 1,
 349                 .postdiv2 = 1,
 350                 .dsmpd = 1,
 351         },
 352         {
 353                 .freq = 1704000000,
 354                 .refdiv = 1,
 355                 .fbdiv = 71,
 356                 .postdiv1 = 1,
 357                 .postdiv2 = 1,
 358                 .dsmpd = 1,
 359         },
 360         {
 361                 .freq = 1680000000,
 362                 .refdiv = 1,
 363                 .fbdiv = 70,
 364                 .postdiv1 = 1,
 365                 .postdiv2 = 1,
 366                 .dsmpd = 1,
 367         },
 368         {
 369                 .freq = 1656000000,
 370                 .refdiv = 1,
 371                 .fbdiv = 69,
 372                 .postdiv1 = 1,
 373                 .postdiv2 = 1,
 374                 .dsmpd = 1,
 375         },
 376         {
 377                 .freq = 1632000000,
 378                 .refdiv = 1,
 379                 .fbdiv = 68,
 380                 .postdiv1 = 1,
 381                 .postdiv2 = 1,
 382                 .dsmpd = 1,
 383         },
 384         {
 385                 .freq = 1608000000,
 386                 .refdiv = 1,
 387                 .fbdiv = 67,
 388                 .postdiv1 = 1,
 389                 .postdiv2 = 1,
 390                 .dsmpd = 1,
 391         },
 392         {
 393                 .freq = 1600000000,
 394                 .refdiv = 3,
 395                 .fbdiv = 200,
 396                 .postdiv1 = 1,
 397                 .postdiv2 = 1,
 398                 .dsmpd = 1,
 399         },
 400         {
 401                 .freq = 1584000000,
 402                 .refdiv = 1,
 403                 .fbdiv = 66,
 404                 .postdiv1 = 1,
 405                 .postdiv2 = 1,
 406                 .dsmpd = 1,
 407         },
 408         {
 409                 .freq = 1560000000,
 410                 .refdiv = 1,
 411                 .fbdiv = 65,
 412                 .postdiv1 = 1,
 413                 .postdiv2 = 1,
 414                 .dsmpd = 1,
 415         },
 416         {
 417                 .freq = 1536000000,
 418                 .refdiv = 1,
 419                 .fbdiv = 64,
 420                 .postdiv1 = 1,
 421                 .postdiv2 = 1,
 422                 .dsmpd = 1,
 423         },
 424         {
 425                 .freq = 1512000000,
 426                 .refdiv = 1,
 427                 .fbdiv = 63,
 428                 .postdiv1 = 1,
 429                 .postdiv2 = 1,
 430                 .dsmpd = 1,
 431         },
 432         {
 433                 .freq = 1488000000,
 434                 .refdiv = 1,
 435                 .fbdiv = 62,
 436                 .postdiv1 = 1,
 437                 .postdiv2 = 1,
 438                 .dsmpd = 1,
 439         },
 440         {
 441                 .freq = 1464000000,
 442                 .refdiv = 1,
 443                 .fbdiv = 61,
 444                 .postdiv1 = 1,
 445                 .postdiv2 = 1,
 446                 .dsmpd = 1,
 447         },
 448         {
 449                 .freq = 1440000000,
 450                 .refdiv = 1,
 451                 .fbdiv = 60,
 452                 .postdiv1 = 1,
 453                 .postdiv2 = 1,
 454                 .dsmpd = 1,
 455         },
 456         {
 457                 .freq = 1416000000,
 458                 .refdiv = 1,
 459                 .fbdiv = 59,
 460                 .postdiv1 = 1,
 461                 .postdiv2 = 1,
 462                 .dsmpd = 1,
 463         },
 464         {
 465                 .freq = 1392000000,
 466                 .refdiv = 1,
 467                 .fbdiv = 58,
 468                 .postdiv1 = 1,
 469                 .postdiv2 = 1,
 470                 .dsmpd = 1,
 471         },
 472         {
 473                 .freq = 1368000000,
 474                 .refdiv = 1,
 475                 .fbdiv = 57,
 476                 .postdiv1 = 1,
 477                 .postdiv2 = 1,
 478                 .dsmpd = 1,
 479         },
 480         {
 481                 .freq = 1344000000,
 482                 .refdiv = 1,
 483                 .fbdiv = 56,
 484                 .postdiv1 = 1,
 485                 .postdiv2 = 1,
 486                 .dsmpd = 1,
 487         },
 488         {
 489                 .freq = 1320000000,
 490                 .refdiv = 1,
 491                 .fbdiv = 55,
 492                 .postdiv1 = 1,
 493                 .postdiv2 = 1,
 494                 .dsmpd = 1,
 495         },
 496         {
 497                 .freq = 1296000000,
 498                 .refdiv = 1,
 499                 .fbdiv = 54,
 500                 .postdiv1 = 1,
 501                 .postdiv2 = 1,
 502                 .dsmpd = 1,
 503         },
 504         {
 505                 .freq = 1272000000,
 506                 .refdiv = 1,
 507                 .fbdiv = 53,
 508                 .postdiv1 = 1,
 509                 .postdiv2 = 1,
 510                 .dsmpd = 1,
 511         },
 512         {
 513                 .freq = 1248000000,
 514                 .refdiv = 1,
 515                 .fbdiv = 52,
 516                 .postdiv1 = 1,
 517                 .postdiv2 = 1,
 518                 .dsmpd = 1,
 519         },
 520         {
 521                 .freq = 1200000000,
 522                 .refdiv = 1,
 523                 .fbdiv = 50,
 524                 .postdiv1 = 1,
 525                 .postdiv2 = 1,
 526                 .dsmpd = 1,
 527         },
 528         {
 529                 .freq = 1188000000,
 530                 .refdiv = 2,
 531                 .fbdiv = 99,
 532                 .postdiv1 = 1,
 533                 .postdiv2 = 1,
 534                 .dsmpd = 1,
 535         },
 536         {
 537                 .freq = 1104000000,
 538                 .refdiv = 1,
 539                 .fbdiv = 46,
 540                 .postdiv1 = 1,
 541                 .postdiv2 = 1,
 542                 .dsmpd = 1,
 543         },
 544         {
 545                 .freq = 1100000000,
 546                 .refdiv = 12,
 547                 .fbdiv = 550,
 548                 .postdiv1 = 1,
 549                 .postdiv2 = 1,
 550                 .dsmpd = 1,
 551         },
 552         {
 553                 .freq = 1008000000,
 554                 .refdiv = 1,
 555                 .fbdiv = 84,
 556                 .postdiv1 = 2,
 557                 .postdiv2 = 1,
 558                 .dsmpd = 1,
 559         },
 560         {
 561                 .freq = 1000000000,
 562                 .refdiv = 1,
 563                 .fbdiv = 125,
 564                 .postdiv1 = 3,
 565                 .postdiv2 = 1,
 566                 .dsmpd = 1,
 567         },
 568         {
 569                 .freq = 984000000,
 570                 .refdiv = 1,
 571                 .fbdiv = 82,
 572                 .postdiv1 = 2,
 573                 .postdiv2 = 1,
 574                 .dsmpd = 1,
 575         },
 576         {
 577                 .freq = 960000000,
 578                 .refdiv = 1,
 579                 .fbdiv = 80,
 580                 .postdiv1 = 2,
 581                 .postdiv2 = 1,
 582                 .dsmpd = 1,
 583         },
 584         {
 585                 .freq = 936000000,
 586                 .refdiv = 1,
 587                 .fbdiv = 78,
 588                 .postdiv1 = 2,
 589                 .postdiv2 = 1,
 590                 .dsmpd = 1,
 591         },
 592         {
 593                 .freq = 912000000,
 594                 .refdiv = 1,
 595                 .fbdiv = 76,
 596                 .postdiv1 = 2,
 597                 .postdiv2 = 1,
 598                 .dsmpd = 1,
 599         },
 600         {
 601                 .freq = 900000000,
 602                 .refdiv = 4,
 603                 .fbdiv = 300,
 604                 .postdiv1 = 2,
 605                 .postdiv2 = 1,
 606                 .dsmpd = 1,
 607         },
 608         {
 609                 .freq = 888000000,
 610                 .refdiv = 1,
 611                 .fbdiv = 74,
 612                 .postdiv1 = 2,
 613                 .postdiv2 = 1,
 614                 .dsmpd = 1,
 615         },
 616         {
 617                 .freq = 864000000,
 618                 .refdiv = 1,
 619                 .fbdiv = 72,
 620                 .postdiv1 = 2,
 621                 .postdiv2 = 1,
 622                 .dsmpd = 1,
 623         },
 624         {
 625                 .freq = 840000000,
 626                 .refdiv = 1,
 627                 .fbdiv = 70,
 628                 .postdiv1 = 2,
 629                 .postdiv2 = 1,
 630                 .dsmpd = 1,
 631         },
 632         {
 633                 .freq = 816000000,
 634                 .refdiv = 1,
 635                 .fbdiv = 68,
 636                 .postdiv1 = 2,
 637                 .postdiv2 = 1,
 638                 .dsmpd = 1,
 639         },
 640         {
 641                 .freq = 800000000,
 642                 .refdiv = 1,
 643                 .fbdiv = 100,
 644                 .postdiv1 = 3,
 645                 .postdiv2 = 1,
 646                 .dsmpd = 1,
 647         },
 648         {
 649                 .freq = 700000000,
 650                 .refdiv = 6,
 651                 .fbdiv = 350,
 652                 .postdiv1 = 2,
 653                 .postdiv2 = 1,
 654                 .dsmpd = 1,
 655         },
 656         {
 657                 .freq = 696000000,
 658                 .refdiv = 1,
 659                 .fbdiv = 58,
 660                 .postdiv1 = 2,
 661                 .postdiv2 = 1,
 662                 .dsmpd = 1,
 663         },
 664         {
 665                 .freq = 676000000,
 666                 .refdiv = 3,
 667                 .fbdiv = 169,
 668                 .postdiv1 = 2,
 669                 .postdiv2 = 1,
 670                 .dsmpd = 1,
 671         },
 672         {
 673                 .freq = 600000000,
 674                 .refdiv = 1,
 675                 .fbdiv = 75,
 676                 .postdiv1 = 3,
 677                 .postdiv2 = 1,
 678                 .dsmpd = 1,
 679         },
 680         {
 681                 .freq = 594000000,
 682                 .refdiv = 1,
 683                 .fbdiv = 99,
 684                 .postdiv1 = 4,
 685                 .postdiv2 = 1,
 686                 .dsmpd = 1,
 687         },
 688         {
 689                 .freq = 533250000,
 690                 .refdiv = 8,
 691                 .fbdiv = 711,
 692                 .postdiv1 = 4,
 693                 .postdiv2 = 1,
 694                 .dsmpd = 1,
 695         },
 696         {
 697                 .freq = 504000000,
 698                 .refdiv = 1,
 699                 .fbdiv = 63,
 700                 .postdiv1 = 3,
 701                 .postdiv2 = 1,
 702                 .dsmpd = 1,
 703         },
 704         {
 705                 .freq = 500000000,
 706                 .refdiv = 6,
 707                 .fbdiv = 250,
 708                 .postdiv1 = 2,
 709                 .postdiv2 = 1,
 710                 .dsmpd = 1,
 711         },
 712         {
 713                 .freq = 408000000,
 714                 .refdiv = 1,
 715                 .fbdiv = 68,
 716                 .postdiv1 = 2,
 717                 .postdiv2 = 2,
 718                 .dsmpd = 1,
 719         },
 720         {
 721                 .freq = 312000000,
 722                 .refdiv = 1,
 723                 .fbdiv = 52,
 724                 .postdiv1 = 2,
 725                 .postdiv2 = 2,
 726                 .dsmpd = 1,
 727         },
 728         {
 729                 .freq = 297000000,
 730                 .refdiv = 1,
 731                 .fbdiv = 99,
 732                 .postdiv1 = 4,
 733                 .postdiv2 = 2,
 734                 .dsmpd = 1,
 735         },
 736         {
 737                 .freq = 216000000,
 738                 .refdiv = 1,
 739                 .fbdiv = 72,
 740                 .postdiv1 = 4,
 741                 .postdiv2 = 2,
 742                 .dsmpd = 1,
 743         },
 744         {
 745                 .freq = 148500000,
 746                 .refdiv = 1,
 747                 .fbdiv = 99,
 748                 .postdiv1 = 4,
 749                 .postdiv2 = 4,
 750                 .dsmpd = 1,
 751         },
 752         {
 753                 .freq = 106500000,
 754                 .refdiv = 1,
 755                 .fbdiv = 71,
 756                 .postdiv1 = 4,
 757                 .postdiv2 = 4,
 758                 .dsmpd = 1,
 759         },
 760         {
 761                 .freq = 96000000,
 762                 .refdiv = 1,
 763                 .fbdiv = 64,
 764                 .postdiv1 = 4,
 765                 .postdiv2 = 4,
 766                 .dsmpd = 1,
 767         },
 768         {
 769                 .freq = 74250000,
 770                 .refdiv = 2,
 771                 .fbdiv = 99,
 772                 .postdiv1 = 4,
 773                 .postdiv2 = 4,
 774                 .dsmpd = 1,
 775         },
 776         {
 777                 .freq = 65000000,
 778                 .refdiv = 1,
 779                 .fbdiv = 65,
 780                 .postdiv1 = 6,
 781                 .postdiv2 = 4,
 782                 .dsmpd = 1,
 783         },
 784         {
 785                 .freq = 54000000,
 786                 .refdiv = 1,
 787                 .fbdiv = 54,
 788                 .postdiv1 = 6,
 789                 .postdiv2 = 4,
 790                 .dsmpd = 1,
 791         },
 792         {
 793                 .freq = 27000000,
 794                 .refdiv = 1,
 795                 .fbdiv = 27,
 796                 .postdiv1 = 6,
 797                 .postdiv2 = 4,
 798                 .dsmpd = 1,
 799         },
 800         {},
 801 };
 802
 803 static const char *pll_parents[] = {"xin24m"};
 804
 805 static struct rk_clk_pll_def lpll = {
 806         .clkdef = {
 807                 .id = PLL_APLLL,
 808                 .name = "lpll",
 809                 .parent_names = pll_parents,
 810                 .parent_cnt = nitems(pll_parents),
 811         },
 812         .base_offset = 0x00,
 813         .gate_offset = 0x300,
 814         .gate_shift = 0,
 815         .flags = RK_CLK_PLL_HAVE_GATE,
 816         .rates = rk3399_pll_rates,
 817         .normal_mode = true,
 818 };
 819
 820 static struct rk_clk_pll_def bpll = {
 821         .clkdef = {
 822                 .id = PLL_APLLB,
 823                 .name = "bpll",
 824                 .parent_names = pll_parents,
 825                 .parent_cnt = nitems(pll_parents),
 826         },
 827         .base_offset = 0x20,
 828         .gate_offset = 0x300,
 829         .gate_shift = 1,
 830         .flags = RK_CLK_PLL_HAVE_GATE,
 831         .rates = rk3399_pll_rates,
 832         .normal_mode = true,
 833 };
 834
 835 static struct rk_clk_pll_def dpll = {
 836         .clkdef = {
 837                 .id = PLL_DPLL,
 838                 .name = "dpll",
 839                 .parent_names = pll_parents,
 840                 .parent_cnt = nitems(pll_parents),
 841         },
 842         .base_offset = 0x40,
 843         .gate_offset = 0x300,
 844         .gate_shift = 2,
 845         .flags = RK_CLK_PLL_HAVE_GATE,
 846         .rates = rk3399_pll_rates,
 847 };
 848
 849
 850 static struct rk_clk_pll_def cpll = {
 851         .clkdef = {
 852                 .id = PLL_CPLL,
 853                 .name = "cpll",
 854                 .parent_names = pll_parents,
 855                 .parent_cnt = nitems(pll_parents),
 856         },
 857         .base_offset = 0x60,
 858         .rates = rk3399_pll_rates,
 859 };
 860
 861 static struct rk_clk_pll_def gpll = {
 862         .clkdef = {
 863                 .id = PLL_GPLL,
 864                 .name = "gpll",
 865                 .parent_names = pll_parents,
 866                 .parent_cnt = nitems(pll_parents),
 867         },
 868         .base_offset = 0x80,
 869         .gate_offset = 0x300,
 870         .gate_shift = 3,
 871         .flags = RK_CLK_PLL_HAVE_GATE,
 872         .rates = rk3399_pll_rates,
 873 };
 874
 875 static struct rk_clk_pll_def npll = {
 876         .clkdef = {
 877                 .id = PLL_NPLL,
 878                 .name = "npll",
 879                 .parent_names = pll_parents,
 880                 .parent_cnt = nitems(pll_parents),
 881         },
 882         .base_offset = 0xa0,
 883         .rates = rk3399_pll_rates,
 884 };
 885
 886 static struct rk_clk_pll_def vpll = {
 887         .clkdef = {
 888                 .id = PLL_VPLL,
 889                 .name = "vpll",
 890                 .parent_names = pll_parents,
 891                 .parent_cnt = nitems(pll_parents),
 892         },
 893         .base_offset = 0xc0,
 894         .rates = rk3399_pll_rates,
 895 };
 896
 897 #define ACLK_PERIHP     192
 898 #define HCLK_PERIHP     448
 899 #define PCLK_PERIHP     320
 900
 901 static const char *aclk_perihp_parents[] = {"cpll_aclk_perihp_src", "gpll_aclk_perihp_src"};
 902
 903 static struct rk_clk_composite_def aclk_perihp = {
 904         .clkdef = {
 905                 .id = ACLK_PERIHP,
 906                 .name = "aclk_perihp",
 907                 .parent_names = aclk_perihp_parents,
 908                 .parent_cnt = nitems(aclk_perihp_parents),
 909         },
 910         /* CRU_CLKSEL_CON14 */
 911         .muxdiv_offset = 0x138,
 912
 913         .mux_shift = 7,
 914         .mux_width = 1,
 915
 916         .div_shift = 0,
 917         .div_width = 5,
 918
 919         /* CRU_CLKGATE_CON5 */
 920         .gate_offset = 0x314,
 921         .gate_shift = 2,
 922
 923         .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
 924 };
 925
 926 static const char *hclk_pclk_perihp_parents[] = {"aclk_perihp"};
 927
 928 static struct rk_clk_composite_def hclk_perihp = {
 929         .clkdef = {
 930                 .id = HCLK_PERIHP,
 931                 .name = "hclk_perihp",
 932                 .parent_names = hclk_pclk_perihp_parents,
 933                 .parent_cnt = nitems(hclk_pclk_perihp_parents),
 934         },
 935         /* CRU_CLKSEL_CON14 */
 936         .muxdiv_offset = 0x138,
 937
 938         .div_shift = 8,
 939         .div_width = 2,
 940
 941         /* CRU_CLKGATE_CON5 */
 942         .gate_offset = 0x314,
 943         .gate_shift = 3,
 944
 945         .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
 946 };
 947
 948 static struct rk_clk_composite_def pclk_perihp = {
 949         .clkdef = {
 950                 .id = PCLK_PERIHP,
 951                 .name = "pclk_perihp",
 952                 .parent_names = hclk_pclk_perihp_parents,
 953                 .parent_cnt = nitems(hclk_pclk_perihp_parents),
 954         },
 955         /* CRU_CLKSEL_CON14 */
 956         .muxdiv_offset = 0x138,
 957
 958         .div_shift = 12,
 959         .div_width = 3,
 960
 961         /* CRU_CLKGATE_CON5 */
 962         .gate_offset = 0x314,
 963         .gate_shift = 4,
 964
 965         .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
 966 };
 967
 968 #define ACLK_PERILP0    194
 969 #define HCLK_PERILP0    449
 970 #define PCLK_PERILP0    322
 971
 972 static const char *aclk_perilp0_parents[] = {"cpll_aclk_perilp0_src", "gpll_aclk_perilp0_src"};
 973
 974 static struct rk_clk_composite_def aclk_perilp0 = {
 975         .clkdef = {
 976                 .id = ACLK_PERILP0,
 977                 .name = "aclk_perilp0",
 978                 .parent_names = aclk_perilp0_parents,
 979                 .parent_cnt = nitems(aclk_perilp0_parents),
 980         },
 981         /* CRU_CLKSEL_CON14 */
 982         .muxdiv_offset = 0x15C,
 983
 984         .mux_shift = 7,
 985         .mux_width = 1,
 986
 987         .div_shift = 0,
 988         .div_width = 5,
 989
 990         /* CRU_CLKGATE_CON7 */
 991         .gate_offset = 0x31C,
 992         .gate_shift = 2,
 993
 994         .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
 995 };
 996
 997 static const char *hclk_pclk_perilp0_parents[] = {"aclk_perilp0"};
 998
 999 static struct rk_clk_composite_def hclk_perilp0 = {
1000         .clkdef = {
1001                 .id = HCLK_PERILP0,
1002                 .name = "hclk_perilp0",
1003                 .parent_names = hclk_pclk_perilp0_parents,
1004                 .parent_cnt = nitems(hclk_pclk_perilp0_parents),
1005         },
1006         /* CRU_CLKSEL_CON23 */
1007         .muxdiv_offset = 0x15C,
1008
1009         .div_shift = 8,
1010         .div_width = 2,
1011
1012         /* CRU_CLKGATE_CON7 */
1013         .gate_offset = 0x31C,
1014         .gate_shift = 3,
1015
1016         .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
1017 };
1018
1019 static struct rk_clk_composite_def pclk_perilp0 = {
1020         .clkdef = {
1021                 .id = PCLK_PERILP0,
1022                 .name = "pclk_perilp0",
1023                 .parent_names = hclk_pclk_perilp0_parents,
1024                 .parent_cnt = nitems(hclk_pclk_perilp0_parents),
1025         },
1026         /* CRU_CLKSEL_CON23 */
1027         .muxdiv_offset = 0x15C,
1028
1029         .div_shift = 12,
1030         .div_width = 3,
1031
1032         /* CRU_CLKGATE_CON7 */
1033         .gate_offset = 0x31C,
1034         .gate_shift = 4,
1035
1036         .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
1037 };
1038
1039 /*
1040  * misc
1041  */
1042 #define PCLK_ALIVE              390
1043
1044 static const char *alive_parents[] = {"gpll"};
1045
1046 static struct rk_clk_composite_def pclk_alive = {
1047         .clkdef = {
1048                 .id = PCLK_ALIVE,
1049                 .name = "pclk_alive",
1050                 .parent_names = alive_parents,
1051                 .parent_cnt = nitems(alive_parents),
1052         },
1053         /* CRU_CLKSEL_CON57 */
1054         .muxdiv_offset = 0x01e4,
1055
1056         .div_shift = 0,
1057         .div_width = 5,
1058 };
1059
1060 #define HCLK_PERILP1            450
1061 #define PCLK_PERILP1            323
1062
1063 static const char *hclk_perilp1_parents[] = {"cpll", "gpll"};
1064
1065 static struct rk_clk_composite_def hclk_perilp1 = {
1066         .clkdef = {
1067                 .id = HCLK_PERILP1,
1068                 .name = "hclk_perilp1",
1069                 .parent_names = hclk_perilp1_parents,
1070                 .parent_cnt = nitems(hclk_perilp1_parents),
1071         },
1072         /* CRU_CLKSEL_CON25 */
1073         .muxdiv_offset = 0x164,
1074         .mux_shift = 7,
1075         .mux_width = 1,
1076
1077         .div_shift = 0,
1078         .div_width = 5,
1079
1080         .flags = RK_CLK_COMPOSITE_HAVE_MUX,
1081 };
1082
1083 static const char *pclk_perilp1_parents[] = {"hclk_perilp1"};
1084
1085 static struct rk_clk_composite_def pclk_perilp1 = {
1086         .clkdef = {
1087                 .id = PCLK_PERILP1,
1088                 .name = "pclk_perilp1",
1089                 .parent_names = pclk_perilp1_parents,
1090                 .parent_cnt = nitems(pclk_perilp1_parents),
1091         },
1092         /* CRU_CLKSEL_CON25 */
1093         .muxdiv_offset = 0x164,
1094
1095         .div_shift = 8,
1096         .div_width = 3,
1097
1098         /* CRU_CLKGATE_CON8 */
1099         .gate_offset = 0x320,
1100         .gate_shift = 2,
1101
1102         .flags = RK_CLK_COMPOSITE_HAVE_GATE,
1103 };
1104
1105 /* USB3 clock */
1106
1107 #define ACLK_USB3       244
1108 static const char *aclk_usb3_parents[] = {"cpll", "gpll", "npll", "npll"};
1109 static struct rk_clk_composite_def aclk_usb3 = {
1110         .clkdef = {
1111                 .id = ACLK_USB3,
1112                 .name = "aclk_usb3",
1113                 .parent_names = aclk_usb3_parents,
1114                 .parent_cnt = nitems(aclk_usb3_parents),
1115         },
1116         /* CRU_CLKSET_CON39 */
1117         .muxdiv_offset = 0x19C,
1118         .mux_shift = 6,
1119         .mux_width = 2,
1120
1121         .div_shift = 0,
1122         .div_width = 5,
1123
1124         /* CRU_CLKGATE_CON12 */
1125         .gate_offset = 0x330,
1126         .gate_shift = 0,
1127
1128         .flags = RK_CLK_COMPOSITE_HAVE_GATE,
1129 };
1130
1131 /*
1132  * i2c
1133  */
1134 static const char *i2c_parents[] = {"cpll", "gpll"};
1135
1136 #define SCLK_I2C1       65
1137 #define SCLK_I2C2       66
1138 #define SCLK_I2C3       67
1139 #define SCLK_I2C5       68
1140 #define SCLK_I2C6       69
1141 #define SCLK_I2C7       70
1142
1143 static struct rk_clk_composite_def i2c1 = {
1144         .clkdef = {
1145                 .id = SCLK_I2C1,
1146                 .name = "clk_i2c1",
1147                 .parent_names = i2c_parents,
1148                 .parent_cnt = nitems(i2c_parents),
1149         },
1150         /* CRU_CLKSEL_CON61 */
1151         .muxdiv_offset = 0x01f4,
1152         .mux_shift = 7,
1153         .mux_width = 1,
1154
1155         .div_shift = 0,
1156         .div_width = 7,
1157
1158         /* CRU_CLKGATE_CON10 */
1159         .gate_offset = 0x0328,
1160         .gate_shift = 0,
1161
1162         .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
1163 };
1164
1165 static struct rk_clk_composite_def i2c2 = {
1166         .clkdef = {
1167                 .id = SCLK_I2C2,
1168                 .name = "clk_i2c2",
1169                 .parent_names = i2c_parents,
1170                 .parent_cnt = nitems(i2c_parents),
1171         },
1172         /* CRU_CLKSEL_CON62 */
1173         .muxdiv_offset = 0x01f8,
1174         .mux_shift = 7,
1175         .mux_width = 1,
1176
1177         .div_shift = 0,
1178         .div_width = 7,
1179
1180         /* CRU_CLKGATE_CON10 */
1181         .gate_offset = 0x0328,
1182         .gate_shift = 2,
1183
1184         .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
1185 };
1186
1187 static struct rk_clk_composite_def i2c3 = {
1188         .clkdef = {
1189                 .id = SCLK_I2C3,
1190                 .name = "clk_i2c3",
1191                 .parent_names = i2c_parents,
1192                 .parent_cnt = nitems(i2c_parents),
1193         },
1194         /* CRU_CLKSEL_CON63 */
1195         .muxdiv_offset = 0x01fc,
1196         .mux_shift = 7,
1197         .mux_width = 1,
1198
1199         .div_shift = 0,
1200         .div_width = 7,
1201
1202         /* CRU_CLKGATE_CON10 */
1203         .gate_offset = 0x0328,
1204         .gate_shift = 4,
1205
1206         .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
1207 };
1208
1209 static struct rk_clk_composite_def i2c5 = {
1210         .clkdef = {
1211                 .id = SCLK_I2C5,
1212                 .name = "clk_i2c5",
1213                 .parent_names = i2c_parents,
1214                 .parent_cnt = nitems(i2c_parents),
1215         },
1216         /* CRU_CLKSEL_CON61 */
1217         .muxdiv_offset = 0x01f4,
1218         .mux_shift = 15,
1219         .mux_width = 1,
1220
1221         .div_shift = 8,
1222         .div_width = 7,
1223
1224         /* CRU_CLKGATE_CON10 */
1225         .gate_offset = 0x0328,
1226         .gate_shift = 1,
1227
1228         .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
1229 };
1230
1231 static struct rk_clk_composite_def i2c6 = {
1232         .clkdef = {
1233                 .id = SCLK_I2C6,
1234                 .name = "clk_i2c6",
1235                 .parent_names = i2c_parents,
1236                 .parent_cnt = nitems(i2c_parents),
1237         },
1238         /* CRU_CLKSEL_CON62 */
1239         .muxdiv_offset = 0x01f8,
1240         .mux_shift = 15,
1241         .mux_width = 1,
1242
1243         .div_shift = 8,
1244         .div_width = 7,
1245
1246         /* CRU_CLKGATE_CON10 */
1247         .gate_offset = 0x0328,
1248         .gate_shift = 3,
1249
1250         .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
1251 };
1252
1253 static struct rk_clk_composite_def i2c7 = {
1254         .clkdef = {
1255                 .id = SCLK_I2C7,
1256                 .name = "clk_i2c7",
1257                 .parent_names = i2c_parents,
1258                 .parent_cnt = nitems(i2c_parents),
1259         },
1260         /* CRU_CLKSEL_CON63 */
1261         .muxdiv_offset = 0x01fc,
1262         .mux_shift = 15,
1263         .mux_width = 1,
1264
1265         .div_shift = 8,
1266         .div_width = 7,
1267
1268         /* CRU_CLKGATE_CON10 */
1269         .gate_offset = 0x0328,
1270         .gate_shift = 5,
1271
1272         .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
1273 };
1274
1275 /* USB3 */
1276
1277 #define SCLK_UPHY0_TCPDPHY_REF  125
1278 #define SCLK_UPHY0_TCPDCORE     126
1279
1280 /* Missing xin32k exported by rk808 */
1281 static const char *uphy0_tcpdphy_ref_parents[] = {"xin24m"};
1282
1283 static struct rk_clk_composite_def uphy0_tcpdphy_ref = {
1284         .clkdef = {
1285                 .id = SCLK_UPHY0_TCPDPHY_REF,
1286                 .name = "uphy0_tcpdphy_ref",
1287                 .parent_names = uphy0_tcpdphy_ref_parents,
1288                 .parent_cnt = nitems(uphy0_tcpdphy_ref_parents),
1289         },
1290         /* CRU_CLKSET_CON64 */
1291         .muxdiv_offset = 0x0200,
1292         .mux_shift = 15,
1293         .mux_width = 1,
1294
1295         .div_shift = 8,
1296         .div_width = 5,
1297
1298         /* CRU_CLKGATE_CON13 */
1299         .gate_offset = 0x0334,
1300         .gate_shift = 4,
1301
1302         .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
1303 };
1304
1305 /* Missing xin32k exported by rk808 */
1306 static const char *uphy0_tcpdcore_parents[] = {"xin24m", "xin24m", "cpll", "gpll"};
1307
1308 static struct rk_clk_composite_def uphy0_tcpdcore = {
1309         .clkdef = {
1310                 .id = SCLK_UPHY0_TCPDCORE,
1311                 .name = "uphy0_tcpdcore",
1312                 .parent_names = uphy0_tcpdcore_parents,
1313                 .parent_cnt = nitems(uphy0_tcpdcore_parents),
1314         },
1315         /* CRU_CLKSET_CON64 */
1316         .muxdiv_offset = 0x0200,
1317         .mux_shift = 6,
1318         .mux_width = 2,
1319
1320         .div_shift = 0,
1321         .div_width = 5,
1322
1323         /* CRU_CLKGATE_CON13 */
1324         .gate_offset = 0x0334,
1325         .gate_shift = 5,
1326
1327         .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
1328 };
1329
1330 #define SCLK_UPHY1_TCPDPHY_REF  127
1331 #define SCLK_UPHY1_TCPDCORE     128
1332
1333 /* Missing xin32k exported by rk808 */
1334 static const char *uphy1_tcpdphy_ref_parents[] = {"xin24m"};
1335
1336 static struct rk_clk_composite_def uphy1_tcpdphy_ref = {
1337         .clkdef = {
1338                 .id = SCLK_UPHY1_TCPDPHY_REF,
1339                 .name = "uphy1_tcpdphy_ref",
1340                 .parent_names = uphy1_tcpdphy_ref_parents,
1341                 .parent_cnt = nitems(uphy1_tcpdphy_ref_parents),
1342         },
1343         /* CRU_CLKSET_CON65 */
1344         .muxdiv_offset = 0x0204,
1345         .mux_shift = 15,
1346         .mux_width = 1,
1347
1348         .div_shift = 8,
1349         .div_width = 5,
1350
1351         /* CRU_CLKGATE_CON13 */
1352         .gate_offset = 0x0334,
1353         .gate_shift = 6,
1354
1355         .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
1356 };
1357
1358 /* Missing xin32k exported by rk808 */
1359 static const char *uphy1_tcpdcore_parents[] = {"xin24m", "xin24m", "cpll", "gpll"};
1360
1361 static struct rk_clk_composite_def uphy1_tcpdcore = {
1362         .clkdef = {
1363                 .id = SCLK_UPHY1_TCPDCORE,
1364                 .name = "uphy1_tcpdcore",
1365                 .parent_names = uphy1_tcpdcore_parents,
1366                 .parent_cnt = nitems(uphy1_tcpdcore_parents),
1367         },
1368         /* CRU_CLKSET_CON65 */
1369         .muxdiv_offset = 0x0204,
1370         .mux_shift = 6,
1371         .mux_width = 2,
1372
1373         .div_shift = 0,
1374         .div_width = 5,
1375
1376         /* CRU_CLKGATE_CON13 */
1377         .gate_offset = 0x0334,
1378         .gate_shift = 7,
1379
1380         .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
1381 };
1382
1383 /*
1384  * spi
1385  */
1386 static const char *spi_parents[] = {"cpll", "gpll"};
1387
1388 #define SCLK_SPI0       71
1389 #define SCLK_SPI1       72
1390 #define SCLK_SPI2       73
1391 #define SCLK_SPI4       74
1392 #define SCLK_SPI5       75
1393
1394 static struct rk_clk_composite_def spi0 = {
1395         .clkdef = {
1396                 .id = SCLK_SPI0,
1397                 .name = "clk_spi0",
1398                 .parent_names = spi_parents,
1399                 .parent_cnt = nitems(spi_parents),
1400         },
1401         /* CRU_CLKSEL_CON59 */
1402         .muxdiv_offset = 0x01ec,
1403         .mux_shift = 7,
1404         .mux_width = 1,
1405
1406         .div_shift = 0,
1407         .div_width = 7,
1408
1409         /* CRU_CLKGATE_CON9 */
1410         .gate_offset = 0x0324,
1411         .gate_shift = 12,
1412
1413         .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
1414 };
1415
1416 static struct rk_clk_composite_def spi1 = {
1417         .clkdef = {
1418                 .id = SCLK_SPI1,
1419                 .name = "clk_spi1",
1420                 .parent_names = spi_parents,
1421                 .parent_cnt = nitems(spi_parents),
1422         },
1423         /* CRU_CLKSEL_CON59 */
1424         .muxdiv_offset = 0x01ec,
1425         .mux_shift = 15,
1426         .mux_width = 1,
1427
1428         .div_shift = 8,
1429         .div_width = 7,
1430
1431         /* CRU_CLKGATE_CON9 */
1432         .gate_offset = 0x0324,
1433         .gate_shift = 13,
1434
1435         .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
1436 };
1437
1438 static struct rk_clk_composite_def spi2 = {
1439         .clkdef = {
1440                 .id = SCLK_SPI2,
1441                 .name = "clk_spi2",
1442                 .parent_names = spi_parents,
1443                 .parent_cnt = nitems(spi_parents),
1444         },
1445         /* CRU_CLKSEL_CON60 */
1446         .muxdiv_offset = 0x01f0,
1447         .mux_shift = 7,
1448         .mux_width = 1,
1449
1450         .div_shift = 0,
1451         .div_width = 7,
1452
1453         /* CRU_CLKGATE_CON9 */
1454         .gate_offset = 0x0324,
1455         .gate_shift = 14,
1456
1457         .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
1458 };
1459
1460 static struct rk_clk_composite_def spi4 = {
1461         .clkdef = {
1462                 .id = SCLK_SPI4,
1463                 .name = "clk_spi4",
1464                 .parent_names = spi_parents,
1465                 .parent_cnt = nitems(spi_parents),
1466         },
1467         /* CRU_CLKSEL_CON60 */
1468         .muxdiv_offset = 0x01f0,
1469         .mux_shift = 15,
1470         .mux_width = 1,
1471
1472         .div_shift = 8,
1473         .div_width = 7,
1474
1475         /* CRU_CLKGATE_CON9 */
1476         .gate_offset = 0x0324,
1477         .gate_shift = 15,
1478
1479         .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
1480 };
1481
1482 static struct rk_clk_composite_def spi5 = {
1483         .clkdef = {
1484                 .id = SCLK_SPI5,
1485                 .name = "clk_spi5",
1486                 .parent_names = spi_parents,
1487                 .parent_cnt = nitems(spi_parents),
1488         },
1489         /* CRU_CLKSEL_CON58 */
1490         .muxdiv_offset = 0x01e8,
1491         .mux_shift = 15,
1492         .mux_width = 1,
1493
1494         .div_shift = 8,
1495         .div_width = 7,
1496
1497         /* CRU_CLKGATE_CON13 */
1498         .gate_offset = 0x0334,
1499         .gate_shift = 13,
1500
1501         .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
1502 };
1503
1504 /*
1505  * ARM CPU clocks (LITTLE and big)
1506  */
1507 #define ARMCLKL                         8
1508 #define ARMCLKB                         9
1509
1510 static const char *armclk_parents[] = {"lpll", "bpll", "dpll", "gpll"};
1511
1512 static struct rk_clk_armclk_rates rk3399_armclkl_rates[] = {
1513         {
1514                 .freq = 1800000000,
1515                 .div = 1,
1516         },
1517         {
1518                 .freq = 1704000000,
1519                 .div = 1,
1520         },
1521         {
1522                 .freq = 1608000000,
1523                 .div = 1,
1524         },
1525         {
1526                 .freq = 1512000000,
1527                 .div = 1,
1528         },
1529         {
1530                 .freq = 1488000000,
1531                 .div = 1,
1532         },
1533         {
1534                 .freq = 1416000000,
1535                 .div = 1,
1536         },
1537         {
1538                 .freq = 1200000000,
1539                 .div = 1,
1540         },
1541         {
1542                 .freq = 1008000000,
1543                 .div = 1,
1544         },
1545         {
1546                 .freq = 816000000,
1547                 .div = 1,
1548         },
1549         {
1550                 .freq = 696000000,
1551                 .div = 1,
1552         },
1553         {
1554                 .freq = 600000000,
1555                 .div = 1,
1556         },
1557         {
1558                 .freq = 408000000,
1559                 .div = 1,
1560         },
1561         {
1562                 .freq = 312000000,
1563                 .div = 1,
1564         },
1565         {
1566                 .freq = 216000000,
1567                 .div = 1,
1568         },
1569         {
1570                 .freq = 96000000,
1571                 .div = 1,
1572         },
1573 };
1574
1575 static struct rk_clk_armclk_def armclk_l = {
1576         .clkdef = {
1577                 .id = ARMCLKL,
1578                 .name = "armclkl",
1579                 .parent_names = armclk_parents,
1580                 .parent_cnt = nitems(armclk_parents),
1581         },
1582         /* CRU_CLKSEL_CON0 */
1583         .muxdiv_offset = 0x100,
1584         .mux_shift = 6,
1585         .mux_width = 2,
1586
1587         .div_shift = 0,
1588         .div_width = 5,
1589
1590         .flags = RK_CLK_COMPOSITE_HAVE_MUX,
1591         .main_parent = 0,
1592         .alt_parent = 3,
1593
1594         .rates = rk3399_armclkl_rates,
1595         .nrates = nitems(rk3399_armclkl_rates),
1596 };
1597
1598 static struct rk_clk_armclk_rates rk3399_armclkb_rates[] = {
1599         {
1600                 .freq = 2208000000,
1601                 .div = 1,
1602         },
1603         {
1604                 .freq = 2184000000,
1605                 .div = 1,
1606         },
1607         {
1608                 .freq = 2088000000,
1609                 .div = 1,
1610         },
1611         {
1612                 .freq = 2040000000,
1613                 .div = 1,
1614         },
1615         {
1616                 .freq = 2016000000,
1617                 .div = 1,
1618         },
1619         {
1620                 .freq = 1992000000,
1621                 .div = 1,
1622         },
1623         {
1624                 .freq = 1896000000,
1625                 .div = 1,
1626         },
1627         {
1628                 .freq = 1800000000,
1629                 .div = 1,
1630         },
1631         {
1632                 .freq = 1704000000,
1633                 .div = 1,
1634         },
1635         {
1636                 .freq = 1608000000,
1637                 .div = 1,
1638         },
1639         {
1640                 .freq = 1512000000,
1641                 .div = 1,
1642         },
1643         {
1644                 .freq = 1488000000,
1645                 .div = 1,
1646         },
1647         {
1648                 .freq = 1416000000,
1649                 .div = 1,
1650         },
1651         {
1652                 .freq = 1200000000,
1653                 .div = 1,
1654         },
1655         {
1656                 .freq = 1008000000,
1657                 .div = 1,
1658         },
1659         {
1660                 .freq = 816000000,
1661                 .div = 1,
1662         },
1663         {
1664                 .freq = 696000000,
1665                 .div = 1,
1666         },
1667         {
1668                 .freq = 600000000,
1669                 .div = 1,
1670         },
1671         {
1672                 .freq = 408000000,
1673                 .div = 1,
1674         },
1675         {
1676                 .freq = 312000000,
1677                 .div = 1,
1678         },
1679         {
1680                 .freq = 216000000,
1681                 .div = 1,
1682         },
1683         {
1684                 .freq = 96000000,
1685                 .div = 1,
1686         },
1687 };
1688
1689 static struct rk_clk_armclk_def armclk_b = {
1690         .clkdef = {
1691                 .id = ARMCLKB,
1692                 .name = "armclkb",
1693                 .parent_names = armclk_parents,
1694                 .parent_cnt = nitems(armclk_parents),
1695         },
1696         .muxdiv_offset = 0x108,
1697         .mux_shift = 6,
1698         .mux_width = 2,
1699
1700         .div_shift = 0,
1701         .div_width = 5,
1702
1703         .flags = RK_CLK_COMPOSITE_HAVE_MUX,
1704         .main_parent = 1,
1705         .alt_parent = 3,
1706
1707         .rates = rk3399_armclkb_rates,
1708         .nrates = nitems(rk3399_armclkb_rates),
1709 };
1710
1711 /*
1712  * sdmmc
1713  */
1714
1715 #define HCLK_SD         461
1716
1717 static const char *hclk_sd_parents[] = {"cpll", "gpll"};
1718
1719 static struct rk_clk_composite_def hclk_sd = {
1720         .clkdef = {
1721                 .id = HCLK_SD,
1722                 .name = "hclk_sd",
1723                 .parent_names = hclk_sd_parents,
1724                 .parent_cnt = nitems(hclk_sd_parents),
1725         },
1726
1727         .muxdiv_offset = 0x134,
1728         .mux_shift = 15,
1729         .mux_width = 1,
1730
1731         .div_shift = 8,
1732         .div_width = 5,
1733
1734         .gate_offset = 0x330,
1735         .gate_shift = 13,
1736
1737         .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
1738 };
1739
1740 #define SCLK_SDMMC              76
1741
1742 static const char *sclk_sdmmc_parents[] = {"cpll", "gpll", "npll", "ppll"};
1743
1744 static struct rk_clk_composite_def sclk_sdmmc = {
1745         .clkdef = {
1746                 .id = SCLK_SDMMC,
1747                 .name = "sclk_sdmmc",
1748                 .parent_names = sclk_sdmmc_parents,
1749                 .parent_cnt = nitems(sclk_sdmmc_parents),
1750         },
1751
1752         .muxdiv_offset = 0x140,
1753         .mux_shift = 8,
1754         .mux_width = 3,
1755
1756         .div_shift = 0,
1757         .div_width = 7,
1758
1759         .gate_offset = 0x318,
1760         .gate_shift = 1,
1761
1762         .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
1763 };
1764
1765 /*
1766  * emmc
1767  */
1768
1769 #define SCLK_EMMC               78
1770
1771 static const char *sclk_emmc_parents[] = {"cpll", "gpll", "npll"};
1772
1773 static struct rk_clk_composite_def sclk_emmc = {
1774         .clkdef = {
1775                 .id = SCLK_EMMC,
1776                 .name = "sclk_emmc",
1777                 .parent_names = sclk_emmc_parents,
1778                 .parent_cnt = nitems(sclk_emmc_parents),
1779         },
1780
1781         .muxdiv_offset = 0x158,
1782         .mux_shift = 8,
1783         .mux_width = 3,
1784
1785         .div_shift = 0,
1786         .div_width = 7,
1787
1788         .gate_offset = 0x318,
1789         .gate_shift = 14,
1790
1791         .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
1792 };
1793
1794 #define ACLK_EMMC               240
1795
1796 static const char *aclk_emmc_parents[] = {
1797         "cpll_aclk_emmc_src",
1798         "gpll_aclk_emmc_src"
1799 };
1800
1801 static struct rk_clk_composite_def aclk_emmc = {
1802         .clkdef = {
1803                 .id = ACLK_EMMC,
1804                 .name = "aclk_emmc",
1805                 .parent_names = aclk_emmc_parents,
1806                 .parent_cnt = nitems(aclk_emmc_parents),
1807         },
1808
1809         .muxdiv_offset = 0x154,
1810         .mux_shift = 7,
1811         .mux_width = 1,
1812
1813         .div_shift = 0,
1814         .div_width = 5,
1815
1816         .flags = RK_CLK_COMPOSITE_HAVE_MUX,
1817 };
1818
1819 static struct rk_clk rk3399_clks[] = {
1820         {
1821                 .type = RK3399_CLK_PLL,
1822                 .clk.pll = &lpll
1823         },
1824         {
1825                 .type = RK3399_CLK_PLL,
1826                 .clk.pll = &bpll
1827         },
1828         {
1829                 .type = RK3399_CLK_PLL,
1830                 .clk.pll = &dpll
1831         },
1832         {
1833                 .type = RK3399_CLK_PLL,
1834                 .clk.pll = &cpll
1835         },
1836         {
1837                 .type = RK3399_CLK_PLL,
1838                 .clk.pll = &gpll
1839         },
1840         {
1841                 .type = RK3399_CLK_PLL,
1842                 .clk.pll = &npll
1843         },
1844         {
1845                 .type = RK3399_CLK_PLL,
1846                 .clk.pll = &vpll
1847         },
1848
1849         {
1850                 .type = RK_CLK_COMPOSITE,
1851                 .clk.composite = &aclk_perihp,
1852         },
1853         {
1854                 .type = RK_CLK_COMPOSITE,
1855                 .clk.composite = &hclk_perihp,
1856         },
1857         {
1858                 .type = RK_CLK_COMPOSITE,
1859                 .clk.composite = &pclk_perihp,
1860         },
1861         {
1862                 .type = RK_CLK_COMPOSITE,
1863                 .clk.composite = &aclk_perilp0,
1864         },
1865         {
1866                 .type = RK_CLK_COMPOSITE,
1867                 .clk.composite = &hclk_perilp0,
1868         },
1869         {
1870                 .type = RK_CLK_COMPOSITE,
1871                 .clk.composite = &pclk_perilp0,
1872         },
1873         {
1874                 .type = RK_CLK_COMPOSITE,
1875                 .clk.composite = &pclk_alive,
1876         },
1877         {
1878                 .type = RK_CLK_COMPOSITE,
1879                 .clk.composite = &hclk_perilp1,
1880         },
1881         {
1882                 .type = RK_CLK_COMPOSITE,
1883                 .clk.composite = &pclk_perilp1,
1884         },
1885         {
1886                 .type = RK_CLK_COMPOSITE,
1887                 .clk.composite = &aclk_usb3,
1888         },
1889         {
1890                 .type = RK_CLK_COMPOSITE,
1891                 .clk.composite = &i2c1,
1892         },
1893         {
1894                 .type = RK_CLK_COMPOSITE,
1895                 .clk.composite = &i2c2,
1896         },
1897         {
1898                 .type = RK_CLK_COMPOSITE,
1899                 .clk.composite = &i2c3,
1900         },
1901         {
1902                 .type = RK_CLK_COMPOSITE,
1903                 .clk.composite = &i2c5,
1904         },
1905         {
1906                 .type = RK_CLK_COMPOSITE,
1907                 .clk.composite = &i2c6,
1908         },
1909         {
1910                 .type = RK_CLK_COMPOSITE,
1911                 .clk.composite = &i2c7,
1912         },
1913         {
1914                 .type = RK_CLK_COMPOSITE,
1915                 .clk.composite = &uphy0_tcpdphy_ref,
1916         },
1917         {
1918                 .type = RK_CLK_COMPOSITE,
1919                 .clk.composite = &uphy0_tcpdcore,
1920         },
1921         {
1922                 .type = RK_CLK_COMPOSITE,
1923                 .clk.composite = &uphy1_tcpdphy_ref,
1924         },
1925         {
1926                 .type = RK_CLK_COMPOSITE,
1927                 .clk.composite = &uphy1_tcpdcore,
1928         },
1929
1930         {
1931                 .type = RK_CLK_COMPOSITE,
1932                 .clk.composite = &spi0,
1933         },
1934         {
1935                 .type = RK_CLK_COMPOSITE,
1936                 .clk.composite = &spi1,
1937         },
1938         {
1939                 .type = RK_CLK_COMPOSITE,
1940                 .clk.composite = &spi2,
1941         },
1942         {
1943                 .type = RK_CLK_COMPOSITE,
1944                 .clk.composite = &spi4,
1945         },
1946         {
1947                 .type = RK_CLK_COMPOSITE,
1948                 .clk.composite = &spi5,
1949         },
1950
1951         {
1952                 .type = RK_CLK_ARMCLK,
1953                 .clk.armclk = &armclk_l,
1954         },
1955         {
1956                 .type = RK_CLK_ARMCLK,
1957                 .clk.armclk = &armclk_b,
1958         },
1959
1960         {
1961                 .type = RK_CLK_COMPOSITE,
1962                 .clk.composite = &hclk_sd,
1963         },
1964         {
1965                 .type = RK_CLK_COMPOSITE,
1966                 .clk.composite = &sclk_sdmmc,
1967         },
1968
1969         {
1970                 .type = RK_CLK_COMPOSITE,
1971                 .clk.composite = &sclk_emmc,
1972         },
1973         {
1974                 .type = RK_CLK_COMPOSITE,
1975                 .clk.composite = &aclk_emmc,
1976         },
1977 };
1978
1979 static int
1980 rk3399_cru_probe(device_t dev)
1981 {
1982
1983         if (!ofw_bus_status_okay(dev))
1984                 return (ENXIO);
1985
1986         if (ofw_bus_is_compatible(dev, "rockchip,rk3399-cru")) {
1987                 device_set_desc(dev, "Rockchip RK3399 Clock and Reset Unit");
1988                 return (BUS_PROBE_DEFAULT);
1989         }
1990
1991         return (ENXIO);
1992 }
1993
1994 static int
1995 rk3399_cru_attach(device_t dev)
1996 {
1997         struct rk_cru_softc *sc;
1998
1999         sc = device_get_softc(dev);
2000         sc->dev = dev;
2001
2002         sc->gates = rk3399_gates;
2003         sc->ngates = nitems(rk3399_gates);
2004
2005         sc->clks = rk3399_clks;
2006         sc->nclks = nitems(rk3399_clks);
2007
2008         sc->reset_offset = 0x400;
2009         sc->reset_num = 335;
2010
2011         return (rk_cru_attach(dev));
2012 }
2013
2014 static device_method_t rk3399_cru_methods[] = {
2015         /* Device interface */
2016         DEVMETHOD(device_probe,         rk3399_cru_probe),
2017         DEVMETHOD(device_attach,        rk3399_cru_attach),
2018
2019         DEVMETHOD_END
2020 };
2021
2022 static devclass_t rk3399_cru_devclass;
2023
2024 DEFINE_CLASS_1(rk3399_cru, rk3399_cru_driver, rk3399_cru_methods,
2025   sizeof(struct rk_cru_softc), rk_cru_driver);
2026
2027 EARLY_DRIVER_MODULE(rk3399_cru, simplebus, rk3399_cru_driver,
2028     rk3399_cru_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE);