sys/arm64/rockchip/clk/rk3399_cru.c

   1 /*-
   2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
   3  *
   4  * Copyright (c) 2018 Emmanuel Vadot <manu@freebsd.org>
   5  * Copyright (c) 2018 Greg V <greg@unrelenting.technology>
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  17  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  18  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  19  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  20  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  21  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  23  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  24  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  26  * SUCH DAMAGE.
  27  *
  28  * $FreeBSD$
  29  */
  30
  31 #include <sys/cdefs.h>
  32 __FBSDID("$FreeBSD$");
  33
  34 #include <sys/param.h>
  35 #include <sys/systm.h>
  36 #include <sys/bus.h>
  37 #include <sys/rman.h>
  38 #include <sys/kernel.h>
  39 #include <sys/module.h>
  40 #include <machine/bus.h>
  41
  42 #include <dev/fdt/simplebus.h>
  43
  44 #include <dev/ofw/ofw_bus.h>
  45 #include <dev/ofw/ofw_bus_subr.h>
  46
  47 #include <dev/extres/clk/clk_div.h>
  48 #include <dev/extres/clk/clk_fixed.h>
  49 #include <dev/extres/clk/clk_mux.h>
  50
  51 #include <arm64/rockchip/clk/rk_cru.h>
  52
  53 /* GATES */
  54
  55 #define SCLK_USB2PHY0_REF       123
  56 #define SCLK_USB2PHY1_REF       124
  57 #define ACLK_EMMC_CORE          241
  58 #define ACLK_EMMC_NOC           242
  59 #define ACLK_EMMC_GRF           243
  60 #define PCLK_GPIO2              336
  61 #define PCLK_GPIO3              337
  62 #define PCLK_GPIO4              338
  63 #define PCLK_I2C1               341
  64 #define PCLK_I2C2               342
  65 #define PCLK_I2C3               343
  66 #define PCLK_I2C5               344
  67 #define PCLK_I2C6               345
  68 #define PCLK_I2C7               346
  69 #define HCLK_HOST0              456
  70 #define HCLK_HOST0_ARB          457
  71 #define HCLK_HOST1              458
  72 #define HCLK_HOST1_ARB          459
  73 #define HCLK_SDMMC              462
  74
  75 static struct rk_cru_gate rk3399_gates[] = {
  76         /* CRU_CLKGATE_CON0 */
  77         CRU_GATE(0, "clk_core_l_lpll_src", "lpll", 0x300, 0)
  78         CRU_GATE(0, "clk_core_l_bpll_src", "bpll", 0x300, 1)
  79         CRU_GATE(0, "clk_core_l_dpll_src", "dpll", 0x300, 2)
  80         CRU_GATE(0, "clk_core_l_gpll_src", "gpll", 0x300, 3)
  81
  82         /* CRU_CLKGATE_CON1 */
  83         CRU_GATE(0, "clk_core_b_lpll_src", "lpll", 0x304, 0)
  84         CRU_GATE(0, "clk_core_b_bpll_src", "bpll", 0x304, 1)
  85         CRU_GATE(0, "clk_core_b_dpll_src", "dpll", 0x304, 2)
  86         CRU_GATE(0, "clk_core_b_gpll_src", "gpll", 0x304, 3)
  87
  88         /* CRU_CLKGATE_CON5 */
  89         CRU_GATE(0, "cpll_aclk_perihp_src", "cpll", 0x314, 0)
  90         CRU_GATE(0, "gpll_aclk_perihp_src", "gpll", 0x314, 1)
  91
  92         /* CRU_CLKGATE_CON6 */
  93         CRU_GATE(0, "gpll_aclk_emmc_src", "gpll", 0x318, 12)
  94         CRU_GATE(0, "cpll_aclk_emmc_src", "cpll", 0x318, 13)
  95         CRU_GATE(SCLK_USB2PHY0_REF, "clk_usb2phy0_ref", "xin24m", 0x318, 5)
  96         CRU_GATE(SCLK_USB2PHY1_REF, "clk_usb2phy1_ref", "xin24m", 0x318, 6)
  97
  98         /* CRU_CLKGATE_CON7 */
  99         CRU_GATE(0, "gpll_aclk_perilp0_src", "gpll", 0x31C, 0)
 100         CRU_GATE(0, "cpll_aclk_perilp0_src", "cpll", 0x31C, 1)
 101
 102         /* CRU_CLKGATE_CON8 */
 103         CRU_GATE(0, "hclk_perilp1_cpll_src", "cpll", 0x320, 1)
 104         CRU_GATE(0, "hclk_perilp1_gpll_src", "gpll", 0x320, 0)
 105
 106         /* CRU_CLKGATE_CON20 */
 107         CRU_GATE(HCLK_HOST0, "hclk_host0", "hclk_perihp", 0x350, 5)
 108         CRU_GATE(HCLK_HOST0_ARB, "hclk_host0_arb", "hclk_perihp", 0x350, 6)
 109         CRU_GATE(HCLK_HOST1, "hclk_host1", "hclk_perihp", 0x350, 7)
 110         CRU_GATE(HCLK_HOST1_ARB, "hclk_host1_arb", "hclk_perihp", 0x350, 8)
 111
 112         /* CRU_CLKGATE_CON22 */
 113         CRU_GATE(PCLK_I2C7, "pclk_rki2c7", "pclk_perilp1", 0x358, 5)
 114         CRU_GATE(PCLK_I2C1, "pclk_rki2c1", "pclk_perilp1", 0x358, 6)
 115         CRU_GATE(PCLK_I2C5, "pclk_rki2c5", "pclk_perilp1", 0x358, 7)
 116         CRU_GATE(PCLK_I2C6, "pclk_rki2c6", "pclk_perilp1", 0x358, 8)
 117         CRU_GATE(PCLK_I2C2, "pclk_rki2c2", "pclk_perilp1", 0x358, 9)
 118         CRU_GATE(PCLK_I2C3, "pclk_rki2c3", "pclk_perilp1", 0x358, 10)
 119
 120         /* CRU_CLKGATE_CON31 */
 121         CRU_GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_alive", 0x37c, 3)
 122         CRU_GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_alive", 0x37c, 4)
 123         CRU_GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_alive", 0x37c, 5)
 124
 125         /* CRU_CLKGATE_CON32 */
 126         CRU_GATE(ACLK_EMMC_CORE, "aclk_emmccore", "aclk_emmc", 0x380, 8)
 127         CRU_GATE(ACLK_EMMC_NOC, "aclk_emmc_noc", "aclk_emmc", 0x380, 9)
 128         CRU_GATE(ACLK_EMMC_GRF, "aclk_emmcgrf", "aclk_emmc", 0x380, 10)
 129
 130         /* CRU_CLKGATE_CON33 */
 131         CRU_GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_sd", 0x384, 8)
 132 };
 133
 134
 135 /*
 136  * PLLs
 137  */
 138
 139 #define PLL_APLLL                       1
 140 #define PLL_APLLB                       2
 141 #define PLL_DPLL                        3
 142 #define PLL_CPLL                        4
 143 #define PLL_GPLL                        5
 144 #define PLL_NPLL                        6
 145 #define PLL_VPLL                        7
 146
 147 static struct rk_clk_pll_rate rk3399_pll_rates[] = {
 148         {
 149                 .freq = 2208000000,
 150                 .refdiv = 1,
 151                 .fbdiv = 92,
 152                 .postdiv1 = 1,
 153                 .postdiv2 = 1,
 154                 .dsmpd = 1,
 155         },
 156         {
 157                 .freq = 2184000000,
 158                 .refdiv = 1,
 159                 .fbdiv = 91,
 160                 .postdiv1 = 1,
 161                 .postdiv2 = 1,
 162                 .dsmpd = 1,
 163         },
 164         {
 165                 .freq = 2160000000,
 166                 .refdiv = 1,
 167                 .fbdiv = 90,
 168                 .postdiv1 = 1,
 169                 .postdiv2 = 1,
 170                 .dsmpd = 1,
 171         },
 172         {
 173                 .freq = 2136000000,
 174                 .refdiv = 1,
 175                 .fbdiv = 89,
 176                 .postdiv1 = 1,
 177                 .postdiv2 = 1,
 178                 .dsmpd = 1,
 179         },
 180         {
 181                 .freq = 2112000000,
 182                 .refdiv = 1,
 183                 .fbdiv = 88,
 184                 .postdiv1 = 1,
 185                 .postdiv2 = 1,
 186                 .dsmpd = 1,
 187         },
 188         {
 189                 .freq = 2088000000,
 190                 .refdiv = 1,
 191                 .fbdiv = 87,
 192                 .postdiv1 = 1,
 193                 .postdiv2 = 1,
 194                 .dsmpd = 1,
 195         },
 196         {
 197                 .freq = 2064000000,
 198                 .refdiv = 1,
 199                 .fbdiv = 86,
 200                 .postdiv1 = 1,
 201                 .postdiv2 = 1,
 202                 .dsmpd = 1,
 203         },
 204         {
 205                 .freq = 2040000000,
 206                 .refdiv = 1,
 207                 .fbdiv = 85,
 208                 .postdiv1 = 1,
 209                 .postdiv2 = 1,
 210                 .dsmpd = 1,
 211         },
 212         {
 213                 .freq = 2016000000,
 214                 .refdiv = 1,
 215                 .fbdiv = 84,
 216                 .postdiv1 = 1,
 217                 .postdiv2 = 1,
 218                 .dsmpd = 1,
 219         },
 220         {
 221                 .freq = 1992000000,
 222                 .refdiv = 1,
 223                 .fbdiv = 83,
 224                 .postdiv1 = 1,
 225                 .postdiv2 = 1,
 226                 .dsmpd = 1,
 227         },
 228         {
 229                 .freq = 1968000000,
 230                 .refdiv = 1,
 231                 .fbdiv = 82,
 232                 .postdiv1 = 1,
 233                 .postdiv2 = 1,
 234                 .dsmpd = 1,
 235         },
 236         {
 237                 .freq = 1944000000,
 238                 .refdiv = 1,
 239                 .fbdiv = 81,
 240                 .postdiv1 = 1,
 241                 .postdiv2 = 1,
 242                 .dsmpd = 1,
 243         },
 244         {
 245                 .freq = 1920000000,
 246                 .refdiv = 1,
 247                 .fbdiv = 80,
 248                 .postdiv1 = 1,
 249                 .postdiv2 = 1,
 250                 .dsmpd = 1,
 251         },
 252         {
 253                 .freq = 1896000000,
 254                 .refdiv = 1,
 255                 .fbdiv = 79,
 256                 .postdiv1 = 1,
 257                 .postdiv2 = 1,
 258                 .dsmpd = 1,
 259         },
 260         {
 261                 .freq = 1872000000,
 262                 .refdiv = 1,
 263                 .fbdiv = 78,
 264                 .postdiv1 = 1,
 265                 .postdiv2 = 1,
 266                 .dsmpd = 1,
 267         },
 268         {
 269                 .freq = 1848000000,
 270                 .refdiv = 1,
 271                 .fbdiv = 77,
 272                 .postdiv1 = 1,
 273                 .postdiv2 = 1,
 274                 .dsmpd = 1,
 275         },
 276         {
 277                 .freq = 1824000000,
 278                 .refdiv = 1,
 279                 .fbdiv = 76,
 280                 .postdiv1 = 1,
 281                 .postdiv2 = 1,
 282                 .dsmpd = 1,
 283         },
 284         {
 285                 .freq = 1800000000,
 286                 .refdiv = 1,
 287                 .fbdiv = 75,
 288                 .postdiv1 = 1,
 289                 .postdiv2 = 1,
 290                 .dsmpd = 1,
 291         },
 292         {
 293                 .freq = 1776000000,
 294                 .refdiv = 1,
 295                 .fbdiv = 74,
 296                 .postdiv1 = 1,
 297                 .postdiv2 = 1,
 298                 .dsmpd = 1,
 299         },
 300         {
 301                 .freq = 1752000000,
 302                 .refdiv = 1,
 303                 .fbdiv = 73,
 304                 .postdiv1 = 1,
 305                 .postdiv2 = 1,
 306                 .dsmpd = 1,
 307         },
 308         {
 309                 .freq = 1728000000,
 310                 .refdiv = 1,
 311                 .fbdiv = 72,
 312                 .postdiv1 = 1,
 313                 .postdiv2 = 1,
 314                 .dsmpd = 1,
 315         },
 316         {
 317                 .freq = 1704000000,
 318                 .refdiv = 1,
 319                 .fbdiv = 71,
 320                 .postdiv1 = 1,
 321                 .postdiv2 = 1,
 322                 .dsmpd = 1,
 323         },
 324         {
 325                 .freq = 1680000000,
 326                 .refdiv = 1,
 327                 .fbdiv = 70,
 328                 .postdiv1 = 1,
 329                 .postdiv2 = 1,
 330                 .dsmpd = 1,
 331         },
 332         {
 333                 .freq = 1656000000,
 334                 .refdiv = 1,
 335                 .fbdiv = 69,
 336                 .postdiv1 = 1,
 337                 .postdiv2 = 1,
 338                 .dsmpd = 1,
 339         },
 340         {
 341                 .freq = 1632000000,
 342                 .refdiv = 1,
 343                 .fbdiv = 68,
 344                 .postdiv1 = 1,
 345                 .postdiv2 = 1,
 346                 .dsmpd = 1,
 347         },
 348         {
 349                 .freq = 1608000000,
 350                 .refdiv = 1,
 351                 .fbdiv = 67,
 352                 .postdiv1 = 1,
 353                 .postdiv2 = 1,
 354                 .dsmpd = 1,
 355         },
 356         {
 357                 .freq = 1600000000,
 358                 .refdiv = 3,
 359                 .fbdiv = 200,
 360                 .postdiv1 = 1,
 361                 .postdiv2 = 1,
 362                 .dsmpd = 1,
 363         },
 364         {
 365                 .freq = 1584000000,
 366                 .refdiv = 1,
 367                 .fbdiv = 66,
 368                 .postdiv1 = 1,
 369                 .postdiv2 = 1,
 370                 .dsmpd = 1,
 371         },
 372         {
 373                 .freq = 1560000000,
 374                 .refdiv = 1,
 375                 .fbdiv = 65,
 376                 .postdiv1 = 1,
 377                 .postdiv2 = 1,
 378                 .dsmpd = 1,
 379         },
 380         {
 381                 .freq = 1536000000,
 382                 .refdiv = 1,
 383                 .fbdiv = 64,
 384                 .postdiv1 = 1,
 385                 .postdiv2 = 1,
 386                 .dsmpd = 1,
 387         },
 388         {
 389                 .freq = 1512000000,
 390                 .refdiv = 1,
 391                 .fbdiv = 63,
 392                 .postdiv1 = 1,
 393                 .postdiv2 = 1,
 394                 .dsmpd = 1,
 395         },
 396         {
 397                 .freq = 1488000000,
 398                 .refdiv = 1,
 399                 .fbdiv = 62,
 400                 .postdiv1 = 1,
 401                 .postdiv2 = 1,
 402                 .dsmpd = 1,
 403         },
 404         {
 405                 .freq = 1464000000,
 406                 .refdiv = 1,
 407                 .fbdiv = 61,
 408                 .postdiv1 = 1,
 409                 .postdiv2 = 1,
 410                 .dsmpd = 1,
 411         },
 412         {
 413                 .freq = 1440000000,
 414                 .refdiv = 1,
 415                 .fbdiv = 60,
 416                 .postdiv1 = 1,
 417                 .postdiv2 = 1,
 418                 .dsmpd = 1,
 419         },
 420         {
 421                 .freq = 1416000000,
 422                 .refdiv = 1,
 423                 .fbdiv = 59,
 424                 .postdiv1 = 1,
 425                 .postdiv2 = 1,
 426                 .dsmpd = 1,
 427         },
 428         {
 429                 .freq = 1392000000,
 430                 .refdiv = 1,
 431                 .fbdiv = 58,
 432                 .postdiv1 = 1,
 433                 .postdiv2 = 1,
 434                 .dsmpd = 1,
 435         },
 436         {
 437                 .freq = 1368000000,
 438                 .refdiv = 1,
 439                 .fbdiv = 57,
 440                 .postdiv1 = 1,
 441                 .postdiv2 = 1,
 442                 .dsmpd = 1,
 443         },
 444         {
 445                 .freq = 1344000000,
 446                 .refdiv = 1,
 447                 .fbdiv = 56,
 448                 .postdiv1 = 1,
 449                 .postdiv2 = 1,
 450                 .dsmpd = 1,
 451         },
 452         {
 453                 .freq = 1320000000,
 454                 .refdiv = 1,
 455                 .fbdiv = 55,
 456                 .postdiv1 = 1,
 457                 .postdiv2 = 1,
 458                 .dsmpd = 1,
 459         },
 460         {
 461                 .freq = 1296000000,
 462                 .refdiv = 1,
 463                 .fbdiv = 54,
 464                 .postdiv1 = 1,
 465                 .postdiv2 = 1,
 466                 .dsmpd = 1,
 467         },
 468         {
 469                 .freq = 1272000000,
 470                 .refdiv = 1,
 471                 .fbdiv = 53,
 472                 .postdiv1 = 1,
 473                 .postdiv2 = 1,
 474                 .dsmpd = 1,
 475         },
 476         {
 477                 .freq = 1248000000,
 478                 .refdiv = 1,
 479                 .fbdiv = 52,
 480                 .postdiv1 = 1,
 481                 .postdiv2 = 1,
 482                 .dsmpd = 1,
 483         },
 484         {
 485                 .freq = 1200000000,
 486                 .refdiv = 1,
 487                 .fbdiv = 50,
 488                 .postdiv1 = 1,
 489                 .postdiv2 = 1,
 490                 .dsmpd = 1,
 491         },
 492         {
 493                 .freq = 1188000000,
 494                 .refdiv = 2,
 495                 .fbdiv = 99,
 496                 .postdiv1 = 1,
 497                 .postdiv2 = 1,
 498                 .dsmpd = 1,
 499         },
 500         {
 501                 .freq = 1104000000,
 502                 .refdiv = 1,
 503                 .fbdiv = 46,
 504                 .postdiv1 = 1,
 505                 .postdiv2 = 1,
 506                 .dsmpd = 1,
 507         },
 508         {
 509                 .freq = 1100000000,
 510                 .refdiv = 12,
 511                 .fbdiv = 550,
 512                 .postdiv1 = 1,
 513                 .postdiv2 = 1,
 514                 .dsmpd = 1,
 515         },
 516         {
 517                 .freq = 1008000000,
 518                 .refdiv = 1,
 519                 .fbdiv = 84,
 520                 .postdiv1 = 2,
 521                 .postdiv2 = 1,
 522                 .dsmpd = 1,
 523         },
 524         {
 525                 .freq = 1000000000,
 526                 .refdiv = 1,
 527                 .fbdiv = 125,
 528                 .postdiv1 = 3,
 529                 .postdiv2 = 1,
 530                 .dsmpd = 1,
 531         },
 532         {
 533                 .freq = 984000000,
 534                 .refdiv = 1,
 535                 .fbdiv = 82,
 536                 .postdiv1 = 2,
 537                 .postdiv2 = 1,
 538                 .dsmpd = 1,
 539         },
 540         {
 541                 .freq = 960000000,
 542                 .refdiv = 1,
 543                 .fbdiv = 80,
 544                 .postdiv1 = 2,
 545                 .postdiv2 = 1,
 546                 .dsmpd = 1,
 547         },
 548         {
 549                 .freq = 936000000,
 550                 .refdiv = 1,
 551                 .fbdiv = 78,
 552                 .postdiv1 = 2,
 553                 .postdiv2 = 1,
 554                 .dsmpd = 1,
 555         },
 556         {
 557                 .freq = 912000000,
 558                 .refdiv = 1,
 559                 .fbdiv = 76,
 560                 .postdiv1 = 2,
 561                 .postdiv2 = 1,
 562                 .dsmpd = 1,
 563         },
 564         {
 565                 .freq = 900000000,
 566                 .refdiv = 4,
 567                 .fbdiv = 300,
 568                 .postdiv1 = 2,
 569                 .postdiv2 = 1,
 570                 .dsmpd = 1,
 571         },
 572         {
 573                 .freq = 888000000,
 574                 .refdiv = 1,
 575                 .fbdiv = 74,
 576                 .postdiv1 = 2,
 577                 .postdiv2 = 1,
 578                 .dsmpd = 1,
 579         },
 580         {
 581                 .freq = 864000000,
 582                 .refdiv = 1,
 583                 .fbdiv = 72,
 584                 .postdiv1 = 2,
 585                 .postdiv2 = 1,
 586                 .dsmpd = 1,
 587         },
 588         {
 589                 .freq = 840000000,
 590                 .refdiv = 1,
 591                 .fbdiv = 70,
 592                 .postdiv1 = 2,
 593                 .postdiv2 = 1,
 594                 .dsmpd = 1,
 595         },
 596         {
 597                 .freq = 816000000,
 598                 .refdiv = 1,
 599                 .fbdiv = 68,
 600                 .postdiv1 = 2,
 601                 .postdiv2 = 1,
 602                 .dsmpd = 1,
 603         },
 604         {
 605                 .freq = 800000000,
 606                 .refdiv = 1,
 607                 .fbdiv = 100,
 608                 .postdiv1 = 3,
 609                 .postdiv2 = 1,
 610                 .dsmpd = 1,
 611         },
 612         {
 613                 .freq = 700000000,
 614                 .refdiv = 6,
 615                 .fbdiv = 350,
 616                 .postdiv1 = 2,
 617                 .postdiv2 = 1,
 618                 .dsmpd = 1,
 619         },
 620         {
 621                 .freq = 696000000,
 622                 .refdiv = 1,
 623                 .fbdiv = 58,
 624                 .postdiv1 = 2,
 625                 .postdiv2 = 1,
 626                 .dsmpd = 1,
 627         },
 628         {
 629                 .freq = 676000000,
 630                 .refdiv = 3,
 631                 .fbdiv = 169,
 632                 .postdiv1 = 2,
 633                 .postdiv2 = 1,
 634                 .dsmpd = 1,
 635         },
 636         {
 637                 .freq = 600000000,
 638                 .refdiv = 1,
 639                 .fbdiv = 75,
 640                 .postdiv1 = 3,
 641                 .postdiv2 = 1,
 642                 .dsmpd = 1,
 643         },
 644         {
 645                 .freq = 594000000,
 646                 .refdiv = 1,
 647                 .fbdiv = 99,
 648                 .postdiv1 = 4,
 649                 .postdiv2 = 1,
 650                 .dsmpd = 1,
 651         },
 652         {
 653                 .freq = 533250000,
 654                 .refdiv = 8,
 655                 .fbdiv = 711,
 656                 .postdiv1 = 4,
 657                 .postdiv2 = 1,
 658                 .dsmpd = 1,
 659         },
 660         {
 661                 .freq = 504000000,
 662                 .refdiv = 1,
 663                 .fbdiv = 63,
 664                 .postdiv1 = 3,
 665                 .postdiv2 = 1,
 666                 .dsmpd = 1,
 667         },
 668         {
 669                 .freq = 500000000,
 670                 .refdiv = 6,
 671                 .fbdiv = 250,
 672                 .postdiv1 = 2,
 673                 .postdiv2 = 1,
 674                 .dsmpd = 1,
 675         },
 676         {
 677                 .freq = 408000000,
 678                 .refdiv = 1,
 679                 .fbdiv = 68,
 680                 .postdiv1 = 2,
 681                 .postdiv2 = 2,
 682                 .dsmpd = 1,
 683         },
 684         {
 685                 .freq = 312000000,
 686                 .refdiv = 1,
 687                 .fbdiv = 52,
 688                 .postdiv1 = 2,
 689                 .postdiv2 = 2,
 690                 .dsmpd = 1,
 691         },
 692         {
 693                 .freq = 297000000,
 694                 .refdiv = 1,
 695                 .fbdiv = 99,
 696                 .postdiv1 = 4,
 697                 .postdiv2 = 2,
 698                 .dsmpd = 1,
 699         },
 700         {
 701                 .freq = 216000000,
 702                 .refdiv = 1,
 703                 .fbdiv = 72,
 704                 .postdiv1 = 4,
 705                 .postdiv2 = 2,
 706                 .dsmpd = 1,
 707         },
 708         {
 709                 .freq = 148500000,
 710                 .refdiv = 1,
 711                 .fbdiv = 99,
 712                 .postdiv1 = 4,
 713                 .postdiv2 = 4,
 714                 .dsmpd = 1,
 715         },
 716         {
 717                 .freq = 106500000,
 718                 .refdiv = 1,
 719                 .fbdiv = 71,
 720                 .postdiv1 = 4,
 721                 .postdiv2 = 4,
 722                 .dsmpd = 1,
 723         },
 724         {
 725                 .freq = 96000000,
 726                 .refdiv = 1,
 727                 .fbdiv = 64,
 728                 .postdiv1 = 4,
 729                 .postdiv2 = 4,
 730                 .dsmpd = 1,
 731         },
 732         {
 733                 .freq = 74250000,
 734                 .refdiv = 2,
 735                 .fbdiv = 99,
 736                 .postdiv1 = 4,
 737                 .postdiv2 = 4,
 738                 .dsmpd = 1,
 739         },
 740         {
 741                 .freq = 65000000,
 742                 .refdiv = 1,
 743                 .fbdiv = 65,
 744                 .postdiv1 = 6,
 745                 .postdiv2 = 4,
 746                 .dsmpd = 1,
 747         },
 748         {
 749                 .freq = 54000000,
 750                 .refdiv = 1,
 751                 .fbdiv = 54,
 752                 .postdiv1 = 6,
 753                 .postdiv2 = 4,
 754                 .dsmpd = 1,
 755         },
 756         {
 757                 .freq = 27000000,
 758                 .refdiv = 1,
 759                 .fbdiv = 27,
 760                 .postdiv1 = 6,
 761                 .postdiv2 = 4,
 762                 .dsmpd = 1,
 763         },
 764         {},
 765 };
 766
 767 static const char *pll_parents[] = {"xin24m"};
 768
 769 static struct rk_clk_pll_def lpll = {
 770         .clkdef = {
 771                 .id = PLL_APLLL,
 772                 .name = "lpll",
 773                 .parent_names = pll_parents,
 774                 .parent_cnt = nitems(pll_parents),
 775         },
 776         .base_offset = 0x00,
 777         .gate_offset = 0x300,
 778         .gate_shift = 0,
 779         .flags = RK_CLK_PLL_HAVE_GATE,
 780         .rates = rk3399_pll_rates,
 781         .normal_mode = true,
 782 };
 783
 784 static struct rk_clk_pll_def bpll = {
 785         .clkdef = {
 786                 .id = PLL_APLLB,
 787                 .name = "bpll",
 788                 .parent_names = pll_parents,
 789                 .parent_cnt = nitems(pll_parents),
 790         },
 791         .base_offset = 0x20,
 792         .gate_offset = 0x300,
 793         .gate_shift = 1,
 794         .flags = RK_CLK_PLL_HAVE_GATE,
 795         .rates = rk3399_pll_rates,
 796         .normal_mode = true,
 797 };
 798
 799 static struct rk_clk_pll_def dpll = {
 800         .clkdef = {
 801                 .id = PLL_DPLL,
 802                 .name = "dpll",
 803                 .parent_names = pll_parents,
 804                 .parent_cnt = nitems(pll_parents),
 805         },
 806         .base_offset = 0x40,
 807         .gate_offset = 0x300,
 808         .gate_shift = 2,
 809         .flags = RK_CLK_PLL_HAVE_GATE,
 810         .rates = rk3399_pll_rates,
 811 };
 812
 813
 814 static struct rk_clk_pll_def cpll = {
 815         .clkdef = {
 816                 .id = PLL_CPLL,
 817                 .name = "cpll",
 818                 .parent_names = pll_parents,
 819                 .parent_cnt = nitems(pll_parents),
 820         },
 821         .base_offset = 0x60,
 822         .rates = rk3399_pll_rates,
 823 };
 824
 825 static struct rk_clk_pll_def gpll = {
 826         .clkdef = {
 827                 .id = PLL_GPLL,
 828                 .name = "gpll",
 829                 .parent_names = pll_parents,
 830                 .parent_cnt = nitems(pll_parents),
 831         },
 832         .base_offset = 0x80,
 833         .gate_offset = 0x300,
 834         .gate_shift = 3,
 835         .flags = RK_CLK_PLL_HAVE_GATE,
 836         .rates = rk3399_pll_rates,
 837 };
 838
 839 static struct rk_clk_pll_def npll = {
 840         .clkdef = {
 841                 .id = PLL_NPLL,
 842                 .name = "npll",
 843                 .parent_names = pll_parents,
 844                 .parent_cnt = nitems(pll_parents),
 845         },
 846         .base_offset = 0xa0,
 847         .rates = rk3399_pll_rates,
 848 };
 849
 850 static struct rk_clk_pll_def vpll = {
 851         .clkdef = {
 852                 .id = PLL_VPLL,
 853                 .name = "vpll",
 854                 .parent_names = pll_parents,
 855                 .parent_cnt = nitems(pll_parents),
 856         },
 857         .base_offset = 0xc0,
 858         .rates = rk3399_pll_rates,
 859 };
 860
 861 #define ACLK_PERIHP     192
 862 #define HCLK_PERIHP     448
 863 #define PCLK_PERIHP     320
 864
 865 static const char *aclk_perihp_parents[] = {"cpll_aclk_perihp_src", "gpll_aclk_perihp_src"};
 866
 867 static struct rk_clk_composite_def aclk_perihp = {
 868         .clkdef = {
 869                 .id = ACLK_PERIHP,
 870                 .name = "aclk_perihp",
 871                 .parent_names = aclk_perihp_parents,
 872                 .parent_cnt = nitems(aclk_perihp_parents),
 873         },
 874         /* CRU_CLKSEL_CON14 */
 875         .muxdiv_offset = 0x138,
 876
 877         .mux_shift = 7,
 878         .mux_width = 1,
 879
 880         .div_shift = 0,
 881         .div_width = 5,
 882
 883         /* CRU_CLKGATE_CON5 */
 884         .gate_offset = 0x314,
 885         .gate_shift = 2,
 886
 887         .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
 888 };
 889
 890 static const char *hclk_pclk_perihp_parents[] = {"aclk_perihp"};
 891
 892 static struct rk_clk_composite_def hclk_perihp = {
 893         .clkdef = {
 894                 .id = HCLK_PERIHP,
 895                 .name = "hclk_perihp",
 896                 .parent_names = hclk_pclk_perihp_parents,
 897                 .parent_cnt = nitems(hclk_pclk_perihp_parents),
 898         },
 899         /* CRU_CLKSEL_CON14 */
 900         .muxdiv_offset = 0x138,
 901
 902         .div_shift = 8,
 903         .div_width = 2,
 904
 905         /* CRU_CLKGATE_CON5 */
 906         .gate_offset = 0x314,
 907         .gate_shift = 3,
 908
 909         .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
 910 };
 911
 912 static struct rk_clk_composite_def pclk_perihp = {
 913         .clkdef = {
 914                 .id = PCLK_PERIHP,
 915                 .name = "pclk_perihp",
 916                 .parent_names = hclk_pclk_perihp_parents,
 917                 .parent_cnt = nitems(hclk_pclk_perihp_parents),
 918         },
 919         /* CRU_CLKSEL_CON14 */
 920         .muxdiv_offset = 0x138,
 921
 922         .div_shift = 12,
 923         .div_width = 3,
 924
 925         /* CRU_CLKGATE_CON5 */
 926         .gate_offset = 0x314,
 927         .gate_shift = 4,
 928
 929         .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
 930 };
 931
 932 #define ACLK_PERILP0    194
 933 #define HCLK_PERILP0    449
 934 #define PCLK_PERILP0    322
 935
 936 static const char *aclk_perilp0_parents[] = {"cpll_aclk_perilp0_src", "gpll_aclk_perilp0_src"};
 937
 938 static struct rk_clk_composite_def aclk_perilp0 = {
 939         .clkdef = {
 940                 .id = ACLK_PERILP0,
 941                 .name = "aclk_perilp0",
 942                 .parent_names = aclk_perilp0_parents,
 943                 .parent_cnt = nitems(aclk_perilp0_parents),
 944         },
 945         /* CRU_CLKSEL_CON14 */
 946         .muxdiv_offset = 0x15C,
 947
 948         .mux_shift = 7,
 949         .mux_width = 1,
 950
 951         .div_shift = 0,
 952         .div_width = 5,
 953
 954         /* CRU_CLKGATE_CON7 */
 955         .gate_offset = 0x31C,
 956         .gate_shift = 2,
 957
 958         .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
 959 };
 960
 961 static const char *hclk_pclk_perilp0_parents[] = {"aclk_perilp0"};
 962
 963 static struct rk_clk_composite_def hclk_perilp0 = {
 964         .clkdef = {
 965                 .id = HCLK_PERILP0,
 966                 .name = "hclk_perilp0",
 967                 .parent_names = hclk_pclk_perilp0_parents,
 968                 .parent_cnt = nitems(hclk_pclk_perilp0_parents),
 969         },
 970         /* CRU_CLKSEL_CON23 */
 971         .muxdiv_offset = 0x15C,
 972
 973         .div_shift = 8,
 974         .div_width = 2,
 975
 976         /* CRU_CLKGATE_CON7 */
 977         .gate_offset = 0x31C,
 978         .gate_shift = 3,
 979
 980         .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
 981 };
 982
 983 static struct rk_clk_composite_def pclk_perilp0 = {
 984         .clkdef = {
 985                 .id = PCLK_PERILP0,
 986                 .name = "pclk_perilp0",
 987                 .parent_names = hclk_pclk_perilp0_parents,
 988                 .parent_cnt = nitems(hclk_pclk_perilp0_parents),
 989         },
 990         /* CRU_CLKSEL_CON23 */
 991         .muxdiv_offset = 0x15C,
 992
 993         .div_shift = 12,
 994         .div_width = 3,
 995
 996         /* CRU_CLKGATE_CON7 */
 997         .gate_offset = 0x31C,
 998         .gate_shift = 4,
 999
1000         .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
1001 };
1002
1003 /*
1004  * misc
1005  */
1006 #define PCLK_ALIVE              390
1007
1008 static const char *alive_parents[] = {"gpll"};
1009
1010 static struct rk_clk_composite_def pclk_alive = {
1011         .clkdef = {
1012                 .id = PCLK_ALIVE,
1013                 .name = "pclk_alive",
1014                 .parent_names = alive_parents,
1015                 .parent_cnt = nitems(alive_parents),
1016         },
1017         /* CRU_CLKSEL_CON57 */
1018         .muxdiv_offset = 0x01e4,
1019
1020         .div_shift = 0,
1021         .div_width = 5,
1022 };
1023
1024 #define HCLK_PERILP1            450
1025 #define PCLK_PERILP1            323
1026
1027 static const char *hclk_perilp1_parents[] = {"cpll", "gpll"};
1028
1029 static struct rk_clk_composite_def hclk_perilp1 = {
1030         .clkdef = {
1031                 .id = HCLK_PERILP1,
1032                 .name = "hclk_perilp1",
1033                 .parent_names = hclk_perilp1_parents,
1034                 .parent_cnt = nitems(hclk_perilp1_parents),
1035         },
1036         /* CRU_CLKSEL_CON25 */
1037         .muxdiv_offset = 0x164,
1038         .mux_shift = 7,
1039         .mux_width = 1,
1040
1041         .div_shift = 0,
1042         .div_width = 5,
1043
1044         .flags = RK_CLK_COMPOSITE_HAVE_MUX,
1045 };
1046
1047 static const char *pclk_perilp1_parents[] = {"hclk_perilp1"};
1048
1049 static struct rk_clk_composite_def pclk_perilp1 = {
1050         .clkdef = {
1051                 .id = PCLK_PERILP1,
1052                 .name = "pclk_perilp1",
1053                 .parent_names = pclk_perilp1_parents,
1054                 .parent_cnt = nitems(pclk_perilp1_parents),
1055         },
1056         /* CRU_CLKSEL_CON25 */
1057         .muxdiv_offset = 0x164,
1058
1059         .div_shift = 8,
1060         .div_width = 3,
1061
1062         /* CRU_CLKGATE_CON8 */
1063         .gate_offset = 0x320,
1064         .gate_shift = 2,
1065
1066         .flags = RK_CLK_COMPOSITE_HAVE_GATE,
1067 };
1068
1069 /*
1070  * i2c
1071  */
1072 static const char *i2c_parents[] = {"cpll", "gpll"};
1073
1074 #define SCLK_I2C1       65
1075 #define SCLK_I2C2       66
1076 #define SCLK_I2C3       67
1077 #define SCLK_I2C5       68
1078 #define SCLK_I2C6       69
1079 #define SCLK_I2C7       70
1080
1081 static struct rk_clk_composite_def i2c1 = {
1082         .clkdef = {
1083                 .id = SCLK_I2C1,
1084                 .name = "clk_i2c1",
1085                 .parent_names = i2c_parents,
1086                 .parent_cnt = nitems(i2c_parents),
1087         },
1088         /* CRU_CLKSEL_CON61 */
1089         .muxdiv_offset = 0x01f4,
1090         .mux_shift = 7,
1091         .mux_width = 1,
1092
1093         .div_shift = 0,
1094         .div_width = 7,
1095
1096         /* CRU_CLKGATE_CON10 */
1097         .gate_offset = 0x0328,
1098         .gate_shift = 0,
1099
1100         .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
1101 };
1102
1103 static struct rk_clk_composite_def i2c2 = {
1104         .clkdef = {
1105                 .id = SCLK_I2C2,
1106                 .name = "clk_i2c2",
1107                 .parent_names = i2c_parents,
1108                 .parent_cnt = nitems(i2c_parents),
1109         },
1110         /* CRU_CLKSEL_CON62 */
1111         .muxdiv_offset = 0x01f8,
1112         .mux_shift = 7,
1113         .mux_width = 1,
1114
1115         .div_shift = 0,
1116         .div_width = 7,
1117
1118         /* CRU_CLKGATE_CON10 */
1119         .gate_offset = 0x0328,
1120         .gate_shift = 2,
1121
1122         .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
1123 };
1124
1125 static struct rk_clk_composite_def i2c3 = {
1126         .clkdef = {
1127                 .id = SCLK_I2C3,
1128                 .name = "clk_i2c3",
1129                 .parent_names = i2c_parents,
1130                 .parent_cnt = nitems(i2c_parents),
1131         },
1132         /* CRU_CLKSEL_CON63 */
1133         .muxdiv_offset = 0x01fc,
1134         .mux_shift = 7,
1135         .mux_width = 1,
1136
1137         .div_shift = 0,
1138         .div_width = 7,
1139
1140         /* CRU_CLKGATE_CON10 */
1141         .gate_offset = 0x0328,
1142         .gate_shift = 4,
1143
1144         .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
1145 };
1146
1147 static struct rk_clk_composite_def i2c5 = {
1148         .clkdef = {
1149                 .id = SCLK_I2C5,
1150                 .name = "clk_i2c5",
1151                 .parent_names = i2c_parents,
1152                 .parent_cnt = nitems(i2c_parents),
1153         },
1154         /* CRU_CLKSEL_CON61 */
1155         .muxdiv_offset = 0x01f4,
1156         .mux_shift = 15,
1157         .mux_width = 1,
1158
1159         .div_shift = 8,
1160         .div_width = 7,
1161
1162         /* CRU_CLKGATE_CON10 */
1163         .gate_offset = 0x0328,
1164         .gate_shift = 1,
1165
1166         .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
1167 };
1168
1169 static struct rk_clk_composite_def i2c6 = {
1170         .clkdef = {
1171                 .id = SCLK_I2C6,
1172                 .name = "clk_i2c6",
1173                 .parent_names = i2c_parents,
1174                 .parent_cnt = nitems(i2c_parents),
1175         },
1176         /* CRU_CLKSEL_CON62 */
1177         .muxdiv_offset = 0x01f8,
1178         .mux_shift = 15,
1179         .mux_width = 1,
1180
1181         .div_shift = 8,
1182         .div_width = 7,
1183
1184         /* CRU_CLKGATE_CON10 */
1185         .gate_offset = 0x0328,
1186         .gate_shift = 3,
1187
1188         .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
1189 };
1190
1191 static struct rk_clk_composite_def i2c7 = {
1192         .clkdef = {
1193                 .id = SCLK_I2C7,
1194                 .name = "clk_i2c7",
1195                 .parent_names = i2c_parents,
1196                 .parent_cnt = nitems(i2c_parents),
1197         },
1198         /* CRU_CLKSEL_CON63 */
1199         .muxdiv_offset = 0x01fc,
1200         .mux_shift = 15,
1201         .mux_width = 1,
1202
1203         .div_shift = 8,
1204         .div_width = 7,
1205
1206         /* CRU_CLKGATE_CON10 */
1207         .gate_offset = 0x0328,
1208         .gate_shift = 5,
1209
1210         .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
1211 };
1212
1213 /*
1214  * ARM CPU clocks (LITTLE and big)
1215  */
1216 #define ARMCLKL                         8
1217 #define ARMCLKB                         9
1218
1219 static const char *armclk_parents[] = {"lpll", "bpll", "dpll", "gpll"};
1220
1221 static struct rk_clk_armclk_rates rk3399_armclkl_rates[] = {
1222         {
1223                 .freq = 1800000000,
1224                 .div = 1,
1225         },
1226         {
1227                 .freq = 1704000000,
1228                 .div = 1,
1229         },
1230         {
1231                 .freq = 1608000000,
1232                 .div = 1,
1233         },
1234         {
1235                 .freq = 1512000000,
1236                 .div = 1,
1237         },
1238         {
1239                 .freq = 1488000000,
1240                 .div = 1,
1241         },
1242         {
1243                 .freq = 1416000000,
1244                 .div = 1,
1245         },
1246         {
1247                 .freq = 1200000000,
1248                 .div = 1,
1249         },
1250         {
1251                 .freq = 1008000000,
1252                 .div = 1,
1253         },
1254         {
1255                 .freq = 816000000,
1256                 .div = 1,
1257         },
1258         {
1259                 .freq = 696000000,
1260                 .div = 1,
1261         },
1262         {
1263                 .freq = 600000000,
1264                 .div = 1,
1265         },
1266         {
1267                 .freq = 408000000,
1268                 .div = 1,
1269         },
1270         {
1271                 .freq = 312000000,
1272                 .div = 1,
1273         },
1274         {
1275                 .freq = 216000000,
1276                 .div = 1,
1277         },
1278         {
1279                 .freq = 96000000,
1280                 .div = 1,
1281         },
1282 };
1283
1284 static struct rk_clk_armclk_def armclk_l = {
1285         .clkdef = {
1286                 .id = ARMCLKL,
1287                 .name = "armclkl",
1288                 .parent_names = armclk_parents,
1289                 .parent_cnt = nitems(armclk_parents),
1290         },
1291         /* CRU_CLKSEL_CON0 */
1292         .muxdiv_offset = 0x100,
1293         .mux_shift = 6,
1294         .mux_width = 2,
1295
1296         .div_shift = 0,
1297         .div_width = 5,
1298
1299         .flags = RK_CLK_COMPOSITE_HAVE_MUX,
1300         .main_parent = 0,
1301         .alt_parent = 3,
1302
1303         .rates = rk3399_armclkl_rates,
1304         .nrates = nitems(rk3399_armclkl_rates),
1305 };
1306
1307 static struct rk_clk_armclk_rates rk3399_armclkb_rates[] = {
1308         {
1309                 .freq = 2208000000,
1310                 .div = 1,
1311         },
1312         {
1313                 .freq = 2184000000,
1314                 .div = 1,
1315         },
1316         {
1317                 .freq = 2088000000,
1318                 .div = 1,
1319         },
1320         {
1321                 .freq = 2040000000,
1322                 .div = 1,
1323         },
1324         {
1325                 .freq = 2016000000,
1326                 .div = 1,
1327         },
1328         {
1329                 .freq = 1992000000,
1330                 .div = 1,
1331         },
1332         {
1333                 .freq = 1896000000,
1334                 .div = 1,
1335         },
1336         {
1337                 .freq = 1800000000,
1338                 .div = 1,
1339         },
1340         {
1341                 .freq = 1704000000,
1342                 .div = 1,
1343         },
1344         {
1345                 .freq = 1608000000,
1346                 .div = 1,
1347         },
1348         {
1349                 .freq = 1512000000,
1350                 .div = 1,
1351         },
1352         {
1353                 .freq = 1488000000,
1354                 .div = 1,
1355         },
1356         {
1357                 .freq = 1416000000,
1358                 .div = 1,
1359         },
1360         {
1361                 .freq = 1200000000,
1362                 .div = 1,
1363         },
1364         {
1365                 .freq = 1008000000,
1366                 .div = 1,
1367         },
1368         {
1369                 .freq = 816000000,
1370                 .div = 1,
1371         },
1372         {
1373                 .freq = 696000000,
1374                 .div = 1,
1375         },
1376         {
1377                 .freq = 600000000,
1378                 .div = 1,
1379         },
1380         {
1381                 .freq = 408000000,
1382                 .div = 1,
1383         },
1384         {
1385                 .freq = 312000000,
1386                 .div = 1,
1387         },
1388         {
1389                 .freq = 216000000,
1390                 .div = 1,
1391         },
1392         {
1393                 .freq = 96000000,
1394                 .div = 1,
1395         },
1396 };
1397
1398 static struct rk_clk_armclk_def armclk_b = {
1399         .clkdef = {
1400                 .id = ARMCLKB,
1401                 .name = "armclkb",
1402                 .parent_names = armclk_parents,
1403                 .parent_cnt = nitems(armclk_parents),
1404         },
1405         .muxdiv_offset = 0x108,
1406         .mux_shift = 6,
1407         .mux_width = 2,
1408
1409         .div_shift = 0,
1410         .div_width = 5,
1411
1412         .flags = RK_CLK_COMPOSITE_HAVE_MUX,
1413         .main_parent = 1,
1414         .alt_parent = 3,
1415
1416         .rates = rk3399_armclkb_rates,
1417         .nrates = nitems(rk3399_armclkb_rates),
1418 };
1419
1420 /*
1421  * sdmmc
1422  */
1423
1424 #define HCLK_SD         461
1425
1426 static const char *hclk_sd_parents[] = {"cpll", "gpll"};
1427
1428 static struct rk_clk_composite_def hclk_sd = {
1429         .clkdef = {
1430                 .id = HCLK_SD,
1431                 .name = "hclk_sd",
1432                 .parent_names = hclk_sd_parents,
1433                 .parent_cnt = nitems(hclk_sd_parents),
1434         },
1435
1436         .muxdiv_offset = 0x134,
1437         .mux_shift = 15,
1438         .mux_width = 1,
1439
1440         .div_shift = 8,
1441         .div_width = 5,
1442
1443         .gate_offset = 0x330,
1444         .gate_shift = 13,
1445
1446         .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
1447 };
1448
1449 #define SCLK_SDMMC              76
1450
1451 static const char *sclk_sdmmc_parents[] = {"cpll", "gpll", "npll", "ppll"};
1452
1453 static struct rk_clk_composite_def sclk_sdmmc = {
1454         .clkdef = {
1455                 .id = SCLK_SDMMC,
1456                 .name = "sclk_sdmmc",
1457                 .parent_names = sclk_sdmmc_parents,
1458                 .parent_cnt = nitems(sclk_sdmmc_parents),
1459         },
1460
1461         .muxdiv_offset = 0x140,
1462         .mux_shift = 8,
1463         .mux_width = 3,
1464
1465         .div_shift = 0,
1466         .div_width = 7,
1467
1468         .gate_offset = 0x318,
1469         .gate_shift = 1,
1470
1471         .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
1472 };
1473
1474 /*
1475  * emmc
1476  */
1477
1478 #define SCLK_EMMC               78
1479
1480 static const char *sclk_emmc_parents[] = {"cpll", "gpll", "npll"};
1481
1482 static struct rk_clk_composite_def sclk_emmc = {
1483         .clkdef = {
1484                 .id = SCLK_EMMC,
1485                 .name = "sclk_emmc",
1486                 .parent_names = sclk_emmc_parents,
1487                 .parent_cnt = nitems(sclk_emmc_parents),
1488         },
1489
1490         .muxdiv_offset = 0x158,
1491         .mux_shift = 8,
1492         .mux_width = 3,
1493
1494         .div_shift = 0,
1495         .div_width = 7,
1496
1497         .gate_offset = 0x318,
1498         .gate_shift = 14,
1499
1500         .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
1501 };
1502
1503 #define ACLK_EMMC               240
1504
1505 static const char *aclk_emmc_parents[] = {
1506         "cpll_aclk_emmc_src",
1507         "gpll_aclk_emmc_src"
1508 };
1509
1510 static struct rk_clk_composite_def aclk_emmc = {
1511         .clkdef = {
1512                 .id = ACLK_EMMC,
1513                 .name = "aclk_emmc",
1514                 .parent_names = aclk_emmc_parents,
1515                 .parent_cnt = nitems(aclk_emmc_parents),
1516         },
1517
1518         .muxdiv_offset = 0x154,
1519         .mux_shift = 7,
1520         .mux_width = 1,
1521
1522         .div_shift = 0,
1523         .div_width = 5,
1524
1525         .flags = RK_CLK_COMPOSITE_HAVE_MUX,
1526 };
1527
1528 static struct rk_clk rk3399_clks[] = {
1529         {
1530                 .type = RK3399_CLK_PLL,
1531                 .clk.pll = &lpll
1532         },
1533         {
1534                 .type = RK3399_CLK_PLL,
1535                 .clk.pll = &bpll
1536         },
1537         {
1538                 .type = RK3399_CLK_PLL,
1539                 .clk.pll = &dpll
1540         },
1541         {
1542                 .type = RK3399_CLK_PLL,
1543                 .clk.pll = &cpll
1544         },
1545         {
1546                 .type = RK3399_CLK_PLL,
1547                 .clk.pll = &gpll
1548         },
1549         {
1550                 .type = RK3399_CLK_PLL,
1551                 .clk.pll = &npll
1552         },
1553         {
1554                 .type = RK3399_CLK_PLL,
1555                 .clk.pll = &vpll
1556         },
1557
1558         {
1559                 .type = RK_CLK_COMPOSITE,
1560                 .clk.composite = &aclk_perihp,
1561         },
1562         {
1563                 .type = RK_CLK_COMPOSITE,
1564                 .clk.composite = &hclk_perihp,
1565         },
1566         {
1567                 .type = RK_CLK_COMPOSITE,
1568                 .clk.composite = &pclk_perihp,
1569         },
1570         {
1571                 .type = RK_CLK_COMPOSITE,
1572                 .clk.composite = &aclk_perilp0,
1573         },
1574         {
1575                 .type = RK_CLK_COMPOSITE,
1576                 .clk.composite = &hclk_perilp0,
1577         },
1578         {
1579                 .type = RK_CLK_COMPOSITE,
1580                 .clk.composite = &pclk_perilp0,
1581         },
1582         {
1583                 .type = RK_CLK_COMPOSITE,
1584                 .clk.composite = &pclk_alive,
1585         },
1586         {
1587                 .type = RK_CLK_COMPOSITE,
1588                 .clk.composite = &hclk_perilp1,
1589         },
1590         {
1591                 .type = RK_CLK_COMPOSITE,
1592                 .clk.composite = &pclk_perilp1,
1593         },
1594         {
1595                 .type = RK_CLK_COMPOSITE,
1596                 .clk.composite = &i2c1,
1597         },
1598         {
1599                 .type = RK_CLK_COMPOSITE,
1600                 .clk.composite = &i2c2,
1601         },
1602         {
1603                 .type = RK_CLK_COMPOSITE,
1604                 .clk.composite = &i2c3,
1605         },
1606         {
1607                 .type = RK_CLK_COMPOSITE,
1608                 .clk.composite = &i2c5,
1609         },
1610         {
1611                 .type = RK_CLK_COMPOSITE,
1612                 .clk.composite = &i2c6,
1613         },
1614         {
1615                 .type = RK_CLK_COMPOSITE,
1616                 .clk.composite = &i2c7,
1617         },
1618
1619         {
1620                 .type = RK_CLK_ARMCLK,
1621                 .clk.armclk = &armclk_l,
1622         },
1623         {
1624                 .type = RK_CLK_ARMCLK,
1625                 .clk.armclk = &armclk_b,
1626         },
1627
1628         {
1629                 .type = RK_CLK_COMPOSITE,
1630                 .clk.composite = &hclk_sd,
1631         },
1632         {
1633                 .type = RK_CLK_COMPOSITE,
1634                 .clk.composite = &sclk_sdmmc,
1635         },
1636
1637         {
1638                 .type = RK_CLK_COMPOSITE,
1639                 .clk.composite = &sclk_emmc,
1640         },
1641         {
1642                 .type = RK_CLK_COMPOSITE,
1643                 .clk.composite = &aclk_emmc,
1644         },
1645 };
1646
1647 static int
1648 rk3399_cru_probe(device_t dev)
1649 {
1650
1651         if (!ofw_bus_status_okay(dev))
1652                 return (ENXIO);
1653
1654         if (ofw_bus_is_compatible(dev, "rockchip,rk3399-cru")) {
1655                 device_set_desc(dev, "Rockchip RK3399 Clock and Reset Unit");
1656                 return (BUS_PROBE_DEFAULT);
1657         }
1658
1659         return (ENXIO);
1660 }
1661
1662 static int
1663 rk3399_cru_attach(device_t dev)
1664 {
1665         struct rk_cru_softc *sc;
1666
1667         sc = device_get_softc(dev);
1668         sc->dev = dev;
1669
1670         sc->gates = rk3399_gates;
1671         sc->ngates = nitems(rk3399_gates);
1672
1673         sc->clks = rk3399_clks;
1674         sc->nclks = nitems(rk3399_clks);
1675
1676         sc->reset_offset = 0x400;
1677         sc->reset_num = 335;
1678
1679         return (rk_cru_attach(dev));
1680 }
1681
1682 static device_method_t rk3399_cru_methods[] = {
1683         /* Device interface */
1684         DEVMETHOD(device_probe,         rk3399_cru_probe),
1685         DEVMETHOD(device_attach,        rk3399_cru_attach),
1686
1687         DEVMETHOD_END
1688 };
1689
1690 static devclass_t rk3399_cru_devclass;
1691
1692 DEFINE_CLASS_1(rk3399_cru, rk3399_cru_driver, rk3399_cru_methods,
1693   sizeof(struct rk_cru_softc), rk_cru_driver);
1694
1695 EARLY_DRIVER_MODULE(rk3399_cru, simplebus, rk3399_cru_driver,
1696     rk3399_cru_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE);