2 * Copyright (c) 2010 Isilon Systems, Inc.
3 * Copyright (c) 2010 iX Systems, Inc.
4 * Copyright (c) 2010 Panasas, Inc.
5 * Copyright (c) 2013-2016 Mellanox Technologies, Ltd.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice unmodified, this list of conditions, and the following
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #define CONFIG_PCI_MSI
36 #include <linux/types.h>
38 #include <sys/param.h>
40 #include <sys/pciio.h>
42 #include <dev/pci/pcivar.h>
43 #include <dev/pci/pcireg.h>
44 #include <dev/pci/pci_private.h>
46 #include <machine/resource.h>
48 #include <linux/list.h>
49 #include <linux/dmapool.h>
50 #include <linux/dma-mapping.h>
51 #include <linux/compiler.h>
52 #include <linux/errno.h>
53 #include <asm/atomic.h>
54 #include <linux/device.h>
56 struct pci_device_id {
63 uintptr_t driver_data;
66 #define MODULE_DEVICE_TABLE(bus, table)
68 #define PCI_BASE_CLASS_DISPLAY 0x03
69 #define PCI_CLASS_DISPLAY_VGA 0x0300
70 #define PCI_CLASS_DISPLAY_OTHER 0x0380
71 #define PCI_BASE_CLASS_BRIDGE 0x06
72 #define PCI_CLASS_BRIDGE_ISA 0x0601
74 #define PCI_ANY_ID -1U
75 #define PCI_VENDOR_ID_APPLE 0x106b
76 #define PCI_VENDOR_ID_ASUSTEK 0x1043
77 #define PCI_VENDOR_ID_ATI 0x1002
78 #define PCI_VENDOR_ID_DELL 0x1028
79 #define PCI_VENDOR_ID_HP 0x103c
80 #define PCI_VENDOR_ID_IBM 0x1014
81 #define PCI_VENDOR_ID_INTEL 0x8086
82 #define PCI_VENDOR_ID_MELLANOX 0x15b3
83 #define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4
84 #define PCI_VENDOR_ID_SERVERWORKS 0x1166
85 #define PCI_VENDOR_ID_SONY 0x104d
86 #define PCI_VENDOR_ID_TOPSPIN 0x1867
87 #define PCI_VENDOR_ID_VIA 0x1106
88 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
89 #define PCI_DEVICE_ID_ATI_RADEON_QY 0x5159
90 #define PCI_DEVICE_ID_MELLANOX_TAVOR 0x5a44
91 #define PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE 0x5a46
92 #define PCI_DEVICE_ID_MELLANOX_ARBEL_COMPAT 0x6278
93 #define PCI_DEVICE_ID_MELLANOX_ARBEL 0x6282
94 #define PCI_DEVICE_ID_MELLANOX_SINAI_OLD 0x5e8c
95 #define PCI_DEVICE_ID_MELLANOX_SINAI 0x6274
96 #define PCI_SUBDEVICE_ID_QEMU 0x1100
98 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
99 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
100 #define PCI_FUNC(devfn) ((devfn) & 0x07)
101 #define PCI_BUS_NUM(devfn) (((devfn) >> 8) & 0xff)
103 #define PCI_VDEVICE(_vendor, _device) \
104 .vendor = PCI_VENDOR_ID_##_vendor, .device = (_device), \
105 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
106 #define PCI_DEVICE(_vendor, _device) \
107 .vendor = (_vendor), .device = (_device), \
108 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
110 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
112 #define PCI_VENDOR_ID PCIR_DEVVENDOR
113 #define PCI_COMMAND PCIR_COMMAND
114 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL /* Device Control */
115 #define PCI_EXP_LNKCTL PCIER_LINK_CTL /* Link Control */
116 #define PCI_EXP_FLAGS_TYPE PCIEM_FLAGS_TYPE /* Device/Port type */
117 #define PCI_EXP_DEVCAP PCIER_DEVICE_CAP /* Device capabilities */
118 #define PCI_EXP_DEVSTA PCIER_DEVICE_STA /* Device Status */
119 #define PCI_EXP_LNKCAP PCIER_LINK_CAP /* Link Capabilities */
120 #define PCI_EXP_LNKSTA PCIER_LINK_STA /* Link Status */
121 #define PCI_EXP_SLTCAP PCIER_SLOT_CAP /* Slot Capabilities */
122 #define PCI_EXP_SLTCTL PCIER_SLOT_CTL /* Slot Control */
123 #define PCI_EXP_SLTSTA PCIER_SLOT_STA /* Slot Status */
124 #define PCI_EXP_RTCTL PCIER_ROOT_CTL /* Root Control */
125 #define PCI_EXP_RTCAP PCIER_ROOT_CAP /* Root Capabilities */
126 #define PCI_EXP_RTSTA PCIER_ROOT_STA /* Root Status */
127 #define PCI_EXP_DEVCAP2 PCIER_DEVICE_CAP2 /* Device Capabilities 2 */
128 #define PCI_EXP_DEVCTL2 PCIER_DEVICE_CTL2 /* Device Control 2 */
129 #define PCI_EXP_LNKCAP2 PCIER_LINK_CAP2 /* Link Capabilities 2 */
130 #define PCI_EXP_LNKCTL2 PCIER_LINK_CTL2 /* Link Control 2 */
131 #define PCI_EXP_LNKSTA2 PCIER_LINK_STA2 /* Link Status 2 */
132 #define PCI_EXP_FLAGS PCIER_FLAGS /* Capabilities register */
133 #define PCI_EXP_FLAGS_VERS PCIEM_FLAGS_VERSION /* Capability version */
134 #define PCI_EXP_TYPE_ROOT_PORT PCIEM_TYPE_ROOT_PORT /* Root Port */
135 #define PCI_EXP_TYPE_ENDPOINT PCIEM_TYPE_ENDPOINT /* Express Endpoint */
136 #define PCI_EXP_TYPE_LEG_END PCIEM_TYPE_LEGACY_ENDPOINT /* Legacy Endpoint */
137 #define PCI_EXP_TYPE_DOWNSTREAM PCIEM_TYPE_DOWNSTREAM_PORT /* Downstream Port */
138 #define PCI_EXP_FLAGS_SLOT PCIEM_FLAGS_SLOT /* Slot implemented */
139 #define PCI_EXP_TYPE_RC_EC PCIEM_TYPE_ROOT_EC /* Root Complex Event Collector */
140 #define PCI_EXP_LNKCAP_SLS_2_5GB 0x01 /* Supported Link Speed 2.5GT/s */
141 #define PCI_EXP_LNKCAP_SLS_5_0GB 0x02 /* Supported Link Speed 5.0GT/s */
142 #define PCI_EXP_LNKCAP_SLS_8_0GB 0x04 /* Supported Link Speed 8.0GT/s */
143 #define PCI_EXP_LNKCAP_SLS_16_0GB 0x08 /* Supported Link Speed 16.0GT/s */
144 #define PCI_EXP_LNKCAP_MLW 0x03f0 /* Maximum Link Width */
145 #define PCI_EXP_LNKCAP2_SLS_2_5GB 0x02 /* Supported Link Speed 2.5GT/s */
146 #define PCI_EXP_LNKCAP2_SLS_5_0GB 0x04 /* Supported Link Speed 5.0GT/s */
147 #define PCI_EXP_LNKCAP2_SLS_8_0GB 0x08 /* Supported Link Speed 8.0GT/s */
148 #define PCI_EXP_LNKCAP2_SLS_16_0GB 0x10 /* Supported Link Speed 16.0GT/s */
150 #define PCI_EXP_LNKCTL_HAWD PCIEM_LINK_CTL_HAWD
151 #define PCI_EXP_LNKCAP_CLKPM 0x00040000
152 #define PCI_EXP_DEVSTA_TRPND 0x0020
154 #define IORESOURCE_MEM (1 << SYS_RES_MEMORY)
155 #define IORESOURCE_IO (1 << SYS_RES_IOPORT)
156 #define IORESOURCE_IRQ (1 << SYS_RES_IRQ)
159 PCI_SPEED_UNKNOWN = -1,
166 enum pcie_link_width {
167 PCIE_LNK_WIDTH_RESRV = 0x00,
175 PCIE_LNK_WIDTH_UNKNOWN = 0xff,
178 typedef int pci_power_t;
180 #define PCI_D0 PCI_POWERSTATE_D0
181 #define PCI_D1 PCI_POWERSTATE_D1
182 #define PCI_D2 PCI_POWERSTATE_D2
183 #define PCI_D3hot PCI_POWERSTATE_D3
186 #define PCI_POWER_ERROR PCI_POWERSTATE_UNKNOWN
191 struct list_head links;
193 const struct pci_device_id *id_table;
194 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id);
195 void (*remove)(struct pci_dev *dev);
196 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */
197 int (*resume) (struct pci_dev *dev); /* Device woken up */
198 void (*shutdown) (struct pci_dev *dev); /* Device shutdown */
201 struct device_driver driver;
202 const struct pci_error_handlers *err_handler;
207 struct pci_dev *self;
212 extern struct list_head pci_drivers;
213 extern struct list_head pci_devices;
214 extern spinlock_t pci_lock;
216 #define __devexit_p(x) x
220 struct list_head links;
221 struct pci_driver *pdrv;
225 uint16_t subsystem_vendor;
226 uint16_t subsystem_device;
233 static inline struct resource_list_entry *
234 linux_pci_get_rle(struct pci_dev *pdev, int type, int rid)
236 struct pci_devinfo *dinfo;
237 struct resource_list *rl;
239 dinfo = device_get_ivars(pdev->dev.bsddev);
240 rl = &dinfo->resources;
241 return resource_list_find(rl, type, rid);
244 static inline struct resource_list_entry *
245 linux_pci_get_bar(struct pci_dev *pdev, int bar)
247 struct resource_list_entry *rle;
250 if ((rle = linux_pci_get_rle(pdev, SYS_RES_MEMORY, bar)) == NULL)
251 rle = linux_pci_get_rle(pdev, SYS_RES_IOPORT, bar);
255 static inline struct device *
256 linux_pci_find_irq_dev(unsigned int irq)
258 struct pci_dev *pdev;
259 struct device *found;
262 spin_lock(&pci_lock);
263 list_for_each_entry(pdev, &pci_devices, links) {
264 if (irq == pdev->dev.irq ||
265 (irq >= pdev->dev.msix && irq < pdev->dev.msix_max)) {
270 spin_unlock(&pci_lock);
275 pci_resource_type(struct pci_dev *pdev, int bar)
279 pm = pci_find_bar(pdev->dev.bsddev, PCIR_BAR(bar));
283 if (PCI_BAR_IO(pm->pm_value))
284 return (SYS_RES_IOPORT);
286 return (SYS_RES_MEMORY);
290 * All drivers just seem to want to inspect the type not flags.
293 pci_resource_flags(struct pci_dev *pdev, int bar)
297 type = pci_resource_type(pdev, bar);
303 static inline const char *
304 pci_name(struct pci_dev *d)
307 return device_get_desc(d->dev.bsddev);
311 pci_get_drvdata(struct pci_dev *pdev)
314 return dev_get_drvdata(&pdev->dev);
318 pci_set_drvdata(struct pci_dev *pdev, void *data)
321 dev_set_drvdata(&pdev->dev, data);
325 pci_enable_device(struct pci_dev *pdev)
328 pci_enable_io(pdev->dev.bsddev, SYS_RES_IOPORT);
329 pci_enable_io(pdev->dev.bsddev, SYS_RES_MEMORY);
334 pci_disable_device(struct pci_dev *pdev)
337 pci_disable_busmaster(pdev->dev.bsddev);
341 pci_set_master(struct pci_dev *pdev)
344 pci_enable_busmaster(pdev->dev.bsddev);
349 pci_set_power_state(struct pci_dev *pdev, int state)
352 pci_set_powerstate(pdev->dev.bsddev, state);
357 pci_clear_master(struct pci_dev *pdev)
360 pci_disable_busmaster(pdev->dev.bsddev);
365 pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
370 type = pci_resource_type(pdev, bar);
374 if (bus_alloc_resource_any(pdev->dev.bsddev, type, &rid,
381 pci_release_region(struct pci_dev *pdev, int bar)
383 struct resource_list_entry *rle;
385 if ((rle = linux_pci_get_bar(pdev, bar)) == NULL)
387 bus_release_resource(pdev->dev.bsddev, rle->type, rle->rid, rle->res);
391 pci_release_regions(struct pci_dev *pdev)
395 for (i = 0; i <= PCIR_MAX_BAR_0; i++)
396 pci_release_region(pdev, i);
400 pci_request_regions(struct pci_dev *pdev, const char *res_name)
405 for (i = 0; i <= PCIR_MAX_BAR_0; i++) {
406 error = pci_request_region(pdev, i, res_name);
407 if (error && error != -ENODEV) {
408 pci_release_regions(pdev);
416 pci_disable_msix(struct pci_dev *pdev)
419 pci_release_msi(pdev->dev.bsddev);
422 * The MSIX IRQ numbers associated with this PCI device are no
423 * longer valid and might be re-assigned. Make sure
424 * linux_pci_find_irq_dev() does no longer see them by
425 * resetting their references to zero:
428 pdev->dev.msix_max = 0;
431 unsigned long pci_resource_start(struct pci_dev *pdev, int bar);
432 unsigned long pci_resource_len(struct pci_dev *pdev, int bar);
434 static inline bus_addr_t
435 pci_bus_address(struct pci_dev *pdev, int bar)
438 return (pci_resource_start(pdev, bar));
441 #define PCI_CAP_ID_EXP PCIY_EXPRESS
442 #define PCI_CAP_ID_PCIX PCIY_PCIX
443 #define PCI_CAP_ID_AGP PCIY_AGP
444 #define PCI_CAP_ID_PM PCIY_PMG
446 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL
447 #define PCI_EXP_DEVCTL_PAYLOAD PCIEM_CTL_MAX_PAYLOAD
448 #define PCI_EXP_DEVCTL_READRQ PCIEM_CTL_MAX_READ_REQUEST
449 #define PCI_EXP_LNKCTL PCIER_LINK_CTL
450 #define PCI_EXP_LNKSTA PCIER_LINK_STA
453 pci_find_capability(struct pci_dev *pdev, int capid)
457 if (pci_find_cap(pdev->dev.bsddev, capid, ®))
462 static inline int pci_pcie_cap(struct pci_dev *dev)
464 return pci_find_capability(dev, PCI_CAP_ID_EXP);
469 pci_read_config_byte(struct pci_dev *pdev, int where, u8 *val)
472 *val = (u8)pci_read_config(pdev->dev.bsddev, where, 1);
477 pci_read_config_word(struct pci_dev *pdev, int where, u16 *val)
480 *val = (u16)pci_read_config(pdev->dev.bsddev, where, 2);
485 pci_read_config_dword(struct pci_dev *pdev, int where, u32 *val)
488 *val = (u32)pci_read_config(pdev->dev.bsddev, where, 4);
493 pci_write_config_byte(struct pci_dev *pdev, int where, u8 val)
496 pci_write_config(pdev->dev.bsddev, where, val, 1);
501 pci_write_config_word(struct pci_dev *pdev, int where, u16 val)
504 pci_write_config(pdev->dev.bsddev, where, val, 2);
509 pci_write_config_dword(struct pci_dev *pdev, int where, u32 val)
512 pci_write_config(pdev->dev.bsddev, where, val, 4);
516 int linux_pci_register_driver(struct pci_driver *pdrv);
517 int linux_pci_register_drm_driver(struct pci_driver *pdrv);
518 void linux_pci_unregister_driver(struct pci_driver *pdrv);
519 void linux_pci_unregister_drm_driver(struct pci_driver *pdrv);
521 #define pci_register_driver(pdrv) linux_pci_register_driver(pdrv)
522 #define pci_unregister_driver(pdrv) linux_pci_unregister_driver(pdrv)
530 * Enable msix, positive errors indicate actual number of available
531 * vectors. Negative errors are failures.
533 * NB: define added to prevent this definition of pci_enable_msix from
534 * clashing with the native FreeBSD version.
536 #define pci_enable_msix(...) \
537 linux_pci_enable_msix(__VA_ARGS__)
540 pci_enable_msix(struct pci_dev *pdev, struct msix_entry *entries, int nreq)
542 struct resource_list_entry *rle;
547 avail = pci_msix_count(pdev->dev.bsddev);
554 if ((error = -pci_alloc_msix(pdev->dev.bsddev, &avail)) != 0)
557 * Handle case where "pci_alloc_msix()" may allocate less
558 * interrupts than available and return with no error:
561 pci_release_msi(pdev->dev.bsddev);
564 rle = linux_pci_get_rle(pdev, SYS_RES_IRQ, 1);
565 pdev->dev.msix = rle->start;
566 pdev->dev.msix_max = rle->start + avail;
567 for (i = 0; i < nreq; i++)
568 entries[i].vector = pdev->dev.msix + i;
572 #define pci_enable_msix_range(...) \
573 linux_pci_enable_msix_range(__VA_ARGS__)
576 pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
577 int minvec, int maxvec)
586 rc = pci_enable_msix(dev, entries, nvec);
599 pci_channel_offline(struct pci_dev *pdev)
602 return (pci_get_vendor(pdev->dev.bsddev) == PCIV_INVALID);
605 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
609 static inline void pci_disable_sriov(struct pci_dev *dev)
613 #define DEFINE_PCI_DEVICE_TABLE(_table) \
614 const struct pci_device_id _table[] __devinitdata
617 /* XXX This should not be necessary. */
618 #define pcix_set_mmrbc(d, v) 0
619 #define pcix_get_max_mmrbc(d) 0
620 #define pcie_set_readrq(d, v) pci_set_max_read_req(&(d)->dev, (v))
622 #define PCI_DMA_BIDIRECTIONAL 0
623 #define PCI_DMA_TODEVICE 1
624 #define PCI_DMA_FROMDEVICE 2
625 #define PCI_DMA_NONE 3
627 #define pci_pool dma_pool
628 #define pci_pool_destroy(...) dma_pool_destroy(__VA_ARGS__)
629 #define pci_pool_alloc(...) dma_pool_alloc(__VA_ARGS__)
630 #define pci_pool_free(...) dma_pool_free(__VA_ARGS__)
631 #define pci_pool_create(_name, _pdev, _size, _align, _alloc) \
632 dma_pool_create(_name, &(_pdev)->dev, _size, _align, _alloc)
633 #define pci_free_consistent(_hwdev, _size, _vaddr, _dma_handle) \
634 dma_free_coherent((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \
635 _size, _vaddr, _dma_handle)
636 #define pci_map_sg(_hwdev, _sg, _nents, _dir) \
637 dma_map_sg((_hwdev) == NULL ? NULL : &(_hwdev->dev), \
638 _sg, _nents, (enum dma_data_direction)_dir)
639 #define pci_map_single(_hwdev, _ptr, _size, _dir) \
640 dma_map_single((_hwdev) == NULL ? NULL : &(_hwdev->dev), \
641 (_ptr), (_size), (enum dma_data_direction)_dir)
642 #define pci_unmap_single(_hwdev, _addr, _size, _dir) \
643 dma_unmap_single((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \
644 _addr, _size, (enum dma_data_direction)_dir)
645 #define pci_unmap_sg(_hwdev, _sg, _nents, _dir) \
646 dma_unmap_sg((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \
647 _sg, _nents, (enum dma_data_direction)_dir)
648 #define pci_map_page(_hwdev, _page, _offset, _size, _dir) \
649 dma_map_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, _page,\
650 _offset, _size, (enum dma_data_direction)_dir)
651 #define pci_unmap_page(_hwdev, _dma_address, _size, _dir) \
652 dma_unmap_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \
653 _dma_address, _size, (enum dma_data_direction)_dir)
654 #define pci_set_dma_mask(_pdev, mask) dma_set_mask(&(_pdev)->dev, (mask))
655 #define pci_dma_mapping_error(_pdev, _dma_addr) \
656 dma_mapping_error(&(_pdev)->dev, _dma_addr)
657 #define pci_set_consistent_dma_mask(_pdev, _mask) \
658 dma_set_coherent_mask(&(_pdev)->dev, (_mask))
659 #define DECLARE_PCI_UNMAP_ADDR(x) DEFINE_DMA_UNMAP_ADDR(x);
660 #define DECLARE_PCI_UNMAP_LEN(x) DEFINE_DMA_UNMAP_LEN(x);
661 #define pci_unmap_addr dma_unmap_addr
662 #define pci_unmap_addr_set dma_unmap_addr_set
663 #define pci_unmap_len dma_unmap_len
664 #define pci_unmap_len_set dma_unmap_len_set
666 typedef unsigned int __bitwise pci_channel_state_t;
667 typedef unsigned int __bitwise pci_ers_result_t;
669 enum pci_channel_state {
670 pci_channel_io_normal = 1,
671 pci_channel_io_frozen = 2,
672 pci_channel_io_perm_failure = 3,
675 enum pci_ers_result {
676 PCI_ERS_RESULT_NONE = 1,
677 PCI_ERS_RESULT_CAN_RECOVER = 2,
678 PCI_ERS_RESULT_NEED_RESET = 3,
679 PCI_ERS_RESULT_DISCONNECT = 4,
680 PCI_ERS_RESULT_RECOVERED = 5,
684 /* PCI bus error event callbacks */
685 struct pci_error_handlers {
686 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
687 enum pci_channel_state error);
688 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
689 pci_ers_result_t (*link_reset)(struct pci_dev *dev);
690 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
691 void (*resume)(struct pci_dev *dev);
694 /* FreeBSD does not support SRIOV - yet */
695 static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
700 static inline bool pci_is_pcie(struct pci_dev *dev)
702 return !!pci_pcie_cap(dev);
705 static inline u16 pcie_flags_reg(struct pci_dev *dev)
710 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
714 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, ®16);
720 static inline int pci_pcie_type(struct pci_dev *dev)
722 return (pcie_flags_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
725 static inline int pcie_cap_version(struct pci_dev *dev)
727 return pcie_flags_reg(dev) & PCI_EXP_FLAGS_VERS;
730 static inline bool pcie_cap_has_lnkctl(struct pci_dev *dev)
732 int type = pci_pcie_type(dev);
734 return pcie_cap_version(dev) > 1 ||
735 type == PCI_EXP_TYPE_ROOT_PORT ||
736 type == PCI_EXP_TYPE_ENDPOINT ||
737 type == PCI_EXP_TYPE_LEG_END;
740 static inline bool pcie_cap_has_devctl(const struct pci_dev *dev)
745 static inline bool pcie_cap_has_sltctl(struct pci_dev *dev)
747 int type = pci_pcie_type(dev);
749 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT ||
750 (type == PCI_EXP_TYPE_DOWNSTREAM &&
751 pcie_flags_reg(dev) & PCI_EXP_FLAGS_SLOT);
754 static inline bool pcie_cap_has_rtctl(struct pci_dev *dev)
756 int type = pci_pcie_type(dev);
758 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT ||
759 type == PCI_EXP_TYPE_RC_EC;
762 static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos)
764 if (!pci_is_pcie(dev))
768 case PCI_EXP_FLAGS_TYPE:
773 return pcie_cap_has_devctl(dev);
777 return pcie_cap_has_lnkctl(dev);
781 return pcie_cap_has_sltctl(dev);
785 return pcie_cap_has_rtctl(dev);
786 case PCI_EXP_DEVCAP2:
787 case PCI_EXP_DEVCTL2:
788 case PCI_EXP_LNKCAP2:
789 case PCI_EXP_LNKCTL2:
790 case PCI_EXP_LNKSTA2:
791 return pcie_cap_version(dev) > 1;
798 pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *dst)
803 if (!pcie_capability_reg_implemented(dev, pos))
806 return pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, dst);
810 pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *dst)
815 if (!pcie_capability_reg_implemented(dev, pos))
818 return pci_read_config_word(dev, pci_pcie_cap(dev) + pos, dst);
822 pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val)
827 if (!pcie_capability_reg_implemented(dev, pos))
830 return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val);
833 static inline int pcie_get_minimum_link(struct pci_dev *dev,
834 enum pci_bus_speed *speed, enum pcie_link_width *width)
836 *speed = PCI_SPEED_UNKNOWN;
837 *width = PCIE_LNK_WIDTH_UNKNOWN;
842 pci_num_vf(struct pci_dev *dev)
847 static inline enum pci_bus_speed
848 pcie_get_speed_cap(struct pci_dev *dev)
851 uint32_t lnkcap, lnkcap2;
854 root = device_get_parent(dev->dev.bsddev);
856 return (PCI_SPEED_UNKNOWN);
857 root = device_get_parent(root);
859 return (PCI_SPEED_UNKNOWN);
860 root = device_get_parent(root);
862 return (PCI_SPEED_UNKNOWN);
864 if (pci_get_vendor(root) == PCI_VENDOR_ID_VIA ||
865 pci_get_vendor(root) == PCI_VENDOR_ID_SERVERWORKS)
866 return (PCI_SPEED_UNKNOWN);
868 if ((error = pci_find_cap(root, PCIY_EXPRESS, &pos)) != 0)
869 return (PCI_SPEED_UNKNOWN);
871 lnkcap2 = pci_read_config(root, pos + PCIER_LINK_CAP2, 4);
873 if (lnkcap2) { /* PCIe r3.0-compliant */
874 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB)
875 return (PCIE_SPEED_2_5GT);
876 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB)
877 return (PCIE_SPEED_5_0GT);
878 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB)
879 return (PCIE_SPEED_8_0GT);
880 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_16_0GB)
881 return (PCIE_SPEED_16_0GT);
882 } else { /* pre-r3.0 */
883 lnkcap = pci_read_config(root, pos + PCIER_LINK_CAP, 4);
884 if (lnkcap & PCI_EXP_LNKCAP_SLS_2_5GB)
885 return (PCIE_SPEED_2_5GT);
886 if (lnkcap & PCI_EXP_LNKCAP_SLS_5_0GB)
887 return (PCIE_SPEED_5_0GT);
888 if (lnkcap & PCI_EXP_LNKCAP_SLS_8_0GB)
889 return (PCIE_SPEED_8_0GT);
890 if (lnkcap & PCI_EXP_LNKCAP_SLS_16_0GB)
891 return (PCIE_SPEED_16_0GT);
893 return (PCI_SPEED_UNKNOWN);
896 static inline enum pcie_link_width
897 pcie_get_width_cap(struct pci_dev *dev)
901 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap);
903 return ((lnkcap & PCI_EXP_LNKCAP_MLW) >> 4);
905 return (PCIE_LNK_WIDTH_UNKNOWN);
908 #endif /* _LINUX_PCI_H_ */