2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2012, 2016 Chelsio Communications, Inc.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
34 #include <sys/param.h>
35 #include <sys/eventhandler.h>
39 #include "t4_regs_values.h"
40 #include "firmware/t4fw_interface.h"
43 #define msleep(x) do { \
47 pause("t4hw", (x) * hz / 1000); \
51 * t4_wait_op_done_val - wait until an operation is completed
52 * @adapter: the adapter performing the operation
53 * @reg: the register to check for completion
54 * @mask: a single-bit field within @reg that indicates completion
55 * @polarity: the value of the field when the operation is completed
56 * @attempts: number of check iterations
57 * @delay: delay in usecs between iterations
58 * @valp: where to store the value of the register at completion time
60 * Wait until an operation is completed by checking a bit in a register
61 * up to @attempts times. If @valp is not NULL the value of the register
62 * at the time it indicated completion is stored there. Returns 0 if the
63 * operation completes and -EAGAIN otherwise.
65 static int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,
66 int polarity, int attempts, int delay, u32 *valp)
69 u32 val = t4_read_reg(adapter, reg);
71 if (!!(val & mask) == polarity) {
83 static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask,
84 int polarity, int attempts, int delay)
86 return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts,
91 * t4_set_reg_field - set a register field to a value
92 * @adapter: the adapter to program
93 * @addr: the register address
94 * @mask: specifies the portion of the register to modify
95 * @val: the new value for the register field
97 * Sets a register field specified by the supplied mask to the
100 void t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask,
103 u32 v = t4_read_reg(adapter, addr) & ~mask;
105 t4_write_reg(adapter, addr, v | val);
106 (void) t4_read_reg(adapter, addr); /* flush */
110 * t4_read_indirect - read indirectly addressed registers
112 * @addr_reg: register holding the indirect address
113 * @data_reg: register holding the value of the indirect register
114 * @vals: where the read register values are stored
115 * @nregs: how many indirect registers to read
116 * @start_idx: index of first indirect register to read
118 * Reads registers that are accessed indirectly through an address/data
121 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
122 unsigned int data_reg, u32 *vals,
123 unsigned int nregs, unsigned int start_idx)
126 t4_write_reg(adap, addr_reg, start_idx);
127 *vals++ = t4_read_reg(adap, data_reg);
133 * t4_write_indirect - write indirectly addressed registers
135 * @addr_reg: register holding the indirect addresses
136 * @data_reg: register holding the value for the indirect registers
137 * @vals: values to write
138 * @nregs: how many indirect registers to write
139 * @start_idx: address of first indirect register to write
141 * Writes a sequential block of registers that are accessed indirectly
142 * through an address/data register pair.
144 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
145 unsigned int data_reg, const u32 *vals,
146 unsigned int nregs, unsigned int start_idx)
149 t4_write_reg(adap, addr_reg, start_idx++);
150 t4_write_reg(adap, data_reg, *vals++);
155 * Read a 32-bit PCI Configuration Space register via the PCI-E backdoor
156 * mechanism. This guarantees that we get the real value even if we're
157 * operating within a Virtual Machine and the Hypervisor is trapping our
158 * Configuration Space accesses.
160 * N.B. This routine should only be used as a last resort: the firmware uses
161 * the backdoor registers on a regular basis and we can end up
162 * conflicting with it's uses!
164 u32 t4_hw_pci_read_cfg4(adapter_t *adap, int reg)
166 u32 req = V_FUNCTION(adap->pf) | V_REGISTER(reg);
169 if (chip_id(adap) <= CHELSIO_T5)
177 t4_write_reg(adap, A_PCIE_CFG_SPACE_REQ, req);
178 val = t4_read_reg(adap, A_PCIE_CFG_SPACE_DATA);
181 * Reset F_ENABLE to 0 so reads of PCIE_CFG_SPACE_DATA won't cause a
182 * Configuration Space read. (None of the other fields matter when
183 * F_ENABLE is 0 so a simple register write is easier than a
184 * read-modify-write via t4_set_reg_field().)
186 t4_write_reg(adap, A_PCIE_CFG_SPACE_REQ, 0);
192 * t4_report_fw_error - report firmware error
195 * The adapter firmware can indicate error conditions to the host.
196 * If the firmware has indicated an error, print out the reason for
197 * the firmware error.
199 static void t4_report_fw_error(struct adapter *adap)
201 static const char *const reason[] = {
202 "Crash", /* PCIE_FW_EVAL_CRASH */
203 "During Device Preparation", /* PCIE_FW_EVAL_PREP */
204 "During Device Configuration", /* PCIE_FW_EVAL_CONF */
205 "During Device Initialization", /* PCIE_FW_EVAL_INIT */
206 "Unexpected Event", /* PCIE_FW_EVAL_UNEXPECTEDEVENT */
207 "Insufficient Airflow", /* PCIE_FW_EVAL_OVERHEAT */
208 "Device Shutdown", /* PCIE_FW_EVAL_DEVICESHUTDOWN */
209 "Reserved", /* reserved */
213 pcie_fw = t4_read_reg(adap, A_PCIE_FW);
214 if (pcie_fw & F_PCIE_FW_ERR) {
215 adap->flags &= ~FW_OK;
216 CH_ERR(adap, "firmware reports adapter error: %s (0x%08x)\n",
217 reason[G_PCIE_FW_EVAL(pcie_fw)], pcie_fw);
218 if (pcie_fw != 0xffffffff)
219 t4_os_dump_devlog(adap);
224 * Get the reply to a mailbox command and store it in @rpl in big-endian order.
226 static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit,
229 for ( ; nflit; nflit--, mbox_addr += 8)
230 *rpl++ = cpu_to_be64(t4_read_reg64(adap, mbox_addr));
234 * Handle a FW assertion reported in a mailbox.
236 static void fw_asrt(struct adapter *adap, struct fw_debug_cmd *asrt)
239 "FW assertion at %.16s:%u, val0 %#x, val1 %#x\n",
240 asrt->u.assert.filename_0_7,
241 be32_to_cpu(asrt->u.assert.line),
242 be32_to_cpu(asrt->u.assert.x),
243 be32_to_cpu(asrt->u.assert.y));
246 struct port_tx_state {
252 read_tx_state_one(struct adapter *sc, int i, struct port_tx_state *tx_state)
254 uint32_t rx_pause_reg, tx_frames_reg;
257 tx_frames_reg = PORT_REG(i, A_MPS_PORT_STAT_TX_PORT_FRAMES_L);
258 rx_pause_reg = PORT_REG(i, A_MPS_PORT_STAT_RX_PORT_PAUSE_L);
260 tx_frames_reg = T5_PORT_REG(i, A_MPS_PORT_STAT_TX_PORT_FRAMES_L);
261 rx_pause_reg = T5_PORT_REG(i, A_MPS_PORT_STAT_RX_PORT_PAUSE_L);
264 tx_state->rx_pause = t4_read_reg64(sc, rx_pause_reg);
265 tx_state->tx_frames = t4_read_reg64(sc, tx_frames_reg);
269 read_tx_state(struct adapter *sc, struct port_tx_state *tx_state)
274 read_tx_state_one(sc, i, &tx_state[i]);
278 check_tx_state(struct adapter *sc, struct port_tx_state *tx_state)
280 uint32_t port_ctl_reg;
281 uint64_t tx_frames, rx_pause;
284 for_each_port(sc, i) {
285 rx_pause = tx_state[i].rx_pause;
286 tx_frames = tx_state[i].tx_frames;
287 read_tx_state_one(sc, i, &tx_state[i]); /* update */
290 port_ctl_reg = PORT_REG(i, A_MPS_PORT_CTL);
292 port_ctl_reg = T5_PORT_REG(i, A_MPS_PORT_CTL);
293 if (t4_read_reg(sc, port_ctl_reg) & F_PORTTXEN &&
294 rx_pause != tx_state[i].rx_pause &&
295 tx_frames == tx_state[i].tx_frames) {
296 t4_set_reg_field(sc, port_ctl_reg, F_PORTTXEN, 0);
298 t4_set_reg_field(sc, port_ctl_reg, F_PORTTXEN, F_PORTTXEN);
303 #define X_CIM_PF_NOACCESS 0xeeeeeeee
305 * t4_wr_mbox_meat_timeout - send a command to FW through the given mailbox
307 * @mbox: index of the mailbox to use
308 * @cmd: the command to write
309 * @size: command length in bytes
310 * @rpl: where to optionally store the reply
311 * @sleep_ok: if true we may sleep while awaiting command completion
312 * @timeout: time to wait for command to finish before timing out
313 * (negative implies @sleep_ok=false)
315 * Sends the given command to FW through the selected mailbox and waits
316 * for the FW to execute the command. If @rpl is not %NULL it is used to
317 * store the FW's reply to the command. The command and its optional
318 * reply are of the same length. Some FW commands like RESET and
319 * INITIALIZE can take a considerable amount of time to execute.
320 * @sleep_ok determines whether we may sleep while awaiting the response.
321 * If sleeping is allowed we use progressive backoff otherwise we spin.
322 * Note that passing in a negative @timeout is an alternate mechanism
323 * for specifying @sleep_ok=false. This is useful when a higher level
324 * interface allows for specification of @timeout but not @sleep_ok ...
326 * The return value is 0 on success or a negative errno on failure. A
327 * failure can happen either because we are not able to execute the
328 * command or FW executes it but signals an error. In the latter case
329 * the return value is the error code indicated by FW (negated).
331 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd,
332 int size, void *rpl, bool sleep_ok, int timeout)
335 * We delay in small increments at first in an effort to maintain
336 * responsiveness for simple, fast executing commands but then back
337 * off to larger delays to a maximum retry delay.
339 static const int delay[] = {
340 1, 1, 3, 5, 10, 10, 20, 50, 100
344 int i, ms, delay_idx, ret, next_tx_check;
345 u32 data_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_DATA);
346 u32 ctl_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_CTRL);
348 __be64 cmd_rpl[MBOX_LEN/8];
350 struct port_tx_state tx_state[MAX_NPORTS];
352 if (adap->flags & CHK_MBOX_ACCESS)
353 ASSERT_SYNCHRONIZED_OP(adap);
355 if (size <= 0 || (size & 15) || size > MBOX_LEN)
358 if (adap->flags & IS_VF) {
360 data_reg = FW_T6VF_MBDATA_BASE_ADDR;
362 data_reg = FW_T4VF_MBDATA_BASE_ADDR;
363 ctl_reg = VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL);
367 * If we have a negative timeout, that implies that we can't sleep.
375 * Attempt to gain access to the mailbox.
377 for (i = 0; i < 4; i++) {
378 ctl = t4_read_reg(adap, ctl_reg);
380 if (v != X_MBOWNER_NONE)
385 * If we were unable to gain access, report the error to our caller.
387 if (v != X_MBOWNER_PL) {
388 t4_report_fw_error(adap);
389 ret = (v == X_MBOWNER_FW) ? -EBUSY : -ETIMEDOUT;
394 * If we gain ownership of the mailbox and there's a "valid" message
395 * in it, this is likely an asynchronous error message from the
396 * firmware. So we'll report that and then proceed on with attempting
397 * to issue our own command ... which may well fail if the error
398 * presaged the firmware crashing ...
400 if (ctl & F_MBMSGVALID) {
401 CH_DUMP_MBOX(adap, mbox, data_reg, "VLD", NULL, true);
405 * Copy in the new mailbox command and send it on its way ...
407 memset(cmd_rpl, 0, sizeof(cmd_rpl));
408 memcpy(cmd_rpl, cmd, size);
409 CH_DUMP_MBOX(adap, mbox, 0, "cmd", cmd_rpl, false);
410 for (i = 0; i < ARRAY_SIZE(cmd_rpl); i++)
411 t4_write_reg64(adap, data_reg + i * 8, be64_to_cpu(cmd_rpl[i]));
413 if (adap->flags & IS_VF) {
415 * For the VFs, the Mailbox Data "registers" are
416 * actually backed by T4's "MA" interface rather than
417 * PL Registers (as is the case for the PFs). Because
418 * these are in different coherency domains, the write
419 * to the VF's PL-register-backed Mailbox Control can
420 * race in front of the writes to the MA-backed VF
421 * Mailbox Data "registers". So we need to do a
422 * read-back on at least one byte of the VF Mailbox
423 * Data registers before doing the write to the VF
424 * Mailbox Control register.
426 t4_read_reg(adap, data_reg);
429 t4_write_reg(adap, ctl_reg, F_MBMSGVALID | V_MBOWNER(X_MBOWNER_FW));
430 read_tx_state(adap, &tx_state[0]); /* also flushes the write_reg */
431 next_tx_check = 1000;
436 * Loop waiting for the reply; bail out if we time out or the firmware
440 for (i = 0; i < timeout; i += ms) {
441 if (!(adap->flags & IS_VF)) {
442 pcie_fw = t4_read_reg(adap, A_PCIE_FW);
443 if (pcie_fw & F_PCIE_FW_ERR)
447 if (i >= next_tx_check) {
448 check_tx_state(adap, &tx_state[0]);
449 next_tx_check = i + 1000;
453 ms = delay[delay_idx]; /* last element may repeat */
454 if (delay_idx < ARRAY_SIZE(delay) - 1)
461 v = t4_read_reg(adap, ctl_reg);
462 if (v == X_CIM_PF_NOACCESS)
464 if (G_MBOWNER(v) == X_MBOWNER_PL) {
465 if (!(v & F_MBMSGVALID)) {
466 t4_write_reg(adap, ctl_reg,
467 V_MBOWNER(X_MBOWNER_NONE));
472 * Retrieve the command reply and release the mailbox.
474 get_mbox_rpl(adap, cmd_rpl, MBOX_LEN/8, data_reg);
475 CH_DUMP_MBOX(adap, mbox, 0, "rpl", cmd_rpl, false);
476 t4_write_reg(adap, ctl_reg, V_MBOWNER(X_MBOWNER_NONE));
478 res = be64_to_cpu(cmd_rpl[0]);
479 if (G_FW_CMD_OP(res >> 32) == FW_DEBUG_CMD) {
480 fw_asrt(adap, (struct fw_debug_cmd *)cmd_rpl);
481 res = V_FW_CMD_RETVAL(EIO);
483 memcpy(rpl, cmd_rpl, size);
484 return -G_FW_CMD_RETVAL((int)res);
489 * We timed out waiting for a reply to our mailbox command. Report
490 * the error and also check to see if the firmware reported any
493 CH_ERR(adap, "command %#x in mbox %d timed out (0x%08x).\n",
494 *(const u8 *)cmd, mbox, pcie_fw);
495 CH_DUMP_MBOX(adap, mbox, 0, "cmdsent", cmd_rpl, true);
496 CH_DUMP_MBOX(adap, mbox, data_reg, "current", NULL, true);
498 if (pcie_fw & F_PCIE_FW_ERR) {
500 t4_report_fw_error(adap);
503 t4_os_dump_devlog(adap);
506 t4_fatal_err(adap, true);
510 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
511 void *rpl, bool sleep_ok)
513 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl,
514 sleep_ok, FW_CMD_MAX_TIMEOUT);
518 static int t4_edc_err_read(struct adapter *adap, int idx)
520 u32 edc_ecc_err_addr_reg;
521 u32 edc_bist_status_rdata_reg;
524 CH_WARN(adap, "%s: T4 NOT supported.\n", __func__);
527 if (idx != MEM_EDC0 && idx != MEM_EDC1) {
528 CH_WARN(adap, "%s: idx %d NOT supported.\n", __func__, idx);
532 edc_ecc_err_addr_reg = EDC_T5_REG(A_EDC_H_ECC_ERR_ADDR, idx);
533 edc_bist_status_rdata_reg = EDC_T5_REG(A_EDC_H_BIST_STATUS_RDATA, idx);
536 "edc%d err addr 0x%x: 0x%x.\n",
537 idx, edc_ecc_err_addr_reg,
538 t4_read_reg(adap, edc_ecc_err_addr_reg));
540 "bist: 0x%x, status %llx %llx %llx %llx %llx %llx %llx %llx %llx.\n",
541 edc_bist_status_rdata_reg,
542 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg),
543 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 8),
544 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 16),
545 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 24),
546 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 32),
547 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 40),
548 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 48),
549 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 56),
550 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 64));
556 * t4_mc_read - read from MC through backdoor accesses
558 * @idx: which MC to access
559 * @addr: address of first byte requested
560 * @data: 64 bytes of data containing the requested address
561 * @ecc: where to store the corresponding 64-bit ECC word
563 * Read 64 bytes of data from MC starting at a 64-byte-aligned address
564 * that covers the requested address @addr. If @parity is not %NULL it
565 * is assigned the 64-bit ECC word for the read data.
567 int t4_mc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *ecc)
570 u32 mc_bist_cmd_reg, mc_bist_cmd_addr_reg, mc_bist_cmd_len_reg;
571 u32 mc_bist_status_rdata_reg, mc_bist_data_pattern_reg;
574 mc_bist_cmd_reg = A_MC_BIST_CMD;
575 mc_bist_cmd_addr_reg = A_MC_BIST_CMD_ADDR;
576 mc_bist_cmd_len_reg = A_MC_BIST_CMD_LEN;
577 mc_bist_status_rdata_reg = A_MC_BIST_STATUS_RDATA;
578 mc_bist_data_pattern_reg = A_MC_BIST_DATA_PATTERN;
580 mc_bist_cmd_reg = MC_REG(A_MC_P_BIST_CMD, idx);
581 mc_bist_cmd_addr_reg = MC_REG(A_MC_P_BIST_CMD_ADDR, idx);
582 mc_bist_cmd_len_reg = MC_REG(A_MC_P_BIST_CMD_LEN, idx);
583 mc_bist_status_rdata_reg = MC_REG(A_MC_P_BIST_STATUS_RDATA,
585 mc_bist_data_pattern_reg = MC_REG(A_MC_P_BIST_DATA_PATTERN,
589 if (t4_read_reg(adap, mc_bist_cmd_reg) & F_START_BIST)
591 t4_write_reg(adap, mc_bist_cmd_addr_reg, addr & ~0x3fU);
592 t4_write_reg(adap, mc_bist_cmd_len_reg, 64);
593 t4_write_reg(adap, mc_bist_data_pattern_reg, 0xc);
594 t4_write_reg(adap, mc_bist_cmd_reg, V_BIST_OPCODE(1) |
595 F_START_BIST | V_BIST_CMD_GAP(1));
596 i = t4_wait_op_done(adap, mc_bist_cmd_reg, F_START_BIST, 0, 10, 1);
600 #define MC_DATA(i) MC_BIST_STATUS_REG(mc_bist_status_rdata_reg, i)
602 for (i = 15; i >= 0; i--)
603 *data++ = ntohl(t4_read_reg(adap, MC_DATA(i)));
605 *ecc = t4_read_reg64(adap, MC_DATA(16));
611 * t4_edc_read - read from EDC through backdoor accesses
613 * @idx: which EDC to access
614 * @addr: address of first byte requested
615 * @data: 64 bytes of data containing the requested address
616 * @ecc: where to store the corresponding 64-bit ECC word
618 * Read 64 bytes of data from EDC starting at a 64-byte-aligned address
619 * that covers the requested address @addr. If @parity is not %NULL it
620 * is assigned the 64-bit ECC word for the read data.
622 int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *ecc)
625 u32 edc_bist_cmd_reg, edc_bist_cmd_addr_reg, edc_bist_cmd_len_reg;
626 u32 edc_bist_cmd_data_pattern, edc_bist_status_rdata_reg;
629 edc_bist_cmd_reg = EDC_REG(A_EDC_BIST_CMD, idx);
630 edc_bist_cmd_addr_reg = EDC_REG(A_EDC_BIST_CMD_ADDR, idx);
631 edc_bist_cmd_len_reg = EDC_REG(A_EDC_BIST_CMD_LEN, idx);
632 edc_bist_cmd_data_pattern = EDC_REG(A_EDC_BIST_DATA_PATTERN,
634 edc_bist_status_rdata_reg = EDC_REG(A_EDC_BIST_STATUS_RDATA,
638 * These macro are missing in t4_regs.h file.
639 * Added temporarily for testing.
641 #define EDC_STRIDE_T5 (EDC_T51_BASE_ADDR - EDC_T50_BASE_ADDR)
642 #define EDC_REG_T5(reg, idx) (reg + EDC_STRIDE_T5 * idx)
643 edc_bist_cmd_reg = EDC_REG_T5(A_EDC_H_BIST_CMD, idx);
644 edc_bist_cmd_addr_reg = EDC_REG_T5(A_EDC_H_BIST_CMD_ADDR, idx);
645 edc_bist_cmd_len_reg = EDC_REG_T5(A_EDC_H_BIST_CMD_LEN, idx);
646 edc_bist_cmd_data_pattern = EDC_REG_T5(A_EDC_H_BIST_DATA_PATTERN,
648 edc_bist_status_rdata_reg = EDC_REG_T5(A_EDC_H_BIST_STATUS_RDATA,
654 if (t4_read_reg(adap, edc_bist_cmd_reg) & F_START_BIST)
656 t4_write_reg(adap, edc_bist_cmd_addr_reg, addr & ~0x3fU);
657 t4_write_reg(adap, edc_bist_cmd_len_reg, 64);
658 t4_write_reg(adap, edc_bist_cmd_data_pattern, 0xc);
659 t4_write_reg(adap, edc_bist_cmd_reg,
660 V_BIST_OPCODE(1) | V_BIST_CMD_GAP(1) | F_START_BIST);
661 i = t4_wait_op_done(adap, edc_bist_cmd_reg, F_START_BIST, 0, 10, 1);
665 #define EDC_DATA(i) EDC_BIST_STATUS_REG(edc_bist_status_rdata_reg, i)
667 for (i = 15; i >= 0; i--)
668 *data++ = ntohl(t4_read_reg(adap, EDC_DATA(i)));
670 *ecc = t4_read_reg64(adap, EDC_DATA(16));
676 * t4_mem_read - read EDC 0, EDC 1 or MC into buffer
678 * @mtype: memory type: MEM_EDC0, MEM_EDC1 or MEM_MC
679 * @addr: address within indicated memory type
680 * @len: amount of memory to read
681 * @buf: host memory buffer
683 * Reads an [almost] arbitrary memory region in the firmware: the
684 * firmware memory address, length and host buffer must be aligned on
685 * 32-bit boudaries. The memory is returned as a raw byte sequence from
686 * the firmware's memory. If this memory contains data structures which
687 * contain multi-byte integers, it's the callers responsibility to
688 * perform appropriate byte order conversions.
690 int t4_mem_read(struct adapter *adap, int mtype, u32 addr, u32 len,
693 u32 pos, start, end, offset;
697 * Argument sanity checks ...
699 if ((addr & 0x3) || (len & 0x3))
703 * The underlaying EDC/MC read routines read 64 bytes at a time so we
704 * need to round down the start and round up the end. We'll start
705 * copying out of the first line at (addr - start) a word at a time.
707 start = rounddown2(addr, 64);
708 end = roundup2(addr + len, 64);
709 offset = (addr - start)/sizeof(__be32);
711 for (pos = start; pos < end; pos += 64, offset = 0) {
715 * Read the chip's memory block and bail if there's an error.
717 if ((mtype == MEM_MC) || (mtype == MEM_MC1))
718 ret = t4_mc_read(adap, mtype - MEM_MC, pos, data, NULL);
720 ret = t4_edc_read(adap, mtype, pos, data, NULL);
725 * Copy the data into the caller's memory buffer.
727 while (offset < 16 && len > 0) {
728 *buf++ = data[offset++];
729 len -= sizeof(__be32);
737 * Return the specified PCI-E Configuration Space register from our Physical
738 * Function. We try first via a Firmware LDST Command (if fw_attach != 0)
739 * since we prefer to let the firmware own all of these registers, but if that
740 * fails we go for it directly ourselves.
742 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg, int drv_fw_attach)
746 * If fw_attach != 0, construct and send the Firmware LDST Command to
747 * retrieve the specified PCI-E Configuration Space register.
749 if (drv_fw_attach != 0) {
750 struct fw_ldst_cmd ldst_cmd;
753 memset(&ldst_cmd, 0, sizeof(ldst_cmd));
754 ldst_cmd.op_to_addrspace =
755 cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
758 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_FUNC_PCIE));
759 ldst_cmd.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst_cmd));
760 ldst_cmd.u.pcie.select_naccess = V_FW_LDST_CMD_NACCESS(1);
761 ldst_cmd.u.pcie.ctrl_to_fn =
762 (F_FW_LDST_CMD_LC | V_FW_LDST_CMD_FN(adap->pf));
763 ldst_cmd.u.pcie.r = reg;
766 * If the LDST Command succeeds, return the result, otherwise
767 * fall through to reading it directly ourselves ...
769 ret = t4_wr_mbox(adap, adap->mbox, &ldst_cmd, sizeof(ldst_cmd),
772 return be32_to_cpu(ldst_cmd.u.pcie.data[0]);
774 CH_WARN(adap, "Firmware failed to return "
775 "Configuration Space register %d, err = %d\n",
780 * Read the desired Configuration Space register via the PCI-E
781 * Backdoor mechanism.
783 return t4_hw_pci_read_cfg4(adap, reg);
787 * t4_get_regs_len - return the size of the chips register set
788 * @adapter: the adapter
790 * Returns the size of the chip's BAR0 register space.
792 unsigned int t4_get_regs_len(struct adapter *adapter)
794 unsigned int chip_version = chip_id(adapter);
796 switch (chip_version) {
798 if (adapter->flags & IS_VF)
799 return FW_T4VF_REGMAP_SIZE;
800 return T4_REGMAP_SIZE;
804 if (adapter->flags & IS_VF)
805 return FW_T4VF_REGMAP_SIZE;
806 return T5_REGMAP_SIZE;
810 "Unsupported chip version %d\n", chip_version);
815 * t4_get_regs - read chip registers into provided buffer
817 * @buf: register buffer
818 * @buf_size: size (in bytes) of register buffer
820 * If the provided register buffer isn't large enough for the chip's
821 * full register range, the register dump will be truncated to the
822 * register buffer's size.
824 void t4_get_regs(struct adapter *adap, u8 *buf, size_t buf_size)
826 static const unsigned int t4_reg_ranges[] = {
1285 static const unsigned int t4vf_reg_ranges[] = {
1286 VF_SGE_REG(A_SGE_VF_KDOORBELL), VF_SGE_REG(A_SGE_VF_GTS),
1287 VF_MPS_REG(A_MPS_VF_CTL),
1288 VF_MPS_REG(A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H),
1289 VF_PL_REG(A_PL_VF_WHOAMI), VF_PL_REG(A_PL_VF_WHOAMI),
1290 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL),
1291 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_STATUS),
1292 FW_T4VF_MBDATA_BASE_ADDR,
1293 FW_T4VF_MBDATA_BASE_ADDR +
1294 ((NUM_CIM_PF_MAILBOX_DATA_INSTANCES - 1) * 4),
1297 static const unsigned int t5_reg_ranges[] = {
2061 static const unsigned int t5vf_reg_ranges[] = {
2062 VF_SGE_REG(A_SGE_VF_KDOORBELL), VF_SGE_REG(A_SGE_VF_GTS),
2063 VF_MPS_REG(A_MPS_VF_CTL),
2064 VF_MPS_REG(A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H),
2065 VF_PL_REG(A_PL_VF_WHOAMI), VF_PL_REG(A_PL_VF_REVISION),
2066 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL),
2067 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_STATUS),
2068 FW_T4VF_MBDATA_BASE_ADDR,
2069 FW_T4VF_MBDATA_BASE_ADDR +
2070 ((NUM_CIM_PF_MAILBOX_DATA_INSTANCES - 1) * 4),
2073 static const unsigned int t6_reg_ranges[] = {
2630 static const unsigned int t6vf_reg_ranges[] = {
2631 VF_SGE_REG(A_SGE_VF_KDOORBELL), VF_SGE_REG(A_SGE_VF_GTS),
2632 VF_MPS_REG(A_MPS_VF_CTL),
2633 VF_MPS_REG(A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H),
2634 VF_PL_REG(A_PL_VF_WHOAMI), VF_PL_REG(A_PL_VF_REVISION),
2635 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL),
2636 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_STATUS),
2637 FW_T6VF_MBDATA_BASE_ADDR,
2638 FW_T6VF_MBDATA_BASE_ADDR +
2639 ((NUM_CIM_PF_MAILBOX_DATA_INSTANCES - 1) * 4),
2642 u32 *buf_end = (u32 *)(buf + buf_size);
2643 const unsigned int *reg_ranges;
2644 int reg_ranges_size, range;
2645 unsigned int chip_version = chip_id(adap);
2648 * Select the right set of register ranges to dump depending on the
2649 * adapter chip type.
2651 switch (chip_version) {
2653 if (adap->flags & IS_VF) {
2654 reg_ranges = t4vf_reg_ranges;
2655 reg_ranges_size = ARRAY_SIZE(t4vf_reg_ranges);
2657 reg_ranges = t4_reg_ranges;
2658 reg_ranges_size = ARRAY_SIZE(t4_reg_ranges);
2663 if (adap->flags & IS_VF) {
2664 reg_ranges = t5vf_reg_ranges;
2665 reg_ranges_size = ARRAY_SIZE(t5vf_reg_ranges);
2667 reg_ranges = t5_reg_ranges;
2668 reg_ranges_size = ARRAY_SIZE(t5_reg_ranges);
2673 if (adap->flags & IS_VF) {
2674 reg_ranges = t6vf_reg_ranges;
2675 reg_ranges_size = ARRAY_SIZE(t6vf_reg_ranges);
2677 reg_ranges = t6_reg_ranges;
2678 reg_ranges_size = ARRAY_SIZE(t6_reg_ranges);
2684 "Unsupported chip version %d\n", chip_version);
2689 * Clear the register buffer and insert the appropriate register
2690 * values selected by the above register ranges.
2692 memset(buf, 0, buf_size);
2693 for (range = 0; range < reg_ranges_size; range += 2) {
2694 unsigned int reg = reg_ranges[range];
2695 unsigned int last_reg = reg_ranges[range + 1];
2696 u32 *bufp = (u32 *)(buf + reg);
2699 * Iterate across the register range filling in the register
2700 * buffer but don't write past the end of the register buffer.
2702 while (reg <= last_reg && bufp < buf_end) {
2703 *bufp++ = t4_read_reg(adap, reg);
2710 * Partial EEPROM Vital Product Data structure. The VPD starts with one ID
2711 * header followed by one or more VPD-R sections, each with its own header.
2719 struct t4_vpdr_hdr {
2725 * EEPROM reads take a few tens of us while writes can take a bit over 5 ms.
2727 #define EEPROM_DELAY 10 /* 10us per poll spin */
2728 #define EEPROM_MAX_POLL 5000 /* x 5000 == 50ms */
2730 #define EEPROM_STAT_ADDR 0x7bfc
2731 #define VPD_SIZE 0x800
2732 #define VPD_BASE 0x400
2733 #define VPD_BASE_OLD 0
2734 #define VPD_LEN 1024
2735 #define VPD_INFO_FLD_HDR_SIZE 3
2736 #define CHELSIO_VPD_UNIQUE_ID 0x82
2739 * Small utility function to wait till any outstanding VPD Access is complete.
2740 * We have a per-adapter state variable "VPD Busy" to indicate when we have a
2741 * VPD Access in flight. This allows us to handle the problem of having a
2742 * previous VPD Access time out and prevent an attempt to inject a new VPD
2743 * Request before any in-flight VPD reguest has completed.
2745 static int t4_seeprom_wait(struct adapter *adapter)
2747 unsigned int base = adapter->params.pci.vpd_cap_addr;
2751 * If no VPD Access is in flight, we can just return success right
2754 if (!adapter->vpd_busy)
2758 * Poll the VPD Capability Address/Flag register waiting for it
2759 * to indicate that the operation is complete.
2761 max_poll = EEPROM_MAX_POLL;
2765 udelay(EEPROM_DELAY);
2766 t4_os_pci_read_cfg2(adapter, base + PCI_VPD_ADDR, &val);
2769 * If the operation is complete, mark the VPD as no longer
2770 * busy and return success.
2772 if ((val & PCI_VPD_ADDR_F) == adapter->vpd_flag) {
2773 adapter->vpd_busy = 0;
2776 } while (--max_poll);
2779 * Failure! Note that we leave the VPD Busy status set in order to
2780 * avoid pushing a new VPD Access request into the VPD Capability till
2781 * the current operation eventually succeeds. It's a bug to issue a
2782 * new request when an existing request is in flight and will result
2783 * in corrupt hardware state.
2789 * t4_seeprom_read - read a serial EEPROM location
2790 * @adapter: adapter to read
2791 * @addr: EEPROM virtual address
2792 * @data: where to store the read data
2794 * Read a 32-bit word from a location in serial EEPROM using the card's PCI
2795 * VPD capability. Note that this function must be called with a virtual
2798 int t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data)
2800 unsigned int base = adapter->params.pci.vpd_cap_addr;
2804 * VPD Accesses must alway be 4-byte aligned!
2806 if (addr >= EEPROMVSIZE || (addr & 3))
2810 * Wait for any previous operation which may still be in flight to
2813 ret = t4_seeprom_wait(adapter);
2815 CH_ERR(adapter, "VPD still busy from previous operation\n");
2820 * Issue our new VPD Read request, mark the VPD as being busy and wait
2821 * for our request to complete. If it doesn't complete, note the
2822 * error and return it to our caller. Note that we do not reset the
2825 t4_os_pci_write_cfg2(adapter, base + PCI_VPD_ADDR, (u16)addr);
2826 adapter->vpd_busy = 1;
2827 adapter->vpd_flag = PCI_VPD_ADDR_F;
2828 ret = t4_seeprom_wait(adapter);
2830 CH_ERR(adapter, "VPD read of address %#x failed\n", addr);
2835 * Grab the returned data, swizzle it into our endianness and
2838 t4_os_pci_read_cfg4(adapter, base + PCI_VPD_DATA, data);
2839 *data = le32_to_cpu(*data);
2844 * t4_seeprom_write - write a serial EEPROM location
2845 * @adapter: adapter to write
2846 * @addr: virtual EEPROM address
2847 * @data: value to write
2849 * Write a 32-bit word to a location in serial EEPROM using the card's PCI
2850 * VPD capability. Note that this function must be called with a virtual
2853 int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data)
2855 unsigned int base = adapter->params.pci.vpd_cap_addr;
2861 * VPD Accesses must alway be 4-byte aligned!
2863 if (addr >= EEPROMVSIZE || (addr & 3))
2867 * Wait for any previous operation which may still be in flight to
2870 ret = t4_seeprom_wait(adapter);
2872 CH_ERR(adapter, "VPD still busy from previous operation\n");
2877 * Issue our new VPD Read request, mark the VPD as being busy and wait
2878 * for our request to complete. If it doesn't complete, note the
2879 * error and return it to our caller. Note that we do not reset the
2882 t4_os_pci_write_cfg4(adapter, base + PCI_VPD_DATA,
2884 t4_os_pci_write_cfg2(adapter, base + PCI_VPD_ADDR,
2885 (u16)addr | PCI_VPD_ADDR_F);
2886 adapter->vpd_busy = 1;
2887 adapter->vpd_flag = 0;
2888 ret = t4_seeprom_wait(adapter);
2890 CH_ERR(adapter, "VPD write of address %#x failed\n", addr);
2895 * Reset PCI_VPD_DATA register after a transaction and wait for our
2896 * request to complete. If it doesn't complete, return error.
2898 t4_os_pci_write_cfg4(adapter, base + PCI_VPD_DATA, 0);
2899 max_poll = EEPROM_MAX_POLL;
2901 udelay(EEPROM_DELAY);
2902 t4_seeprom_read(adapter, EEPROM_STAT_ADDR, &stats_reg);
2903 } while ((stats_reg & 0x1) && --max_poll);
2907 /* Return success! */
2912 * t4_eeprom_ptov - translate a physical EEPROM address to virtual
2913 * @phys_addr: the physical EEPROM address
2914 * @fn: the PCI function number
2915 * @sz: size of function-specific area
2917 * Translate a physical EEPROM address to virtual. The first 1K is
2918 * accessed through virtual addresses starting at 31K, the rest is
2919 * accessed through virtual addresses starting at 0.
2921 * The mapping is as follows:
2922 * [0..1K) -> [31K..32K)
2923 * [1K..1K+A) -> [ES-A..ES)
2924 * [1K+A..ES) -> [0..ES-A-1K)
2926 * where A = @fn * @sz, and ES = EEPROM size.
2928 int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz)
2931 if (phys_addr < 1024)
2932 return phys_addr + (31 << 10);
2933 if (phys_addr < 1024 + fn)
2934 return EEPROMSIZE - fn + phys_addr - 1024;
2935 if (phys_addr < EEPROMSIZE)
2936 return phys_addr - 1024 - fn;
2941 * t4_seeprom_wp - enable/disable EEPROM write protection
2942 * @adapter: the adapter
2943 * @enable: whether to enable or disable write protection
2945 * Enables or disables write protection on the serial EEPROM.
2947 int t4_seeprom_wp(struct adapter *adapter, int enable)
2949 return t4_seeprom_write(adapter, EEPROM_STAT_ADDR, enable ? 0xc : 0);
2953 * get_vpd_keyword_val - Locates an information field keyword in the VPD
2954 * @vpd: Pointer to buffered vpd data structure
2955 * @kw: The keyword to search for
2956 * @region: VPD region to search (starting from 0)
2958 * Returns the value of the information field keyword or
2959 * -ENOENT otherwise.
2961 static int get_vpd_keyword_val(const u8 *vpd, const char *kw, int region)
2964 unsigned int offset, len;
2965 const struct t4_vpdr_hdr *vpdr;
2967 offset = sizeof(struct t4_vpd_hdr);
2968 vpdr = (const void *)(vpd + offset);
2969 tag = vpdr->vpdr_tag;
2970 len = (u16)vpdr->vpdr_len[0] + ((u16)vpdr->vpdr_len[1] << 8);
2972 offset += sizeof(struct t4_vpdr_hdr) + len;
2973 vpdr = (const void *)(vpd + offset);
2974 if (++tag != vpdr->vpdr_tag)
2976 len = (u16)vpdr->vpdr_len[0] + ((u16)vpdr->vpdr_len[1] << 8);
2978 offset += sizeof(struct t4_vpdr_hdr);
2980 if (offset + len > VPD_LEN) {
2984 for (i = offset; i + VPD_INFO_FLD_HDR_SIZE <= offset + len;) {
2985 if (memcmp(vpd + i , kw , 2) == 0){
2986 i += VPD_INFO_FLD_HDR_SIZE;
2990 i += VPD_INFO_FLD_HDR_SIZE + vpd[i+2];
2998 * get_vpd_params - read VPD parameters from VPD EEPROM
2999 * @adapter: adapter to read
3000 * @p: where to store the parameters
3001 * @vpd: caller provided temporary space to read the VPD into
3003 * Reads card parameters stored in VPD EEPROM.
3005 static int get_vpd_params(struct adapter *adapter, struct vpd_params *p,
3006 uint16_t device_id, u32 *buf)
3009 int ec, sn, pn, na, md;
3011 const u8 *vpd = (const u8 *)buf;
3014 * Card information normally starts at VPD_BASE but early cards had
3017 ret = t4_seeprom_read(adapter, VPD_BASE, buf);
3022 * The VPD shall have a unique identifier specified by the PCI SIG.
3023 * For chelsio adapters, the identifier is 0x82. The first byte of a VPD
3024 * shall be CHELSIO_VPD_UNIQUE_ID (0x82). The VPD programming software
3025 * is expected to automatically put this entry at the
3026 * beginning of the VPD.
3028 addr = *vpd == CHELSIO_VPD_UNIQUE_ID ? VPD_BASE : VPD_BASE_OLD;
3030 for (i = 0; i < VPD_LEN; i += 4) {
3031 ret = t4_seeprom_read(adapter, addr + i, buf++);
3036 #define FIND_VPD_KW(var,name) do { \
3037 var = get_vpd_keyword_val(vpd, name, 0); \
3039 CH_ERR(adapter, "missing VPD keyword " name "\n"); \
3044 FIND_VPD_KW(i, "RV");
3045 for (csum = 0; i >= 0; i--)
3050 "corrupted VPD EEPROM, actual csum %u\n", csum);
3054 FIND_VPD_KW(ec, "EC");
3055 FIND_VPD_KW(sn, "SN");
3056 FIND_VPD_KW(pn, "PN");
3057 FIND_VPD_KW(na, "NA");
3060 memcpy(p->id, vpd + offsetof(struct t4_vpd_hdr, id_data), ID_LEN);
3062 memcpy(p->ec, vpd + ec, EC_LEN);
3064 i = vpd[sn - VPD_INFO_FLD_HDR_SIZE + 2];
3065 memcpy(p->sn, vpd + sn, min(i, SERNUM_LEN));
3067 i = vpd[pn - VPD_INFO_FLD_HDR_SIZE + 2];
3068 memcpy(p->pn, vpd + pn, min(i, PN_LEN));
3069 strstrip((char *)p->pn);
3070 i = vpd[na - VPD_INFO_FLD_HDR_SIZE + 2];
3071 memcpy(p->na, vpd + na, min(i, MACADDR_LEN));
3072 strstrip((char *)p->na);
3074 if (device_id & 0x80)
3075 return 0; /* Custom card */
3077 md = get_vpd_keyword_val(vpd, "VF", 1);
3079 snprintf(p->md, sizeof(p->md), "unknown");
3081 i = vpd[md - VPD_INFO_FLD_HDR_SIZE + 2];
3082 memcpy(p->md, vpd + md, min(i, MD_LEN));
3083 strstrip((char *)p->md);
3089 /* serial flash and firmware constants and flash config file constants */
3091 SF_ATTEMPTS = 10, /* max retries for SF operations */
3093 /* flash command opcodes */
3094 SF_PROG_PAGE = 2, /* program 256B page */
3095 SF_WR_DISABLE = 4, /* disable writes */
3096 SF_RD_STATUS = 5, /* read status register */
3097 SF_WR_ENABLE = 6, /* enable writes */
3098 SF_RD_DATA_FAST = 0xb, /* read flash */
3099 SF_RD_ID = 0x9f, /* read ID */
3100 SF_ERASE_SECTOR = 0xd8, /* erase 64KB sector */
3104 * sf1_read - read data from the serial flash
3105 * @adapter: the adapter
3106 * @byte_cnt: number of bytes to read
3107 * @cont: whether another operation will be chained
3108 * @lock: whether to lock SF for PL access only
3109 * @valp: where to store the read data
3111 * Reads up to 4 bytes of data from the serial flash. The location of
3112 * the read needs to be specified prior to calling this by issuing the
3113 * appropriate commands to the serial flash.
3115 static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont,
3116 int lock, u32 *valp)
3120 if (!byte_cnt || byte_cnt > 4)
3122 if (t4_read_reg(adapter, A_SF_OP) & F_BUSY)
3124 t4_write_reg(adapter, A_SF_OP,
3125 V_SF_LOCK(lock) | V_CONT(cont) | V_BYTECNT(byte_cnt - 1));
3126 ret = t4_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 5);
3128 *valp = t4_read_reg(adapter, A_SF_DATA);
3133 * sf1_write - write data to the serial flash
3134 * @adapter: the adapter
3135 * @byte_cnt: number of bytes to write
3136 * @cont: whether another operation will be chained
3137 * @lock: whether to lock SF for PL access only
3138 * @val: value to write
3140 * Writes up to 4 bytes of data to the serial flash. The location of
3141 * the write needs to be specified prior to calling this by issuing the
3142 * appropriate commands to the serial flash.
3144 static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont,
3147 if (!byte_cnt || byte_cnt > 4)
3149 if (t4_read_reg(adapter, A_SF_OP) & F_BUSY)
3151 t4_write_reg(adapter, A_SF_DATA, val);
3152 t4_write_reg(adapter, A_SF_OP, V_SF_LOCK(lock) |
3153 V_CONT(cont) | V_BYTECNT(byte_cnt - 1) | V_OP(1));
3154 return t4_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 5);
3158 * flash_wait_op - wait for a flash operation to complete
3159 * @adapter: the adapter
3160 * @attempts: max number of polls of the status register
3161 * @delay: delay between polls in ms
3163 * Wait for a flash operation to complete by polling the status register.
3165 static int flash_wait_op(struct adapter *adapter, int attempts, int delay)
3171 if ((ret = sf1_write(adapter, 1, 1, 1, SF_RD_STATUS)) != 0 ||
3172 (ret = sf1_read(adapter, 1, 0, 1, &status)) != 0)
3176 if (--attempts == 0)
3184 * t4_read_flash - read words from serial flash
3185 * @adapter: the adapter
3186 * @addr: the start address for the read
3187 * @nwords: how many 32-bit words to read
3188 * @data: where to store the read data
3189 * @byte_oriented: whether to store data as bytes or as words
3191 * Read the specified number of 32-bit words from the serial flash.
3192 * If @byte_oriented is set the read data is stored as a byte array
3193 * (i.e., big-endian), otherwise as 32-bit words in the platform's
3194 * natural endianness.
3196 int t4_read_flash(struct adapter *adapter, unsigned int addr,
3197 unsigned int nwords, u32 *data, int byte_oriented)
3201 if (addr + nwords * sizeof(u32) > adapter->params.sf_size || (addr & 3))
3204 addr = swab32(addr) | SF_RD_DATA_FAST;
3206 if ((ret = sf1_write(adapter, 4, 1, 0, addr)) != 0 ||
3207 (ret = sf1_read(adapter, 1, 1, 0, data)) != 0)
3210 for ( ; nwords; nwords--, data++) {
3211 ret = sf1_read(adapter, 4, nwords > 1, nwords == 1, data);
3213 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */
3217 *data = (__force __u32)(cpu_to_be32(*data));
3223 * t4_write_flash - write up to a page of data to the serial flash
3224 * @adapter: the adapter
3225 * @addr: the start address to write
3226 * @n: length of data to write in bytes
3227 * @data: the data to write
3228 * @byte_oriented: whether to store data as bytes or as words
3230 * Writes up to a page of data (256 bytes) to the serial flash starting
3231 * at the given address. All the data must be written to the same page.
3232 * If @byte_oriented is set the write data is stored as byte stream
3233 * (i.e. matches what on disk), otherwise in big-endian.
3235 int t4_write_flash(struct adapter *adapter, unsigned int addr,
3236 unsigned int n, const u8 *data, int byte_oriented)
3239 u32 buf[SF_PAGE_SIZE / 4];
3240 unsigned int i, c, left, val, offset = addr & 0xff;
3242 if (addr >= adapter->params.sf_size || offset + n > SF_PAGE_SIZE)
3245 val = swab32(addr) | SF_PROG_PAGE;
3247 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
3248 (ret = sf1_write(adapter, 4, 1, 1, val)) != 0)
3251 for (left = n; left; left -= c) {
3253 for (val = 0, i = 0; i < c; ++i)
3254 val = (val << 8) + *data++;
3257 val = cpu_to_be32(val);
3259 ret = sf1_write(adapter, c, c != left, 1, val);
3263 ret = flash_wait_op(adapter, 8, 1);
3267 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */
3269 /* Read the page to verify the write succeeded */
3270 ret = t4_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf,
3275 if (memcmp(data - n, (u8 *)buf + offset, n)) {
3277 "failed to correctly write the flash page at %#x\n",
3284 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */
3289 * t4_get_fw_version - read the firmware version
3290 * @adapter: the adapter
3291 * @vers: where to place the version
3293 * Reads the FW version from flash.
3295 int t4_get_fw_version(struct adapter *adapter, u32 *vers)
3297 return t4_read_flash(adapter, FLASH_FW_START +
3298 offsetof(struct fw_hdr, fw_ver), 1,
3303 * t4_get_fw_hdr - read the firmware header
3304 * @adapter: the adapter
3305 * @hdr: where to place the version
3307 * Reads the FW header from flash into caller provided buffer.
3309 int t4_get_fw_hdr(struct adapter *adapter, struct fw_hdr *hdr)
3311 return t4_read_flash(adapter, FLASH_FW_START,
3312 sizeof (*hdr) / sizeof (uint32_t), (uint32_t *)hdr, 1);
3316 * t4_get_bs_version - read the firmware bootstrap version
3317 * @adapter: the adapter
3318 * @vers: where to place the version
3320 * Reads the FW Bootstrap version from flash.
3322 int t4_get_bs_version(struct adapter *adapter, u32 *vers)
3324 return t4_read_flash(adapter, FLASH_FWBOOTSTRAP_START +
3325 offsetof(struct fw_hdr, fw_ver), 1,
3330 * t4_get_tp_version - read the TP microcode version
3331 * @adapter: the adapter
3332 * @vers: where to place the version
3334 * Reads the TP microcode version from flash.
3336 int t4_get_tp_version(struct adapter *adapter, u32 *vers)
3338 return t4_read_flash(adapter, FLASH_FW_START +
3339 offsetof(struct fw_hdr, tp_microcode_ver),
3344 * t4_get_exprom_version - return the Expansion ROM version (if any)
3345 * @adapter: the adapter
3346 * @vers: where to place the version
3348 * Reads the Expansion ROM header from FLASH and returns the version
3349 * number (if present) through the @vers return value pointer. We return
3350 * this in the Firmware Version Format since it's convenient. Return
3351 * 0 on success, -ENOENT if no Expansion ROM is present.
3353 int t4_get_exprom_version(struct adapter *adapter, u32 *vers)
3355 struct exprom_header {
3356 unsigned char hdr_arr[16]; /* must start with 0x55aa */
3357 unsigned char hdr_ver[4]; /* Expansion ROM version */
3359 u32 exprom_header_buf[DIV_ROUND_UP(sizeof(struct exprom_header),
3363 ret = t4_read_flash(adapter, FLASH_EXP_ROM_START,
3364 ARRAY_SIZE(exprom_header_buf), exprom_header_buf,
3369 hdr = (struct exprom_header *)exprom_header_buf;
3370 if (hdr->hdr_arr[0] != 0x55 || hdr->hdr_arr[1] != 0xaa)
3373 *vers = (V_FW_HDR_FW_VER_MAJOR(hdr->hdr_ver[0]) |
3374 V_FW_HDR_FW_VER_MINOR(hdr->hdr_ver[1]) |
3375 V_FW_HDR_FW_VER_MICRO(hdr->hdr_ver[2]) |
3376 V_FW_HDR_FW_VER_BUILD(hdr->hdr_ver[3]));
3381 * t4_get_scfg_version - return the Serial Configuration version
3382 * @adapter: the adapter
3383 * @vers: where to place the version
3385 * Reads the Serial Configuration Version via the Firmware interface
3386 * (thus this can only be called once we're ready to issue Firmware
3387 * commands). The format of the Serial Configuration version is
3388 * adapter specific. Returns 0 on success, an error on failure.
3390 * Note that early versions of the Firmware didn't include the ability
3391 * to retrieve the Serial Configuration version, so we zero-out the
3392 * return-value parameter in that case to avoid leaving it with
3395 * Also note that the Firmware will return its cached copy of the Serial
3396 * Initialization Revision ID, not the actual Revision ID as written in
3397 * the Serial EEPROM. This is only an issue if a new VPD has been written
3398 * and the Firmware/Chip haven't yet gone through a RESET sequence. So
3399 * it's best to defer calling this routine till after a FW_RESET_CMD has
3400 * been issued if the Host Driver will be performing a full adapter
3403 int t4_get_scfg_version(struct adapter *adapter, u32 *vers)
3408 scfgrev_param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
3409 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_SCFGREV));
3410 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
3411 1, &scfgrev_param, vers);
3418 * t4_get_vpd_version - return the VPD version
3419 * @adapter: the adapter
3420 * @vers: where to place the version
3422 * Reads the VPD via the Firmware interface (thus this can only be called
3423 * once we're ready to issue Firmware commands). The format of the
3424 * VPD version is adapter specific. Returns 0 on success, an error on
3427 * Note that early versions of the Firmware didn't include the ability
3428 * to retrieve the VPD version, so we zero-out the return-value parameter
3429 * in that case to avoid leaving it with garbage in it.
3431 * Also note that the Firmware will return its cached copy of the VPD
3432 * Revision ID, not the actual Revision ID as written in the Serial
3433 * EEPROM. This is only an issue if a new VPD has been written and the
3434 * Firmware/Chip haven't yet gone through a RESET sequence. So it's best
3435 * to defer calling this routine till after a FW_RESET_CMD has been issued
3436 * if the Host Driver will be performing a full adapter initialization.
3438 int t4_get_vpd_version(struct adapter *adapter, u32 *vers)
3443 vpdrev_param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
3444 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_VPDREV));
3445 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
3446 1, &vpdrev_param, vers);
3453 * t4_get_version_info - extract various chip/firmware version information
3454 * @adapter: the adapter
3456 * Reads various chip/firmware version numbers and stores them into the
3457 * adapter Adapter Parameters structure. If any of the efforts fails
3458 * the first failure will be returned, but all of the version numbers
3461 int t4_get_version_info(struct adapter *adapter)
3465 #define FIRST_RET(__getvinfo) \
3467 int __ret = __getvinfo; \
3468 if (__ret && !ret) \
3472 FIRST_RET(t4_get_fw_version(adapter, &adapter->params.fw_vers));
3473 FIRST_RET(t4_get_bs_version(adapter, &adapter->params.bs_vers));
3474 FIRST_RET(t4_get_tp_version(adapter, &adapter->params.tp_vers));
3475 FIRST_RET(t4_get_exprom_version(adapter, &adapter->params.er_vers));
3476 FIRST_RET(t4_get_scfg_version(adapter, &adapter->params.scfg_vers));
3477 FIRST_RET(t4_get_vpd_version(adapter, &adapter->params.vpd_vers));
3485 * t4_flash_erase_sectors - erase a range of flash sectors
3486 * @adapter: the adapter
3487 * @start: the first sector to erase
3488 * @end: the last sector to erase
3490 * Erases the sectors in the given inclusive range.
3492 int t4_flash_erase_sectors(struct adapter *adapter, int start, int end)
3496 if (end >= adapter->params.sf_nsec)
3499 while (start <= end) {
3500 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
3501 (ret = sf1_write(adapter, 4, 0, 1,
3502 SF_ERASE_SECTOR | (start << 8))) != 0 ||
3503 (ret = flash_wait_op(adapter, 14, 500)) != 0) {
3505 "erase of flash sector %d failed, error %d\n",
3511 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */
3516 * t4_flash_cfg_addr - return the address of the flash configuration file
3517 * @adapter: the adapter
3519 * Return the address within the flash where the Firmware Configuration
3520 * File is stored, or an error if the device FLASH is too small to contain
3521 * a Firmware Configuration File.
3523 int t4_flash_cfg_addr(struct adapter *adapter)
3526 * If the device FLASH isn't large enough to hold a Firmware
3527 * Configuration File, return an error.
3529 if (adapter->params.sf_size < FLASH_CFG_START + FLASH_CFG_MAX_SIZE)
3532 return FLASH_CFG_START;
3536 * Return TRUE if the specified firmware matches the adapter. I.e. T4
3537 * firmware for T4 adapters, T5 firmware for T5 adapters, etc. We go ahead
3538 * and emit an error message for mismatched firmware to save our caller the
3541 static int t4_fw_matches_chip(struct adapter *adap,
3542 const struct fw_hdr *hdr)
3545 * The expression below will return FALSE for any unsupported adapter
3546 * which will keep us "honest" in the future ...
3548 if ((is_t4(adap) && hdr->chip == FW_HDR_CHIP_T4) ||
3549 (is_t5(adap) && hdr->chip == FW_HDR_CHIP_T5) ||
3550 (is_t6(adap) && hdr->chip == FW_HDR_CHIP_T6))
3554 "FW image (%d) is not suitable for this adapter (%d)\n",
3555 hdr->chip, chip_id(adap));
3560 * t4_load_fw - download firmware
3561 * @adap: the adapter
3562 * @fw_data: the firmware image to write
3565 * Write the supplied firmware image to the card's serial flash.
3567 int t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size)
3572 u8 first_page[SF_PAGE_SIZE];
3573 const u32 *p = (const u32 *)fw_data;
3574 const struct fw_hdr *hdr = (const struct fw_hdr *)fw_data;
3575 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
3576 unsigned int fw_start_sec;
3577 unsigned int fw_start;
3578 unsigned int fw_size;
3580 if (ntohl(hdr->magic) == FW_HDR_MAGIC_BOOTSTRAP) {
3581 fw_start_sec = FLASH_FWBOOTSTRAP_START_SEC;
3582 fw_start = FLASH_FWBOOTSTRAP_START;
3583 fw_size = FLASH_FWBOOTSTRAP_MAX_SIZE;
3585 fw_start_sec = FLASH_FW_START_SEC;
3586 fw_start = FLASH_FW_START;
3587 fw_size = FLASH_FW_MAX_SIZE;
3591 CH_ERR(adap, "FW image has no data\n");
3596 "FW image size not multiple of 512 bytes\n");
3599 if ((unsigned int) be16_to_cpu(hdr->len512) * 512 != size) {
3601 "FW image size differs from size in FW header\n");
3604 if (size > fw_size) {
3605 CH_ERR(adap, "FW image too large, max is %u bytes\n",
3609 if (!t4_fw_matches_chip(adap, hdr))
3612 for (csum = 0, i = 0; i < size / sizeof(csum); i++)
3613 csum += be32_to_cpu(p[i]);
3615 if (csum != 0xffffffff) {
3617 "corrupted firmware image, checksum %#x\n", csum);
3621 i = DIV_ROUND_UP(size, sf_sec_size); /* # of sectors spanned */
3622 ret = t4_flash_erase_sectors(adap, fw_start_sec, fw_start_sec + i - 1);
3627 * We write the correct version at the end so the driver can see a bad
3628 * version if the FW write fails. Start by writing a copy of the
3629 * first page with a bad version.
3631 memcpy(first_page, fw_data, SF_PAGE_SIZE);
3632 ((struct fw_hdr *)first_page)->fw_ver = cpu_to_be32(0xffffffff);
3633 ret = t4_write_flash(adap, fw_start, SF_PAGE_SIZE, first_page, 1);
3638 for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) {
3639 addr += SF_PAGE_SIZE;
3640 fw_data += SF_PAGE_SIZE;
3641 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, fw_data, 1);
3646 ret = t4_write_flash(adap,
3647 fw_start + offsetof(struct fw_hdr, fw_ver),
3648 sizeof(hdr->fw_ver), (const u8 *)&hdr->fw_ver, 1);
3651 CH_ERR(adap, "firmware download failed, error %d\n",
3657 * t4_fwcache - firmware cache operation
3658 * @adap: the adapter
3659 * @op : the operation (flush or flush and invalidate)
3661 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op)
3663 struct fw_params_cmd c;
3665 memset(&c, 0, sizeof(c));
3667 cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) |
3668 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
3669 V_FW_PARAMS_CMD_PFN(adap->pf) |
3670 V_FW_PARAMS_CMD_VFN(0));
3671 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
3673 cpu_to_be32(V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
3674 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_FWCACHE));
3675 c.param[0].val = (__force __be32)op;
3677 return t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), NULL);
3680 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp,
3681 unsigned int *pif_req_wrptr,
3682 unsigned int *pif_rsp_wrptr)
3685 u32 cfg, val, req, rsp;
3687 cfg = t4_read_reg(adap, A_CIM_DEBUGCFG);
3688 if (cfg & F_LADBGEN)
3689 t4_write_reg(adap, A_CIM_DEBUGCFG, cfg ^ F_LADBGEN);
3691 val = t4_read_reg(adap, A_CIM_DEBUGSTS);
3692 req = G_POLADBGWRPTR(val);
3693 rsp = G_PILADBGWRPTR(val);
3695 *pif_req_wrptr = req;
3697 *pif_rsp_wrptr = rsp;
3699 for (i = 0; i < CIM_PIFLA_SIZE; i++) {
3700 for (j = 0; j < 6; j++) {
3701 t4_write_reg(adap, A_CIM_DEBUGCFG, V_POLADBGRDPTR(req) |
3702 V_PILADBGRDPTR(rsp));
3703 *pif_req++ = t4_read_reg(adap, A_CIM_PO_LA_DEBUGDATA);
3704 *pif_rsp++ = t4_read_reg(adap, A_CIM_PI_LA_DEBUGDATA);
3708 req = (req + 2) & M_POLADBGRDPTR;
3709 rsp = (rsp + 2) & M_PILADBGRDPTR;
3711 t4_write_reg(adap, A_CIM_DEBUGCFG, cfg);
3714 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp)
3719 cfg = t4_read_reg(adap, A_CIM_DEBUGCFG);
3720 if (cfg & F_LADBGEN)
3721 t4_write_reg(adap, A_CIM_DEBUGCFG, cfg ^ F_LADBGEN);
3723 for (i = 0; i < CIM_MALA_SIZE; i++) {
3724 for (j = 0; j < 5; j++) {
3726 t4_write_reg(adap, A_CIM_DEBUGCFG, V_POLADBGRDPTR(idx) |
3727 V_PILADBGRDPTR(idx));
3728 *ma_req++ = t4_read_reg(adap, A_CIM_PO_LA_MADEBUGDATA);
3729 *ma_rsp++ = t4_read_reg(adap, A_CIM_PI_LA_MADEBUGDATA);
3732 t4_write_reg(adap, A_CIM_DEBUGCFG, cfg);
3735 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf)
3739 for (i = 0; i < 8; i++) {
3740 u32 *p = la_buf + i;
3742 t4_write_reg(adap, A_ULP_RX_LA_CTL, i);
3743 j = t4_read_reg(adap, A_ULP_RX_LA_WRPTR);
3744 t4_write_reg(adap, A_ULP_RX_LA_RDPTR, j);
3745 for (j = 0; j < ULPRX_LA_SIZE; j++, p += 8)
3746 *p = t4_read_reg(adap, A_ULP_RX_LA_RDDATA);
3751 * fwcaps16_to_caps32 - convert 16-bit Port Capabilities to 32-bits
3752 * @caps16: a 16-bit Port Capabilities value
3754 * Returns the equivalent 32-bit Port Capabilities value.
3756 static uint32_t fwcaps16_to_caps32(uint16_t caps16)
3758 uint32_t caps32 = 0;
3760 #define CAP16_TO_CAP32(__cap) \
3762 if (caps16 & FW_PORT_CAP_##__cap) \
3763 caps32 |= FW_PORT_CAP32_##__cap; \
3766 CAP16_TO_CAP32(SPEED_100M);
3767 CAP16_TO_CAP32(SPEED_1G);
3768 CAP16_TO_CAP32(SPEED_25G);
3769 CAP16_TO_CAP32(SPEED_10G);
3770 CAP16_TO_CAP32(SPEED_40G);
3771 CAP16_TO_CAP32(SPEED_100G);
3772 CAP16_TO_CAP32(FC_RX);
3773 CAP16_TO_CAP32(FC_TX);
3774 CAP16_TO_CAP32(ANEG);
3775 CAP16_TO_CAP32(FORCE_PAUSE);
3776 CAP16_TO_CAP32(MDIAUTO);
3777 CAP16_TO_CAP32(MDISTRAIGHT);
3778 CAP16_TO_CAP32(FEC_RS);
3779 CAP16_TO_CAP32(FEC_BASER_RS);
3780 CAP16_TO_CAP32(802_3_PAUSE);
3781 CAP16_TO_CAP32(802_3_ASM_DIR);
3783 #undef CAP16_TO_CAP32
3789 * fwcaps32_to_caps16 - convert 32-bit Port Capabilities to 16-bits
3790 * @caps32: a 32-bit Port Capabilities value
3792 * Returns the equivalent 16-bit Port Capabilities value. Note that
3793 * not all 32-bit Port Capabilities can be represented in the 16-bit
3794 * Port Capabilities and some fields/values may not make it.
3796 static uint16_t fwcaps32_to_caps16(uint32_t caps32)
3798 uint16_t caps16 = 0;
3800 #define CAP32_TO_CAP16(__cap) \
3802 if (caps32 & FW_PORT_CAP32_##__cap) \
3803 caps16 |= FW_PORT_CAP_##__cap; \
3806 CAP32_TO_CAP16(SPEED_100M);
3807 CAP32_TO_CAP16(SPEED_1G);
3808 CAP32_TO_CAP16(SPEED_10G);
3809 CAP32_TO_CAP16(SPEED_25G);
3810 CAP32_TO_CAP16(SPEED_40G);
3811 CAP32_TO_CAP16(SPEED_100G);
3812 CAP32_TO_CAP16(FC_RX);
3813 CAP32_TO_CAP16(FC_TX);
3814 CAP32_TO_CAP16(802_3_PAUSE);
3815 CAP32_TO_CAP16(802_3_ASM_DIR);
3816 CAP32_TO_CAP16(ANEG);
3817 CAP32_TO_CAP16(FORCE_PAUSE);
3818 CAP32_TO_CAP16(MDIAUTO);
3819 CAP32_TO_CAP16(MDISTRAIGHT);
3820 CAP32_TO_CAP16(FEC_RS);
3821 CAP32_TO_CAP16(FEC_BASER_RS);
3823 #undef CAP32_TO_CAP16
3829 is_bt(struct port_info *pi)
3832 return (pi->port_type == FW_PORT_TYPE_BT_SGMII ||
3833 pi->port_type == FW_PORT_TYPE_BT_XFI ||
3834 pi->port_type == FW_PORT_TYPE_BT_XAUI);
3837 static int8_t fwcap_to_fec(uint32_t caps, bool unset_means_none)
3841 if ((caps & V_FW_PORT_CAP32_FEC(M_FW_PORT_CAP32_FEC)) == 0)
3842 return (unset_means_none ? FEC_NONE : 0);
3844 if (caps & FW_PORT_CAP32_FEC_RS)
3846 if (caps & FW_PORT_CAP32_FEC_BASER_RS)
3847 fec |= FEC_BASER_RS;
3848 if (caps & FW_PORT_CAP32_FEC_NO_FEC)
3855 * Note that 0 is not translated to NO_FEC.
3857 static uint32_t fec_to_fwcap(int8_t fec)
3861 /* Only real FECs allowed. */
3862 MPASS((fec & ~M_FW_PORT_CAP32_FEC) == 0);
3865 caps |= FW_PORT_CAP32_FEC_RS;
3866 if (fec & FEC_BASER_RS)
3867 caps |= FW_PORT_CAP32_FEC_BASER_RS;
3869 caps |= FW_PORT_CAP32_FEC_NO_FEC;
3875 * t4_link_l1cfg - apply link configuration to MAC/PHY
3876 * @phy: the PHY to setup
3877 * @mac: the MAC to setup
3878 * @lc: the requested link configuration
3880 * Set up a port's MAC and PHY according to a desired link configuration.
3881 * - If the PHY can auto-negotiate first decide what to advertise, then
3882 * enable/disable auto-negotiation as desired, and reset.
3883 * - If the PHY does not auto-negotiate just reset it.
3884 * - If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
3885 * otherwise do it later based on the outcome of auto-negotiation.
3887 int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port,
3888 struct link_config *lc)
3890 struct fw_port_cmd c;
3891 unsigned int mdi = V_FW_PORT_CAP32_MDI(FW_PORT_CAP32_MDI_AUTO);
3892 unsigned int aneg, fc, fec, speed, rcap;
3895 if (lc->requested_fc & PAUSE_RX)
3896 fc |= FW_PORT_CAP32_FC_RX;
3897 if (lc->requested_fc & PAUSE_TX)
3898 fc |= FW_PORT_CAP32_FC_TX;
3899 if (!(lc->requested_fc & PAUSE_AUTONEG))
3900 fc |= FW_PORT_CAP32_FORCE_PAUSE;
3902 if (lc->requested_aneg == AUTONEG_DISABLE)
3904 else if (lc->requested_aneg == AUTONEG_ENABLE)
3905 aneg = FW_PORT_CAP32_ANEG;
3907 aneg = lc->pcaps & FW_PORT_CAP32_ANEG;
3911 V_FW_PORT_CAP32_SPEED(M_FW_PORT_CAP32_SPEED);
3912 } else if (lc->requested_speed != 0)
3913 speed = speed_to_fwcap(lc->requested_speed);
3915 speed = fwcap_top_speed(lc->pcaps);
3918 if (fec_supported(speed)) {
3919 if (lc->requested_fec == FEC_AUTO) {
3920 if (lc->pcaps & FW_PORT_CAP32_FORCE_FEC) {
3921 if (speed & FW_PORT_CAP32_SPEED_100G) {
3922 fec |= FW_PORT_CAP32_FEC_RS;
3923 fec |= FW_PORT_CAP32_FEC_NO_FEC;
3925 fec |= FW_PORT_CAP32_FEC_RS;
3926 fec |= FW_PORT_CAP32_FEC_BASER_RS;
3927 fec |= FW_PORT_CAP32_FEC_NO_FEC;
3930 /* Set only 1b with old firmwares. */
3931 fec |= fec_to_fwcap(lc->fec_hint);
3934 fec |= fec_to_fwcap(lc->requested_fec &
3935 M_FW_PORT_CAP32_FEC);
3936 if (lc->requested_fec & FEC_MODULE)
3937 fec |= fec_to_fwcap(lc->fec_hint);
3940 if (lc->pcaps & FW_PORT_CAP32_FORCE_FEC)
3941 fec |= FW_PORT_CAP32_FORCE_FEC;
3942 else if (fec == FW_PORT_CAP32_FEC_NO_FEC)
3946 /* Force AN on for BT cards. */
3947 if (is_bt(adap->port[adap->chan_map[port]]))
3948 aneg = lc->pcaps & FW_PORT_CAP32_ANEG;
3950 rcap = aneg | speed | fc | fec;
3951 if ((rcap | lc->pcaps) != lc->pcaps) {
3953 CH_WARN(adap, "rcap 0x%08x, pcap 0x%08x, removed 0x%x\n", rcap,
3954 lc->pcaps, rcap & (rcap ^ lc->pcaps));
3960 memset(&c, 0, sizeof(c));
3961 c.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) |
3962 F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
3963 V_FW_PORT_CMD_PORTID(port));
3964 if (adap->params.port_caps32) {
3966 cpu_to_be32(V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG32) |
3968 c.u.l1cfg32.rcap32 = cpu_to_be32(rcap);
3971 cpu_to_be32(V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG) |
3973 c.u.l1cfg.rcap = cpu_to_be32(fwcaps32_to_caps16(rcap));
3976 return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL);
3980 * t4_restart_aneg - restart autonegotiation
3981 * @adap: the adapter
3982 * @mbox: mbox to use for the FW command
3983 * @port: the port id
3985 * Restarts autonegotiation for the selected port.
3987 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port)
3989 struct fw_port_cmd c;
3991 memset(&c, 0, sizeof(c));
3992 c.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) |
3993 F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
3994 V_FW_PORT_CMD_PORTID(port));
3996 cpu_to_be32(V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG) |
3998 c.u.l1cfg.rcap = cpu_to_be32(FW_PORT_CAP_ANEG);
3999 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
4002 struct intr_details {
4007 struct intr_action {
4010 bool (*action)(struct adapter *, int, bool);
4013 #define NONFATAL_IF_DISABLED 1
4015 const char *name; /* name of the INT_CAUSE register */
4016 int cause_reg; /* INT_CAUSE register */
4017 int enable_reg; /* INT_ENABLE register */
4018 u32 fatal; /* bits that are fatal */
4019 int flags; /* hints */
4020 const struct intr_details *details;
4021 const struct intr_action *actions;
4025 intr_alert_char(u32 cause, u32 enable, u32 fatal)
4036 t4_show_intr_info(struct adapter *adap, const struct intr_info *ii, u32 cause)
4038 u32 enable, fatal, leftover;
4039 const struct intr_details *details;
4042 enable = t4_read_reg(adap, ii->enable_reg);
4043 if (ii->flags & NONFATAL_IF_DISABLED)
4044 fatal = ii->fatal & t4_read_reg(adap, ii->enable_reg);
4047 alert = intr_alert_char(cause, enable, fatal);
4048 CH_ALERT(adap, "%c %s 0x%x = 0x%08x, E 0x%08x, F 0x%08x\n",
4049 alert, ii->name, ii->cause_reg, cause, enable, fatal);
4052 for (details = ii->details; details && details->mask != 0; details++) {
4053 u32 msgbits = details->mask & cause;
4056 alert = intr_alert_char(msgbits, enable, ii->fatal);
4057 CH_ALERT(adap, " %c [0x%08x] %s\n", alert, msgbits,
4059 leftover &= ~msgbits;
4061 if (leftover != 0 && leftover != cause)
4062 CH_ALERT(adap, " ? [0x%08x]\n", leftover);
4066 * Returns true for fatal error.
4069 t4_handle_intr(struct adapter *adap, const struct intr_info *ii,
4070 u32 additional_cause, bool verbose)
4074 const struct intr_action *action;
4077 * Read and display cause. Note that the top level PL_INT_CAUSE is a
4078 * bit special and we need to completely ignore the bits that are not in
4081 cause = t4_read_reg(adap, ii->cause_reg);
4082 if (ii->cause_reg == A_PL_INT_CAUSE)
4083 cause &= t4_read_reg(adap, ii->enable_reg);
4084 if (verbose || cause != 0)
4085 t4_show_intr_info(adap, ii, cause);
4086 fatal = cause & ii->fatal;
4087 if (fatal != 0 && ii->flags & NONFATAL_IF_DISABLED)
4088 fatal &= t4_read_reg(adap, ii->enable_reg);
4089 cause |= additional_cause;
4094 for (action = ii->actions; action && action->mask != 0; action++) {
4095 if (!(action->mask & cause))
4097 rc |= (action->action)(adap, action->arg, verbose);
4101 t4_write_reg(adap, ii->cause_reg, cause);
4102 (void)t4_read_reg(adap, ii->cause_reg);
4108 * Interrupt handler for the PCIE module.
4110 static bool pcie_intr_handler(struct adapter *adap, int arg, bool verbose)
4112 static const struct intr_details sysbus_intr_details[] = {
4113 { F_RNPP, "RXNP array parity error" },
4114 { F_RPCP, "RXPC array parity error" },
4115 { F_RCIP, "RXCIF array parity error" },
4116 { F_RCCP, "Rx completions control array parity error" },
4117 { F_RFTP, "RXFT array parity error" },
4120 static const struct intr_info sysbus_intr_info = {
4121 .name = "PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS",
4122 .cause_reg = A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS,
4123 .enable_reg = A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_INTERRUPT_ENABLE,
4124 .fatal = F_RFTP | F_RCCP | F_RCIP | F_RPCP | F_RNPP,
4126 .details = sysbus_intr_details,
4129 static const struct intr_details pcie_port_intr_details[] = {
4130 { F_TPCP, "TXPC array parity error" },
4131 { F_TNPP, "TXNP array parity error" },
4132 { F_TFTP, "TXFT array parity error" },
4133 { F_TCAP, "TXCA array parity error" },
4134 { F_TCIP, "TXCIF array parity error" },
4135 { F_RCAP, "RXCA array parity error" },
4136 { F_OTDD, "outbound request TLP discarded" },
4137 { F_RDPE, "Rx data parity error" },
4138 { F_TDUE, "Tx uncorrectable data error" },
4141 static const struct intr_info pcie_port_intr_info = {
4142 .name = "PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS",
4143 .cause_reg = A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS,
4144 .enable_reg = A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_INTERRUPT_ENABLE,
4145 .fatal = F_TPCP | F_TNPP | F_TFTP | F_TCAP | F_TCIP | F_RCAP |
4146 F_OTDD | F_RDPE | F_TDUE,
4148 .details = pcie_port_intr_details,
4151 static const struct intr_details pcie_intr_details[] = {
4152 { F_MSIADDRLPERR, "MSI AddrL parity error" },
4153 { F_MSIADDRHPERR, "MSI AddrH parity error" },
4154 { F_MSIDATAPERR, "MSI data parity error" },
4155 { F_MSIXADDRLPERR, "MSI-X AddrL parity error" },
4156 { F_MSIXADDRHPERR, "MSI-X AddrH parity error" },
4157 { F_MSIXDATAPERR, "MSI-X data parity error" },
4158 { F_MSIXDIPERR, "MSI-X DI parity error" },
4159 { F_PIOCPLPERR, "PCIe PIO completion FIFO parity error" },
4160 { F_PIOREQPERR, "PCIe PIO request FIFO parity error" },
4161 { F_TARTAGPERR, "PCIe target tag FIFO parity error" },
4162 { F_CCNTPERR, "PCIe CMD channel count parity error" },
4163 { F_CREQPERR, "PCIe CMD channel request parity error" },
4164 { F_CRSPPERR, "PCIe CMD channel response parity error" },
4165 { F_DCNTPERR, "PCIe DMA channel count parity error" },
4166 { F_DREQPERR, "PCIe DMA channel request parity error" },
4167 { F_DRSPPERR, "PCIe DMA channel response parity error" },
4168 { F_HCNTPERR, "PCIe HMA channel count parity error" },
4169 { F_HREQPERR, "PCIe HMA channel request parity error" },
4170 { F_HRSPPERR, "PCIe HMA channel response parity error" },
4171 { F_CFGSNPPERR, "PCIe config snoop FIFO parity error" },
4172 { F_FIDPERR, "PCIe FID parity error" },
4173 { F_INTXCLRPERR, "PCIe INTx clear parity error" },
4174 { F_MATAGPERR, "PCIe MA tag parity error" },
4175 { F_PIOTAGPERR, "PCIe PIO tag parity error" },
4176 { F_RXCPLPERR, "PCIe Rx completion parity error" },
4177 { F_RXWRPERR, "PCIe Rx write parity error" },
4178 { F_RPLPERR, "PCIe replay buffer parity error" },
4179 { F_PCIESINT, "PCIe core secondary fault" },
4180 { F_PCIEPINT, "PCIe core primary fault" },
4181 { F_UNXSPLCPLERR, "PCIe unexpected split completion error" },
4184 static const struct intr_details t5_pcie_intr_details[] = {
4185 { F_IPGRPPERR, "Parity errors observed by IP" },
4186 { F_NONFATALERR, "PCIe non-fatal error" },
4187 { F_READRSPERR, "Outbound read error" },
4188 { F_TRGT1GRPPERR, "PCIe TRGT1 group FIFOs parity error" },
4189 { F_IPSOTPERR, "PCIe IP SOT buffer SRAM parity error" },
4190 { F_IPRETRYPERR, "PCIe IP replay buffer parity error" },
4191 { F_IPRXDATAGRPPERR, "PCIe IP Rx data group SRAMs parity error" },
4192 { F_IPRXHDRGRPPERR, "PCIe IP Rx header group SRAMs parity error" },
4193 { F_PIOTAGQPERR, "PIO tag queue FIFO parity error" },
4194 { F_MAGRPPERR, "MA group FIFO parity error" },
4195 { F_VFIDPERR, "VFID SRAM parity error" },
4196 { F_FIDPERR, "FID SRAM parity error" },
4197 { F_CFGSNPPERR, "config snoop FIFO parity error" },
4198 { F_HRSPPERR, "HMA channel response data SRAM parity error" },
4199 { F_HREQRDPERR, "HMA channel read request SRAM parity error" },
4200 { F_HREQWRPERR, "HMA channel write request SRAM parity error" },
4201 { F_DRSPPERR, "DMA channel response data SRAM parity error" },
4202 { F_DREQRDPERR, "DMA channel write request SRAM parity error" },
4203 { F_CRSPPERR, "CMD channel response data SRAM parity error" },
4204 { F_CREQRDPERR, "CMD channel read request SRAM parity error" },
4205 { F_MSTTAGQPERR, "PCIe master tag queue SRAM parity error" },
4206 { F_TGTTAGQPERR, "PCIe target tag queue FIFO parity error" },
4207 { F_PIOREQGRPPERR, "PIO request group FIFOs parity error" },
4208 { F_PIOCPLGRPPERR, "PIO completion group FIFOs parity error" },
4209 { F_MSIXDIPERR, "MSI-X DI SRAM parity error" },
4210 { F_MSIXDATAPERR, "MSI-X data SRAM parity error" },
4211 { F_MSIXADDRHPERR, "MSI-X AddrH SRAM parity error" },
4212 { F_MSIXADDRLPERR, "MSI-X AddrL SRAM parity error" },
4213 { F_MSIXSTIPERR, "MSI-X STI SRAM parity error" },
4214 { F_MSTTIMEOUTPERR, "Master timeout FIFO parity error" },
4215 { F_MSTGRPPERR, "Master response read queue SRAM parity error" },
4218 struct intr_info pcie_intr_info = {
4219 .name = "PCIE_INT_CAUSE",
4220 .cause_reg = A_PCIE_INT_CAUSE,
4221 .enable_reg = A_PCIE_INT_ENABLE,
4222 .fatal = 0xffffffff,
4223 .flags = NONFATAL_IF_DISABLED,
4230 fatal |= t4_handle_intr(adap, &sysbus_intr_info, 0, verbose);
4231 fatal |= t4_handle_intr(adap, &pcie_port_intr_info, 0, verbose);
4233 pcie_intr_info.details = pcie_intr_details;
4235 pcie_intr_info.details = t5_pcie_intr_details;
4237 fatal |= t4_handle_intr(adap, &pcie_intr_info, 0, verbose);
4243 * TP interrupt handler.
4245 static bool tp_intr_handler(struct adapter *adap, int arg, bool verbose)
4247 static const struct intr_details tp_intr_details[] = {
4248 { 0x3fffffff, "TP parity error" },
4249 { F_FLMTXFLSTEMPTY, "TP out of Tx pages" },
4252 static const struct intr_info tp_intr_info = {
4253 .name = "TP_INT_CAUSE",
4254 .cause_reg = A_TP_INT_CAUSE,
4255 .enable_reg = A_TP_INT_ENABLE,
4256 .fatal = 0x7fffffff,
4257 .flags = NONFATAL_IF_DISABLED,
4258 .details = tp_intr_details,
4262 return (t4_handle_intr(adap, &tp_intr_info, 0, verbose));
4266 * SGE interrupt handler.
4268 static bool sge_intr_handler(struct adapter *adap, int arg, bool verbose)
4270 static const struct intr_info sge_int1_info = {
4271 .name = "SGE_INT_CAUSE1",
4272 .cause_reg = A_SGE_INT_CAUSE1,
4273 .enable_reg = A_SGE_INT_ENABLE1,
4274 .fatal = 0xffffffff,
4275 .flags = NONFATAL_IF_DISABLED,
4279 static const struct intr_info sge_int2_info = {
4280 .name = "SGE_INT_CAUSE2",
4281 .cause_reg = A_SGE_INT_CAUSE2,
4282 .enable_reg = A_SGE_INT_ENABLE2,
4283 .fatal = 0xffffffff,
4284 .flags = NONFATAL_IF_DISABLED,
4288 static const struct intr_details sge_int3_details[] = {
4290 "DBP pointer delivery for invalid context or QID" },
4291 { F_ERR_FLM_IDMA1 | F_ERR_FLM_IDMA0,
4292 "Invalid QID or header request by IDMA" },
4293 { F_ERR_FLM_HINT, "FLM hint is for invalid context or QID" },
4294 { F_ERR_PCIE_ERROR3, "SGE PCIe error for DBP thread 3" },
4295 { F_ERR_PCIE_ERROR2, "SGE PCIe error for DBP thread 2" },
4296 { F_ERR_PCIE_ERROR1, "SGE PCIe error for DBP thread 1" },
4297 { F_ERR_PCIE_ERROR0, "SGE PCIe error for DBP thread 0" },
4298 { F_ERR_TIMER_ABOVE_MAX_QID,
4299 "SGE GTS with timer 0-5 for IQID > 1023" },
4300 { F_ERR_CPL_EXCEED_IQE_SIZE,
4301 "SGE received CPL exceeding IQE size" },
4302 { F_ERR_INVALID_CIDX_INC, "SGE GTS CIDX increment too large" },
4303 { F_ERR_ITP_TIME_PAUSED, "SGE ITP error" },
4304 { F_ERR_CPL_OPCODE_0, "SGE received 0-length CPL" },
4305 { F_ERR_DROPPED_DB, "SGE DB dropped" },
4306 { F_ERR_DATA_CPL_ON_HIGH_QID1 | F_ERR_DATA_CPL_ON_HIGH_QID0,
4307 "SGE IQID > 1023 received CPL for FL" },
4308 { F_ERR_BAD_DB_PIDX3 | F_ERR_BAD_DB_PIDX2 | F_ERR_BAD_DB_PIDX1 |
4309 F_ERR_BAD_DB_PIDX0, "SGE DBP pidx increment too large" },
4310 { F_ERR_ING_PCIE_CHAN, "SGE Ingress PCIe channel mismatch" },
4311 { F_ERR_ING_CTXT_PRIO,
4312 "Ingress context manager priority user error" },
4313 { F_ERR_EGR_CTXT_PRIO,
4314 "Egress context manager priority user error" },
4315 { F_DBFIFO_HP_INT, "High priority DB FIFO threshold reached" },
4316 { F_DBFIFO_LP_INT, "Low priority DB FIFO threshold reached" },
4317 { F_REG_ADDRESS_ERR, "Undefined SGE register accessed" },
4318 { F_INGRESS_SIZE_ERR, "SGE illegal ingress QID" },
4319 { F_EGRESS_SIZE_ERR, "SGE illegal egress QID" },
4320 { 0x0000000f, "SGE context access for invalid queue" },
4323 static const struct intr_details t6_sge_int3_details[] = {
4325 "DBP pointer delivery for invalid context or QID" },
4326 { F_ERR_FLM_IDMA1 | F_ERR_FLM_IDMA0,
4327 "Invalid QID or header request by IDMA" },
4328 { F_ERR_FLM_HINT, "FLM hint is for invalid context or QID" },
4329 { F_ERR_PCIE_ERROR3, "SGE PCIe error for DBP thread 3" },
4330 { F_ERR_PCIE_ERROR2, "SGE PCIe error for DBP thread 2" },
4331 { F_ERR_PCIE_ERROR1, "SGE PCIe error for DBP thread 1" },
4332 { F_ERR_PCIE_ERROR0, "SGE PCIe error for DBP thread 0" },
4333 { F_ERR_TIMER_ABOVE_MAX_QID,
4334 "SGE GTS with timer 0-5 for IQID > 1023" },
4335 { F_ERR_CPL_EXCEED_IQE_SIZE,
4336 "SGE received CPL exceeding IQE size" },
4337 { F_ERR_INVALID_CIDX_INC, "SGE GTS CIDX increment too large" },
4338 { F_ERR_ITP_TIME_PAUSED, "SGE ITP error" },
4339 { F_ERR_CPL_OPCODE_0, "SGE received 0-length CPL" },
4340 { F_ERR_DROPPED_DB, "SGE DB dropped" },
4341 { F_ERR_DATA_CPL_ON_HIGH_QID1 | F_ERR_DATA_CPL_ON_HIGH_QID0,
4342 "SGE IQID > 1023 received CPL for FL" },
4343 { F_ERR_BAD_DB_PIDX3 | F_ERR_BAD_DB_PIDX2 | F_ERR_BAD_DB_PIDX1 |
4344 F_ERR_BAD_DB_PIDX0, "SGE DBP pidx increment too large" },
4345 { F_ERR_ING_PCIE_CHAN, "SGE Ingress PCIe channel mismatch" },
4346 { F_ERR_ING_CTXT_PRIO,
4347 "Ingress context manager priority user error" },
4348 { F_ERR_EGR_CTXT_PRIO,
4349 "Egress context manager priority user error" },
4350 { F_DBP_TBUF_FULL, "SGE DBP tbuf full" },
4352 "SGE WRE packet less than advertized length" },
4353 { F_REG_ADDRESS_ERR, "Undefined SGE register accessed" },
4354 { F_INGRESS_SIZE_ERR, "SGE illegal ingress QID" },
4355 { F_EGRESS_SIZE_ERR, "SGE illegal egress QID" },
4356 { 0x0000000f, "SGE context access for invalid queue" },
4359 struct intr_info sge_int3_info = {
4360 .name = "SGE_INT_CAUSE3",
4361 .cause_reg = A_SGE_INT_CAUSE3,
4362 .enable_reg = A_SGE_INT_ENABLE3,
4363 .fatal = F_ERR_CPL_EXCEED_IQE_SIZE,
4368 static const struct intr_info sge_int4_info = {
4369 .name = "SGE_INT_CAUSE4",
4370 .cause_reg = A_SGE_INT_CAUSE4,
4371 .enable_reg = A_SGE_INT_ENABLE4,
4377 static const struct intr_info sge_int5_info = {
4378 .name = "SGE_INT_CAUSE5",
4379 .cause_reg = A_SGE_INT_CAUSE5,
4380 .enable_reg = A_SGE_INT_ENABLE5,
4381 .fatal = 0xffffffff,
4382 .flags = NONFATAL_IF_DISABLED,
4386 static const struct intr_info sge_int6_info = {
4387 .name = "SGE_INT_CAUSE6",
4388 .cause_reg = A_SGE_INT_CAUSE6,
4389 .enable_reg = A_SGE_INT_ENABLE6,
4399 if (chip_id(adap) <= CHELSIO_T5) {
4400 sge_int3_info.details = sge_int3_details;
4402 sge_int3_info.details = t6_sge_int3_details;
4406 fatal |= t4_handle_intr(adap, &sge_int1_info, 0, verbose);
4407 fatal |= t4_handle_intr(adap, &sge_int2_info, 0, verbose);
4408 fatal |= t4_handle_intr(adap, &sge_int3_info, 0, verbose);
4409 fatal |= t4_handle_intr(adap, &sge_int4_info, 0, verbose);
4410 if (chip_id(adap) >= CHELSIO_T5)
4411 fatal |= t4_handle_intr(adap, &sge_int5_info, 0, verbose);
4412 if (chip_id(adap) >= CHELSIO_T6)
4413 fatal |= t4_handle_intr(adap, &sge_int6_info, 0, verbose);
4415 v = t4_read_reg(adap, A_SGE_ERROR_STATS);
4416 if (v & F_ERROR_QID_VALID) {
4417 CH_ERR(adap, "SGE error for QID %u\n", G_ERROR_QID(v));
4418 if (v & F_UNCAPTURED_ERROR)
4419 CH_ERR(adap, "SGE UNCAPTURED_ERROR set (clearing)\n");
4420 t4_write_reg(adap, A_SGE_ERROR_STATS,
4421 F_ERROR_QID_VALID | F_UNCAPTURED_ERROR);
4428 * CIM interrupt handler.
4430 static bool cim_intr_handler(struct adapter *adap, int arg, bool verbose)
4432 static const struct intr_action cim_host_intr_actions[] = {
4433 { F_TIMER0INT, 0, t4_os_dump_cimla },
4436 static const struct intr_details cim_host_intr_details[] = {
4438 { F_PCIE2CIMINTFPARERR, "CIM IBQ PCIe interface parity error" },
4441 { F_MA_CIM_INTFPERR, "MA2CIM interface parity error" },
4442 { F_PLCIM_MSTRSPDATAPARERR,
4443 "PL2CIM master response data parity error" },
4444 { F_NCSI2CIMINTFPARERR, "CIM IBQ NC-SI interface parity error" },
4445 { F_SGE2CIMINTFPARERR, "CIM IBQ SGE interface parity error" },
4446 { F_ULP2CIMINTFPARERR, "CIM IBQ ULP_TX interface parity error" },
4447 { F_TP2CIMINTFPARERR, "CIM IBQ TP interface parity error" },
4448 { F_OBQSGERX1PARERR, "CIM OBQ SGE1_RX parity error" },
4449 { F_OBQSGERX0PARERR, "CIM OBQ SGE0_RX parity error" },
4452 { F_TIEQOUTPARERRINT, "CIM TIEQ outgoing FIFO parity error" },
4453 { F_TIEQINPARERRINT, "CIM TIEQ incoming FIFO parity error" },
4454 { F_MBHOSTPARERR, "CIM mailbox host read parity error" },
4455 { F_MBUPPARERR, "CIM mailbox uP parity error" },
4456 { F_IBQTP0PARERR, "CIM IBQ TP0 parity error" },
4457 { F_IBQTP1PARERR, "CIM IBQ TP1 parity error" },
4458 { F_IBQULPPARERR, "CIM IBQ ULP parity error" },
4459 { F_IBQSGELOPARERR, "CIM IBQ SGE_LO parity error" },
4460 { F_IBQSGEHIPARERR | F_IBQPCIEPARERR, /* same bit */
4461 "CIM IBQ PCIe/SGE_HI parity error" },
4462 { F_IBQNCSIPARERR, "CIM IBQ NC-SI parity error" },
4463 { F_OBQULP0PARERR, "CIM OBQ ULP0 parity error" },
4464 { F_OBQULP1PARERR, "CIM OBQ ULP1 parity error" },
4465 { F_OBQULP2PARERR, "CIM OBQ ULP2 parity error" },
4466 { F_OBQULP3PARERR, "CIM OBQ ULP3 parity error" },
4467 { F_OBQSGEPARERR, "CIM OBQ SGE parity error" },
4468 { F_OBQNCSIPARERR, "CIM OBQ NC-SI parity error" },
4469 { F_TIMER1INT, "CIM TIMER0 interrupt" },
4470 { F_TIMER0INT, "CIM TIMER0 interrupt" },
4471 { F_PREFDROPINT, "CIM control register prefetch drop" },
4474 static const struct intr_info cim_host_intr_info = {
4475 .name = "CIM_HOST_INT_CAUSE",
4476 .cause_reg = A_CIM_HOST_INT_CAUSE,
4477 .enable_reg = A_CIM_HOST_INT_ENABLE,
4478 .fatal = 0x007fffe6,
4479 .flags = NONFATAL_IF_DISABLED,
4480 .details = cim_host_intr_details,
4481 .actions = cim_host_intr_actions,
4483 static const struct intr_details cim_host_upacc_intr_details[] = {
4484 { F_EEPROMWRINT, "CIM EEPROM came out of busy state" },
4485 { F_TIMEOUTMAINT, "CIM PIF MA timeout" },
4486 { F_TIMEOUTINT, "CIM PIF timeout" },
4487 { F_RSPOVRLOOKUPINT, "CIM response FIFO overwrite" },
4488 { F_REQOVRLOOKUPINT, "CIM request FIFO overwrite" },
4489 { F_BLKWRPLINT, "CIM block write to PL space" },
4490 { F_BLKRDPLINT, "CIM block read from PL space" },
4492 "CIM single write to PL space with illegal BEs" },
4494 "CIM single read from PL space with illegal BEs" },
4495 { F_BLKWRCTLINT, "CIM block write to CTL space" },
4496 { F_BLKRDCTLINT, "CIM block read from CTL space" },
4498 "CIM single write to CTL space with illegal BEs" },
4500 "CIM single read from CTL space with illegal BEs" },
4501 { F_BLKWREEPROMINT, "CIM block write to EEPROM space" },
4502 { F_BLKRDEEPROMINT, "CIM block read from EEPROM space" },
4504 "CIM single write to EEPROM space with illegal BEs" },
4506 "CIM single read from EEPROM space with illegal BEs" },
4507 { F_BLKWRFLASHINT, "CIM block write to flash space" },
4508 { F_BLKRDFLASHINT, "CIM block read from flash space" },
4509 { F_SGLWRFLASHINT, "CIM single write to flash space" },
4511 "CIM single read from flash space with illegal BEs" },
4512 { F_BLKWRBOOTINT, "CIM block write to boot space" },
4513 { F_BLKRDBOOTINT, "CIM block read from boot space" },
4514 { F_SGLWRBOOTINT, "CIM single write to boot space" },
4516 "CIM single read from boot space with illegal BEs" },
4517 { F_ILLWRBEINT, "CIM illegal write BEs" },
4518 { F_ILLRDBEINT, "CIM illegal read BEs" },
4519 { F_ILLRDINT, "CIM illegal read" },
4520 { F_ILLWRINT, "CIM illegal write" },
4521 { F_ILLTRANSINT, "CIM illegal transaction" },
4522 { F_RSVDSPACEINT, "CIM reserved space access" },
4525 static const struct intr_info cim_host_upacc_intr_info = {
4526 .name = "CIM_HOST_UPACC_INT_CAUSE",
4527 .cause_reg = A_CIM_HOST_UPACC_INT_CAUSE,
4528 .enable_reg = A_CIM_HOST_UPACC_INT_ENABLE,
4529 .fatal = 0x3fffeeff,
4530 .flags = NONFATAL_IF_DISABLED,
4531 .details = cim_host_upacc_intr_details,
4534 static const struct intr_info cim_pf_host_intr_info = {
4535 .name = "CIM_PF_HOST_INT_CAUSE",
4536 .cause_reg = MYPF_REG(A_CIM_PF_HOST_INT_CAUSE),
4537 .enable_reg = MYPF_REG(A_CIM_PF_HOST_INT_ENABLE),
4546 fw_err = t4_read_reg(adap, A_PCIE_FW);
4547 if (fw_err & F_PCIE_FW_ERR)
4548 t4_report_fw_error(adap);
4551 * When the Firmware detects an internal error which normally wouldn't
4552 * raise a Host Interrupt, it forces a CIM Timer0 interrupt in order
4553 * to make sure the Host sees the Firmware Crash. So if we have a
4554 * Timer0 interrupt and don't see a Firmware Crash, ignore the Timer0
4557 val = t4_read_reg(adap, A_CIM_HOST_INT_CAUSE);
4558 if (val & F_TIMER0INT && (!(fw_err & F_PCIE_FW_ERR) ||
4559 G_PCIE_FW_EVAL(fw_err) != PCIE_FW_EVAL_CRASH)) {
4560 t4_write_reg(adap, A_CIM_HOST_INT_CAUSE, F_TIMER0INT);
4564 fatal |= t4_handle_intr(adap, &cim_host_intr_info, 0, verbose);
4565 fatal |= t4_handle_intr(adap, &cim_host_upacc_intr_info, 0, verbose);
4566 fatal |= t4_handle_intr(adap, &cim_pf_host_intr_info, 0, verbose);
4572 * ULP RX interrupt handler.
4574 static bool ulprx_intr_handler(struct adapter *adap, int arg, bool verbose)
4576 static const struct intr_details ulprx_intr_details[] = {
4578 { F_SE_CNT_MISMATCH_1, "ULPRX SE count mismatch in channel 1" },
4579 { F_SE_CNT_MISMATCH_0, "ULPRX SE count mismatch in channel 0" },
4582 { F_CAUSE_CTX_1, "ULPRX channel 1 context error" },
4583 { F_CAUSE_CTX_0, "ULPRX channel 0 context error" },
4584 { 0x007fffff, "ULPRX parity error" },
4587 static const struct intr_info ulprx_intr_info = {
4588 .name = "ULP_RX_INT_CAUSE",
4589 .cause_reg = A_ULP_RX_INT_CAUSE,
4590 .enable_reg = A_ULP_RX_INT_ENABLE,
4591 .fatal = 0x07ffffff,
4592 .flags = NONFATAL_IF_DISABLED,
4593 .details = ulprx_intr_details,
4596 static const struct intr_info ulprx_intr2_info = {
4597 .name = "ULP_RX_INT_CAUSE_2",
4598 .cause_reg = A_ULP_RX_INT_CAUSE_2,
4599 .enable_reg = A_ULP_RX_INT_ENABLE_2,
4607 fatal |= t4_handle_intr(adap, &ulprx_intr_info, 0, verbose);
4608 fatal |= t4_handle_intr(adap, &ulprx_intr2_info, 0, verbose);
4614 * ULP TX interrupt handler.
4616 static bool ulptx_intr_handler(struct adapter *adap, int arg, bool verbose)
4618 static const struct intr_details ulptx_intr_details[] = {
4619 { F_PBL_BOUND_ERR_CH3, "ULPTX channel 3 PBL out of bounds" },
4620 { F_PBL_BOUND_ERR_CH2, "ULPTX channel 2 PBL out of bounds" },
4621 { F_PBL_BOUND_ERR_CH1, "ULPTX channel 1 PBL out of bounds" },
4622 { F_PBL_BOUND_ERR_CH0, "ULPTX channel 0 PBL out of bounds" },
4623 { 0x0fffffff, "ULPTX parity error" },
4626 static const struct intr_info ulptx_intr_info = {
4627 .name = "ULP_TX_INT_CAUSE",
4628 .cause_reg = A_ULP_TX_INT_CAUSE,
4629 .enable_reg = A_ULP_TX_INT_ENABLE,
4630 .fatal = 0x0fffffff,
4631 .flags = NONFATAL_IF_DISABLED,
4632 .details = ulptx_intr_details,
4635 static const struct intr_info ulptx_intr2_info = {
4636 .name = "ULP_TX_INT_CAUSE_2",
4637 .cause_reg = A_ULP_TX_INT_CAUSE_2,
4638 .enable_reg = A_ULP_TX_INT_ENABLE_2,
4640 .flags = NONFATAL_IF_DISABLED,
4646 fatal |= t4_handle_intr(adap, &ulptx_intr_info, 0, verbose);
4647 fatal |= t4_handle_intr(adap, &ulptx_intr2_info, 0, verbose);
4652 static bool pmtx_dump_dbg_stats(struct adapter *adap, int arg, bool verbose)
4657 t4_read_indirect(adap, A_PM_TX_DBG_CTRL, A_PM_TX_DBG_DATA, &data[0],
4658 ARRAY_SIZE(data), A_PM_TX_DBG_STAT0);
4659 for (i = 0; i < ARRAY_SIZE(data); i++) {
4660 CH_ALERT(adap, " - PM_TX_DBG_STAT%u (0x%x) = 0x%08x\n", i,
4661 A_PM_TX_DBG_STAT0 + i, data[i]);
4668 * PM TX interrupt handler.
4670 static bool pmtx_intr_handler(struct adapter *adap, int arg, bool verbose)
4672 static const struct intr_action pmtx_intr_actions[] = {
4673 { 0xffffffff, 0, pmtx_dump_dbg_stats },
4676 static const struct intr_details pmtx_intr_details[] = {
4677 { F_PCMD_LEN_OVFL0, "PMTX channel 0 pcmd too large" },
4678 { F_PCMD_LEN_OVFL1, "PMTX channel 1 pcmd too large" },
4679 { F_PCMD_LEN_OVFL2, "PMTX channel 2 pcmd too large" },
4680 { F_ZERO_C_CMD_ERROR, "PMTX 0-length pcmd" },
4681 { 0x0f000000, "PMTX icspi FIFO2X Rx framing error" },
4682 { 0x00f00000, "PMTX icspi FIFO Rx framing error" },
4683 { 0x000f0000, "PMTX icspi FIFO Tx framing error" },
4684 { 0x0000f000, "PMTX oespi FIFO Rx framing error" },
4685 { 0x00000f00, "PMTX oespi FIFO Tx framing error" },
4686 { 0x000000f0, "PMTX oespi FIFO2X Tx framing error" },
4687 { F_OESPI_PAR_ERROR, "PMTX oespi parity error" },
4688 { F_DB_OPTIONS_PAR_ERROR, "PMTX db_options parity error" },
4689 { F_ICSPI_PAR_ERROR, "PMTX icspi parity error" },
4690 { F_C_PCMD_PAR_ERROR, "PMTX c_pcmd parity error" },
4693 static const struct intr_info pmtx_intr_info = {
4694 .name = "PM_TX_INT_CAUSE",
4695 .cause_reg = A_PM_TX_INT_CAUSE,
4696 .enable_reg = A_PM_TX_INT_ENABLE,
4697 .fatal = 0xffffffff,
4699 .details = pmtx_intr_details,
4700 .actions = pmtx_intr_actions,
4703 return (t4_handle_intr(adap, &pmtx_intr_info, 0, verbose));
4707 * PM RX interrupt handler.
4709 static bool pmrx_intr_handler(struct adapter *adap, int arg, bool verbose)
4711 static const struct intr_details pmrx_intr_details[] = {
4713 { 0x18000000, "PMRX ospi overflow" },
4714 { F_MA_INTF_SDC_ERR, "PMRX MA interface SDC parity error" },
4715 { F_BUNDLE_LEN_PARERR, "PMRX bundle len FIFO parity error" },
4716 { F_BUNDLE_LEN_OVFL, "PMRX bundle len FIFO overflow" },
4717 { F_SDC_ERR, "PMRX SDC error" },
4720 { F_ZERO_E_CMD_ERROR, "PMRX 0-length pcmd" },
4721 { 0x003c0000, "PMRX iespi FIFO2X Rx framing error" },
4722 { 0x0003c000, "PMRX iespi Rx framing error" },
4723 { 0x00003c00, "PMRX iespi Tx framing error" },
4724 { 0x00000300, "PMRX ocspi Rx framing error" },
4725 { 0x000000c0, "PMRX ocspi Tx framing error" },
4726 { 0x00000030, "PMRX ocspi FIFO2X Tx framing error" },
4727 { F_OCSPI_PAR_ERROR, "PMRX ocspi parity error" },
4728 { F_DB_OPTIONS_PAR_ERROR, "PMRX db_options parity error" },
4729 { F_IESPI_PAR_ERROR, "PMRX iespi parity error" },
4730 { F_E_PCMD_PAR_ERROR, "PMRX e_pcmd parity error"},
4733 static const struct intr_info pmrx_intr_info = {
4734 .name = "PM_RX_INT_CAUSE",
4735 .cause_reg = A_PM_RX_INT_CAUSE,
4736 .enable_reg = A_PM_RX_INT_ENABLE,
4737 .fatal = 0x1fffffff,
4738 .flags = NONFATAL_IF_DISABLED,
4739 .details = pmrx_intr_details,
4743 return (t4_handle_intr(adap, &pmrx_intr_info, 0, verbose));
4747 * CPL switch interrupt handler.
4749 static bool cplsw_intr_handler(struct adapter *adap, int arg, bool verbose)
4751 static const struct intr_details cplsw_intr_details[] = {
4753 { F_PERR_CPL_128TO128_1, "CPLSW 128TO128 FIFO1 parity error" },
4754 { F_PERR_CPL_128TO128_0, "CPLSW 128TO128 FIFO0 parity error" },
4757 { F_CIM_OP_MAP_PERR, "CPLSW CIM op_map parity error" },
4758 { F_CIM_OVFL_ERROR, "CPLSW CIM overflow" },
4759 { F_TP_FRAMING_ERROR, "CPLSW TP framing error" },
4760 { F_SGE_FRAMING_ERROR, "CPLSW SGE framing error" },
4761 { F_CIM_FRAMING_ERROR, "CPLSW CIM framing error" },
4762 { F_ZERO_SWITCH_ERROR, "CPLSW no-switch error" },
4765 static const struct intr_info cplsw_intr_info = {
4766 .name = "CPL_INTR_CAUSE",
4767 .cause_reg = A_CPL_INTR_CAUSE,
4768 .enable_reg = A_CPL_INTR_ENABLE,
4770 .flags = NONFATAL_IF_DISABLED,
4771 .details = cplsw_intr_details,
4775 return (t4_handle_intr(adap, &cplsw_intr_info, 0, verbose));
4778 #define T4_LE_FATAL_MASK (F_PARITYERR | F_UNKNOWNCMD | F_REQQPARERR)
4779 #define T5_LE_FATAL_MASK (T4_LE_FATAL_MASK | F_VFPARERR)
4780 #define T6_LE_PERRCRC_MASK (F_PIPELINEERR | F_CLIPTCAMACCFAIL | \
4781 F_SRVSRAMACCFAIL | F_CLCAMCRCPARERR | F_CLCAMINTPERR | F_SSRAMINTPERR | \
4782 F_SRVSRAMPERR | F_VFSRAMPERR | F_TCAMINTPERR | F_TCAMCRCERR | \
4783 F_HASHTBLMEMACCERR | F_MAIFWRINTPERR | F_HASHTBLMEMCRCERR)
4784 #define T6_LE_FATAL_MASK (T6_LE_PERRCRC_MASK | F_T6_UNKNOWNCMD | \
4785 F_TCAMACCFAIL | F_HASHTBLACCFAIL | F_CMDTIDERR | F_CMDPRSRINTERR | \
4786 F_TOTCNTERR | F_CLCAMFIFOERR | F_CLIPSUBERR)
4789 * LE interrupt handler.
4791 static bool le_intr_handler(struct adapter *adap, int arg, bool verbose)
4793 static const struct intr_details le_intr_details[] = {
4794 { F_REQQPARERR, "LE request queue parity error" },
4795 { F_UNKNOWNCMD, "LE unknown command" },
4796 { F_ACTRGNFULL, "LE active region full" },
4797 { F_PARITYERR, "LE parity error" },
4798 { F_LIPMISS, "LE LIP miss" },
4799 { F_LIP0, "LE 0 LIP error" },
4802 static const struct intr_details t6_le_intr_details[] = {
4803 { F_CLIPSUBERR, "LE CLIP CAM reverse substitution error" },
4804 { F_CLCAMFIFOERR, "LE CLIP CAM internal FIFO error" },
4805 { F_CTCAMINVLDENT, "Invalid IPv6 CLIP TCAM entry" },
4806 { F_TCAMINVLDENT, "Invalid IPv6 TCAM entry" },
4807 { F_TOTCNTERR, "LE total active < TCAM count" },
4808 { F_CMDPRSRINTERR, "LE internal error in parser" },
4809 { F_CMDTIDERR, "Incorrect tid in LE command" },
4810 { F_T6_ACTRGNFULL, "LE active region full" },
4811 { F_T6_ACTCNTIPV6TZERO, "LE IPv6 active open TCAM counter -ve" },
4812 { F_T6_ACTCNTIPV4TZERO, "LE IPv4 active open TCAM counter -ve" },
4813 { F_T6_ACTCNTIPV6ZERO, "LE IPv6 active open counter -ve" },
4814 { F_T6_ACTCNTIPV4ZERO, "LE IPv4 active open counter -ve" },
4815 { F_HASHTBLACCFAIL, "Hash table read error (proto conflict)" },
4816 { F_TCAMACCFAIL, "LE TCAM access failure" },
4817 { F_T6_UNKNOWNCMD, "LE unknown command" },
4818 { F_T6_LIP0, "LE found 0 LIP during CLIP substitution" },
4819 { F_T6_LIPMISS, "LE CLIP lookup miss" },
4820 { T6_LE_PERRCRC_MASK, "LE parity/CRC error" },
4823 struct intr_info le_intr_info = {
4824 .name = "LE_DB_INT_CAUSE",
4825 .cause_reg = A_LE_DB_INT_CAUSE,
4826 .enable_reg = A_LE_DB_INT_ENABLE,
4828 .flags = NONFATAL_IF_DISABLED,
4833 if (chip_id(adap) <= CHELSIO_T5) {
4834 le_intr_info.details = le_intr_details;
4835 le_intr_info.fatal = T5_LE_FATAL_MASK;
4837 le_intr_info.details = t6_le_intr_details;
4838 le_intr_info.fatal = T6_LE_FATAL_MASK;
4841 return (t4_handle_intr(adap, &le_intr_info, 0, verbose));
4845 * MPS interrupt handler.
4847 static bool mps_intr_handler(struct adapter *adap, int arg, bool verbose)
4849 static const struct intr_details mps_rx_perr_intr_details[] = {
4850 { 0xffffffff, "MPS Rx parity error" },
4853 static const struct intr_info mps_rx_perr_intr_info = {
4854 .name = "MPS_RX_PERR_INT_CAUSE",
4855 .cause_reg = A_MPS_RX_PERR_INT_CAUSE,
4856 .enable_reg = A_MPS_RX_PERR_INT_ENABLE,
4857 .fatal = 0xffffffff,
4858 .flags = NONFATAL_IF_DISABLED,
4859 .details = mps_rx_perr_intr_details,
4862 static const struct intr_details mps_tx_intr_details[] = {
4863 { F_PORTERR, "MPS Tx destination port is disabled" },
4864 { F_FRMERR, "MPS Tx framing error" },
4865 { F_SECNTERR, "MPS Tx SOP/EOP error" },
4866 { F_BUBBLE, "MPS Tx underflow" },
4867 { V_TXDESCFIFO(M_TXDESCFIFO), "MPS Tx desc FIFO parity error" },
4868 { V_TXDATAFIFO(M_TXDATAFIFO), "MPS Tx data FIFO parity error" },
4869 { F_NCSIFIFO, "MPS Tx NC-SI FIFO parity error" },
4870 { V_TPFIFO(M_TPFIFO), "MPS Tx TP FIFO parity error" },
4873 static const struct intr_info mps_tx_intr_info = {
4874 .name = "MPS_TX_INT_CAUSE",
4875 .cause_reg = A_MPS_TX_INT_CAUSE,
4876 .enable_reg = A_MPS_TX_INT_ENABLE,
4878 .flags = NONFATAL_IF_DISABLED,
4879 .details = mps_tx_intr_details,
4882 static const struct intr_details mps_trc_intr_details[] = {
4883 { F_MISCPERR, "MPS TRC misc parity error" },
4884 { V_PKTFIFO(M_PKTFIFO), "MPS TRC packet FIFO parity error" },
4885 { V_FILTMEM(M_FILTMEM), "MPS TRC filter parity error" },
4888 static const struct intr_info mps_trc_intr_info = {
4889 .name = "MPS_TRC_INT_CAUSE",
4890 .cause_reg = A_MPS_TRC_INT_CAUSE,
4891 .enable_reg = A_MPS_TRC_INT_ENABLE,
4892 .fatal = F_MISCPERR | V_PKTFIFO(M_PKTFIFO) | V_FILTMEM(M_FILTMEM),
4894 .details = mps_trc_intr_details,
4897 static const struct intr_details mps_stat_sram_intr_details[] = {
4898 { 0xffffffff, "MPS statistics SRAM parity error" },
4901 static const struct intr_info mps_stat_sram_intr_info = {
4902 .name = "MPS_STAT_PERR_INT_CAUSE_SRAM",
4903 .cause_reg = A_MPS_STAT_PERR_INT_CAUSE_SRAM,
4904 .enable_reg = A_MPS_STAT_PERR_INT_ENABLE_SRAM,
4905 .fatal = 0x1fffffff,
4906 .flags = NONFATAL_IF_DISABLED,
4907 .details = mps_stat_sram_intr_details,
4910 static const struct intr_details mps_stat_tx_intr_details[] = {
4911 { 0xffffff, "MPS statistics Tx FIFO parity error" },
4914 static const struct intr_info mps_stat_tx_intr_info = {
4915 .name = "MPS_STAT_PERR_INT_CAUSE_TX_FIFO",
4916 .cause_reg = A_MPS_STAT_PERR_INT_CAUSE_TX_FIFO,
4917 .enable_reg = A_MPS_STAT_PERR_INT_ENABLE_TX_FIFO,
4919 .flags = NONFATAL_IF_DISABLED,
4920 .details = mps_stat_tx_intr_details,
4923 static const struct intr_details mps_stat_rx_intr_details[] = {
4924 { 0xffffff, "MPS statistics Rx FIFO parity error" },
4927 static const struct intr_info mps_stat_rx_intr_info = {
4928 .name = "MPS_STAT_PERR_INT_CAUSE_RX_FIFO",
4929 .cause_reg = A_MPS_STAT_PERR_INT_CAUSE_RX_FIFO,
4930 .enable_reg = A_MPS_STAT_PERR_INT_ENABLE_RX_FIFO,
4933 .details = mps_stat_rx_intr_details,
4936 static const struct intr_details mps_cls_intr_details[] = {
4937 { F_HASHSRAM, "MPS hash SRAM parity error" },
4938 { F_MATCHTCAM, "MPS match TCAM parity error" },
4939 { F_MATCHSRAM, "MPS match SRAM parity error" },
4942 static const struct intr_info mps_cls_intr_info = {
4943 .name = "MPS_CLS_INT_CAUSE",
4944 .cause_reg = A_MPS_CLS_INT_CAUSE,
4945 .enable_reg = A_MPS_CLS_INT_ENABLE,
4946 .fatal = F_MATCHSRAM | F_MATCHTCAM | F_HASHSRAM,
4948 .details = mps_cls_intr_details,
4951 static const struct intr_details mps_stat_sram1_intr_details[] = {
4952 { 0xff, "MPS statistics SRAM1 parity error" },
4955 static const struct intr_info mps_stat_sram1_intr_info = {
4956 .name = "MPS_STAT_PERR_INT_CAUSE_SRAM1",
4957 .cause_reg = A_MPS_STAT_PERR_INT_CAUSE_SRAM1,
4958 .enable_reg = A_MPS_STAT_PERR_INT_ENABLE_SRAM1,
4961 .details = mps_stat_sram1_intr_details,
4968 fatal |= t4_handle_intr(adap, &mps_rx_perr_intr_info, 0, verbose);
4969 fatal |= t4_handle_intr(adap, &mps_tx_intr_info, 0, verbose);
4970 fatal |= t4_handle_intr(adap, &mps_trc_intr_info, 0, verbose);
4971 fatal |= t4_handle_intr(adap, &mps_stat_sram_intr_info, 0, verbose);
4972 fatal |= t4_handle_intr(adap, &mps_stat_tx_intr_info, 0, verbose);
4973 fatal |= t4_handle_intr(adap, &mps_stat_rx_intr_info, 0, verbose);
4974 fatal |= t4_handle_intr(adap, &mps_cls_intr_info, 0, verbose);
4975 if (chip_id(adap) > CHELSIO_T4) {
4976 fatal |= t4_handle_intr(adap, &mps_stat_sram1_intr_info, 0,
4980 t4_write_reg(adap, A_MPS_INT_CAUSE, is_t4(adap) ? 0 : 0xffffffff);
4981 t4_read_reg(adap, A_MPS_INT_CAUSE); /* flush */
4988 * EDC/MC interrupt handler.
4990 static bool mem_intr_handler(struct adapter *adap, int idx, bool verbose)
4992 static const char name[4][5] = { "EDC0", "EDC1", "MC0", "MC1" };
4993 unsigned int count_reg, v;
4994 static const struct intr_details mem_intr_details[] = {
4995 { F_ECC_UE_INT_CAUSE, "Uncorrectable ECC data error(s)" },
4996 { F_ECC_CE_INT_CAUSE, "Correctable ECC data error(s)" },
4997 { F_PERR_INT_CAUSE, "FIFO parity error" },
5000 struct intr_info ii = {
5001 .fatal = F_PERR_INT_CAUSE | F_ECC_UE_INT_CAUSE,
5002 .details = mem_intr_details,
5010 ii.name = "EDC0_INT_CAUSE";
5011 ii.cause_reg = EDC_REG(A_EDC_INT_CAUSE, 0);
5012 ii.enable_reg = EDC_REG(A_EDC_INT_ENABLE, 0);
5013 count_reg = EDC_REG(A_EDC_ECC_STATUS, 0);
5016 ii.name = "EDC1_INT_CAUSE";
5017 ii.cause_reg = EDC_REG(A_EDC_INT_CAUSE, 1);
5018 ii.enable_reg = EDC_REG(A_EDC_INT_ENABLE, 1);
5019 count_reg = EDC_REG(A_EDC_ECC_STATUS, 1);
5022 ii.name = "MC0_INT_CAUSE";
5024 ii.cause_reg = A_MC_INT_CAUSE;
5025 ii.enable_reg = A_MC_INT_ENABLE;
5026 count_reg = A_MC_ECC_STATUS;
5028 ii.cause_reg = A_MC_P_INT_CAUSE;
5029 ii.enable_reg = A_MC_P_INT_ENABLE;
5030 count_reg = A_MC_P_ECC_STATUS;
5034 ii.name = "MC1_INT_CAUSE";
5035 ii.cause_reg = MC_REG(A_MC_P_INT_CAUSE, 1);
5036 ii.enable_reg = MC_REG(A_MC_P_INT_ENABLE, 1);
5037 count_reg = MC_REG(A_MC_P_ECC_STATUS, 1);
5041 fatal = t4_handle_intr(adap, &ii, 0, verbose);
5043 v = t4_read_reg(adap, count_reg);
5045 if (G_ECC_UECNT(v) != 0) {
5047 "%s: %u uncorrectable ECC data error(s)\n",
5048 name[idx], G_ECC_UECNT(v));
5050 if (G_ECC_CECNT(v) != 0) {
5051 if (idx <= MEM_EDC1)
5052 t4_edc_err_read(adap, idx);
5053 CH_WARN_RATELIMIT(adap,
5054 "%s: %u correctable ECC data error(s)\n",
5055 name[idx], G_ECC_CECNT(v));
5057 t4_write_reg(adap, count_reg, 0xffffffff);
5063 static bool ma_wrap_status(struct adapter *adap, int arg, bool verbose)
5067 v = t4_read_reg(adap, A_MA_INT_WRAP_STATUS);
5069 "MA address wrap-around error by client %u to address %#x\n",
5070 G_MEM_WRAP_CLIENT_NUM(v), G_MEM_WRAP_ADDRESS(v) << 4);
5071 t4_write_reg(adap, A_MA_INT_WRAP_STATUS, v);
5078 * MA interrupt handler.
5080 static bool ma_intr_handler(struct adapter *adap, int arg, bool verbose)
5082 static const struct intr_action ma_intr_actions[] = {
5083 { F_MEM_WRAP_INT_CAUSE, 0, ma_wrap_status },
5086 static const struct intr_info ma_intr_info = {
5087 .name = "MA_INT_CAUSE",
5088 .cause_reg = A_MA_INT_CAUSE,
5089 .enable_reg = A_MA_INT_ENABLE,
5090 .fatal = F_MEM_PERR_INT_CAUSE | F_MEM_TO_INT_CAUSE,
5091 .flags = NONFATAL_IF_DISABLED,
5093 .actions = ma_intr_actions,
5095 static const struct intr_info ma_perr_status1 = {
5096 .name = "MA_PARITY_ERROR_STATUS1",
5097 .cause_reg = A_MA_PARITY_ERROR_STATUS1,
5098 .enable_reg = A_MA_PARITY_ERROR_ENABLE1,
5099 .fatal = 0xffffffff,
5104 static const struct intr_info ma_perr_status2 = {
5105 .name = "MA_PARITY_ERROR_STATUS2",
5106 .cause_reg = A_MA_PARITY_ERROR_STATUS2,
5107 .enable_reg = A_MA_PARITY_ERROR_ENABLE2,
5108 .fatal = 0xffffffff,
5116 fatal |= t4_handle_intr(adap, &ma_intr_info, 0, verbose);
5117 fatal |= t4_handle_intr(adap, &ma_perr_status1, 0, verbose);
5118 if (chip_id(adap) > CHELSIO_T4)
5119 fatal |= t4_handle_intr(adap, &ma_perr_status2, 0, verbose);
5125 * SMB interrupt handler.
5127 static bool smb_intr_handler(struct adapter *adap, int arg, bool verbose)
5129 static const struct intr_details smb_intr_details[] = {
5130 { F_MSTTXFIFOPARINT, "SMB master Tx FIFO parity error" },
5131 { F_MSTRXFIFOPARINT, "SMB master Rx FIFO parity error" },
5132 { F_SLVFIFOPARINT, "SMB slave FIFO parity error" },
5135 static const struct intr_info smb_intr_info = {
5136 .name = "SMB_INT_CAUSE",
5137 .cause_reg = A_SMB_INT_CAUSE,
5138 .enable_reg = A_SMB_INT_ENABLE,
5139 .fatal = F_SLVFIFOPARINT | F_MSTRXFIFOPARINT | F_MSTTXFIFOPARINT,
5141 .details = smb_intr_details,
5145 return (t4_handle_intr(adap, &smb_intr_info, 0, verbose));
5149 * NC-SI interrupt handler.
5151 static bool ncsi_intr_handler(struct adapter *adap, int arg, bool verbose)
5153 static const struct intr_details ncsi_intr_details[] = {
5154 { F_CIM_DM_PRTY_ERR, "NC-SI CIM parity error" },
5155 { F_MPS_DM_PRTY_ERR, "NC-SI MPS parity error" },
5156 { F_TXFIFO_PRTY_ERR, "NC-SI Tx FIFO parity error" },
5157 { F_RXFIFO_PRTY_ERR, "NC-SI Rx FIFO parity error" },
5160 static const struct intr_info ncsi_intr_info = {
5161 .name = "NCSI_INT_CAUSE",
5162 .cause_reg = A_NCSI_INT_CAUSE,
5163 .enable_reg = A_NCSI_INT_ENABLE,
5164 .fatal = F_RXFIFO_PRTY_ERR | F_TXFIFO_PRTY_ERR |
5165 F_MPS_DM_PRTY_ERR | F_CIM_DM_PRTY_ERR,
5167 .details = ncsi_intr_details,
5171 return (t4_handle_intr(adap, &ncsi_intr_info, 0, verbose));
5175 * MAC interrupt handler.
5177 static bool mac_intr_handler(struct adapter *adap, int port, bool verbose)
5179 static const struct intr_details mac_intr_details[] = {
5180 { F_TXFIFO_PRTY_ERR, "MAC Tx FIFO parity error" },
5181 { F_RXFIFO_PRTY_ERR, "MAC Rx FIFO parity error" },
5185 struct intr_info ii;
5189 snprintf(name, sizeof(name), "XGMAC_PORT%u_INT_CAUSE", port);
5191 ii.cause_reg = PORT_REG(port, A_XGMAC_PORT_INT_CAUSE);
5192 ii.enable_reg = PORT_REG(port, A_XGMAC_PORT_INT_EN);
5193 ii.fatal = F_TXFIFO_PRTY_ERR | F_RXFIFO_PRTY_ERR;
5195 ii.details = mac_intr_details;
5198 snprintf(name, sizeof(name), "MAC_PORT%u_INT_CAUSE", port);
5200 ii.cause_reg = T5_PORT_REG(port, A_MAC_PORT_INT_CAUSE);
5201 ii.enable_reg = T5_PORT_REG(port, A_MAC_PORT_INT_EN);
5202 ii.fatal = F_TXFIFO_PRTY_ERR | F_RXFIFO_PRTY_ERR;
5204 ii.details = mac_intr_details;
5207 fatal |= t4_handle_intr(adap, &ii, 0, verbose);
5209 if (chip_id(adap) >= CHELSIO_T5) {
5210 snprintf(name, sizeof(name), "MAC_PORT%u_PERR_INT_CAUSE", port);
5212 ii.cause_reg = T5_PORT_REG(port, A_MAC_PORT_PERR_INT_CAUSE);
5213 ii.enable_reg = T5_PORT_REG(port, A_MAC_PORT_PERR_INT_EN);
5218 fatal |= t4_handle_intr(adap, &ii, 0, verbose);
5221 if (chip_id(adap) >= CHELSIO_T6) {
5222 snprintf(name, sizeof(name), "MAC_PORT%u_PERR_INT_CAUSE_100G", port);
5224 ii.cause_reg = T5_PORT_REG(port, A_MAC_PORT_PERR_INT_CAUSE_100G);
5225 ii.enable_reg = T5_PORT_REG(port, A_MAC_PORT_PERR_INT_EN_100G);
5230 fatal |= t4_handle_intr(adap, &ii, 0, verbose);
5236 static bool plpl_intr_handler(struct adapter *adap, int arg, bool verbose)
5238 static const struct intr_details plpl_intr_details[] = {
5239 { F_FATALPERR, "Fatal parity error" },
5240 { F_PERRVFID, "VFID_MAP parity error" },
5243 static const struct intr_info plpl_intr_info = {
5244 .name = "PL_PL_INT_CAUSE",
5245 .cause_reg = A_PL_PL_INT_CAUSE,
5246 .enable_reg = A_PL_PL_INT_ENABLE,
5247 .fatal = F_FATALPERR | F_PERRVFID,
5248 .flags = NONFATAL_IF_DISABLED,
5249 .details = plpl_intr_details,
5253 return (t4_handle_intr(adap, &plpl_intr_info, 0, verbose));
5257 * t4_slow_intr_handler - control path interrupt handler
5258 * @adap: the adapter
5259 * @verbose: increased verbosity, for debug
5261 * T4 interrupt handler for non-data global interrupt events, e.g., errors.
5262 * The designation 'slow' is because it involves register reads, while
5263 * data interrupts typically don't involve any MMIOs.
5265 int t4_slow_intr_handler(struct adapter *adap, bool verbose)
5267 static const struct intr_details pl_intr_details[] = {
5270 { F_ULP_TX, "ULP TX" },
5273 { F_CPL_SWITCH, "CPL Switch" },
5274 { F_ULP_RX, "ULP RX" },
5275 { F_PM_RX, "PM RX" },
5276 { F_PM_TX, "PM TX" },
5292 { F_NCSI, "NC-SI" },
5300 static const struct intr_info pl_perr_cause = {
5301 .name = "PL_PERR_CAUSE",
5302 .cause_reg = A_PL_PERR_CAUSE,
5303 .enable_reg = A_PL_PERR_ENABLE,
5304 .fatal = 0xffffffff,
5306 .details = pl_intr_details,
5309 static const struct intr_action pl_intr_action[] = {
5310 { F_MC1, MEM_MC1, mem_intr_handler },
5311 { F_ULP_TX, -1, ulptx_intr_handler },
5312 { F_SGE, -1, sge_intr_handler },
5313 { F_CPL_SWITCH, -1, cplsw_intr_handler },
5314 { F_ULP_RX, -1, ulprx_intr_handler },
5315 { F_PM_RX, -1, pmrx_intr_handler},
5316 { F_PM_TX, -1, pmtx_intr_handler},
5317 { F_MA, -1, ma_intr_handler },
5318 { F_TP, -1, tp_intr_handler },
5319 { F_LE, -1, le_intr_handler },
5320 { F_EDC1, MEM_EDC1, mem_intr_handler },
5321 { F_EDC0, MEM_EDC0, mem_intr_handler },
5322 { F_MC0, MEM_MC0, mem_intr_handler },
5323 { F_PCIE, -1, pcie_intr_handler },
5324 { F_MAC3, 3, mac_intr_handler},
5325 { F_MAC2, 2, mac_intr_handler},
5326 { F_MAC1, 1, mac_intr_handler},
5327 { F_MAC0, 0, mac_intr_handler},
5328 { F_SMB, -1, smb_intr_handler},
5329 { F_PL, -1, plpl_intr_handler },
5330 { F_NCSI, -1, ncsi_intr_handler},
5331 { F_MPS, -1, mps_intr_handler },
5332 { F_CIM, -1, cim_intr_handler },
5335 static const struct intr_info pl_intr_info = {
5336 .name = "PL_INT_CAUSE",
5337 .cause_reg = A_PL_INT_CAUSE,
5338 .enable_reg = A_PL_INT_ENABLE,
5341 .details = pl_intr_details,
5342 .actions = pl_intr_action,
5347 perr = t4_read_reg(adap, pl_perr_cause.cause_reg);
5348 if (verbose || perr != 0) {
5349 t4_show_intr_info(adap, &pl_perr_cause, perr);
5351 t4_write_reg(adap, pl_perr_cause.cause_reg, perr);
5353 perr |= t4_read_reg(adap, pl_intr_info.enable_reg);
5355 fatal = t4_handle_intr(adap, &pl_intr_info, perr, verbose);
5357 t4_fatal_err(adap, false);
5362 #define PF_INTR_MASK (F_PFSW | F_PFCIM)
5365 * t4_intr_enable - enable interrupts
5366 * @adapter: the adapter whose interrupts should be enabled
5368 * Enable PF-specific interrupts for the calling function and the top-level
5369 * interrupt concentrator for global interrupts. Interrupts are already
5370 * enabled at each module, here we just enable the roots of the interrupt
5373 * Note: this function should be called only when the driver manages
5374 * non PF-specific interrupts from the various HW modules. Only one PCI
5375 * function at a time should be doing this.
5377 void t4_intr_enable(struct adapter *adap)
5381 if (chip_id(adap) <= CHELSIO_T5)
5382 val = F_ERR_DROPPED_DB | F_ERR_EGR_CTXT_PRIO | F_DBFIFO_HP_INT;
5384 val = F_ERR_PCIE_ERROR0 | F_ERR_PCIE_ERROR1 | F_FATAL_WRE_LEN;
5385 val |= F_ERR_CPL_EXCEED_IQE_SIZE | F_ERR_INVALID_CIDX_INC |
5386 F_ERR_CPL_OPCODE_0 | F_ERR_DATA_CPL_ON_HIGH_QID1 |
5387 F_INGRESS_SIZE_ERR | F_ERR_DATA_CPL_ON_HIGH_QID0 |
5388 F_ERR_BAD_DB_PIDX3 | F_ERR_BAD_DB_PIDX2 | F_ERR_BAD_DB_PIDX1 |
5389 F_ERR_BAD_DB_PIDX0 | F_ERR_ING_CTXT_PRIO | F_DBFIFO_LP_INT |
5391 t4_set_reg_field(adap, A_SGE_INT_ENABLE3, val, val);
5392 t4_write_reg(adap, MYPF_REG(A_PL_PF_INT_ENABLE), PF_INTR_MASK);
5393 t4_set_reg_field(adap, A_PL_INT_ENABLE, F_SF | F_I2CM, 0);
5394 t4_set_reg_field(adap, A_PL_INT_MAP0, 0, 1 << adap->pf);
5398 * t4_intr_disable - disable interrupts
5399 * @adap: the adapter whose interrupts should be disabled
5401 * Disable interrupts. We only disable the top-level interrupt
5402 * concentrators. The caller must be a PCI function managing global
5405 void t4_intr_disable(struct adapter *adap)
5408 t4_write_reg(adap, MYPF_REG(A_PL_PF_INT_ENABLE), 0);
5409 t4_set_reg_field(adap, A_PL_INT_MAP0, 1 << adap->pf, 0);
5413 * t4_intr_clear - clear all interrupts
5414 * @adap: the adapter whose interrupts should be cleared
5416 * Clears all interrupts. The caller must be a PCI function managing
5417 * global interrupts.
5419 void t4_intr_clear(struct adapter *adap)
5421 static const u32 cause_reg[] = {
5422 A_CIM_HOST_INT_CAUSE,
5423 A_CIM_HOST_UPACC_INT_CAUSE,
5424 MYPF_REG(A_CIM_PF_HOST_INT_CAUSE),
5426 EDC_REG(A_EDC_INT_CAUSE, 0), EDC_REG(A_EDC_INT_CAUSE, 1),
5428 A_MA_INT_WRAP_STATUS,
5429 A_MA_PARITY_ERROR_STATUS1,
5431 A_MPS_CLS_INT_CAUSE,
5432 A_MPS_RX_PERR_INT_CAUSE,
5433 A_MPS_STAT_PERR_INT_CAUSE_RX_FIFO,
5434 A_MPS_STAT_PERR_INT_CAUSE_SRAM,
5435 A_MPS_TRC_INT_CAUSE,
5437 A_MPS_STAT_PERR_INT_CAUSE_TX_FIFO,
5451 A_ULP_RX_INT_CAUSE_2,
5453 A_ULP_TX_INT_CAUSE_2,
5455 MYPF_REG(A_PL_PF_INT_CAUSE),
5458 const int nchan = adap->chip_params->nchan;
5460 for (i = 0; i < ARRAY_SIZE(cause_reg); i++)
5461 t4_write_reg(adap, cause_reg[i], 0xffffffff);
5464 t4_write_reg(adap, A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS,
5466 t4_write_reg(adap, A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS,
5468 t4_write_reg(adap, A_MC_INT_CAUSE, 0xffffffff);
5469 for (i = 0; i < nchan; i++) {
5470 t4_write_reg(adap, PORT_REG(i, A_XGMAC_PORT_INT_CAUSE),
5474 if (chip_id(adap) >= CHELSIO_T5) {
5475 t4_write_reg(adap, A_MA_PARITY_ERROR_STATUS2, 0xffffffff);
5476 t4_write_reg(adap, A_MPS_STAT_PERR_INT_CAUSE_SRAM1, 0xffffffff);
5477 t4_write_reg(adap, A_SGE_INT_CAUSE5, 0xffffffff);
5478 t4_write_reg(adap, A_MC_P_INT_CAUSE, 0xffffffff);
5480 t4_write_reg(adap, MC_REG(A_MC_P_INT_CAUSE, 1),
5483 for (i = 0; i < nchan; i++) {
5484 t4_write_reg(adap, T5_PORT_REG(i,
5485 A_MAC_PORT_PERR_INT_CAUSE), 0xffffffff);
5486 if (chip_id(adap) > CHELSIO_T5) {
5487 t4_write_reg(adap, T5_PORT_REG(i,
5488 A_MAC_PORT_PERR_INT_CAUSE_100G),
5491 t4_write_reg(adap, T5_PORT_REG(i, A_MAC_PORT_INT_CAUSE),
5495 if (chip_id(adap) >= CHELSIO_T6) {
5496 t4_write_reg(adap, A_SGE_INT_CAUSE6, 0xffffffff);
5499 t4_write_reg(adap, A_MPS_INT_CAUSE, is_t4(adap) ? 0 : 0xffffffff);
5500 t4_write_reg(adap, A_PL_PERR_CAUSE, 0xffffffff);
5501 t4_write_reg(adap, A_PL_INT_CAUSE, 0xffffffff);
5502 (void) t4_read_reg(adap, A_PL_INT_CAUSE); /* flush */
5506 * hash_mac_addr - return the hash value of a MAC address
5507 * @addr: the 48-bit Ethernet MAC address
5509 * Hashes a MAC address according to the hash function used by HW inexact
5510 * (hash) address matching.
5512 static int hash_mac_addr(const u8 *addr)
5514 u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2];
5515 u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5];
5523 * t4_config_rss_range - configure a portion of the RSS mapping table
5524 * @adapter: the adapter
5525 * @mbox: mbox to use for the FW command
5526 * @viid: virtual interface whose RSS subtable is to be written
5527 * @start: start entry in the table to write
5528 * @n: how many table entries to write
5529 * @rspq: values for the "response queue" (Ingress Queue) lookup table
5530 * @nrspq: number of values in @rspq
5532 * Programs the selected part of the VI's RSS mapping table with the
5533 * provided values. If @nrspq < @n the supplied values are used repeatedly
5534 * until the full table range is populated.
5536 * The caller must ensure the values in @rspq are in the range allowed for
5539 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
5540 int start, int n, const u16 *rspq, unsigned int nrspq)
5543 const u16 *rsp = rspq;
5544 const u16 *rsp_end = rspq + nrspq;
5545 struct fw_rss_ind_tbl_cmd cmd;
5547 memset(&cmd, 0, sizeof(cmd));
5548 cmd.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_RSS_IND_TBL_CMD) |
5549 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
5550 V_FW_RSS_IND_TBL_CMD_VIID(viid));
5551 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
5554 * Each firmware RSS command can accommodate up to 32 RSS Ingress
5555 * Queue Identifiers. These Ingress Queue IDs are packed three to
5556 * a 32-bit word as 10-bit values with the upper remaining 2 bits
5560 int nq = min(n, 32);
5562 __be32 *qp = &cmd.iq0_to_iq2;
5565 * Set up the firmware RSS command header to send the next
5566 * "nq" Ingress Queue IDs to the firmware.
5568 cmd.niqid = cpu_to_be16(nq);
5569 cmd.startidx = cpu_to_be16(start);
5572 * "nq" more done for the start of the next loop.
5578 * While there are still Ingress Queue IDs to stuff into the
5579 * current firmware RSS command, retrieve them from the
5580 * Ingress Queue ID array and insert them into the command.
5584 * Grab up to the next 3 Ingress Queue IDs (wrapping
5585 * around the Ingress Queue ID array if necessary) and
5586 * insert them into the firmware RSS command at the
5587 * current 3-tuple position within the commad.
5591 int nqbuf = min(3, nq);
5594 qbuf[0] = qbuf[1] = qbuf[2] = 0;
5595 while (nqbuf && nq_packed < 32) {
5602 *qp++ = cpu_to_be32(V_FW_RSS_IND_TBL_CMD_IQ0(qbuf[0]) |
5603 V_FW_RSS_IND_TBL_CMD_IQ1(qbuf[1]) |
5604 V_FW_RSS_IND_TBL_CMD_IQ2(qbuf[2]));
5608 * Send this portion of the RRS table update to the firmware;
5609 * bail out on any errors.
5611 ret = t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL);
5619 * t4_config_glbl_rss - configure the global RSS mode
5620 * @adapter: the adapter
5621 * @mbox: mbox to use for the FW command
5622 * @mode: global RSS mode
5623 * @flags: mode-specific flags
5625 * Sets the global RSS mode.
5627 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
5630 struct fw_rss_glb_config_cmd c;
5632 memset(&c, 0, sizeof(c));
5633 c.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_RSS_GLB_CONFIG_CMD) |
5634 F_FW_CMD_REQUEST | F_FW_CMD_WRITE);
5635 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
5636 if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL) {
5637 c.u.manual.mode_pkd =
5638 cpu_to_be32(V_FW_RSS_GLB_CONFIG_CMD_MODE(mode));
5639 } else if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL) {
5640 c.u.basicvirtual.mode_keymode =
5641 cpu_to_be32(V_FW_RSS_GLB_CONFIG_CMD_MODE(mode));
5642 c.u.basicvirtual.synmapen_to_hashtoeplitz = cpu_to_be32(flags);
5645 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
5649 * t4_config_vi_rss - configure per VI RSS settings
5650 * @adapter: the adapter
5651 * @mbox: mbox to use for the FW command
5654 * @defq: id of the default RSS queue for the VI.
5655 * @skeyidx: RSS secret key table index for non-global mode
5656 * @skey: RSS vf_scramble key for VI.
5658 * Configures VI-specific RSS properties.
5660 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
5661 unsigned int flags, unsigned int defq, unsigned int skeyidx,
5664 struct fw_rss_vi_config_cmd c;
5666 memset(&c, 0, sizeof(c));
5667 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_RSS_VI_CONFIG_CMD) |
5668 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
5669 V_FW_RSS_VI_CONFIG_CMD_VIID(viid));
5670 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
5671 c.u.basicvirtual.defaultq_to_udpen = cpu_to_be32(flags |
5672 V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(defq));
5673 c.u.basicvirtual.secretkeyidx_pkd = cpu_to_be32(
5674 V_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX(skeyidx));
5675 c.u.basicvirtual.secretkeyxor = cpu_to_be32(skey);
5677 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
5680 /* Read an RSS table row */
5681 static int rd_rss_row(struct adapter *adap, int row, u32 *val)
5683 t4_write_reg(adap, A_TP_RSS_LKP_TABLE, 0xfff00000 | row);
5684 return t4_wait_op_done_val(adap, A_TP_RSS_LKP_TABLE, F_LKPTBLROWVLD, 1,
5689 * t4_read_rss - read the contents of the RSS mapping table
5690 * @adapter: the adapter
5691 * @map: holds the contents of the RSS mapping table
5693 * Reads the contents of the RSS hash->queue mapping table.
5695 int t4_read_rss(struct adapter *adapter, u16 *map)
5699 int rss_nentries = adapter->chip_params->rss_nentries;
5701 for (i = 0; i < rss_nentries / 2; ++i) {
5702 ret = rd_rss_row(adapter, i, &val);
5705 *map++ = G_LKPTBLQUEUE0(val);
5706 *map++ = G_LKPTBLQUEUE1(val);
5712 * t4_tp_fw_ldst_rw - Access TP indirect register through LDST
5713 * @adap: the adapter
5714 * @cmd: TP fw ldst address space type
5715 * @vals: where the indirect register values are stored/written
5716 * @nregs: how many indirect registers to read/write
5717 * @start_idx: index of first indirect register to read/write
5718 * @rw: Read (1) or Write (0)
5719 * @sleep_ok: if true we may sleep while awaiting command completion
5721 * Access TP indirect registers through LDST
5723 static int t4_tp_fw_ldst_rw(struct adapter *adap, int cmd, u32 *vals,
5724 unsigned int nregs, unsigned int start_index,
5725 unsigned int rw, bool sleep_ok)
5729 struct fw_ldst_cmd c;
5731 for (i = 0; i < nregs; i++) {
5732 memset(&c, 0, sizeof(c));
5733 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
5735 (rw ? F_FW_CMD_READ :
5737 V_FW_LDST_CMD_ADDRSPACE(cmd));
5738 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
5740 c.u.addrval.addr = cpu_to_be32(start_index + i);
5741 c.u.addrval.val = rw ? 0 : cpu_to_be32(vals[i]);
5742 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c,
5748 vals[i] = be32_to_cpu(c.u.addrval.val);
5754 * t4_tp_indirect_rw - Read/Write TP indirect register through LDST or backdoor
5755 * @adap: the adapter
5756 * @reg_addr: Address Register
5757 * @reg_data: Data register
5758 * @buff: where the indirect register values are stored/written
5759 * @nregs: how many indirect registers to read/write
5760 * @start_index: index of first indirect register to read/write
5761 * @rw: READ(1) or WRITE(0)
5762 * @sleep_ok: if true we may sleep while awaiting command completion
5764 * Read/Write TP indirect registers through LDST if possible.
5765 * Else, use backdoor access
5767 static void t4_tp_indirect_rw(struct adapter *adap, u32 reg_addr, u32 reg_data,
5768 u32 *buff, u32 nregs, u32 start_index, int rw,
5776 cmd = FW_LDST_ADDRSPC_TP_PIO;
5778 case A_TP_TM_PIO_ADDR:
5779 cmd = FW_LDST_ADDRSPC_TP_TM_PIO;
5781 case A_TP_MIB_INDEX:
5782 cmd = FW_LDST_ADDRSPC_TP_MIB;
5785 goto indirect_access;
5788 if (t4_use_ldst(adap))
5789 rc = t4_tp_fw_ldst_rw(adap, cmd, buff, nregs, start_index, rw,
5796 t4_read_indirect(adap, reg_addr, reg_data, buff, nregs,
5799 t4_write_indirect(adap, reg_addr, reg_data, buff, nregs,
5805 * t4_tp_pio_read - Read TP PIO registers
5806 * @adap: the adapter
5807 * @buff: where the indirect register values are written
5808 * @nregs: how many indirect registers to read
5809 * @start_index: index of first indirect register to read
5810 * @sleep_ok: if true we may sleep while awaiting command completion
5812 * Read TP PIO Registers
5814 void t4_tp_pio_read(struct adapter *adap, u32 *buff, u32 nregs,
5815 u32 start_index, bool sleep_ok)
5817 t4_tp_indirect_rw(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA, buff, nregs,
5818 start_index, 1, sleep_ok);
5822 * t4_tp_pio_write - Write TP PIO registers
5823 * @adap: the adapter
5824 * @buff: where the indirect register values are stored
5825 * @nregs: how many indirect registers to write
5826 * @start_index: index of first indirect register to write
5827 * @sleep_ok: if true we may sleep while awaiting command completion
5829 * Write TP PIO Registers
5831 void t4_tp_pio_write(struct adapter *adap, const u32 *buff, u32 nregs,
5832 u32 start_index, bool sleep_ok)
5834 t4_tp_indirect_rw(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA,
5835 __DECONST(u32 *, buff), nregs, start_index, 0, sleep_ok);
5839 * t4_tp_tm_pio_read - Read TP TM PIO registers
5840 * @adap: the adapter
5841 * @buff: where the indirect register values are written
5842 * @nregs: how many indirect registers to read
5843 * @start_index: index of first indirect register to read
5844 * @sleep_ok: if true we may sleep while awaiting command completion
5846 * Read TP TM PIO Registers
5848 void t4_tp_tm_pio_read(struct adapter *adap, u32 *buff, u32 nregs,
5849 u32 start_index, bool sleep_ok)
5851 t4_tp_indirect_rw(adap, A_TP_TM_PIO_ADDR, A_TP_TM_PIO_DATA, buff,
5852 nregs, start_index, 1, sleep_ok);
5856 * t4_tp_mib_read - Read TP MIB registers
5857 * @adap: the adapter
5858 * @buff: where the indirect register values are written
5859 * @nregs: how many indirect registers to read
5860 * @start_index: index of first indirect register to read
5861 * @sleep_ok: if true we may sleep while awaiting command completion
5863 * Read TP MIB Registers
5865 void t4_tp_mib_read(struct adapter *adap, u32 *buff, u32 nregs, u32 start_index,
5868 t4_tp_indirect_rw(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, buff, nregs,
5869 start_index, 1, sleep_ok);
5873 * t4_read_rss_key - read the global RSS key
5874 * @adap: the adapter
5875 * @key: 10-entry array holding the 320-bit RSS key
5876 * @sleep_ok: if true we may sleep while awaiting command completion
5878 * Reads the global 320-bit RSS key.
5880 void t4_read_rss_key(struct adapter *adap, u32 *key, bool sleep_ok)
5882 t4_tp_pio_read(adap, key, 10, A_TP_RSS_SECRET_KEY0, sleep_ok);
5886 * t4_write_rss_key - program one of the RSS keys
5887 * @adap: the adapter
5888 * @key: 10-entry array holding the 320-bit RSS key
5889 * @idx: which RSS key to write
5890 * @sleep_ok: if true we may sleep while awaiting command completion
5892 * Writes one of the RSS keys with the given 320-bit value. If @idx is
5893 * 0..15 the corresponding entry in the RSS key table is written,
5894 * otherwise the global RSS key is written.
5896 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx,
5899 u8 rss_key_addr_cnt = 16;
5900 u32 vrt = t4_read_reg(adap, A_TP_RSS_CONFIG_VRT);
5903 * T6 and later: for KeyMode 3 (per-vf and per-vf scramble),
5904 * allows access to key addresses 16-63 by using KeyWrAddrX
5905 * as index[5:4](upper 2) into key table
5907 if ((chip_id(adap) > CHELSIO_T5) &&
5908 (vrt & F_KEYEXTEND) && (G_KEYMODE(vrt) == 3))
5909 rss_key_addr_cnt = 32;
5911 t4_tp_pio_write(adap, key, 10, A_TP_RSS_SECRET_KEY0, sleep_ok);
5913 if (idx >= 0 && idx < rss_key_addr_cnt) {
5914 if (rss_key_addr_cnt > 16)
5915 t4_write_reg(adap, A_TP_RSS_CONFIG_VRT,
5916 vrt | V_KEYWRADDRX(idx >> 4) |
5917 V_T6_VFWRADDR(idx) | F_KEYWREN);
5919 t4_write_reg(adap, A_TP_RSS_CONFIG_VRT,
5920 vrt| V_KEYWRADDR(idx) | F_KEYWREN);
5925 * t4_read_rss_pf_config - read PF RSS Configuration Table
5926 * @adapter: the adapter
5927 * @index: the entry in the PF RSS table to read
5928 * @valp: where to store the returned value
5929 * @sleep_ok: if true we may sleep while awaiting command completion
5931 * Reads the PF RSS Configuration Table at the specified index and returns
5932 * the value found there.
5934 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index,
5935 u32 *valp, bool sleep_ok)
5937 t4_tp_pio_read(adapter, valp, 1, A_TP_RSS_PF0_CONFIG + index, sleep_ok);
5941 * t4_write_rss_pf_config - write PF RSS Configuration Table
5942 * @adapter: the adapter
5943 * @index: the entry in the VF RSS table to read
5944 * @val: the value to store
5945 * @sleep_ok: if true we may sleep while awaiting command completion
5947 * Writes the PF RSS Configuration Table at the specified index with the
5950 void t4_write_rss_pf_config(struct adapter *adapter, unsigned int index,
5951 u32 val, bool sleep_ok)
5953 t4_tp_pio_write(adapter, &val, 1, A_TP_RSS_PF0_CONFIG + index,
5958 * t4_read_rss_vf_config - read VF RSS Configuration Table
5959 * @adapter: the adapter
5960 * @index: the entry in the VF RSS table to read
5961 * @vfl: where to store the returned VFL
5962 * @vfh: where to store the returned VFH
5963 * @sleep_ok: if true we may sleep while awaiting command completion
5965 * Reads the VF RSS Configuration Table at the specified index and returns
5966 * the (VFL, VFH) values found there.
5968 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index,
5969 u32 *vfl, u32 *vfh, bool sleep_ok)
5971 u32 vrt, mask, data;
5973 if (chip_id(adapter) <= CHELSIO_T5) {
5974 mask = V_VFWRADDR(M_VFWRADDR);
5975 data = V_VFWRADDR(index);
5977 mask = V_T6_VFWRADDR(M_T6_VFWRADDR);
5978 data = V_T6_VFWRADDR(index);
5981 * Request that the index'th VF Table values be read into VFL/VFH.
5983 vrt = t4_read_reg(adapter, A_TP_RSS_CONFIG_VRT);
5984 vrt &= ~(F_VFRDRG | F_VFWREN | F_KEYWREN | mask);
5985 vrt |= data | F_VFRDEN;
5986 t4_write_reg(adapter, A_TP_RSS_CONFIG_VRT, vrt);
5989 * Grab the VFL/VFH values ...
5991 t4_tp_pio_read(adapter, vfl, 1, A_TP_RSS_VFL_CONFIG, sleep_ok);
5992 t4_tp_pio_read(adapter, vfh, 1, A_TP_RSS_VFH_CONFIG, sleep_ok);
5996 * t4_write_rss_vf_config - write VF RSS Configuration Table
5998 * @adapter: the adapter
5999 * @index: the entry in the VF RSS table to write
6000 * @vfl: the VFL to store
6001 * @vfh: the VFH to store
6003 * Writes the VF RSS Configuration Table at the specified index with the
6004 * specified (VFL, VFH) values.
6006 void t4_write_rss_vf_config(struct adapter *adapter, unsigned int index,
6007 u32 vfl, u32 vfh, bool sleep_ok)
6009 u32 vrt, mask, data;
6011 if (chip_id(adapter) <= CHELSIO_T5) {
6012 mask = V_VFWRADDR(M_VFWRADDR);
6013 data = V_VFWRADDR(index);
6015 mask = V_T6_VFWRADDR(M_T6_VFWRADDR);
6016 data = V_T6_VFWRADDR(index);
6020 * Load up VFL/VFH with the values to be written ...
6022 t4_tp_pio_write(adapter, &vfl, 1, A_TP_RSS_VFL_CONFIG, sleep_ok);
6023 t4_tp_pio_write(adapter, &vfh, 1, A_TP_RSS_VFH_CONFIG, sleep_ok);
6026 * Write the VFL/VFH into the VF Table at index'th location.
6028 vrt = t4_read_reg(adapter, A_TP_RSS_CONFIG_VRT);
6029 vrt &= ~(F_VFRDRG | F_VFWREN | F_KEYWREN | mask);
6030 vrt |= data | F_VFRDEN;
6031 t4_write_reg(adapter, A_TP_RSS_CONFIG_VRT, vrt);
6035 * t4_read_rss_pf_map - read PF RSS Map
6036 * @adapter: the adapter
6037 * @sleep_ok: if true we may sleep while awaiting command completion
6039 * Reads the PF RSS Map register and returns its value.
6041 u32 t4_read_rss_pf_map(struct adapter *adapter, bool sleep_ok)
6045 t4_tp_pio_read(adapter, &pfmap, 1, A_TP_RSS_PF_MAP, sleep_ok);
6051 * t4_write_rss_pf_map - write PF RSS Map
6052 * @adapter: the adapter
6053 * @pfmap: PF RSS Map value
6055 * Writes the specified value to the PF RSS Map register.
6057 void t4_write_rss_pf_map(struct adapter *adapter, u32 pfmap, bool sleep_ok)
6059 t4_tp_pio_write(adapter, &pfmap, 1, A_TP_RSS_PF_MAP, sleep_ok);
6063 * t4_read_rss_pf_mask - read PF RSS Mask
6064 * @adapter: the adapter
6065 * @sleep_ok: if true we may sleep while awaiting command completion
6067 * Reads the PF RSS Mask register and returns its value.
6069 u32 t4_read_rss_pf_mask(struct adapter *adapter, bool sleep_ok)
6073 t4_tp_pio_read(adapter, &pfmask, 1, A_TP_RSS_PF_MSK, sleep_ok);
6079 * t4_write_rss_pf_mask - write PF RSS Mask
6080 * @adapter: the adapter
6081 * @pfmask: PF RSS Mask value
6083 * Writes the specified value to the PF RSS Mask register.
6085 void t4_write_rss_pf_mask(struct adapter *adapter, u32 pfmask, bool sleep_ok)
6087 t4_tp_pio_write(adapter, &pfmask, 1, A_TP_RSS_PF_MSK, sleep_ok);
6091 * t4_tp_get_tcp_stats - read TP's TCP MIB counters
6092 * @adap: the adapter
6093 * @v4: holds the TCP/IP counter values
6094 * @v6: holds the TCP/IPv6 counter values
6095 * @sleep_ok: if true we may sleep while awaiting command completion
6097 * Returns the values of TP's TCP/IP and TCP/IPv6 MIB counters.
6098 * Either @v4 or @v6 may be %NULL to skip the corresponding stats.
6100 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
6101 struct tp_tcp_stats *v6, bool sleep_ok)
6103 u32 val[A_TP_MIB_TCP_RXT_SEG_LO - A_TP_MIB_TCP_OUT_RST + 1];
6105 #define STAT_IDX(x) ((A_TP_MIB_TCP_##x) - A_TP_MIB_TCP_OUT_RST)
6106 #define STAT(x) val[STAT_IDX(x)]
6107 #define STAT64(x) (((u64)STAT(x##_HI) << 32) | STAT(x##_LO))
6110 t4_tp_mib_read(adap, val, ARRAY_SIZE(val),
6111 A_TP_MIB_TCP_OUT_RST, sleep_ok);
6112 v4->tcp_out_rsts = STAT(OUT_RST);
6113 v4->tcp_in_segs = STAT64(IN_SEG);
6114 v4->tcp_out_segs = STAT64(OUT_SEG);
6115 v4->tcp_retrans_segs = STAT64(RXT_SEG);
6118 t4_tp_mib_read(adap, val, ARRAY_SIZE(val),
6119 A_TP_MIB_TCP_V6OUT_RST, sleep_ok);
6120 v6->tcp_out_rsts = STAT(OUT_RST);
6121 v6->tcp_in_segs = STAT64(IN_SEG);
6122 v6->tcp_out_segs = STAT64(OUT_SEG);
6123 v6->tcp_retrans_segs = STAT64(RXT_SEG);
6131 * t4_tp_get_err_stats - read TP's error MIB counters
6132 * @adap: the adapter
6133 * @st: holds the counter values
6134 * @sleep_ok: if true we may sleep while awaiting command completion
6136 * Returns the values of TP's error counters.
6138 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st,
6141 int nchan = adap->chip_params->nchan;
6143 t4_tp_mib_read(adap, st->mac_in_errs, nchan, A_TP_MIB_MAC_IN_ERR_0,
6146 t4_tp_mib_read(adap, st->hdr_in_errs, nchan, A_TP_MIB_HDR_IN_ERR_0,
6149 t4_tp_mib_read(adap, st->tcp_in_errs, nchan, A_TP_MIB_TCP_IN_ERR_0,
6152 t4_tp_mib_read(adap, st->tnl_cong_drops, nchan,
6153 A_TP_MIB_TNL_CNG_DROP_0, sleep_ok);
6155 t4_tp_mib_read(adap, st->ofld_chan_drops, nchan,
6156 A_TP_MIB_OFD_CHN_DROP_0, sleep_ok);
6158 t4_tp_mib_read(adap, st->tnl_tx_drops, nchan, A_TP_MIB_TNL_DROP_0,
6161 t4_tp_mib_read(adap, st->ofld_vlan_drops, nchan,
6162 A_TP_MIB_OFD_VLN_DROP_0, sleep_ok);
6164 t4_tp_mib_read(adap, st->tcp6_in_errs, nchan,
6165 A_TP_MIB_TCP_V6IN_ERR_0, sleep_ok);
6167 t4_tp_mib_read(adap, &st->ofld_no_neigh, 2, A_TP_MIB_OFD_ARP_DROP,
6172 * t4_tp_get_proxy_stats - read TP's proxy MIB counters
6173 * @adap: the adapter
6174 * @st: holds the counter values
6176 * Returns the values of TP's proxy counters.
6178 void t4_tp_get_proxy_stats(struct adapter *adap, struct tp_proxy_stats *st,
6181 int nchan = adap->chip_params->nchan;
6183 t4_tp_mib_read(adap, st->proxy, nchan, A_TP_MIB_TNL_LPBK_0, sleep_ok);
6187 * t4_tp_get_cpl_stats - read TP's CPL MIB counters
6188 * @adap: the adapter
6189 * @st: holds the counter values
6190 * @sleep_ok: if true we may sleep while awaiting command completion
6192 * Returns the values of TP's CPL counters.
6194 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st,
6197 int nchan = adap->chip_params->nchan;
6199 t4_tp_mib_read(adap, st->req, nchan, A_TP_MIB_CPL_IN_REQ_0, sleep_ok);
6201 t4_tp_mib_read(adap, st->rsp, nchan, A_TP_MIB_CPL_OUT_RSP_0, sleep_ok);
6205 * t4_tp_get_rdma_stats - read TP's RDMA MIB counters
6206 * @adap: the adapter
6207 * @st: holds the counter values
6209 * Returns the values of TP's RDMA counters.
6211 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st,
6214 t4_tp_mib_read(adap, &st->rqe_dfr_pkt, 2, A_TP_MIB_RQE_DFR_PKT,
6219 * t4_get_fcoe_stats - read TP's FCoE MIB counters for a port
6220 * @adap: the adapter
6221 * @idx: the port index
6222 * @st: holds the counter values
6223 * @sleep_ok: if true we may sleep while awaiting command completion
6225 * Returns the values of TP's FCoE counters for the selected port.
6227 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx,
6228 struct tp_fcoe_stats *st, bool sleep_ok)
6232 t4_tp_mib_read(adap, &st->frames_ddp, 1, A_TP_MIB_FCOE_DDP_0 + idx,
6235 t4_tp_mib_read(adap, &st->frames_drop, 1,
6236 A_TP_MIB_FCOE_DROP_0 + idx, sleep_ok);
6238 t4_tp_mib_read(adap, val, 2, A_TP_MIB_FCOE_BYTE_0_HI + 2 * idx,
6241 st->octets_ddp = ((u64)val[0] << 32) | val[1];
6245 * t4_get_usm_stats - read TP's non-TCP DDP MIB counters
6246 * @adap: the adapter
6247 * @st: holds the counter values
6248 * @sleep_ok: if true we may sleep while awaiting command completion
6250 * Returns the values of TP's counters for non-TCP directly-placed packets.
6252 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st,
6257 t4_tp_mib_read(adap, val, 4, A_TP_MIB_USM_PKTS, sleep_ok);
6259 st->frames = val[0];
6261 st->octets = ((u64)val[2] << 32) | val[3];
6265 * t4_read_mtu_tbl - returns the values in the HW path MTU table
6266 * @adap: the adapter
6267 * @mtus: where to store the MTU values
6268 * @mtu_log: where to store the MTU base-2 log (may be %NULL)
6270 * Reads the HW path MTU table.
6272 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log)
6277 for (i = 0; i < NMTUS; ++i) {
6278 t4_write_reg(adap, A_TP_MTU_TABLE,
6279 V_MTUINDEX(0xff) | V_MTUVALUE(i));
6280 v = t4_read_reg(adap, A_TP_MTU_TABLE);
6281 mtus[i] = G_MTUVALUE(v);
6283 mtu_log[i] = G_MTUWIDTH(v);
6288 * t4_read_cong_tbl - reads the congestion control table
6289 * @adap: the adapter
6290 * @incr: where to store the alpha values
6292 * Reads the additive increments programmed into the HW congestion
6295 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN])
6297 unsigned int mtu, w;
6299 for (mtu = 0; mtu < NMTUS; ++mtu)
6300 for (w = 0; w < NCCTRL_WIN; ++w) {
6301 t4_write_reg(adap, A_TP_CCTRL_TABLE,
6302 V_ROWINDEX(0xffff) | (mtu << 5) | w);
6303 incr[mtu][w] = (u16)t4_read_reg(adap,
6304 A_TP_CCTRL_TABLE) & 0x1fff;
6309 * t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register
6310 * @adap: the adapter
6311 * @addr: the indirect TP register address
6312 * @mask: specifies the field within the register to modify
6313 * @val: new value for the field
6315 * Sets a field of an indirect TP register to the given value.
6317 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
6318 unsigned int mask, unsigned int val)
6320 t4_write_reg(adap, A_TP_PIO_ADDR, addr);
6321 val |= t4_read_reg(adap, A_TP_PIO_DATA) & ~mask;
6322 t4_write_reg(adap, A_TP_PIO_DATA, val);
6326 * init_cong_ctrl - initialize congestion control parameters
6327 * @a: the alpha values for congestion control
6328 * @b: the beta values for congestion control
6330 * Initialize the congestion control parameters.
6332 static void init_cong_ctrl(unsigned short *a, unsigned short *b)
6334 a[0] = a[1] = a[2] = a[3] = a[4] = a[5] = a[6] = a[7] = a[8] = 1;
6359 b[0] = b[1] = b[2] = b[3] = b[4] = b[5] = b[6] = b[7] = b[8] = 0;
6362 b[13] = b[14] = b[15] = b[16] = 3;
6363 b[17] = b[18] = b[19] = b[20] = b[21] = 4;
6364 b[22] = b[23] = b[24] = b[25] = b[26] = b[27] = 5;
6369 /* The minimum additive increment value for the congestion control table */
6370 #define CC_MIN_INCR 2U
6373 * t4_load_mtus - write the MTU and congestion control HW tables
6374 * @adap: the adapter
6375 * @mtus: the values for the MTU table
6376 * @alpha: the values for the congestion control alpha parameter
6377 * @beta: the values for the congestion control beta parameter
6379 * Write the HW MTU table with the supplied MTUs and the high-speed
6380 * congestion control table with the supplied alpha, beta, and MTUs.
6381 * We write the two tables together because the additive increments
6382 * depend on the MTUs.
6384 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
6385 const unsigned short *alpha, const unsigned short *beta)
6387 static const unsigned int avg_pkts[NCCTRL_WIN] = {
6388 2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640,
6389 896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480,
6390 28672, 40960, 57344, 81920, 114688, 163840, 229376
6395 for (i = 0; i < NMTUS; ++i) {
6396 unsigned int mtu = mtus[i];
6397 unsigned int log2 = fls(mtu);
6399 if (!(mtu & ((1 << log2) >> 2))) /* round */
6401 t4_write_reg(adap, A_TP_MTU_TABLE, V_MTUINDEX(i) |
6402 V_MTUWIDTH(log2) | V_MTUVALUE(mtu));
6404 for (w = 0; w < NCCTRL_WIN; ++w) {
6407 inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w],
6410 t4_write_reg(adap, A_TP_CCTRL_TABLE, (i << 21) |
6411 (w << 16) | (beta[w] << 13) | inc);
6417 * t4_set_pace_tbl - set the pace table
6418 * @adap: the adapter
6419 * @pace_vals: the pace values in microseconds
6420 * @start: index of the first entry in the HW pace table to set
6421 * @n: how many entries to set
6423 * Sets (a subset of the) HW pace table.
6425 int t4_set_pace_tbl(struct adapter *adap, const unsigned int *pace_vals,
6426 unsigned int start, unsigned int n)
6428 unsigned int vals[NTX_SCHED], i;
6429 unsigned int tick_ns = dack_ticks_to_usec(adap, 1000);
6434 /* convert values from us to dack ticks, rounding to closest value */
6435 for (i = 0; i < n; i++, pace_vals++) {
6436 vals[i] = (1000 * *pace_vals + tick_ns / 2) / tick_ns;
6437 if (vals[i] > 0x7ff)
6439 if (*pace_vals && vals[i] == 0)
6442 for (i = 0; i < n; i++, start++)
6443 t4_write_reg(adap, A_TP_PACE_TABLE, (start << 16) | vals[i]);
6448 * t4_set_sched_bps - set the bit rate for a HW traffic scheduler
6449 * @adap: the adapter
6450 * @kbps: target rate in Kbps
6451 * @sched: the scheduler index
6453 * Configure a Tx HW scheduler for the target rate.
6455 int t4_set_sched_bps(struct adapter *adap, int sched, unsigned int kbps)
6457 unsigned int v, tps, cpt, bpt, delta, mindelta = ~0;
6458 unsigned int clk = adap->params.vpd.cclk * 1000;
6459 unsigned int selected_cpt = 0, selected_bpt = 0;
6462 kbps *= 125; /* -> bytes */
6463 for (cpt = 1; cpt <= 255; cpt++) {
6465 bpt = (kbps + tps / 2) / tps;
6466 if (bpt > 0 && bpt <= 255) {
6468 delta = v >= kbps ? v - kbps : kbps - v;
6469 if (delta < mindelta) {
6474 } else if (selected_cpt)
6480 t4_write_reg(adap, A_TP_TM_PIO_ADDR,
6481 A_TP_TX_MOD_Q1_Q0_RATE_LIMIT - sched / 2);
6482 v = t4_read_reg(adap, A_TP_TM_PIO_DATA);
6484 v = (v & 0xffff) | (selected_cpt << 16) | (selected_bpt << 24);
6486 v = (v & 0xffff0000) | selected_cpt | (selected_bpt << 8);
6487 t4_write_reg(adap, A_TP_TM_PIO_DATA, v);
6492 * t4_set_sched_ipg - set the IPG for a Tx HW packet rate scheduler
6493 * @adap: the adapter
6494 * @sched: the scheduler index
6495 * @ipg: the interpacket delay in tenths of nanoseconds
6497 * Set the interpacket delay for a HW packet rate scheduler.
6499 int t4_set_sched_ipg(struct adapter *adap, int sched, unsigned int ipg)
6501 unsigned int v, addr = A_TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR - sched / 2;
6503 /* convert ipg to nearest number of core clocks */
6504 ipg *= core_ticks_per_usec(adap);
6505 ipg = (ipg + 5000) / 10000;
6506 if (ipg > M_TXTIMERSEPQ0)
6509 t4_write_reg(adap, A_TP_TM_PIO_ADDR, addr);
6510 v = t4_read_reg(adap, A_TP_TM_PIO_DATA);
6512 v = (v & V_TXTIMERSEPQ0(M_TXTIMERSEPQ0)) | V_TXTIMERSEPQ1(ipg);
6514 v = (v & V_TXTIMERSEPQ1(M_TXTIMERSEPQ1)) | V_TXTIMERSEPQ0(ipg);
6515 t4_write_reg(adap, A_TP_TM_PIO_DATA, v);
6516 t4_read_reg(adap, A_TP_TM_PIO_DATA);
6521 * Calculates a rate in bytes/s given the number of 256-byte units per 4K core
6522 * clocks. The formula is
6524 * bytes/s = bytes256 * 256 * ClkFreq / 4096
6526 * which is equivalent to
6528 * bytes/s = 62.5 * bytes256 * ClkFreq_ms
6530 static u64 chan_rate(struct adapter *adap, unsigned int bytes256)
6532 u64 v = (u64)bytes256 * adap->params.vpd.cclk;
6534 return v * 62 + v / 2;
6538 * t4_get_chan_txrate - get the current per channel Tx rates
6539 * @adap: the adapter
6540 * @nic_rate: rates for NIC traffic
6541 * @ofld_rate: rates for offloaded traffic
6543 * Return the current Tx rates in bytes/s for NIC and offloaded traffic
6546 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate)
6550 v = t4_read_reg(adap, A_TP_TX_TRATE);
6551 nic_rate[0] = chan_rate(adap, G_TNLRATE0(v));
6552 nic_rate[1] = chan_rate(adap, G_TNLRATE1(v));
6553 if (adap->chip_params->nchan > 2) {
6554 nic_rate[2] = chan_rate(adap, G_TNLRATE2(v));
6555 nic_rate[3] = chan_rate(adap, G_TNLRATE3(v));
6558 v = t4_read_reg(adap, A_TP_TX_ORATE);
6559 ofld_rate[0] = chan_rate(adap, G_OFDRATE0(v));
6560 ofld_rate[1] = chan_rate(adap, G_OFDRATE1(v));
6561 if (adap->chip_params->nchan > 2) {
6562 ofld_rate[2] = chan_rate(adap, G_OFDRATE2(v));
6563 ofld_rate[3] = chan_rate(adap, G_OFDRATE3(v));
6568 * t4_set_trace_filter - configure one of the tracing filters
6569 * @adap: the adapter
6570 * @tp: the desired trace filter parameters
6571 * @idx: which filter to configure
6572 * @enable: whether to enable or disable the filter
6574 * Configures one of the tracing filters available in HW. If @tp is %NULL
6575 * it indicates that the filter is already written in the register and it
6576 * just needs to be enabled or disabled.
6578 int t4_set_trace_filter(struct adapter *adap, const struct trace_params *tp,
6579 int idx, int enable)
6581 int i, ofst = idx * 4;
6582 u32 data_reg, mask_reg, cfg;
6583 u32 multitrc = F_TRCMULTIFILTER;
6584 u32 en = is_t4(adap) ? F_TFEN : F_T5_TFEN;
6586 if (idx < 0 || idx >= NTRACE)
6589 if (tp == NULL || !enable) {
6590 t4_set_reg_field(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst, en,
6596 * TODO - After T4 data book is updated, specify the exact
6599 * See T4 data book - MPS section for a complete description
6600 * of the below if..else handling of A_MPS_TRC_CFG register
6603 cfg = t4_read_reg(adap, A_MPS_TRC_CFG);
6604 if (cfg & F_TRCMULTIFILTER) {
6606 * If multiple tracers are enabled, then maximum
6607 * capture size is 2.5KB (FIFO size of a single channel)
6608 * minus 2 flits for CPL_TRACE_PKT header.
6610 if (tp->snap_len > ((10 * 1024 / 4) - (2 * 8)))
6614 * If multiple tracers are disabled, to avoid deadlocks
6615 * maximum packet capture size of 9600 bytes is recommended.
6616 * Also in this mode, only trace0 can be enabled and running.
6619 if (tp->snap_len > 9600 || idx)
6623 if (tp->port > (is_t4(adap) ? 11 : 19) || tp->invert > 1 ||
6624 tp->skip_len > M_TFLENGTH || tp->skip_ofst > M_TFOFFSET ||
6625 tp->min_len > M_TFMINPKTSIZE)
6628 /* stop the tracer we'll be changing */
6629 t4_set_reg_field(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst, en, 0);
6631 idx *= (A_MPS_TRC_FILTER1_MATCH - A_MPS_TRC_FILTER0_MATCH);
6632 data_reg = A_MPS_TRC_FILTER0_MATCH + idx;
6633 mask_reg = A_MPS_TRC_FILTER0_DONT_CARE + idx;
6635 for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) {
6636 t4_write_reg(adap, data_reg, tp->data[i]);
6637 t4_write_reg(adap, mask_reg, ~tp->mask[i]);
6639 t4_write_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_B + ofst,
6640 V_TFCAPTUREMAX(tp->snap_len) |
6641 V_TFMINPKTSIZE(tp->min_len));
6642 t4_write_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst,
6643 V_TFOFFSET(tp->skip_ofst) | V_TFLENGTH(tp->skip_len) | en |
6645 V_TFPORT(tp->port) | V_TFINVERTMATCH(tp->invert) :
6646 V_T5_TFPORT(tp->port) | V_T5_TFINVERTMATCH(tp->invert)));
6652 * t4_get_trace_filter - query one of the tracing filters
6653 * @adap: the adapter
6654 * @tp: the current trace filter parameters
6655 * @idx: which trace filter to query
6656 * @enabled: non-zero if the filter is enabled
6658 * Returns the current settings of one of the HW tracing filters.
6660 void t4_get_trace_filter(struct adapter *adap, struct trace_params *tp, int idx,
6664 int i, ofst = idx * 4;
6665 u32 data_reg, mask_reg;
6667 ctla = t4_read_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst);
6668 ctlb = t4_read_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_B + ofst);
6671 *enabled = !!(ctla & F_TFEN);
6672 tp->port = G_TFPORT(ctla);
6673 tp->invert = !!(ctla & F_TFINVERTMATCH);
6675 *enabled = !!(ctla & F_T5_TFEN);
6676 tp->port = G_T5_TFPORT(ctla);
6677 tp->invert = !!(ctla & F_T5_TFINVERTMATCH);
6679 tp->snap_len = G_TFCAPTUREMAX(ctlb);
6680 tp->min_len = G_TFMINPKTSIZE(ctlb);
6681 tp->skip_ofst = G_TFOFFSET(ctla);
6682 tp->skip_len = G_TFLENGTH(ctla);
6684 ofst = (A_MPS_TRC_FILTER1_MATCH - A_MPS_TRC_FILTER0_MATCH) * idx;
6685 data_reg = A_MPS_TRC_FILTER0_MATCH + ofst;
6686 mask_reg = A_MPS_TRC_FILTER0_DONT_CARE + ofst;
6688 for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) {
6689 tp->mask[i] = ~t4_read_reg(adap, mask_reg);
6690 tp->data[i] = t4_read_reg(adap, data_reg) & tp->mask[i];
6695 * t4_pmtx_get_stats - returns the HW stats from PMTX
6696 * @adap: the adapter
6697 * @cnt: where to store the count statistics
6698 * @cycles: where to store the cycle statistics
6700 * Returns performance statistics from PMTX.
6702 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
6707 for (i = 0; i < adap->chip_params->pm_stats_cnt; i++) {
6708 t4_write_reg(adap, A_PM_TX_STAT_CONFIG, i + 1);
6709 cnt[i] = t4_read_reg(adap, A_PM_TX_STAT_COUNT);
6711 cycles[i] = t4_read_reg64(adap, A_PM_TX_STAT_LSB);
6713 t4_read_indirect(adap, A_PM_TX_DBG_CTRL,
6714 A_PM_TX_DBG_DATA, data, 2,
6715 A_PM_TX_DBG_STAT_MSB);
6716 cycles[i] = (((u64)data[0] << 32) | data[1]);
6722 * t4_pmrx_get_stats - returns the HW stats from PMRX
6723 * @adap: the adapter
6724 * @cnt: where to store the count statistics
6725 * @cycles: where to store the cycle statistics
6727 * Returns performance statistics from PMRX.
6729 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
6734 for (i = 0; i < adap->chip_params->pm_stats_cnt; i++) {
6735 t4_write_reg(adap, A_PM_RX_STAT_CONFIG, i + 1);
6736 cnt[i] = t4_read_reg(adap, A_PM_RX_STAT_COUNT);
6738 cycles[i] = t4_read_reg64(adap, A_PM_RX_STAT_LSB);
6740 t4_read_indirect(adap, A_PM_RX_DBG_CTRL,
6741 A_PM_RX_DBG_DATA, data, 2,
6742 A_PM_RX_DBG_STAT_MSB);
6743 cycles[i] = (((u64)data[0] << 32) | data[1]);
6749 * t4_get_mps_bg_map - return the buffer groups associated with a port
6750 * @adap: the adapter
6751 * @idx: the port index
6753 * Returns a bitmap indicating which MPS buffer groups are associated
6754 * with the given port. Bit i is set if buffer group i is used by the
6757 static unsigned int t4_get_mps_bg_map(struct adapter *adap, int idx)
6761 if (adap->params.mps_bg_map)
6762 return ((adap->params.mps_bg_map >> (idx << 3)) & 0xff);
6764 n = G_NUMPORTS(t4_read_reg(adap, A_MPS_CMN_CTL));
6766 return idx == 0 ? 0xf : 0;
6767 if (n == 1 && chip_id(adap) <= CHELSIO_T5)
6768 return idx < 2 ? (3 << (2 * idx)) : 0;
6773 * TP RX e-channels associated with the port.
6775 static unsigned int t4_get_rx_e_chan_map(struct adapter *adap, int idx)
6777 u32 n = G_NUMPORTS(t4_read_reg(adap, A_MPS_CMN_CTL));
6778 const u32 all_chan = (1 << adap->chip_params->nchan) - 1;
6781 return idx == 0 ? all_chan : 0;
6782 if (n == 1 && chip_id(adap) <= CHELSIO_T5)
6783 return idx < 2 ? (3 << (2 * idx)) : 0;
6788 * t4_get_port_type_description - return Port Type string description
6789 * @port_type: firmware Port Type enumeration
6791 const char *t4_get_port_type_description(enum fw_port_type port_type)
6793 static const char *const port_type_description[] = {
6818 if (port_type < ARRAY_SIZE(port_type_description))
6819 return port_type_description[port_type];
6824 * t4_get_port_stats_offset - collect port stats relative to a previous
6826 * @adap: The adapter
6828 * @stats: Current stats to fill
6829 * @offset: Previous stats snapshot
6831 void t4_get_port_stats_offset(struct adapter *adap, int idx,
6832 struct port_stats *stats,
6833 struct port_stats *offset)
6838 t4_get_port_stats(adap, idx, stats);
6839 for (i = 0, s = (u64 *)stats, o = (u64 *)offset ;
6840 i < (sizeof(struct port_stats)/sizeof(u64)) ;
6846 * t4_get_port_stats - collect port statistics
6847 * @adap: the adapter
6848 * @idx: the port index
6849 * @p: the stats structure to fill
6851 * Collect statistics related to the given port from HW.
6853 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p)
6855 struct port_info *pi = adap->port[idx];
6856 u32 bgmap = pi->mps_bg_map;
6857 u32 stat_ctl = t4_read_reg(adap, A_MPS_STAT_CTL);
6859 #define GET_STAT(name) \
6860 t4_read_reg64(adap, \
6861 (is_t4(adap) ? PORT_REG(idx, A_MPS_PORT_STAT_##name##_L) : \
6862 T5_PORT_REG(idx, A_MPS_PORT_STAT_##name##_L)))
6863 #define GET_STAT_COM(name) t4_read_reg64(adap, A_MPS_STAT_##name##_L)
6865 p->tx_pause = GET_STAT(TX_PORT_PAUSE);
6866 p->tx_octets = GET_STAT(TX_PORT_BYTES);
6867 p->tx_frames = GET_STAT(TX_PORT_FRAMES);
6868 p->tx_bcast_frames = GET_STAT(TX_PORT_BCAST);
6869 p->tx_mcast_frames = GET_STAT(TX_PORT_MCAST);
6870 p->tx_ucast_frames = GET_STAT(TX_PORT_UCAST);
6871 p->tx_error_frames = GET_STAT(TX_PORT_ERROR);
6872 p->tx_frames_64 = GET_STAT(TX_PORT_64B);
6873 p->tx_frames_65_127 = GET_STAT(TX_PORT_65B_127B);
6874 p->tx_frames_128_255 = GET_STAT(TX_PORT_128B_255B);
6875 p->tx_frames_256_511 = GET_STAT(TX_PORT_256B_511B);
6876 p->tx_frames_512_1023 = GET_STAT(TX_PORT_512B_1023B);
6877 p->tx_frames_1024_1518 = GET_STAT(TX_PORT_1024B_1518B);
6878 p->tx_frames_1519_max = GET_STAT(TX_PORT_1519B_MAX);
6879 p->tx_drop = GET_STAT(TX_PORT_DROP);
6880 p->tx_ppp0 = GET_STAT(TX_PORT_PPP0);
6881 p->tx_ppp1 = GET_STAT(TX_PORT_PPP1);
6882 p->tx_ppp2 = GET_STAT(TX_PORT_PPP2);
6883 p->tx_ppp3 = GET_STAT(TX_PORT_PPP3);
6884 p->tx_ppp4 = GET_STAT(TX_PORT_PPP4);
6885 p->tx_ppp5 = GET_STAT(TX_PORT_PPP5);
6886 p->tx_ppp6 = GET_STAT(TX_PORT_PPP6);
6887 p->tx_ppp7 = GET_STAT(TX_PORT_PPP7);
6889 if (chip_id(adap) >= CHELSIO_T5) {
6890 if (stat_ctl & F_COUNTPAUSESTATTX) {
6891 p->tx_frames -= p->tx_pause;
6892 p->tx_octets -= p->tx_pause * 64;
6894 if (stat_ctl & F_COUNTPAUSEMCTX)
6895 p->tx_mcast_frames -= p->tx_pause;
6898 p->rx_pause = GET_STAT(RX_PORT_PAUSE);
6899 p->rx_octets = GET_STAT(RX_PORT_BYTES);
6900 p->rx_frames = GET_STAT(RX_PORT_FRAMES);
6901 p->rx_bcast_frames = GET_STAT(RX_PORT_BCAST);
6902 p->rx_mcast_frames = GET_STAT(RX_PORT_MCAST);
6903 p->rx_ucast_frames = GET_STAT(RX_PORT_UCAST);
6904 p->rx_too_long = GET_STAT(RX_PORT_MTU_ERROR);
6905 p->rx_jabber = GET_STAT(RX_PORT_MTU_CRC_ERROR);
6906 p->rx_len_err = GET_STAT(RX_PORT_LEN_ERROR);
6907 p->rx_symbol_err = GET_STAT(RX_PORT_SYM_ERROR);
6908 p->rx_runt = GET_STAT(RX_PORT_LESS_64B);
6909 p->rx_frames_64 = GET_STAT(RX_PORT_64B);
6910 p->rx_frames_65_127 = GET_STAT(RX_PORT_65B_127B);
6911 p->rx_frames_128_255 = GET_STAT(RX_PORT_128B_255B);
6912 p->rx_frames_256_511 = GET_STAT(RX_PORT_256B_511B);
6913 p->rx_frames_512_1023 = GET_STAT(RX_PORT_512B_1023B);
6914 p->rx_frames_1024_1518 = GET_STAT(RX_PORT_1024B_1518B);
6915 p->rx_frames_1519_max = GET_STAT(RX_PORT_1519B_MAX);
6916 p->rx_ppp0 = GET_STAT(RX_PORT_PPP0);
6917 p->rx_ppp1 = GET_STAT(RX_PORT_PPP1);
6918 p->rx_ppp2 = GET_STAT(RX_PORT_PPP2);
6919 p->rx_ppp3 = GET_STAT(RX_PORT_PPP3);
6920 p->rx_ppp4 = GET_STAT(RX_PORT_PPP4);
6921 p->rx_ppp5 = GET_STAT(RX_PORT_PPP5);
6922 p->rx_ppp6 = GET_STAT(RX_PORT_PPP6);
6923 p->rx_ppp7 = GET_STAT(RX_PORT_PPP7);
6925 if (pi->fcs_reg != -1)
6926 p->rx_fcs_err = t4_read_reg64(adap, pi->fcs_reg) - pi->fcs_base;
6928 if (chip_id(adap) >= CHELSIO_T5) {
6929 if (stat_ctl & F_COUNTPAUSESTATRX) {
6930 p->rx_frames -= p->rx_pause;
6931 p->rx_octets -= p->rx_pause * 64;
6933 if (stat_ctl & F_COUNTPAUSEMCRX)
6934 p->rx_mcast_frames -= p->rx_pause;
6937 p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0;
6938 p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0;
6939 p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0;
6940 p->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0;
6941 p->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0;
6942 p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0;
6943 p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0;
6944 p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0;
6951 * t4_get_lb_stats - collect loopback port statistics
6952 * @adap: the adapter
6953 * @idx: the loopback port index
6954 * @p: the stats structure to fill
6956 * Return HW statistics for the given loopback port.
6958 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p)
6961 #define GET_STAT(name) \
6962 t4_read_reg64(adap, \
6964 PORT_REG(idx, A_MPS_PORT_STAT_LB_PORT_##name##_L) : \
6965 T5_PORT_REG(idx, A_MPS_PORT_STAT_LB_PORT_##name##_L)))
6966 #define GET_STAT_COM(name) t4_read_reg64(adap, A_MPS_STAT_##name##_L)
6968 p->octets = GET_STAT(BYTES);
6969 p->frames = GET_STAT(FRAMES);
6970 p->bcast_frames = GET_STAT(BCAST);
6971 p->mcast_frames = GET_STAT(MCAST);
6972 p->ucast_frames = GET_STAT(UCAST);
6973 p->error_frames = GET_STAT(ERROR);
6975 p->frames_64 = GET_STAT(64B);
6976 p->frames_65_127 = GET_STAT(65B_127B);
6977 p->frames_128_255 = GET_STAT(128B_255B);
6978 p->frames_256_511 = GET_STAT(256B_511B);
6979 p->frames_512_1023 = GET_STAT(512B_1023B);
6980 p->frames_1024_1518 = GET_STAT(1024B_1518B);
6981 p->frames_1519_max = GET_STAT(1519B_MAX);
6982 p->drop = GET_STAT(DROP_FRAMES);
6984 if (idx < adap->params.nports) {
6985 u32 bg = adap2pinfo(adap, idx)->mps_bg_map;
6987 p->ovflow0 = (bg & 1) ? GET_STAT_COM(RX_BG_0_LB_DROP_FRAME) : 0;
6988 p->ovflow1 = (bg & 2) ? GET_STAT_COM(RX_BG_1_LB_DROP_FRAME) : 0;
6989 p->ovflow2 = (bg & 4) ? GET_STAT_COM(RX_BG_2_LB_DROP_FRAME) : 0;
6990 p->ovflow3 = (bg & 8) ? GET_STAT_COM(RX_BG_3_LB_DROP_FRAME) : 0;
6991 p->trunc0 = (bg & 1) ? GET_STAT_COM(RX_BG_0_LB_TRUNC_FRAME) : 0;
6992 p->trunc1 = (bg & 2) ? GET_STAT_COM(RX_BG_1_LB_TRUNC_FRAME) : 0;
6993 p->trunc2 = (bg & 4) ? GET_STAT_COM(RX_BG_2_LB_TRUNC_FRAME) : 0;
6994 p->trunc3 = (bg & 8) ? GET_STAT_COM(RX_BG_3_LB_TRUNC_FRAME) : 0;
7002 * t4_wol_magic_enable - enable/disable magic packet WoL
7003 * @adap: the adapter
7004 * @port: the physical port index
7005 * @addr: MAC address expected in magic packets, %NULL to disable
7007 * Enables/disables magic packet wake-on-LAN for the selected port.
7009 void t4_wol_magic_enable(struct adapter *adap, unsigned int port,
7012 u32 mag_id_reg_l, mag_id_reg_h, port_cfg_reg;
7015 mag_id_reg_l = PORT_REG(port, A_XGMAC_PORT_MAGIC_MACID_LO);
7016 mag_id_reg_h = PORT_REG(port, A_XGMAC_PORT_MAGIC_MACID_HI);
7017 port_cfg_reg = PORT_REG(port, A_XGMAC_PORT_CFG2);
7019 mag_id_reg_l = T5_PORT_REG(port, A_MAC_PORT_MAGIC_MACID_LO);
7020 mag_id_reg_h = T5_PORT_REG(port, A_MAC_PORT_MAGIC_MACID_HI);
7021 port_cfg_reg = T5_PORT_REG(port, A_MAC_PORT_CFG2);
7025 t4_write_reg(adap, mag_id_reg_l,
7026 (addr[2] << 24) | (addr[3] << 16) |
7027 (addr[4] << 8) | addr[5]);
7028 t4_write_reg(adap, mag_id_reg_h,
7029 (addr[0] << 8) | addr[1]);
7031 t4_set_reg_field(adap, port_cfg_reg, F_MAGICEN,
7032 V_MAGICEN(addr != NULL));
7036 * t4_wol_pat_enable - enable/disable pattern-based WoL
7037 * @adap: the adapter
7038 * @port: the physical port index
7039 * @map: bitmap of which HW pattern filters to set
7040 * @mask0: byte mask for bytes 0-63 of a packet
7041 * @mask1: byte mask for bytes 64-127 of a packet
7042 * @crc: Ethernet CRC for selected bytes
7043 * @enable: enable/disable switch
7045 * Sets the pattern filters indicated in @map to mask out the bytes
7046 * specified in @mask0/@mask1 in received packets and compare the CRC of
7047 * the resulting packet against @crc. If @enable is %true pattern-based
7048 * WoL is enabled, otherwise disabled.
7050 int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map,
7051 u64 mask0, u64 mask1, unsigned int crc, bool enable)
7057 port_cfg_reg = PORT_REG(port, A_XGMAC_PORT_CFG2);
7059 port_cfg_reg = T5_PORT_REG(port, A_MAC_PORT_CFG2);
7062 t4_set_reg_field(adap, port_cfg_reg, F_PATEN, 0);
7068 #define EPIO_REG(name) \
7069 (is_t4(adap) ? PORT_REG(port, A_XGMAC_PORT_EPIO_##name) : \
7070 T5_PORT_REG(port, A_MAC_PORT_EPIO_##name))
7072 t4_write_reg(adap, EPIO_REG(DATA1), mask0 >> 32);
7073 t4_write_reg(adap, EPIO_REG(DATA2), mask1);
7074 t4_write_reg(adap, EPIO_REG(DATA3), mask1 >> 32);
7076 for (i = 0; i < NWOL_PAT; i++, map >>= 1) {
7080 /* write byte masks */
7081 t4_write_reg(adap, EPIO_REG(DATA0), mask0);
7082 t4_write_reg(adap, EPIO_REG(OP), V_ADDRESS(i) | F_EPIOWR);
7083 t4_read_reg(adap, EPIO_REG(OP)); /* flush */
7084 if (t4_read_reg(adap, EPIO_REG(OP)) & F_BUSY)
7088 t4_write_reg(adap, EPIO_REG(DATA0), crc);
7089 t4_write_reg(adap, EPIO_REG(OP), V_ADDRESS(i + 32) | F_EPIOWR);
7090 t4_read_reg(adap, EPIO_REG(OP)); /* flush */
7091 if (t4_read_reg(adap, EPIO_REG(OP)) & F_BUSY)
7096 t4_set_reg_field(adap, port_cfg_reg, 0, F_PATEN);
7100 /* t4_mk_filtdelwr - create a delete filter WR
7101 * @ftid: the filter ID
7102 * @wr: the filter work request to populate
7103 * @qid: ingress queue to receive the delete notification
7105 * Creates a filter work request to delete the supplied filter. If @qid is
7106 * negative the delete notification is suppressed.
7108 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid)
7110 memset(wr, 0, sizeof(*wr));
7111 wr->op_pkd = cpu_to_be32(V_FW_WR_OP(FW_FILTER_WR));
7112 wr->len16_pkd = cpu_to_be32(V_FW_WR_LEN16(sizeof(*wr) / 16));
7113 wr->tid_to_iq = cpu_to_be32(V_FW_FILTER_WR_TID(ftid) |
7114 V_FW_FILTER_WR_NOREPLY(qid < 0));
7115 wr->del_filter_to_l2tix = cpu_to_be32(F_FW_FILTER_WR_DEL_FILTER);
7117 wr->rx_chan_rx_rpl_iq =
7118 cpu_to_be16(V_FW_FILTER_WR_RX_RPL_IQ(qid));
7121 #define INIT_CMD(var, cmd, rd_wr) do { \
7122 (var).op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_##cmd##_CMD) | \
7123 F_FW_CMD_REQUEST | \
7124 F_FW_CMD_##rd_wr); \
7125 (var).retval_len16 = cpu_to_be32(FW_LEN16(var)); \
7128 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
7132 struct fw_ldst_cmd c;
7134 memset(&c, 0, sizeof(c));
7135 ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_FIRMWARE);
7136 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
7140 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
7141 c.u.addrval.addr = cpu_to_be32(addr);
7142 c.u.addrval.val = cpu_to_be32(val);
7144 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7148 * t4_mdio_rd - read a PHY register through MDIO
7149 * @adap: the adapter
7150 * @mbox: mailbox to use for the FW command
7151 * @phy_addr: the PHY address
7152 * @mmd: the PHY MMD to access (0 for clause 22 PHYs)
7153 * @reg: the register to read
7154 * @valp: where to store the value
7156 * Issues a FW command through the given mailbox to read a PHY register.
7158 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
7159 unsigned int mmd, unsigned int reg, unsigned int *valp)
7163 struct fw_ldst_cmd c;
7165 memset(&c, 0, sizeof(c));
7166 ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MDIO);
7167 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
7168 F_FW_CMD_REQUEST | F_FW_CMD_READ |
7170 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
7171 c.u.mdio.paddr_mmd = cpu_to_be16(V_FW_LDST_CMD_PADDR(phy_addr) |
7172 V_FW_LDST_CMD_MMD(mmd));
7173 c.u.mdio.raddr = cpu_to_be16(reg);
7175 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
7177 *valp = be16_to_cpu(c.u.mdio.rval);
7182 * t4_mdio_wr - write a PHY register through MDIO
7183 * @adap: the adapter
7184 * @mbox: mailbox to use for the FW command
7185 * @phy_addr: the PHY address
7186 * @mmd: the PHY MMD to access (0 for clause 22 PHYs)
7187 * @reg: the register to write
7188 * @valp: value to write
7190 * Issues a FW command through the given mailbox to write a PHY register.
7192 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
7193 unsigned int mmd, unsigned int reg, unsigned int val)
7196 struct fw_ldst_cmd c;
7198 memset(&c, 0, sizeof(c));
7199 ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MDIO);
7200 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
7201 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
7203 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
7204 c.u.mdio.paddr_mmd = cpu_to_be16(V_FW_LDST_CMD_PADDR(phy_addr) |
7205 V_FW_LDST_CMD_MMD(mmd));
7206 c.u.mdio.raddr = cpu_to_be16(reg);
7207 c.u.mdio.rval = cpu_to_be16(val);
7209 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7214 * t4_sge_decode_idma_state - decode the idma state
7215 * @adap: the adapter
7216 * @state: the state idma is stuck in
7218 void t4_sge_decode_idma_state(struct adapter *adapter, int state)
7220 static const char * const t4_decode[] = {
7222 "IDMA_PUSH_MORE_CPL_FIFO",
7223 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
7225 "IDMA_PHYSADDR_SEND_PCIEHDR",
7226 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
7227 "IDMA_PHYSADDR_SEND_PAYLOAD",
7228 "IDMA_SEND_FIFO_TO_IMSG",
7229 "IDMA_FL_REQ_DATA_FL_PREP",
7230 "IDMA_FL_REQ_DATA_FL",
7232 "IDMA_FL_H_REQ_HEADER_FL",
7233 "IDMA_FL_H_SEND_PCIEHDR",
7234 "IDMA_FL_H_PUSH_CPL_FIFO",
7235 "IDMA_FL_H_SEND_CPL",
7236 "IDMA_FL_H_SEND_IP_HDR_FIRST",
7237 "IDMA_FL_H_SEND_IP_HDR",
7238 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
7239 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
7240 "IDMA_FL_H_SEND_IP_HDR_PADDING",
7241 "IDMA_FL_D_SEND_PCIEHDR",
7242 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
7243 "IDMA_FL_D_REQ_NEXT_DATA_FL",
7244 "IDMA_FL_SEND_PCIEHDR",
7245 "IDMA_FL_PUSH_CPL_FIFO",
7247 "IDMA_FL_SEND_PAYLOAD_FIRST",
7248 "IDMA_FL_SEND_PAYLOAD",
7249 "IDMA_FL_REQ_NEXT_DATA_FL",
7250 "IDMA_FL_SEND_NEXT_PCIEHDR",
7251 "IDMA_FL_SEND_PADDING",
7252 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
7253 "IDMA_FL_SEND_FIFO_TO_IMSG",
7254 "IDMA_FL_REQ_DATAFL_DONE",
7255 "IDMA_FL_REQ_HEADERFL_DONE",
7257 static const char * const t5_decode[] = {
7260 "IDMA_PUSH_MORE_CPL_FIFO",
7261 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
7262 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
7263 "IDMA_PHYSADDR_SEND_PCIEHDR",
7264 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
7265 "IDMA_PHYSADDR_SEND_PAYLOAD",
7266 "IDMA_SEND_FIFO_TO_IMSG",
7267 "IDMA_FL_REQ_DATA_FL",
7269 "IDMA_FL_DROP_SEND_INC",
7270 "IDMA_FL_H_REQ_HEADER_FL",
7271 "IDMA_FL_H_SEND_PCIEHDR",
7272 "IDMA_FL_H_PUSH_CPL_FIFO",
7273 "IDMA_FL_H_SEND_CPL",
7274 "IDMA_FL_H_SEND_IP_HDR_FIRST",
7275 "IDMA_FL_H_SEND_IP_HDR",
7276 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
7277 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
7278 "IDMA_FL_H_SEND_IP_HDR_PADDING",
7279 "IDMA_FL_D_SEND_PCIEHDR",
7280 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
7281 "IDMA_FL_D_REQ_NEXT_DATA_FL",
7282 "IDMA_FL_SEND_PCIEHDR",
7283 "IDMA_FL_PUSH_CPL_FIFO",
7285 "IDMA_FL_SEND_PAYLOAD_FIRST",
7286 "IDMA_FL_SEND_PAYLOAD",
7287 "IDMA_FL_REQ_NEXT_DATA_FL",
7288 "IDMA_FL_SEND_NEXT_PCIEHDR",
7289 "IDMA_FL_SEND_PADDING",
7290 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
7292 static const char * const t6_decode[] = {
7294 "IDMA_PUSH_MORE_CPL_FIFO",
7295 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
7296 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
7297 "IDMA_PHYSADDR_SEND_PCIEHDR",
7298 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
7299 "IDMA_PHYSADDR_SEND_PAYLOAD",
7300 "IDMA_FL_REQ_DATA_FL",
7302 "IDMA_FL_DROP_SEND_INC",
7303 "IDMA_FL_H_REQ_HEADER_FL",
7304 "IDMA_FL_H_SEND_PCIEHDR",
7305 "IDMA_FL_H_PUSH_CPL_FIFO",
7306 "IDMA_FL_H_SEND_CPL",
7307 "IDMA_FL_H_SEND_IP_HDR_FIRST",
7308 "IDMA_FL_H_SEND_IP_HDR",
7309 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
7310 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
7311 "IDMA_FL_H_SEND_IP_HDR_PADDING",
7312 "IDMA_FL_D_SEND_PCIEHDR",
7313 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
7314 "IDMA_FL_D_REQ_NEXT_DATA_FL",
7315 "IDMA_FL_SEND_PCIEHDR",
7316 "IDMA_FL_PUSH_CPL_FIFO",
7318 "IDMA_FL_SEND_PAYLOAD_FIRST",
7319 "IDMA_FL_SEND_PAYLOAD",
7320 "IDMA_FL_REQ_NEXT_DATA_FL",
7321 "IDMA_FL_SEND_NEXT_PCIEHDR",
7322 "IDMA_FL_SEND_PADDING",
7323 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
7325 static const u32 sge_regs[] = {
7326 A_SGE_DEBUG_DATA_LOW_INDEX_2,
7327 A_SGE_DEBUG_DATA_LOW_INDEX_3,
7328 A_SGE_DEBUG_DATA_HIGH_INDEX_10,
7330 const char * const *sge_idma_decode;
7331 int sge_idma_decode_nstates;
7333 unsigned int chip_version = chip_id(adapter);
7335 /* Select the right set of decode strings to dump depending on the
7336 * adapter chip type.
7338 switch (chip_version) {
7340 sge_idma_decode = (const char * const *)t4_decode;
7341 sge_idma_decode_nstates = ARRAY_SIZE(t4_decode);
7345 sge_idma_decode = (const char * const *)t5_decode;
7346 sge_idma_decode_nstates = ARRAY_SIZE(t5_decode);
7350 sge_idma_decode = (const char * const *)t6_decode;
7351 sge_idma_decode_nstates = ARRAY_SIZE(t6_decode);
7355 CH_ERR(adapter, "Unsupported chip version %d\n", chip_version);
7359 if (state < sge_idma_decode_nstates)
7360 CH_WARN(adapter, "idma state %s\n", sge_idma_decode[state]);
7362 CH_WARN(adapter, "idma state %d unknown\n", state);
7364 for (i = 0; i < ARRAY_SIZE(sge_regs); i++)
7365 CH_WARN(adapter, "SGE register %#x value %#x\n",
7366 sge_regs[i], t4_read_reg(adapter, sge_regs[i]));
7370 * t4_sge_ctxt_flush - flush the SGE context cache
7371 * @adap: the adapter
7372 * @mbox: mailbox to use for the FW command
7374 * Issues a FW command through the given mailbox to flush the
7375 * SGE context cache.
7377 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox, int ctxt_type)
7381 struct fw_ldst_cmd c;
7383 memset(&c, 0, sizeof(c));
7384 ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(ctxt_type == CTXT_EGRESS ?
7385 FW_LDST_ADDRSPC_SGE_EGRC :
7386 FW_LDST_ADDRSPC_SGE_INGC);
7387 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
7388 F_FW_CMD_REQUEST | F_FW_CMD_READ |
7390 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
7391 c.u.idctxt.msg_ctxtflush = cpu_to_be32(F_FW_LDST_CMD_CTXTFLUSH);
7393 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
7398 * t4_fw_hello - establish communication with FW
7399 * @adap: the adapter
7400 * @mbox: mailbox to use for the FW command
7401 * @evt_mbox: mailbox to receive async FW events
7402 * @master: specifies the caller's willingness to be the device master
7403 * @state: returns the current device state (if non-NULL)
7405 * Issues a command to establish communication with FW. Returns either
7406 * an error (negative integer) or the mailbox of the Master PF.
7408 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
7409 enum dev_master master, enum dev_state *state)
7412 struct fw_hello_cmd c;
7414 unsigned int master_mbox;
7415 int retries = FW_CMD_HELLO_RETRIES;
7418 memset(&c, 0, sizeof(c));
7419 INIT_CMD(c, HELLO, WRITE);
7420 c.err_to_clearinit = cpu_to_be32(
7421 V_FW_HELLO_CMD_MASTERDIS(master == MASTER_CANT) |
7422 V_FW_HELLO_CMD_MASTERFORCE(master == MASTER_MUST) |
7423 V_FW_HELLO_CMD_MBMASTER(master == MASTER_MUST ?
7424 mbox : M_FW_HELLO_CMD_MBMASTER) |
7425 V_FW_HELLO_CMD_MBASYNCNOT(evt_mbox) |
7426 V_FW_HELLO_CMD_STAGE(FW_HELLO_CMD_STAGE_OS) |
7427 F_FW_HELLO_CMD_CLEARINIT);
7430 * Issue the HELLO command to the firmware. If it's not successful
7431 * but indicates that we got a "busy" or "timeout" condition, retry
7432 * the HELLO until we exhaust our retry limit. If we do exceed our
7433 * retry limit, check to see if the firmware left us any error
7434 * information and report that if so ...
7436 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
7437 if (ret != FW_SUCCESS) {
7438 if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0)
7440 if (t4_read_reg(adap, A_PCIE_FW) & F_PCIE_FW_ERR)
7441 t4_report_fw_error(adap);
7445 v = be32_to_cpu(c.err_to_clearinit);
7446 master_mbox = G_FW_HELLO_CMD_MBMASTER(v);
7448 if (v & F_FW_HELLO_CMD_ERR)
7449 *state = DEV_STATE_ERR;
7450 else if (v & F_FW_HELLO_CMD_INIT)
7451 *state = DEV_STATE_INIT;
7453 *state = DEV_STATE_UNINIT;
7457 * If we're not the Master PF then we need to wait around for the
7458 * Master PF Driver to finish setting up the adapter.
7460 * Note that we also do this wait if we're a non-Master-capable PF and
7461 * there is no current Master PF; a Master PF may show up momentarily
7462 * and we wouldn't want to fail pointlessly. (This can happen when an
7463 * OS loads lots of different drivers rapidly at the same time). In
7464 * this case, the Master PF returned by the firmware will be
7465 * M_PCIE_FW_MASTER so the test below will work ...
7467 if ((v & (F_FW_HELLO_CMD_ERR|F_FW_HELLO_CMD_INIT)) == 0 &&
7468 master_mbox != mbox) {
7469 int waiting = FW_CMD_HELLO_TIMEOUT;
7472 * Wait for the firmware to either indicate an error or
7473 * initialized state. If we see either of these we bail out
7474 * and report the issue to the caller. If we exhaust the
7475 * "hello timeout" and we haven't exhausted our retries, try
7476 * again. Otherwise bail with a timeout error.
7485 * If neither Error nor Initialialized are indicated
7486 * by the firmware keep waiting till we exhaust our
7487 * timeout ... and then retry if we haven't exhausted
7490 pcie_fw = t4_read_reg(adap, A_PCIE_FW);
7491 if (!(pcie_fw & (F_PCIE_FW_ERR|F_PCIE_FW_INIT))) {
7502 * We either have an Error or Initialized condition
7503 * report errors preferentially.
7506 if (pcie_fw & F_PCIE_FW_ERR)
7507 *state = DEV_STATE_ERR;
7508 else if (pcie_fw & F_PCIE_FW_INIT)
7509 *state = DEV_STATE_INIT;
7513 * If we arrived before a Master PF was selected and
7514 * there's not a valid Master PF, grab its identity
7517 if (master_mbox == M_PCIE_FW_MASTER &&
7518 (pcie_fw & F_PCIE_FW_MASTER_VLD))
7519 master_mbox = G_PCIE_FW_MASTER(pcie_fw);
7528 * t4_fw_bye - end communication with FW
7529 * @adap: the adapter
7530 * @mbox: mailbox to use for the FW command
7532 * Issues a command to terminate communication with FW.
7534 int t4_fw_bye(struct adapter *adap, unsigned int mbox)
7536 struct fw_bye_cmd c;
7538 memset(&c, 0, sizeof(c));
7539 INIT_CMD(c, BYE, WRITE);
7540 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7544 * t4_fw_reset - issue a reset to FW
7545 * @adap: the adapter
7546 * @mbox: mailbox to use for the FW command
7547 * @reset: specifies the type of reset to perform
7549 * Issues a reset command of the specified type to FW.
7551 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset)
7553 struct fw_reset_cmd c;
7555 memset(&c, 0, sizeof(c));
7556 INIT_CMD(c, RESET, WRITE);
7557 c.val = cpu_to_be32(reset);
7558 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7562 * t4_fw_halt - issue a reset/halt to FW and put uP into RESET
7563 * @adap: the adapter
7564 * @mbox: mailbox to use for the FW RESET command (if desired)
7565 * @force: force uP into RESET even if FW RESET command fails
7567 * Issues a RESET command to firmware (if desired) with a HALT indication
7568 * and then puts the microprocessor into RESET state. The RESET command
7569 * will only be issued if a legitimate mailbox is provided (mbox <=
7570 * M_PCIE_FW_MASTER).
7572 * This is generally used in order for the host to safely manipulate the
7573 * adapter without fear of conflicting with whatever the firmware might
7574 * be doing. The only way out of this state is to RESTART the firmware
7577 int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force)
7582 * If a legitimate mailbox is provided, issue a RESET command
7583 * with a HALT indication.
7585 if (adap->flags & FW_OK && mbox <= M_PCIE_FW_MASTER) {
7586 struct fw_reset_cmd c;
7588 memset(&c, 0, sizeof(c));
7589 INIT_CMD(c, RESET, WRITE);
7590 c.val = cpu_to_be32(F_PIORST | F_PIORSTMODE);
7591 c.halt_pkd = cpu_to_be32(F_FW_RESET_CMD_HALT);
7592 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7596 * Normally we won't complete the operation if the firmware RESET
7597 * command fails but if our caller insists we'll go ahead and put the
7598 * uP into RESET. This can be useful if the firmware is hung or even
7599 * missing ... We'll have to take the risk of putting the uP into
7600 * RESET without the cooperation of firmware in that case.
7602 * We also force the firmware's HALT flag to be on in case we bypassed
7603 * the firmware RESET command above or we're dealing with old firmware
7604 * which doesn't have the HALT capability. This will serve as a flag
7605 * for the incoming firmware to know that it's coming out of a HALT
7606 * rather than a RESET ... if it's new enough to understand that ...
7608 if (ret == 0 || force) {
7609 t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, F_UPCRST);
7610 t4_set_reg_field(adap, A_PCIE_FW, F_PCIE_FW_HALT,
7615 * And we always return the result of the firmware RESET command
7616 * even when we force the uP into RESET ...
7622 * t4_fw_restart - restart the firmware by taking the uP out of RESET
7623 * @adap: the adapter
7625 * Restart firmware previously halted by t4_fw_halt(). On successful
7626 * return the previous PF Master remains as the new PF Master and there
7627 * is no need to issue a new HELLO command, etc.
7629 int t4_fw_restart(struct adapter *adap, unsigned int mbox)
7633 t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, 0);
7634 for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) {
7635 if (!(t4_read_reg(adap, A_PCIE_FW) & F_PCIE_FW_HALT))
7645 * t4_fw_upgrade - perform all of the steps necessary to upgrade FW
7646 * @adap: the adapter
7647 * @mbox: mailbox to use for the FW RESET command (if desired)
7648 * @fw_data: the firmware image to write
7650 * @force: force upgrade even if firmware doesn't cooperate
7652 * Perform all of the steps necessary for upgrading an adapter's
7653 * firmware image. Normally this requires the cooperation of the
7654 * existing firmware in order to halt all existing activities
7655 * but if an invalid mailbox token is passed in we skip that step
7656 * (though we'll still put the adapter microprocessor into RESET in
7659 * On successful return the new firmware will have been loaded and
7660 * the adapter will have been fully RESET losing all previous setup
7661 * state. On unsuccessful return the adapter may be completely hosed ...
7662 * positive errno indicates that the adapter is ~probably~ intact, a
7663 * negative errno indicates that things are looking bad ...
7665 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
7666 const u8 *fw_data, unsigned int size, int force)
7668 const struct fw_hdr *fw_hdr = (const struct fw_hdr *)fw_data;
7669 unsigned int bootstrap =
7670 be32_to_cpu(fw_hdr->magic) == FW_HDR_MAGIC_BOOTSTRAP;
7673 if (!t4_fw_matches_chip(adap, fw_hdr))
7677 ret = t4_fw_halt(adap, mbox, force);
7678 if (ret < 0 && !force)
7682 ret = t4_load_fw(adap, fw_data, size);
7683 if (ret < 0 || bootstrap)
7686 return t4_fw_restart(adap, mbox);
7690 * t4_fw_initialize - ask FW to initialize the device
7691 * @adap: the adapter
7692 * @mbox: mailbox to use for the FW command
7694 * Issues a command to FW to partially initialize the device. This
7695 * performs initialization that generally doesn't depend on user input.
7697 int t4_fw_initialize(struct adapter *adap, unsigned int mbox)
7699 struct fw_initialize_cmd c;
7701 memset(&c, 0, sizeof(c));
7702 INIT_CMD(c, INITIALIZE, WRITE);
7703 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7707 * t4_query_params_rw - query FW or device parameters
7708 * @adap: the adapter
7709 * @mbox: mailbox to use for the FW command
7712 * @nparams: the number of parameters
7713 * @params: the parameter names
7714 * @val: the parameter values
7715 * @rw: Write and read flag
7717 * Reads the value of FW or device parameters. Up to 7 parameters can be
7720 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf,
7721 unsigned int vf, unsigned int nparams, const u32 *params,
7725 struct fw_params_cmd c;
7726 __be32 *p = &c.param[0].mnem;
7731 memset(&c, 0, sizeof(c));
7732 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) |
7733 F_FW_CMD_REQUEST | F_FW_CMD_READ |
7734 V_FW_PARAMS_CMD_PFN(pf) |
7735 V_FW_PARAMS_CMD_VFN(vf));
7736 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
7738 for (i = 0; i < nparams; i++) {
7739 *p++ = cpu_to_be32(*params++);
7741 *p = cpu_to_be32(*(val + i));
7745 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
7747 for (i = 0, p = &c.param[0].val; i < nparams; i++, p += 2)
7748 *val++ = be32_to_cpu(*p);
7752 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
7753 unsigned int vf, unsigned int nparams, const u32 *params,
7756 return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0);
7760 * t4_set_params_timeout - sets FW or device parameters
7761 * @adap: the adapter
7762 * @mbox: mailbox to use for the FW command
7765 * @nparams: the number of parameters
7766 * @params: the parameter names
7767 * @val: the parameter values
7768 * @timeout: the timeout time
7770 * Sets the value of FW or device parameters. Up to 7 parameters can be
7771 * specified at once.
7773 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
7774 unsigned int pf, unsigned int vf,
7775 unsigned int nparams, const u32 *params,
7776 const u32 *val, int timeout)
7778 struct fw_params_cmd c;
7779 __be32 *p = &c.param[0].mnem;
7784 memset(&c, 0, sizeof(c));
7785 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) |
7786 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
7787 V_FW_PARAMS_CMD_PFN(pf) |
7788 V_FW_PARAMS_CMD_VFN(vf));
7789 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
7792 *p++ = cpu_to_be32(*params++);
7793 *p++ = cpu_to_be32(*val++);
7796 return t4_wr_mbox_timeout(adap, mbox, &c, sizeof(c), NULL, timeout);
7800 * t4_set_params - sets FW or device parameters
7801 * @adap: the adapter
7802 * @mbox: mailbox to use for the FW command
7805 * @nparams: the number of parameters
7806 * @params: the parameter names
7807 * @val: the parameter values
7809 * Sets the value of FW or device parameters. Up to 7 parameters can be
7810 * specified at once.
7812 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
7813 unsigned int vf, unsigned int nparams, const u32 *params,
7816 return t4_set_params_timeout(adap, mbox, pf, vf, nparams, params, val,
7817 FW_CMD_MAX_TIMEOUT);
7821 * t4_cfg_pfvf - configure PF/VF resource limits
7822 * @adap: the adapter
7823 * @mbox: mailbox to use for the FW command
7824 * @pf: the PF being configured
7825 * @vf: the VF being configured
7826 * @txq: the max number of egress queues
7827 * @txq_eth_ctrl: the max number of egress Ethernet or control queues
7828 * @rxqi: the max number of interrupt-capable ingress queues
7829 * @rxq: the max number of interruptless ingress queues
7830 * @tc: the PCI traffic class
7831 * @vi: the max number of virtual interfaces
7832 * @cmask: the channel access rights mask for the PF/VF
7833 * @pmask: the port access rights mask for the PF/VF
7834 * @nexact: the maximum number of exact MPS filters
7835 * @rcaps: read capabilities
7836 * @wxcaps: write/execute capabilities
7838 * Configures resource limits and capabilities for a physical or virtual
7841 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
7842 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
7843 unsigned int rxqi, unsigned int rxq, unsigned int tc,
7844 unsigned int vi, unsigned int cmask, unsigned int pmask,
7845 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps)
7847 struct fw_pfvf_cmd c;
7849 memset(&c, 0, sizeof(c));
7850 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PFVF_CMD) | F_FW_CMD_REQUEST |
7851 F_FW_CMD_WRITE | V_FW_PFVF_CMD_PFN(pf) |
7852 V_FW_PFVF_CMD_VFN(vf));
7853 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
7854 c.niqflint_niq = cpu_to_be32(V_FW_PFVF_CMD_NIQFLINT(rxqi) |
7855 V_FW_PFVF_CMD_NIQ(rxq));
7856 c.type_to_neq = cpu_to_be32(V_FW_PFVF_CMD_CMASK(cmask) |
7857 V_FW_PFVF_CMD_PMASK(pmask) |
7858 V_FW_PFVF_CMD_NEQ(txq));
7859 c.tc_to_nexactf = cpu_to_be32(V_FW_PFVF_CMD_TC(tc) |
7860 V_FW_PFVF_CMD_NVI(vi) |
7861 V_FW_PFVF_CMD_NEXACTF(nexact));
7862 c.r_caps_to_nethctrl = cpu_to_be32(V_FW_PFVF_CMD_R_CAPS(rcaps) |
7863 V_FW_PFVF_CMD_WX_CAPS(wxcaps) |
7864 V_FW_PFVF_CMD_NETHCTRL(txq_eth_ctrl));
7865 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7869 * t4_alloc_vi_func - allocate a virtual interface
7870 * @adap: the adapter
7871 * @mbox: mailbox to use for the FW command
7872 * @port: physical port associated with the VI
7873 * @pf: the PF owning the VI
7874 * @vf: the VF owning the VI
7875 * @nmac: number of MAC addresses needed (1 to 5)
7876 * @mac: the MAC addresses of the VI
7877 * @rss_size: size of RSS table slice associated with this VI
7878 * @portfunc: which Port Application Function MAC Address is desired
7879 * @idstype: Intrusion Detection Type
7881 * Allocates a virtual interface for the given physical port. If @mac is
7882 * not %NULL it contains the MAC addresses of the VI as assigned by FW.
7883 * If @rss_size is %NULL the VI is not assigned any RSS slice by FW.
7884 * @mac should be large enough to hold @nmac Ethernet addresses, they are
7885 * stored consecutively so the space needed is @nmac * 6 bytes.
7886 * Returns a negative error number or the non-negative VI id.
7888 int t4_alloc_vi_func(struct adapter *adap, unsigned int mbox,
7889 unsigned int port, unsigned int pf, unsigned int vf,
7890 unsigned int nmac, u8 *mac, u16 *rss_size,
7891 uint8_t *vfvld, uint16_t *vin,
7892 unsigned int portfunc, unsigned int idstype)
7897 memset(&c, 0, sizeof(c));
7898 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_VI_CMD) | F_FW_CMD_REQUEST |
7899 F_FW_CMD_WRITE | F_FW_CMD_EXEC |
7900 V_FW_VI_CMD_PFN(pf) | V_FW_VI_CMD_VFN(vf));
7901 c.alloc_to_len16 = cpu_to_be32(F_FW_VI_CMD_ALLOC | FW_LEN16(c));
7902 c.type_to_viid = cpu_to_be16(V_FW_VI_CMD_TYPE(idstype) |
7903 V_FW_VI_CMD_FUNC(portfunc));
7904 c.portid_pkd = V_FW_VI_CMD_PORTID(port);
7907 c.norss_rsssize = F_FW_VI_CMD_NORSS;
7909 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
7912 ret = G_FW_VI_CMD_VIID(be16_to_cpu(c.type_to_viid));
7915 memcpy(mac, c.mac, sizeof(c.mac));
7918 memcpy(mac + 24, c.nmac3, sizeof(c.nmac3));
7920 memcpy(mac + 18, c.nmac2, sizeof(c.nmac2));
7922 memcpy(mac + 12, c.nmac1, sizeof(c.nmac1));
7924 memcpy(mac + 6, c.nmac0, sizeof(c.nmac0));
7928 *rss_size = G_FW_VI_CMD_RSSSIZE(be16_to_cpu(c.norss_rsssize));
7930 *vfvld = adap->params.viid_smt_extn_support ?
7931 G_FW_VI_CMD_VFVLD(be32_to_cpu(c.alloc_to_len16)) :
7932 G_FW_VIID_VIVLD(ret);
7935 *vin = adap->params.viid_smt_extn_support ?
7936 G_FW_VI_CMD_VIN(be32_to_cpu(c.alloc_to_len16)) :
7944 * t4_alloc_vi - allocate an [Ethernet Function] virtual interface
7945 * @adap: the adapter
7946 * @mbox: mailbox to use for the FW command
7947 * @port: physical port associated with the VI
7948 * @pf: the PF owning the VI
7949 * @vf: the VF owning the VI
7950 * @nmac: number of MAC addresses needed (1 to 5)
7951 * @mac: the MAC addresses of the VI
7952 * @rss_size: size of RSS table slice associated with this VI
7954 * backwards compatible and convieniance routine to allocate a Virtual
7955 * Interface with a Ethernet Port Application Function and Intrustion
7956 * Detection System disabled.
7958 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
7959 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
7960 u16 *rss_size, uint8_t *vfvld, uint16_t *vin)
7962 return t4_alloc_vi_func(adap, mbox, port, pf, vf, nmac, mac, rss_size,
7963 vfvld, vin, FW_VI_FUNC_ETH, 0);
7967 * t4_free_vi - free a virtual interface
7968 * @adap: the adapter
7969 * @mbox: mailbox to use for the FW command
7970 * @pf: the PF owning the VI
7971 * @vf: the VF owning the VI
7972 * @viid: virtual interface identifiler
7974 * Free a previously allocated virtual interface.
7976 int t4_free_vi(struct adapter *adap, unsigned int mbox, unsigned int pf,
7977 unsigned int vf, unsigned int viid)
7981 memset(&c, 0, sizeof(c));
7982 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_VI_CMD) |
7985 V_FW_VI_CMD_PFN(pf) |
7986 V_FW_VI_CMD_VFN(vf));
7987 c.alloc_to_len16 = cpu_to_be32(F_FW_VI_CMD_FREE | FW_LEN16(c));
7988 c.type_to_viid = cpu_to_be16(V_FW_VI_CMD_VIID(viid));
7990 return t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
7994 * t4_set_rxmode - set Rx properties of a virtual interface
7995 * @adap: the adapter
7996 * @mbox: mailbox to use for the FW command
7998 * @mtu: the new MTU or -1
7999 * @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change
8000 * @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change
8001 * @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change
8002 * @vlanex: 1 to enable HW VLAN extraction, 0 to disable it, -1 no change
8003 * @sleep_ok: if true we may sleep while awaiting command completion
8005 * Sets Rx properties of a virtual interface.
8007 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
8008 int mtu, int promisc, int all_multi, int bcast, int vlanex,
8011 struct fw_vi_rxmode_cmd c;
8013 /* convert to FW values */
8015 mtu = M_FW_VI_RXMODE_CMD_MTU;
8017 promisc = M_FW_VI_RXMODE_CMD_PROMISCEN;
8019 all_multi = M_FW_VI_RXMODE_CMD_ALLMULTIEN;
8021 bcast = M_FW_VI_RXMODE_CMD_BROADCASTEN;
8023 vlanex = M_FW_VI_RXMODE_CMD_VLANEXEN;
8025 memset(&c, 0, sizeof(c));
8026 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_RXMODE_CMD) |
8027 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
8028 V_FW_VI_RXMODE_CMD_VIID(viid));
8029 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
8031 cpu_to_be32(V_FW_VI_RXMODE_CMD_MTU(mtu) |
8032 V_FW_VI_RXMODE_CMD_PROMISCEN(promisc) |
8033 V_FW_VI_RXMODE_CMD_ALLMULTIEN(all_multi) |
8034 V_FW_VI_RXMODE_CMD_BROADCASTEN(bcast) |
8035 V_FW_VI_RXMODE_CMD_VLANEXEN(vlanex));
8036 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
8040 * t4_alloc_encap_mac_filt - Adds a mac entry in mps tcam with VNI support
8041 * @adap: the adapter
8043 * @mac: the MAC address
8045 * @vni: the VNI id for the tunnel protocol
8046 * @vni_mask: mask for the VNI id
8047 * @dip_hit: to enable DIP match for the MPS entry
8048 * @lookup_type: MAC address for inner (1) or outer (0) header
8049 * @sleep_ok: call is allowed to sleep
8051 * Allocates an MPS entry with specified MAC address and VNI value.
8053 * Returns a negative error number or the allocated index for this mac.
8055 int t4_alloc_encap_mac_filt(struct adapter *adap, unsigned int viid,
8056 const u8 *addr, const u8 *mask, unsigned int vni,
8057 unsigned int vni_mask, u8 dip_hit, u8 lookup_type,
8060 struct fw_vi_mac_cmd c;
8061 struct fw_vi_mac_vni *p = c.u.exact_vni;
8065 memset(&c, 0, sizeof(c));
8066 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) |
8067 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
8068 V_FW_VI_MAC_CMD_VIID(viid));
8069 val = V_FW_CMD_LEN16(1) |
8070 V_FW_VI_MAC_CMD_ENTRY_TYPE(FW_VI_MAC_TYPE_EXACTMAC_VNI);
8071 c.freemacs_to_len16 = cpu_to_be32(val);
8072 p->valid_to_idx = cpu_to_be16(F_FW_VI_MAC_CMD_VALID |
8073 V_FW_VI_MAC_CMD_IDX(FW_VI_MAC_ADD_MAC));
8074 memcpy(p->macaddr, addr, sizeof(p->macaddr));
8075 memcpy(p->macaddr_mask, mask, sizeof(p->macaddr_mask));
8077 p->lookup_type_to_vni = cpu_to_be32(V_FW_VI_MAC_CMD_VNI(vni) |
8078 V_FW_VI_MAC_CMD_DIP_HIT(dip_hit) |
8079 V_FW_VI_MAC_CMD_LOOKUP_TYPE(lookup_type));
8080 p->vni_mask_pkd = cpu_to_be32(V_FW_VI_MAC_CMD_VNI_MASK(vni_mask));
8082 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok);
8084 ret = G_FW_VI_MAC_CMD_IDX(be16_to_cpu(p->valid_to_idx));
8089 * t4_alloc_raw_mac_filt - Adds a mac entry in mps tcam
8090 * @adap: the adapter
8092 * @mac: the MAC address
8094 * @idx: index at which to add this entry
8095 * @port_id: the port index
8096 * @lookup_type: MAC address for inner (1) or outer (0) header
8097 * @sleep_ok: call is allowed to sleep
8099 * Adds the mac entry at the specified index using raw mac interface.
8101 * Returns a negative error number or the allocated index for this mac.
8103 int t4_alloc_raw_mac_filt(struct adapter *adap, unsigned int viid,
8104 const u8 *addr, const u8 *mask, unsigned int idx,
8105 u8 lookup_type, u8 port_id, bool sleep_ok)
8108 struct fw_vi_mac_cmd c;
8109 struct fw_vi_mac_raw *p = &c.u.raw;
8112 memset(&c, 0, sizeof(c));
8113 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) |
8114 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
8115 V_FW_VI_MAC_CMD_VIID(viid));
8116 val = V_FW_CMD_LEN16(1) |
8117 V_FW_VI_MAC_CMD_ENTRY_TYPE(FW_VI_MAC_TYPE_RAW);
8118 c.freemacs_to_len16 = cpu_to_be32(val);
8120 /* Specify that this is an inner mac address */
8121 p->raw_idx_pkd = cpu_to_be32(V_FW_VI_MAC_CMD_RAW_IDX(idx));
8123 /* Lookup Type. Outer header: 0, Inner header: 1 */
8124 p->data0_pkd = cpu_to_be32(V_DATALKPTYPE(lookup_type) |
8125 V_DATAPORTNUM(port_id));
8126 /* Lookup mask and port mask */
8127 p->data0m_pkd = cpu_to_be64(V_DATALKPTYPE(M_DATALKPTYPE) |
8128 V_DATAPORTNUM(M_DATAPORTNUM));
8130 /* Copy the address and the mask */
8131 memcpy((u8 *)&p->data1[0] + 2, addr, ETHER_ADDR_LEN);
8132 memcpy((u8 *)&p->data1m[0] + 2, mask, ETHER_ADDR_LEN);
8134 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok);
8136 ret = G_FW_VI_MAC_CMD_RAW_IDX(be32_to_cpu(p->raw_idx_pkd));
8145 * t4_alloc_mac_filt - allocates exact-match filters for MAC addresses
8146 * @adap: the adapter
8147 * @mbox: mailbox to use for the FW command
8149 * @free: if true any existing filters for this VI id are first removed
8150 * @naddr: the number of MAC addresses to allocate filters for (up to 7)
8151 * @addr: the MAC address(es)
8152 * @idx: where to store the index of each allocated filter
8153 * @hash: pointer to hash address filter bitmap
8154 * @sleep_ok: call is allowed to sleep
8156 * Allocates an exact-match filter for each of the supplied addresses and
8157 * sets it to the corresponding address. If @idx is not %NULL it should
8158 * have at least @naddr entries, each of which will be set to the index of
8159 * the filter allocated for the corresponding MAC address. If a filter
8160 * could not be allocated for an address its index is set to 0xffff.
8161 * If @hash is not %NULL addresses that fail to allocate an exact filter
8162 * are hashed and update the hash filter bitmap pointed at by @hash.
8164 * Returns a negative error number or the number of filters allocated.
8166 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
8167 unsigned int viid, bool free, unsigned int naddr,
8168 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok)
8170 int offset, ret = 0;
8171 struct fw_vi_mac_cmd c;
8172 unsigned int nfilters = 0;
8173 unsigned int max_naddr = adap->chip_params->mps_tcam_size;
8174 unsigned int rem = naddr;
8176 if (naddr > max_naddr)
8179 for (offset = 0; offset < naddr ; /**/) {
8180 unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact)
8182 : ARRAY_SIZE(c.u.exact));
8183 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
8184 u.exact[fw_naddr]), 16);
8185 struct fw_vi_mac_exact *p;
8188 memset(&c, 0, sizeof(c));
8189 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) |
8192 V_FW_CMD_EXEC(free) |
8193 V_FW_VI_MAC_CMD_VIID(viid));
8194 c.freemacs_to_len16 = cpu_to_be32(V_FW_VI_MAC_CMD_FREEMACS(free) |
8195 V_FW_CMD_LEN16(len16));
8197 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
8199 cpu_to_be16(F_FW_VI_MAC_CMD_VALID |
8200 V_FW_VI_MAC_CMD_IDX(FW_VI_MAC_ADD_MAC));
8201 memcpy(p->macaddr, addr[offset+i], sizeof(p->macaddr));
8205 * It's okay if we run out of space in our MAC address arena.
8206 * Some of the addresses we submit may get stored so we need
8207 * to run through the reply to see what the results were ...
8209 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
8210 if (ret && ret != -FW_ENOMEM)
8213 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
8214 u16 index = G_FW_VI_MAC_CMD_IDX(
8215 be16_to_cpu(p->valid_to_idx));
8218 idx[offset+i] = (index >= max_naddr
8221 if (index < max_naddr)
8224 *hash |= (1ULL << hash_mac_addr(addr[offset+i]));
8232 if (ret == 0 || ret == -FW_ENOMEM)
8238 * t4_free_encap_mac_filt - frees MPS entry at given index
8239 * @adap: the adapter
8241 * @idx: index of MPS entry to be freed
8242 * @sleep_ok: call is allowed to sleep
8244 * Frees the MPS entry at supplied index
8246 * Returns a negative error number or zero on success
8248 int t4_free_encap_mac_filt(struct adapter *adap, unsigned int viid,
8249 int idx, bool sleep_ok)
8251 struct fw_vi_mac_exact *p;
8252 struct fw_vi_mac_cmd c;
8253 u8 addr[] = {0,0,0,0,0,0};
8257 memset(&c, 0, sizeof(c));
8258 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) |
8262 V_FW_VI_MAC_CMD_VIID(viid));
8263 exact = V_FW_VI_MAC_CMD_ENTRY_TYPE(FW_VI_MAC_TYPE_EXACTMAC);
8264 c.freemacs_to_len16 = cpu_to_be32(V_FW_VI_MAC_CMD_FREEMACS(0) |
8268 p->valid_to_idx = cpu_to_be16(F_FW_VI_MAC_CMD_VALID |
8269 V_FW_VI_MAC_CMD_IDX(idx));
8270 memcpy(p->macaddr, addr, sizeof(p->macaddr));
8272 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok);
8277 * t4_free_raw_mac_filt - Frees a raw mac entry in mps tcam
8278 * @adap: the adapter
8280 * @addr: the MAC address
8282 * @idx: index of the entry in mps tcam
8283 * @lookup_type: MAC address for inner (1) or outer (0) header
8284 * @port_id: the port index
8285 * @sleep_ok: call is allowed to sleep
8287 * Removes the mac entry at the specified index using raw mac interface.
8289 * Returns a negative error number on failure.
8291 int t4_free_raw_mac_filt(struct adapter *adap, unsigned int viid,
8292 const u8 *addr, const u8 *mask, unsigned int idx,
8293 u8 lookup_type, u8 port_id, bool sleep_ok)
8295 struct fw_vi_mac_cmd c;
8296 struct fw_vi_mac_raw *p = &c.u.raw;
8299 memset(&c, 0, sizeof(c));
8300 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) |
8301 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
8303 V_FW_VI_MAC_CMD_VIID(viid));
8304 raw = V_FW_VI_MAC_CMD_ENTRY_TYPE(FW_VI_MAC_TYPE_RAW);
8305 c.freemacs_to_len16 = cpu_to_be32(V_FW_VI_MAC_CMD_FREEMACS(0) |
8309 p->raw_idx_pkd = cpu_to_be32(V_FW_VI_MAC_CMD_RAW_IDX(idx) |
8310 FW_VI_MAC_ID_BASED_FREE);
8312 /* Lookup Type. Outer header: 0, Inner header: 1 */
8313 p->data0_pkd = cpu_to_be32(V_DATALKPTYPE(lookup_type) |
8314 V_DATAPORTNUM(port_id));
8315 /* Lookup mask and port mask */
8316 p->data0m_pkd = cpu_to_be64(V_DATALKPTYPE(M_DATALKPTYPE) |
8317 V_DATAPORTNUM(M_DATAPORTNUM));
8319 /* Copy the address and the mask */
8320 memcpy((u8 *)&p->data1[0] + 2, addr, ETHER_ADDR_LEN);
8321 memcpy((u8 *)&p->data1m[0] + 2, mask, ETHER_ADDR_LEN);
8323 return t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok);
8327 * t4_free_mac_filt - frees exact-match filters of given MAC addresses
8328 * @adap: the adapter
8329 * @mbox: mailbox to use for the FW command
8331 * @naddr: the number of MAC addresses to allocate filters for (up to 7)
8332 * @addr: the MAC address(es)
8333 * @sleep_ok: call is allowed to sleep
8335 * Frees the exact-match filter for each of the supplied addresses
8337 * Returns a negative error number or the number of filters freed.
8339 int t4_free_mac_filt(struct adapter *adap, unsigned int mbox,
8340 unsigned int viid, unsigned int naddr,
8341 const u8 **addr, bool sleep_ok)
8343 int offset, ret = 0;
8344 struct fw_vi_mac_cmd c;
8345 unsigned int nfilters = 0;
8346 unsigned int max_naddr = adap->chip_params->mps_tcam_size;
8347 unsigned int rem = naddr;
8349 if (naddr > max_naddr)
8352 for (offset = 0; offset < (int)naddr ; /**/) {
8353 unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact)
8355 : ARRAY_SIZE(c.u.exact));
8356 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
8357 u.exact[fw_naddr]), 16);
8358 struct fw_vi_mac_exact *p;
8361 memset(&c, 0, sizeof(c));
8362 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) |
8366 V_FW_VI_MAC_CMD_VIID(viid));
8367 c.freemacs_to_len16 =
8368 cpu_to_be32(V_FW_VI_MAC_CMD_FREEMACS(0) |
8369 V_FW_CMD_LEN16(len16));
8371 for (i = 0, p = c.u.exact; i < (int)fw_naddr; i++, p++) {
8372 p->valid_to_idx = cpu_to_be16(
8373 F_FW_VI_MAC_CMD_VALID |
8374 V_FW_VI_MAC_CMD_IDX(FW_VI_MAC_MAC_BASED_FREE));
8375 memcpy(p->macaddr, addr[offset+i], sizeof(p->macaddr));
8378 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
8382 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
8383 u16 index = G_FW_VI_MAC_CMD_IDX(
8384 be16_to_cpu(p->valid_to_idx));
8386 if (index < max_naddr)
8400 * t4_change_mac - modifies the exact-match filter for a MAC address
8401 * @adap: the adapter
8402 * @mbox: mailbox to use for the FW command
8404 * @idx: index of existing filter for old value of MAC address, or -1
8405 * @addr: the new MAC address value
8406 * @persist: whether a new MAC allocation should be persistent
8407 * @smt_idx: add MAC to SMT and return its index, or NULL
8409 * Modifies an exact-match filter and sets it to the new MAC address if
8410 * @idx >= 0, or adds the MAC address to a new filter if @idx < 0. In the
8411 * latter case the address is added persistently if @persist is %true.
8413 * Note that in general it is not possible to modify the value of a given
8414 * filter so the generic way to modify an address filter is to free the one
8415 * being used by the old address value and allocate a new filter for the
8416 * new address value.
8418 * Returns a negative error number or the index of the filter with the new
8419 * MAC value. Note that this index may differ from @idx.
8421 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
8422 int idx, const u8 *addr, bool persist, uint16_t *smt_idx)
8425 struct fw_vi_mac_cmd c;
8426 struct fw_vi_mac_exact *p = c.u.exact;
8427 unsigned int max_mac_addr = adap->chip_params->mps_tcam_size;
8429 if (idx < 0) /* new allocation */
8430 idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC;
8431 mode = smt_idx ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY;
8433 memset(&c, 0, sizeof(c));
8434 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) |
8435 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
8436 V_FW_VI_MAC_CMD_VIID(viid));
8437 c.freemacs_to_len16 = cpu_to_be32(V_FW_CMD_LEN16(1));
8438 p->valid_to_idx = cpu_to_be16(F_FW_VI_MAC_CMD_VALID |
8439 V_FW_VI_MAC_CMD_SMAC_RESULT(mode) |
8440 V_FW_VI_MAC_CMD_IDX(idx));
8441 memcpy(p->macaddr, addr, sizeof(p->macaddr));
8443 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
8445 ret = G_FW_VI_MAC_CMD_IDX(be16_to_cpu(p->valid_to_idx));
8446 if (ret >= max_mac_addr)
8449 if (adap->params.viid_smt_extn_support)
8450 *smt_idx = G_FW_VI_MAC_CMD_SMTID(be32_to_cpu(c.op_to_viid));
8452 if (chip_id(adap) <= CHELSIO_T5)
8453 *smt_idx = (viid & M_FW_VIID_VIN) << 1;
8455 *smt_idx = viid & M_FW_VIID_VIN;
8463 * t4_set_addr_hash - program the MAC inexact-match hash filter
8464 * @adap: the adapter
8465 * @mbox: mailbox to use for the FW command
8467 * @ucast: whether the hash filter should also match unicast addresses
8468 * @vec: the value to be written to the hash filter
8469 * @sleep_ok: call is allowed to sleep
8471 * Sets the 64-bit inexact-match hash filter for a virtual interface.
8473 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
8474 bool ucast, u64 vec, bool sleep_ok)
8476 struct fw_vi_mac_cmd c;
8479 memset(&c, 0, sizeof(c));
8480 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) |
8481 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
8482 V_FW_VI_ENABLE_CMD_VIID(viid));
8483 val = V_FW_VI_MAC_CMD_ENTRY_TYPE(FW_VI_MAC_TYPE_HASHVEC) |
8484 V_FW_VI_MAC_CMD_HASHUNIEN(ucast) | V_FW_CMD_LEN16(1);
8485 c.freemacs_to_len16 = cpu_to_be32(val);
8486 c.u.hash.hashvec = cpu_to_be64(vec);
8487 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
8491 * t4_enable_vi_params - enable/disable a virtual interface
8492 * @adap: the adapter
8493 * @mbox: mailbox to use for the FW command
8495 * @rx_en: 1=enable Rx, 0=disable Rx
8496 * @tx_en: 1=enable Tx, 0=disable Tx
8497 * @dcb_en: 1=enable delivery of Data Center Bridging messages.
8499 * Enables/disables a virtual interface. Note that setting DCB Enable
8500 * only makes sense when enabling a Virtual Interface ...
8502 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
8503 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en)
8505 struct fw_vi_enable_cmd c;
8507 memset(&c, 0, sizeof(c));
8508 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_ENABLE_CMD) |
8509 F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
8510 V_FW_VI_ENABLE_CMD_VIID(viid));
8511 c.ien_to_len16 = cpu_to_be32(V_FW_VI_ENABLE_CMD_IEN(rx_en) |
8512 V_FW_VI_ENABLE_CMD_EEN(tx_en) |
8513 V_FW_VI_ENABLE_CMD_DCB_INFO(dcb_en) |
8515 return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL);
8519 * t4_enable_vi - enable/disable a virtual interface
8520 * @adap: the adapter
8521 * @mbox: mailbox to use for the FW command
8523 * @rx_en: 1=enable Rx, 0=disable Rx
8524 * @tx_en: 1=enable Tx, 0=disable Tx
8526 * Enables/disables a virtual interface. Note that setting DCB Enable
8527 * only makes sense when enabling a Virtual Interface ...
8529 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
8530 bool rx_en, bool tx_en)
8532 return t4_enable_vi_params(adap, mbox, viid, rx_en, tx_en, 0);
8536 * t4_identify_port - identify a VI's port by blinking its LED
8537 * @adap: the adapter
8538 * @mbox: mailbox to use for the FW command
8540 * @nblinks: how many times to blink LED at 2.5 Hz
8542 * Identifies a VI's port by blinking its LED.
8544 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
8545 unsigned int nblinks)
8547 struct fw_vi_enable_cmd c;
8549 memset(&c, 0, sizeof(c));
8550 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_ENABLE_CMD) |
8551 F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
8552 V_FW_VI_ENABLE_CMD_VIID(viid));
8553 c.ien_to_len16 = cpu_to_be32(F_FW_VI_ENABLE_CMD_LED | FW_LEN16(c));
8554 c.blinkdur = cpu_to_be16(nblinks);
8555 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8559 * t4_iq_stop - stop an ingress queue and its FLs
8560 * @adap: the adapter
8561 * @mbox: mailbox to use for the FW command
8562 * @pf: the PF owning the queues
8563 * @vf: the VF owning the queues
8564 * @iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.)
8565 * @iqid: ingress queue id
8566 * @fl0id: FL0 queue id or 0xffff if no attached FL0
8567 * @fl1id: FL1 queue id or 0xffff if no attached FL1
8569 * Stops an ingress queue and its associated FLs, if any. This causes
8570 * any current or future data/messages destined for these queues to be
8573 int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf,
8574 unsigned int vf, unsigned int iqtype, unsigned int iqid,
8575 unsigned int fl0id, unsigned int fl1id)
8579 memset(&c, 0, sizeof(c));
8580 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |
8581 F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(pf) |
8582 V_FW_IQ_CMD_VFN(vf));
8583 c.alloc_to_len16 = cpu_to_be32(F_FW_IQ_CMD_IQSTOP | FW_LEN16(c));
8584 c.type_to_iqandstindex = cpu_to_be32(V_FW_IQ_CMD_TYPE(iqtype));
8585 c.iqid = cpu_to_be16(iqid);
8586 c.fl0id = cpu_to_be16(fl0id);
8587 c.fl1id = cpu_to_be16(fl1id);
8588 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8592 * t4_iq_free - free an ingress queue and its FLs
8593 * @adap: the adapter
8594 * @mbox: mailbox to use for the FW command
8595 * @pf: the PF owning the queues
8596 * @vf: the VF owning the queues
8597 * @iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.)
8598 * @iqid: ingress queue id
8599 * @fl0id: FL0 queue id or 0xffff if no attached FL0
8600 * @fl1id: FL1 queue id or 0xffff if no attached FL1
8602 * Frees an ingress queue and its associated FLs, if any.
8604 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
8605 unsigned int vf, unsigned int iqtype, unsigned int iqid,
8606 unsigned int fl0id, unsigned int fl1id)
8610 memset(&c, 0, sizeof(c));
8611 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |
8612 F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(pf) |
8613 V_FW_IQ_CMD_VFN(vf));
8614 c.alloc_to_len16 = cpu_to_be32(F_FW_IQ_CMD_FREE | FW_LEN16(c));
8615 c.type_to_iqandstindex = cpu_to_be32(V_FW_IQ_CMD_TYPE(iqtype));
8616 c.iqid = cpu_to_be16(iqid);
8617 c.fl0id = cpu_to_be16(fl0id);
8618 c.fl1id = cpu_to_be16(fl1id);
8619 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8623 * t4_eth_eq_stop - stop an Ethernet egress queue
8624 * @adap: the adapter
8625 * @mbox: mailbox to use for the FW command
8626 * @pf: the PF owning the queues
8627 * @vf: the VF owning the queues
8628 * @eqid: egress queue id
8630 * Stops an Ethernet egress queue. The queue can be reinitialized or
8631 * freed but is not otherwise functional after this call.
8633 int t4_eth_eq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf,
8634 unsigned int vf, unsigned int eqid)
8636 struct fw_eq_eth_cmd c;
8638 memset(&c, 0, sizeof(c));
8639 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_ETH_CMD) |
8640 F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
8641 V_FW_EQ_ETH_CMD_PFN(pf) |
8642 V_FW_EQ_ETH_CMD_VFN(vf));
8643 c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_ETH_CMD_EQSTOP | FW_LEN16(c));
8644 c.eqid_pkd = cpu_to_be32(V_FW_EQ_ETH_CMD_EQID(eqid));
8645 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8649 * t4_eth_eq_free - free an Ethernet egress queue
8650 * @adap: the adapter
8651 * @mbox: mailbox to use for the FW command
8652 * @pf: the PF owning the queue
8653 * @vf: the VF owning the queue
8654 * @eqid: egress queue id
8656 * Frees an Ethernet egress queue.
8658 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
8659 unsigned int vf, unsigned int eqid)
8661 struct fw_eq_eth_cmd c;
8663 memset(&c, 0, sizeof(c));
8664 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_ETH_CMD) |
8665 F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
8666 V_FW_EQ_ETH_CMD_PFN(pf) |
8667 V_FW_EQ_ETH_CMD_VFN(vf));
8668 c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_ETH_CMD_FREE | FW_LEN16(c));
8669 c.eqid_pkd = cpu_to_be32(V_FW_EQ_ETH_CMD_EQID(eqid));
8670 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8674 * t4_ctrl_eq_free - free a control egress queue
8675 * @adap: the adapter
8676 * @mbox: mailbox to use for the FW command
8677 * @pf: the PF owning the queue
8678 * @vf: the VF owning the queue
8679 * @eqid: egress queue id
8681 * Frees a control egress queue.
8683 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
8684 unsigned int vf, unsigned int eqid)
8686 struct fw_eq_ctrl_cmd c;
8688 memset(&c, 0, sizeof(c));
8689 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_CTRL_CMD) |
8690 F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
8691 V_FW_EQ_CTRL_CMD_PFN(pf) |
8692 V_FW_EQ_CTRL_CMD_VFN(vf));
8693 c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_CTRL_CMD_FREE | FW_LEN16(c));
8694 c.cmpliqid_eqid = cpu_to_be32(V_FW_EQ_CTRL_CMD_EQID(eqid));
8695 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8699 * t4_ofld_eq_free - free an offload egress queue
8700 * @adap: the adapter
8701 * @mbox: mailbox to use for the FW command
8702 * @pf: the PF owning the queue
8703 * @vf: the VF owning the queue
8704 * @eqid: egress queue id
8706 * Frees a control egress queue.
8708 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
8709 unsigned int vf, unsigned int eqid)
8711 struct fw_eq_ofld_cmd c;
8713 memset(&c, 0, sizeof(c));
8714 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_OFLD_CMD) |
8715 F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
8716 V_FW_EQ_OFLD_CMD_PFN(pf) |
8717 V_FW_EQ_OFLD_CMD_VFN(vf));
8718 c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_OFLD_CMD_FREE | FW_LEN16(c));
8719 c.eqid_pkd = cpu_to_be32(V_FW_EQ_OFLD_CMD_EQID(eqid));
8720 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8724 * t4_link_down_rc_str - return a string for a Link Down Reason Code
8725 * @link_down_rc: Link Down Reason Code
8727 * Returns a string representation of the Link Down Reason Code.
8729 const char *t4_link_down_rc_str(unsigned char link_down_rc)
8731 static const char *reason[] = {
8734 "Auto-negotiation Failure",
8736 "Insufficient Airflow",
8737 "Unable To Determine Reason",
8738 "No RX Signal Detected",
8742 if (link_down_rc >= ARRAY_SIZE(reason))
8743 return "Bad Reason Code";
8745 return reason[link_down_rc];
8749 * Return the highest speed set in the port capabilities, in Mb/s.
8751 unsigned int fwcap_to_speed(uint32_t caps)
8753 #define TEST_SPEED_RETURN(__caps_speed, __speed) \
8755 if (caps & FW_PORT_CAP32_SPEED_##__caps_speed) \
8759 TEST_SPEED_RETURN(400G, 400000);
8760 TEST_SPEED_RETURN(200G, 200000);
8761 TEST_SPEED_RETURN(100G, 100000);
8762 TEST_SPEED_RETURN(50G, 50000);
8763 TEST_SPEED_RETURN(40G, 40000);
8764 TEST_SPEED_RETURN(25G, 25000);
8765 TEST_SPEED_RETURN(10G, 10000);
8766 TEST_SPEED_RETURN(1G, 1000);
8767 TEST_SPEED_RETURN(100M, 100);
8769 #undef TEST_SPEED_RETURN
8775 * Return the port capabilities bit for the given speed, which is in Mb/s.
8777 uint32_t speed_to_fwcap(unsigned int speed)
8779 #define TEST_SPEED_RETURN(__caps_speed, __speed) \
8781 if (speed == __speed) \
8782 return FW_PORT_CAP32_SPEED_##__caps_speed; \
8785 TEST_SPEED_RETURN(400G, 400000);
8786 TEST_SPEED_RETURN(200G, 200000);
8787 TEST_SPEED_RETURN(100G, 100000);
8788 TEST_SPEED_RETURN(50G, 50000);
8789 TEST_SPEED_RETURN(40G, 40000);
8790 TEST_SPEED_RETURN(25G, 25000);
8791 TEST_SPEED_RETURN(10G, 10000);
8792 TEST_SPEED_RETURN(1G, 1000);
8793 TEST_SPEED_RETURN(100M, 100);
8795 #undef TEST_SPEED_RETURN
8801 * Return the port capabilities bit for the highest speed in the capabilities.
8803 uint32_t fwcap_top_speed(uint32_t caps)
8805 #define TEST_SPEED_RETURN(__caps_speed) \
8807 if (caps & FW_PORT_CAP32_SPEED_##__caps_speed) \
8808 return FW_PORT_CAP32_SPEED_##__caps_speed; \
8811 TEST_SPEED_RETURN(400G);
8812 TEST_SPEED_RETURN(200G);
8813 TEST_SPEED_RETURN(100G);
8814 TEST_SPEED_RETURN(50G);
8815 TEST_SPEED_RETURN(40G);
8816 TEST_SPEED_RETURN(25G);
8817 TEST_SPEED_RETURN(10G);
8818 TEST_SPEED_RETURN(1G);
8819 TEST_SPEED_RETURN(100M);
8821 #undef TEST_SPEED_RETURN
8827 * lstatus_to_fwcap - translate old lstatus to 32-bit Port Capabilities
8828 * @lstatus: old FW_PORT_ACTION_GET_PORT_INFO lstatus value
8830 * Translates old FW_PORT_ACTION_GET_PORT_INFO lstatus field into new
8831 * 32-bit Port Capabilities value.
8833 static uint32_t lstatus_to_fwcap(u32 lstatus)
8835 uint32_t linkattr = 0;
8838 * Unfortunately the format of the Link Status in the old
8839 * 16-bit Port Information message isn't the same as the
8840 * 16-bit Port Capabilities bitfield used everywhere else ...
8842 if (lstatus & F_FW_PORT_CMD_RXPAUSE)
8843 linkattr |= FW_PORT_CAP32_FC_RX;
8844 if (lstatus & F_FW_PORT_CMD_TXPAUSE)
8845 linkattr |= FW_PORT_CAP32_FC_TX;
8846 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100M))
8847 linkattr |= FW_PORT_CAP32_SPEED_100M;
8848 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_1G))
8849 linkattr |= FW_PORT_CAP32_SPEED_1G;
8850 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_10G))
8851 linkattr |= FW_PORT_CAP32_SPEED_10G;
8852 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_25G))
8853 linkattr |= FW_PORT_CAP32_SPEED_25G;
8854 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_40G))
8855 linkattr |= FW_PORT_CAP32_SPEED_40G;
8856 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100G))
8857 linkattr |= FW_PORT_CAP32_SPEED_100G;
8863 * Updates all fields owned by the common code in port_info and link_config
8864 * based on information provided by the firmware. Does not touch any
8865 * requested_* field.
8867 static void handle_port_info(struct port_info *pi, const struct fw_port_cmd *p,
8868 enum fw_port_action action, bool *mod_changed, bool *link_changed)
8870 struct link_config old_lc, *lc = &pi->link_cfg;
8873 int old_ptype, old_mtype;
8875 old_ptype = pi->port_type;
8876 old_mtype = pi->mod_type;
8878 if (action == FW_PORT_ACTION_GET_PORT_INFO) {
8879 stat = be32_to_cpu(p->u.info.lstatus_to_modtype);
8881 pi->port_type = G_FW_PORT_CMD_PTYPE(stat);
8882 pi->mod_type = G_FW_PORT_CMD_MODTYPE(stat);
8883 pi->mdio_addr = stat & F_FW_PORT_CMD_MDIOCAP ?
8884 G_FW_PORT_CMD_MDIOADDR(stat) : -1;
8886 lc->pcaps = fwcaps16_to_caps32(be16_to_cpu(p->u.info.pcap));
8887 lc->acaps = fwcaps16_to_caps32(be16_to_cpu(p->u.info.acap));
8888 lc->lpacaps = fwcaps16_to_caps32(be16_to_cpu(p->u.info.lpacap));
8889 lc->link_ok = (stat & F_FW_PORT_CMD_LSTATUS) != 0;
8890 lc->link_down_rc = G_FW_PORT_CMD_LINKDNRC(stat);
8892 linkattr = lstatus_to_fwcap(stat);
8893 } else if (action == FW_PORT_ACTION_GET_PORT_INFO32) {
8894 stat = be32_to_cpu(p->u.info32.lstatus32_to_cbllen32);
8896 pi->port_type = G_FW_PORT_CMD_PORTTYPE32(stat);
8897 pi->mod_type = G_FW_PORT_CMD_MODTYPE32(stat);
8898 pi->mdio_addr = stat & F_FW_PORT_CMD_MDIOCAP32 ?
8899 G_FW_PORT_CMD_MDIOADDR32(stat) : -1;
8901 lc->pcaps = be32_to_cpu(p->u.info32.pcaps32);
8902 lc->acaps = be32_to_cpu(p->u.info32.acaps32);
8903 lc->lpacaps = be32_to_cpu(p->u.info32.lpacaps32);
8904 lc->link_ok = (stat & F_FW_PORT_CMD_LSTATUS32) != 0;
8905 lc->link_down_rc = G_FW_PORT_CMD_LINKDNRC32(stat);
8907 linkattr = be32_to_cpu(p->u.info32.linkattr32);
8909 CH_ERR(pi->adapter, "bad port_info action 0x%x\n", action);
8913 lc->speed = fwcap_to_speed(linkattr);
8914 lc->fec = fwcap_to_fec(linkattr, true);
8917 if (linkattr & FW_PORT_CAP32_FC_RX)
8919 if (linkattr & FW_PORT_CAP32_FC_TX)
8923 if (mod_changed != NULL)
8924 *mod_changed = false;
8925 if (link_changed != NULL)
8926 *link_changed = false;
8927 if (old_ptype != pi->port_type || old_mtype != pi->mod_type ||
8928 old_lc.pcaps != lc->pcaps) {
8929 if (pi->mod_type != FW_PORT_MOD_TYPE_NONE)
8930 lc->fec_hint = fwcap_to_fec(lc->acaps, true);
8931 if (mod_changed != NULL)
8932 *mod_changed = true;
8934 if (old_lc.link_ok != lc->link_ok || old_lc.speed != lc->speed ||
8935 old_lc.fec != lc->fec || old_lc.fc != lc->fc) {
8936 if (link_changed != NULL)
8937 *link_changed = true;
8942 * t4_update_port_info - retrieve and update port information if changed
8943 * @pi: the port_info
8945 * We issue a Get Port Information Command to the Firmware and, if
8946 * successful, we check to see if anything is different from what we
8947 * last recorded and update things accordingly.
8949 int t4_update_port_info(struct port_info *pi)
8951 struct adapter *sc = pi->adapter;
8952 struct fw_port_cmd cmd;
8953 enum fw_port_action action;
8956 memset(&cmd, 0, sizeof(cmd));
8957 cmd.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) |
8958 F_FW_CMD_REQUEST | F_FW_CMD_READ |
8959 V_FW_PORT_CMD_PORTID(pi->tx_chan));
8960 action = sc->params.port_caps32 ? FW_PORT_ACTION_GET_PORT_INFO32 :
8961 FW_PORT_ACTION_GET_PORT_INFO;
8962 cmd.action_to_len16 = cpu_to_be32(V_FW_PORT_CMD_ACTION(action) |
8964 ret = t4_wr_mbox_ns(sc, sc->mbox, &cmd, sizeof(cmd), &cmd);
8968 handle_port_info(pi, &cmd, action, NULL, NULL);
8973 * t4_handle_fw_rpl - process a FW reply message
8974 * @adap: the adapter
8975 * @rpl: start of the FW message
8977 * Processes a FW message, such as link state change messages.
8979 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl)
8981 u8 opcode = *(const u8 *)rpl;
8982 const struct fw_port_cmd *p = (const void *)rpl;
8983 enum fw_port_action action =
8984 G_FW_PORT_CMD_ACTION(be32_to_cpu(p->action_to_len16));
8985 bool mod_changed, link_changed;
8987 if (opcode == FW_PORT_CMD &&
8988 (action == FW_PORT_ACTION_GET_PORT_INFO ||
8989 action == FW_PORT_ACTION_GET_PORT_INFO32)) {
8990 /* link/module state change message */
8992 int chan = G_FW_PORT_CMD_PORTID(be32_to_cpu(p->op_to_portid));
8993 struct port_info *pi = NULL;
8994 struct link_config *lc;
8996 for_each_port(adap, i) {
8997 pi = adap2pinfo(adap, i);
8998 if (pi->tx_chan == chan)
9004 handle_port_info(pi, p, action, &mod_changed, &link_changed);
9007 t4_os_portmod_changed(pi);
9010 t4_os_link_changed(pi);
9014 CH_WARN_RATELIMIT(adap, "Unknown firmware reply %d\n", opcode);
9021 * get_pci_mode - determine a card's PCI mode
9022 * @adapter: the adapter
9023 * @p: where to store the PCI settings
9025 * Determines a card's PCI mode and associated parameters, such as speed
9028 static void get_pci_mode(struct adapter *adapter,
9029 struct pci_params *p)
9034 pcie_cap = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP);
9036 t4_os_pci_read_cfg2(adapter, pcie_cap + PCI_EXP_LNKSTA, &val);
9037 p->speed = val & PCI_EXP_LNKSTA_CLS;
9038 p->width = (val & PCI_EXP_LNKSTA_NLW) >> 4;
9043 u32 vendor_and_model_id;
9047 int t4_get_flash_params(struct adapter *adapter)
9050 * Table for non-standard supported Flash parts. Note, all Flash
9051 * parts must have 64KB sectors.
9053 static struct flash_desc supported_flash[] = {
9054 { 0x00150201, 4 << 20 }, /* Spansion 4MB S25FL032P */
9059 unsigned int part, manufacturer;
9060 unsigned int density, size = 0;
9064 * Issue a Read ID Command to the Flash part. We decode supported
9065 * Flash parts and their sizes from this. There's a newer Query
9066 * Command which can retrieve detailed geometry information but many
9067 * Flash parts don't support it.
9069 ret = sf1_write(adapter, 1, 1, 0, SF_RD_ID);
9071 ret = sf1_read(adapter, 3, 0, 1, &flashid);
9072 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */
9077 * Check to see if it's one of our non-standard supported Flash parts.
9079 for (part = 0; part < ARRAY_SIZE(supported_flash); part++)
9080 if (supported_flash[part].vendor_and_model_id == flashid) {
9081 adapter->params.sf_size =
9082 supported_flash[part].size_mb;
9083 adapter->params.sf_nsec =
9084 adapter->params.sf_size / SF_SEC_SIZE;
9089 * Decode Flash part size. The code below looks repetative with
9090 * common encodings, but that's not guaranteed in the JEDEC
9091 * specification for the Read JADEC ID command. The only thing that
9092 * we're guaranteed by the JADEC specification is where the
9093 * Manufacturer ID is in the returned result. After that each
9094 * Manufacturer ~could~ encode things completely differently.
9095 * Note, all Flash parts must have 64KB sectors.
9097 manufacturer = flashid & 0xff;
9098 switch (manufacturer) {
9099 case 0x20: /* Micron/Numonix */
9101 * This Density -> Size decoding table is taken from Micron
9104 density = (flashid >> 16) & 0xff;
9106 case 0x14: size = 1 << 20; break; /* 1MB */
9107 case 0x15: size = 1 << 21; break; /* 2MB */
9108 case 0x16: size = 1 << 22; break; /* 4MB */
9109 case 0x17: size = 1 << 23; break; /* 8MB */
9110 case 0x18: size = 1 << 24; break; /* 16MB */
9111 case 0x19: size = 1 << 25; break; /* 32MB */
9112 case 0x20: size = 1 << 26; break; /* 64MB */
9113 case 0x21: size = 1 << 27; break; /* 128MB */
9114 case 0x22: size = 1 << 28; break; /* 256MB */
9118 case 0x9d: /* ISSI -- Integrated Silicon Solution, Inc. */
9120 * This Density -> Size decoding table is taken from ISSI
9123 density = (flashid >> 16) & 0xff;
9125 case 0x16: size = 1 << 25; break; /* 32MB */
9126 case 0x17: size = 1 << 26; break; /* 64MB */
9130 case 0xc2: /* Macronix */
9132 * This Density -> Size decoding table is taken from Macronix
9135 density = (flashid >> 16) & 0xff;
9137 case 0x17: size = 1 << 23; break; /* 8MB */
9138 case 0x18: size = 1 << 24; break; /* 16MB */
9142 case 0xef: /* Winbond */
9144 * This Density -> Size decoding table is taken from Winbond
9147 density = (flashid >> 16) & 0xff;
9149 case 0x17: size = 1 << 23; break; /* 8MB */
9150 case 0x18: size = 1 << 24; break; /* 16MB */
9155 /* If we didn't recognize the FLASH part, that's no real issue: the
9156 * Hardware/Software contract says that Hardware will _*ALWAYS*_
9157 * use a FLASH part which is at least 4MB in size and has 64KB
9158 * sectors. The unrecognized FLASH part is likely to be much larger
9159 * than 4MB, but that's all we really need.
9162 CH_WARN(adapter, "Unknown Flash Part, ID = %#x, assuming 4MB\n", flashid);
9167 * Store decoded Flash size and fall through into vetting code.
9169 adapter->params.sf_size = size;
9170 adapter->params.sf_nsec = size / SF_SEC_SIZE;
9174 * We should ~probably~ reject adapters with FLASHes which are too
9175 * small but we have some legacy FPGAs with small FLASHes that we'd
9176 * still like to use. So instead we emit a scary message ...
9178 if (adapter->params.sf_size < FLASH_MIN_SIZE)
9179 CH_WARN(adapter, "WARNING: Flash Part ID %#x, size %#x < %#x\n",
9180 flashid, adapter->params.sf_size, FLASH_MIN_SIZE);
9185 static void set_pcie_completion_timeout(struct adapter *adapter,
9191 pcie_cap = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP);
9193 t4_os_pci_read_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, &val);
9196 t4_os_pci_write_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, val);
9200 const struct chip_params *t4_get_chip_params(int chipid)
9202 static const struct chip_params chip_params[] = {
9206 .pm_stats_cnt = PM_NSTATS,
9207 .cng_ch_bits_log = 2,
9209 .cim_num_obq = CIM_NUM_OBQ,
9210 .mps_rplc_size = 128,
9212 .sge_fl_db = F_DBPRIO,
9213 .mps_tcam_size = NUM_MPS_CLS_SRAM_L_INSTANCES,
9214 .rss_nentries = RSS_NENTRIES,
9219 .pm_stats_cnt = PM_NSTATS,
9220 .cng_ch_bits_log = 2,
9222 .cim_num_obq = CIM_NUM_OBQ_T5,
9223 .mps_rplc_size = 128,
9225 .sge_fl_db = F_DBPRIO | F_DBTYPE,
9226 .mps_tcam_size = NUM_MPS_T5_CLS_SRAM_L_INSTANCES,
9227 .rss_nentries = RSS_NENTRIES,
9232 .pm_stats_cnt = T6_PM_NSTATS,
9233 .cng_ch_bits_log = 3,
9235 .cim_num_obq = CIM_NUM_OBQ_T5,
9236 .mps_rplc_size = 256,
9239 .mps_tcam_size = NUM_MPS_T5_CLS_SRAM_L_INSTANCES,
9240 .rss_nentries = T6_RSS_NENTRIES,
9244 chipid -= CHELSIO_T4;
9245 if (chipid < 0 || chipid >= ARRAY_SIZE(chip_params))
9248 return &chip_params[chipid];
9252 * t4_prep_adapter - prepare SW and HW for operation
9253 * @adapter: the adapter
9254 * @buf: temporary space of at least VPD_LEN size provided by the caller.
9256 * Initialize adapter SW state for the various HW modules, set initial
9257 * values for some adapter tunables, take PHYs out of reset, and
9258 * initialize the MDIO interface.
9260 int t4_prep_adapter(struct adapter *adapter, u32 *buf)
9266 get_pci_mode(adapter, &adapter->params.pci);
9268 pl_rev = t4_read_reg(adapter, A_PL_REV);
9269 adapter->params.chipid = G_CHIPID(pl_rev);
9270 adapter->params.rev = G_REV(pl_rev);
9271 if (adapter->params.chipid == 0) {
9272 /* T4 did not have chipid in PL_REV (T5 onwards do) */
9273 adapter->params.chipid = CHELSIO_T4;
9275 /* T4A1 chip is not supported */
9276 if (adapter->params.rev == 1) {
9277 CH_ALERT(adapter, "T4 rev 1 chip is not supported.\n");
9282 adapter->chip_params = t4_get_chip_params(chip_id(adapter));
9283 if (adapter->chip_params == NULL)
9286 adapter->params.pci.vpd_cap_addr =
9287 t4_os_find_pci_capability(adapter, PCI_CAP_ID_VPD);
9289 ret = t4_get_flash_params(adapter);
9293 /* Cards with real ASICs have the chipid in the PCIe device id */
9294 t4_os_pci_read_cfg2(adapter, PCI_DEVICE_ID, &device_id);
9295 if (device_id >> 12 == chip_id(adapter))
9296 adapter->params.cim_la_size = CIMLA_SIZE;
9299 adapter->params.fpga = 1;
9300 adapter->params.cim_la_size = 2 * CIMLA_SIZE;
9303 ret = get_vpd_params(adapter, &adapter->params.vpd, device_id, buf);
9307 init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd);
9310 * Default port and clock for debugging in case we can't reach FW.
9312 adapter->params.nports = 1;
9313 adapter->params.portvec = 1;
9314 adapter->params.vpd.cclk = 50000;
9316 /* Set pci completion timeout value to 4 seconds. */
9317 set_pcie_completion_timeout(adapter, 0xd);
9322 * t4_shutdown_adapter - shut down adapter, host & wire
9323 * @adapter: the adapter
9325 * Perform an emergency shutdown of the adapter and stop it from
9326 * continuing any further communication on the ports or DMA to the
9327 * host. This is typically used when the adapter and/or firmware
9328 * have crashed and we want to prevent any further accidental
9329 * communication with the rest of the world. This will also force
9330 * the port Link Status to go down -- if register writes work --
9331 * which should help our peers figure out that we're down.
9333 int t4_shutdown_adapter(struct adapter *adapter)
9337 t4_intr_disable(adapter);
9338 t4_write_reg(adapter, A_DBG_GPIO_EN, 0);
9339 for_each_port(adapter, port) {
9340 u32 a_port_cfg = is_t4(adapter) ?
9341 PORT_REG(port, A_XGMAC_PORT_CFG) :
9342 T5_PORT_REG(port, A_MAC_PORT_CFG);
9344 t4_write_reg(adapter, a_port_cfg,
9345 t4_read_reg(adapter, a_port_cfg)
9346 & ~V_SIGNAL_DET(1));
9348 t4_set_reg_field(adapter, A_SGE_CONTROL, F_GLOBALENABLE, 0);
9354 * t4_bar2_sge_qregs - return BAR2 SGE Queue register information
9355 * @adapter: the adapter
9356 * @qid: the Queue ID
9357 * @qtype: the Ingress or Egress type for @qid
9358 * @user: true if this request is for a user mode queue
9359 * @pbar2_qoffset: BAR2 Queue Offset
9360 * @pbar2_qid: BAR2 Queue ID or 0 for Queue ID inferred SGE Queues
9362 * Returns the BAR2 SGE Queue Registers information associated with the
9363 * indicated Absolute Queue ID. These are passed back in return value
9364 * pointers. @qtype should be T4_BAR2_QTYPE_EGRESS for Egress Queue
9365 * and T4_BAR2_QTYPE_INGRESS for Ingress Queues.
9367 * This may return an error which indicates that BAR2 SGE Queue
9368 * registers aren't available. If an error is not returned, then the
9369 * following values are returned:
9371 * *@pbar2_qoffset: the BAR2 Offset of the @qid Registers
9372 * *@pbar2_qid: the BAR2 SGE Queue ID or 0 of @qid
9374 * If the returned BAR2 Queue ID is 0, then BAR2 SGE registers which
9375 * require the "Inferred Queue ID" ability may be used. E.g. the
9376 * Write Combining Doorbell Buffer. If the BAR2 Queue ID is not 0,
9377 * then these "Inferred Queue ID" register may not be used.
9379 int t4_bar2_sge_qregs(struct adapter *adapter,
9381 enum t4_bar2_qtype qtype,
9384 unsigned int *pbar2_qid)
9386 unsigned int page_shift, page_size, qpp_shift, qpp_mask;
9387 u64 bar2_page_offset, bar2_qoffset;
9388 unsigned int bar2_qid, bar2_qid_offset, bar2_qinferred;
9390 /* T4 doesn't support BAR2 SGE Queue registers for kernel
9393 if (!user && is_t4(adapter))
9396 /* Get our SGE Page Size parameters.
9398 page_shift = adapter->params.sge.page_shift;
9399 page_size = 1 << page_shift;
9401 /* Get the right Queues per Page parameters for our Queue.
9403 qpp_shift = (qtype == T4_BAR2_QTYPE_EGRESS
9404 ? adapter->params.sge.eq_s_qpp
9405 : adapter->params.sge.iq_s_qpp);
9406 qpp_mask = (1 << qpp_shift) - 1;
9408 /* Calculate the basics of the BAR2 SGE Queue register area:
9409 * o The BAR2 page the Queue registers will be in.
9410 * o The BAR2 Queue ID.
9411 * o The BAR2 Queue ID Offset into the BAR2 page.
9413 bar2_page_offset = ((u64)(qid >> qpp_shift) << page_shift);
9414 bar2_qid = qid & qpp_mask;
9415 bar2_qid_offset = bar2_qid * SGE_UDB_SIZE;
9417 /* If the BAR2 Queue ID Offset is less than the Page Size, then the
9418 * hardware will infer the Absolute Queue ID simply from the writes to
9419 * the BAR2 Queue ID Offset within the BAR2 Page (and we need to use a
9420 * BAR2 Queue ID of 0 for those writes). Otherwise, we'll simply
9421 * write to the first BAR2 SGE Queue Area within the BAR2 Page with
9422 * the BAR2 Queue ID and the hardware will infer the Absolute Queue ID
9423 * from the BAR2 Page and BAR2 Queue ID.
9425 * One important censequence of this is that some BAR2 SGE registers
9426 * have a "Queue ID" field and we can write the BAR2 SGE Queue ID
9427 * there. But other registers synthesize the SGE Queue ID purely
9428 * from the writes to the registers -- the Write Combined Doorbell
9429 * Buffer is a good example. These BAR2 SGE Registers are only
9430 * available for those BAR2 SGE Register areas where the SGE Absolute
9431 * Queue ID can be inferred from simple writes.
9433 bar2_qoffset = bar2_page_offset;
9434 bar2_qinferred = (bar2_qid_offset < page_size);
9435 if (bar2_qinferred) {
9436 bar2_qoffset += bar2_qid_offset;
9440 *pbar2_qoffset = bar2_qoffset;
9441 *pbar2_qid = bar2_qid;
9446 * t4_init_devlog_params - initialize adapter->params.devlog
9447 * @adap: the adapter
9448 * @fw_attach: whether we can talk to the firmware
9450 * Initialize various fields of the adapter's Firmware Device Log
9451 * Parameters structure.
9453 int t4_init_devlog_params(struct adapter *adap, int fw_attach)
9455 struct devlog_params *dparams = &adap->params.devlog;
9457 unsigned int devlog_meminfo;
9458 struct fw_devlog_cmd devlog_cmd;
9461 /* If we're dealing with newer firmware, the Device Log Paramerters
9462 * are stored in a designated register which allows us to access the
9463 * Device Log even if we can't talk to the firmware.
9466 t4_read_reg(adap, PCIE_FW_REG(A_PCIE_FW_PF, PCIE_FW_PF_DEVLOG));
9468 unsigned int nentries, nentries128;
9470 dparams->memtype = G_PCIE_FW_PF_DEVLOG_MEMTYPE(pf_dparams);
9471 dparams->start = G_PCIE_FW_PF_DEVLOG_ADDR16(pf_dparams) << 4;
9473 nentries128 = G_PCIE_FW_PF_DEVLOG_NENTRIES128(pf_dparams);
9474 nentries = (nentries128 + 1) * 128;
9475 dparams->size = nentries * sizeof(struct fw_devlog_e);
9481 * For any failing returns ...
9483 memset(dparams, 0, sizeof *dparams);
9486 * If we can't talk to the firmware, there's really nothing we can do
9492 /* Otherwise, ask the firmware for it's Device Log Parameters.
9494 memset(&devlog_cmd, 0, sizeof devlog_cmd);
9495 devlog_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_DEVLOG_CMD) |
9496 F_FW_CMD_REQUEST | F_FW_CMD_READ);
9497 devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd));
9498 ret = t4_wr_mbox(adap, adap->mbox, &devlog_cmd, sizeof(devlog_cmd),
9504 be32_to_cpu(devlog_cmd.memtype_devlog_memaddr16_devlog);
9505 dparams->memtype = G_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(devlog_meminfo);
9506 dparams->start = G_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(devlog_meminfo) << 4;
9507 dparams->size = be32_to_cpu(devlog_cmd.memsize_devlog);
9513 * t4_init_sge_params - initialize adap->params.sge
9514 * @adapter: the adapter
9516 * Initialize various fields of the adapter's SGE Parameters structure.
9518 int t4_init_sge_params(struct adapter *adapter)
9521 struct sge_params *sp = &adapter->params.sge;
9522 unsigned i, tscale = 1;
9524 r = t4_read_reg(adapter, A_SGE_INGRESS_RX_THRESHOLD);
9525 sp->counter_val[0] = G_THRESHOLD_0(r);
9526 sp->counter_val[1] = G_THRESHOLD_1(r);
9527 sp->counter_val[2] = G_THRESHOLD_2(r);
9528 sp->counter_val[3] = G_THRESHOLD_3(r);
9530 if (chip_id(adapter) >= CHELSIO_T6) {
9531 r = t4_read_reg(adapter, A_SGE_ITP_CONTROL);
9532 tscale = G_TSCALE(r);
9539 r = t4_read_reg(adapter, A_SGE_TIMER_VALUE_0_AND_1);
9540 sp->timer_val[0] = core_ticks_to_us(adapter, G_TIMERVALUE0(r)) * tscale;
9541 sp->timer_val[1] = core_ticks_to_us(adapter, G_TIMERVALUE1(r)) * tscale;
9542 r = t4_read_reg(adapter, A_SGE_TIMER_VALUE_2_AND_3);
9543 sp->timer_val[2] = core_ticks_to_us(adapter, G_TIMERVALUE2(r)) * tscale;
9544 sp->timer_val[3] = core_ticks_to_us(adapter, G_TIMERVALUE3(r)) * tscale;
9545 r = t4_read_reg(adapter, A_SGE_TIMER_VALUE_4_AND_5);
9546 sp->timer_val[4] = core_ticks_to_us(adapter, G_TIMERVALUE4(r)) * tscale;
9547 sp->timer_val[5] = core_ticks_to_us(adapter, G_TIMERVALUE5(r)) * tscale;
9549 r = t4_read_reg(adapter, A_SGE_CONM_CTRL);
9550 sp->fl_starve_threshold = G_EGRTHRESHOLD(r) * 2 + 1;
9552 sp->fl_starve_threshold2 = sp->fl_starve_threshold;
9553 else if (is_t5(adapter))
9554 sp->fl_starve_threshold2 = G_EGRTHRESHOLDPACKING(r) * 2 + 1;
9556 sp->fl_starve_threshold2 = G_T6_EGRTHRESHOLDPACKING(r) * 2 + 1;
9558 /* egress queues: log2 of # of doorbells per BAR2 page */
9559 r = t4_read_reg(adapter, A_SGE_EGRESS_QUEUES_PER_PAGE_PF);
9560 r >>= S_QUEUESPERPAGEPF0 +
9561 (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * adapter->pf;
9562 sp->eq_s_qpp = r & M_QUEUESPERPAGEPF0;
9564 /* ingress queues: log2 of # of doorbells per BAR2 page */
9565 r = t4_read_reg(adapter, A_SGE_INGRESS_QUEUES_PER_PAGE_PF);
9566 r >>= S_QUEUESPERPAGEPF0 +
9567 (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * adapter->pf;
9568 sp->iq_s_qpp = r & M_QUEUESPERPAGEPF0;
9570 r = t4_read_reg(adapter, A_SGE_HOST_PAGE_SIZE);
9571 r >>= S_HOSTPAGESIZEPF0 +
9572 (S_HOSTPAGESIZEPF1 - S_HOSTPAGESIZEPF0) * adapter->pf;
9573 sp->page_shift = (r & M_HOSTPAGESIZEPF0) + 10;
9575 r = t4_read_reg(adapter, A_SGE_CONTROL);
9576 sp->sge_control = r;
9577 sp->spg_len = r & F_EGRSTATUSPAGESIZE ? 128 : 64;
9578 sp->fl_pktshift = G_PKTSHIFT(r);
9579 if (chip_id(adapter) <= CHELSIO_T5) {
9580 sp->pad_boundary = 1 << (G_INGPADBOUNDARY(r) +
9581 X_INGPADBOUNDARY_SHIFT);
9583 sp->pad_boundary = 1 << (G_INGPADBOUNDARY(r) +
9584 X_T6_INGPADBOUNDARY_SHIFT);
9587 sp->pack_boundary = sp->pad_boundary;
9589 r = t4_read_reg(adapter, A_SGE_CONTROL2);
9590 if (G_INGPACKBOUNDARY(r) == 0)
9591 sp->pack_boundary = 16;
9593 sp->pack_boundary = 1 << (G_INGPACKBOUNDARY(r) + 5);
9595 for (i = 0; i < SGE_FLBUF_SIZES; i++)
9596 sp->sge_fl_buffer_size[i] = t4_read_reg(adapter,
9597 A_SGE_FL_BUFFER_SIZE0 + (4 * i));
9603 * Read and cache the adapter's compressed filter mode and ingress config.
9605 static void read_filter_mode_and_ingress_config(struct adapter *adap,
9609 struct tp_params *tpp = &adap->params.tp;
9611 t4_tp_pio_read(adap, &tpp->vlan_pri_map, 1, A_TP_VLAN_PRI_MAP,
9613 t4_tp_pio_read(adap, &tpp->ingress_config, 1, A_TP_INGRESS_CONFIG,
9617 * Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field
9618 * shift positions of several elements of the Compressed Filter Tuple
9619 * for this adapter which we need frequently ...
9621 tpp->fcoe_shift = t4_filter_field_shift(adap, F_FCOE);
9622 tpp->port_shift = t4_filter_field_shift(adap, F_PORT);
9623 tpp->vnic_shift = t4_filter_field_shift(adap, F_VNIC_ID);
9624 tpp->vlan_shift = t4_filter_field_shift(adap, F_VLAN);
9625 tpp->tos_shift = t4_filter_field_shift(adap, F_TOS);
9626 tpp->protocol_shift = t4_filter_field_shift(adap, F_PROTOCOL);
9627 tpp->ethertype_shift = t4_filter_field_shift(adap, F_ETHERTYPE);
9628 tpp->macmatch_shift = t4_filter_field_shift(adap, F_MACMATCH);
9629 tpp->matchtype_shift = t4_filter_field_shift(adap, F_MPSHITTYPE);
9630 tpp->frag_shift = t4_filter_field_shift(adap, F_FRAGMENTATION);
9632 if (chip_id(adap) > CHELSIO_T4) {
9633 v = t4_read_reg(adap, LE_HASH_MASK_GEN_IPV4T5(3));
9634 adap->params.tp.hash_filter_mask = v;
9635 v = t4_read_reg(adap, LE_HASH_MASK_GEN_IPV4T5(4));
9636 adap->params.tp.hash_filter_mask |= (u64)v << 32;
9641 * t4_init_tp_params - initialize adap->params.tp
9642 * @adap: the adapter
9644 * Initialize various fields of the adapter's TP Parameters structure.
9646 int t4_init_tp_params(struct adapter *adap, bool sleep_ok)
9649 u32 tx_len, rx_len, r, v;
9650 struct tp_params *tpp = &adap->params.tp;
9652 v = t4_read_reg(adap, A_TP_TIMER_RESOLUTION);
9653 tpp->tre = G_TIMERRESOLUTION(v);
9654 tpp->dack_re = G_DELAYEDACKRESOLUTION(v);
9656 /* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */
9657 for (chan = 0; chan < MAX_NCHAN; chan++)
9658 tpp->tx_modq[chan] = chan;
9660 read_filter_mode_and_ingress_config(adap, sleep_ok);
9662 if (chip_id(adap) > CHELSIO_T5) {
9663 v = t4_read_reg(adap, A_TP_OUT_CONFIG);
9664 tpp->rx_pkt_encap = v & F_CRXPKTENC;
9666 tpp->rx_pkt_encap = false;
9668 rx_len = t4_read_reg(adap, A_TP_PMM_RX_PAGE_SIZE);
9669 tx_len = t4_read_reg(adap, A_TP_PMM_TX_PAGE_SIZE);
9671 r = t4_read_reg(adap, A_TP_PARA_REG2);
9672 rx_len = min(rx_len, G_MAXRXDATA(r));
9673 tx_len = min(tx_len, G_MAXRXDATA(r));
9675 r = t4_read_reg(adap, A_TP_PARA_REG7);
9676 v = min(G_PMMAXXFERLEN0(r), G_PMMAXXFERLEN1(r));
9677 rx_len = min(rx_len, v);
9678 tx_len = min(tx_len, v);
9680 tpp->max_tx_pdu = tx_len;
9681 tpp->max_rx_pdu = rx_len;
9687 * t4_filter_field_shift - calculate filter field shift
9688 * @adap: the adapter
9689 * @filter_sel: the desired field (from TP_VLAN_PRI_MAP bits)
9691 * Return the shift position of a filter field within the Compressed
9692 * Filter Tuple. The filter field is specified via its selection bit
9693 * within TP_VLAN_PRI_MAL (filter mode). E.g. F_VLAN.
9695 int t4_filter_field_shift(const struct adapter *adap, int filter_sel)
9697 unsigned int filter_mode = adap->params.tp.vlan_pri_map;
9701 if ((filter_mode & filter_sel) == 0)
9704 for (sel = 1, field_shift = 0; sel < filter_sel; sel <<= 1) {
9705 switch (filter_mode & sel) {
9707 field_shift += W_FT_FCOE;
9710 field_shift += W_FT_PORT;
9713 field_shift += W_FT_VNIC_ID;
9716 field_shift += W_FT_VLAN;
9719 field_shift += W_FT_TOS;
9722 field_shift += W_FT_PROTOCOL;
9725 field_shift += W_FT_ETHERTYPE;
9728 field_shift += W_FT_MACMATCH;
9731 field_shift += W_FT_MPSHITTYPE;
9733 case F_FRAGMENTATION:
9734 field_shift += W_FT_FRAGMENTATION;
9741 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf, int port_id)
9745 struct port_info *p = adap2pinfo(adap, port_id);
9747 struct vi_info *vi = &p->vi[0];
9749 for (i = 0, j = -1; i <= p->port_id; i++) {
9752 } while ((adap->params.portvec & (1 << j)) == 0);
9756 p->mps_bg_map = t4_get_mps_bg_map(adap, j);
9757 p->rx_e_chan_map = t4_get_rx_e_chan_map(adap, j);
9760 if (!(adap->flags & IS_VF) ||
9761 adap->params.vfres.r_caps & FW_CMD_CAP_PORT) {
9762 t4_update_port_info(p);
9765 ret = t4_alloc_vi(adap, mbox, j, pf, vf, 1, addr, &vi->rss_size,
9766 &vi->vfvld, &vi->vin);
9771 t4_os_set_hw_addr(p, addr);
9773 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
9774 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_RSSINFO) |
9775 V_FW_PARAMS_PARAM_YZ(vi->viid);
9776 ret = t4_query_params(adap, mbox, pf, vf, 1, ¶m, &val);
9778 vi->rss_base = 0xffff;
9780 /* MPASS((val >> 16) == rss_size); */
9781 vi->rss_base = val & 0xffff;
9788 * t4_read_cimq_cfg - read CIM queue configuration
9789 * @adap: the adapter
9790 * @base: holds the queue base addresses in bytes
9791 * @size: holds the queue sizes in bytes
9792 * @thres: holds the queue full thresholds in bytes
9794 * Returns the current configuration of the CIM queues, starting with
9795 * the IBQs, then the OBQs.
9797 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres)
9800 int cim_num_obq = adap->chip_params->cim_num_obq;
9802 for (i = 0; i < CIM_NUM_IBQ; i++) {
9803 t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, F_IBQSELECT |
9805 v = t4_read_reg(adap, A_CIM_QUEUE_CONFIG_CTRL);
9806 /* value is in 256-byte units */
9807 *base++ = G_CIMQBASE(v) * 256;
9808 *size++ = G_CIMQSIZE(v) * 256;
9809 *thres++ = G_QUEFULLTHRSH(v) * 8; /* 8-byte unit */
9811 for (i = 0; i < cim_num_obq; i++) {
9812 t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, F_OBQSELECT |
9814 v = t4_read_reg(adap, A_CIM_QUEUE_CONFIG_CTRL);
9815 /* value is in 256-byte units */
9816 *base++ = G_CIMQBASE(v) * 256;
9817 *size++ = G_CIMQSIZE(v) * 256;
9822 * t4_read_cim_ibq - read the contents of a CIM inbound queue
9823 * @adap: the adapter
9824 * @qid: the queue index
9825 * @data: where to store the queue contents
9826 * @n: capacity of @data in 32-bit words
9828 * Reads the contents of the selected CIM queue starting at address 0 up
9829 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on
9830 * error and the number of 32-bit words actually read on success.
9832 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
9834 int i, err, attempts;
9836 const unsigned int nwords = CIM_IBQ_SIZE * 4;
9838 if (qid > 5 || (n & 3))
9841 addr = qid * nwords;
9845 /* It might take 3-10ms before the IBQ debug read access is allowed.
9846 * Wait for 1 Sec with a delay of 1 usec.
9850 for (i = 0; i < n; i++, addr++) {
9851 t4_write_reg(adap, A_CIM_IBQ_DBG_CFG, V_IBQDBGADDR(addr) |
9853 err = t4_wait_op_done(adap, A_CIM_IBQ_DBG_CFG, F_IBQDBGBUSY, 0,
9857 *data++ = t4_read_reg(adap, A_CIM_IBQ_DBG_DATA);
9859 t4_write_reg(adap, A_CIM_IBQ_DBG_CFG, 0);
9864 * t4_read_cim_obq - read the contents of a CIM outbound queue
9865 * @adap: the adapter
9866 * @qid: the queue index
9867 * @data: where to store the queue contents
9868 * @n: capacity of @data in 32-bit words
9870 * Reads the contents of the selected CIM queue starting at address 0 up
9871 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on
9872 * error and the number of 32-bit words actually read on success.
9874 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
9877 unsigned int addr, v, nwords;
9878 int cim_num_obq = adap->chip_params->cim_num_obq;
9880 if ((qid > (cim_num_obq - 1)) || (n & 3))
9883 t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, F_OBQSELECT |
9884 V_QUENUMSELECT(qid));
9885 v = t4_read_reg(adap, A_CIM_QUEUE_CONFIG_CTRL);
9887 addr = G_CIMQBASE(v) * 64; /* muliple of 256 -> muliple of 4 */
9888 nwords = G_CIMQSIZE(v) * 64; /* same */
9892 for (i = 0; i < n; i++, addr++) {
9893 t4_write_reg(adap, A_CIM_OBQ_DBG_CFG, V_OBQDBGADDR(addr) |
9895 err = t4_wait_op_done(adap, A_CIM_OBQ_DBG_CFG, F_OBQDBGBUSY, 0,
9899 *data++ = t4_read_reg(adap, A_CIM_OBQ_DBG_DATA);
9901 t4_write_reg(adap, A_CIM_OBQ_DBG_CFG, 0);
9907 CIM_CTL_BASE = 0x2000,
9908 CIM_PBT_ADDR_BASE = 0x2800,
9909 CIM_PBT_LRF_BASE = 0x3000,
9910 CIM_PBT_DATA_BASE = 0x3800
9914 * t4_cim_read - read a block from CIM internal address space
9915 * @adap: the adapter
9916 * @addr: the start address within the CIM address space
9917 * @n: number of words to read
9918 * @valp: where to store the result
9920 * Reads a block of 4-byte words from the CIM intenal address space.
9922 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
9927 if (t4_read_reg(adap, A_CIM_HOST_ACC_CTRL) & F_HOSTBUSY)
9930 for ( ; !ret && n--; addr += 4) {
9931 t4_write_reg(adap, A_CIM_HOST_ACC_CTRL, addr);
9932 ret = t4_wait_op_done(adap, A_CIM_HOST_ACC_CTRL, F_HOSTBUSY,
9935 *valp++ = t4_read_reg(adap, A_CIM_HOST_ACC_DATA);
9941 * t4_cim_write - write a block into CIM internal address space
9942 * @adap: the adapter
9943 * @addr: the start address within the CIM address space
9944 * @n: number of words to write
9945 * @valp: set of values to write
9947 * Writes a block of 4-byte words into the CIM intenal address space.
9949 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
9950 const unsigned int *valp)
9954 if (t4_read_reg(adap, A_CIM_HOST_ACC_CTRL) & F_HOSTBUSY)
9957 for ( ; !ret && n--; addr += 4) {
9958 t4_write_reg(adap, A_CIM_HOST_ACC_DATA, *valp++);
9959 t4_write_reg(adap, A_CIM_HOST_ACC_CTRL, addr | F_HOSTWRITE);
9960 ret = t4_wait_op_done(adap, A_CIM_HOST_ACC_CTRL, F_HOSTBUSY,
9966 static int t4_cim_write1(struct adapter *adap, unsigned int addr,
9969 return t4_cim_write(adap, addr, 1, &val);
9973 * t4_cim_ctl_read - read a block from CIM control region
9974 * @adap: the adapter
9975 * @addr: the start address within the CIM control region
9976 * @n: number of words to read
9977 * @valp: where to store the result
9979 * Reads a block of 4-byte words from the CIM control region.
9981 int t4_cim_ctl_read(struct adapter *adap, unsigned int addr, unsigned int n,
9984 return t4_cim_read(adap, addr + CIM_CTL_BASE, n, valp);
9988 * t4_cim_read_la - read CIM LA capture buffer
9989 * @adap: the adapter
9990 * @la_buf: where to store the LA data
9991 * @wrptr: the HW write pointer within the capture buffer
9993 * Reads the contents of the CIM LA buffer with the most recent entry at
9994 * the end of the returned data and with the entry at @wrptr first.
9995 * We try to leave the LA in the running state we find it in.
9997 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr)
10000 unsigned int cfg, val, idx;
10002 ret = t4_cim_read(adap, A_UP_UP_DBG_LA_CFG, 1, &cfg);
10006 if (cfg & F_UPDBGLAEN) { /* LA is running, freeze it */
10007 ret = t4_cim_write1(adap, A_UP_UP_DBG_LA_CFG, 0);
10012 ret = t4_cim_read(adap, A_UP_UP_DBG_LA_CFG, 1, &val);
10016 idx = G_UPDBGLAWRPTR(val);
10020 for (i = 0; i < adap->params.cim_la_size; i++) {
10021 ret = t4_cim_write1(adap, A_UP_UP_DBG_LA_CFG,
10022 V_UPDBGLARDPTR(idx) | F_UPDBGLARDEN);
10025 ret = t4_cim_read(adap, A_UP_UP_DBG_LA_CFG, 1, &val);
10028 if (val & F_UPDBGLARDEN) {
10032 ret = t4_cim_read(adap, A_UP_UP_DBG_LA_DATA, 1, &la_buf[i]);
10036 /* Bits 0-3 of UpDbgLaRdPtr can be between 0000 to 1001 to
10037 * identify the 32-bit portion of the full 312-bit data
10039 if (is_t6(adap) && (idx & 0xf) >= 9)
10040 idx = (idx & 0xff0) + 0x10;
10043 /* address can't exceed 0xfff */
10044 idx &= M_UPDBGLARDPTR;
10047 if (cfg & F_UPDBGLAEN) {
10048 int r = t4_cim_write1(adap, A_UP_UP_DBG_LA_CFG,
10049 cfg & ~F_UPDBGLARDEN);
10057 * t4_tp_read_la - read TP LA capture buffer
10058 * @adap: the adapter
10059 * @la_buf: where to store the LA data
10060 * @wrptr: the HW write pointer within the capture buffer
10062 * Reads the contents of the TP LA buffer with the most recent entry at
10063 * the end of the returned data and with the entry at @wrptr first.
10064 * We leave the LA in the running state we find it in.
10066 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr)
10068 bool last_incomplete;
10069 unsigned int i, cfg, val, idx;
10071 cfg = t4_read_reg(adap, A_TP_DBG_LA_CONFIG) & 0xffff;
10072 if (cfg & F_DBGLAENABLE) /* freeze LA */
10073 t4_write_reg(adap, A_TP_DBG_LA_CONFIG,
10074 adap->params.tp.la_mask | (cfg ^ F_DBGLAENABLE));
10076 val = t4_read_reg(adap, A_TP_DBG_LA_CONFIG);
10077 idx = G_DBGLAWPTR(val);
10078 last_incomplete = G_DBGLAMODE(val) >= 2 && (val & F_DBGLAWHLF) == 0;
10079 if (last_incomplete)
10080 idx = (idx + 1) & M_DBGLARPTR;
10085 val &= ~V_DBGLARPTR(M_DBGLARPTR);
10086 val |= adap->params.tp.la_mask;
10088 for (i = 0; i < TPLA_SIZE; i++) {
10089 t4_write_reg(adap, A_TP_DBG_LA_CONFIG, V_DBGLARPTR(idx) | val);
10090 la_buf[i] = t4_read_reg64(adap, A_TP_DBG_LA_DATAL);
10091 idx = (idx + 1) & M_DBGLARPTR;
10094 /* Wipe out last entry if it isn't valid */
10095 if (last_incomplete)
10096 la_buf[TPLA_SIZE - 1] = ~0ULL;
10098 if (cfg & F_DBGLAENABLE) /* restore running state */
10099 t4_write_reg(adap, A_TP_DBG_LA_CONFIG,
10100 cfg | adap->params.tp.la_mask);
10104 * SGE Hung Ingress DMA Warning Threshold time and Warning Repeat Rate (in
10105 * seconds). If we find one of the SGE Ingress DMA State Machines in the same
10106 * state for more than the Warning Threshold then we'll issue a warning about
10107 * a potential hang. We'll repeat the warning as the SGE Ingress DMA Channel
10108 * appears to be hung every Warning Repeat second till the situation clears.
10109 * If the situation clears, we'll note that as well.
10111 #define SGE_IDMA_WARN_THRESH 1
10112 #define SGE_IDMA_WARN_REPEAT 300
10115 * t4_idma_monitor_init - initialize SGE Ingress DMA Monitor
10116 * @adapter: the adapter
10117 * @idma: the adapter IDMA Monitor state
10119 * Initialize the state of an SGE Ingress DMA Monitor.
10121 void t4_idma_monitor_init(struct adapter *adapter,
10122 struct sge_idma_monitor_state *idma)
10124 /* Initialize the state variables for detecting an SGE Ingress DMA
10125 * hang. The SGE has internal counters which count up on each clock
10126 * tick whenever the SGE finds its Ingress DMA State Engines in the
10127 * same state they were on the previous clock tick. The clock used is
10128 * the Core Clock so we have a limit on the maximum "time" they can
10129 * record; typically a very small number of seconds. For instance,
10130 * with a 600MHz Core Clock, we can only count up to a bit more than
10131 * 7s. So we'll synthesize a larger counter in order to not run the
10132 * risk of having the "timers" overflow and give us the flexibility to
10133 * maintain a Hung SGE State Machine of our own which operates across
10134 * a longer time frame.
10136 idma->idma_1s_thresh = core_ticks_per_usec(adapter) * 1000000; /* 1s */
10137 idma->idma_stalled[0] = idma->idma_stalled[1] = 0;
10141 * t4_idma_monitor - monitor SGE Ingress DMA state
10142 * @adapter: the adapter
10143 * @idma: the adapter IDMA Monitor state
10144 * @hz: number of ticks/second
10145 * @ticks: number of ticks since the last IDMA Monitor call
10147 void t4_idma_monitor(struct adapter *adapter,
10148 struct sge_idma_monitor_state *idma,
10151 int i, idma_same_state_cnt[2];
10153 /* Read the SGE Debug Ingress DMA Same State Count registers. These
10154 * are counters inside the SGE which count up on each clock when the
10155 * SGE finds its Ingress DMA State Engines in the same states they
10156 * were in the previous clock. The counters will peg out at
10157 * 0xffffffff without wrapping around so once they pass the 1s
10158 * threshold they'll stay above that till the IDMA state changes.
10160 t4_write_reg(adapter, A_SGE_DEBUG_INDEX, 13);
10161 idma_same_state_cnt[0] = t4_read_reg(adapter, A_SGE_DEBUG_DATA_HIGH);
10162 idma_same_state_cnt[1] = t4_read_reg(adapter, A_SGE_DEBUG_DATA_LOW);
10164 for (i = 0; i < 2; i++) {
10165 u32 debug0, debug11;
10167 /* If the Ingress DMA Same State Counter ("timer") is less
10168 * than 1s, then we can reset our synthesized Stall Timer and
10169 * continue. If we have previously emitted warnings about a
10170 * potential stalled Ingress Queue, issue a note indicating
10171 * that the Ingress Queue has resumed forward progress.
10173 if (idma_same_state_cnt[i] < idma->idma_1s_thresh) {
10174 if (idma->idma_stalled[i] >= SGE_IDMA_WARN_THRESH*hz)
10175 CH_WARN(adapter, "SGE idma%d, queue %u, "
10176 "resumed after %d seconds\n",
10177 i, idma->idma_qid[i],
10178 idma->idma_stalled[i]/hz);
10179 idma->idma_stalled[i] = 0;
10183 /* Synthesize an SGE Ingress DMA Same State Timer in the Hz
10184 * domain. The first time we get here it'll be because we
10185 * passed the 1s Threshold; each additional time it'll be
10186 * because the RX Timer Callback is being fired on its regular
10189 * If the stall is below our Potential Hung Ingress Queue
10190 * Warning Threshold, continue.
10192 if (idma->idma_stalled[i] == 0) {
10193 idma->idma_stalled[i] = hz;
10194 idma->idma_warn[i] = 0;
10196 idma->idma_stalled[i] += ticks;
10197 idma->idma_warn[i] -= ticks;
10200 if (idma->idma_stalled[i] < SGE_IDMA_WARN_THRESH*hz)
10203 /* We'll issue a warning every SGE_IDMA_WARN_REPEAT seconds.
10205 if (idma->idma_warn[i] > 0)
10207 idma->idma_warn[i] = SGE_IDMA_WARN_REPEAT*hz;
10209 /* Read and save the SGE IDMA State and Queue ID information.
10210 * We do this every time in case it changes across time ...
10211 * can't be too careful ...
10213 t4_write_reg(adapter, A_SGE_DEBUG_INDEX, 0);
10214 debug0 = t4_read_reg(adapter, A_SGE_DEBUG_DATA_LOW);
10215 idma->idma_state[i] = (debug0 >> (i * 9)) & 0x3f;
10217 t4_write_reg(adapter, A_SGE_DEBUG_INDEX, 11);
10218 debug11 = t4_read_reg(adapter, A_SGE_DEBUG_DATA_LOW);
10219 idma->idma_qid[i] = (debug11 >> (i * 16)) & 0xffff;
10221 CH_WARN(adapter, "SGE idma%u, queue %u, potentially stuck in "
10222 " state %u for %d seconds (debug0=%#x, debug11=%#x)\n",
10223 i, idma->idma_qid[i], idma->idma_state[i],
10224 idma->idma_stalled[i]/hz,
10226 t4_sge_decode_idma_state(adapter, idma->idma_state[i]);
10231 * t4_set_vf_mac - Set MAC address for the specified VF
10232 * @adapter: The adapter
10233 * @pf: the PF used to instantiate the VFs
10234 * @vf: one of the VFs instantiated by the specified PF
10235 * @naddr: the number of MAC addresses
10236 * @addr: the MAC address(es) to be set to the specified VF
10238 int t4_set_vf_mac(struct adapter *adapter, unsigned int pf, unsigned int vf,
10239 unsigned int naddr, u8 *addr)
10241 struct fw_acl_mac_cmd cmd;
10243 memset(&cmd, 0, sizeof(cmd));
10244 cmd.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_ACL_MAC_CMD) |
10247 V_FW_ACL_MAC_CMD_PFN(pf) |
10248 V_FW_ACL_MAC_CMD_VFN(vf));
10250 /* Note: Do not enable the ACL */
10251 cmd.en_to_len16 = cpu_to_be32((unsigned int)FW_LEN16(cmd));
10256 memcpy(cmd.macaddr3, addr, sizeof(cmd.macaddr3));
10259 memcpy(cmd.macaddr2, addr, sizeof(cmd.macaddr2));
10262 memcpy(cmd.macaddr1, addr, sizeof(cmd.macaddr1));
10265 memcpy(cmd.macaddr0, addr, sizeof(cmd.macaddr0));
10269 return t4_wr_mbox(adapter, adapter->mbox, &cmd, sizeof(cmd), &cmd);
10273 * t4_read_pace_tbl - read the pace table
10274 * @adap: the adapter
10275 * @pace_vals: holds the returned values
10277 * Returns the values of TP's pace table in microseconds.
10279 void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED])
10283 for (i = 0; i < NTX_SCHED; i++) {
10284 t4_write_reg(adap, A_TP_PACE_TABLE, 0xffff0000 + i);
10285 v = t4_read_reg(adap, A_TP_PACE_TABLE);
10286 pace_vals[i] = dack_ticks_to_usec(adap, v);
10291 * t4_get_tx_sched - get the configuration of a Tx HW traffic scheduler
10292 * @adap: the adapter
10293 * @sched: the scheduler index
10294 * @kbps: the byte rate in Kbps
10295 * @ipg: the interpacket delay in tenths of nanoseconds
10297 * Return the current configuration of a HW Tx scheduler.
10299 void t4_get_tx_sched(struct adapter *adap, unsigned int sched, unsigned int *kbps,
10300 unsigned int *ipg, bool sleep_ok)
10302 unsigned int v, addr, bpt, cpt;
10305 addr = A_TP_TX_MOD_Q1_Q0_RATE_LIMIT - sched / 2;
10306 t4_tp_tm_pio_read(adap, &v, 1, addr, sleep_ok);
10309 bpt = (v >> 8) & 0xff;
10312 *kbps = 0; /* scheduler disabled */
10314 v = (adap->params.vpd.cclk * 1000) / cpt; /* ticks/s */
10315 *kbps = (v * bpt) / 125;
10319 addr = A_TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR - sched / 2;
10320 t4_tp_tm_pio_read(adap, &v, 1, addr, sleep_ok);
10324 *ipg = (10000 * v) / core_ticks_per_usec(adap);
10329 * t4_load_cfg - download config file
10330 * @adap: the adapter
10331 * @cfg_data: the cfg text file to write
10332 * @size: text file size
10334 * Write the supplied config text file to the card's serial flash.
10336 int t4_load_cfg(struct adapter *adap, const u8 *cfg_data, unsigned int size)
10338 int ret, i, n, cfg_addr;
10340 unsigned int flash_cfg_start_sec;
10341 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
10343 cfg_addr = t4_flash_cfg_addr(adap);
10348 flash_cfg_start_sec = addr / SF_SEC_SIZE;
10350 if (size > FLASH_CFG_MAX_SIZE) {
10351 CH_ERR(adap, "cfg file too large, max is %u bytes\n",
10352 FLASH_CFG_MAX_SIZE);
10356 i = DIV_ROUND_UP(FLASH_CFG_MAX_SIZE, /* # of sectors spanned */
10358 ret = t4_flash_erase_sectors(adap, flash_cfg_start_sec,
10359 flash_cfg_start_sec + i - 1);
10361 * If size == 0 then we're simply erasing the FLASH sectors associated
10362 * with the on-adapter Firmware Configuration File.
10364 if (ret || size == 0)
10367 /* this will write to the flash up to SF_PAGE_SIZE at a time */
10368 for (i = 0; i< size; i+= SF_PAGE_SIZE) {
10369 if ( (size - i) < SF_PAGE_SIZE)
10373 ret = t4_write_flash(adap, addr, n, cfg_data, 1);
10377 addr += SF_PAGE_SIZE;
10378 cfg_data += SF_PAGE_SIZE;
10383 CH_ERR(adap, "config file %s failed %d\n",
10384 (size == 0 ? "clear" : "download"), ret);
10389 * t5_fw_init_extern_mem - initialize the external memory
10390 * @adap: the adapter
10392 * Initializes the external memory on T5.
10394 int t5_fw_init_extern_mem(struct adapter *adap)
10396 u32 params[1], val[1];
10402 val[0] = 0xff; /* Initialize all MCs */
10403 params[0] = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
10404 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_MCINIT));
10405 ret = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1, params, val,
10406 FW_CMD_MAX_TIMEOUT);
10411 /* BIOS boot headers */
10412 typedef struct pci_expansion_rom_header {
10413 u8 signature[2]; /* ROM Signature. Should be 0xaa55 */
10414 u8 reserved[22]; /* Reserved per processor Architecture data */
10415 u8 pcir_offset[2]; /* Offset to PCI Data Structure */
10416 } pci_exp_rom_header_t; /* PCI_EXPANSION_ROM_HEADER */
10418 /* Legacy PCI Expansion ROM Header */
10419 typedef struct legacy_pci_expansion_rom_header {
10420 u8 signature[2]; /* ROM Signature. Should be 0xaa55 */
10421 u8 size512; /* Current Image Size in units of 512 bytes */
10422 u8 initentry_point[4];
10423 u8 cksum; /* Checksum computed on the entire Image */
10424 u8 reserved[16]; /* Reserved */
10425 u8 pcir_offset[2]; /* Offset to PCI Data Struture */
10426 } legacy_pci_exp_rom_header_t; /* LEGACY_PCI_EXPANSION_ROM_HEADER */
10428 /* EFI PCI Expansion ROM Header */
10429 typedef struct efi_pci_expansion_rom_header {
10430 u8 signature[2]; // ROM signature. The value 0xaa55
10431 u8 initialization_size[2]; /* Units 512. Includes this header */
10432 u8 efi_signature[4]; /* Signature from EFI image header. 0x0EF1 */
10433 u8 efi_subsystem[2]; /* Subsystem value for EFI image header */
10434 u8 efi_machine_type[2]; /* Machine type from EFI image header */
10435 u8 compression_type[2]; /* Compression type. */
10437 * Compression type definition
10438 * 0x0: uncompressed
10440 * 0x2-0xFFFF: Reserved
10442 u8 reserved[8]; /* Reserved */
10443 u8 efi_image_header_offset[2]; /* Offset to EFI Image */
10444 u8 pcir_offset[2]; /* Offset to PCI Data Structure */
10445 } efi_pci_exp_rom_header_t; /* EFI PCI Expansion ROM Header */
10447 /* PCI Data Structure Format */
10448 typedef struct pcir_data_structure { /* PCI Data Structure */
10449 u8 signature[4]; /* Signature. The string "PCIR" */
10450 u8 vendor_id[2]; /* Vendor Identification */
10451 u8 device_id[2]; /* Device Identification */
10452 u8 vital_product[2]; /* Pointer to Vital Product Data */
10453 u8 length[2]; /* PCIR Data Structure Length */
10454 u8 revision; /* PCIR Data Structure Revision */
10455 u8 class_code[3]; /* Class Code */
10456 u8 image_length[2]; /* Image Length. Multiple of 512B */
10457 u8 code_revision[2]; /* Revision Level of Code/Data */
10458 u8 code_type; /* Code Type. */
10460 * PCI Expansion ROM Code Types
10461 * 0x00: Intel IA-32, PC-AT compatible. Legacy
10462 * 0x01: Open Firmware standard for PCI. FCODE
10463 * 0x02: Hewlett-Packard PA RISC. HP reserved
10464 * 0x03: EFI Image. EFI
10465 * 0x04-0xFF: Reserved.
10467 u8 indicator; /* Indicator. Identifies the last image in the ROM */
10468 u8 reserved[2]; /* Reserved */
10469 } pcir_data_t; /* PCI__DATA_STRUCTURE */
10471 /* BOOT constants */
10473 BOOT_FLASH_BOOT_ADDR = 0x0,/* start address of boot image in flash */
10474 BOOT_SIGNATURE = 0xaa55, /* signature of BIOS boot ROM */
10475 BOOT_SIZE_INC = 512, /* image size measured in 512B chunks */
10476 BOOT_MIN_SIZE = sizeof(pci_exp_rom_header_t), /* basic header */
10477 BOOT_MAX_SIZE = 1024*BOOT_SIZE_INC, /* 1 byte * length increment */
10478 VENDOR_ID = 0x1425, /* Vendor ID */
10479 PCIR_SIGNATURE = 0x52494350 /* PCIR signature */
10483 * modify_device_id - Modifies the device ID of the Boot BIOS image
10484 * @adatper: the device ID to write.
10485 * @boot_data: the boot image to modify.
10487 * Write the supplied device ID to the boot BIOS image.
10489 static void modify_device_id(int device_id, u8 *boot_data)
10491 legacy_pci_exp_rom_header_t *header;
10492 pcir_data_t *pcir_header;
10493 u32 cur_header = 0;
10496 * Loop through all chained images and change the device ID's
10499 header = (legacy_pci_exp_rom_header_t *) &boot_data[cur_header];
10500 pcir_header = (pcir_data_t *) &boot_data[cur_header +
10501 le16_to_cpu(*(u16*)header->pcir_offset)];
10504 * Only modify the Device ID if code type is Legacy or HP.
10505 * 0x00: Okay to modify
10506 * 0x01: FCODE. Do not be modify
10507 * 0x03: Okay to modify
10508 * 0x04-0xFF: Do not modify
10510 if (pcir_header->code_type == 0x00) {
10515 * Modify Device ID to match current adatper
10517 *(u16*) pcir_header->device_id = device_id;
10520 * Set checksum temporarily to 0.
10521 * We will recalculate it later.
10523 header->cksum = 0x0;
10526 * Calculate and update checksum
10528 for (i = 0; i < (header->size512 * 512); i++)
10529 csum += (u8)boot_data[cur_header + i];
10532 * Invert summed value to create the checksum
10533 * Writing new checksum value directly to the boot data
10535 boot_data[cur_header + 7] = -csum;
10537 } else if (pcir_header->code_type == 0x03) {
10540 * Modify Device ID to match current adatper
10542 *(u16*) pcir_header->device_id = device_id;
10548 * Check indicator element to identify if this is the last
10549 * image in the ROM.
10551 if (pcir_header->indicator & 0x80)
10555 * Move header pointer up to the next image in the ROM.
10557 cur_header += header->size512 * 512;
10562 * t4_load_boot - download boot flash
10563 * @adapter: the adapter
10564 * @boot_data: the boot image to write
10565 * @boot_addr: offset in flash to write boot_data
10566 * @size: image size
10568 * Write the supplied boot image to the card's serial flash.
10569 * The boot image has the following sections: a 28-byte header and the
10572 int t4_load_boot(struct adapter *adap, u8 *boot_data,
10573 unsigned int boot_addr, unsigned int size)
10575 pci_exp_rom_header_t *header;
10577 pcir_data_t *pcir_header;
10579 uint16_t device_id;
10581 unsigned int boot_sector = (boot_addr * 1024 );
10582 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
10585 * Make sure the boot image does not encroach on the firmware region
10587 if ((boot_sector + size) >> 16 > FLASH_FW_START_SEC) {
10588 CH_ERR(adap, "boot image encroaching on firmware region\n");
10593 * The boot sector is comprised of the Expansion-ROM boot, iSCSI boot,
10594 * and Boot configuration data sections. These 3 boot sections span
10595 * sectors 0 to 7 in flash and live right before the FW image location.
10597 i = DIV_ROUND_UP(size ? size : FLASH_FW_START,
10599 ret = t4_flash_erase_sectors(adap, boot_sector >> 16,
10600 (boot_sector >> 16) + i - 1);
10603 * If size == 0 then we're simply erasing the FLASH sectors associated
10604 * with the on-adapter option ROM file
10606 if (ret || (size == 0))
10609 /* Get boot header */
10610 header = (pci_exp_rom_header_t *)boot_data;
10611 pcir_offset = le16_to_cpu(*(u16 *)header->pcir_offset);
10612 /* PCIR Data Structure */
10613 pcir_header = (pcir_data_t *) &boot_data[pcir_offset];
10616 * Perform some primitive sanity testing to avoid accidentally
10617 * writing garbage over the boot sectors. We ought to check for
10618 * more but it's not worth it for now ...
10620 if (size < BOOT_MIN_SIZE || size > BOOT_MAX_SIZE) {
10621 CH_ERR(adap, "boot image too small/large\n");
10625 #ifndef CHELSIO_T4_DIAGS
10627 * Check BOOT ROM header signature
10629 if (le16_to_cpu(*(u16*)header->signature) != BOOT_SIGNATURE ) {
10630 CH_ERR(adap, "Boot image missing signature\n");
10635 * Check PCI header signature
10637 if (le32_to_cpu(*(u32*)pcir_header->signature) != PCIR_SIGNATURE) {
10638 CH_ERR(adap, "PCI header missing signature\n");
10643 * Check Vendor ID matches Chelsio ID
10645 if (le16_to_cpu(*(u16*)pcir_header->vendor_id) != VENDOR_ID) {
10646 CH_ERR(adap, "Vendor ID missing signature\n");
10652 * Retrieve adapter's device ID
10654 t4_os_pci_read_cfg2(adap, PCI_DEVICE_ID, &device_id);
10655 /* Want to deal with PF 0 so I strip off PF 4 indicator */
10656 device_id = device_id & 0xf0ff;
10659 * Check PCIE Device ID
10661 if (le16_to_cpu(*(u16*)pcir_header->device_id) != device_id) {
10663 * Change the device ID in the Boot BIOS image to match
10664 * the Device ID of the current adapter.
10666 modify_device_id(device_id, boot_data);
10670 * Skip over the first SF_PAGE_SIZE worth of data and write it after
10671 * we finish copying the rest of the boot image. This will ensure
10672 * that the BIOS boot header will only be written if the boot image
10673 * was written in full.
10675 addr = boot_sector;
10676 for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) {
10677 addr += SF_PAGE_SIZE;
10678 boot_data += SF_PAGE_SIZE;
10679 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, boot_data, 0);
10684 ret = t4_write_flash(adap, boot_sector, SF_PAGE_SIZE,
10685 (const u8 *)header, 0);
10689 CH_ERR(adap, "boot image download failed, error %d\n", ret);
10694 * t4_flash_bootcfg_addr - return the address of the flash optionrom configuration
10695 * @adapter: the adapter
10697 * Return the address within the flash where the OptionROM Configuration
10698 * is stored, or an error if the device FLASH is too small to contain
10699 * a OptionROM Configuration.
10701 static int t4_flash_bootcfg_addr(struct adapter *adapter)
10704 * If the device FLASH isn't large enough to hold a Firmware
10705 * Configuration File, return an error.
10707 if (adapter->params.sf_size < FLASH_BOOTCFG_START + FLASH_BOOTCFG_MAX_SIZE)
10710 return FLASH_BOOTCFG_START;
10713 int t4_load_bootcfg(struct adapter *adap,const u8 *cfg_data, unsigned int size)
10715 int ret, i, n, cfg_addr;
10717 unsigned int flash_cfg_start_sec;
10718 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
10720 cfg_addr = t4_flash_bootcfg_addr(adap);
10725 flash_cfg_start_sec = addr / SF_SEC_SIZE;
10727 if (size > FLASH_BOOTCFG_MAX_SIZE) {
10728 CH_ERR(adap, "bootcfg file too large, max is %u bytes\n",
10729 FLASH_BOOTCFG_MAX_SIZE);
10733 i = DIV_ROUND_UP(FLASH_BOOTCFG_MAX_SIZE,/* # of sectors spanned */
10735 ret = t4_flash_erase_sectors(adap, flash_cfg_start_sec,
10736 flash_cfg_start_sec + i - 1);
10739 * If size == 0 then we're simply erasing the FLASH sectors associated
10740 * with the on-adapter OptionROM Configuration File.
10742 if (ret || size == 0)
10745 /* this will write to the flash up to SF_PAGE_SIZE at a time */
10746 for (i = 0; i< size; i+= SF_PAGE_SIZE) {
10747 if ( (size - i) < SF_PAGE_SIZE)
10751 ret = t4_write_flash(adap, addr, n, cfg_data, 0);
10755 addr += SF_PAGE_SIZE;
10756 cfg_data += SF_PAGE_SIZE;
10761 CH_ERR(adap, "boot config data %s failed %d\n",
10762 (size == 0 ? "clear" : "download"), ret);
10767 * t4_set_filter_mode - configure the optional components of filter tuples
10768 * @adap: the adapter
10769 * @mode_map: a bitmap selcting which optional filter components to enable
10770 * @sleep_ok: if true we may sleep while awaiting command completion
10772 * Sets the filter mode by selecting the optional components to enable
10773 * in filter tuples. Returns 0 on success and a negative error if the
10774 * requested mode needs more bits than are available for optional
10777 int t4_set_filter_mode(struct adapter *adap, unsigned int mode_map,
10780 static u8 width[] = { 1, 3, 17, 17, 8, 8, 16, 9, 3, 1 };
10784 for (i = S_FCOE; i <= S_FRAGMENTATION; i++)
10785 if (mode_map & (1 << i))
10787 if (nbits > FILTER_OPT_LEN)
10789 t4_tp_pio_write(adap, &mode_map, 1, A_TP_VLAN_PRI_MAP, sleep_ok);
10790 read_filter_mode_and_ingress_config(adap, sleep_ok);
10796 * t4_clr_port_stats - clear port statistics
10797 * @adap: the adapter
10798 * @idx: the port index
10800 * Clear HW statistics for the given port.
10802 void t4_clr_port_stats(struct adapter *adap, int idx)
10805 u32 bgmap = adap2pinfo(adap, idx)->mps_bg_map;
10806 u32 port_base_addr;
10809 port_base_addr = PORT_BASE(idx);
10811 port_base_addr = T5_PORT_BASE(idx);
10813 for (i = A_MPS_PORT_STAT_TX_PORT_BYTES_L;
10814 i <= A_MPS_PORT_STAT_TX_PORT_PPP7_H; i += 8)
10815 t4_write_reg(adap, port_base_addr + i, 0);
10816 for (i = A_MPS_PORT_STAT_RX_PORT_BYTES_L;
10817 i <= A_MPS_PORT_STAT_RX_PORT_LESS_64B_H; i += 8)
10818 t4_write_reg(adap, port_base_addr + i, 0);
10819 for (i = 0; i < 4; i++)
10820 if (bgmap & (1 << i)) {
10822 A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L + i * 8, 0);
10824 A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L + i * 8, 0);
10829 * t4_i2c_io - read/write I2C data from adapter
10830 * @adap: the adapter
10831 * @port: Port number if per-port device; <0 if not
10832 * @devid: per-port device ID or absolute device ID
10833 * @offset: byte offset into device I2C space
10834 * @len: byte length of I2C space data
10835 * @buf: buffer in which to return I2C data for read
10836 * buffer which holds the I2C data for write
10837 * @write: if true, do a write; else do a read
10838 * Reads/Writes the I2C data from/to the indicated device and location.
10840 int t4_i2c_io(struct adapter *adap, unsigned int mbox,
10841 int port, unsigned int devid,
10842 unsigned int offset, unsigned int len,
10843 u8 *buf, bool write)
10845 struct fw_ldst_cmd ldst_cmd, ldst_rpl;
10846 unsigned int i2c_max = sizeof(ldst_cmd.u.i2c.data);
10849 if (len > I2C_PAGE_SIZE)
10852 /* Dont allow reads that spans multiple pages */
10853 if (offset < I2C_PAGE_SIZE && offset + len > I2C_PAGE_SIZE)
10856 memset(&ldst_cmd, 0, sizeof(ldst_cmd));
10857 ldst_cmd.op_to_addrspace =
10858 cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
10860 (write ? F_FW_CMD_WRITE : F_FW_CMD_READ) |
10861 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_I2C));
10862 ldst_cmd.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst_cmd));
10863 ldst_cmd.u.i2c.pid = (port < 0 ? 0xff : port);
10864 ldst_cmd.u.i2c.did = devid;
10867 unsigned int i2c_len = (len < i2c_max) ? len : i2c_max;
10869 ldst_cmd.u.i2c.boffset = offset;
10870 ldst_cmd.u.i2c.blen = i2c_len;
10873 memcpy(ldst_cmd.u.i2c.data, buf, i2c_len);
10875 ret = t4_wr_mbox(adap, mbox, &ldst_cmd, sizeof(ldst_cmd),
10876 write ? NULL : &ldst_rpl);
10881 memcpy(buf, ldst_rpl.u.i2c.data, i2c_len);
10890 int t4_i2c_rd(struct adapter *adap, unsigned int mbox,
10891 int port, unsigned int devid,
10892 unsigned int offset, unsigned int len,
10895 return t4_i2c_io(adap, mbox, port, devid, offset, len, buf, false);
10898 int t4_i2c_wr(struct adapter *adap, unsigned int mbox,
10899 int port, unsigned int devid,
10900 unsigned int offset, unsigned int len,
10903 return t4_i2c_io(adap, mbox, port, devid, offset, len, buf, true);
10907 * t4_sge_ctxt_rd - read an SGE context through FW
10908 * @adap: the adapter
10909 * @mbox: mailbox to use for the FW command
10910 * @cid: the context id
10911 * @ctype: the context type
10912 * @data: where to store the context data
10914 * Issues a FW command through the given mailbox to read an SGE context.
10916 int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid,
10917 enum ctxt_type ctype, u32 *data)
10920 struct fw_ldst_cmd c;
10922 if (ctype == CTXT_EGRESS)
10923 ret = FW_LDST_ADDRSPC_SGE_EGRC;
10924 else if (ctype == CTXT_INGRESS)
10925 ret = FW_LDST_ADDRSPC_SGE_INGC;
10926 else if (ctype == CTXT_FLM)
10927 ret = FW_LDST_ADDRSPC_SGE_FLMC;
10929 ret = FW_LDST_ADDRSPC_SGE_CONMC;
10931 memset(&c, 0, sizeof(c));
10932 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
10933 F_FW_CMD_REQUEST | F_FW_CMD_READ |
10934 V_FW_LDST_CMD_ADDRSPACE(ret));
10935 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
10936 c.u.idctxt.physid = cpu_to_be32(cid);
10938 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
10940 data[0] = be32_to_cpu(c.u.idctxt.ctxt_data0);
10941 data[1] = be32_to_cpu(c.u.idctxt.ctxt_data1);
10942 data[2] = be32_to_cpu(c.u.idctxt.ctxt_data2);
10943 data[3] = be32_to_cpu(c.u.idctxt.ctxt_data3);
10944 data[4] = be32_to_cpu(c.u.idctxt.ctxt_data4);
10945 data[5] = be32_to_cpu(c.u.idctxt.ctxt_data5);
10951 * t4_sge_ctxt_rd_bd - read an SGE context bypassing FW
10952 * @adap: the adapter
10953 * @cid: the context id
10954 * @ctype: the context type
10955 * @data: where to store the context data
10957 * Reads an SGE context directly, bypassing FW. This is only for
10958 * debugging when FW is unavailable.
10960 int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid, enum ctxt_type ctype,
10965 t4_write_reg(adap, A_SGE_CTXT_CMD, V_CTXTQID(cid) | V_CTXTTYPE(ctype));
10966 ret = t4_wait_op_done(adap, A_SGE_CTXT_CMD, F_BUSY, 0, 3, 1);
10968 for (i = A_SGE_CTXT_DATA0; i <= A_SGE_CTXT_DATA5; i += 4)
10969 *data++ = t4_read_reg(adap, i);
10973 int t4_sched_config(struct adapter *adapter, int type, int minmaxen,
10976 struct fw_sched_cmd cmd;
10978 memset(&cmd, 0, sizeof(cmd));
10979 cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) |
10982 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
10984 cmd.u.config.sc = FW_SCHED_SC_CONFIG;
10985 cmd.u.config.type = type;
10986 cmd.u.config.minmaxen = minmaxen;
10988 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd),
10992 int t4_sched_params(struct adapter *adapter, int type, int level, int mode,
10993 int rateunit, int ratemode, int channel, int cl,
10994 int minrate, int maxrate, int weight, int pktsize,
10995 int burstsize, int sleep_ok)
10997 struct fw_sched_cmd cmd;
10999 memset(&cmd, 0, sizeof(cmd));
11000 cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) |
11003 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
11005 cmd.u.params.sc = FW_SCHED_SC_PARAMS;
11006 cmd.u.params.type = type;
11007 cmd.u.params.level = level;
11008 cmd.u.params.mode = mode;
11009 cmd.u.params.ch = channel;
11010 cmd.u.params.cl = cl;
11011 cmd.u.params.unit = rateunit;
11012 cmd.u.params.rate = ratemode;
11013 cmd.u.params.min = cpu_to_be32(minrate);
11014 cmd.u.params.max = cpu_to_be32(maxrate);
11015 cmd.u.params.weight = cpu_to_be16(weight);
11016 cmd.u.params.pktsize = cpu_to_be16(pktsize);
11017 cmd.u.params.burstsize = cpu_to_be16(burstsize);
11019 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd),
11023 int t4_sched_params_ch_rl(struct adapter *adapter, int channel, int ratemode,
11024 unsigned int maxrate, int sleep_ok)
11026 struct fw_sched_cmd cmd;
11028 memset(&cmd, 0, sizeof(cmd));
11029 cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) |
11032 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
11034 cmd.u.params.sc = FW_SCHED_SC_PARAMS;
11035 cmd.u.params.type = FW_SCHED_TYPE_PKTSCHED;
11036 cmd.u.params.level = FW_SCHED_PARAMS_LEVEL_CH_RL;
11037 cmd.u.params.ch = channel;
11038 cmd.u.params.rate = ratemode; /* REL or ABS */
11039 cmd.u.params.max = cpu_to_be32(maxrate);/* % or kbps */
11041 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd),
11045 int t4_sched_params_cl_wrr(struct adapter *adapter, int channel, int cl,
11046 int weight, int sleep_ok)
11048 struct fw_sched_cmd cmd;
11050 if (weight < 0 || weight > 100)
11053 memset(&cmd, 0, sizeof(cmd));
11054 cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) |
11057 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
11059 cmd.u.params.sc = FW_SCHED_SC_PARAMS;
11060 cmd.u.params.type = FW_SCHED_TYPE_PKTSCHED;
11061 cmd.u.params.level = FW_SCHED_PARAMS_LEVEL_CL_WRR;
11062 cmd.u.params.ch = channel;
11063 cmd.u.params.cl = cl;
11064 cmd.u.params.weight = cpu_to_be16(weight);
11066 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd),
11070 int t4_sched_params_cl_rl_kbps(struct adapter *adapter, int channel, int cl,
11071 int mode, unsigned int maxrate, int pktsize, int sleep_ok)
11073 struct fw_sched_cmd cmd;
11075 memset(&cmd, 0, sizeof(cmd));
11076 cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) |
11079 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
11081 cmd.u.params.sc = FW_SCHED_SC_PARAMS;
11082 cmd.u.params.type = FW_SCHED_TYPE_PKTSCHED;
11083 cmd.u.params.level = FW_SCHED_PARAMS_LEVEL_CL_RL;
11084 cmd.u.params.mode = mode;
11085 cmd.u.params.ch = channel;
11086 cmd.u.params.cl = cl;
11087 cmd.u.params.unit = FW_SCHED_PARAMS_UNIT_BITRATE;
11088 cmd.u.params.rate = FW_SCHED_PARAMS_RATE_ABS;
11089 cmd.u.params.max = cpu_to_be32(maxrate);
11090 cmd.u.params.pktsize = cpu_to_be16(pktsize);
11092 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd),
11097 * t4_config_watchdog - configure (enable/disable) a watchdog timer
11098 * @adapter: the adapter
11099 * @mbox: mailbox to use for the FW command
11100 * @pf: the PF owning the queue
11101 * @vf: the VF owning the queue
11102 * @timeout: watchdog timeout in ms
11103 * @action: watchdog timer / action
11105 * There are separate watchdog timers for each possible watchdog
11106 * action. Configure one of the watchdog timers by setting a non-zero
11107 * timeout. Disable a watchdog timer by using a timeout of zero.
11109 int t4_config_watchdog(struct adapter *adapter, unsigned int mbox,
11110 unsigned int pf, unsigned int vf,
11111 unsigned int timeout, unsigned int action)
11113 struct fw_watchdog_cmd wdog;
11114 unsigned int ticks;
11117 * The watchdog command expects a timeout in units of 10ms so we need
11118 * to convert it here (via rounding) and force a minimum of one 10ms
11119 * "tick" if the timeout is non-zero but the conversion results in 0
11122 ticks = (timeout + 5)/10;
11123 if (timeout && !ticks)
11126 memset(&wdog, 0, sizeof wdog);
11127 wdog.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_WATCHDOG_CMD) |
11130 V_FW_PARAMS_CMD_PFN(pf) |
11131 V_FW_PARAMS_CMD_VFN(vf));
11132 wdog.retval_len16 = cpu_to_be32(FW_LEN16(wdog));
11133 wdog.timeout = cpu_to_be32(ticks);
11134 wdog.action = cpu_to_be32(action);
11136 return t4_wr_mbox(adapter, mbox, &wdog, sizeof wdog, NULL);
11139 int t4_get_devlog_level(struct adapter *adapter, unsigned int *level)
11141 struct fw_devlog_cmd devlog_cmd;
11144 memset(&devlog_cmd, 0, sizeof(devlog_cmd));
11145 devlog_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_DEVLOG_CMD) |
11146 F_FW_CMD_REQUEST | F_FW_CMD_READ);
11147 devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd));
11148 ret = t4_wr_mbox(adapter, adapter->mbox, &devlog_cmd,
11149 sizeof(devlog_cmd), &devlog_cmd);
11153 *level = devlog_cmd.level;
11157 int t4_set_devlog_level(struct adapter *adapter, unsigned int level)
11159 struct fw_devlog_cmd devlog_cmd;
11161 memset(&devlog_cmd, 0, sizeof(devlog_cmd));
11162 devlog_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_DEVLOG_CMD) |
11165 devlog_cmd.level = level;
11166 devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd));
11167 return t4_wr_mbox(adapter, adapter->mbox, &devlog_cmd,
11168 sizeof(devlog_cmd), &devlog_cmd);
11171 int t4_configure_add_smac(struct adapter *adap)
11173 unsigned int param, val;
11176 adap->params.smac_add_support = 0;
11177 param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
11178 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_ADD_SMAC));
11179 /* Query FW to check if FW supports adding source mac address
11180 * to TCAM feature or not.
11181 * If FW returns 1, driver can use this feature and driver need to send
11182 * FW_PARAMS_PARAM_DEV_ADD_SMAC write command with value 1 to
11183 * enable adding smac to TCAM.
11185 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, ¶m, &val);
11190 ret = t4_set_params(adap, adap->mbox, adap->pf, 0, 1,
11193 /* Firmware allows adding explicit TCAM entries.
11194 * Save this internally.
11196 adap->params.smac_add_support = 1;
11202 int t4_configure_ringbb(struct adapter *adap)
11204 unsigned int param, val;
11207 param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
11208 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_RING_BACKBONE));
11209 /* Query FW to check if FW supports ring switch feature or not.
11210 * If FW returns 1, driver can use this feature and driver need to send
11211 * FW_PARAMS_PARAM_DEV_RING_BACKBONE write command with value 1 to
11212 * enable the ring backbone configuration.
11214 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, ¶m, &val);
11216 CH_ERR(adap, "Querying FW using Ring backbone params command failed, err=%d\n",
11222 CH_ERR(adap, "FW doesnot support ringbackbone features\n");
11226 ret = t4_set_params(adap, adap->mbox, adap->pf, 0, 1, ¶m, &val);
11228 CH_ERR(adap, "Could not set Ringbackbone, err= %d\n",
11238 * t4_set_vlan_acl - Set a VLAN id for the specified VF
11239 * @adapter: the adapter
11240 * @mbox: mailbox to use for the FW command
11241 * @vf: one of the VFs instantiated by the specified PF
11242 * @vlan: The vlanid to be set
11245 int t4_set_vlan_acl(struct adapter *adap, unsigned int mbox, unsigned int vf,
11248 struct fw_acl_vlan_cmd vlan_cmd;
11249 unsigned int enable;
11251 enable = (vlan ? F_FW_ACL_VLAN_CMD_EN : 0);
11252 memset(&vlan_cmd, 0, sizeof(vlan_cmd));
11253 vlan_cmd.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_ACL_VLAN_CMD) |
11257 V_FW_ACL_VLAN_CMD_PFN(adap->pf) |
11258 V_FW_ACL_VLAN_CMD_VFN(vf));
11259 vlan_cmd.en_to_len16 = cpu_to_be32(enable | FW_LEN16(vlan_cmd));
11260 /* Drop all packets that donot match vlan id */
11261 vlan_cmd.dropnovlan_fm = (enable
11262 ? (F_FW_ACL_VLAN_CMD_DROPNOVLAN |
11263 F_FW_ACL_VLAN_CMD_FM)
11266 vlan_cmd.nvlan = 1;
11267 vlan_cmd.vlanid[0] = cpu_to_be16(vlan);
11270 return t4_wr_mbox(adap, adap->mbox, &vlan_cmd, sizeof(vlan_cmd), NULL);
11274 * t4_del_mac - Removes the exact-match filter for a MAC address
11275 * @adap: the adapter
11276 * @mbox: mailbox to use for the FW command
11278 * @addr: the MAC address value
11279 * @smac: if true, delete from only the smac region of MPS
11281 * Modifies an exact-match filter and sets it to the new MAC address if
11282 * @idx >= 0, or adds the MAC address to a new filter if @idx < 0. In the
11283 * latter case the address is added persistently if @persist is %true.
11285 * Returns a negative error number or the index of the filter with the new
11286 * MAC value. Note that this index may differ from @idx.
11288 int t4_del_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
11289 const u8 *addr, bool smac)
11292 struct fw_vi_mac_cmd c;
11293 struct fw_vi_mac_exact *p = c.u.exact;
11294 unsigned int max_mac_addr = adap->chip_params->mps_tcam_size;
11296 memset(&c, 0, sizeof(c));
11297 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) |
11298 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
11299 V_FW_VI_MAC_CMD_VIID(viid));
11300 c.freemacs_to_len16 = cpu_to_be32(
11301 V_FW_CMD_LEN16(1) |
11302 (smac ? F_FW_VI_MAC_CMD_IS_SMAC : 0));
11304 memcpy(p->macaddr, addr, sizeof(p->macaddr));
11305 p->valid_to_idx = cpu_to_be16(
11306 F_FW_VI_MAC_CMD_VALID |
11307 V_FW_VI_MAC_CMD_IDX(FW_VI_MAC_MAC_BASED_FREE));
11309 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
11311 ret = G_FW_VI_MAC_CMD_IDX(be16_to_cpu(p->valid_to_idx));
11312 if (ret < max_mac_addr)
11320 * t4_add_mac - Adds an exact-match filter for a MAC address
11321 * @adap: the adapter
11322 * @mbox: mailbox to use for the FW command
11324 * @idx: index of existing filter for old value of MAC address, or -1
11325 * @addr: the new MAC address value
11326 * @persist: whether a new MAC allocation should be persistent
11327 * @add_smt: if true also add the address to the HW SMT
11328 * @smac: if true, update only the smac region of MPS
11330 * Modifies an exact-match filter and sets it to the new MAC address if
11331 * @idx >= 0, or adds the MAC address to a new filter if @idx < 0. In the
11332 * latter case the address is added persistently if @persist is %true.
11334 * Returns a negative error number or the index of the filter with the new
11335 * MAC value. Note that this index may differ from @idx.
11337 int t4_add_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
11338 int idx, const u8 *addr, bool persist, u8 *smt_idx, bool smac)
11341 struct fw_vi_mac_cmd c;
11342 struct fw_vi_mac_exact *p = c.u.exact;
11343 unsigned int max_mac_addr = adap->chip_params->mps_tcam_size;
11345 if (idx < 0) /* new allocation */
11346 idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC;
11347 mode = smt_idx ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY;
11349 memset(&c, 0, sizeof(c));
11350 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) |
11351 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
11352 V_FW_VI_MAC_CMD_VIID(viid));
11353 c.freemacs_to_len16 = cpu_to_be32(
11354 V_FW_CMD_LEN16(1) |
11355 (smac ? F_FW_VI_MAC_CMD_IS_SMAC : 0));
11356 p->valid_to_idx = cpu_to_be16(F_FW_VI_MAC_CMD_VALID |
11357 V_FW_VI_MAC_CMD_SMAC_RESULT(mode) |
11358 V_FW_VI_MAC_CMD_IDX(idx));
11359 memcpy(p->macaddr, addr, sizeof(p->macaddr));
11361 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
11363 ret = G_FW_VI_MAC_CMD_IDX(be16_to_cpu(p->valid_to_idx));
11364 if (ret >= max_mac_addr)
11367 /* Does fw supports returning smt_idx? */
11368 if (adap->params.viid_smt_extn_support)
11369 *smt_idx = G_FW_VI_MAC_CMD_SMTID(be32_to_cpu(c.op_to_viid));
11371 /* In T4/T5, SMT contains 256 SMAC entries
11372 * organized in 128 rows of 2 entries each.
11373 * In T6, SMT contains 256 SMAC entries in
11376 if (chip_id(adap) <= CHELSIO_T5)
11377 *smt_idx = ((viid & M_FW_VIID_VIN) << 1);
11379 *smt_idx = (viid & M_FW_VIID_VIN);