sys/dev/igc/igc_hw.h

   1 /*-
   2  * Copyright 2021 Intel Corp
   3  * Copyright 2021 Rubicon Communications, LLC (Netgate)
   4  * SPDX-License-Identifier: BSD-3-Clause
   5  *
   6  * $FreeBSD$
   7  */
   8
   9 #ifndef _IGC_HW_H_
  10 #define _IGC_HW_H_
  11
  12 #include "igc_osdep.h"
  13 #include "igc_regs.h"
  14 #include "igc_defines.h"
  15
  16 struct igc_hw;
  17
  18 #define IGC_DEV_ID_I225_LM                      0x15F2
  19 #define IGC_DEV_ID_I225_V                       0x15F3
  20 #define IGC_DEV_ID_I225_K                       0x3100
  21 #define IGC_DEV_ID_I225_I                       0x15F8
  22 #define IGC_DEV_ID_I220_V                       0x15F7
  23 #define IGC_DEV_ID_I225_K2                      0x3101
  24 #define IGC_DEV_ID_I225_LMVP                    0x5502
  25 #define IGC_DEV_ID_I226_K                       0x5504
  26 #define IGC_DEV_ID_I225_IT                      0x0D9F
  27 #define IGC_DEV_ID_I226_LM                      0x125B
  28 #define IGC_DEV_ID_I226_V                       0x125C
  29 #define IGC_DEV_ID_I226_IT                      0x125D
  30 #define IGC_DEV_ID_I221_V                       0x125E
  31 #define IGC_DEV_ID_I226_BLANK_NVM               0x125F
  32 #define IGC_DEV_ID_I225_BLANK_NVM               0x15FD
  33
  34 #define IGC_REVISION_0  0
  35 #define IGC_REVISION_1  1
  36 #define IGC_REVISION_2  2
  37 #define IGC_REVISION_3  3
  38 #define IGC_REVISION_4  4
  39
  40 #define IGC_FUNC_1              1
  41
  42 #define IGC_ALT_MAC_ADDRESS_OFFSET_LAN0 0
  43 #define IGC_ALT_MAC_ADDRESS_OFFSET_LAN1 3
  44
  45 enum igc_mac_type {
  46         igc_undefined = 0,
  47         igc_i225,
  48         igc_num_macs  /* List is 1-based, so subtract 1 for TRUE count. */
  49 };
  50
  51 enum igc_media_type {
  52         igc_media_type_unknown = 0,
  53         igc_media_type_copper = 1,
  54         igc_num_media_types
  55 };
  56
  57 enum igc_nvm_type {
  58         igc_nvm_unknown = 0,
  59         igc_nvm_eeprom_spi,
  60         igc_nvm_flash_hw,
  61         igc_nvm_invm,
  62 };
  63
  64 enum igc_phy_type {
  65         igc_phy_unknown = 0,
  66         igc_phy_none,
  67         igc_phy_i225,
  68 };
  69
  70 enum igc_bus_type {
  71         igc_bus_type_unknown = 0,
  72         igc_bus_type_pci,
  73         igc_bus_type_pcix,
  74         igc_bus_type_pci_express,
  75         igc_bus_type_reserved
  76 };
  77
  78 enum igc_bus_speed {
  79         igc_bus_speed_unknown = 0,
  80         igc_bus_speed_33,
  81         igc_bus_speed_66,
  82         igc_bus_speed_100,
  83         igc_bus_speed_120,
  84         igc_bus_speed_133,
  85         igc_bus_speed_2500,
  86         igc_bus_speed_5000,
  87         igc_bus_speed_reserved
  88 };
  89
  90 enum igc_bus_width {
  91         igc_bus_width_unknown = 0,
  92         igc_bus_width_pcie_x1,
  93         igc_bus_width_pcie_x2,
  94         igc_bus_width_pcie_x4 = 4,
  95         igc_bus_width_pcie_x8 = 8,
  96         igc_bus_width_32,
  97         igc_bus_width_64,
  98         igc_bus_width_reserved
  99 };
 100
 101 enum igc_fc_mode {
 102         igc_fc_none = 0,
 103         igc_fc_rx_pause,
 104         igc_fc_tx_pause,
 105         igc_fc_full,
 106         igc_fc_default = 0xFF
 107 };
 108
 109 enum igc_ms_type {
 110         igc_ms_hw_default = 0,
 111         igc_ms_force_master,
 112         igc_ms_force_slave,
 113         igc_ms_auto
 114 };
 115
 116 enum igc_smart_speed {
 117         igc_smart_speed_default = 0,
 118         igc_smart_speed_on,
 119         igc_smart_speed_off
 120 };
 121
 122 #define __le16 u16
 123 #define __le32 u32
 124 #define __le64 u64
 125 /* Receive Descriptor */
 126 struct igc_rx_desc {
 127         __le64 buffer_addr; /* Address of the descriptor's data buffer */
 128         __le16 length;      /* Length of data DMAed into data buffer */
 129         __le16 csum; /* Packet checksum */
 130         u8  status;  /* Descriptor status */
 131         u8  errors;  /* Descriptor Errors */
 132         __le16 special;
 133 };
 134
 135 /* Receive Descriptor - Extended */
 136 union igc_rx_desc_extended {
 137         struct {
 138                 __le64 buffer_addr;
 139                 __le64 reserved;
 140         } read;
 141         struct {
 142                 struct {
 143                         __le32 mrq; /* Multiple Rx Queues */
 144                         union {
 145                                 __le32 rss; /* RSS Hash */
 146                                 struct {
 147                                         __le16 ip_id;  /* IP id */
 148                                         __le16 csum;   /* Packet Checksum */
 149                                 } csum_ip;
 150                         } hi_dword;
 151                 } lower;
 152                 struct {
 153                         __le32 status_error;  /* ext status/error */
 154                         __le16 length;
 155                         __le16 vlan; /* VLAN tag */
 156                 } upper;
 157         } wb;  /* writeback */
 158 };
 159
 160 #define MAX_PS_BUFFERS 4
 161
 162 /* Number of packet split data buffers (not including the header buffer) */
 163 #define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1)
 164
 165 /* Receive Descriptor - Packet Split */
 166 union igc_rx_desc_packet_split {
 167         struct {
 168                 /* one buffer for protocol header(s), three data buffers */
 169                 __le64 buffer_addr[MAX_PS_BUFFERS];
 170         } read;
 171         struct {
 172                 struct {
 173                         __le32 mrq;  /* Multiple Rx Queues */
 174                         union {
 175                                 __le32 rss; /* RSS Hash */
 176                                 struct {
 177                                         __le16 ip_id;    /* IP id */
 178                                         __le16 csum;     /* Packet Checksum */
 179                                 } csum_ip;
 180                         } hi_dword;
 181                 } lower;
 182                 struct {
 183                         __le32 status_error;  /* ext status/error */
 184                         __le16 length0;  /* length of buffer 0 */
 185                         __le16 vlan;  /* VLAN tag */
 186                 } middle;
 187                 struct {
 188                         __le16 header_status;
 189                         /* length of buffers 1-3 */
 190                         __le16 length[PS_PAGE_BUFFERS];
 191                 } upper;
 192                 __le64 reserved;
 193         } wb; /* writeback */
 194 };
 195
 196 /* Transmit Descriptor */
 197 struct igc_tx_desc {
 198         __le64 buffer_addr;   /* Address of the descriptor's data buffer */
 199         union {
 200                 __le32 data;
 201                 struct {
 202                         __le16 length;  /* Data buffer length */
 203                         u8 cso;  /* Checksum offset */
 204                         u8 cmd;  /* Descriptor control */
 205                 } flags;
 206         } lower;
 207         union {
 208                 __le32 data;
 209                 struct {
 210                         u8 status; /* Descriptor status */
 211                         u8 css;  /* Checksum start */
 212                         __le16 special;
 213                 } fields;
 214         } upper;
 215 };
 216
 217 /* Offload Context Descriptor */
 218 struct igc_context_desc {
 219         union {
 220                 __le32 ip_config;
 221                 struct {
 222                         u8 ipcss;  /* IP checksum start */
 223                         u8 ipcso;  /* IP checksum offset */
 224                         __le16 ipcse;  /* IP checksum end */
 225                 } ip_fields;
 226         } lower_setup;
 227         union {
 228                 __le32 tcp_config;
 229                 struct {
 230                         u8 tucss;  /* TCP checksum start */
 231                         u8 tucso;  /* TCP checksum offset */
 232                         __le16 tucse;  /* TCP checksum end */
 233                 } tcp_fields;
 234         } upper_setup;
 235         __le32 cmd_and_length;
 236         union {
 237                 __le32 data;
 238                 struct {
 239                         u8 status;  /* Descriptor status */
 240                         u8 hdr_len;  /* Header length */
 241                         __le16 mss;  /* Maximum segment size */
 242                 } fields;
 243         } tcp_seg_setup;
 244 };
 245
 246 /* Offload data descriptor */
 247 struct igc_data_desc {
 248         __le64 buffer_addr;  /* Address of the descriptor's buffer address */
 249         union {
 250                 __le32 data;
 251                 struct {
 252                         __le16 length;  /* Data buffer length */
 253                         u8 typ_len_ext;
 254                         u8 cmd;
 255                 } flags;
 256         } lower;
 257         union {
 258                 __le32 data;
 259                 struct {
 260                         u8 status;  /* Descriptor status */
 261                         u8 popts;  /* Packet Options */
 262                         __le16 special;
 263                 } fields;
 264         } upper;
 265 };
 266
 267 /* Statistics counters collected by the MAC */
 268 struct igc_hw_stats {
 269         u64 crcerrs;
 270         u64 algnerrc;
 271         u64 symerrs;
 272         u64 rxerrc;
 273         u64 mpc;
 274         u64 scc;
 275         u64 ecol;
 276         u64 mcc;
 277         u64 latecol;
 278         u64 colc;
 279         u64 dc;
 280         u64 tncrs;
 281         u64 sec;
 282         u64 rlec;
 283         u64 xonrxc;
 284         u64 xontxc;
 285         u64 xoffrxc;
 286         u64 xofftxc;
 287         u64 fcruc;
 288         u64 prc64;
 289         u64 prc127;
 290         u64 prc255;
 291         u64 prc511;
 292         u64 prc1023;
 293         u64 prc1522;
 294         u64 tlpic;
 295         u64 rlpic;
 296         u64 gprc;
 297         u64 bprc;
 298         u64 mprc;
 299         u64 gptc;
 300         u64 gorc;
 301         u64 gotc;
 302         u64 rnbc;
 303         u64 ruc;
 304         u64 rfc;
 305         u64 roc;
 306         u64 rjc;
 307         u64 mgprc;
 308         u64 mgpdc;
 309         u64 mgptc;
 310         u64 tor;
 311         u64 tot;
 312         u64 tpr;
 313         u64 tpt;
 314         u64 ptc64;
 315         u64 ptc127;
 316         u64 ptc255;
 317         u64 ptc511;
 318         u64 ptc1023;
 319         u64 ptc1522;
 320         u64 mptc;
 321         u64 bptc;
 322         u64 tsctc;
 323         u64 iac;
 324         u64 rxdmtc;
 325         u64 htdpmc;
 326         u64 rpthc;
 327         u64 hgptc;
 328         u64 hgorc;
 329         u64 hgotc;
 330         u64 lenerrs;
 331         u64 scvpc;
 332         u64 hrmpc;
 333         u64 doosync;
 334         u64 o2bgptc;
 335         u64 o2bspc;
 336         u64 b2ospc;
 337         u64 b2ogprc;
 338 };
 339
 340 #include "igc_mac.h"
 341 #include "igc_phy.h"
 342 #include "igc_nvm.h"
 343
 344 /* Function pointers for the MAC. */
 345 struct igc_mac_operations {
 346         s32  (*init_params)(struct igc_hw *);
 347         s32  (*check_for_link)(struct igc_hw *);
 348         void (*clear_hw_cntrs)(struct igc_hw *);
 349         void (*clear_vfta)(struct igc_hw *);
 350         s32  (*get_bus_info)(struct igc_hw *);
 351         void (*set_lan_id)(struct igc_hw *);
 352         s32  (*get_link_up_info)(struct igc_hw *, u16 *, u16 *);
 353         void (*update_mc_addr_list)(struct igc_hw *, u8 *, u32);
 354         s32  (*reset_hw)(struct igc_hw *);
 355         s32  (*init_hw)(struct igc_hw *);
 356         s32  (*setup_link)(struct igc_hw *);
 357         s32  (*setup_physical_interface)(struct igc_hw *);
 358         void (*write_vfta)(struct igc_hw *, u32, u32);
 359         void (*config_collision_dist)(struct igc_hw *);
 360         int  (*rar_set)(struct igc_hw *, u8*, u32);
 361         s32  (*read_mac_addr)(struct igc_hw *);
 362         s32  (*validate_mdi_setting)(struct igc_hw *);
 363         s32  (*acquire_swfw_sync)(struct igc_hw *, u16);
 364         void (*release_swfw_sync)(struct igc_hw *, u16);
 365 };
 366
 367 /* When to use various PHY register access functions:
 368  *
 369  *                 Func   Caller
 370  *   Function      Does   Does    When to use
 371  *   ~~~~~~~~~~~~  ~~~~~  ~~~~~~  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 372  *   X_reg         L,P,A  n/a     for simple PHY reg accesses
 373  *   X_reg_locked  P,A    L       for multiple accesses of different regs
 374  *                                on different pages
 375  *   X_reg_page    A      L,P     for multiple accesses of different regs
 376  *                                on the same page
 377  *
 378  * Where X=[read|write], L=locking, P=sets page, A=register access
 379  *
 380  */
 381 struct igc_phy_operations {
 382         s32  (*init_params)(struct igc_hw *);
 383         s32  (*acquire)(struct igc_hw *);
 384         s32  (*check_reset_block)(struct igc_hw *);
 385         s32  (*force_speed_duplex)(struct igc_hw *);
 386         s32  (*get_info)(struct igc_hw *);
 387         s32  (*set_page)(struct igc_hw *, u16);
 388         s32  (*read_reg)(struct igc_hw *, u32, u16 *);
 389         s32  (*read_reg_locked)(struct igc_hw *, u32, u16 *);
 390         s32  (*read_reg_page)(struct igc_hw *, u32, u16 *);
 391         void (*release)(struct igc_hw *);
 392         s32  (*reset)(struct igc_hw *);
 393         s32  (*set_d0_lplu_state)(struct igc_hw *, bool);
 394         s32  (*set_d3_lplu_state)(struct igc_hw *, bool);
 395         s32  (*write_reg)(struct igc_hw *, u32, u16);
 396         s32  (*write_reg_locked)(struct igc_hw *, u32, u16);
 397         s32  (*write_reg_page)(struct igc_hw *, u32, u16);
 398         void (*power_up)(struct igc_hw *);
 399         void (*power_down)(struct igc_hw *);
 400 };
 401
 402 /* Function pointers for the NVM. */
 403 struct igc_nvm_operations {
 404         s32  (*init_params)(struct igc_hw *);
 405         s32  (*acquire)(struct igc_hw *);
 406         s32  (*read)(struct igc_hw *, u16, u16, u16 *);
 407         void (*release)(struct igc_hw *);
 408         void (*reload)(struct igc_hw *);
 409         s32  (*update)(struct igc_hw *);
 410         s32  (*validate)(struct igc_hw *);
 411         s32  (*write)(struct igc_hw *, u16, u16, u16 *);
 412 };
 413
 414 struct igc_info {
 415         s32 (*get_invariants)(struct igc_hw *hw);
 416         struct igc_mac_operations *mac_ops;
 417         const struct igc_phy_operations *phy_ops;
 418         struct igc_nvm_operations *nvm_ops;
 419 };
 420
 421 extern const struct igc_info igc_i225_info;
 422
 423 struct igc_mac_info {
 424         struct igc_mac_operations ops;
 425         u8 addr[ETH_ADDR_LEN];
 426         u8 perm_addr[ETH_ADDR_LEN];
 427
 428         enum igc_mac_type type;
 429
 430         u32 mc_filter_type;
 431
 432         u16 current_ifs_val;
 433         u16 ifs_max_val;
 434         u16 ifs_min_val;
 435         u16 ifs_ratio;
 436         u16 ifs_step_size;
 437         u16 mta_reg_count;
 438         u16 uta_reg_count;
 439
 440         /* Maximum size of the MTA register table in all supported adapters */
 441 #define MAX_MTA_REG 128
 442         u32 mta_shadow[MAX_MTA_REG];
 443         u16 rar_entry_count;
 444
 445         u8  forced_speed_duplex;
 446
 447         bool asf_firmware_present;
 448         bool autoneg;
 449         bool get_link_status;
 450         u32  max_frame_size;
 451 };
 452
 453 struct igc_phy_info {
 454         struct igc_phy_operations ops;
 455         enum igc_phy_type type;
 456
 457         enum igc_smart_speed smart_speed;
 458
 459         u32 addr;
 460         u32 id;
 461         u32 reset_delay_us; /* in usec */
 462         u32 revision;
 463
 464         enum igc_media_type media_type;
 465
 466         u16 autoneg_advertised;
 467         u16 autoneg_mask;
 468
 469         u8 mdix;
 470
 471         bool polarity_correction;
 472         bool speed_downgraded;
 473         bool autoneg_wait_to_complete;
 474 };
 475
 476 struct igc_nvm_info {
 477         struct igc_nvm_operations ops;
 478         enum igc_nvm_type type;
 479
 480         u16 word_size;
 481         u16 delay_usec;
 482         u16 address_bits;
 483         u16 opcode_bits;
 484         u16 page_size;
 485 };
 486
 487 struct igc_bus_info {
 488         enum igc_bus_type type;
 489         enum igc_bus_speed speed;
 490         enum igc_bus_width width;
 491
 492         u16 func;
 493         u16 pci_cmd_word;
 494 };
 495
 496 struct igc_fc_info {
 497         u32 high_water;  /* Flow control high-water mark */
 498         u32 low_water;  /* Flow control low-water mark */
 499         u16 pause_time;  /* Flow control pause timer */
 500         u16 refresh_time;  /* Flow control refresh timer */
 501         bool send_xon;  /* Flow control send XON */
 502         bool strict_ieee;  /* Strict IEEE mode */
 503         enum igc_fc_mode current_mode;  /* FC mode in effect */
 504         enum igc_fc_mode requested_mode;  /* FC mode requested by caller */
 505 };
 506
 507 struct igc_dev_spec_i225 {
 508         bool eee_disable;
 509         bool clear_semaphore_once;
 510         u32 mtu;
 511 };
 512
 513 struct igc_hw {
 514         void *back;
 515
 516         u8 *hw_addr;
 517         u8 *flash_address;
 518         unsigned long io_base;
 519
 520         struct igc_mac_info  mac;
 521         struct igc_fc_info   fc;
 522         struct igc_phy_info  phy;
 523         struct igc_nvm_info  nvm;
 524         struct igc_bus_info  bus;
 525
 526         union {
 527                 struct igc_dev_spec_i225 _i225;
 528         } dev_spec;
 529
 530         u16 device_id;
 531         u16 subsystem_vendor_id;
 532         u16 subsystem_device_id;
 533         u16 vendor_id;
 534
 535         u8  revision_id;
 536 };
 537
 538 #include "igc_i225.h"
 539 #include "igc_base.h"
 540
 541 /* These functions must be implemented by drivers */
 542 s32  igc_read_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value);
 543 s32  igc_write_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value);
 544 void igc_read_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value);
 545 void igc_write_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value);
 546
 547 #endif