1 /******************************************************************************
2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
7 Redistribution and use in source and binary forms, with or without
8 modification, are permitted provided that the following conditions are met:
10 1. Redistributions of source code must retain the above copyright notice,
11 this list of conditions and the following disclaimer.
13 2. Redistributions in binary form must reproduce the above copyright
14 notice, this list of conditions and the following disclaimer in the
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17 3. Neither the name of the Intel Corporation nor the names of its
18 contributors may be used to endorse or promote products derived from
19 this software without specific prior written permission.
21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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24 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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31 POSSIBILITY OF SUCH DAMAGE.
33 ******************************************************************************/
36 #include "ixgbe_api.h"
37 #include "ixgbe_common.h"
38 #include "ixgbe_phy.h"
40 static void ixgbe_i2c_start(struct ixgbe_hw *hw);
41 static void ixgbe_i2c_stop(struct ixgbe_hw *hw);
42 static void ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
43 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
44 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
45 static void ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
46 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
47 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
48 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
49 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
50 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl);
51 static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
55 * ixgbe_out_i2c_byte_ack - Send I2C byte with ack
56 * @hw: pointer to the hardware structure
59 * Returns an error code on error.
61 static s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte)
65 status = ixgbe_clock_out_i2c_byte(hw, byte);
68 return ixgbe_get_i2c_ack(hw);
72 * ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack
73 * @hw: pointer to the hardware structure
74 * @byte: pointer to a u8 to receive the byte
76 * Returns an error code on error.
78 static s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte)
80 ixgbe_clock_in_i2c_byte(hw, byte);
82 return ixgbe_clock_out_i2c_bit(hw, false);
86 * ixgbe_ones_comp_byte_add - Perform one's complement addition
90 * Returns one's complement 8-bit sum.
92 static u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2)
94 u16 sum = add1 + add2;
96 sum = (sum & 0xFF) + (sum >> 8);
101 * ixgbe_read_i2c_combined_generic_int - Perform I2C read combined operation
102 * @hw: pointer to the hardware structure
103 * @addr: I2C bus address to read from
104 * @reg: I2C device register to read from
105 * @val: pointer to location to receive read value
106 * @lock: true if to take and release semaphore
108 * Returns an error code on error.
110 s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg,
113 u32 swfw_mask = hw->phy.phy_semaphore_mask;
122 reg_high = ((reg >> 7) & 0xFE) | 1; /* Indicate read combined */
123 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
126 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
127 return IXGBE_ERR_SWFW_SYNC;
129 /* Device Address and write indication */
130 if (ixgbe_out_i2c_byte_ack(hw, addr))
132 /* Write bits 14:8 */
133 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
136 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
139 if (ixgbe_out_i2c_byte_ack(hw, csum))
141 /* Re-start condition */
143 /* Device Address and read indication */
144 if (ixgbe_out_i2c_byte_ack(hw, addr | 1))
147 if (ixgbe_in_i2c_byte_ack(hw, &high_bits))
150 if (ixgbe_in_i2c_byte_ack(hw, &low_bits))
153 ixgbe_clock_in_i2c_byte(hw, &csum_byte);
155 if (ixgbe_clock_out_i2c_bit(hw, false))
159 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
160 *val = (high_bits << 8) | low_bits;
164 ixgbe_i2c_bus_clear(hw);
166 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
167 if (retry < max_retry)
168 DEBUGOUT("I2C byte read combined error - Retrying.\n");
170 DEBUGOUT("I2C byte read combined error.\n");
172 } while (retry <= max_retry);
174 return IXGBE_ERR_I2C;
178 * ixgbe_write_i2c_combined_generic_int - Perform I2C write combined operation
179 * @hw: pointer to the hardware structure
180 * @addr: I2C bus address to write to
181 * @reg: I2C device register to write to
182 * @val: value to write
183 * @lock: true if to take and release semaphore
185 * Returns an error code on error.
187 s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg,
190 u32 swfw_mask = hw->phy.phy_semaphore_mask;
196 reg_high = (reg >> 7) & 0xFE; /* Indicate write combined */
197 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
198 csum = ixgbe_ones_comp_byte_add(csum, val >> 8);
199 csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF);
202 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
203 return IXGBE_ERR_SWFW_SYNC;
205 /* Device Address and write indication */
206 if (ixgbe_out_i2c_byte_ack(hw, addr))
208 /* Write bits 14:8 */
209 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
212 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
214 /* Write data 15:8 */
215 if (ixgbe_out_i2c_byte_ack(hw, val >> 8))
218 if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF))
221 if (ixgbe_out_i2c_byte_ack(hw, csum))
225 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
229 ixgbe_i2c_bus_clear(hw);
231 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
232 if (retry < max_retry)
233 DEBUGOUT("I2C byte write combined error - Retrying.\n");
235 DEBUGOUT("I2C byte write combined error.\n");
237 } while (retry <= max_retry);
239 return IXGBE_ERR_I2C;
243 * ixgbe_init_phy_ops_generic - Inits PHY function ptrs
244 * @hw: pointer to the hardware structure
246 * Initialize the function pointers.
248 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)
250 struct ixgbe_phy_info *phy = &hw->phy;
252 DEBUGFUNC("ixgbe_init_phy_ops_generic");
255 phy->ops.identify = ixgbe_identify_phy_generic;
256 phy->ops.reset = ixgbe_reset_phy_generic;
257 phy->ops.read_reg = ixgbe_read_phy_reg_generic;
258 phy->ops.write_reg = ixgbe_write_phy_reg_generic;
259 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi;
260 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi;
261 phy->ops.setup_link = ixgbe_setup_phy_link_generic;
262 phy->ops.setup_link_speed = ixgbe_setup_phy_link_speed_generic;
263 phy->ops.check_link = NULL;
264 phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic;
265 phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_generic;
266 phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_generic;
267 phy->ops.read_i2c_sff8472 = ixgbe_read_i2c_sff8472_generic;
268 phy->ops.read_i2c_eeprom = ixgbe_read_i2c_eeprom_generic;
269 phy->ops.write_i2c_eeprom = ixgbe_write_i2c_eeprom_generic;
270 phy->ops.i2c_bus_clear = ixgbe_i2c_bus_clear;
271 phy->ops.identify_sfp = ixgbe_identify_module_generic;
272 phy->sfp_type = ixgbe_sfp_type_unknown;
273 phy->ops.read_i2c_byte_unlocked = ixgbe_read_i2c_byte_generic_unlocked;
274 phy->ops.write_i2c_byte_unlocked =
275 ixgbe_write_i2c_byte_generic_unlocked;
276 phy->ops.check_overtemp = ixgbe_tn_check_overtemp;
277 return IXGBE_SUCCESS;
281 * ixgbe_probe_phy - Probe a single address for a PHY
282 * @hw: pointer to hardware structure
283 * @phy_addr: PHY address to probe
285 * Returns true if PHY found
287 static bool ixgbe_probe_phy(struct ixgbe_hw *hw, u16 phy_addr)
291 if (!ixgbe_validate_phy_addr(hw, phy_addr)) {
292 DEBUGOUT1("Unable to validate PHY address 0x%04X\n",
297 if (ixgbe_get_phy_id(hw))
300 hw->phy.type = ixgbe_get_phy_type_from_id(hw->phy.id);
302 if (hw->phy.type == ixgbe_phy_unknown) {
303 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
304 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
306 (IXGBE_MDIO_PHY_10GBASET_ABILITY |
307 IXGBE_MDIO_PHY_1000BASET_ABILITY))
308 hw->phy.type = ixgbe_phy_cu_unknown;
310 hw->phy.type = ixgbe_phy_generic;
317 * ixgbe_identify_phy_generic - Get physical layer module
318 * @hw: pointer to hardware structure
320 * Determines the physical layer module found on the current adapter.
322 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
324 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
327 DEBUGFUNC("ixgbe_identify_phy_generic");
329 if (!hw->phy.phy_semaphore_mask) {
331 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
333 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
336 if (hw->phy.type != ixgbe_phy_unknown)
337 return IXGBE_SUCCESS;
339 if (hw->phy.nw_mng_if_sel) {
340 phy_addr = (hw->phy.nw_mng_if_sel &
341 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
342 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
343 if (ixgbe_probe_phy(hw, phy_addr))
344 return IXGBE_SUCCESS;
346 return IXGBE_ERR_PHY_ADDR_INVALID;
349 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
350 if (ixgbe_probe_phy(hw, phy_addr)) {
351 status = IXGBE_SUCCESS;
356 /* Certain media types do not have a phy so an address will not
357 * be found and the code will take this path. Caller has to
358 * decide if it is an error or not.
360 if (status != IXGBE_SUCCESS)
367 * ixgbe_check_reset_blocked - check status of MNG FW veto bit
368 * @hw: pointer to the hardware structure
370 * This function checks the MMNGC.MNG_VETO bit to see if there are
371 * any constraints on link from manageability. For MAC's that don't
372 * have this bit just return faluse since the link can not be blocked
375 s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw)
379 DEBUGFUNC("ixgbe_check_reset_blocked");
381 /* If we don't have this bit, it can't be blocking */
382 if (hw->mac.type == ixgbe_mac_82598EB)
385 mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC);
386 if (mmngc & IXGBE_MMNGC_MNG_VETO) {
387 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE,
388 "MNG_VETO bit detected.\n");
396 * ixgbe_validate_phy_addr - Determines phy address is valid
397 * @hw: pointer to hardware structure
398 * @phy_addr: PHY address
401 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
406 DEBUGFUNC("ixgbe_validate_phy_addr");
408 hw->phy.addr = phy_addr;
409 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
410 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id);
412 if (phy_id != 0xFFFF && phy_id != 0x0)
415 DEBUGOUT1("PHY ID HIGH is 0x%04X\n", phy_id);
421 * ixgbe_get_phy_id - Get the phy type
422 * @hw: pointer to hardware structure
425 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
431 DEBUGFUNC("ixgbe_get_phy_id");
433 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
434 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
437 if (status == IXGBE_SUCCESS) {
438 hw->phy.id = (u32)(phy_id_high << 16);
439 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
440 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
442 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
443 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
445 DEBUGOUT2("PHY_ID_HIGH 0x%04X, PHY_ID_LOW 0x%04X\n",
446 phy_id_high, phy_id_low);
452 * ixgbe_get_phy_type_from_id - Get the phy type
453 * @phy_id: PHY ID information
456 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
458 enum ixgbe_phy_type phy_type;
460 DEBUGFUNC("ixgbe_get_phy_type_from_id");
464 phy_type = ixgbe_phy_tn;
469 phy_type = ixgbe_phy_aq;
472 phy_type = ixgbe_phy_qt;
475 phy_type = ixgbe_phy_nl;
479 phy_type = ixgbe_phy_x550em_ext_t;
481 case IXGBE_M88E1500_E_PHY_ID:
482 case IXGBE_M88E1543_E_PHY_ID:
483 phy_type = ixgbe_phy_ext_1g_t;
486 phy_type = ixgbe_phy_unknown;
493 * ixgbe_reset_phy_generic - Performs a PHY reset
494 * @hw: pointer to hardware structure
496 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
500 s32 status = IXGBE_SUCCESS;
502 DEBUGFUNC("ixgbe_reset_phy_generic");
504 if (hw->phy.type == ixgbe_phy_unknown)
505 status = ixgbe_identify_phy_generic(hw);
507 if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none)
510 /* Don't reset PHY if it's shut down due to overtemp. */
511 if (!hw->phy.reset_if_overtemp &&
512 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
515 /* Blocked by MNG FW so bail */
516 if (ixgbe_check_reset_blocked(hw))
520 * Perform soft PHY reset to the PHY_XS.
521 * This will cause a soft reset to the PHY
523 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
524 IXGBE_MDIO_PHY_XS_DEV_TYPE,
525 IXGBE_MDIO_PHY_XS_RESET);
528 * Poll for reset bit to self-clear indicating reset is complete.
529 * Some PHYs could take up to 3 seconds to complete and need about
530 * 1.7 usec delay after the reset is complete.
532 for (i = 0; i < 30; i++) {
534 if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
535 status = hw->phy.ops.read_reg(hw,
536 IXGBE_MDIO_TX_VENDOR_ALARMS_3,
537 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
539 if (status != IXGBE_SUCCESS)
542 if (ctrl & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
547 status = hw->phy.ops.read_reg(hw,
548 IXGBE_MDIO_PHY_XS_CONTROL,
549 IXGBE_MDIO_PHY_XS_DEV_TYPE,
551 if (status != IXGBE_SUCCESS)
554 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) {
561 if (ctrl & IXGBE_MDIO_PHY_XS_RESET) {
562 status = IXGBE_ERR_RESET_FAILED;
563 ERROR_REPORT1(IXGBE_ERROR_POLLING,
564 "PHY reset polling failed to complete.\n");
572 * ixgbe_restart_auto_neg - Restart auto negotiation on the PHY
573 * @hw: pointer to hardware structure
575 void ixgbe_restart_auto_neg(struct ixgbe_hw *hw)
579 /* Check if PHY reset is blocked by MNG FW */
580 if (ixgbe_check_reset_blocked(hw))
583 /* Restart PHY auto-negotiation. */
584 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
585 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
586 autoneg_reg |= IXGBE_MII_RESTART;
587 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
588 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
592 * ixgbe_read_phy_mdi - Reads a value from a specified PHY register without
594 * @hw: pointer to hardware structure
595 * @reg_addr: 32 bit address of PHY register to read
596 * @device_type: 5 bit device type
597 * @phy_data: Pointer to read data from PHY register
599 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
602 u32 i, data, command;
604 /* Setup and write the address cycle command */
605 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
606 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
607 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
608 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
610 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
613 * Check every 10 usec to see if the address cycle completed.
614 * The MDI Command bit will clear when the operation is
617 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
620 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
621 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
626 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
627 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address command did not complete.\n");
628 DEBUGOUT("PHY address command did not complete, returning IXGBE_ERR_PHY\n");
629 return IXGBE_ERR_PHY;
633 * Address cycle complete, setup and write the read
636 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
637 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
638 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
639 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
641 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
644 * Check every 10 usec to see if the address cycle
645 * completed. The MDI Command bit will clear when the
646 * operation is complete
648 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
651 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
652 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
656 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
657 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY read command didn't complete\n");
658 DEBUGOUT("PHY read command didn't complete, returning IXGBE_ERR_PHY\n");
659 return IXGBE_ERR_PHY;
663 * Read operation is complete. Get the data
666 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
667 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
668 *phy_data = (u16)(data);
670 return IXGBE_SUCCESS;
674 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
675 * using the SWFW lock - this function is needed in most cases
676 * @hw: pointer to hardware structure
677 * @reg_addr: 32 bit address of PHY register to read
678 * @device_type: 5 bit device type
679 * @phy_data: Pointer to read data from PHY register
681 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
682 u32 device_type, u16 *phy_data)
685 u32 gssr = hw->phy.phy_semaphore_mask;
687 DEBUGFUNC("ixgbe_read_phy_reg_generic");
689 if (hw->mac.ops.acquire_swfw_sync(hw, gssr))
690 return IXGBE_ERR_SWFW_SYNC;
692 status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
694 hw->mac.ops.release_swfw_sync(hw, gssr);
700 * ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register
702 * @hw: pointer to hardware structure
703 * @reg_addr: 32 bit PHY register to write
704 * @device_type: 5 bit device type
705 * @phy_data: Data to write to the PHY register
707 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
708 u32 device_type, u16 phy_data)
712 /* Put the data in the MDI single read and write data register*/
713 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
715 /* Setup and write the address cycle command */
716 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
717 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
718 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
719 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
721 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
724 * Check every 10 usec to see if the address cycle completed.
725 * The MDI Command bit will clear when the operation is
728 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
731 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
732 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
736 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
737 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address cmd didn't complete\n");
738 return IXGBE_ERR_PHY;
742 * Address cycle complete, setup and write the write
745 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
746 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
747 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
748 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
750 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
753 * Check every 10 usec to see if the address cycle
754 * completed. The MDI Command bit will clear when the
755 * operation is complete
757 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
760 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
761 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
765 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
766 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY write cmd didn't complete\n");
767 return IXGBE_ERR_PHY;
770 return IXGBE_SUCCESS;
774 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
775 * using SWFW lock- this function is needed in most cases
776 * @hw: pointer to hardware structure
777 * @reg_addr: 32 bit PHY register to write
778 * @device_type: 5 bit device type
779 * @phy_data: Data to write to the PHY register
781 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
782 u32 device_type, u16 phy_data)
785 u32 gssr = hw->phy.phy_semaphore_mask;
787 DEBUGFUNC("ixgbe_write_phy_reg_generic");
789 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) {
790 status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type,
792 hw->mac.ops.release_swfw_sync(hw, gssr);
794 status = IXGBE_ERR_SWFW_SYNC;
801 * ixgbe_setup_phy_link_generic - Set and restart auto-neg
802 * @hw: pointer to hardware structure
804 * Restart auto-negotiation and PHY and waits for completion.
806 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
808 s32 status = IXGBE_SUCCESS;
809 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
810 bool autoneg = false;
811 ixgbe_link_speed speed;
813 DEBUGFUNC("ixgbe_setup_phy_link_generic");
815 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
817 /* Set or unset auto-negotiation 10G advertisement */
818 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
819 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
822 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
823 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) &&
824 (speed & IXGBE_LINK_SPEED_10GB_FULL))
825 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
827 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
828 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
831 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
832 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
835 if (hw->mac.type == ixgbe_mac_X550) {
836 /* Set or unset auto-negotiation 5G advertisement */
837 autoneg_reg &= ~IXGBE_MII_5GBASE_T_ADVERTISE;
838 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_5GB_FULL) &&
839 (speed & IXGBE_LINK_SPEED_5GB_FULL))
840 autoneg_reg |= IXGBE_MII_5GBASE_T_ADVERTISE;
842 /* Set or unset auto-negotiation 2.5G advertisement */
843 autoneg_reg &= ~IXGBE_MII_2_5GBASE_T_ADVERTISE;
844 if ((hw->phy.autoneg_advertised &
845 IXGBE_LINK_SPEED_2_5GB_FULL) &&
846 (speed & IXGBE_LINK_SPEED_2_5GB_FULL))
847 autoneg_reg |= IXGBE_MII_2_5GBASE_T_ADVERTISE;
850 /* Set or unset auto-negotiation 1G advertisement */
851 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
852 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) &&
853 (speed & IXGBE_LINK_SPEED_1GB_FULL))
854 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
856 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
857 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
860 /* Set or unset auto-negotiation 100M advertisement */
861 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
862 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
865 autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE |
866 IXGBE_MII_100BASE_T_ADVERTISE_HALF);
867 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) &&
868 (speed & IXGBE_LINK_SPEED_100_FULL))
869 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
871 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
872 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
875 ixgbe_restart_auto_neg(hw);
880 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
881 * @hw: pointer to hardware structure
882 * @speed: new link speed
883 * @autoneg_wait_to_complete: unused
885 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
886 ixgbe_link_speed speed,
887 bool autoneg_wait_to_complete)
889 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
891 DEBUGFUNC("ixgbe_setup_phy_link_speed_generic");
894 * Clear autoneg_advertised and set new values based on input link
897 hw->phy.autoneg_advertised = 0;
899 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
900 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
902 if (speed & IXGBE_LINK_SPEED_5GB_FULL)
903 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL;
905 if (speed & IXGBE_LINK_SPEED_2_5GB_FULL)
906 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL;
908 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
909 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
911 if (speed & IXGBE_LINK_SPEED_100_FULL)
912 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
914 if (speed & IXGBE_LINK_SPEED_10_FULL)
915 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10_FULL;
917 /* Setup link based on the new speed settings */
918 ixgbe_setup_phy_link(hw);
920 return IXGBE_SUCCESS;
924 * ixgbe_get_copper_speeds_supported - Get copper link speeds from phy
925 * @hw: pointer to hardware structure
927 * Determines the supported link capabilities by reading the PHY auto
928 * negotiation register.
930 static s32 ixgbe_get_copper_speeds_supported(struct ixgbe_hw *hw)
935 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
936 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
941 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
942 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL;
943 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
944 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL;
945 if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M)
946 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL;
948 switch (hw->mac.type) {
950 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL;
951 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL;
953 case ixgbe_mac_X550EM_x:
954 case ixgbe_mac_X550EM_a:
955 hw->phy.speeds_supported &= ~IXGBE_LINK_SPEED_100_FULL;
965 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
966 * @hw: pointer to hardware structure
967 * @speed: pointer to link speed
968 * @autoneg: boolean auto-negotiation value
970 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
971 ixgbe_link_speed *speed,
974 s32 status = IXGBE_SUCCESS;
976 DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic");
979 if (!hw->phy.speeds_supported)
980 status = ixgbe_get_copper_speeds_supported(hw);
982 *speed = hw->phy.speeds_supported;
987 * ixgbe_check_phy_link_tnx - Determine link and speed status
988 * @hw: pointer to hardware structure
989 * @speed: current link speed
990 * @link_up: true is link is up, false otherwise
992 * Reads the VS1 register to determine if link is up and the current speed for
995 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
998 s32 status = IXGBE_SUCCESS;
1000 u32 max_time_out = 10;
1005 DEBUGFUNC("ixgbe_check_phy_link_tnx");
1007 /* Initialize speed and link to default case */
1009 *speed = IXGBE_LINK_SPEED_10GB_FULL;
1012 * Check current speed and link status of the PHY register.
1013 * This is a vendor specific register and may have to
1014 * be changed for other copper PHYs.
1016 for (time_out = 0; time_out < max_time_out; time_out++) {
1018 status = hw->phy.ops.read_reg(hw,
1019 IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
1020 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1022 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
1023 phy_speed = phy_data &
1024 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
1025 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
1028 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
1029 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1038 * ixgbe_setup_phy_link_tnx - Set and restart auto-neg
1039 * @hw: pointer to hardware structure
1041 * Restart auto-negotiation and PHY and waits for completion.
1043 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
1045 s32 status = IXGBE_SUCCESS;
1046 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
1047 bool autoneg = false;
1048 ixgbe_link_speed speed;
1050 DEBUGFUNC("ixgbe_setup_phy_link_tnx");
1052 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
1054 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
1055 /* Set or unset auto-negotiation 10G advertisement */
1056 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1057 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1060 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
1061 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1062 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
1064 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1065 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1069 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
1070 /* Set or unset auto-negotiation 1G advertisement */
1071 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1072 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1075 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1076 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1077 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1079 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1080 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1084 if (speed & IXGBE_LINK_SPEED_100_FULL) {
1085 /* Set or unset auto-negotiation 100M advertisement */
1086 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1087 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1090 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE;
1091 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
1092 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
1094 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1095 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1099 ixgbe_restart_auto_neg(hw);
1104 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
1105 * @hw: pointer to hardware structure
1106 * @firmware_version: pointer to the PHY Firmware Version
1108 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
1109 u16 *firmware_version)
1113 DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx");
1115 status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
1116 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1123 * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
1124 * @hw: pointer to hardware structure
1125 * @firmware_version: pointer to the PHY Firmware Version
1127 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
1128 u16 *firmware_version)
1132 DEBUGFUNC("ixgbe_get_phy_firmware_version_generic");
1134 status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
1135 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1142 * ixgbe_reset_phy_nl - Performs a PHY reset
1143 * @hw: pointer to hardware structure
1145 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
1147 u16 phy_offset, control, eword, edata, block_crc;
1148 bool end_data = false;
1149 u16 list_offset, data_offset;
1151 s32 ret_val = IXGBE_SUCCESS;
1154 DEBUGFUNC("ixgbe_reset_phy_nl");
1156 /* Blocked by MNG FW so bail */
1157 if (ixgbe_check_reset_blocked(hw))
1160 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1161 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1163 /* reset the PHY and poll for completion */
1164 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1165 IXGBE_MDIO_PHY_XS_DEV_TYPE,
1166 (phy_data | IXGBE_MDIO_PHY_XS_RESET));
1168 for (i = 0; i < 100; i++) {
1169 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1170 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1171 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0)
1176 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) {
1177 DEBUGOUT("PHY reset did not complete.\n");
1178 ret_val = IXGBE_ERR_PHY;
1182 /* Get init offsets */
1183 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
1185 if (ret_val != IXGBE_SUCCESS)
1188 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
1192 * Read control word from PHY init contents offset
1194 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
1197 control = (eword & IXGBE_CONTROL_MASK_NL) >>
1198 IXGBE_CONTROL_SHIFT_NL;
1199 edata = eword & IXGBE_DATA_MASK_NL;
1201 case IXGBE_DELAY_NL:
1203 DEBUGOUT1("DELAY: %d MS\n", edata);
1207 DEBUGOUT("DATA:\n");
1209 ret_val = hw->eeprom.ops.read(hw, data_offset,
1214 for (i = 0; i < edata; i++) {
1215 ret_val = hw->eeprom.ops.read(hw, data_offset,
1219 hw->phy.ops.write_reg(hw, phy_offset,
1220 IXGBE_TWINAX_DEV, eword);
1221 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword,
1227 case IXGBE_CONTROL_NL:
1229 DEBUGOUT("CONTROL:\n");
1230 if (edata == IXGBE_CONTROL_EOL_NL) {
1233 } else if (edata == IXGBE_CONTROL_SOL_NL) {
1236 DEBUGOUT("Bad control value\n");
1237 ret_val = IXGBE_ERR_PHY;
1242 DEBUGOUT("Bad control type\n");
1243 ret_val = IXGBE_ERR_PHY;
1252 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1253 "eeprom read at offset %d failed", data_offset);
1254 return IXGBE_ERR_PHY;
1258 * ixgbe_identify_module_generic - Identifies module type
1259 * @hw: pointer to hardware structure
1261 * Determines HW type and calls appropriate function.
1263 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
1265 s32 status = IXGBE_ERR_SFP_NOT_PRESENT;
1267 DEBUGFUNC("ixgbe_identify_module_generic");
1269 switch (hw->mac.ops.get_media_type(hw)) {
1270 case ixgbe_media_type_fiber:
1271 status = ixgbe_identify_sfp_module_generic(hw);
1274 case ixgbe_media_type_fiber_qsfp:
1275 status = ixgbe_identify_qsfp_module_generic(hw);
1279 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1280 status = IXGBE_ERR_SFP_NOT_PRESENT;
1288 * ixgbe_identify_sfp_module_generic - Identifies SFP modules
1289 * @hw: pointer to hardware structure
1291 * Searches for and identifies the SFP module and assigns appropriate PHY type.
1293 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
1295 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1297 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1299 u8 comp_codes_1g = 0;
1300 u8 comp_codes_10g = 0;
1301 u8 oui_bytes[3] = {0, 0, 0};
1304 u16 enforce_sfp = 0;
1306 DEBUGFUNC("ixgbe_identify_sfp_module_generic");
1308 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
1309 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1310 status = IXGBE_ERR_SFP_NOT_PRESENT;
1314 /* LAN ID is needed for I2C access */
1315 hw->mac.ops.set_lan_id(hw);
1317 status = hw->phy.ops.read_i2c_eeprom(hw,
1318 IXGBE_SFF_IDENTIFIER,
1321 if (status != IXGBE_SUCCESS)
1322 goto err_read_i2c_eeprom;
1324 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
1325 hw->phy.type = ixgbe_phy_sfp_unsupported;
1326 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1328 status = hw->phy.ops.read_i2c_eeprom(hw,
1329 IXGBE_SFF_1GBE_COMP_CODES,
1332 if (status != IXGBE_SUCCESS)
1333 goto err_read_i2c_eeprom;
1335 status = hw->phy.ops.read_i2c_eeprom(hw,
1336 IXGBE_SFF_10GBE_COMP_CODES,
1339 if (status != IXGBE_SUCCESS)
1340 goto err_read_i2c_eeprom;
1341 status = hw->phy.ops.read_i2c_eeprom(hw,
1342 IXGBE_SFF_CABLE_TECHNOLOGY,
1345 if (status != IXGBE_SUCCESS)
1346 goto err_read_i2c_eeprom;
1353 * 3 SFP_DA_CORE0 - 82599-specific
1354 * 4 SFP_DA_CORE1 - 82599-specific
1355 * 5 SFP_SR/LR_CORE0 - 82599-specific
1356 * 6 SFP_SR/LR_CORE1 - 82599-specific
1357 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific
1358 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific
1359 * 9 SFP_1g_cu_CORE0 - 82599-specific
1360 * 10 SFP_1g_cu_CORE1 - 82599-specific
1361 * 11 SFP_1g_sx_CORE0 - 82599-specific
1362 * 12 SFP_1g_sx_CORE1 - 82599-specific
1364 if (hw->mac.type == ixgbe_mac_82598EB) {
1365 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1366 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
1367 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1368 hw->phy.sfp_type = ixgbe_sfp_type_sr;
1369 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1370 hw->phy.sfp_type = ixgbe_sfp_type_lr;
1372 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1374 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
1375 if (hw->bus.lan_id == 0)
1377 ixgbe_sfp_type_da_cu_core0;
1380 ixgbe_sfp_type_da_cu_core1;
1381 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
1382 hw->phy.ops.read_i2c_eeprom(
1383 hw, IXGBE_SFF_CABLE_SPEC_COMP,
1386 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
1387 if (hw->bus.lan_id == 0)
1389 ixgbe_sfp_type_da_act_lmt_core0;
1392 ixgbe_sfp_type_da_act_lmt_core1;
1395 ixgbe_sfp_type_unknown;
1397 } else if (comp_codes_10g &
1398 (IXGBE_SFF_10GBASESR_CAPABLE |
1399 IXGBE_SFF_10GBASELR_CAPABLE)) {
1400 if (hw->bus.lan_id == 0)
1402 ixgbe_sfp_type_srlr_core0;
1405 ixgbe_sfp_type_srlr_core1;
1406 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
1407 if (hw->bus.lan_id == 0)
1409 ixgbe_sfp_type_1g_cu_core0;
1412 ixgbe_sfp_type_1g_cu_core1;
1413 } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
1414 if (hw->bus.lan_id == 0)
1416 ixgbe_sfp_type_1g_sx_core0;
1419 ixgbe_sfp_type_1g_sx_core1;
1420 } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) {
1421 if (hw->bus.lan_id == 0)
1423 ixgbe_sfp_type_1g_lx_core0;
1426 ixgbe_sfp_type_1g_lx_core1;
1428 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1432 if (hw->phy.sfp_type != stored_sfp_type)
1433 hw->phy.sfp_setup_needed = true;
1435 /* Determine if the SFP+ PHY is dual speed or not. */
1436 hw->phy.multispeed_fiber = false;
1437 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1438 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1439 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1440 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1441 hw->phy.multispeed_fiber = true;
1443 /* Determine PHY vendor */
1444 if (hw->phy.type != ixgbe_phy_nl) {
1445 hw->phy.id = identifier;
1446 status = hw->phy.ops.read_i2c_eeprom(hw,
1447 IXGBE_SFF_VENDOR_OUI_BYTE0,
1450 if (status != IXGBE_SUCCESS)
1451 goto err_read_i2c_eeprom;
1453 status = hw->phy.ops.read_i2c_eeprom(hw,
1454 IXGBE_SFF_VENDOR_OUI_BYTE1,
1457 if (status != IXGBE_SUCCESS)
1458 goto err_read_i2c_eeprom;
1460 status = hw->phy.ops.read_i2c_eeprom(hw,
1461 IXGBE_SFF_VENDOR_OUI_BYTE2,
1464 if (status != IXGBE_SUCCESS)
1465 goto err_read_i2c_eeprom;
1468 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1469 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1470 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1472 switch (vendor_oui) {
1473 case IXGBE_SFF_VENDOR_OUI_TYCO:
1474 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1476 ixgbe_phy_sfp_passive_tyco;
1478 case IXGBE_SFF_VENDOR_OUI_FTL:
1479 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1480 hw->phy.type = ixgbe_phy_sfp_ftl_active;
1482 hw->phy.type = ixgbe_phy_sfp_ftl;
1484 case IXGBE_SFF_VENDOR_OUI_AVAGO:
1485 hw->phy.type = ixgbe_phy_sfp_avago;
1487 case IXGBE_SFF_VENDOR_OUI_INTEL:
1488 hw->phy.type = ixgbe_phy_sfp_intel;
1491 hw->phy.type = ixgbe_phy_sfp_unknown;
1496 /* Allow any DA cable vendor */
1497 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1498 IXGBE_SFF_DA_ACTIVE_CABLE)) {
1499 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1500 hw->phy.type = ixgbe_phy_sfp_passive_unknown;
1501 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1502 hw->phy.type = ixgbe_phy_sfp_active_unknown;
1503 status = IXGBE_SUCCESS;
1507 /* Verify supported 1G SFP modules */
1508 if (comp_codes_10g == 0 &&
1509 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1510 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1511 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1512 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1513 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1514 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1515 hw->phy.type = ixgbe_phy_sfp_unsupported;
1516 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1520 /* Anything else 82598-based is supported */
1521 if (hw->mac.type == ixgbe_mac_82598EB) {
1522 status = IXGBE_SUCCESS;
1526 ixgbe_get_device_caps(hw, &enforce_sfp);
1527 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1528 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1529 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1530 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1531 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1532 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1533 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1534 /* Make sure we're a supported PHY type */
1535 if (hw->phy.type == ixgbe_phy_sfp_intel) {
1536 status = IXGBE_SUCCESS;
1538 if (hw->allow_unsupported_sfp == true) {
1540 "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. "
1541 "Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. "
1542 "Intel Corporation is not responsible for any harm caused by using untested modules.\n");
1543 status = IXGBE_SUCCESS;
1545 DEBUGOUT("SFP+ module not supported\n");
1547 ixgbe_phy_sfp_unsupported;
1548 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1552 status = IXGBE_SUCCESS;
1559 err_read_i2c_eeprom:
1560 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1561 if (hw->phy.type != ixgbe_phy_nl) {
1563 hw->phy.type = ixgbe_phy_unknown;
1565 return IXGBE_ERR_SFP_NOT_PRESENT;
1569 * ixgbe_get_supported_phy_sfp_layer_generic - Returns physical layer type
1570 * @hw: pointer to hardware structure
1572 * Determines physical layer capabilities of the current SFP.
1574 u64 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw)
1576 u64 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1577 u8 comp_codes_10g = 0;
1578 u8 comp_codes_1g = 0;
1580 DEBUGFUNC("ixgbe_get_supported_phy_sfp_layer_generic");
1582 hw->phy.ops.identify_sfp(hw);
1583 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1584 return physical_layer;
1586 switch (hw->phy.type) {
1587 case ixgbe_phy_sfp_passive_tyco:
1588 case ixgbe_phy_sfp_passive_unknown:
1589 case ixgbe_phy_qsfp_passive_unknown:
1590 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1592 case ixgbe_phy_sfp_ftl_active:
1593 case ixgbe_phy_sfp_active_unknown:
1594 case ixgbe_phy_qsfp_active_unknown:
1595 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
1597 case ixgbe_phy_sfp_avago:
1598 case ixgbe_phy_sfp_ftl:
1599 case ixgbe_phy_sfp_intel:
1600 case ixgbe_phy_sfp_unknown:
1601 hw->phy.ops.read_i2c_eeprom(hw,
1602 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
1603 hw->phy.ops.read_i2c_eeprom(hw,
1604 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
1605 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1606 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1607 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1608 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1609 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
1610 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
1611 else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE)
1612 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX;
1614 case ixgbe_phy_qsfp_intel:
1615 case ixgbe_phy_qsfp_unknown:
1616 hw->phy.ops.read_i2c_eeprom(hw,
1617 IXGBE_SFF_QSFP_10GBE_COMP, &comp_codes_10g);
1618 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1619 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1620 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1621 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1627 return physical_layer;
1631 * ixgbe_identify_qsfp_module_generic - Identifies QSFP modules
1632 * @hw: pointer to hardware structure
1634 * Searches for and identifies the QSFP module and assigns appropriate PHY type
1636 s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)
1638 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1640 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1642 u8 comp_codes_1g = 0;
1643 u8 comp_codes_10g = 0;
1644 u8 oui_bytes[3] = {0, 0, 0};
1645 u16 enforce_sfp = 0;
1647 u8 cable_length = 0;
1649 bool active_cable = false;
1651 DEBUGFUNC("ixgbe_identify_qsfp_module_generic");
1653 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) {
1654 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1655 status = IXGBE_ERR_SFP_NOT_PRESENT;
1659 /* LAN ID is needed for I2C access */
1660 hw->mac.ops.set_lan_id(hw);
1662 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
1665 if (status != IXGBE_SUCCESS)
1666 goto err_read_i2c_eeprom;
1668 if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) {
1669 hw->phy.type = ixgbe_phy_sfp_unsupported;
1670 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1674 hw->phy.id = identifier;
1676 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP,
1679 if (status != IXGBE_SUCCESS)
1680 goto err_read_i2c_eeprom;
1682 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP,
1685 if (status != IXGBE_SUCCESS)
1686 goto err_read_i2c_eeprom;
1688 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) {
1689 hw->phy.type = ixgbe_phy_qsfp_passive_unknown;
1690 if (hw->bus.lan_id == 0)
1691 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0;
1693 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1;
1694 } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1695 IXGBE_SFF_10GBASELR_CAPABLE)) {
1696 if (hw->bus.lan_id == 0)
1697 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0;
1699 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1;
1701 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE)
1702 active_cable = true;
1704 if (!active_cable) {
1705 /* check for active DA cables that pre-date
1707 hw->phy.ops.read_i2c_eeprom(hw,
1708 IXGBE_SFF_QSFP_CONNECTOR,
1711 hw->phy.ops.read_i2c_eeprom(hw,
1712 IXGBE_SFF_QSFP_CABLE_LENGTH,
1715 hw->phy.ops.read_i2c_eeprom(hw,
1716 IXGBE_SFF_QSFP_DEVICE_TECH,
1720 IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) &&
1721 (cable_length > 0) &&
1722 ((device_tech >> 4) ==
1723 IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL))
1724 active_cable = true;
1728 hw->phy.type = ixgbe_phy_qsfp_active_unknown;
1729 if (hw->bus.lan_id == 0)
1731 ixgbe_sfp_type_da_act_lmt_core0;
1734 ixgbe_sfp_type_da_act_lmt_core1;
1736 /* unsupported module type */
1737 hw->phy.type = ixgbe_phy_sfp_unsupported;
1738 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1743 if (hw->phy.sfp_type != stored_sfp_type)
1744 hw->phy.sfp_setup_needed = true;
1746 /* Determine if the QSFP+ PHY is dual speed or not. */
1747 hw->phy.multispeed_fiber = false;
1748 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1749 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1750 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1751 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1752 hw->phy.multispeed_fiber = true;
1754 /* Determine PHY vendor for optical modules */
1755 if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1756 IXGBE_SFF_10GBASELR_CAPABLE)) {
1757 status = hw->phy.ops.read_i2c_eeprom(hw,
1758 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0,
1761 if (status != IXGBE_SUCCESS)
1762 goto err_read_i2c_eeprom;
1764 status = hw->phy.ops.read_i2c_eeprom(hw,
1765 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1,
1768 if (status != IXGBE_SUCCESS)
1769 goto err_read_i2c_eeprom;
1771 status = hw->phy.ops.read_i2c_eeprom(hw,
1772 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2,
1775 if (status != IXGBE_SUCCESS)
1776 goto err_read_i2c_eeprom;
1779 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1780 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1781 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1783 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL)
1784 hw->phy.type = ixgbe_phy_qsfp_intel;
1786 hw->phy.type = ixgbe_phy_qsfp_unknown;
1788 ixgbe_get_device_caps(hw, &enforce_sfp);
1789 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {
1790 /* Make sure we're a supported PHY type */
1791 if (hw->phy.type == ixgbe_phy_qsfp_intel) {
1792 status = IXGBE_SUCCESS;
1794 if (hw->allow_unsupported_sfp == true) {
1796 "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. "
1797 "Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. "
1798 "Intel Corporation is not responsible for any harm caused by using untested modules.\n");
1799 status = IXGBE_SUCCESS;
1801 DEBUGOUT("QSFP module not supported\n");
1803 ixgbe_phy_sfp_unsupported;
1804 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1808 status = IXGBE_SUCCESS;
1815 err_read_i2c_eeprom:
1816 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1818 hw->phy.type = ixgbe_phy_unknown;
1820 return IXGBE_ERR_SFP_NOT_PRESENT;
1824 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1825 * @hw: pointer to hardware structure
1826 * @list_offset: offset to the SFP ID list
1827 * @data_offset: offset to the SFP data block
1829 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1830 * so it returns the offsets to the phy init sequence block.
1832 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1837 u16 sfp_type = hw->phy.sfp_type;
1839 DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets");
1841 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1842 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1844 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1845 return IXGBE_ERR_SFP_NOT_PRESENT;
1847 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1848 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1849 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1852 * Limiting active cables and 1G Phys must be initialized as
1855 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
1856 sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1857 sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1858 sfp_type == ixgbe_sfp_type_1g_sx_core0)
1859 sfp_type = ixgbe_sfp_type_srlr_core0;
1860 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
1861 sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1862 sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1863 sfp_type == ixgbe_sfp_type_1g_sx_core1)
1864 sfp_type = ixgbe_sfp_type_srlr_core1;
1866 /* Read offset to PHY init contents */
1867 if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) {
1868 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1869 "eeprom read at offset %d failed",
1870 IXGBE_PHY_INIT_OFFSET_NL);
1871 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1874 if ((!*list_offset) || (*list_offset == 0xFFFF))
1875 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1877 /* Shift offset to first ID word */
1881 * Find the matching SFP ID in the EEPROM
1882 * and program the init sequence
1884 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1887 while (sfp_id != IXGBE_PHY_INIT_END_NL) {
1888 if (sfp_id == sfp_type) {
1890 if (hw->eeprom.ops.read(hw, *list_offset, data_offset))
1892 if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1893 DEBUGOUT("SFP+ module not supported\n");
1894 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1899 (*list_offset) += 2;
1900 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1905 if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1906 DEBUGOUT("No matching SFP+ module found\n");
1907 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1910 return IXGBE_SUCCESS;
1913 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1914 "eeprom read at offset %d failed", *list_offset);
1915 return IXGBE_ERR_PHY;
1919 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1920 * @hw: pointer to hardware structure
1921 * @byte_offset: EEPROM byte offset to read
1922 * @eeprom_data: value read
1924 * Performs byte read operation to SFP module's EEPROM over I2C interface.
1926 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1929 DEBUGFUNC("ixgbe_read_i2c_eeprom_generic");
1931 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1932 IXGBE_I2C_EEPROM_DEV_ADDR,
1937 * ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface
1938 * @hw: pointer to hardware structure
1939 * @byte_offset: byte offset at address 0xA2
1940 * @sff8472_data: value read
1942 * Performs byte read operation to SFP module's SFF-8472 data over I2C
1944 static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
1947 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1948 IXGBE_I2C_EEPROM_DEV_ADDR2,
1953 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1954 * @hw: pointer to hardware structure
1955 * @byte_offset: EEPROM byte offset to write
1956 * @eeprom_data: value to write
1958 * Performs byte write operation to SFP module's EEPROM over I2C interface.
1960 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1963 DEBUGFUNC("ixgbe_write_i2c_eeprom_generic");
1965 return hw->phy.ops.write_i2c_byte(hw, byte_offset,
1966 IXGBE_I2C_EEPROM_DEV_ADDR,
1971 * ixgbe_is_sfp_probe - Returns true if SFP is being detected
1972 * @hw: pointer to hardware structure
1973 * @offset: eeprom offset to be read
1974 * @addr: I2C address to be read
1976 static bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr)
1978 if (addr == IXGBE_I2C_EEPROM_DEV_ADDR &&
1979 offset == IXGBE_SFF_IDENTIFIER &&
1980 hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1986 * ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C
1987 * @hw: pointer to hardware structure
1988 * @byte_offset: byte offset to read
1989 * @dev_addr: address to read from
1991 * @lock: true if to take and release semaphore
1993 * Performs byte read operation to SFP module's EEPROM over I2C interface at
1994 * a specified device address.
1996 static s32 ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
1997 u8 dev_addr, u8 *data, bool lock)
2002 u32 swfw_mask = hw->phy.phy_semaphore_mask;
2006 DEBUGFUNC("ixgbe_read_i2c_byte_generic");
2008 if (hw->mac.type >= ixgbe_mac_X550)
2010 if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr))
2011 max_retry = IXGBE_SFP_DETECT_RETRIES;
2014 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
2015 return IXGBE_ERR_SWFW_SYNC;
2017 ixgbe_i2c_start(hw);
2019 /* Device Address and write indication */
2020 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2021 if (status != IXGBE_SUCCESS)
2024 status = ixgbe_get_i2c_ack(hw);
2025 if (status != IXGBE_SUCCESS)
2028 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2029 if (status != IXGBE_SUCCESS)
2032 status = ixgbe_get_i2c_ack(hw);
2033 if (status != IXGBE_SUCCESS)
2036 ixgbe_i2c_start(hw);
2038 /* Device Address and read indication */
2039 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
2040 if (status != IXGBE_SUCCESS)
2043 status = ixgbe_get_i2c_ack(hw);
2044 if (status != IXGBE_SUCCESS)
2047 ixgbe_clock_in_i2c_byte(hw, data);
2049 status = ixgbe_clock_out_i2c_bit(hw, nack);
2050 if (status != IXGBE_SUCCESS)
2055 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2056 return IXGBE_SUCCESS;
2059 ixgbe_i2c_bus_clear(hw);
2061 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2064 if (retry < max_retry)
2065 DEBUGOUT("I2C byte read error - Retrying.\n");
2067 DEBUGOUT("I2C byte read error.\n");
2069 } while (retry <= max_retry);
2075 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
2076 * @hw: pointer to hardware structure
2077 * @byte_offset: byte offset to read
2078 * @dev_addr: address to read from
2081 * Performs byte read operation to SFP module's EEPROM over I2C interface at
2082 * a specified device address.
2084 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2085 u8 dev_addr, u8 *data)
2087 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2092 * ixgbe_read_i2c_byte_generic_unlocked - Reads 8 bit word over I2C
2093 * @hw: pointer to hardware structure
2094 * @byte_offset: byte offset to read
2095 * @dev_addr: address to read from
2098 * Performs byte read operation to SFP module's EEPROM over I2C interface at
2099 * a specified device address.
2101 s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2102 u8 dev_addr, u8 *data)
2104 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2109 * ixgbe_write_i2c_byte_generic_int - Writes 8 bit word over I2C
2110 * @hw: pointer to hardware structure
2111 * @byte_offset: byte offset to write
2112 * @dev_addr: address to write to
2113 * @data: value to write
2114 * @lock: true if to take and release semaphore
2116 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2117 * a specified device address.
2119 static s32 ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
2120 u8 dev_addr, u8 data, bool lock)
2125 u32 swfw_mask = hw->phy.phy_semaphore_mask;
2127 DEBUGFUNC("ixgbe_write_i2c_byte_generic");
2129 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) !=
2131 return IXGBE_ERR_SWFW_SYNC;
2134 ixgbe_i2c_start(hw);
2136 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2137 if (status != IXGBE_SUCCESS)
2140 status = ixgbe_get_i2c_ack(hw);
2141 if (status != IXGBE_SUCCESS)
2144 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2145 if (status != IXGBE_SUCCESS)
2148 status = ixgbe_get_i2c_ack(hw);
2149 if (status != IXGBE_SUCCESS)
2152 status = ixgbe_clock_out_i2c_byte(hw, data);
2153 if (status != IXGBE_SUCCESS)
2156 status = ixgbe_get_i2c_ack(hw);
2157 if (status != IXGBE_SUCCESS)
2162 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2163 return IXGBE_SUCCESS;
2166 ixgbe_i2c_bus_clear(hw);
2167 if (retry < max_retry)
2168 DEBUGOUT("I2C byte write error - Retrying.\n");
2170 DEBUGOUT("I2C byte write error.\n");
2172 } while (retry <= max_retry);
2175 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2181 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
2182 * @hw: pointer to hardware structure
2183 * @byte_offset: byte offset to write
2184 * @dev_addr: address to write to
2185 * @data: value to write
2187 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2188 * a specified device address.
2190 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2191 u8 dev_addr, u8 data)
2193 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2198 * ixgbe_write_i2c_byte_generic_unlocked - Writes 8 bit word over I2C
2199 * @hw: pointer to hardware structure
2200 * @byte_offset: byte offset to write
2201 * @dev_addr: address to write to
2202 * @data: value to write
2204 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2205 * a specified device address.
2207 s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2208 u8 dev_addr, u8 data)
2210 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2215 * ixgbe_i2c_start - Sets I2C start condition
2216 * @hw: pointer to hardware structure
2218 * Sets I2C start condition (High -> Low on SDA while SCL is High)
2219 * Set bit-bang mode on X550 hardware.
2221 static void ixgbe_i2c_start(struct ixgbe_hw *hw)
2223 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2225 DEBUGFUNC("ixgbe_i2c_start");
2227 i2cctl |= IXGBE_I2C_BB_EN_BY_MAC(hw);
2229 /* Start condition must begin with data and clock high */
2230 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2231 ixgbe_raise_i2c_clk(hw, &i2cctl);
2233 /* Setup time for start condition (4.7us) */
2234 usec_delay(IXGBE_I2C_T_SU_STA);
2236 ixgbe_set_i2c_data(hw, &i2cctl, 0);
2238 /* Hold time for start condition (4us) */
2239 usec_delay(IXGBE_I2C_T_HD_STA);
2241 ixgbe_lower_i2c_clk(hw, &i2cctl);
2243 /* Minimum low period of clock is 4.7 us */
2244 usec_delay(IXGBE_I2C_T_LOW);
2249 * ixgbe_i2c_stop - Sets I2C stop condition
2250 * @hw: pointer to hardware structure
2252 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
2253 * Disables bit-bang mode and negates data output enable on X550
2256 static void ixgbe_i2c_stop(struct ixgbe_hw *hw)
2258 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2259 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2260 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2261 u32 bb_en_bit = IXGBE_I2C_BB_EN_BY_MAC(hw);
2263 DEBUGFUNC("ixgbe_i2c_stop");
2265 /* Stop condition must begin with data low and clock high */
2266 ixgbe_set_i2c_data(hw, &i2cctl, 0);
2267 ixgbe_raise_i2c_clk(hw, &i2cctl);
2269 /* Setup time for stop condition (4us) */
2270 usec_delay(IXGBE_I2C_T_SU_STO);
2272 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2274 /* bus free time between stop and start (4.7us)*/
2275 usec_delay(IXGBE_I2C_T_BUF);
2277 if (bb_en_bit || data_oe_bit || clk_oe_bit) {
2278 i2cctl &= ~bb_en_bit;
2279 i2cctl |= data_oe_bit | clk_oe_bit;
2280 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2281 IXGBE_WRITE_FLUSH(hw);
2286 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
2287 * @hw: pointer to hardware structure
2288 * @data: data byte to clock in
2290 * Clocks in one byte data via I2C data/clock
2292 static void ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
2297 DEBUGFUNC("ixgbe_clock_in_i2c_byte");
2300 for (i = 7; i >= 0; i--) {
2301 ixgbe_clock_in_i2c_bit(hw, &bit);
2307 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
2308 * @hw: pointer to hardware structure
2309 * @data: data byte clocked out
2311 * Clocks out one byte data via I2C data/clock
2313 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
2315 s32 status = IXGBE_SUCCESS;
2320 DEBUGFUNC("ixgbe_clock_out_i2c_byte");
2322 for (i = 7; i >= 0; i--) {
2323 bit = (data >> i) & 0x1;
2324 status = ixgbe_clock_out_i2c_bit(hw, bit);
2326 if (status != IXGBE_SUCCESS)
2330 /* Release SDA line (set high) */
2331 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2332 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2333 i2cctl |= IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2334 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2335 IXGBE_WRITE_FLUSH(hw);
2341 * ixgbe_get_i2c_ack - Polls for I2C ACK
2342 * @hw: pointer to hardware structure
2344 * Clocks in/out one bit via I2C data/clock
2346 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
2348 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2349 s32 status = IXGBE_SUCCESS;
2351 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2355 DEBUGFUNC("ixgbe_get_i2c_ack");
2358 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2359 i2cctl |= data_oe_bit;
2360 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2361 IXGBE_WRITE_FLUSH(hw);
2363 ixgbe_raise_i2c_clk(hw, &i2cctl);
2365 /* Minimum high period of clock is 4us */
2366 usec_delay(IXGBE_I2C_T_HIGH);
2368 /* Poll for ACK. Note that ACK in I2C spec is
2369 * transition from 1 to 0 */
2370 for (i = 0; i < timeout; i++) {
2371 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2372 ack = ixgbe_get_i2c_data(hw, &i2cctl);
2380 DEBUGOUT("I2C ack was not received.\n");
2381 status = IXGBE_ERR_I2C;
2384 ixgbe_lower_i2c_clk(hw, &i2cctl);
2386 /* Minimum low period of clock is 4.7 us */
2387 usec_delay(IXGBE_I2C_T_LOW);
2393 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
2394 * @hw: pointer to hardware structure
2395 * @data: read data value
2397 * Clocks in one bit via I2C data/clock
2399 static void ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
2401 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2402 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2404 DEBUGFUNC("ixgbe_clock_in_i2c_bit");
2407 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2408 i2cctl |= data_oe_bit;
2409 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2410 IXGBE_WRITE_FLUSH(hw);
2412 ixgbe_raise_i2c_clk(hw, &i2cctl);
2414 /* Minimum high period of clock is 4us */
2415 usec_delay(IXGBE_I2C_T_HIGH);
2417 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2418 *data = ixgbe_get_i2c_data(hw, &i2cctl);
2420 ixgbe_lower_i2c_clk(hw, &i2cctl);
2422 /* Minimum low period of clock is 4.7 us */
2423 usec_delay(IXGBE_I2C_T_LOW);
2427 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
2428 * @hw: pointer to hardware structure
2429 * @data: data value to write
2431 * Clocks out one bit via I2C data/clock
2433 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
2436 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2438 DEBUGFUNC("ixgbe_clock_out_i2c_bit");
2440 status = ixgbe_set_i2c_data(hw, &i2cctl, data);
2441 if (status == IXGBE_SUCCESS) {
2442 ixgbe_raise_i2c_clk(hw, &i2cctl);
2444 /* Minimum high period of clock is 4us */
2445 usec_delay(IXGBE_I2C_T_HIGH);
2447 ixgbe_lower_i2c_clk(hw, &i2cctl);
2449 /* Minimum low period of clock is 4.7 us.
2450 * This also takes care of the data hold time.
2452 usec_delay(IXGBE_I2C_T_LOW);
2454 status = IXGBE_ERR_I2C;
2455 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2456 "I2C data was not set to %X\n", data);
2463 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock
2464 * @hw: pointer to hardware structure
2465 * @i2cctl: Current value of I2CCTL register
2467 * Raises the I2C clock line '0'->'1'
2468 * Negates the I2C clock output enable on X550 hardware.
2470 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2472 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2474 u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
2477 DEBUGFUNC("ixgbe_raise_i2c_clk");
2480 *i2cctl |= clk_oe_bit;
2481 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2484 for (i = 0; i < timeout; i++) {
2485 *i2cctl |= IXGBE_I2C_CLK_OUT_BY_MAC(hw);
2487 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2488 IXGBE_WRITE_FLUSH(hw);
2489 /* SCL rise time (1000ns) */
2490 usec_delay(IXGBE_I2C_T_RISE);
2492 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2493 if (i2cctl_r & IXGBE_I2C_CLK_IN_BY_MAC(hw))
2499 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
2500 * @hw: pointer to hardware structure
2501 * @i2cctl: Current value of I2CCTL register
2503 * Lowers the I2C clock line '1'->'0'
2504 * Asserts the I2C clock output enable on X550 hardware.
2506 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2508 DEBUGFUNC("ixgbe_lower_i2c_clk");
2510 *i2cctl &= ~(IXGBE_I2C_CLK_OUT_BY_MAC(hw));
2511 *i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2513 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2514 IXGBE_WRITE_FLUSH(hw);
2516 /* SCL fall time (300ns) */
2517 usec_delay(IXGBE_I2C_T_FALL);
2521 * ixgbe_set_i2c_data - Sets the I2C data bit
2522 * @hw: pointer to hardware structure
2523 * @i2cctl: Current value of I2CCTL register
2524 * @data: I2C data value (0 or 1) to set
2526 * Sets the I2C data bit
2527 * Asserts the I2C data output enable on X550 hardware.
2529 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
2531 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2532 s32 status = IXGBE_SUCCESS;
2534 DEBUGFUNC("ixgbe_set_i2c_data");
2537 *i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2539 *i2cctl &= ~(IXGBE_I2C_DATA_OUT_BY_MAC(hw));
2540 *i2cctl &= ~data_oe_bit;
2542 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2543 IXGBE_WRITE_FLUSH(hw);
2545 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
2546 usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
2548 if (!data) /* Can't verify data in this case */
2549 return IXGBE_SUCCESS;
2551 *i2cctl |= data_oe_bit;
2552 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2553 IXGBE_WRITE_FLUSH(hw);
2556 /* Verify data was set correctly */
2557 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2558 if (data != ixgbe_get_i2c_data(hw, i2cctl)) {
2559 status = IXGBE_ERR_I2C;
2560 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2561 "Error - I2C data was not set to %X.\n",
2569 * ixgbe_get_i2c_data - Reads the I2C SDA data bit
2570 * @hw: pointer to hardware structure
2571 * @i2cctl: Current value of I2CCTL register
2573 * Returns the I2C data bit value
2574 * Negates the I2C data output enable on X550 hardware.
2576 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl)
2578 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2581 DEBUGFUNC("ixgbe_get_i2c_data");
2584 *i2cctl |= data_oe_bit;
2585 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2586 IXGBE_WRITE_FLUSH(hw);
2587 usec_delay(IXGBE_I2C_T_FALL);
2590 if (*i2cctl & IXGBE_I2C_DATA_IN_BY_MAC(hw))
2599 * ixgbe_i2c_bus_clear - Clears the I2C bus
2600 * @hw: pointer to hardware structure
2602 * Clears the I2C bus by sending nine clock pulses.
2603 * Used when data line is stuck low.
2605 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
2610 DEBUGFUNC("ixgbe_i2c_bus_clear");
2612 ixgbe_i2c_start(hw);
2613 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2615 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2617 for (i = 0; i < 9; i++) {
2618 ixgbe_raise_i2c_clk(hw, &i2cctl);
2620 /* Min high period of clock is 4us */
2621 usec_delay(IXGBE_I2C_T_HIGH);
2623 ixgbe_lower_i2c_clk(hw, &i2cctl);
2625 /* Min low period of clock is 4.7us*/
2626 usec_delay(IXGBE_I2C_T_LOW);
2629 ixgbe_i2c_start(hw);
2631 /* Put the i2c bus back to default state */
2636 * ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
2637 * @hw: pointer to hardware structure
2639 * Checks if the LASI temp alarm status was triggered due to overtemp
2641 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
2643 s32 status = IXGBE_SUCCESS;
2646 DEBUGFUNC("ixgbe_tn_check_overtemp");
2648 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
2651 /* Check that the LASI temp alarm status was triggered */
2652 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
2653 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data);
2655 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
2658 status = IXGBE_ERR_OVERTEMP;
2659 ERROR_REPORT1(IXGBE_ERROR_CAUTION, "Device over temperature");
2665 * ixgbe_set_copper_phy_power - Control power for copper phy
2666 * @hw: pointer to hardware structure
2667 * @on: true for on, false for off
2669 s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on)
2674 if (!on && ixgbe_mng_present(hw))
2677 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2678 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2684 reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2686 if (ixgbe_check_reset_blocked(hw))
2688 reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2691 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2692 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,