sys/dev/mlx5/mlx5_core/mlx5_fw.c

   1 /*-
   2  * Copyright (c) 2013-2017, Mellanox Technologies, Ltd.  All rights reserved.
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions
   6  * are met:
   7  * 1. Redistributions of source code must retain the above copyright
   8  *    notice, this list of conditions and the following disclaimer.
   9  * 2. Redistributions in binary form must reproduce the above copyright
  10  *    notice, this list of conditions and the following disclaimer in the
  11  *    documentation and/or other materials provided with the distribution.
  12  *
  13  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
  14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  16  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
  17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  23  * SUCH DAMAGE.
  24  *
  25  * $FreeBSD$
  26  */
  27
  28 #include <dev/mlx5/driver.h>
  29 #include <linux/module.h>
  30 #include "mlx5_core.h"
  31
  32 static int mlx5_cmd_query_adapter(struct mlx5_core_dev *dev, u32 *out,
  33                                   int outlen)
  34 {
  35         u32 in[MLX5_ST_SZ_DW(query_adapter_in)];
  36         int err;
  37
  38         memset(in, 0, sizeof(in));
  39
  40         MLX5_SET(query_adapter_in, in, opcode, MLX5_CMD_OP_QUERY_ADAPTER);
  41
  42         err = mlx5_cmd_exec(dev, in, sizeof(in), out, outlen);
  43         return err;
  44 }
  45
  46 int mlx5_query_board_id(struct mlx5_core_dev *dev)
  47 {
  48         u32 *out;
  49         int outlen = MLX5_ST_SZ_BYTES(query_adapter_out);
  50         int err;
  51
  52         out = kzalloc(outlen, GFP_KERNEL);
  53
  54         err = mlx5_cmd_query_adapter(dev, out, outlen);
  55         if (err)
  56                 goto out_out;
  57
  58         memcpy(dev->board_id,
  59                MLX5_ADDR_OF(query_adapter_out, out,
  60                             query_adapter_struct.vsd_contd_psid),
  61                MLX5_FLD_SZ_BYTES(query_adapter_out,
  62                                  query_adapter_struct.vsd_contd_psid));
  63
  64 out_out:
  65         kfree(out);
  66
  67         return err;
  68 }
  69
  70 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id)
  71 {
  72         u32 *out;
  73         int outlen = MLX5_ST_SZ_BYTES(query_adapter_out);
  74         int err;
  75
  76         out = kzalloc(outlen, GFP_KERNEL);
  77
  78         err = mlx5_cmd_query_adapter(mdev, out, outlen);
  79         if (err)
  80                 goto out_out;
  81
  82         *vendor_id = MLX5_GET(query_adapter_out, out,
  83                               query_adapter_struct.ieee_vendor_id);
  84
  85 out_out:
  86         kfree(out);
  87
  88         return err;
  89 }
  90 EXPORT_SYMBOL(mlx5_core_query_vendor_id);
  91
  92 static int mlx5_core_query_special_contexts(struct mlx5_core_dev *dev)
  93 {
  94         u32 in[MLX5_ST_SZ_DW(query_special_contexts_in)];
  95         u32 out[MLX5_ST_SZ_DW(query_special_contexts_out)];
  96         int err;
  97
  98         memset(in, 0, sizeof(in));
  99         memset(out, 0, sizeof(out));
 100
 101         MLX5_SET(query_special_contexts_in, in, opcode,
 102                  MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS);
 103         err = mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
 104         if (err)
 105                 return err;
 106
 107         dev->special_contexts.resd_lkey = MLX5_GET(query_special_contexts_out,
 108                                                    out, resd_lkey);
 109
 110         return err;
 111 }
 112
 113 static int mlx5_get_qcam_reg(struct mlx5_core_dev *dev)
 114 {
 115         return mlx5_query_qcam_reg(dev, dev->caps.qcam,
 116                                    MLX5_QCAM_FEATURE_ENHANCED_FEATURES,
 117                                    MLX5_QCAM_REGS_FIRST_128);
 118 }
 119
 120 static int mlx5_get_pcam_reg(struct mlx5_core_dev *dev)
 121 {
 122         return mlx5_query_pcam_reg(dev, dev->caps.pcam,
 123                                    MLX5_PCAM_FEATURE_ENHANCED_FEATURES,
 124                                    MLX5_PCAM_REGS_5000_TO_507F);
 125 }
 126
 127 static int mlx5_get_mcam_reg(struct mlx5_core_dev *dev)
 128 {
 129         return mlx5_query_mcam_reg(dev, dev->caps.mcam,
 130                                    MLX5_MCAM_FEATURE_ENHANCED_FEATURES,
 131                                    MLX5_MCAM_REGS_FIRST_128);
 132 }
 133
 134 int mlx5_query_hca_caps(struct mlx5_core_dev *dev)
 135 {
 136         int err;
 137
 138         err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL);
 139         if (err)
 140                 return err;
 141
 142         if (MLX5_CAP_GEN(dev, eth_net_offloads)) {
 143                 err = mlx5_core_get_caps(dev, MLX5_CAP_ETHERNET_OFFLOADS);
 144                 if (err)
 145                         return err;
 146         }
 147
 148         if (MLX5_CAP_GEN(dev, pg)) {
 149                 err = mlx5_core_get_caps(dev, MLX5_CAP_ODP);
 150                 if (err)
 151                         return err;
 152         }
 153
 154         if (MLX5_CAP_GEN(dev, atomic)) {
 155                 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC);
 156                 if (err)
 157                         return err;
 158         }
 159
 160         if (MLX5_CAP_GEN(dev, roce)) {
 161                 err = mlx5_core_get_caps(dev, MLX5_CAP_ROCE);
 162                 if (err)
 163                         return err;
 164         }
 165
 166         if ((MLX5_CAP_GEN(dev, port_type) ==
 167             MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET &&
 168             MLX5_CAP_GEN(dev, nic_flow_table)) ||
 169             (MLX5_CAP_GEN(dev, port_type) == MLX5_CMD_HCA_CAP_PORT_TYPE_IB &&
 170             MLX5_CAP_GEN(dev, ipoib_enhanced_offloads))) {
 171                 err = mlx5_core_get_caps(dev, MLX5_CAP_FLOW_TABLE);
 172                 if (err)
 173                         return err;
 174         }
 175
 176         if (MLX5_CAP_GEN(dev, eswitch_flow_table)) {
 177                 err = mlx5_core_get_caps(dev, MLX5_CAP_ESWITCH_FLOW_TABLE);
 178                 if (err)
 179                         return err;
 180         }
 181
 182         if (MLX5_CAP_GEN(dev, vport_group_manager)) {
 183                 err = mlx5_core_get_caps(dev, MLX5_CAP_ESWITCH);
 184                 if (err)
 185                         return err;
 186         }
 187
 188         if (MLX5_CAP_GEN(dev, snapshot)) {
 189                 err = mlx5_core_get_caps(dev, MLX5_CAP_SNAPSHOT);
 190                 if (err)
 191                         return err;
 192         }
 193
 194         if (MLX5_CAP_GEN(dev, ipoib_enhanced_offloads)) {
 195                 err = mlx5_core_get_caps(dev, MLX5_CAP_EOIB_OFFLOADS);
 196                 if (err)
 197                         return err;
 198         }
 199
 200         if (MLX5_CAP_GEN(dev, debug)) {
 201                 err = mlx5_core_get_caps(dev, MLX5_CAP_DEBUG);
 202                 if (err)
 203                         return err;
 204         }
 205
 206         if (MLX5_CAP_GEN(dev, qos)) {
 207                 err = mlx5_core_get_caps(dev, MLX5_CAP_QOS);
 208                 if (err)
 209                         return err;
 210         }
 211
 212         if (MLX5_CAP_GEN(dev, qcam_reg)) {
 213                 err = mlx5_get_qcam_reg(dev);
 214                 if (err)
 215                         return err;
 216         }
 217
 218         if (MLX5_CAP_GEN(dev, mcam_reg)) {
 219                 err = mlx5_get_mcam_reg(dev);
 220                 if (err)
 221                         return err;
 222         }
 223
 224         if (MLX5_CAP_GEN(dev, pcam_reg)) {
 225                 err = mlx5_get_pcam_reg(dev);
 226                 if (err)
 227                         return err;
 228         }
 229
 230         err = mlx5_core_query_special_contexts(dev);
 231         if (err)
 232                 return err;
 233
 234         return 0;
 235 }
 236
 237 int mlx5_cmd_init_hca(struct mlx5_core_dev *dev)
 238 {
 239         u32 in[MLX5_ST_SZ_DW(init_hca_in)];
 240         u32 out[MLX5_ST_SZ_DW(init_hca_out)];
 241
 242         memset(in, 0, sizeof(in));
 243
 244         MLX5_SET(init_hca_in, in, opcode, MLX5_CMD_OP_INIT_HCA);
 245
 246         memset(out, 0, sizeof(out));
 247         return mlx5_cmd_exec(dev, in,  sizeof(in), out, sizeof(out));
 248 }
 249
 250 int mlx5_cmd_teardown_hca(struct mlx5_core_dev *dev)
 251 {
 252         u32 in[MLX5_ST_SZ_DW(teardown_hca_in)] = {0};
 253         u32 out[MLX5_ST_SZ_DW(teardown_hca_out)] = {0};
 254
 255         MLX5_SET(teardown_hca_in, in, opcode, MLX5_CMD_OP_TEARDOWN_HCA);
 256         return mlx5_cmd_exec(dev, in,  sizeof(in), out, sizeof(out));
 257 }
 258
 259 int mlx5_cmd_force_teardown_hca(struct mlx5_core_dev *dev)
 260 {
 261         u32 out[MLX5_ST_SZ_DW(teardown_hca_out)] = {0};
 262         u32 in[MLX5_ST_SZ_DW(teardown_hca_in)] = {0};
 263         int force_state;
 264         int ret;
 265
 266         if (!MLX5_CAP_GEN(dev, force_teardown)) {
 267                 mlx5_core_dbg(dev, "force teardown is not supported in the firmware\n");
 268                 return -EOPNOTSUPP;
 269         }
 270
 271         MLX5_SET(teardown_hca_in, in, opcode, MLX5_CMD_OP_TEARDOWN_HCA);
 272         MLX5_SET(teardown_hca_in, in, profile, MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE);
 273
 274         ret = mlx5_cmd_exec_polling(dev, in, sizeof(in), out, sizeof(out));
 275         if (ret)
 276                 return ret;
 277
 278         force_state = MLX5_GET(teardown_hca_out, out, state);
 279         if (force_state == MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL)  {
 280                 mlx5_core_err(dev, "teardown with force mode failed\n");
 281                 return -EIO;
 282         }
 283
 284         return 0;
 285 }
 286
 287 #define MLX5_FAST_TEARDOWN_WAIT_MS 3000
 288 int mlx5_cmd_fast_teardown_hca(struct mlx5_core_dev *dev)
 289 {
 290         int end, delay_ms = MLX5_FAST_TEARDOWN_WAIT_MS;
 291         u32 out[MLX5_ST_SZ_DW(teardown_hca_out)] = {};
 292         u32 in[MLX5_ST_SZ_DW(teardown_hca_in)] = {};
 293         int state;
 294         int ret;
 295
 296         if (!MLX5_CAP_GEN(dev, fast_teardown)) {
 297                 mlx5_core_dbg(dev, "fast teardown is not supported in the firmware\n");
 298                 return -EOPNOTSUPP;
 299         }
 300
 301         MLX5_SET(teardown_hca_in, in, opcode, MLX5_CMD_OP_TEARDOWN_HCA);
 302         MLX5_SET(teardown_hca_in, in, profile,
 303                  MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN);
 304
 305         ret = mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
 306         if (ret)
 307                 return ret;
 308
 309         state = MLX5_GET(teardown_hca_out, out, state);
 310         if (state == MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL) {
 311                 mlx5_core_warn(dev, "teardown with fast mode failed\n");
 312                 return -EIO;
 313         }
 314
 315         mlx5_set_nic_state(dev, MLX5_NIC_IFC_DISABLED);
 316
 317         /* Loop until device state turns to disable */
 318         end = jiffies + msecs_to_jiffies(delay_ms);
 319         do {
 320                 if (mlx5_get_nic_state(dev) == MLX5_NIC_IFC_DISABLED)
 321                         break;
 322
 323                 pause("W", 1);
 324         } while (!time_after(jiffies, end));
 325
 326         if (mlx5_get_nic_state(dev) != MLX5_NIC_IFC_DISABLED) {
 327                 mlx5_core_err(dev, "NIC IFC still %d after %ums.\n",
 328                         mlx5_get_nic_state(dev), delay_ms);
 329                 return -EIO;
 330         }
 331         return 0;
 332 }
 333
 334 int mlx5_core_set_dc_cnak_trace(struct mlx5_core_dev *dev, int enable,
 335                                 u64 addr)
 336 {
 337         u32 in[MLX5_ST_SZ_DW(set_dc_cnak_trace_in)] = {0};
 338         u32 out[MLX5_ST_SZ_DW(set_dc_cnak_trace_out)] = {0};
 339         __be64 be_addr;
 340         void *pas;
 341
 342         MLX5_SET(set_dc_cnak_trace_in, in, opcode, MLX5_CMD_OP_SET_DC_CNAK_TRACE);
 343         MLX5_SET(set_dc_cnak_trace_in, in, enable, enable);
 344         pas = MLX5_ADDR_OF(set_dc_cnak_trace_in, in, pas);
 345         be_addr = cpu_to_be64(addr);
 346         memcpy(MLX5_ADDR_OF(cmd_pas, pas, pa_h), &be_addr, sizeof(be_addr));
 347
 348         return mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
 349 }
 350
 351 enum mlxsw_reg_mcc_instruction {
 352         MLX5_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE = 0x01,
 353         MLX5_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE = 0x02,
 354         MLX5_REG_MCC_INSTRUCTION_UPDATE_COMPONENT = 0x03,
 355         MLX5_REG_MCC_INSTRUCTION_VERIFY_COMPONENT = 0x04,
 356         MLX5_REG_MCC_INSTRUCTION_ACTIVATE = 0x06,
 357         MLX5_REG_MCC_INSTRUCTION_CANCEL = 0x08,
 358 };
 359
 360 static int mlx5_reg_mcc_set(struct mlx5_core_dev *dev,
 361                             enum mlxsw_reg_mcc_instruction instr,
 362                             u16 component_index, u32 update_handle,
 363                             u32 component_size)
 364 {
 365         u32 out[MLX5_ST_SZ_DW(mcc_reg)];
 366         u32 in[MLX5_ST_SZ_DW(mcc_reg)];
 367
 368         memset(in, 0, sizeof(in));
 369
 370         MLX5_SET(mcc_reg, in, instruction, instr);
 371         MLX5_SET(mcc_reg, in, component_index, component_index);
 372         MLX5_SET(mcc_reg, in, update_handle, update_handle);
 373         MLX5_SET(mcc_reg, in, component_size, component_size);
 374
 375         return mlx5_core_access_reg(dev, in, sizeof(in), out,
 376                                     sizeof(out), MLX5_REG_MCC, 0, 1);
 377 }
 378
 379 static int mlx5_reg_mcc_query(struct mlx5_core_dev *dev,
 380                               u32 *update_handle, u8 *error_code,
 381                               u8 *control_state)
 382 {
 383         u32 out[MLX5_ST_SZ_DW(mcc_reg)];
 384         u32 in[MLX5_ST_SZ_DW(mcc_reg)];
 385         int err;
 386
 387         memset(in, 0, sizeof(in));
 388         memset(out, 0, sizeof(out));
 389         MLX5_SET(mcc_reg, in, update_handle, *update_handle);
 390
 391         err = mlx5_core_access_reg(dev, in, sizeof(in), out,
 392                                    sizeof(out), MLX5_REG_MCC, 0, 0);
 393         if (err)
 394                 goto out;
 395
 396         *update_handle = MLX5_GET(mcc_reg, out, update_handle);
 397         *error_code = MLX5_GET(mcc_reg, out, error_code);
 398         *control_state = MLX5_GET(mcc_reg, out, control_state);
 399
 400 out:
 401         return err;
 402 }
 403
 404 static int mlx5_reg_mcda_set(struct mlx5_core_dev *dev,
 405                              u32 update_handle,
 406                              u32 offset, u16 size,
 407                              u8 *data)
 408 {
 409         int err, in_size = MLX5_ST_SZ_BYTES(mcda_reg) + size;
 410         u32 out[MLX5_ST_SZ_DW(mcda_reg)];
 411         int i, j, dw_size = size >> 2;
 412         __be32 data_element;
 413         u32 *in;
 414
 415         in = kzalloc(in_size, GFP_KERNEL);
 416         if (!in)
 417                 return -ENOMEM;
 418
 419         MLX5_SET(mcda_reg, in, update_handle, update_handle);
 420         MLX5_SET(mcda_reg, in, offset, offset);
 421         MLX5_SET(mcda_reg, in, size, size);
 422
 423         for (i = 0; i < dw_size; i++) {
 424                 j = i * 4;
 425                 data_element = htonl(*(u32 *)&data[j]);
 426                 memcpy(MLX5_ADDR_OF(mcda_reg, in, data) + j, &data_element, 4);
 427         }
 428
 429         err = mlx5_core_access_reg(dev, in, in_size, out,
 430                                    sizeof(out), MLX5_REG_MCDA, 0, 1);
 431         kfree(in);
 432         return err;
 433 }
 434
 435 static int mlx5_reg_mcqi_query(struct mlx5_core_dev *dev,
 436                                u16 component_index,
 437                                u32 *max_component_size,
 438                                u8 *log_mcda_word_size,
 439                                u16 *mcda_max_write_size)
 440 {
 441         u32 out[MLX5_ST_SZ_DW(mcqi_reg) + MLX5_ST_SZ_DW(mcqi_cap)];
 442         int offset = MLX5_ST_SZ_DW(mcqi_reg);
 443         u32 in[MLX5_ST_SZ_DW(mcqi_reg)];
 444         int err;
 445
 446         memset(in, 0, sizeof(in));
 447         memset(out, 0, sizeof(out));
 448
 449         MLX5_SET(mcqi_reg, in, component_index, component_index);
 450         MLX5_SET(mcqi_reg, in, data_size, MLX5_ST_SZ_BYTES(mcqi_cap));
 451
 452         err = mlx5_core_access_reg(dev, in, sizeof(in), out,
 453                                    sizeof(out), MLX5_REG_MCQI, 0, 0);
 454         if (err)
 455                 goto out;
 456
 457         *max_component_size = MLX5_GET(mcqi_cap, out + offset, max_component_size);
 458         *log_mcda_word_size = MLX5_GET(mcqi_cap, out + offset, log_mcda_word_size);
 459         *mcda_max_write_size = MLX5_GET(mcqi_cap, out + offset, mcda_max_write_size);
 460
 461 out:
 462         return err;
 463 }
 464
 465 struct mlx5_mlxfw_dev {
 466         struct mlxfw_dev mlxfw_dev;
 467         struct mlx5_core_dev *mlx5_core_dev;
 468 };
 469
 470 static int mlx5_component_query(struct mlxfw_dev *mlxfw_dev,
 471                                 u16 component_index, u32 *p_max_size,
 472                                 u8 *p_align_bits, u16 *p_max_write_size)
 473 {
 474         struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
 475                 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
 476         struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
 477
 478         return mlx5_reg_mcqi_query(dev, component_index, p_max_size,
 479                                    p_align_bits, p_max_write_size);
 480 }
 481
 482 static int mlx5_fsm_lock(struct mlxfw_dev *mlxfw_dev, u32 *fwhandle)
 483 {
 484         struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
 485                 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
 486         struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
 487         u8 control_state, error_code;
 488         int err;
 489
 490         *fwhandle = 0;
 491         err = mlx5_reg_mcc_query(dev, fwhandle, &error_code, &control_state);
 492         if (err)
 493                 return err;
 494
 495         if (control_state != MLXFW_FSM_STATE_IDLE)
 496                 return -EBUSY;
 497
 498         return mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE,
 499                                 0, *fwhandle, 0);
 500 }
 501
 502 static int mlx5_fsm_component_update(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
 503                                      u16 component_index, u32 component_size)
 504 {
 505         struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
 506                 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
 507         struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
 508
 509         return mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_UPDATE_COMPONENT,
 510                                 component_index, fwhandle, component_size);
 511 }
 512
 513 static int mlx5_fsm_block_download(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
 514                                    u8 *data, u16 size, u32 offset)
 515 {
 516         struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
 517                 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
 518         struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
 519
 520         return mlx5_reg_mcda_set(dev, fwhandle, offset, size, data);
 521 }
 522
 523 static int mlx5_fsm_component_verify(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
 524                                      u16 component_index)
 525 {
 526         struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
 527                 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
 528         struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
 529
 530         return mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_VERIFY_COMPONENT,
 531                                 component_index, fwhandle, 0);
 532 }
 533
 534 static int mlx5_fsm_activate(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
 535 {
 536         struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
 537                 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
 538         struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
 539
 540         return mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_ACTIVATE, 0,
 541                                 fwhandle, 0);
 542 }
 543
 544 static int mlx5_fsm_query_state(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
 545                                 enum mlxfw_fsm_state *fsm_state,
 546                                 enum mlxfw_fsm_state_err *fsm_state_err)
 547 {
 548         struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
 549                 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
 550         struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
 551         u8 control_state, error_code;
 552         int err;
 553
 554         err = mlx5_reg_mcc_query(dev, &fwhandle, &error_code, &control_state);
 555         if (err)
 556                 return err;
 557
 558         *fsm_state = control_state;
 559         *fsm_state_err = min_t(enum mlxfw_fsm_state_err, error_code,
 560                                MLXFW_FSM_STATE_ERR_MAX);
 561         return 0;
 562 }
 563
 564 static void mlx5_fsm_cancel(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
 565 {
 566         struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
 567                 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
 568         struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
 569
 570         mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_CANCEL, 0, fwhandle, 0);
 571 }
 572
 573 static void mlx5_fsm_release(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
 574 {
 575         struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
 576                 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
 577         struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
 578
 579         mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE, 0,
 580                          fwhandle, 0);
 581 }
 582
 583 static const struct mlxfw_dev_ops mlx5_mlxfw_dev_ops = {
 584         .component_query        = mlx5_component_query,
 585         .fsm_lock               = mlx5_fsm_lock,
 586         .fsm_component_update   = mlx5_fsm_component_update,
 587         .fsm_block_download     = mlx5_fsm_block_download,
 588         .fsm_component_verify   = mlx5_fsm_component_verify,
 589         .fsm_activate           = mlx5_fsm_activate,
 590         .fsm_query_state        = mlx5_fsm_query_state,
 591         .fsm_cancel             = mlx5_fsm_cancel,
 592         .fsm_release            = mlx5_fsm_release
 593 };
 594
 595 int mlx5_firmware_flash(struct mlx5_core_dev *dev,
 596                         const struct firmware *firmware)
 597 {
 598         struct mlx5_mlxfw_dev mlx5_mlxfw_dev = {
 599                 .mlxfw_dev = {
 600                         .ops = &mlx5_mlxfw_dev_ops,
 601                         .psid = dev->board_id,
 602                         .psid_size = strlen(dev->board_id),
 603                 },
 604                 .mlx5_core_dev = dev
 605         };
 606
 607         if (!MLX5_CAP_GEN(dev, mcam_reg)  ||
 608             !MLX5_CAP_MCAM_REG(dev, mcqi) ||
 609             !MLX5_CAP_MCAM_REG(dev, mcc)  ||
 610             !MLX5_CAP_MCAM_REG(dev, mcda)) {
 611                 pr_info("%s flashing isn't supported by the running FW\n", __func__);
 612                 return -EOPNOTSUPP;
 613         }
 614
 615         return mlxfw_firmware_flash(&mlx5_mlxfw_dev.mlxfw_dev, firmware);
 616 }