2 * Copyright (c) 2016-2018, Mellanox Technologies, Ltd. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
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28 #ifndef __MLX5_PORT_H__
29 #define __MLX5_PORT_H__
31 #include <dev/mlx5/driver.h>
33 enum mlx5_beacon_duration {
34 MLX5_BEACON_DURATION_OFF = 0x0,
35 MLX5_BEACON_DURATION_INF = 0xffff,
39 MLX5_MODULE_ID_SFP = 0x3,
40 MLX5_MODULE_ID_QSFP = 0xC,
41 MLX5_MODULE_ID_QSFP_PLUS = 0xD,
42 MLX5_MODULE_ID_QSFP28 = 0x11,
46 MLX5_AN_UNAVAILABLE = 0,
50 MLX5_AN_LINK_DOWN = 4,
53 /* EEPROM I2C Addresses */
54 #define MLX5_I2C_ADDR_LOW 0x50
55 #define MLX5_I2C_ADDR_HIGH 0x51
56 #define MLX5_EEPROM_PAGE_LENGTH 256
57 #define MLX5_EEPROM_MAX_BYTES 32
58 #define MLX5_EEPROM_IDENTIFIER_BYTE_MASK 0x000000ff
59 #define MLX5_EEPROM_REVISION_ID_BYTE_MASK 0x0000ff00
60 #define MLX5_EEPROM_PAGE_3_VALID_BIT_MASK 0x00040000
61 #define MLX5_EEPROM_LOW_PAGE 0x0
62 #define MLX5_EEPROM_HIGH_PAGE 0x3
63 #define MLX5_EEPROM_HIGH_PAGE_OFFSET 128
64 #define MLX5_EEPROM_INFO_BYTES 0x3
66 /* EEPROM Standards for plug in modules */
67 #ifndef MLX5_ETH_MODULE_SFF_8472
68 #define MLX5_ETH_MODULE_SFF_8472 0x1
69 #define MLX5_ETH_MODULE_SFF_8472_LEN 128
72 #ifndef MLX5_ETH_MODULE_SFF_8636
73 #define MLX5_ETH_MODULE_SFF_8636 0x2
74 #define MLX5_ETH_MODULE_SFF_8636_LEN 256
77 #ifndef MLX5_ETH_MODULE_SFF_8436
78 #define MLX5_ETH_MODULE_SFF_8436 0x3
79 #define MLX5_ETH_MODULE_SFF_8436_LEN 256
82 enum mlx5e_link_speed {
83 MLX5E_1000BASE_CX_SGMII = 0,
84 MLX5E_1000BASE_KX = 1,
85 MLX5E_10GBASE_CX4 = 2,
86 MLX5E_10GBASE_KX4 = 3,
88 MLX5E_20GBASE_KR2 = 5,
89 MLX5E_40GBASE_CR4 = 6,
90 MLX5E_40GBASE_KR4 = 7,
92 MLX5E_10GBASE_CR = 12,
93 MLX5E_10GBASE_SR = 13,
94 MLX5E_10GBASE_ER_LR = 14,
95 MLX5E_40GBASE_SR4 = 15,
96 MLX5E_40GBASE_LR4_ER4 = 16,
97 MLX5E_50GBASE_SR2 = 18,
98 MLX5E_100GBASE_CR4 = 20,
99 MLX5E_100GBASE_SR4 = 21,
100 MLX5E_100GBASE_KR4 = 22,
101 MLX5E_100GBASE_LR4 = 23,
102 MLX5E_100BASE_TX = 24,
103 MLX5E_1000BASE_T = 25,
104 MLX5E_10GBASE_T = 26,
105 MLX5E_25GBASE_CR = 27,
106 MLX5E_25GBASE_KR = 28,
107 MLX5E_25GBASE_SR = 29,
108 MLX5E_50GBASE_CR2 = 30,
109 MLX5E_50GBASE_KR2 = 31,
110 MLX5E_LINK_SPEEDS_NUMBER,
113 enum mlx5e_ext_link_speed {
114 MLX5E_SGMII_100M = 0,
115 MLX5E_1000BASE_X_SGMII = 1,
117 MLX5E_10GBASE_XFI_XAUI_1 = 4,
118 MLX5E_40GBASE_XLAUI_4_XLPPI_4 = 5,
119 MLX5E_25GAUI_1_25GBASE_CR_KR = 6,
120 MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2 = 7,
121 MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR = 8,
122 MLX5E_CAUI_4_100GBASE_CR4_KR4 = 9,
123 MLX5E_100GAUI_2_100GBASE_CR2_KR2 = 10,
124 MLX5E_200GAUI_4_200GBASE_CR4_KR4 = 12,
125 MLX5E_400GAUI_8 = 15,
126 MLX5E_EXT_LINK_SPEEDS_NUMBER,
129 enum mlx5e_link_mode {
182 MLX5E_LINK_MODES_NUMBER,
185 enum mlx5e_connector_type {
186 MLX5E_PORT_UNKNOWN = 0,
192 MLX5E_PORT_FIBRE = 6,
194 MLX5E_PORT_OTHER = 8,
195 MLX5E_CONNECTOR_TYPE_NUMBER,
198 enum mlx5_qpts_trust_state {
199 MLX5_QPTS_TRUST_PCP = 1,
200 MLX5_QPTS_TRUST_DSCP = 2,
201 MLX5_QPTS_TRUST_BOTH = 3,
203 struct mlx5e_port_eth_proto {
210 #define SPEED_40000 40000
213 #define MLX5E_PROT_MASK(link_mode) (1 << (link_mode))
215 #define PORT_MODULE_EVENT_MODULE_STATUS_MASK 0xF
216 #define PORT_MODULE_EVENT_ERROR_TYPE_MASK 0xF
218 #define MLX5_GET_ETH_PROTO(reg, out, ext, field) \
219 ((ext) ? MLX5_GET(reg, out, ext_##field) : \
220 MLX5_GET(reg, out, field))
222 int mlx5_set_port_caps(struct mlx5_core_dev *dev, u8 port_num, u32 caps);
223 int mlx5_query_port_ptys(struct mlx5_core_dev *dev, u32 *ptys,
224 int ptys_size, int proto_mask, u8 local_port);
225 int mlx5_query_port_proto_cap(struct mlx5_core_dev *dev,
226 u32 *proto_cap, int proto_mask);
227 int mlx5_query_port_autoneg(struct mlx5_core_dev *dev, int proto_mask,
228 u8 *an_disable_cap, u8 *an_disable_status);
229 int mlx5_set_port_autoneg(struct mlx5_core_dev *dev, bool disable,
230 u32 eth_proto_admin, int proto_mask);
231 int mlx5_query_port_proto_admin(struct mlx5_core_dev *dev,
232 u32 *proto_admin, int proto_mask);
233 int mlx5_query_port_eth_proto_oper(struct mlx5_core_dev *dev,
234 u32 *proto_oper, u8 local_port);
235 int mlx5_set_port_proto(struct mlx5_core_dev *dev, u32 proto_admin,
236 int proto_mask, bool ext);
237 int mlx5_set_port_status(struct mlx5_core_dev *dev,
238 enum mlx5_port_status status);
239 int mlx5_query_port_status(struct mlx5_core_dev *dev, u8 *status);
240 int mlx5_query_port_admin_status(struct mlx5_core_dev *dev,
241 enum mlx5_port_status *status);
242 int mlx5_set_port_pause_and_pfc(struct mlx5_core_dev *dev, u32 port,
243 u8 rx_pause, u8 tx_pause,
244 u8 pfc_en_rx, u8 pfc_en_tx);
245 int mlx5_query_port_pause(struct mlx5_core_dev *dev, u32 port,
246 u32 *rx_pause, u32 *tx_pause);
247 int mlx5_query_port_pfc(struct mlx5_core_dev *dev, u8 *pfc_en_tx, u8 *pfc_en_rx);
249 int mlx5_set_port_mtu(struct mlx5_core_dev *dev, int mtu);
250 int mlx5_query_port_max_mtu(struct mlx5_core_dev *dev, int *max_mtu);
251 int mlx5_query_port_oper_mtu(struct mlx5_core_dev *dev, int *oper_mtu);
253 unsigned int mlx5_query_module_status(struct mlx5_core_dev *dev, int module_num);
254 int mlx5_query_module_num(struct mlx5_core_dev *dev, int *module_num);
255 int mlx5_query_eeprom(struct mlx5_core_dev *dev, int i2c_addr, int page_num,
256 int device_addr, int size, int module_num, u32 *data,
259 int mlx5_max_tc(struct mlx5_core_dev *mdev);
260 int mlx5_query_port_tc_rate_limit(struct mlx5_core_dev *mdev,
263 int mlx5_modify_port_tc_rate_limit(struct mlx5_core_dev *mdev,
264 const u8 *max_bw_value,
265 const u8 *max_bw_units);
266 int mlx5_query_port_prio_tc(struct mlx5_core_dev *mdev,
268 int mlx5_set_port_prio_tc(struct mlx5_core_dev *mdev, int prio_index,
270 int mlx5_set_port_tc_group(struct mlx5_core_dev *mdev, const u8 *tc_group);
271 int mlx5_query_port_tc_group(struct mlx5_core_dev *mdev,
272 u8 tc, u8 *tc_group);
273 int mlx5_set_port_tc_bw_alloc(struct mlx5_core_dev *mdev, const u8 *tc_bw);
274 int mlx5_query_port_tc_bw_alloc(struct mlx5_core_dev *mdev, u8 *bw_pct);
276 int mlx5_set_trust_state(struct mlx5_core_dev *mdev, u8 trust_state);
277 int mlx5_query_trust_state(struct mlx5_core_dev *mdev, u8 *trust_state);
279 #define MLX5_MAX_SUPPORTED_DSCP 64
280 int mlx5_set_dscp2prio(struct mlx5_core_dev *mdev, const u8 *dscp2prio);
281 int mlx5_query_dscp2prio(struct mlx5_core_dev *mdev, u8 *dscp2prio);
283 int mlx5_query_pddr_range_info(struct mlx5_core_dev *mdev, u8 local_port, u8 *is_er_type);
285 u32 mlx5e_port_ptys2speed(struct mlx5_core_dev *mdev, u32 eth_proto_oper);
286 int mlx5e_port_linkspeed(struct mlx5_core_dev *mdev, u32 *speed);
287 int mlx5_port_query_eth_proto(struct mlx5_core_dev *dev, u8 port, bool ext,
288 struct mlx5e_port_eth_proto *eproto);
290 int mlx5e_port_query_pbmc(struct mlx5_core_dev *mdev, void *out);
291 int mlx5e_port_set_pbmc(struct mlx5_core_dev *mdev, void *in);
292 int mlx5e_port_query_priority2buffer(struct mlx5_core_dev *mdev, u8 *buffer);
293 int mlx5e_port_set_priority2buffer(struct mlx5_core_dev *mdev, u8 *buffer);
295 #endif /* __MLX5_PORT_H__ */