3 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
5 * Copyright (c) 2010 Hans Petter Selasky. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * USB eXtensible Host Controller Interface, a.k.a. USB 3.0 controller.
32 * The XHCI 1.0 spec can be found at
33 * http://www.intel.com/technology/usb/download/xHCI_Specification_for_USB.pdf
34 * and the USB 3.0 spec at
35 * http://www.usb.org/developers/docs/usb_30_spec_060910.zip
39 * A few words about the design implementation: This driver emulates
40 * the concept about TDs which is found in EHCI specification. This
41 * way we achieve that the USB controller drivers look similar to
42 * eachother which makes it easier to understand the code.
45 #ifdef USB_GLOBAL_INCLUDE_FILE
46 #include USB_GLOBAL_INCLUDE_FILE
48 #include <sys/stdint.h>
49 #include <sys/stddef.h>
50 #include <sys/param.h>
51 #include <sys/queue.h>
52 #include <sys/types.h>
53 #include <sys/systm.h>
54 #include <sys/kernel.h>
56 #include <sys/module.h>
58 #include <sys/mutex.h>
59 #include <sys/condvar.h>
60 #include <sys/sysctl.h>
62 #include <sys/unistd.h>
63 #include <sys/callout.h>
64 #include <sys/malloc.h>
67 #include <dev/usb/usb.h>
68 #include <dev/usb/usbdi.h>
70 #define USB_DEBUG_VAR xhcidebug
72 #include <dev/usb/usb_core.h>
73 #include <dev/usb/usb_debug.h>
74 #include <dev/usb/usb_busdma.h>
75 #include <dev/usb/usb_process.h>
76 #include <dev/usb/usb_transfer.h>
77 #include <dev/usb/usb_device.h>
78 #include <dev/usb/usb_hub.h>
79 #include <dev/usb/usb_util.h>
81 #include <dev/usb/usb_controller.h>
82 #include <dev/usb/usb_bus.h>
83 #endif /* USB_GLOBAL_INCLUDE_FILE */
85 #include <dev/usb/controller/xhci.h>
86 #include <dev/usb/controller/xhcireg.h>
88 #define XHCI_BUS2SC(bus) \
89 __containerof(bus, struct xhci_softc, sc_bus)
91 static SYSCTL_NODE(_hw_usb, OID_AUTO, xhci, CTLFLAG_RW | CTLFLAG_MPSAFE, 0,
94 static int xhcistreams;
95 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, streams, CTLFLAG_RWTUN,
96 &xhcistreams, 0, "Set to enable streams mode support");
98 static int xhcictlquirk = 1;
99 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, ctlquirk, CTLFLAG_RWTUN,
100 &xhcictlquirk, 0, "Set to enable control endpoint quirk");
103 static int xhcidebug;
104 static int xhciroute;
105 static int xhcipolling;
106 static int xhcidma32;
107 static int xhcictlstep;
109 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, debug, CTLFLAG_RWTUN,
110 &xhcidebug, 0, "Debug level");
111 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, xhci_port_route, CTLFLAG_RWTUN,
112 &xhciroute, 0, "Routing bitmap for switching EHCI ports to the XHCI controller");
113 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, use_polling, CTLFLAG_RWTUN,
114 &xhcipolling, 0, "Set to enable software interrupt polling for the XHCI controller");
115 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, dma32, CTLFLAG_RWTUN,
116 &xhcidma32, 0, "Set to only use 32-bit DMA for the XHCI controller");
117 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, ctlstep, CTLFLAG_RWTUN,
118 &xhcictlstep, 0, "Set to enable control endpoint status stage stepping");
122 #define xhcictlstep 0
125 #define XHCI_INTR_ENDPT 1
127 struct xhci_std_temp {
128 struct xhci_softc *sc;
129 struct usb_page_cache *pc;
131 struct xhci_td *td_next;
134 uint32_t max_packet_size;
146 uint8_t do_isoc_sync;
149 static void xhci_do_poll(struct usb_bus *);
150 static void xhci_device_done(struct usb_xfer *, usb_error_t);
151 static void xhci_root_intr(struct xhci_softc *);
152 static void xhci_free_device_ext(struct usb_device *);
153 static struct xhci_endpoint_ext *xhci_get_endpoint_ext(struct usb_device *,
154 struct usb_endpoint_descriptor *);
155 static usb_proc_callback_t xhci_configure_msg;
156 static usb_error_t xhci_configure_device(struct usb_device *);
157 static usb_error_t xhci_configure_endpoint(struct usb_device *,
158 struct usb_endpoint_descriptor *, struct xhci_endpoint_ext *,
159 uint16_t, uint8_t, uint8_t, uint8_t, uint16_t, uint16_t,
161 static usb_error_t xhci_configure_mask(struct usb_device *,
163 static usb_error_t xhci_cmd_evaluate_ctx(struct xhci_softc *,
165 static void xhci_endpoint_doorbell(struct usb_xfer *);
166 static void xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val);
167 static uint32_t xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr);
168 static void xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val);
170 static uint64_t xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr);
173 static const struct usb_bus_methods xhci_bus_methods;
177 xhci_dump_trb(struct xhci_trb *trb)
179 DPRINTFN(5, "trb = %p\n", trb);
180 DPRINTFN(5, "qwTrb0 = 0x%016llx\n", (long long)le64toh(trb->qwTrb0));
181 DPRINTFN(5, "dwTrb2 = 0x%08x\n", le32toh(trb->dwTrb2));
182 DPRINTFN(5, "dwTrb3 = 0x%08x\n", le32toh(trb->dwTrb3));
186 xhci_dump_endpoint(struct xhci_softc *sc, struct xhci_endp_ctx *pep)
188 DPRINTFN(5, "pep = %p\n", pep);
189 DPRINTFN(5, "dwEpCtx0=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx0));
190 DPRINTFN(5, "dwEpCtx1=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx1));
191 DPRINTFN(5, "qwEpCtx2=0x%016llx\n", (long long)xhci_ctx_get_le64(sc, &pep->qwEpCtx2));
192 DPRINTFN(5, "dwEpCtx4=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx4));
193 DPRINTFN(5, "dwEpCtx5=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx5));
194 DPRINTFN(5, "dwEpCtx6=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx6));
195 DPRINTFN(5, "dwEpCtx7=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx7));
199 xhci_dump_device(struct xhci_softc *sc, struct xhci_slot_ctx *psl)
201 DPRINTFN(5, "psl = %p\n", psl);
202 DPRINTFN(5, "dwSctx0=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx0));
203 DPRINTFN(5, "dwSctx1=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx1));
204 DPRINTFN(5, "dwSctx2=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx2));
205 DPRINTFN(5, "dwSctx3=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx3));
210 xhci_use_polling(void)
213 return (xhcipolling != 0);
220 xhci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb)
222 struct xhci_softc *sc = XHCI_BUS2SC(bus);
225 cb(bus, &sc->sc_hw.root_pc, &sc->sc_hw.root_pg,
226 sizeof(struct xhci_hw_root), XHCI_PAGE_SIZE);
228 cb(bus, &sc->sc_hw.ctx_pc, &sc->sc_hw.ctx_pg,
229 sizeof(struct xhci_dev_ctx_addr), XHCI_PAGE_SIZE);
231 for (i = 0; i != sc->sc_noscratch; i++) {
232 cb(bus, &sc->sc_hw.scratch_pc[i], &sc->sc_hw.scratch_pg[i],
233 XHCI_PAGE_SIZE, XHCI_PAGE_SIZE);
238 xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val)
240 if (sc->sc_ctx_is_64_byte) {
242 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
243 /* all contexts are initially 32-bytes */
244 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
245 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset);
251 xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr)
253 if (sc->sc_ctx_is_64_byte) {
255 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
256 /* all contexts are initially 32-bytes */
257 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
258 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset);
260 return (le32toh(*ptr));
264 xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val)
266 if (sc->sc_ctx_is_64_byte) {
268 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
269 /* all contexts are initially 32-bytes */
270 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
271 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset);
278 xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr)
280 if (sc->sc_ctx_is_64_byte) {
282 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
283 /* all contexts are initially 32-bytes */
284 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
285 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset);
287 return (le64toh(*ptr));
292 xhci_reset_command_queue_locked(struct xhci_softc *sc)
294 struct usb_page_search buf_res;
295 struct xhci_hw_root *phwr;
301 temp = XREAD4(sc, oper, XHCI_CRCR_LO);
302 if (temp & XHCI_CRCR_LO_CRR) {
303 DPRINTF("Command ring running\n");
304 temp &= ~(XHCI_CRCR_LO_CS | XHCI_CRCR_LO_CA);
307 * Try to abort the last command as per section
308 * 4.6.1.2 "Aborting a Command" of the XHCI
312 /* stop and cancel */
313 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CS);
314 XWRITE4(sc, oper, XHCI_CRCR_HI, 0);
316 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CA);
317 XWRITE4(sc, oper, XHCI_CRCR_HI, 0);
320 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 4);
322 /* check if command ring is still running */
323 temp = XREAD4(sc, oper, XHCI_CRCR_LO);
324 if (temp & XHCI_CRCR_LO_CRR) {
325 DPRINTF("Comand ring still running\n");
326 return (USB_ERR_IOERROR);
330 /* reset command ring */
331 sc->sc_command_ccs = 1;
332 sc->sc_command_idx = 0;
334 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
336 /* set up command ring control base address */
337 addr = buf_res.physaddr;
338 phwr = buf_res.buffer;
339 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0];
341 DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr);
343 memset(phwr->hwr_commands, 0, sizeof(phwr->hwr_commands));
344 phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr);
346 usb_pc_cpu_flush(&sc->sc_hw.root_pc);
348 XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS);
349 XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32));
355 xhci_start_controller(struct xhci_softc *sc)
357 struct usb_page_search buf_res;
358 struct xhci_hw_root *phwr;
359 struct xhci_dev_ctx_addr *pdctxa;
367 sc->sc_event_ccs = 1;
368 sc->sc_event_idx = 0;
369 sc->sc_command_ccs = 1;
370 sc->sc_command_idx = 0;
372 err = xhci_reset_controller(sc);
376 /* set up number of device slots */
377 DPRINTF("CONFIG=0x%08x -> 0x%08x\n",
378 XREAD4(sc, oper, XHCI_CONFIG), sc->sc_noslot);
380 XWRITE4(sc, oper, XHCI_CONFIG, sc->sc_noslot);
382 temp = XREAD4(sc, oper, XHCI_USBSTS);
384 /* clear interrupts */
385 XWRITE4(sc, oper, XHCI_USBSTS, temp);
386 /* disable all device notifications */
387 XWRITE4(sc, oper, XHCI_DNCTRL, 0);
389 /* set up device context base address */
390 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res);
391 pdctxa = buf_res.buffer;
392 memset(pdctxa, 0, sizeof(*pdctxa));
394 addr = buf_res.physaddr;
395 addr += (uintptr_t)&((struct xhci_dev_ctx_addr *)0)->qwSpBufPtr[0];
397 /* slot 0 points to the table of scratchpad pointers */
398 pdctxa->qwBaaDevCtxAddr[0] = htole64(addr);
400 for (i = 0; i != sc->sc_noscratch; i++) {
401 struct usb_page_search buf_scp;
402 usbd_get_page(&sc->sc_hw.scratch_pc[i], 0, &buf_scp);
403 pdctxa->qwSpBufPtr[i] = htole64((uint64_t)buf_scp.physaddr);
406 addr = buf_res.physaddr;
408 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr);
409 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32));
410 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr);
411 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32));
413 /* set up event table size */
414 DPRINTF("ERSTSZ=0x%08x -> 0x%08x\n",
415 XREAD4(sc, runt, XHCI_ERSTSZ(0)), sc->sc_erst_max);
417 XWRITE4(sc, runt, XHCI_ERSTSZ(0), XHCI_ERSTS_SET(sc->sc_erst_max));
419 /* set up interrupt rate */
420 XWRITE4(sc, runt, XHCI_IMOD(0), sc->sc_imod_default);
422 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
424 phwr = buf_res.buffer;
425 addr = buf_res.physaddr;
426 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[0];
428 /* reset hardware root structure */
429 memset(phwr, 0, sizeof(*phwr));
431 phwr->hwr_ring_seg[0].qwEvrsTablePtr = htole64(addr);
432 phwr->hwr_ring_seg[0].dwEvrsTableSize = htole32(XHCI_MAX_EVENTS);
437 * According to the XHCI specification, the XWRITE4's to
438 * XHCI_ERSTBA_LO and _HI lead to the XHCI to copy the
439 * qwEvrsTablePtr and dwEvrsTableSize values above at that
440 * time, as the XHCI initializes its event ring support. This
441 * is before the event ring starts to pay attention to the
442 * RUN/STOP bit. Thus, make sure the values are observable to
443 * the XHCI before that point.
445 usb_bus_mem_flush_all(&sc->sc_bus, &xhci_iterate_hw_softc);
447 DPRINTF("ERDP(0)=0x%016llx\n", (unsigned long long)addr);
449 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr);
450 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32));
452 addr = buf_res.physaddr;
454 DPRINTF("ERSTBA(0)=0x%016llx\n", (unsigned long long)addr);
456 XWRITE4(sc, runt, XHCI_ERSTBA_LO(0), (uint32_t)addr);
457 XWRITE4(sc, runt, XHCI_ERSTBA_HI(0), (uint32_t)(addr >> 32));
459 /* set up interrupter registers */
460 temp = XREAD4(sc, runt, XHCI_IMAN(0));
461 temp |= XHCI_IMAN_INTR_ENA;
462 XWRITE4(sc, runt, XHCI_IMAN(0), temp);
464 /* set up command ring control base address */
465 addr = buf_res.physaddr;
466 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0];
468 DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr);
470 XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS);
471 XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32));
473 phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr);
475 usb_bus_mem_flush_all(&sc->sc_bus, &xhci_iterate_hw_softc);
478 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_RS |
479 XHCI_CMD_INTE | XHCI_CMD_HSEE);
481 for (i = 0; i != 100; i++) {
482 usb_pause_mtx(NULL, hz / 100);
483 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH;
488 XWRITE4(sc, oper, XHCI_USBCMD, 0);
489 device_printf(sc->sc_bus.parent, "Run timeout.\n");
490 return (USB_ERR_IOERROR);
493 /* catch any lost interrupts */
494 xhci_do_poll(&sc->sc_bus);
496 if (sc->sc_port_route != NULL) {
497 /* Route all ports to the XHCI by default */
498 sc->sc_port_route(sc->sc_bus.parent,
499 ~xhciroute, xhciroute);
505 xhci_halt_controller(struct xhci_softc *sc)
513 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH);
514 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0xF;
515 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3;
517 /* Halt controller */
518 XWRITE4(sc, oper, XHCI_USBCMD, 0);
520 for (i = 0; i != 100; i++) {
521 usb_pause_mtx(NULL, hz / 100);
522 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH;
528 device_printf(sc->sc_bus.parent, "Controller halt timeout.\n");
529 return (USB_ERR_IOERROR);
535 xhci_reset_controller(struct xhci_softc *sc)
542 /* Reset controller */
543 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_HCRST);
545 for (i = 0; i != 100; i++) {
546 usb_pause_mtx(NULL, hz / 100);
547 temp = (XREAD4(sc, oper, XHCI_USBCMD) & XHCI_CMD_HCRST) |
548 (XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_CNR);
554 device_printf(sc->sc_bus.parent, "Controller "
556 return (USB_ERR_IOERROR);
562 xhci_init(struct xhci_softc *sc, device_t self, uint8_t dma32)
568 /* initialize some bus fields */
569 sc->sc_bus.parent = self;
571 /* set the bus revision */
572 sc->sc_bus.usbrev = USB_REV_3_0;
574 /* set up the bus struct */
575 sc->sc_bus.methods = &xhci_bus_methods;
577 /* set up devices array */
578 sc->sc_bus.devices = sc->sc_devices;
579 sc->sc_bus.devices_max = XHCI_MAX_DEVICES;
581 /* set default cycle state in case of early interrupts */
582 sc->sc_event_ccs = 1;
583 sc->sc_command_ccs = 1;
585 /* set up bus space offsets */
587 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH);
588 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0x1F;
589 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3;
591 DPRINTF("CAPLENGTH=0x%x\n", sc->sc_oper_off);
592 DPRINTF("RUNTIMEOFFSET=0x%x\n", sc->sc_runt_off);
593 DPRINTF("DOOROFFSET=0x%x\n", sc->sc_door_off);
595 DPRINTF("xHCI version = 0x%04x\n", XREAD2(sc, capa, XHCI_HCIVERSION));
597 if (!(XREAD4(sc, oper, XHCI_PAGESIZE) & XHCI_PAGESIZE_4K)) {
598 device_printf(sc->sc_bus.parent, "Controller does "
599 "not support 4K page size.\n");
603 temp = XREAD4(sc, capa, XHCI_HCSPARAMS0);
605 DPRINTF("HCS0 = 0x%08x\n", temp);
607 /* set up context size */
608 if (XHCI_HCS0_CSZ(temp)) {
609 sc->sc_ctx_is_64_byte = 1;
611 sc->sc_ctx_is_64_byte = 0;
615 sc->sc_bus.dma_bits = (XHCI_HCS0_AC64(temp) &&
616 xhcidma32 == 0 && dma32 == 0) ? 64 : 32;
618 device_printf(self, "%d bytes context size, %d-bit DMA\n",
619 sc->sc_ctx_is_64_byte ? 64 : 32, (int)sc->sc_bus.dma_bits);
621 /* enable 64Kbyte control endpoint quirk */
622 sc->sc_bus.control_ep_quirk = (xhcictlquirk ? 1 : 0);
624 temp = XREAD4(sc, capa, XHCI_HCSPARAMS1);
626 /* get number of device slots */
627 sc->sc_noport = XHCI_HCS1_N_PORTS(temp);
629 if (sc->sc_noport == 0) {
630 device_printf(sc->sc_bus.parent, "Invalid number "
631 "of ports: %u\n", sc->sc_noport);
635 sc->sc_noport = sc->sc_noport;
636 sc->sc_noslot = XHCI_HCS1_DEVSLOT_MAX(temp);
638 DPRINTF("Max slots: %u\n", sc->sc_noslot);
640 if (sc->sc_noslot > XHCI_MAX_DEVICES)
641 sc->sc_noslot = XHCI_MAX_DEVICES;
643 temp = XREAD4(sc, capa, XHCI_HCSPARAMS2);
645 DPRINTF("HCS2=0x%08x\n", temp);
647 /* get number of scratchpads */
648 sc->sc_noscratch = XHCI_HCS2_SPB_MAX(temp);
650 if (sc->sc_noscratch > XHCI_MAX_SCRATCHPADS) {
651 device_printf(sc->sc_bus.parent, "XHCI request "
652 "too many scratchpads\n");
656 DPRINTF("Max scratch: %u\n", sc->sc_noscratch);
658 /* get event table size */
659 sc->sc_erst_max = 1U << XHCI_HCS2_ERST_MAX(temp);
660 if (sc->sc_erst_max > XHCI_MAX_RSEG)
661 sc->sc_erst_max = XHCI_MAX_RSEG;
663 temp = XREAD4(sc, capa, XHCI_HCSPARAMS3);
665 /* get maximum exit latency */
666 sc->sc_exit_lat_max = XHCI_HCS3_U1_DEL(temp) +
667 XHCI_HCS3_U2_DEL(temp) + 250 /* us */;
669 /* Check if we should use the default IMOD value. */
670 if (sc->sc_imod_default == 0)
671 sc->sc_imod_default = XHCI_IMOD_DEFAULT;
673 /* get all DMA memory */
674 if (usb_bus_mem_alloc_all(&sc->sc_bus,
675 USB_GET_DMA_TAG(self), &xhci_iterate_hw_softc)) {
679 /* set up command queue mutex and condition varible */
680 cv_init(&sc->sc_cmd_cv, "CMDQ");
681 sx_init(&sc->sc_cmd_sx, "CMDQ lock");
683 sc->sc_config_msg[0].hdr.pm_callback = &xhci_configure_msg;
684 sc->sc_config_msg[0].bus = &sc->sc_bus;
685 sc->sc_config_msg[1].hdr.pm_callback = &xhci_configure_msg;
686 sc->sc_config_msg[1].bus = &sc->sc_bus;
692 xhci_uninit(struct xhci_softc *sc)
695 * NOTE: At this point the control transfer process is gone
696 * and "xhci_configure_msg" is no longer called. Consequently
697 * waiting for the configuration messages to complete is not
700 usb_bus_mem_free_all(&sc->sc_bus, &xhci_iterate_hw_softc);
702 cv_destroy(&sc->sc_cmd_cv);
703 sx_destroy(&sc->sc_cmd_sx);
707 xhci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
709 struct xhci_softc *sc = XHCI_BUS2SC(bus);
712 case USB_HW_POWER_SUSPEND:
713 DPRINTF("Stopping the XHCI\n");
714 xhci_halt_controller(sc);
715 xhci_reset_controller(sc);
717 case USB_HW_POWER_SHUTDOWN:
718 DPRINTF("Stopping the XHCI\n");
719 xhci_halt_controller(sc);
720 xhci_reset_controller(sc);
722 case USB_HW_POWER_RESUME:
723 DPRINTF("Starting the XHCI\n");
724 xhci_start_controller(sc);
732 xhci_generic_done_sub(struct usb_xfer *xfer)
735 struct xhci_td *td_alt_next;
739 td = xfer->td_transfer_cache;
740 td_alt_next = td->alt_next;
742 if (xfer->aframes != xfer->nframes)
743 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0);
746 usb_pc_cpu_invalidate(td->page_cache);
751 DPRINTFN(4, "xfer=%p[%u/%u] rem=%u/%u status=%u\n",
752 xfer, (unsigned int)xfer->aframes,
753 (unsigned int)xfer->nframes,
754 (unsigned int)len, (unsigned int)td->len,
755 (unsigned int)status);
758 * Verify the status length and
759 * add the length to "frlengths[]":
762 /* should not happen */
763 DPRINTF("Invalid status length, "
764 "0x%04x/0x%04x bytes\n", len, td->len);
765 status = XHCI_TRB_ERROR_LENGTH;
766 } else if (xfer->aframes != xfer->nframes) {
767 xfer->frlengths[xfer->aframes] += td->len - len;
769 /* Check for last transfer */
770 if (((void *)td) == xfer->td_transfer_last) {
774 /* Check for transfer error */
775 if (status != XHCI_TRB_ERROR_SHORT_PKT &&
776 status != XHCI_TRB_ERROR_SUCCESS) {
777 /* the transfer is finished */
781 /* Check for short transfer */
783 if (xfer->flags_int.short_frames_ok ||
784 xfer->flags_int.isochronous_xfr ||
785 xfer->flags_int.control_xfr) {
786 /* follow alt next */
789 /* the transfer is finished */
796 if (td->alt_next != td_alt_next) {
797 /* this USB frame is complete */
802 /* update transfer cache */
804 xfer->td_transfer_cache = td;
806 return ((status == XHCI_TRB_ERROR_STALL) ? USB_ERR_STALLED :
807 (status != XHCI_TRB_ERROR_SHORT_PKT &&
808 status != XHCI_TRB_ERROR_SUCCESS) ? USB_ERR_IOERROR :
809 USB_ERR_NORMAL_COMPLETION);
813 xhci_generic_done(struct usb_xfer *xfer)
817 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
818 xfer, xfer->endpoint);
822 xfer->td_transfer_cache = xfer->td_transfer_first;
824 if (xfer->flags_int.control_xfr) {
825 if (xfer->flags_int.control_hdr)
826 err = xhci_generic_done_sub(xfer);
830 if (xfer->td_transfer_cache == NULL)
834 while (xfer->aframes != xfer->nframes) {
835 err = xhci_generic_done_sub(xfer);
838 if (xfer->td_transfer_cache == NULL)
842 if (xfer->flags_int.control_xfr &&
843 !xfer->flags_int.control_act)
844 err = xhci_generic_done_sub(xfer);
846 /* transfer is complete */
847 xhci_device_done(xfer, err);
851 xhci_activate_transfer(struct usb_xfer *xfer)
855 td = xfer->td_transfer_cache;
857 usb_pc_cpu_invalidate(td->page_cache);
859 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) {
860 /* activate the transfer */
862 td->td_trb[0].dwTrb3 |= htole32(XHCI_TRB_3_CYCLE_BIT);
863 usb_pc_cpu_flush(td->page_cache);
865 xhci_endpoint_doorbell(xfer);
870 xhci_skip_transfer(struct usb_xfer *xfer)
873 struct xhci_td *td_last;
875 td = xfer->td_transfer_cache;
876 td_last = xfer->td_transfer_last;
880 usb_pc_cpu_invalidate(td->page_cache);
882 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) {
883 usb_pc_cpu_invalidate(td_last->page_cache);
885 /* copy LINK TRB to current waiting location */
887 td->td_trb[0].qwTrb0 = td_last->td_trb[td_last->ntrb].qwTrb0;
888 td->td_trb[0].dwTrb2 = td_last->td_trb[td_last->ntrb].dwTrb2;
889 usb_pc_cpu_flush(td->page_cache);
891 td->td_trb[0].dwTrb3 = td_last->td_trb[td_last->ntrb].dwTrb3;
892 usb_pc_cpu_flush(td->page_cache);
894 xhci_endpoint_doorbell(xfer);
898 /*------------------------------------------------------------------------*
899 * xhci_check_transfer
900 *------------------------------------------------------------------------*/
902 xhci_check_transfer(struct xhci_softc *sc, struct xhci_trb *trb)
904 struct xhci_endpoint_ext *pepext;
909 uint16_t stream_id = 0;
917 td_event = le64toh(trb->qwTrb0);
918 temp = le32toh(trb->dwTrb2);
920 remainder = XHCI_TRB_2_REM_GET(temp);
921 status = XHCI_TRB_2_ERROR_GET(temp);
923 temp = le32toh(trb->dwTrb3);
924 epno = XHCI_TRB_3_EP_GET(temp);
925 index = XHCI_TRB_3_SLOT_GET(temp);
927 /* check if error means halted */
928 halted = (status != XHCI_TRB_ERROR_SHORT_PKT &&
929 status != XHCI_TRB_ERROR_SUCCESS);
931 DPRINTF("slot=%u epno=%u remainder=%u status=%u\n",
932 index, epno, remainder, status);
934 if (index > sc->sc_noslot) {
935 DPRINTF("Invalid slot.\n");
939 if ((epno == 0) || (epno >= XHCI_MAX_ENDPOINTS)) {
940 DPRINTF("Invalid endpoint.\n");
944 pepext = &sc->sc_hw.devs[index].endp[epno];
946 /* try to find the USB transfer that generated the event */
948 struct usb_xfer *xfer;
951 if (i == (XHCI_MAX_TRANSFERS - 1)) {
952 if (pepext->trb_ep_mode != USB_EP_MODE_STREAMS ||
953 stream_id == (XHCI_MAX_STREAMS - 1))
957 DPRINTFN(5, "stream_id=%u\n", stream_id);
960 xfer = pepext->xfer[i + (XHCI_MAX_TRANSFERS * stream_id)];
964 td = xfer->td_transfer_cache;
966 DPRINTFN(5, "Checking if 0x%016llx == (0x%016llx .. 0x%016llx)\n",
968 (long long)td->td_self,
969 (long long)td->td_self + sizeof(td->td_trb));
972 * NOTE: Some XHCI implementations might not trigger
973 * an event on the last LINK TRB so we need to
974 * consider both the last and second last event
975 * address as conditions for a successful transfer.
977 * NOTE: We assume that the XHCI will only trigger one
978 * event per chain of TRBs.
981 offset = td_event - td->td_self;
984 offset < (int64_t)sizeof(td->td_trb)) {
985 usb_pc_cpu_invalidate(td->page_cache);
987 /* compute rest of remainder, if any */
988 for (i = (offset / 16) + 1; i < td->ntrb; i++) {
989 temp = le32toh(td->td_trb[i].dwTrb2);
990 remainder += XHCI_TRB_2_BYTES_GET(temp);
993 DPRINTFN(5, "New remainder: %u\n", remainder);
995 /* clear isochronous transfer errors */
996 if (xfer->flags_int.isochronous_xfr) {
999 status = XHCI_TRB_ERROR_SUCCESS;
1000 remainder = td->len;
1004 /* "td->remainder" is verified later */
1005 td->remainder = remainder;
1006 td->status = status;
1008 usb_pc_cpu_flush(td->page_cache);
1011 * 1) Last transfer descriptor makes the
1014 if (((void *)td) == xfer->td_transfer_last) {
1015 DPRINTF("TD is last\n");
1016 xhci_generic_done(xfer);
1021 * 2) Any kind of error makes the transfer
1025 DPRINTF("TD has I/O error\n");
1026 xhci_generic_done(xfer);
1031 * 3) If there is no alternate next transfer,
1032 * a short packet also makes the transfer done
1034 if (td->remainder > 0) {
1035 if (td->alt_next == NULL) {
1037 "short TD has no alternate next\n");
1038 xhci_generic_done(xfer);
1041 DPRINTF("TD has short pkt\n");
1042 if (xfer->flags_int.short_frames_ok ||
1043 xfer->flags_int.isochronous_xfr ||
1044 xfer->flags_int.control_xfr) {
1045 /* follow the alt next */
1046 xfer->td_transfer_cache = td->alt_next;
1047 xhci_activate_transfer(xfer);
1050 xhci_skip_transfer(xfer);
1051 xhci_generic_done(xfer);
1056 * 4) Transfer complete - go to next TD
1058 DPRINTF("Following next TD\n");
1059 xfer->td_transfer_cache = td->obj_next;
1060 xhci_activate_transfer(xfer);
1061 break; /* there should only be one match */
1067 xhci_check_command(struct xhci_softc *sc, struct xhci_trb *trb)
1069 if (sc->sc_cmd_addr == trb->qwTrb0) {
1070 DPRINTF("Received command event\n");
1071 sc->sc_cmd_result[0] = trb->dwTrb2;
1072 sc->sc_cmd_result[1] = trb->dwTrb3;
1073 cv_signal(&sc->sc_cmd_cv);
1074 return (1); /* command match */
1080 xhci_interrupt_poll(struct xhci_softc *sc)
1082 struct usb_page_search buf_res;
1083 struct xhci_hw_root *phwr;
1093 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
1095 phwr = buf_res.buffer;
1097 /* Receive any events */
1099 usb_pc_cpu_invalidate(&sc->sc_hw.root_pc);
1101 i = sc->sc_event_idx;
1102 j = sc->sc_event_ccs;
1106 temp = le32toh(phwr->hwr_events[i].dwTrb3);
1108 k = (temp & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0;
1113 event = XHCI_TRB_3_TYPE_GET(temp);
1115 DPRINTFN(10, "event[%u] = %u (0x%016llx 0x%08lx 0x%08lx)\n",
1116 i, event, (long long)le64toh(phwr->hwr_events[i].qwTrb0),
1117 (long)le32toh(phwr->hwr_events[i].dwTrb2),
1118 (long)le32toh(phwr->hwr_events[i].dwTrb3));
1121 case XHCI_TRB_EVENT_TRANSFER:
1122 xhci_check_transfer(sc, &phwr->hwr_events[i]);
1124 case XHCI_TRB_EVENT_CMD_COMPLETE:
1125 retval |= xhci_check_command(sc, &phwr->hwr_events[i]);
1128 DPRINTF("Unhandled event = %u\n", event);
1134 if (i == XHCI_MAX_EVENTS) {
1138 /* check for timeout */
1144 sc->sc_event_idx = i;
1145 sc->sc_event_ccs = j;
1148 * NOTE: The Event Ring Dequeue Pointer Register is 64-bit
1149 * latched. That means to activate the register we need to
1150 * write both the low and high double word of the 64-bit
1154 addr = buf_res.physaddr;
1155 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[i];
1157 /* try to clear busy bit */
1158 addr |= XHCI_ERDP_LO_BUSY;
1160 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr);
1161 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32));
1167 xhci_do_command(struct xhci_softc *sc, struct xhci_trb *trb,
1168 uint16_t timeout_ms)
1170 struct usb_page_search buf_res;
1171 struct xhci_hw_root *phwr;
1176 uint8_t timeout = 0;
1179 XHCI_CMD_ASSERT_LOCKED(sc);
1181 /* get hardware root structure */
1183 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
1185 phwr = buf_res.buffer;
1189 USB_BUS_LOCK(&sc->sc_bus);
1191 i = sc->sc_command_idx;
1192 j = sc->sc_command_ccs;
1194 DPRINTFN(10, "command[%u] = %u (0x%016llx, 0x%08lx, 0x%08lx)\n",
1195 i, XHCI_TRB_3_TYPE_GET(le32toh(trb->dwTrb3)),
1196 (long long)le64toh(trb->qwTrb0),
1197 (long)le32toh(trb->dwTrb2),
1198 (long)le32toh(trb->dwTrb3));
1200 phwr->hwr_commands[i].qwTrb0 = trb->qwTrb0;
1201 phwr->hwr_commands[i].dwTrb2 = trb->dwTrb2;
1203 usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1208 temp |= htole32(XHCI_TRB_3_CYCLE_BIT);
1210 temp &= ~htole32(XHCI_TRB_3_CYCLE_BIT);
1212 temp &= ~htole32(XHCI_TRB_3_TC_BIT);
1214 phwr->hwr_commands[i].dwTrb3 = temp;
1216 usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1218 addr = buf_res.physaddr;
1219 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[i];
1221 sc->sc_cmd_addr = htole64(addr);
1225 if (i == (XHCI_MAX_COMMANDS - 1)) {
1227 temp = htole32(XHCI_TRB_3_TC_BIT |
1228 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) |
1229 XHCI_TRB_3_CYCLE_BIT);
1231 temp = htole32(XHCI_TRB_3_TC_BIT |
1232 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
1235 phwr->hwr_commands[i].dwTrb3 = temp;
1237 usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1243 sc->sc_command_idx = i;
1244 sc->sc_command_ccs = j;
1246 XWRITE4(sc, door, XHCI_DOORBELL(0), 0);
1248 err = cv_timedwait(&sc->sc_cmd_cv, &sc->sc_bus.bus_mtx,
1249 USB_MS_TO_TICKS(timeout_ms));
1252 * In some error cases event interrupts are not generated.
1253 * Poll one time to see if the command has completed.
1255 if (err != 0 && xhci_interrupt_poll(sc) != 0) {
1256 DPRINTF("Command was completed when polling\n");
1260 DPRINTF("Command timeout!\n");
1262 * After some weeks of continuous operation, it has
1263 * been observed that the ASMedia Technology, ASM1042
1264 * SuperSpeed USB Host Controller can suddenly stop
1265 * accepting commands via the command queue. Try to
1266 * first reset the command queue. If that fails do a
1267 * host controller reset.
1270 xhci_reset_command_queue_locked(sc) == 0) {
1271 temp = le32toh(trb->dwTrb3);
1274 * Avoid infinite XHCI reset loops if the set
1275 * address command fails to respond due to a
1276 * non-enumerating device:
1278 if (XHCI_TRB_3_TYPE_GET(temp) == XHCI_TRB_TYPE_ADDRESS_DEVICE &&
1279 (temp & XHCI_TRB_3_BSR_BIT) == 0) {
1280 DPRINTF("Set address timeout\n");
1286 DPRINTF("Controller reset!\n");
1287 usb_bus_reset_async_locked(&sc->sc_bus);
1289 err = USB_ERR_TIMEOUT;
1293 temp = le32toh(sc->sc_cmd_result[0]);
1294 if (XHCI_TRB_2_ERROR_GET(temp) != XHCI_TRB_ERROR_SUCCESS)
1295 err = USB_ERR_IOERROR;
1297 trb->dwTrb2 = sc->sc_cmd_result[0];
1298 trb->dwTrb3 = sc->sc_cmd_result[1];
1301 USB_BUS_UNLOCK(&sc->sc_bus);
1308 xhci_cmd_nop(struct xhci_softc *sc)
1310 struct xhci_trb trb;
1317 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NOOP);
1319 trb.dwTrb3 = htole32(temp);
1321 return (xhci_do_command(sc, &trb, 100 /* ms */));
1326 xhci_cmd_enable_slot(struct xhci_softc *sc, uint8_t *pslot)
1328 struct xhci_trb trb;
1336 trb.dwTrb3 = htole32(XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT));
1338 err = xhci_do_command(sc, &trb, 100 /* ms */);
1342 temp = le32toh(trb.dwTrb3);
1344 *pslot = XHCI_TRB_3_SLOT_GET(temp);
1351 xhci_cmd_disable_slot(struct xhci_softc *sc, uint8_t slot_id)
1353 struct xhci_trb trb;
1360 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT) |
1361 XHCI_TRB_3_SLOT_SET(slot_id);
1363 trb.dwTrb3 = htole32(temp);
1365 return (xhci_do_command(sc, &trb, 100 /* ms */));
1369 xhci_cmd_set_address(struct xhci_softc *sc, uint64_t input_ctx,
1370 uint8_t bsr, uint8_t slot_id)
1372 struct xhci_trb trb;
1377 trb.qwTrb0 = htole64(input_ctx);
1379 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) |
1380 XHCI_TRB_3_SLOT_SET(slot_id);
1383 temp |= XHCI_TRB_3_BSR_BIT;
1385 trb.dwTrb3 = htole32(temp);
1387 return (xhci_do_command(sc, &trb, 500 /* ms */));
1391 xhci_set_address(struct usb_device *udev, struct mtx *mtx, uint16_t address)
1393 struct usb_page_search buf_inp;
1394 struct usb_page_search buf_dev;
1395 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
1396 struct xhci_hw_dev *hdev;
1397 struct xhci_dev_ctx *pdev;
1398 struct xhci_endpoint_ext *pepext;
1404 /* the root HUB case is not handled here */
1405 if (udev->parent_hub == NULL)
1406 return (USB_ERR_INVAL);
1408 index = udev->controller_slot_id;
1410 hdev = &sc->sc_hw.devs[index];
1417 switch (hdev->state) {
1418 case XHCI_ST_DEFAULT:
1419 case XHCI_ST_ENABLED:
1421 hdev->state = XHCI_ST_ENABLED;
1423 /* set configure mask to slot and EP0 */
1424 xhci_configure_mask(udev, 3, 0);
1426 /* configure input slot context structure */
1427 err = xhci_configure_device(udev);
1430 DPRINTF("Could not configure device\n");
1434 /* configure input endpoint context structure */
1435 switch (udev->speed) {
1437 case USB_SPEED_FULL:
1440 case USB_SPEED_HIGH:
1448 pepext = xhci_get_endpoint_ext(udev,
1449 &udev->ctrl_ep_desc);
1451 /* ensure the control endpoint is setup again */
1452 USB_BUS_LOCK(udev->bus);
1453 pepext->trb_halted = 1;
1454 pepext->trb_running = 0;
1455 USB_BUS_UNLOCK(udev->bus);
1457 err = xhci_configure_endpoint(udev,
1458 &udev->ctrl_ep_desc, pepext,
1459 0, 1, 1, 0, mps, mps, USB_EP_MODE_DEFAULT);
1462 DPRINTF("Could not configure default endpoint\n");
1466 /* execute set address command */
1467 usbd_get_page(&hdev->input_pc, 0, &buf_inp);
1469 err = xhci_cmd_set_address(sc, buf_inp.physaddr,
1470 (address == 0), index);
1473 temp = le32toh(sc->sc_cmd_result[0]);
1474 if (address == 0 && sc->sc_port_route != NULL &&
1475 XHCI_TRB_2_ERROR_GET(temp) ==
1476 XHCI_TRB_ERROR_PARAMETER) {
1477 /* LynxPoint XHCI - ports are not switchable */
1478 /* Un-route all ports from the XHCI */
1479 sc->sc_port_route(sc->sc_bus.parent, 0, ~0);
1481 DPRINTF("Could not set address "
1482 "for slot %u.\n", index);
1487 /* update device address to new value */
1489 usbd_get_page(&hdev->device_pc, 0, &buf_dev);
1490 pdev = buf_dev.buffer;
1491 usb_pc_cpu_invalidate(&hdev->device_pc);
1493 temp = xhci_ctx_get_le32(sc, &pdev->ctx_slot.dwSctx3);
1494 udev->address = XHCI_SCTX_3_DEV_ADDR_GET(temp);
1496 /* update device state to new value */
1499 hdev->state = XHCI_ST_ADDRESSED;
1501 hdev->state = XHCI_ST_DEFAULT;
1505 DPRINTF("Wrong state for set address.\n");
1506 err = USB_ERR_IOERROR;
1509 XHCI_CMD_UNLOCK(sc);
1518 xhci_cmd_configure_ep(struct xhci_softc *sc, uint64_t input_ctx,
1519 uint8_t deconfigure, uint8_t slot_id)
1521 struct xhci_trb trb;
1526 trb.qwTrb0 = htole64(input_ctx);
1528 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP) |
1529 XHCI_TRB_3_SLOT_SET(slot_id);
1532 temp |= XHCI_TRB_3_DCEP_BIT;
1534 trb.dwTrb3 = htole32(temp);
1536 return (xhci_do_command(sc, &trb, 100 /* ms */));
1540 xhci_cmd_evaluate_ctx(struct xhci_softc *sc, uint64_t input_ctx,
1543 struct xhci_trb trb;
1548 trb.qwTrb0 = htole64(input_ctx);
1550 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX) |
1551 XHCI_TRB_3_SLOT_SET(slot_id);
1552 trb.dwTrb3 = htole32(temp);
1554 return (xhci_do_command(sc, &trb, 100 /* ms */));
1558 xhci_cmd_reset_ep(struct xhci_softc *sc, uint8_t preserve,
1559 uint8_t ep_id, uint8_t slot_id)
1561 struct xhci_trb trb;
1568 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP) |
1569 XHCI_TRB_3_SLOT_SET(slot_id) |
1570 XHCI_TRB_3_EP_SET(ep_id);
1573 temp |= XHCI_TRB_3_PRSV_BIT;
1575 trb.dwTrb3 = htole32(temp);
1577 return (xhci_do_command(sc, &trb, 100 /* ms */));
1581 xhci_cmd_set_tr_dequeue_ptr(struct xhci_softc *sc, uint64_t dequeue_ptr,
1582 uint16_t stream_id, uint8_t ep_id, uint8_t slot_id)
1584 struct xhci_trb trb;
1589 trb.qwTrb0 = htole64(dequeue_ptr);
1591 temp = XHCI_TRB_2_STREAM_SET(stream_id);
1592 trb.dwTrb2 = htole32(temp);
1594 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE) |
1595 XHCI_TRB_3_SLOT_SET(slot_id) |
1596 XHCI_TRB_3_EP_SET(ep_id);
1597 trb.dwTrb3 = htole32(temp);
1599 return (xhci_do_command(sc, &trb, 100 /* ms */));
1603 xhci_cmd_stop_ep(struct xhci_softc *sc, uint8_t suspend,
1604 uint8_t ep_id, uint8_t slot_id)
1606 struct xhci_trb trb;
1613 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP) |
1614 XHCI_TRB_3_SLOT_SET(slot_id) |
1615 XHCI_TRB_3_EP_SET(ep_id);
1618 temp |= XHCI_TRB_3_SUSP_EP_BIT;
1620 trb.dwTrb3 = htole32(temp);
1622 return (xhci_do_command(sc, &trb, 100 /* ms */));
1626 xhci_cmd_reset_dev(struct xhci_softc *sc, uint8_t slot_id)
1628 struct xhci_trb trb;
1635 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_DEVICE) |
1636 XHCI_TRB_3_SLOT_SET(slot_id);
1638 trb.dwTrb3 = htole32(temp);
1640 return (xhci_do_command(sc, &trb, 100 /* ms */));
1643 /*------------------------------------------------------------------------*
1644 * xhci_interrupt - XHCI interrupt handler
1645 *------------------------------------------------------------------------*/
1647 xhci_interrupt(struct xhci_softc *sc)
1652 USB_BUS_LOCK(&sc->sc_bus);
1654 status = XREAD4(sc, oper, XHCI_USBSTS);
1656 /* acknowledge interrupts, if any */
1658 XWRITE4(sc, oper, XHCI_USBSTS, status);
1659 DPRINTFN(16, "real interrupt (status=0x%08x)\n", status);
1662 temp = XREAD4(sc, runt, XHCI_IMAN(0));
1664 /* force clearing of pending interrupts */
1665 if (temp & XHCI_IMAN_INTR_PEND)
1666 XWRITE4(sc, runt, XHCI_IMAN(0), temp);
1668 /* check for event(s) */
1669 xhci_interrupt_poll(sc);
1671 if (status & (XHCI_STS_PCD | XHCI_STS_HCH |
1672 XHCI_STS_HSE | XHCI_STS_HCE)) {
1673 if (status & XHCI_STS_PCD) {
1677 if (status & XHCI_STS_HCH) {
1678 printf("%s: host controller halted\n",
1682 if (status & XHCI_STS_HSE) {
1683 printf("%s: host system error\n",
1687 if (status & XHCI_STS_HCE) {
1688 printf("%s: host controller error\n",
1692 USB_BUS_UNLOCK(&sc->sc_bus);
1695 /*------------------------------------------------------------------------*
1696 * xhci_timeout - XHCI timeout handler
1697 *------------------------------------------------------------------------*/
1699 xhci_timeout(void *arg)
1701 struct usb_xfer *xfer = arg;
1703 DPRINTF("xfer=%p\n", xfer);
1705 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
1707 /* transfer is transferred */
1708 xhci_device_done(xfer, USB_ERR_TIMEOUT);
1712 xhci_do_poll(struct usb_bus *bus)
1714 struct xhci_softc *sc = XHCI_BUS2SC(bus);
1716 USB_BUS_LOCK(&sc->sc_bus);
1717 xhci_interrupt_poll(sc);
1718 USB_BUS_UNLOCK(&sc->sc_bus);
1722 xhci_setup_generic_chain_sub(struct xhci_std_temp *temp)
1724 struct usb_page_search buf_res;
1726 struct xhci_td *td_next;
1727 struct xhci_td *td_alt_next;
1728 struct xhci_td *td_first;
1729 uint32_t buf_offset;
1734 uint8_t shortpkt_old;
1740 shortpkt_old = temp->shortpkt;
1741 len_old = temp->len;
1748 td_next = td_first = temp->td_next;
1751 if (temp->len == 0) {
1755 /* send a Zero Length Packet, ZLP, last */
1761 average = temp->average;
1763 if (temp->len < average) {
1764 if (temp->len % temp->max_packet_size) {
1767 average = temp->len;
1771 if (td_next == NULL)
1772 panic("%s: out of XHCI transfer descriptors!", __FUNCTION__);
1777 td_next = td->obj_next;
1779 /* check if we are pre-computing */
1782 /* update remaining length */
1784 temp->len -= average;
1788 /* fill out current TD */
1794 /* update remaining length */
1796 temp->len -= average;
1798 /* reset TRB index */
1802 if (temp->trb_type == XHCI_TRB_TYPE_SETUP_STAGE) {
1803 /* immediate data */
1808 td->td_trb[0].qwTrb0 = 0;
1810 usbd_copy_out(temp->pc, temp->offset + buf_offset,
1811 (uint8_t *)(uintptr_t)&td->td_trb[0].qwTrb0,
1814 dword = XHCI_TRB_2_BYTES_SET(8) |
1815 XHCI_TRB_2_TDSZ_SET(0) |
1816 XHCI_TRB_2_IRQ_SET(0);
1818 td->td_trb[0].dwTrb2 = htole32(dword);
1820 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) |
1821 XHCI_TRB_3_IDT_BIT | XHCI_TRB_3_CYCLE_BIT;
1824 if (td->td_trb[0].qwTrb0 &
1825 htole64(XHCI_TRB_0_WLENGTH_MASK)) {
1826 if (td->td_trb[0].qwTrb0 &
1827 htole64(XHCI_TRB_0_DIR_IN_MASK))
1828 dword |= XHCI_TRB_3_TRT_IN;
1830 dword |= XHCI_TRB_3_TRT_OUT;
1833 td->td_trb[0].dwTrb3 = htole32(dword);
1835 xhci_dump_trb(&td->td_trb[x]);
1842 /* fill out buffer pointers */
1845 memset(&buf_res, 0, sizeof(buf_res));
1847 usbd_get_page(temp->pc, temp->offset +
1848 buf_offset, &buf_res);
1850 /* get length to end of page */
1851 if (buf_res.length > average)
1852 buf_res.length = average;
1854 /* check for maximum length */
1855 if (buf_res.length > XHCI_TD_PAGE_SIZE)
1856 buf_res.length = XHCI_TD_PAGE_SIZE;
1858 npkt_off += buf_res.length;
1862 npkt = howmany(len_old - npkt_off,
1863 temp->max_packet_size);
1870 /* fill out TRB's */
1871 td->td_trb[x].qwTrb0 =
1872 htole64((uint64_t)buf_res.physaddr);
1875 XHCI_TRB_2_BYTES_SET(buf_res.length) |
1876 XHCI_TRB_2_TDSZ_SET(npkt) |
1877 XHCI_TRB_2_IRQ_SET(0);
1879 td->td_trb[x].dwTrb2 = htole32(dword);
1881 switch (temp->trb_type) {
1882 case XHCI_TRB_TYPE_ISOCH:
1883 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1884 XHCI_TRB_3_TBC_SET(temp->tbc) |
1885 XHCI_TRB_3_TLBPC_SET(temp->tlbpc);
1886 if (td != td_first) {
1887 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL);
1888 } else if (temp->do_isoc_sync != 0) {
1889 temp->do_isoc_sync = 0;
1890 /* wait until "isoc_frame" */
1891 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) |
1892 XHCI_TRB_3_FRID_SET(temp->isoc_frame / 8);
1894 /* start data transfer at next interval */
1895 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) |
1896 XHCI_TRB_3_ISO_SIA_BIT;
1898 if (temp->direction == UE_DIR_IN)
1899 dword |= XHCI_TRB_3_ISP_BIT;
1901 case XHCI_TRB_TYPE_DATA_STAGE:
1902 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1903 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE);
1904 if (temp->direction == UE_DIR_IN)
1905 dword |= XHCI_TRB_3_DIR_IN | XHCI_TRB_3_ISP_BIT;
1907 * Section 3.2.9 in the XHCI
1908 * specification about control
1909 * transfers says that we should use a
1910 * normal-TRB if there are more TRBs
1911 * extending the data-stage
1912 * TRB. Update the "trb_type".
1914 temp->trb_type = XHCI_TRB_TYPE_NORMAL;
1916 case XHCI_TRB_TYPE_STATUS_STAGE:
1917 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1918 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE);
1919 if (temp->direction == UE_DIR_IN)
1920 dword |= XHCI_TRB_3_DIR_IN;
1922 default: /* XHCI_TRB_TYPE_NORMAL */
1923 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1924 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL);
1925 if (temp->direction == UE_DIR_IN)
1926 dword |= XHCI_TRB_3_ISP_BIT;
1929 td->td_trb[x].dwTrb3 = htole32(dword);
1931 average -= buf_res.length;
1932 buf_offset += buf_res.length;
1934 xhci_dump_trb(&td->td_trb[x]);
1938 } while (average != 0);
1940 td->td_trb[x-1].dwTrb3 |= htole32(XHCI_TRB_3_IOC_BIT);
1942 /* store number of data TRB's */
1946 DPRINTF("NTRB=%u\n", x);
1948 /* fill out link TRB */
1950 if (td_next != NULL) {
1951 /* link the current TD with the next one */
1952 td->td_trb[x].qwTrb0 = htole64((uint64_t)td_next->td_self);
1953 DPRINTF("LINK=0x%08llx\n", (long long)td_next->td_self);
1955 /* this field will get updated later */
1956 DPRINTF("NOLINK\n");
1959 dword = XHCI_TRB_2_IRQ_SET(0);
1961 td->td_trb[x].dwTrb2 = htole32(dword);
1963 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) |
1964 XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_IOC_BIT |
1966 * CHAIN-BIT: Ensure that a multi-TRB IN-endpoint
1967 * frame only receives a single short packet event
1968 * by setting the CHAIN bit in the LINK field. In
1969 * addition some XHCI controllers have problems
1970 * sending a ZLP unless the CHAIN-BIT is set in
1973 XHCI_TRB_3_CHAIN_BIT;
1975 td->td_trb[x].dwTrb3 = htole32(dword);
1977 td->alt_next = td_alt_next;
1979 xhci_dump_trb(&td->td_trb[x]);
1981 usb_pc_cpu_flush(td->page_cache);
1987 /* set up alt next pointer, if any */
1988 if (temp->last_frame) {
1991 /* we use this field internally */
1992 td_alt_next = td_next;
1996 temp->shortpkt = shortpkt_old;
1997 temp->len = len_old;
2002 * Remove cycle bit from the first TRB if we are
2005 if (temp->step_td != 0) {
2006 td_first->td_trb[0].dwTrb3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT);
2007 usb_pc_cpu_flush(td_first->page_cache);
2010 /* clear TD SIZE to zero, hence this is the last TRB */
2011 /* remove chain bit because this is the last data TRB in the chain */
2012 td->td_trb[td->ntrb - 1].dwTrb2 &= ~htole32(XHCI_TRB_2_TDSZ_SET(31));
2013 td->td_trb[td->ntrb - 1].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT);
2014 /* remove CHAIN-BIT from last LINK TRB */
2015 td->td_trb[td->ntrb].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT);
2017 usb_pc_cpu_flush(td->page_cache);
2020 temp->td_next = td_next;
2024 xhci_setup_generic_chain(struct usb_xfer *xfer)
2026 struct xhci_std_temp temp;
2032 temp.do_isoc_sync = 0;
2036 temp.average = xfer->max_hc_frame_size;
2037 temp.max_packet_size = xfer->max_packet_size;
2038 temp.sc = XHCI_BUS2SC(xfer->xroot->bus);
2040 temp.last_frame = 0;
2042 temp.multishort = xfer->flags_int.isochronous_xfr ||
2043 xfer->flags_int.control_xfr ||
2044 xfer->flags_int.short_frames_ok;
2046 /* toggle the DMA set we are using */
2047 xfer->flags_int.curr_dma_set ^= 1;
2049 /* get next DMA set */
2050 td = xfer->td_start[xfer->flags_int.curr_dma_set];
2055 xfer->td_transfer_first = td;
2056 xfer->td_transfer_cache = td;
2058 if (xfer->flags_int.isochronous_xfr) {
2061 /* compute multiplier for ISOCHRONOUS transfers */
2062 mult = xfer->endpoint->ecomp ?
2063 UE_GET_SS_ISO_MULT(xfer->endpoint->ecomp->bmAttributes)
2065 /* check for USB 2.0 multiplier */
2067 mult = (xfer->endpoint->edesc->
2068 wMaxPacketSize[1] >> 3) & 3;
2076 x = XREAD4(temp.sc, runt, XHCI_MFINDEX);
2078 DPRINTF("MFINDEX=0x%08x\n", x);
2080 switch (usbd_get_speed(xfer->xroot->udev)) {
2081 case USB_SPEED_FULL:
2083 temp.isoc_delta = 8; /* 1ms */
2084 x += temp.isoc_delta - 1;
2085 x &= ~(temp.isoc_delta - 1);
2088 shift = usbd_xfer_get_fps_shift(xfer);
2089 temp.isoc_delta = 1U << shift;
2090 x += temp.isoc_delta - 1;
2091 x &= ~(temp.isoc_delta - 1);
2092 /* simple frame load balancing */
2093 x += xfer->endpoint->usb_uframe;
2097 y = XHCI_MFINDEX_GET(x - xfer->endpoint->isoc_next);
2099 if ((xfer->endpoint->is_synced == 0) ||
2100 (y < (xfer->nframes << shift)) ||
2101 (XHCI_MFINDEX_GET(-y) >= (128 * 8))) {
2103 * If there is data underflow or the pipe
2104 * queue is empty we schedule the transfer a
2105 * few frames ahead of the current frame
2106 * position. Else two isochronous transfers
2109 xfer->endpoint->isoc_next = XHCI_MFINDEX_GET(x + (3 * 8));
2110 xfer->endpoint->is_synced = 1;
2111 temp.do_isoc_sync = 1;
2113 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
2116 /* compute isochronous completion time */
2118 y = XHCI_MFINDEX_GET(xfer->endpoint->isoc_next - (x & ~7));
2120 xfer->isoc_time_complete =
2121 usb_isoc_time_expand(&temp.sc->sc_bus, x / 8) +
2122 (y / 8) + (((xfer->nframes << shift) + 7) / 8);
2125 temp.isoc_frame = xfer->endpoint->isoc_next;
2126 temp.trb_type = XHCI_TRB_TYPE_ISOCH;
2128 xfer->endpoint->isoc_next += xfer->nframes << shift;
2130 } else if (xfer->flags_int.control_xfr) {
2131 /* check if we should prepend a setup message */
2133 if (xfer->flags_int.control_hdr) {
2134 temp.len = xfer->frlengths[0];
2135 temp.pc = xfer->frbuffers + 0;
2136 temp.shortpkt = temp.len ? 1 : 0;
2137 temp.trb_type = XHCI_TRB_TYPE_SETUP_STAGE;
2140 /* check for last frame */
2141 if (xfer->nframes == 1) {
2142 /* no STATUS stage yet, SETUP is last */
2143 if (xfer->flags_int.control_act)
2144 temp.last_frame = 1;
2147 xhci_setup_generic_chain_sub(&temp);
2151 temp.isoc_delta = 0;
2152 temp.isoc_frame = 0;
2153 temp.trb_type = xfer->flags_int.control_did_data ?
2154 XHCI_TRB_TYPE_NORMAL : XHCI_TRB_TYPE_DATA_STAGE;
2158 temp.isoc_delta = 0;
2159 temp.isoc_frame = 0;
2160 temp.trb_type = XHCI_TRB_TYPE_NORMAL;
2163 if (x != xfer->nframes) {
2164 /* set up page_cache pointer */
2165 temp.pc = xfer->frbuffers + x;
2166 /* set endpoint direction */
2167 temp.direction = UE_GET_DIR(xfer->endpointno);
2170 while (x != xfer->nframes) {
2171 /* DATA0 / DATA1 message */
2173 temp.len = xfer->frlengths[x];
2174 temp.step_td = ((xfer->endpointno & UE_DIR_IN) &&
2175 x != 0 && temp.multishort == 0);
2179 if (x == xfer->nframes) {
2180 if (xfer->flags_int.control_xfr) {
2181 /* no STATUS stage yet, DATA is last */
2182 if (xfer->flags_int.control_act)
2183 temp.last_frame = 1;
2185 temp.last_frame = 1;
2188 if (temp.len == 0) {
2189 /* make sure that we send an USB packet */
2194 temp.tlbpc = mult - 1;
2196 } else if (xfer->flags_int.isochronous_xfr) {
2200 * Isochronous transfers don't have short
2201 * packet termination:
2206 /* isochronous transfers have a transfer limit */
2208 if (temp.len > xfer->max_frame_size)
2209 temp.len = xfer->max_frame_size;
2211 /* compute TD packet count */
2212 tdpc = howmany(temp.len, xfer->max_packet_size);
2214 temp.tbc = howmany(tdpc, mult) - 1;
2215 temp.tlbpc = (tdpc % mult);
2217 if (temp.tlbpc == 0)
2218 temp.tlbpc = mult - 1;
2222 /* regular data transfer */
2224 temp.shortpkt = xfer->flags.force_short_xfer ? 0 : 1;
2227 xhci_setup_generic_chain_sub(&temp);
2229 if (xfer->flags_int.isochronous_xfr) {
2230 temp.offset += xfer->frlengths[x - 1];
2231 temp.isoc_frame += temp.isoc_delta;
2233 /* get next Page Cache pointer */
2234 temp.pc = xfer->frbuffers + x;
2238 /* check if we should append a status stage */
2240 if (xfer->flags_int.control_xfr &&
2241 !xfer->flags_int.control_act) {
2243 * Send a DATA1 message and invert the current
2244 * endpoint direction.
2246 if (xhcictlstep || temp.sc->sc_ctlstep) {
2248 * Some XHCI controllers will not delay the
2249 * status stage until the next SOF. Force this
2250 * behaviour to avoid failed control
2253 temp.step_td = (xfer->nframes != 0);
2257 temp.direction = UE_GET_DIR(xfer->endpointno) ^ UE_DIR_IN;
2261 temp.last_frame = 1;
2262 temp.trb_type = XHCI_TRB_TYPE_STATUS_STAGE;
2264 xhci_setup_generic_chain_sub(&temp);
2269 /* must have at least one frame! */
2271 xfer->td_transfer_last = td;
2273 DPRINTF("first=%p last=%p\n", xfer->td_transfer_first, td);
2277 xhci_set_slot_pointer(struct xhci_softc *sc, uint8_t index, uint64_t dev_addr)
2279 struct usb_page_search buf_res;
2280 struct xhci_dev_ctx_addr *pdctxa;
2282 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res);
2284 pdctxa = buf_res.buffer;
2286 DPRINTF("addr[%u]=0x%016llx\n", index, (long long)dev_addr);
2288 pdctxa->qwBaaDevCtxAddr[index] = htole64(dev_addr);
2290 usb_pc_cpu_flush(&sc->sc_hw.ctx_pc);
2294 xhci_configure_mask(struct usb_device *udev, uint32_t mask, uint8_t drop)
2296 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2297 struct usb_page_search buf_inp;
2298 struct xhci_input_dev_ctx *pinp;
2303 index = udev->controller_slot_id;
2305 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
2307 pinp = buf_inp.buffer;
2310 mask &= XHCI_INCTX_NON_CTRL_MASK;
2311 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, mask);
2312 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, 0);
2315 * Some hardware requires that we drop the endpoint
2316 * context before adding it again:
2318 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0,
2319 mask & XHCI_INCTX_NON_CTRL_MASK);
2321 /* Add new endpoint context */
2322 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, mask);
2324 /* find most significant set bit */
2325 for (x = 31; x != 1; x--) {
2326 if (mask & (1 << x))
2333 /* figure out the maximum number of contexts */
2334 if (x > sc->sc_hw.devs[index].context_num)
2335 sc->sc_hw.devs[index].context_num = x;
2337 x = sc->sc_hw.devs[index].context_num;
2339 /* update number of contexts */
2340 temp = xhci_ctx_get_le32(sc, &pinp->ctx_slot.dwSctx0);
2341 temp &= ~XHCI_SCTX_0_CTX_NUM_SET(31);
2342 temp |= XHCI_SCTX_0_CTX_NUM_SET(x + 1);
2343 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp);
2345 usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc);
2350 xhci_configure_endpoint(struct usb_device *udev,
2351 struct usb_endpoint_descriptor *edesc, struct xhci_endpoint_ext *pepext,
2352 uint16_t interval, uint8_t max_packet_count,
2353 uint8_t mult, uint8_t fps_shift, uint16_t max_packet_size,
2354 uint16_t max_frame_size, uint8_t ep_mode)
2356 struct usb_page_search buf_inp;
2357 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2358 struct xhci_input_dev_ctx *pinp;
2359 uint64_t ring_addr = pepext->physaddr;
2365 index = udev->controller_slot_id;
2367 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
2369 pinp = buf_inp.buffer;
2371 epno = edesc->bEndpointAddress;
2372 type = edesc->bmAttributes & UE_XFERTYPE;
2374 if (type == UE_CONTROL)
2377 epno = XHCI_EPNO2EPID(epno);
2380 return (USB_ERR_NO_PIPE); /* invalid */
2382 if (max_packet_count == 0)
2383 return (USB_ERR_BAD_BUFSIZE);
2388 return (USB_ERR_BAD_BUFSIZE);
2390 /* store endpoint mode */
2391 pepext->trb_ep_mode = ep_mode;
2392 /* store bMaxPacketSize for control endpoints */
2393 pepext->trb_ep_maxp = edesc->wMaxPacketSize[0];
2394 usb_pc_cpu_flush(pepext->page_cache);
2396 if (ep_mode == USB_EP_MODE_STREAMS) {
2397 temp = XHCI_EPCTX_0_EPSTATE_SET(0) |
2398 XHCI_EPCTX_0_MAXP_STREAMS_SET(XHCI_MAX_STREAMS_LOG - 1) |
2399 XHCI_EPCTX_0_LSA_SET(1);
2401 ring_addr += sizeof(struct xhci_trb) *
2402 XHCI_MAX_TRANSFERS * XHCI_MAX_STREAMS;
2404 temp = XHCI_EPCTX_0_EPSTATE_SET(0) |
2405 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) |
2406 XHCI_EPCTX_0_LSA_SET(0);
2408 ring_addr |= XHCI_EPCTX_2_DCS_SET(1);
2411 switch (udev->speed) {
2412 case USB_SPEED_FULL:
2425 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift);
2427 case UE_ISOCHRONOUS:
2428 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift);
2430 switch (udev->speed) {
2431 case USB_SPEED_SUPER:
2434 temp |= XHCI_EPCTX_0_MULT_SET(mult - 1);
2435 max_packet_count /= mult;
2445 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx0, temp);
2448 XHCI_EPCTX_1_HID_SET(0) |
2449 XHCI_EPCTX_1_MAXB_SET(max_packet_count) |
2450 XHCI_EPCTX_1_MAXP_SIZE_SET(max_packet_size);
2453 * Always enable the "three strikes and you are gone" feature
2454 * except for ISOCHRONOUS endpoints. This is suggested by
2455 * section 4.3.3 in the XHCI specification about device slot
2458 if (type != UE_ISOCHRONOUS)
2459 temp |= XHCI_EPCTX_1_CERR_SET(3);
2463 temp |= XHCI_EPCTX_1_EPTYPE_SET(4);
2465 case UE_ISOCHRONOUS:
2466 temp |= XHCI_EPCTX_1_EPTYPE_SET(1);
2469 temp |= XHCI_EPCTX_1_EPTYPE_SET(2);
2472 temp |= XHCI_EPCTX_1_EPTYPE_SET(3);
2476 /* check for IN direction */
2478 temp |= XHCI_EPCTX_1_EPTYPE_SET(4);
2480 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx1, temp);
2481 xhci_ctx_set_le64(sc, &pinp->ctx_ep[epno - 1].qwEpCtx2, ring_addr);
2483 switch (edesc->bmAttributes & UE_XFERTYPE) {
2485 case UE_ISOCHRONOUS:
2486 temp = XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(max_frame_size) |
2487 XHCI_EPCTX_4_AVG_TRB_LEN_SET(MIN(XHCI_PAGE_SIZE,
2491 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8);
2494 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(XHCI_PAGE_SIZE);
2498 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx4, temp);
2501 xhci_dump_endpoint(sc, &pinp->ctx_ep[epno - 1]);
2503 usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc);
2505 return (0); /* success */
2509 xhci_configure_endpoint_by_xfer(struct usb_xfer *xfer)
2511 struct xhci_endpoint_ext *pepext;
2512 struct usb_endpoint_ss_comp_descriptor *ecomp;
2515 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2516 xfer->endpoint->edesc);
2518 ecomp = xfer->endpoint->ecomp;
2520 for (x = 0; x != XHCI_MAX_STREAMS; x++) {
2523 /* halt any transfers */
2524 pepext->trb[x * XHCI_MAX_TRANSFERS].dwTrb3 = 0;
2526 /* compute start of TRB ring for stream "x" */
2527 temp = pepext->physaddr +
2528 (x * XHCI_MAX_TRANSFERS * sizeof(struct xhci_trb)) +
2529 XHCI_SCTX_0_SCT_SEC_TR_RING;
2531 /* make tree structure */
2532 pepext->trb[(XHCI_MAX_TRANSFERS *
2533 XHCI_MAX_STREAMS) + x].qwTrb0 = htole64(temp);
2535 /* reserved fields */
2536 pepext->trb[(XHCI_MAX_TRANSFERS *
2537 XHCI_MAX_STREAMS) + x].dwTrb2 = 0;
2538 pepext->trb[(XHCI_MAX_TRANSFERS *
2539 XHCI_MAX_STREAMS) + x].dwTrb3 = 0;
2541 usb_pc_cpu_flush(pepext->page_cache);
2543 return (xhci_configure_endpoint(xfer->xroot->udev,
2544 xfer->endpoint->edesc, pepext,
2545 xfer->interval, xfer->max_packet_count,
2546 (ecomp != NULL) ? UE_GET_SS_ISO_MULT(ecomp->bmAttributes) + 1 : 1,
2547 usbd_xfer_get_fps_shift(xfer), xfer->max_packet_size,
2548 xfer->max_frame_size, xfer->endpoint->ep_mode));
2552 xhci_configure_device(struct usb_device *udev)
2554 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2555 struct usb_page_search buf_inp;
2556 struct usb_page_cache *pcinp;
2557 struct xhci_input_dev_ctx *pinp;
2558 struct usb_device *hubdev;
2566 index = udev->controller_slot_id;
2568 DPRINTF("index=%u\n", index);
2570 pcinp = &sc->sc_hw.devs[index].input_pc;
2572 usbd_get_page(pcinp, 0, &buf_inp);
2574 pinp = buf_inp.buffer;
2579 /* figure out route string and root HUB port number */
2581 for (hubdev = udev; hubdev != NULL; hubdev = hubdev->parent_hub) {
2582 if (hubdev->parent_hub == NULL)
2585 depth = hubdev->parent_hub->depth;
2588 * NOTE: HS/FS/LS devices and the SS root HUB can have
2589 * more than 15 ports
2592 rh_port = hubdev->port_no;
2601 route |= rh_port << (4 * (depth - 1));
2604 DPRINTF("Route=0x%08x\n", route);
2606 temp = XHCI_SCTX_0_ROUTE_SET(route) |
2607 XHCI_SCTX_0_CTX_NUM_SET(
2608 sc->sc_hw.devs[index].context_num + 1);
2610 switch (udev->speed) {
2612 temp |= XHCI_SCTX_0_SPEED_SET(2);
2613 if (udev->parent_hs_hub != NULL &&
2614 udev->parent_hs_hub->ddesc.bDeviceProtocol ==
2616 DPRINTF("Device inherits MTT\n");
2617 temp |= XHCI_SCTX_0_MTT_SET(1);
2620 case USB_SPEED_HIGH:
2621 temp |= XHCI_SCTX_0_SPEED_SET(3);
2622 if (sc->sc_hw.devs[index].nports != 0 &&
2623 udev->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT) {
2624 DPRINTF("HUB supports MTT\n");
2625 temp |= XHCI_SCTX_0_MTT_SET(1);
2628 case USB_SPEED_FULL:
2629 temp |= XHCI_SCTX_0_SPEED_SET(1);
2630 if (udev->parent_hs_hub != NULL &&
2631 udev->parent_hs_hub->ddesc.bDeviceProtocol ==
2633 DPRINTF("Device inherits MTT\n");
2634 temp |= XHCI_SCTX_0_MTT_SET(1);
2638 temp |= XHCI_SCTX_0_SPEED_SET(4);
2642 is_hub = sc->sc_hw.devs[index].nports != 0 &&
2643 (udev->speed == USB_SPEED_SUPER ||
2644 udev->speed == USB_SPEED_HIGH);
2647 temp |= XHCI_SCTX_0_HUB_SET(1);
2649 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp);
2651 temp = XHCI_SCTX_1_RH_PORT_SET(rh_port);
2654 temp |= XHCI_SCTX_1_NUM_PORTS_SET(
2655 sc->sc_hw.devs[index].nports);
2658 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx1, temp);
2660 temp = XHCI_SCTX_2_IRQ_TARGET_SET(0);
2663 temp |= XHCI_SCTX_2_TT_THINK_TIME_SET(
2664 sc->sc_hw.devs[index].tt);
2667 hubdev = udev->parent_hs_hub;
2669 /* check if we should activate the transaction translator */
2670 switch (udev->speed) {
2671 case USB_SPEED_FULL:
2673 if (hubdev != NULL) {
2674 temp |= XHCI_SCTX_2_TT_HUB_SID_SET(
2675 hubdev->controller_slot_id);
2676 temp |= XHCI_SCTX_2_TT_PORT_NUM_SET(
2684 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx2, temp);
2687 * These fields should be initialized to zero, according to
2688 * XHCI section 6.2.2 - slot context:
2690 temp = XHCI_SCTX_3_DEV_ADDR_SET(0) |
2691 XHCI_SCTX_3_SLOT_STATE_SET(0);
2693 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx3, temp);
2696 xhci_dump_device(sc, &pinp->ctx_slot);
2698 usb_pc_cpu_flush(pcinp);
2700 return (0); /* success */
2704 xhci_alloc_device_ext(struct usb_device *udev)
2706 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2707 struct usb_page_search buf_dev;
2708 struct usb_page_search buf_ep;
2709 struct xhci_trb *trb;
2710 struct usb_page_cache *pc;
2711 struct usb_page *pg;
2716 index = udev->controller_slot_id;
2718 pc = &sc->sc_hw.devs[index].device_pc;
2719 pg = &sc->sc_hw.devs[index].device_pg;
2721 /* need to initialize the page cache */
2722 pc->tag_parent = sc->sc_bus.dma_parent_tag;
2724 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ?
2725 (2 * sizeof(struct xhci_dev_ctx)) :
2726 sizeof(struct xhci_dev_ctx), XHCI_PAGE_SIZE))
2729 usbd_get_page(pc, 0, &buf_dev);
2731 pc = &sc->sc_hw.devs[index].input_pc;
2732 pg = &sc->sc_hw.devs[index].input_pg;
2734 /* need to initialize the page cache */
2735 pc->tag_parent = sc->sc_bus.dma_parent_tag;
2737 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ?
2738 (2 * sizeof(struct xhci_input_dev_ctx)) :
2739 sizeof(struct xhci_input_dev_ctx), XHCI_PAGE_SIZE)) {
2743 /* initialize all endpoint LINK TRBs */
2745 for (i = 0; i != XHCI_MAX_ENDPOINTS; i++) {
2746 pc = &sc->sc_hw.devs[index].endpoint_pc[i];
2747 pg = &sc->sc_hw.devs[index].endpoint_pg[i];
2749 /* need to initialize the page cache */
2750 pc->tag_parent = sc->sc_bus.dma_parent_tag;
2752 if (usb_pc_alloc_mem(pc, pg,
2753 sizeof(struct xhci_dev_endpoint_trbs), XHCI_TRB_ALIGN)) {
2757 /* lookup endpoint TRB ring */
2758 usbd_get_page(pc, 0, &buf_ep);
2760 /* get TRB pointer */
2761 trb = buf_ep.buffer;
2762 trb += XHCI_MAX_TRANSFERS - 1;
2764 /* get TRB start address */
2765 addr = buf_ep.physaddr;
2767 /* create LINK TRB */
2768 trb->qwTrb0 = htole64(addr);
2769 trb->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2770 trb->dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT |
2771 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2773 usb_pc_cpu_flush(pc);
2776 xhci_set_slot_pointer(sc, index, buf_dev.physaddr);
2781 xhci_free_device_ext(udev);
2783 return (USB_ERR_NOMEM);
2787 xhci_free_device_ext(struct usb_device *udev)
2789 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2793 index = udev->controller_slot_id;
2794 xhci_set_slot_pointer(sc, index, 0);
2796 usb_pc_free_mem(&sc->sc_hw.devs[index].device_pc);
2797 usb_pc_free_mem(&sc->sc_hw.devs[index].input_pc);
2798 for (i = 0; i != XHCI_MAX_ENDPOINTS; i++)
2799 usb_pc_free_mem(&sc->sc_hw.devs[index].endpoint_pc[i]);
2802 static struct xhci_endpoint_ext *
2803 xhci_get_endpoint_ext(struct usb_device *udev, struct usb_endpoint_descriptor *edesc)
2805 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2806 struct xhci_endpoint_ext *pepext;
2807 struct usb_page_cache *pc;
2808 struct usb_page_search buf_ep;
2812 epno = edesc->bEndpointAddress;
2813 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL)
2816 epno = XHCI_EPNO2EPID(epno);
2818 index = udev->controller_slot_id;
2820 pc = &sc->sc_hw.devs[index].endpoint_pc[epno];
2822 usbd_get_page(pc, 0, &buf_ep);
2824 pepext = &sc->sc_hw.devs[index].endp[epno];
2825 pepext->page_cache = pc;
2826 pepext->trb = buf_ep.buffer;
2827 pepext->physaddr = buf_ep.physaddr;
2833 xhci_endpoint_doorbell(struct usb_xfer *xfer)
2835 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
2839 epno = xfer->endpointno;
2840 if (xfer->flags_int.control_xfr)
2843 epno = XHCI_EPNO2EPID(epno);
2844 index = xfer->xroot->udev->controller_slot_id;
2846 if (xfer->xroot->udev->flags.self_suspended == 0) {
2847 XWRITE4(sc, door, XHCI_DOORBELL(index),
2848 epno | XHCI_DB_SID_SET(xfer->stream_id));
2853 xhci_transfer_remove(struct usb_xfer *xfer, usb_error_t error)
2855 struct xhci_endpoint_ext *pepext;
2857 if (xfer->flags_int.bandwidth_reclaimed) {
2858 xfer->flags_int.bandwidth_reclaimed = 0;
2860 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2861 xfer->endpoint->edesc);
2863 pepext->trb_used[xfer->stream_id]--;
2865 pepext->xfer[xfer->qh_pos] = NULL;
2867 if (error && pepext->trb_running != 0) {
2868 pepext->trb_halted = 1;
2869 pepext->trb_running = 0;
2875 xhci_transfer_insert(struct usb_xfer *xfer)
2877 struct xhci_td *td_first;
2878 struct xhci_td *td_last;
2879 struct xhci_trb *trb_link;
2880 struct xhci_endpoint_ext *pepext;
2889 id = xfer->stream_id;
2891 /* check if already inserted */
2892 if (xfer->flags_int.bandwidth_reclaimed) {
2893 DPRINTFN(8, "Already in schedule\n");
2897 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2898 xfer->endpoint->edesc);
2900 td_first = xfer->td_transfer_first;
2901 td_last = xfer->td_transfer_last;
2902 addr = pepext->physaddr;
2904 switch (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) {
2907 /* single buffered */
2911 /* multi buffered */
2912 trb_limit = (XHCI_MAX_TRANSFERS - 2);
2916 if (pepext->trb_used[id] >= trb_limit) {
2917 DPRINTFN(8, "Too many TDs queued.\n");
2918 return (USB_ERR_NOMEM);
2921 /* check if bMaxPacketSize changed */
2922 if (xfer->flags_int.control_xfr != 0 &&
2923 pepext->trb_ep_maxp != xfer->endpoint->edesc->wMaxPacketSize[0]) {
2924 DPRINTFN(8, "Reconfigure control endpoint\n");
2926 /* force driver to reconfigure endpoint */
2927 pepext->trb_halted = 1;
2928 pepext->trb_running = 0;
2931 /* check for stopped condition, after putting transfer on interrupt queue */
2932 if (pepext->trb_running == 0) {
2933 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
2935 DPRINTFN(8, "Not running\n");
2937 /* start configuration */
2938 (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus),
2939 &sc->sc_config_msg[0], &sc->sc_config_msg[1]);
2943 pepext->trb_used[id]++;
2945 /* get current TRB index */
2946 i = pepext->trb_index[id];
2948 /* get next TRB index */
2951 /* the last entry of the ring is a hardcoded link TRB */
2952 if (inext >= (XHCI_MAX_TRANSFERS - 1))
2955 /* store next TRB index, before stream ID offset is added */
2956 pepext->trb_index[id] = inext;
2958 /* offset for stream */
2959 i += id * XHCI_MAX_TRANSFERS;
2960 inext += id * XHCI_MAX_TRANSFERS;
2962 /* compute terminating return address */
2963 addr += (inext * sizeof(struct xhci_trb));
2965 /* compute link TRB pointer */
2966 trb_link = td_last->td_trb + td_last->ntrb;
2968 /* update next pointer of last link TRB */
2969 trb_link->qwTrb0 = htole64(addr);
2970 trb_link->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2971 trb_link->dwTrb3 = htole32(XHCI_TRB_3_IOC_BIT |
2972 XHCI_TRB_3_CYCLE_BIT |
2973 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2976 xhci_dump_trb(&td_last->td_trb[td_last->ntrb]);
2978 usb_pc_cpu_flush(td_last->page_cache);
2980 /* write ahead chain end marker */
2982 pepext->trb[inext].qwTrb0 = 0;
2983 pepext->trb[inext].dwTrb2 = 0;
2984 pepext->trb[inext].dwTrb3 = 0;
2986 /* update next pointer of link TRB */
2988 pepext->trb[i].qwTrb0 = htole64((uint64_t)td_first->td_self);
2989 pepext->trb[i].dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2992 xhci_dump_trb(&pepext->trb[i]);
2994 usb_pc_cpu_flush(pepext->page_cache);
2996 /* toggle cycle bit which activates the transfer chain */
2998 pepext->trb[i].dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT |
2999 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
3001 usb_pc_cpu_flush(pepext->page_cache);
3003 DPRINTF("qh_pos = %u\n", i);
3005 pepext->xfer[i] = xfer;
3009 xfer->flags_int.bandwidth_reclaimed = 1;
3011 xhci_endpoint_doorbell(xfer);
3017 xhci_root_intr(struct xhci_softc *sc)
3021 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
3023 /* clear any old interrupt data */
3024 memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata));
3026 for (i = 1; i <= sc->sc_noport; i++) {
3027 /* pick out CHANGE bits from the status register */
3028 if (XREAD4(sc, oper, XHCI_PORTSC(i)) & (
3029 XHCI_PS_CSC | XHCI_PS_PEC |
3030 XHCI_PS_OCC | XHCI_PS_WRC |
3031 XHCI_PS_PRC | XHCI_PS_PLC |
3033 sc->sc_hub_idata[i / 8] |= 1 << (i % 8);
3034 DPRINTF("port %d changed\n", i);
3037 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
3038 sizeof(sc->sc_hub_idata));
3041 /*------------------------------------------------------------------------*
3042 * xhci_device_done - XHCI done handler
3044 * NOTE: This function can be called two times in a row on
3045 * the same USB transfer. From close and from interrupt.
3046 *------------------------------------------------------------------------*/
3048 xhci_device_done(struct usb_xfer *xfer, usb_error_t error)
3050 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n",
3051 xfer, xfer->endpoint, error);
3053 /* remove transfer from HW queue */
3054 xhci_transfer_remove(xfer, error);
3056 /* dequeue transfer and start next transfer */
3057 usbd_transfer_done(xfer, error);
3060 /*------------------------------------------------------------------------*
3061 * XHCI data transfer support (generic type)
3062 *------------------------------------------------------------------------*/
3064 xhci_device_generic_open(struct usb_xfer *xfer)
3066 if (xfer->flags_int.isochronous_xfr) {
3067 switch (xfer->xroot->udev->speed) {
3068 case USB_SPEED_FULL:
3071 usb_hs_bandwidth_alloc(xfer);
3078 xhci_device_generic_close(struct usb_xfer *xfer)
3082 xhci_device_done(xfer, USB_ERR_CANCELLED);
3084 if (xfer->flags_int.isochronous_xfr) {
3085 switch (xfer->xroot->udev->speed) {
3086 case USB_SPEED_FULL:
3089 usb_hs_bandwidth_free(xfer);
3096 xhci_device_generic_multi_enter(struct usb_endpoint *ep,
3097 usb_stream_t stream_id, struct usb_xfer *enter_xfer)
3099 struct usb_xfer *xfer;
3101 /* check if there is a current transfer */
3102 xfer = ep->endpoint_q[stream_id].curr;
3107 * Check if the current transfer is started and then pickup
3108 * the next one, if any. Else wait for next start event due to
3109 * block on failure feature.
3111 if (!xfer->flags_int.bandwidth_reclaimed)
3114 xfer = TAILQ_FIRST(&ep->endpoint_q[stream_id].head);
3117 * In case of enter we have to consider that the
3118 * transfer is queued by the USB core after the enter
3127 /* try to multi buffer */
3128 xhci_transfer_insert(xfer);
3132 xhci_device_generic_enter(struct usb_xfer *xfer)
3136 /* set up TD's and QH */
3137 xhci_setup_generic_chain(xfer);
3139 xhci_device_generic_multi_enter(xfer->endpoint,
3140 xfer->stream_id, xfer);
3144 xhci_device_generic_start(struct usb_xfer *xfer)
3148 /* try to insert xfer on HW queue */
3149 xhci_transfer_insert(xfer);
3151 /* try to multi buffer */
3152 xhci_device_generic_multi_enter(xfer->endpoint,
3153 xfer->stream_id, NULL);
3155 /* add transfer last on interrupt queue */
3156 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
3158 /* start timeout, if any */
3159 if (xfer->timeout != 0)
3160 usbd_transfer_timeout_ms(xfer, &xhci_timeout, xfer->timeout);
3163 static const struct usb_pipe_methods xhci_device_generic_methods =
3165 .open = xhci_device_generic_open,
3166 .close = xhci_device_generic_close,
3167 .enter = xhci_device_generic_enter,
3168 .start = xhci_device_generic_start,
3171 /*------------------------------------------------------------------------*
3172 * xhci root HUB support
3173 *------------------------------------------------------------------------*
3174 * Simulate a hardware HUB by handling all the necessary requests.
3175 *------------------------------------------------------------------------*/
3176 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) }
3179 struct usb_device_descriptor xhci_devd =
3181 .bLength = sizeof(xhci_devd),
3182 .bDescriptorType = UDESC_DEVICE, /* type */
3183 HSETW(.bcdUSB, 0x0300), /* USB version */
3184 .bDeviceClass = UDCLASS_HUB, /* class */
3185 .bDeviceSubClass = UDSUBCLASS_HUB, /* subclass */
3186 .bDeviceProtocol = UDPROTO_SSHUB, /* protocol */
3187 .bMaxPacketSize = 9, /* max packet size */
3188 HSETW(.idVendor, 0x0000), /* vendor */
3189 HSETW(.idProduct, 0x0000), /* product */
3190 HSETW(.bcdDevice, 0x0100), /* device version */
3194 .bNumConfigurations = 1, /* # of configurations */
3198 struct xhci_bos_desc xhci_bosd = {
3200 .bLength = sizeof(xhci_bosd.bosd),
3201 .bDescriptorType = UDESC_BOS,
3202 HSETW(.wTotalLength, sizeof(xhci_bosd)),
3203 .bNumDeviceCaps = 3,
3206 .bLength = sizeof(xhci_bosd.usb2extd),
3207 .bDescriptorType = 1,
3208 .bDevCapabilityType = 2,
3209 .bmAttributes[0] = 2,
3212 .bLength = sizeof(xhci_bosd.usbdcd),
3213 .bDescriptorType = UDESC_DEVICE_CAPABILITY,
3214 .bDevCapabilityType = 3,
3215 .bmAttributes = 0, /* XXX */
3216 HSETW(.wSpeedsSupported, 0x000C),
3217 .bFunctionalitySupport = 8,
3218 .bU1DevExitLat = 255, /* dummy - not used */
3219 .wU2DevExitLat = { 0x00, 0x08 },
3222 .bLength = sizeof(xhci_bosd.cidd),
3223 .bDescriptorType = 1,
3224 .bDevCapabilityType = 4,
3226 .bContainerID = 0, /* XXX */
3231 struct xhci_config_desc xhci_confd = {
3233 .bLength = sizeof(xhci_confd.confd),
3234 .bDescriptorType = UDESC_CONFIG,
3235 .wTotalLength[0] = sizeof(xhci_confd),
3237 .bConfigurationValue = 1,
3238 .iConfiguration = 0,
3239 .bmAttributes = UC_SELF_POWERED,
3240 .bMaxPower = 0 /* max power */
3243 .bLength = sizeof(xhci_confd.ifcd),
3244 .bDescriptorType = UDESC_INTERFACE,
3246 .bInterfaceClass = UICLASS_HUB,
3247 .bInterfaceSubClass = UISUBCLASS_HUB,
3248 .bInterfaceProtocol = 0,
3251 .bLength = sizeof(xhci_confd.endpd),
3252 .bDescriptorType = UDESC_ENDPOINT,
3253 .bEndpointAddress = UE_DIR_IN | XHCI_INTR_ENDPT,
3254 .bmAttributes = UE_INTERRUPT,
3255 .wMaxPacketSize[0] = 2, /* max 15 ports */
3259 .bLength = sizeof(xhci_confd.endpcd),
3260 .bDescriptorType = UDESC_ENDPOINT_SS_COMP,
3267 struct usb_hub_ss_descriptor xhci_hubd = {
3268 .bLength = sizeof(xhci_hubd),
3269 .bDescriptorType = UDESC_SS_HUB,
3273 xhci_roothub_exec(struct usb_device *udev,
3274 struct usb_device_request *req, const void **pptr, uint16_t *plength)
3276 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3277 const char *str_ptr;
3288 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
3291 ptr = (const void *)&sc->sc_hub_desc;
3295 value = UGETW(req->wValue);
3296 index = UGETW(req->wIndex);
3298 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x "
3299 "wValue=0x%04x wIndex=0x%04x\n",
3300 req->bmRequestType, req->bRequest,
3301 UGETW(req->wLength), value, index);
3303 #define C(x,y) ((x) | ((y) << 8))
3304 switch (C(req->bRequest, req->bmRequestType)) {
3305 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE):
3306 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE):
3307 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT):
3309 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops
3310 * for the integrated root hub.
3313 case C(UR_GET_CONFIG, UT_READ_DEVICE):
3315 sc->sc_hub_desc.temp[0] = sc->sc_conf;
3317 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
3318 switch (value >> 8) {
3320 if ((value & 0xff) != 0) {
3321 err = USB_ERR_IOERROR;
3324 len = sizeof(xhci_devd);
3325 ptr = (const void *)&xhci_devd;
3329 if ((value & 0xff) != 0) {
3330 err = USB_ERR_IOERROR;
3333 len = sizeof(xhci_bosd);
3334 ptr = (const void *)&xhci_bosd;
3338 if ((value & 0xff) != 0) {
3339 err = USB_ERR_IOERROR;
3342 len = sizeof(xhci_confd);
3343 ptr = (const void *)&xhci_confd;
3347 switch (value & 0xff) {
3348 case 0: /* Language table */
3352 case 1: /* Vendor */
3353 str_ptr = sc->sc_vendor;
3356 case 2: /* Product */
3357 str_ptr = "XHCI root HUB";
3365 len = usb_make_str_desc(
3366 sc->sc_hub_desc.temp,
3367 sizeof(sc->sc_hub_desc.temp),
3372 err = USB_ERR_IOERROR;
3376 case C(UR_GET_INTERFACE, UT_READ_INTERFACE):
3378 sc->sc_hub_desc.temp[0] = 0;
3380 case C(UR_GET_STATUS, UT_READ_DEVICE):
3382 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED);
3384 case C(UR_GET_STATUS, UT_READ_INTERFACE):
3385 case C(UR_GET_STATUS, UT_READ_ENDPOINT):
3387 USETW(sc->sc_hub_desc.stat.wStatus, 0);
3389 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE):
3390 if (value >= XHCI_MAX_DEVICES) {
3391 err = USB_ERR_IOERROR;
3395 case C(UR_SET_CONFIG, UT_WRITE_DEVICE):
3396 if (value != 0 && value != 1) {
3397 err = USB_ERR_IOERROR;
3400 sc->sc_conf = value;
3402 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE):
3404 case C(UR_SET_FEATURE, UT_WRITE_DEVICE):
3405 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE):
3406 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT):
3407 err = USB_ERR_IOERROR;
3409 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE):
3411 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT):
3414 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
3416 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
3417 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n");
3420 (index > sc->sc_noport)) {
3421 err = USB_ERR_IOERROR;
3424 port = XHCI_PORTSC(index);
3426 v = XREAD4(sc, oper, port);
3427 i = XHCI_PS_PLS_GET(v);
3428 v &= ~XHCI_PS_CLEAR;
3431 case UHF_C_BH_PORT_RESET:
3432 XWRITE4(sc, oper, port, v | XHCI_PS_WRC);
3434 case UHF_C_PORT_CONFIG_ERROR:
3435 XWRITE4(sc, oper, port, v | XHCI_PS_CEC);
3437 case UHF_C_PORT_SUSPEND:
3438 case UHF_C_PORT_LINK_STATE:
3439 XWRITE4(sc, oper, port, v | XHCI_PS_PLC);
3441 case UHF_C_PORT_CONNECTION:
3442 XWRITE4(sc, oper, port, v | XHCI_PS_CSC);
3444 case UHF_C_PORT_ENABLE:
3445 XWRITE4(sc, oper, port, v | XHCI_PS_PEC);
3447 case UHF_C_PORT_OVER_CURRENT:
3448 XWRITE4(sc, oper, port, v | XHCI_PS_OCC);
3450 case UHF_C_PORT_RESET:
3451 XWRITE4(sc, oper, port, v | XHCI_PS_PRC);
3453 case UHF_PORT_ENABLE:
3454 XWRITE4(sc, oper, port, v | XHCI_PS_PED);
3456 case UHF_PORT_POWER:
3457 XWRITE4(sc, oper, port, v & ~XHCI_PS_PP);
3459 case UHF_PORT_INDICATOR:
3460 XWRITE4(sc, oper, port, v & ~XHCI_PS_PIC_SET(3));
3462 case UHF_PORT_SUSPEND:
3466 XWRITE4(sc, oper, port, v |
3467 XHCI_PS_PLS_SET(0xF) | XHCI_PS_LWS);
3470 /* wait 20ms for resume sequence to complete */
3471 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50);
3474 XWRITE4(sc, oper, port, v |
3475 XHCI_PS_PLS_SET(0) | XHCI_PS_LWS);
3478 err = USB_ERR_IOERROR;
3483 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
3484 if ((value & 0xff) != 0) {
3485 err = USB_ERR_IOERROR;
3489 v = XREAD4(sc, capa, XHCI_HCSPARAMS0);
3491 sc->sc_hub_desc.hubd = xhci_hubd;
3493 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport;
3495 if (XHCI_HCS0_PPC(v))
3496 i = UHD_PWR_INDIVIDUAL;
3500 if (XHCI_HCS0_PIND(v))
3503 i |= UHD_OC_INDIVIDUAL;
3505 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i);
3507 /* see XHCI section 5.4.9: */
3508 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 10;
3510 for (j = 1; j <= sc->sc_noport; j++) {
3511 v = XREAD4(sc, oper, XHCI_PORTSC(j));
3512 if (v & XHCI_PS_DR) {
3513 sc->sc_hub_desc.hubd.
3514 DeviceRemovable[j / 8] |= 1U << (j % 8);
3517 len = sc->sc_hub_desc.hubd.bLength;
3520 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
3522 memset(sc->sc_hub_desc.temp, 0, 16);
3525 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
3526 DPRINTFN(9, "UR_GET_STATUS i=%d\n", index);
3529 (index > sc->sc_noport)) {
3530 err = USB_ERR_IOERROR;
3534 v = XREAD4(sc, oper, XHCI_PORTSC(index));
3536 DPRINTFN(9, "port status=0x%08x\n", v);
3538 i = UPS_PORT_LINK_STATE_SET(XHCI_PS_PLS_GET(v));
3540 switch (XHCI_PS_SPEED_GET(v)) {
3542 i |= UPS_HIGH_SPEED;
3551 i |= UPS_OTHER_SPEED;
3555 if (v & XHCI_PS_CCS)
3556 i |= UPS_CURRENT_CONNECT_STATUS;
3557 if (v & XHCI_PS_PED)
3558 i |= UPS_PORT_ENABLED;
3559 if (v & XHCI_PS_OCA)
3560 i |= UPS_OVERCURRENT_INDICATOR;
3567 USETW(sc->sc_hub_desc.ps.wPortStatus, i);
3570 if (v & XHCI_PS_CSC)
3571 i |= UPS_C_CONNECT_STATUS;
3572 if (v & XHCI_PS_PEC)
3573 i |= UPS_C_PORT_ENABLED;
3574 if (v & XHCI_PS_OCC)
3575 i |= UPS_C_OVERCURRENT_INDICATOR;
3576 if (v & XHCI_PS_WRC)
3577 i |= UPS_C_BH_PORT_RESET;
3578 if (v & XHCI_PS_PRC)
3579 i |= UPS_C_PORT_RESET;
3580 if (v & XHCI_PS_PLC)
3581 i |= UPS_C_PORT_LINK_STATE;
3582 if (v & XHCI_PS_CEC)
3583 i |= UPS_C_PORT_CONFIG_ERROR;
3585 USETW(sc->sc_hub_desc.ps.wPortChange, i);
3586 len = sizeof(sc->sc_hub_desc.ps);
3589 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
3590 err = USB_ERR_IOERROR;
3593 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
3596 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
3602 (index > sc->sc_noport)) {
3603 err = USB_ERR_IOERROR;
3607 port = XHCI_PORTSC(index);
3608 v = XREAD4(sc, oper, port) & ~XHCI_PS_CLEAR;
3611 case UHF_PORT_U1_TIMEOUT:
3612 if (XHCI_PS_SPEED_GET(v) != 4) {
3613 err = USB_ERR_IOERROR;
3616 port = XHCI_PORTPMSC(index);
3617 v = XREAD4(sc, oper, port);
3618 v &= ~XHCI_PM3_U1TO_SET(0xFF);
3619 v |= XHCI_PM3_U1TO_SET(i);
3620 XWRITE4(sc, oper, port, v);
3622 case UHF_PORT_U2_TIMEOUT:
3623 if (XHCI_PS_SPEED_GET(v) != 4) {
3624 err = USB_ERR_IOERROR;
3627 port = XHCI_PORTPMSC(index);
3628 v = XREAD4(sc, oper, port);
3629 v &= ~XHCI_PM3_U2TO_SET(0xFF);
3630 v |= XHCI_PM3_U2TO_SET(i);
3631 XWRITE4(sc, oper, port, v);
3633 case UHF_BH_PORT_RESET:
3634 XWRITE4(sc, oper, port, v | XHCI_PS_WPR);
3636 case UHF_PORT_LINK_STATE:
3637 XWRITE4(sc, oper, port, v |
3638 XHCI_PS_PLS_SET(i) | XHCI_PS_LWS);
3639 /* 4ms settle time */
3640 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250);
3642 case UHF_PORT_ENABLE:
3643 DPRINTFN(3, "set port enable %d\n", index);
3645 case UHF_PORT_SUSPEND:
3646 DPRINTFN(6, "suspend port %u (LPM=%u)\n", index, i);
3647 j = XHCI_PS_SPEED_GET(v);
3648 if ((j < 1) || (j > 3)) {
3649 /* non-supported speed */
3650 err = USB_ERR_IOERROR;
3653 XWRITE4(sc, oper, port, v |
3654 XHCI_PS_PLS_SET(i ? 2 /* LPM */ : 3) | XHCI_PS_LWS);
3656 case UHF_PORT_RESET:
3657 DPRINTFN(6, "reset port %d\n", index);
3658 XWRITE4(sc, oper, port, v | XHCI_PS_PR);
3660 case UHF_PORT_POWER:
3661 DPRINTFN(3, "set port power %d\n", index);
3662 XWRITE4(sc, oper, port, v | XHCI_PS_PP);
3665 DPRINTFN(3, "set port test %d\n", index);
3667 case UHF_PORT_INDICATOR:
3668 DPRINTFN(3, "set port indicator %d\n", index);
3670 v &= ~XHCI_PS_PIC_SET(3);
3671 v |= XHCI_PS_PIC_SET(1);
3673 XWRITE4(sc, oper, port, v);
3676 err = USB_ERR_IOERROR;
3681 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER):
3682 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER):
3683 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER):
3684 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER):
3687 err = USB_ERR_IOERROR;
3697 xhci_xfer_setup(struct usb_setup_params *parm)
3699 struct usb_page_search page_info;
3700 struct usb_page_cache *pc;
3701 struct usb_xfer *xfer;
3706 xfer = parm->curr_xfer;
3709 * The proof for the "ntd" formula is illustrated like this:
3711 * +------------------------------------+
3715 * | | xxx | x | frm 0 |
3717 * | | xxx | xx | frm 1 |
3720 * +------------------------------------+
3722 * "xxx" means a completely full USB transfer descriptor
3724 * "x" and "xx" means a short USB packet
3726 * For the remainder of an USB transfer modulo
3727 * "max_data_length" we need two USB transfer descriptors.
3728 * One to transfer the remaining data and one to finalise with
3729 * a zero length packet in case the "force_short_xfer" flag is
3730 * set. We only need two USB transfer descriptors in the case
3731 * where the transfer length of the first one is a factor of
3732 * "max_frame_size". The rest of the needed USB transfer
3733 * descriptors is given by the buffer size divided by the
3734 * maximum data payload.
3736 parm->hc_max_packet_size = 0x400;
3737 parm->hc_max_packet_count = 16 * 3;
3738 parm->hc_max_frame_size = XHCI_TD_PAYLOAD_MAX;
3740 xfer->flags_int.bdma_enable = 1;
3742 usbd_transfer_setup_sub(parm);
3744 if (xfer->flags_int.isochronous_xfr) {
3745 ntd = ((1 * xfer->nframes)
3746 + (xfer->max_data_length / xfer->max_hc_frame_size));
3747 } else if (xfer->flags_int.control_xfr) {
3748 ntd = ((2 * xfer->nframes) + 1 /* STATUS */
3749 + (xfer->max_data_length / xfer->max_hc_frame_size));
3751 ntd = ((2 * xfer->nframes)
3752 + (xfer->max_data_length / xfer->max_hc_frame_size));
3761 * Allocate queue heads and transfer descriptors
3765 if (usbd_transfer_setup_sub_malloc(
3766 parm, &pc, sizeof(struct xhci_td),
3767 XHCI_TD_ALIGN, ntd)) {
3768 parm->err = USB_ERR_NOMEM;
3772 for (n = 0; n != ntd; n++) {
3775 usbd_get_page(pc + n, 0, &page_info);
3777 td = page_info.buffer;
3780 td->td_self = page_info.physaddr;
3781 td->obj_next = last_obj;
3782 td->page_cache = pc + n;
3786 usb_pc_cpu_flush(pc + n);
3789 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj;
3791 if (!xfer->flags_int.curr_dma_set) {
3792 xfer->flags_int.curr_dma_set = 1;
3798 xhci_get_endpoint_state(struct usb_device *udev, uint8_t epno)
3800 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3801 struct usb_page_search buf_dev;
3802 struct xhci_hw_dev *hdev;
3803 struct xhci_dev_ctx *pdev;
3808 hdev = &sc->sc_hw.devs[udev->controller_slot_id];
3810 usbd_get_page(&hdev->device_pc, 0, &buf_dev);
3811 pdev = buf_dev.buffer;
3812 usb_pc_cpu_invalidate(&hdev->device_pc);
3814 temp = xhci_ctx_get_le32(sc, &pdev->ctx_ep[epno - 1].dwEpCtx0);
3816 return (XHCI_EPCTX_0_EPSTATE_GET(temp));
3820 xhci_configure_reset_endpoint(struct usb_xfer *xfer)
3822 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
3823 struct usb_page_search buf_inp;
3824 struct usb_device *udev;
3825 struct xhci_endpoint_ext *pepext;
3826 struct usb_endpoint_descriptor *edesc;
3827 struct usb_page_cache *pcinp;
3829 usb_stream_t stream_id;
3834 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
3835 xfer->endpoint->edesc);
3837 udev = xfer->xroot->udev;
3838 index = udev->controller_slot_id;
3840 pcinp = &sc->sc_hw.devs[index].input_pc;
3842 usbd_get_page(pcinp, 0, &buf_inp);
3844 edesc = xfer->endpoint->edesc;
3846 epno = edesc->bEndpointAddress;
3847 stream_id = xfer->stream_id;
3849 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL)
3852 epno = XHCI_EPNO2EPID(epno);
3855 return (USB_ERR_NO_PIPE); /* invalid */
3859 /* configure endpoint */
3861 err = xhci_configure_endpoint_by_xfer(xfer);
3864 XHCI_CMD_UNLOCK(sc);
3869 * Get the endpoint into the stopped state according to the
3870 * endpoint context state diagram in the XHCI specification:
3872 switch (xhci_get_endpoint_state(udev, epno)) {
3873 case XHCI_EPCTX_0_EPSTATE_STOPPED:
3875 case XHCI_EPCTX_0_EPSTATE_HALTED:
3876 err = xhci_cmd_reset_ep(sc, 0, epno, index);
3878 DPRINTF("Could not reset endpoint %u\n", epno);
3881 err = xhci_cmd_stop_ep(sc, 0, epno, index);
3883 DPRINTF("Could not stop endpoint %u\n", epno);
3887 err = xhci_cmd_set_tr_dequeue_ptr(sc,
3888 (pepext->physaddr + (stream_id * sizeof(struct xhci_trb) *
3889 XHCI_MAX_TRANSFERS)) | XHCI_EPCTX_2_DCS_SET(1),
3890 stream_id, epno, index);
3893 DPRINTF("Could not set dequeue ptr for endpoint %u\n", epno);
3896 * Get the endpoint into the running state according to the
3897 * endpoint context state diagram in the XHCI specification:
3900 mask = (1U << epno);
3901 xhci_configure_mask(udev, mask | 1U, 0);
3903 if (!(sc->sc_hw.devs[index].ep_configured & mask)) {
3904 sc->sc_hw.devs[index].ep_configured |= mask;
3905 err = xhci_cmd_configure_ep(sc, buf_inp.physaddr, 0, index);
3907 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index);
3911 DPRINTF("Could not configure "
3912 "endpoint %u at slot %u.\n", epno, index);
3914 XHCI_CMD_UNLOCK(sc);
3920 xhci_xfer_unsetup(struct usb_xfer *xfer)
3926 xhci_start_dma_delay(struct usb_xfer *xfer)
3928 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
3930 /* put transfer on interrupt queue (again) */
3931 usbd_transfer_enqueue(&sc->sc_bus.intr_q, xfer);
3933 (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus),
3934 &sc->sc_config_msg[0], &sc->sc_config_msg[1]);
3938 xhci_configure_msg(struct usb_proc_msg *pm)
3940 struct xhci_softc *sc;
3941 struct xhci_endpoint_ext *pepext;
3942 struct usb_xfer *xfer;
3944 sc = XHCI_BUS2SC(((struct usb_bus_msg *)pm)->bus);
3947 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3948 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
3949 xfer->endpoint->edesc);
3951 if ((pepext->trb_halted != 0) ||
3952 (pepext->trb_running == 0)) {
3955 /* clear halted and running */
3956 pepext->trb_halted = 0;
3957 pepext->trb_running = 0;
3959 /* nuke remaining buffered transfers */
3961 for (i = 0; i != (XHCI_MAX_TRANSFERS *
3962 XHCI_MAX_STREAMS); i++) {
3964 * NOTE: We need to use the timeout
3965 * error code here else existing
3966 * isochronous clients can get
3969 if (pepext->xfer[i] != NULL) {
3970 xhci_device_done(pepext->xfer[i],
3976 * NOTE: The USB transfer cannot vanish in
3980 USB_BUS_UNLOCK(&sc->sc_bus);
3982 xhci_configure_reset_endpoint(xfer);
3984 USB_BUS_LOCK(&sc->sc_bus);
3986 /* check if halted is still cleared */
3987 if (pepext->trb_halted == 0) {
3988 pepext->trb_running = 1;
3989 memset(pepext->trb_index, 0,
3990 sizeof(pepext->trb_index));
3995 if (xfer->flags_int.did_dma_delay) {
3996 /* remove transfer from interrupt queue (again) */
3997 usbd_transfer_dequeue(xfer);
3999 /* we are finally done */
4000 usb_dma_delay_done_cb(xfer);
4002 /* queue changed - restart */
4007 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
4008 /* try to insert xfer on HW queue */
4009 xhci_transfer_insert(xfer);
4011 /* try to multi buffer */
4012 xhci_device_generic_multi_enter(xfer->endpoint,
4013 xfer->stream_id, NULL);
4018 xhci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
4019 struct usb_endpoint *ep)
4021 struct xhci_endpoint_ext *pepext;
4022 struct xhci_softc *sc;
4026 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d\n",
4027 ep, udev->address, edesc->bEndpointAddress, udev->flags.usb_mode);
4029 if (udev->parent_hub == NULL) {
4030 /* root HUB has special endpoint handling */
4034 ep->methods = &xhci_device_generic_methods;
4036 pepext = xhci_get_endpoint_ext(udev, edesc);
4038 USB_BUS_LOCK(udev->bus);
4039 pepext->trb_halted = 1;
4040 pepext->trb_running = 0;
4043 * When doing an alternate setting, except for control
4044 * endpoints, we need to re-configure the XHCI endpoint
4047 if ((edesc->bEndpointAddress & UE_ADDR) != 0) {
4048 sc = XHCI_BUS2SC(udev->bus);
4049 index = udev->controller_slot_id;
4050 epno = XHCI_EPNO2EPID(edesc->bEndpointAddress);
4051 sc->sc_hw.devs[index].ep_configured &= ~(1U << epno);
4053 USB_BUS_UNLOCK(udev->bus);
4057 xhci_ep_uninit(struct usb_device *udev, struct usb_endpoint *ep)
4063 xhci_ep_clear_stall(struct usb_device *udev, struct usb_endpoint *ep)
4065 struct xhci_endpoint_ext *pepext;
4069 if (udev->flags.usb_mode != USB_MODE_HOST) {
4073 if (udev->parent_hub == NULL) {
4074 /* root HUB has special endpoint handling */
4078 pepext = xhci_get_endpoint_ext(udev, ep->edesc);
4080 USB_BUS_LOCK(udev->bus);
4081 pepext->trb_halted = 1;
4082 pepext->trb_running = 0;
4083 USB_BUS_UNLOCK(udev->bus);
4087 xhci_device_init(struct usb_device *udev)
4089 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4093 /* no init for root HUB */
4094 if (udev->parent_hub == NULL)
4099 /* set invalid default */
4101 udev->controller_slot_id = sc->sc_noslot + 1;
4103 /* try to get a new slot ID from the XHCI */
4105 err = xhci_cmd_enable_slot(sc, &temp);
4108 XHCI_CMD_UNLOCK(sc);
4112 if (temp > sc->sc_noslot) {
4113 XHCI_CMD_UNLOCK(sc);
4114 return (USB_ERR_BAD_ADDRESS);
4117 if (sc->sc_hw.devs[temp].state != XHCI_ST_DISABLED) {
4118 DPRINTF("slot %u already allocated.\n", temp);
4119 XHCI_CMD_UNLOCK(sc);
4120 return (USB_ERR_BAD_ADDRESS);
4123 /* store slot ID for later reference */
4125 udev->controller_slot_id = temp;
4127 /* reset data structure */
4129 memset(&sc->sc_hw.devs[temp], 0, sizeof(sc->sc_hw.devs[0]));
4131 /* set mark slot allocated */
4133 sc->sc_hw.devs[temp].state = XHCI_ST_ENABLED;
4135 err = xhci_alloc_device_ext(udev);
4137 XHCI_CMD_UNLOCK(sc);
4139 /* get device into default state */
4142 err = xhci_set_address(udev, NULL, 0);
4148 xhci_device_uninit(struct usb_device *udev)
4150 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4153 /* no init for root HUB */
4154 if (udev->parent_hub == NULL)
4159 index = udev->controller_slot_id;
4161 if (index <= sc->sc_noslot) {
4162 xhci_cmd_disable_slot(sc, index);
4163 sc->sc_hw.devs[index].state = XHCI_ST_DISABLED;
4165 /* free device extension */
4166 xhci_free_device_ext(udev);
4169 XHCI_CMD_UNLOCK(sc);
4173 xhci_get_dma_delay(struct usb_device *udev, uint32_t *pus)
4176 * Wait until the hardware has finished any possible use of
4177 * the transfer descriptor(s)
4179 *pus = 2048; /* microseconds */
4183 xhci_device_resume(struct usb_device *udev)
4185 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4192 /* check for root HUB */
4193 if (udev->parent_hub == NULL)
4196 index = udev->controller_slot_id;
4200 /* blindly resume all endpoints */
4202 USB_BUS_LOCK(udev->bus);
4204 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) {
4205 for (p = 0; p != XHCI_MAX_STREAMS; p++) {
4206 XWRITE4(sc, door, XHCI_DOORBELL(index),
4207 n | XHCI_DB_SID_SET(p));
4211 USB_BUS_UNLOCK(udev->bus);
4213 XHCI_CMD_UNLOCK(sc);
4217 xhci_device_suspend(struct usb_device *udev)
4219 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4226 /* check for root HUB */
4227 if (udev->parent_hub == NULL)
4230 index = udev->controller_slot_id;
4234 /* blindly suspend all endpoints */
4236 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) {
4237 err = xhci_cmd_stop_ep(sc, 1, n, index);
4239 DPRINTF("Failed to suspend endpoint "
4240 "%u on slot %u (ignored).\n", n, index);
4244 XHCI_CMD_UNLOCK(sc);
4248 xhci_set_hw_power(struct usb_bus *bus)
4254 xhci_device_state_change(struct usb_device *udev)
4256 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4257 struct usb_page_search buf_inp;
4261 /* check for root HUB */
4262 if (udev->parent_hub == NULL)
4265 index = udev->controller_slot_id;
4269 if (usb_get_device_state(udev) == USB_STATE_CONFIGURED) {
4270 err = uhub_query_info(udev, &sc->sc_hw.devs[index].nports,
4271 &sc->sc_hw.devs[index].tt);
4273 sc->sc_hw.devs[index].nports = 0;
4278 switch (usb_get_device_state(udev)) {
4279 case USB_STATE_POWERED:
4280 if (sc->sc_hw.devs[index].state == XHCI_ST_DEFAULT)
4283 /* set default state */
4284 sc->sc_hw.devs[index].state = XHCI_ST_DEFAULT;
4285 sc->sc_hw.devs[index].ep_configured = 3U;
4287 /* reset number of contexts */
4288 sc->sc_hw.devs[index].context_num = 0;
4290 err = xhci_cmd_reset_dev(sc, index);
4293 DPRINTF("Device reset failed "
4294 "for slot %u.\n", index);
4298 case USB_STATE_ADDRESSED:
4299 if (sc->sc_hw.devs[index].state == XHCI_ST_ADDRESSED)
4302 sc->sc_hw.devs[index].state = XHCI_ST_ADDRESSED;
4303 sc->sc_hw.devs[index].ep_configured = 3U;
4305 /* set configure mask to slot only */
4306 xhci_configure_mask(udev, 1, 0);
4308 /* deconfigure all endpoints, except EP0 */
4309 err = xhci_cmd_configure_ep(sc, 0, 1, index);
4312 DPRINTF("Failed to deconfigure "
4313 "slot %u.\n", index);
4317 case USB_STATE_CONFIGURED:
4318 if (sc->sc_hw.devs[index].state == XHCI_ST_CONFIGURED) {
4319 /* deconfigure all endpoints, except EP0 */
4320 err = xhci_cmd_configure_ep(sc, 0, 1, index);
4323 DPRINTF("Failed to deconfigure "
4324 "slot %u.\n", index);
4328 /* set configured state */
4329 sc->sc_hw.devs[index].state = XHCI_ST_CONFIGURED;
4330 sc->sc_hw.devs[index].ep_configured = 3U;
4332 /* reset number of contexts */
4333 sc->sc_hw.devs[index].context_num = 0;
4335 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
4337 xhci_configure_mask(udev, 3, 0);
4339 err = xhci_configure_device(udev);
4341 DPRINTF("Could not configure device "
4342 "at slot %u.\n", index);
4345 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index);
4347 DPRINTF("Could not evaluate device "
4348 "context at slot %u.\n", index);
4355 XHCI_CMD_UNLOCK(sc);
4359 xhci_set_endpoint_mode(struct usb_device *udev, struct usb_endpoint *ep,
4363 case USB_EP_MODE_DEFAULT:
4365 case USB_EP_MODE_STREAMS:
4366 if (xhcistreams == 0 ||
4367 (ep->edesc->bmAttributes & UE_XFERTYPE) != UE_BULK ||
4368 udev->speed != USB_SPEED_SUPER)
4369 return (USB_ERR_INVAL);
4372 return (USB_ERR_INVAL);
4376 static const struct usb_bus_methods xhci_bus_methods = {
4377 .endpoint_init = xhci_ep_init,
4378 .endpoint_uninit = xhci_ep_uninit,
4379 .xfer_setup = xhci_xfer_setup,
4380 .xfer_unsetup = xhci_xfer_unsetup,
4381 .get_dma_delay = xhci_get_dma_delay,
4382 .device_init = xhci_device_init,
4383 .device_uninit = xhci_device_uninit,
4384 .device_resume = xhci_device_resume,
4385 .device_suspend = xhci_device_suspend,
4386 .set_hw_power = xhci_set_hw_power,
4387 .roothub_exec = xhci_roothub_exec,
4388 .xfer_poll = xhci_do_poll,
4389 .start_dma_delay = xhci_start_dma_delay,
4390 .set_address = xhci_set_address,
4391 .clear_stall = xhci_ep_clear_stall,
4392 .device_state_change = xhci_device_state_change,
4393 .set_hw_power_sleep = xhci_set_hw_power_sleep,
4394 .set_endpoint_mode = xhci_set_endpoint_mode,