sys/dev/usb/controller/xhci.c

   1 /* $FreeBSD$ */
   2 /*-
   3  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
   4  *
   5  * Copyright (c) 2010 Hans Petter Selasky. All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  26  * SUCH DAMAGE.
  27  */
  28
  29 /*
  30  * USB eXtensible Host Controller Interface, a.k.a. USB 3.0 controller.
  31  *
  32  * The XHCI 1.0 spec can be found at
  33  * http://www.intel.com/technology/usb/download/xHCI_Specification_for_USB.pdf
  34  * and the USB 3.0 spec at
  35  * http://www.usb.org/developers/docs/usb_30_spec_060910.zip
  36  */
  37
  38 /*
  39  * A few words about the design implementation: This driver emulates
  40  * the concept about TDs which is found in EHCI specification. This
  41  * way we achieve that the USB controller drivers look similar to
  42  * eachother which makes it easier to understand the code.
  43  */
  44
  45 #ifdef USB_GLOBAL_INCLUDE_FILE
  46 #include USB_GLOBAL_INCLUDE_FILE
  47 #else
  48 #include <sys/stdint.h>
  49 #include <sys/stddef.h>
  50 #include <sys/param.h>
  51 #include <sys/queue.h>
  52 #include <sys/types.h>
  53 #include <sys/systm.h>
  54 #include <sys/kernel.h>
  55 #include <sys/bus.h>
  56 #include <sys/module.h>
  57 #include <sys/lock.h>
  58 #include <sys/mutex.h>
  59 #include <sys/condvar.h>
  60 #include <sys/sysctl.h>
  61 #include <sys/sx.h>
  62 #include <sys/unistd.h>
  63 #include <sys/callout.h>
  64 #include <sys/malloc.h>
  65 #include <sys/priv.h>
  66
  67 #include <dev/usb/usb.h>
  68 #include <dev/usb/usbdi.h>
  69
  70 #define USB_DEBUG_VAR xhcidebug
  71
  72 #include <dev/usb/usb_core.h>
  73 #include <dev/usb/usb_debug.h>
  74 #include <dev/usb/usb_busdma.h>
  75 #include <dev/usb/usb_process.h>
  76 #include <dev/usb/usb_transfer.h>
  77 #include <dev/usb/usb_device.h>
  78 #include <dev/usb/usb_hub.h>
  79 #include <dev/usb/usb_util.h>
  80
  81 #include <dev/usb/usb_controller.h>
  82 #include <dev/usb/usb_bus.h>
  83 #endif                  /* USB_GLOBAL_INCLUDE_FILE */
  84
  85 #include <dev/usb/controller/xhci.h>
  86 #include <dev/usb/controller/xhcireg.h>
  87
  88 #define XHCI_BUS2SC(bus) \
  89    ((struct xhci_softc *)(((uint8_t *)(bus)) - \
  90     ((uint8_t *)&(((struct xhci_softc *)0)->sc_bus))))
  91
  92 static SYSCTL_NODE(_hw_usb, OID_AUTO, xhci, CTLFLAG_RW, 0, "USB XHCI");
  93
  94 static int xhcistreams;
  95 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, streams, CTLFLAG_RWTUN,
  96     &xhcistreams, 0, "Set to enable streams mode support");
  97
  98 #ifdef USB_DEBUG
  99 static int xhcidebug;
 100 static int xhciroute;
 101 static int xhcipolling;
 102 static int xhcidma32;
 103 static int xhcictlstep;
 104
 105 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, debug, CTLFLAG_RWTUN,
 106     &xhcidebug, 0, "Debug level");
 107 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, xhci_port_route, CTLFLAG_RWTUN,
 108     &xhciroute, 0, "Routing bitmap for switching EHCI ports to the XHCI controller");
 109 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, use_polling, CTLFLAG_RWTUN,
 110     &xhcipolling, 0, "Set to enable software interrupt polling for the XHCI controller");
 111 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, dma32, CTLFLAG_RWTUN,
 112     &xhcidma32, 0, "Set to only use 32-bit DMA for the XHCI controller");
 113 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, ctlstep, CTLFLAG_RWTUN,
 114     &xhcictlstep, 0, "Set to enable control endpoint status stage stepping");
 115 #else
 116 #define xhciroute 0
 117 #define xhcidma32 0
 118 #define xhcictlstep 0
 119 #endif
 120
 121 #define XHCI_INTR_ENDPT 1
 122
 123 struct xhci_std_temp {
 124         struct xhci_softc       *sc;
 125         struct usb_page_cache   *pc;
 126         struct xhci_td          *td;
 127         struct xhci_td          *td_next;
 128         uint32_t                len;
 129         uint32_t                offset;
 130         uint32_t                max_packet_size;
 131         uint32_t                average;
 132         uint16_t                isoc_delta;
 133         uint16_t                isoc_frame;
 134         uint8_t                 shortpkt;
 135         uint8_t                 multishort;
 136         uint8_t                 last_frame;
 137         uint8_t                 trb_type;
 138         uint8_t                 direction;
 139         uint8_t                 tbc;
 140         uint8_t                 tlbpc;
 141         uint8_t                 step_td;
 142         uint8_t                 do_isoc_sync;
 143 };
 144
 145 static void     xhci_do_poll(struct usb_bus *);
 146 static void     xhci_device_done(struct usb_xfer *, usb_error_t);
 147 static void     xhci_root_intr(struct xhci_softc *);
 148 static void     xhci_free_device_ext(struct usb_device *);
 149 static struct xhci_endpoint_ext *xhci_get_endpoint_ext(struct usb_device *,
 150                     struct usb_endpoint_descriptor *);
 151 static usb_proc_callback_t xhci_configure_msg;
 152 static usb_error_t xhci_configure_device(struct usb_device *);
 153 static usb_error_t xhci_configure_endpoint(struct usb_device *,
 154                    struct usb_endpoint_descriptor *, struct xhci_endpoint_ext *,
 155                    uint16_t, uint8_t, uint8_t, uint8_t, uint16_t, uint16_t,
 156                    uint8_t);
 157 static usb_error_t xhci_configure_mask(struct usb_device *,
 158                     uint32_t, uint8_t);
 159 static usb_error_t xhci_cmd_evaluate_ctx(struct xhci_softc *,
 160                     uint64_t, uint8_t);
 161 static void xhci_endpoint_doorbell(struct usb_xfer *);
 162 static void xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val);
 163 static uint32_t xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr);
 164 static void xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val);
 165 #ifdef USB_DEBUG
 166 static uint64_t xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr);
 167 #endif
 168
 169 static const struct usb_bus_methods xhci_bus_methods;
 170
 171 #ifdef USB_DEBUG
 172 static void
 173 xhci_dump_trb(struct xhci_trb *trb)
 174 {
 175         DPRINTFN(5, "trb = %p\n", trb);
 176         DPRINTFN(5, "qwTrb0 = 0x%016llx\n", (long long)le64toh(trb->qwTrb0));
 177         DPRINTFN(5, "dwTrb2 = 0x%08x\n", le32toh(trb->dwTrb2));
 178         DPRINTFN(5, "dwTrb3 = 0x%08x\n", le32toh(trb->dwTrb3));
 179 }
 180
 181 static void
 182 xhci_dump_endpoint(struct xhci_softc *sc, struct xhci_endp_ctx *pep)
 183 {
 184         DPRINTFN(5, "pep = %p\n", pep);
 185         DPRINTFN(5, "dwEpCtx0=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx0));
 186         DPRINTFN(5, "dwEpCtx1=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx1));
 187         DPRINTFN(5, "qwEpCtx2=0x%016llx\n", (long long)xhci_ctx_get_le64(sc, &pep->qwEpCtx2));
 188         DPRINTFN(5, "dwEpCtx4=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx4));
 189         DPRINTFN(5, "dwEpCtx5=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx5));
 190         DPRINTFN(5, "dwEpCtx6=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx6));
 191         DPRINTFN(5, "dwEpCtx7=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx7));
 192 }
 193
 194 static void
 195 xhci_dump_device(struct xhci_softc *sc, struct xhci_slot_ctx *psl)
 196 {
 197         DPRINTFN(5, "psl = %p\n", psl);
 198         DPRINTFN(5, "dwSctx0=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx0));
 199         DPRINTFN(5, "dwSctx1=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx1));
 200         DPRINTFN(5, "dwSctx2=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx2));
 201         DPRINTFN(5, "dwSctx3=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx3));
 202 }
 203 #endif
 204
 205 uint8_t
 206 xhci_use_polling(void)
 207 {
 208 #ifdef USB_DEBUG
 209         return (xhcipolling != 0);
 210 #else
 211         return (0);
 212 #endif
 213 }
 214
 215 static void
 216 xhci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb)
 217 {
 218         struct xhci_softc *sc = XHCI_BUS2SC(bus);
 219         uint16_t i;
 220
 221         cb(bus, &sc->sc_hw.root_pc, &sc->sc_hw.root_pg,
 222            sizeof(struct xhci_hw_root), XHCI_PAGE_SIZE);
 223
 224         cb(bus, &sc->sc_hw.ctx_pc, &sc->sc_hw.ctx_pg,
 225            sizeof(struct xhci_dev_ctx_addr), XHCI_PAGE_SIZE);
 226
 227         for (i = 0; i != sc->sc_noscratch; i++) {
 228                 cb(bus, &sc->sc_hw.scratch_pc[i], &sc->sc_hw.scratch_pg[i],
 229                     XHCI_PAGE_SIZE, XHCI_PAGE_SIZE);
 230         }
 231 }
 232
 233 static void
 234 xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val)
 235 {
 236         if (sc->sc_ctx_is_64_byte) {
 237                 uint32_t offset;
 238                 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
 239                 /* all contexts are initially 32-bytes */
 240                 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
 241                 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset);
 242         }
 243         *ptr = htole32(val);
 244 }
 245
 246 static uint32_t
 247 xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr)
 248 {
 249         if (sc->sc_ctx_is_64_byte) {
 250                 uint32_t offset;
 251                 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
 252                 /* all contexts are initially 32-bytes */
 253                 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
 254                 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset);
 255         }
 256         return (le32toh(*ptr));
 257 }
 258
 259 static void
 260 xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val)
 261 {
 262         if (sc->sc_ctx_is_64_byte) {
 263                 uint32_t offset;
 264                 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
 265                 /* all contexts are initially 32-bytes */
 266                 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
 267                 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset);
 268         }
 269         *ptr = htole64(val);
 270 }
 271
 272 #ifdef USB_DEBUG
 273 static uint64_t
 274 xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr)
 275 {
 276         if (sc->sc_ctx_is_64_byte) {
 277                 uint32_t offset;
 278                 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
 279                 /* all contexts are initially 32-bytes */
 280                 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
 281                 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset);
 282         }
 283         return (le64toh(*ptr));
 284 }
 285 #endif
 286
 287 static int
 288 xhci_reset_command_queue_locked(struct xhci_softc *sc)
 289 {
 290         struct usb_page_search buf_res;
 291         struct xhci_hw_root *phwr;
 292         uint64_t addr;
 293         uint32_t temp;
 294
 295         DPRINTF("\n");
 296
 297         temp = XREAD4(sc, oper, XHCI_CRCR_LO);
 298         if (temp & XHCI_CRCR_LO_CRR) {
 299                 DPRINTF("Command ring running\n");
 300                 temp &= ~(XHCI_CRCR_LO_CS | XHCI_CRCR_LO_CA);
 301
 302                 /*
 303                  * Try to abort the last command as per section
 304                  * 4.6.1.2 "Aborting a Command" of the XHCI
 305                  * specification:
 306                  */
 307
 308                 /* stop and cancel */
 309                 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CS);
 310                 XWRITE4(sc, oper, XHCI_CRCR_HI, 0);
 311
 312                 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CA);
 313                 XWRITE4(sc, oper, XHCI_CRCR_HI, 0);
 314
 315                 /* wait 250ms */
 316                 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 4);
 317
 318                 /* check if command ring is still running */
 319                 temp = XREAD4(sc, oper, XHCI_CRCR_LO);
 320                 if (temp & XHCI_CRCR_LO_CRR) {
 321                         DPRINTF("Comand ring still running\n");
 322                         return (USB_ERR_IOERROR);
 323                 }
 324         }
 325
 326         /* reset command ring */
 327         sc->sc_command_ccs = 1;
 328         sc->sc_command_idx = 0;
 329
 330         usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
 331
 332         /* set up command ring control base address */
 333         addr = buf_res.physaddr;
 334         phwr = buf_res.buffer;
 335         addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0];
 336
 337         DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr);
 338
 339         memset(phwr->hwr_commands, 0, sizeof(phwr->hwr_commands));
 340         phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr);
 341
 342         usb_pc_cpu_flush(&sc->sc_hw.root_pc);
 343
 344         XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS);
 345         XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32));
 346
 347         return (0);
 348 }
 349
 350 usb_error_t
 351 xhci_start_controller(struct xhci_softc *sc)
 352 {
 353         struct usb_page_search buf_res;
 354         struct xhci_hw_root *phwr;
 355         struct xhci_dev_ctx_addr *pdctxa;
 356         usb_error_t err;
 357         uint64_t addr;
 358         uint32_t temp;
 359         uint16_t i;
 360
 361         DPRINTF("\n");
 362
 363         sc->sc_event_ccs = 1;
 364         sc->sc_event_idx = 0;
 365         sc->sc_command_ccs = 1;
 366         sc->sc_command_idx = 0;
 367
 368         err = xhci_reset_controller(sc);
 369         if (err)
 370                 return (err);
 371
 372         /* set up number of device slots */
 373         DPRINTF("CONFIG=0x%08x -> 0x%08x\n",
 374             XREAD4(sc, oper, XHCI_CONFIG), sc->sc_noslot);
 375
 376         XWRITE4(sc, oper, XHCI_CONFIG, sc->sc_noslot);
 377
 378         temp = XREAD4(sc, oper, XHCI_USBSTS);
 379
 380         /* clear interrupts */
 381         XWRITE4(sc, oper, XHCI_USBSTS, temp);
 382         /* disable all device notifications */
 383         XWRITE4(sc, oper, XHCI_DNCTRL, 0);
 384
 385         /* set up device context base address */
 386         usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res);
 387         pdctxa = buf_res.buffer;
 388         memset(pdctxa, 0, sizeof(*pdctxa));
 389
 390         addr = buf_res.physaddr;
 391         addr += (uintptr_t)&((struct xhci_dev_ctx_addr *)0)->qwSpBufPtr[0];
 392
 393         /* slot 0 points to the table of scratchpad pointers */
 394         pdctxa->qwBaaDevCtxAddr[0] = htole64(addr);
 395
 396         for (i = 0; i != sc->sc_noscratch; i++) {
 397                 struct usb_page_search buf_scp;
 398                 usbd_get_page(&sc->sc_hw.scratch_pc[i], 0, &buf_scp);
 399                 pdctxa->qwSpBufPtr[i] = htole64((uint64_t)buf_scp.physaddr);
 400         }
 401
 402         addr = buf_res.physaddr;
 403
 404         XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr);
 405         XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32));
 406         XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr);
 407         XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32));
 408
 409         /* set up event table size */
 410         DPRINTF("ERSTSZ=0x%08x -> 0x%08x\n",
 411             XREAD4(sc, runt, XHCI_ERSTSZ(0)), sc->sc_erst_max);
 412
 413         XWRITE4(sc, runt, XHCI_ERSTSZ(0), XHCI_ERSTS_SET(sc->sc_erst_max));
 414
 415         /* set up interrupt rate */
 416         XWRITE4(sc, runt, XHCI_IMOD(0), sc->sc_imod_default);
 417
 418         usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
 419
 420         phwr = buf_res.buffer;
 421         addr = buf_res.physaddr;
 422         addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[0];
 423
 424         /* reset hardware root structure */
 425         memset(phwr, 0, sizeof(*phwr));
 426
 427         phwr->hwr_ring_seg[0].qwEvrsTablePtr = htole64(addr);
 428         phwr->hwr_ring_seg[0].dwEvrsTableSize = htole32(XHCI_MAX_EVENTS);
 429
 430         DPRINTF("ERDP(0)=0x%016llx\n", (unsigned long long)addr);
 431
 432         XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr);
 433         XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32));
 434
 435         addr = buf_res.physaddr;
 436
 437         DPRINTF("ERSTBA(0)=0x%016llx\n", (unsigned long long)addr);
 438
 439         XWRITE4(sc, runt, XHCI_ERSTBA_LO(0), (uint32_t)addr);
 440         XWRITE4(sc, runt, XHCI_ERSTBA_HI(0), (uint32_t)(addr >> 32));
 441
 442         /* set up interrupter registers */
 443         temp = XREAD4(sc, runt, XHCI_IMAN(0));
 444         temp |= XHCI_IMAN_INTR_ENA;
 445         XWRITE4(sc, runt, XHCI_IMAN(0), temp);
 446
 447         /* set up command ring control base address */
 448         addr = buf_res.physaddr;
 449         addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0];
 450
 451         DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr);
 452
 453         XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS);
 454         XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32));
 455
 456         phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr);
 457
 458         usb_bus_mem_flush_all(&sc->sc_bus, &xhci_iterate_hw_softc);
 459
 460         /* Go! */
 461         XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_RS |
 462             XHCI_CMD_INTE | XHCI_CMD_HSEE);
 463
 464         for (i = 0; i != 100; i++) {
 465                 usb_pause_mtx(NULL, hz / 100);
 466                 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH;
 467                 if (!temp)
 468                         break;
 469         }
 470         if (temp) {
 471                 XWRITE4(sc, oper, XHCI_USBCMD, 0);
 472                 device_printf(sc->sc_bus.parent, "Run timeout.\n");
 473                 return (USB_ERR_IOERROR);
 474         }
 475
 476         /* catch any lost interrupts */
 477         xhci_do_poll(&sc->sc_bus);
 478
 479         if (sc->sc_port_route != NULL) {
 480                 /* Route all ports to the XHCI by default */
 481                 sc->sc_port_route(sc->sc_bus.parent,
 482                     ~xhciroute, xhciroute);
 483         }
 484         return (0);
 485 }
 486
 487 usb_error_t
 488 xhci_halt_controller(struct xhci_softc *sc)
 489 {
 490         uint32_t temp;
 491         uint16_t i;
 492
 493         DPRINTF("\n");
 494
 495         sc->sc_capa_off = 0;
 496         sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH);
 497         sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0xF;
 498         sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3;
 499
 500         /* Halt controller */
 501         XWRITE4(sc, oper, XHCI_USBCMD, 0);
 502
 503         for (i = 0; i != 100; i++) {
 504                 usb_pause_mtx(NULL, hz / 100);
 505                 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH;
 506                 if (temp)
 507                         break;
 508         }
 509
 510         if (!temp) {
 511                 device_printf(sc->sc_bus.parent, "Controller halt timeout.\n");
 512                 return (USB_ERR_IOERROR);
 513         }
 514         return (0);
 515 }
 516
 517 usb_error_t
 518 xhci_reset_controller(struct xhci_softc *sc)
 519 {
 520         uint32_t temp = 0;
 521         uint16_t i;
 522
 523         DPRINTF("\n");
 524
 525         /* Reset controller */
 526         XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_HCRST);
 527
 528         for (i = 0; i != 100; i++) {
 529                 usb_pause_mtx(NULL, hz / 100);
 530                 temp = (XREAD4(sc, oper, XHCI_USBCMD) & XHCI_CMD_HCRST) |
 531                     (XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_CNR);
 532                 if (!temp)
 533                         break;
 534         }
 535
 536         if (temp) {
 537                 device_printf(sc->sc_bus.parent, "Controller "
 538                     "reset timeout.\n");
 539                 return (USB_ERR_IOERROR);
 540         }
 541         return (0);
 542 }
 543
 544 usb_error_t
 545 xhci_init(struct xhci_softc *sc, device_t self, uint8_t dma32)
 546 {
 547         uint32_t temp;
 548
 549         DPRINTF("\n");
 550
 551         /* initialize some bus fields */
 552         sc->sc_bus.parent = self;
 553
 554         /* set the bus revision */
 555         sc->sc_bus.usbrev = USB_REV_3_0;
 556
 557         /* set up the bus struct */
 558         sc->sc_bus.methods = &xhci_bus_methods;
 559
 560         /* set up devices array */
 561         sc->sc_bus.devices = sc->sc_devices;
 562         sc->sc_bus.devices_max = XHCI_MAX_DEVICES;
 563
 564         /* set default cycle state in case of early interrupts */
 565         sc->sc_event_ccs = 1;
 566         sc->sc_command_ccs = 1;
 567
 568         /* set up bus space offsets */
 569         sc->sc_capa_off = 0;
 570         sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH);
 571         sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0x1F;
 572         sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3;
 573
 574         DPRINTF("CAPLENGTH=0x%x\n", sc->sc_oper_off);
 575         DPRINTF("RUNTIMEOFFSET=0x%x\n", sc->sc_runt_off);
 576         DPRINTF("DOOROFFSET=0x%x\n", sc->sc_door_off);
 577
 578         DPRINTF("xHCI version = 0x%04x\n", XREAD2(sc, capa, XHCI_HCIVERSION));
 579
 580         if (!(XREAD4(sc, oper, XHCI_PAGESIZE) & XHCI_PAGESIZE_4K)) {
 581                 device_printf(sc->sc_bus.parent, "Controller does "
 582                     "not support 4K page size.\n");
 583                 return (ENXIO);
 584         }
 585
 586         temp = XREAD4(sc, capa, XHCI_HCSPARAMS0);
 587
 588         DPRINTF("HCS0 = 0x%08x\n", temp);
 589
 590         /* set up context size */
 591         if (XHCI_HCS0_CSZ(temp)) {
 592                 sc->sc_ctx_is_64_byte = 1;
 593         } else {
 594                 sc->sc_ctx_is_64_byte = 0;
 595         }
 596
 597         /* get DMA bits */
 598         sc->sc_bus.dma_bits = (XHCI_HCS0_AC64(temp) &&
 599             xhcidma32 == 0 && dma32 == 0) ? 64 : 32;
 600
 601         device_printf(self, "%d bytes context size, %d-bit DMA\n",
 602             sc->sc_ctx_is_64_byte ? 64 : 32, (int)sc->sc_bus.dma_bits);
 603
 604         /* enable 64Kbyte control endpoint quirk */
 605         sc->sc_bus.control_ep_quirk = 1;
 606
 607         temp = XREAD4(sc, capa, XHCI_HCSPARAMS1);
 608
 609         /* get number of device slots */
 610         sc->sc_noport = XHCI_HCS1_N_PORTS(temp);
 611
 612         if (sc->sc_noport == 0) {
 613                 device_printf(sc->sc_bus.parent, "Invalid number "
 614                     "of ports: %u\n", sc->sc_noport);
 615                 return (ENXIO);
 616         }
 617
 618         sc->sc_noport = sc->sc_noport;
 619         sc->sc_noslot = XHCI_HCS1_DEVSLOT_MAX(temp);
 620
 621         DPRINTF("Max slots: %u\n", sc->sc_noslot);
 622
 623         if (sc->sc_noslot > XHCI_MAX_DEVICES)
 624                 sc->sc_noslot = XHCI_MAX_DEVICES;
 625
 626         temp = XREAD4(sc, capa, XHCI_HCSPARAMS2);
 627
 628         DPRINTF("HCS2=0x%08x\n", temp);
 629
 630         /* get number of scratchpads */
 631         sc->sc_noscratch = XHCI_HCS2_SPB_MAX(temp);
 632
 633         if (sc->sc_noscratch > XHCI_MAX_SCRATCHPADS) {
 634                 device_printf(sc->sc_bus.parent, "XHCI request "
 635                     "too many scratchpads\n");
 636                 return (ENOMEM);
 637         }
 638
 639         DPRINTF("Max scratch: %u\n", sc->sc_noscratch);
 640
 641         /* get event table size */
 642         sc->sc_erst_max = 1U << XHCI_HCS2_ERST_MAX(temp);
 643         if (sc->sc_erst_max > XHCI_MAX_RSEG)
 644                 sc->sc_erst_max = XHCI_MAX_RSEG;
 645
 646         temp = XREAD4(sc, capa, XHCI_HCSPARAMS3);
 647
 648         /* get maximum exit latency */
 649         sc->sc_exit_lat_max = XHCI_HCS3_U1_DEL(temp) +
 650             XHCI_HCS3_U2_DEL(temp) + 250 /* us */;
 651
 652         /* Check if we should use the default IMOD value. */
 653         if (sc->sc_imod_default == 0)
 654                 sc->sc_imod_default = XHCI_IMOD_DEFAULT;
 655
 656         /* get all DMA memory */
 657         if (usb_bus_mem_alloc_all(&sc->sc_bus,
 658             USB_GET_DMA_TAG(self), &xhci_iterate_hw_softc)) {
 659                 return (ENOMEM);
 660         }
 661
 662         /* set up command queue mutex and condition varible */
 663         cv_init(&sc->sc_cmd_cv, "CMDQ");
 664         sx_init(&sc->sc_cmd_sx, "CMDQ lock");
 665
 666         sc->sc_config_msg[0].hdr.pm_callback = &xhci_configure_msg;
 667         sc->sc_config_msg[0].bus = &sc->sc_bus;
 668         sc->sc_config_msg[1].hdr.pm_callback = &xhci_configure_msg;
 669         sc->sc_config_msg[1].bus = &sc->sc_bus;
 670
 671         return (0);
 672 }
 673
 674 void
 675 xhci_uninit(struct xhci_softc *sc)
 676 {
 677         /*
 678          * NOTE: At this point the control transfer process is gone
 679          * and "xhci_configure_msg" is no longer called. Consequently
 680          * waiting for the configuration messages to complete is not
 681          * needed.
 682          */
 683         usb_bus_mem_free_all(&sc->sc_bus, &xhci_iterate_hw_softc);
 684
 685         cv_destroy(&sc->sc_cmd_cv);
 686         sx_destroy(&sc->sc_cmd_sx);
 687 }
 688
 689 static void
 690 xhci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
 691 {
 692         struct xhci_softc *sc = XHCI_BUS2SC(bus);
 693
 694         switch (state) {
 695         case USB_HW_POWER_SUSPEND:
 696                 DPRINTF("Stopping the XHCI\n");
 697                 xhci_halt_controller(sc);
 698                 xhci_reset_controller(sc);
 699                 break;
 700         case USB_HW_POWER_SHUTDOWN:
 701                 DPRINTF("Stopping the XHCI\n");
 702                 xhci_halt_controller(sc);
 703                 xhci_reset_controller(sc);
 704                 break;
 705         case USB_HW_POWER_RESUME:
 706                 DPRINTF("Starting the XHCI\n");
 707                 xhci_start_controller(sc);
 708                 break;
 709         default:
 710                 break;
 711         }
 712 }
 713
 714 static usb_error_t
 715 xhci_generic_done_sub(struct usb_xfer *xfer)
 716 {
 717         struct xhci_td *td;
 718         struct xhci_td *td_alt_next;
 719         uint32_t len;
 720         uint8_t status;
 721
 722         td = xfer->td_transfer_cache;
 723         td_alt_next = td->alt_next;
 724
 725         if (xfer->aframes != xfer->nframes)
 726                 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0);
 727
 728         while (1) {
 729
 730                 usb_pc_cpu_invalidate(td->page_cache);
 731
 732                 status = td->status;
 733                 len = td->remainder;
 734
 735                 DPRINTFN(4, "xfer=%p[%u/%u] rem=%u/%u status=%u\n",
 736                     xfer, (unsigned int)xfer->aframes,
 737                     (unsigned int)xfer->nframes,
 738                     (unsigned int)len, (unsigned int)td->len,
 739                     (unsigned int)status);
 740
 741                 /*
 742                  * Verify the status length and
 743                  * add the length to "frlengths[]":
 744                  */
 745                 if (len > td->len) {
 746                         /* should not happen */
 747                         DPRINTF("Invalid status length, "
 748                             "0x%04x/0x%04x bytes\n", len, td->len);
 749                         status = XHCI_TRB_ERROR_LENGTH;
 750                 } else if (xfer->aframes != xfer->nframes) {
 751                         xfer->frlengths[xfer->aframes] += td->len - len;
 752                 }
 753                 /* Check for last transfer */
 754                 if (((void *)td) == xfer->td_transfer_last) {
 755                         td = NULL;
 756                         break;
 757                 }
 758                 /* Check for transfer error */
 759                 if (status != XHCI_TRB_ERROR_SHORT_PKT &&
 760                     status != XHCI_TRB_ERROR_SUCCESS) {
 761                         /* the transfer is finished */
 762                         td = NULL;
 763                         break;
 764                 }
 765                 /* Check for short transfer */
 766                 if (len > 0) {
 767                         if (xfer->flags_int.short_frames_ok ||
 768                             xfer->flags_int.isochronous_xfr ||
 769                             xfer->flags_int.control_xfr) {
 770                                 /* follow alt next */
 771                                 td = td->alt_next;
 772                         } else {
 773                                 /* the transfer is finished */
 774                                 td = NULL;
 775                         }
 776                         break;
 777                 }
 778                 td = td->obj_next;
 779
 780                 if (td->alt_next != td_alt_next) {
 781                         /* this USB frame is complete */
 782                         break;
 783                 }
 784         }
 785
 786         /* update transfer cache */
 787
 788         xfer->td_transfer_cache = td;
 789
 790         return ((status == XHCI_TRB_ERROR_STALL) ? USB_ERR_STALLED :
 791             (status != XHCI_TRB_ERROR_SHORT_PKT &&
 792             status != XHCI_TRB_ERROR_SUCCESS) ? USB_ERR_IOERROR :
 793             USB_ERR_NORMAL_COMPLETION);
 794 }
 795
 796 static void
 797 xhci_generic_done(struct usb_xfer *xfer)
 798 {
 799         usb_error_t err = 0;
 800
 801         DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
 802             xfer, xfer->endpoint);
 803
 804         /* reset scanner */
 805
 806         xfer->td_transfer_cache = xfer->td_transfer_first;
 807
 808         if (xfer->flags_int.control_xfr) {
 809
 810                 if (xfer->flags_int.control_hdr)
 811                         err = xhci_generic_done_sub(xfer);
 812
 813                 xfer->aframes = 1;
 814
 815                 if (xfer->td_transfer_cache == NULL)
 816                         goto done;
 817         }
 818
 819         while (xfer->aframes != xfer->nframes) {
 820
 821                 err = xhci_generic_done_sub(xfer);
 822                 xfer->aframes++;
 823
 824                 if (xfer->td_transfer_cache == NULL)
 825                         goto done;
 826         }
 827
 828         if (xfer->flags_int.control_xfr &&
 829             !xfer->flags_int.control_act)
 830                 err = xhci_generic_done_sub(xfer);
 831 done:
 832         /* transfer is complete */
 833         xhci_device_done(xfer, err);
 834 }
 835
 836 static void
 837 xhci_activate_transfer(struct usb_xfer *xfer)
 838 {
 839         struct xhci_td *td;
 840
 841         td = xfer->td_transfer_cache;
 842
 843         usb_pc_cpu_invalidate(td->page_cache);
 844
 845         if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) {
 846
 847                 /* activate the transfer */
 848
 849                 td->td_trb[0].dwTrb3 |= htole32(XHCI_TRB_3_CYCLE_BIT);
 850                 usb_pc_cpu_flush(td->page_cache);
 851
 852                 xhci_endpoint_doorbell(xfer);
 853         }
 854 }
 855
 856 static void
 857 xhci_skip_transfer(struct usb_xfer *xfer)
 858 {
 859         struct xhci_td *td;
 860         struct xhci_td *td_last;
 861
 862         td = xfer->td_transfer_cache;
 863         td_last = xfer->td_transfer_last;
 864
 865         td = td->alt_next;
 866
 867         usb_pc_cpu_invalidate(td->page_cache);
 868
 869         if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) {
 870
 871                 usb_pc_cpu_invalidate(td_last->page_cache);
 872
 873                 /* copy LINK TRB to current waiting location */
 874
 875                 td->td_trb[0].qwTrb0 = td_last->td_trb[td_last->ntrb].qwTrb0;
 876                 td->td_trb[0].dwTrb2 = td_last->td_trb[td_last->ntrb].dwTrb2;
 877                 usb_pc_cpu_flush(td->page_cache);
 878
 879                 td->td_trb[0].dwTrb3 = td_last->td_trb[td_last->ntrb].dwTrb3;
 880                 usb_pc_cpu_flush(td->page_cache);
 881
 882                 xhci_endpoint_doorbell(xfer);
 883         }
 884 }
 885
 886 /*------------------------------------------------------------------------*
 887  *      xhci_check_transfer
 888  *------------------------------------------------------------------------*/
 889 static void
 890 xhci_check_transfer(struct xhci_softc *sc, struct xhci_trb *trb)
 891 {
 892         struct xhci_endpoint_ext *pepext;
 893         int64_t offset;
 894         uint64_t td_event;
 895         uint32_t temp;
 896         uint32_t remainder;
 897         uint16_t stream_id = 0;
 898         uint16_t i;
 899         uint8_t status;
 900         uint8_t halted;
 901         uint8_t epno;
 902         uint8_t index;
 903
 904         /* decode TRB */
 905         td_event = le64toh(trb->qwTrb0);
 906         temp = le32toh(trb->dwTrb2);
 907
 908         remainder = XHCI_TRB_2_REM_GET(temp);
 909         status = XHCI_TRB_2_ERROR_GET(temp);
 910
 911         temp = le32toh(trb->dwTrb3);
 912         epno = XHCI_TRB_3_EP_GET(temp);
 913         index = XHCI_TRB_3_SLOT_GET(temp);
 914
 915         /* check if error means halted */
 916         halted = (status != XHCI_TRB_ERROR_SHORT_PKT &&
 917             status != XHCI_TRB_ERROR_SUCCESS);
 918
 919         DPRINTF("slot=%u epno=%u remainder=%u status=%u\n",
 920             index, epno, remainder, status);
 921
 922         if (index > sc->sc_noslot) {
 923                 DPRINTF("Invalid slot.\n");
 924                 return;
 925         }
 926
 927         if ((epno == 0) || (epno >= XHCI_MAX_ENDPOINTS)) {
 928                 DPRINTF("Invalid endpoint.\n");
 929                 return;
 930         }
 931
 932         pepext = &sc->sc_hw.devs[index].endp[epno];
 933
 934         /* try to find the USB transfer that generated the event */
 935         for (i = 0;; i++) {
 936                 struct usb_xfer *xfer;
 937                 struct xhci_td *td;
 938
 939                 if (i == (XHCI_MAX_TRANSFERS - 1)) {
 940                         if (pepext->trb_ep_mode != USB_EP_MODE_STREAMS ||
 941                             stream_id == (XHCI_MAX_STREAMS - 1))
 942                                 break;
 943                         stream_id++;
 944                         i = 0;
 945                         DPRINTFN(5, "stream_id=%u\n", stream_id);
 946                 }
 947
 948                 xfer = pepext->xfer[i + (XHCI_MAX_TRANSFERS * stream_id)];
 949                 if (xfer == NULL)
 950                         continue;
 951
 952                 td = xfer->td_transfer_cache;
 953
 954                 DPRINTFN(5, "Checking if 0x%016llx == (0x%016llx .. 0x%016llx)\n",
 955                         (long long)td_event,
 956                         (long long)td->td_self,
 957                         (long long)td->td_self + sizeof(td->td_trb));
 958
 959                 /*
 960                  * NOTE: Some XHCI implementations might not trigger
 961                  * an event on the last LINK TRB so we need to
 962                  * consider both the last and second last event
 963                  * address as conditions for a successful transfer.
 964                  *
 965                  * NOTE: We assume that the XHCI will only trigger one
 966                  * event per chain of TRBs.
 967                  */
 968
 969                 offset = td_event - td->td_self;
 970
 971                 if (offset >= 0 &&
 972                     offset < (int64_t)sizeof(td->td_trb)) {
 973
 974                         usb_pc_cpu_invalidate(td->page_cache);
 975
 976                         /* compute rest of remainder, if any */
 977                         for (i = (offset / 16) + 1; i < td->ntrb; i++) {
 978                                 temp = le32toh(td->td_trb[i].dwTrb2);
 979                                 remainder += XHCI_TRB_2_BYTES_GET(temp);
 980                         }
 981
 982                         DPRINTFN(5, "New remainder: %u\n", remainder);
 983
 984                         /* clear isochronous transfer errors */
 985                         if (xfer->flags_int.isochronous_xfr) {
 986                                 if (halted) {
 987                                         halted = 0;
 988                                         status = XHCI_TRB_ERROR_SUCCESS;
 989                                         remainder = td->len;
 990                                 }
 991                         }
 992
 993                         /* "td->remainder" is verified later */
 994                         td->remainder = remainder;
 995                         td->status = status;
 996
 997                         usb_pc_cpu_flush(td->page_cache);
 998
 999                         /*
1000                          * 1) Last transfer descriptor makes the
1001                          * transfer done
1002                          */
1003                         if (((void *)td) == xfer->td_transfer_last) {
1004                                 DPRINTF("TD is last\n");
1005                                 xhci_generic_done(xfer);
1006                                 break;
1007                         }
1008
1009                         /*
1010                          * 2) Any kind of error makes the transfer
1011                          * done
1012                          */
1013                         if (halted) {
1014                                 DPRINTF("TD has I/O error\n");
1015                                 xhci_generic_done(xfer);
1016                                 break;
1017                         }
1018
1019                         /*
1020                          * 3) If there is no alternate next transfer,
1021                          * a short packet also makes the transfer done
1022                          */
1023                         if (td->remainder > 0) {
1024                                 if (td->alt_next == NULL) {
1025                                         DPRINTF(
1026                                             "short TD has no alternate next\n");
1027                                         xhci_generic_done(xfer);
1028                                         break;
1029                                 }
1030                                 DPRINTF("TD has short pkt\n");
1031                                 if (xfer->flags_int.short_frames_ok ||
1032                                     xfer->flags_int.isochronous_xfr ||
1033                                     xfer->flags_int.control_xfr) {
1034                                         /* follow the alt next */
1035                                         xfer->td_transfer_cache = td->alt_next;
1036                                         xhci_activate_transfer(xfer);
1037                                         break;
1038                                 }
1039                                 xhci_skip_transfer(xfer);
1040                                 xhci_generic_done(xfer);
1041                                 break;
1042                         }
1043
1044                         /*
1045                          * 4) Transfer complete - go to next TD
1046                          */
1047                         DPRINTF("Following next TD\n");
1048                         xfer->td_transfer_cache = td->obj_next;
1049                         xhci_activate_transfer(xfer);
1050                         break;          /* there should only be one match */
1051                 }
1052         }
1053 }
1054
1055 static int
1056 xhci_check_command(struct xhci_softc *sc, struct xhci_trb *trb)
1057 {
1058         if (sc->sc_cmd_addr == trb->qwTrb0) {
1059                 DPRINTF("Received command event\n");
1060                 sc->sc_cmd_result[0] = trb->dwTrb2;
1061                 sc->sc_cmd_result[1] = trb->dwTrb3;
1062                 cv_signal(&sc->sc_cmd_cv);
1063                 return (1);     /* command match */
1064         }
1065         return (0);
1066 }
1067
1068 static int
1069 xhci_interrupt_poll(struct xhci_softc *sc)
1070 {
1071         struct usb_page_search buf_res;
1072         struct xhci_hw_root *phwr;
1073         uint64_t addr;
1074         uint32_t temp;
1075         int retval = 0;
1076         uint16_t i;
1077         uint8_t event;
1078         uint8_t j;
1079         uint8_t k;
1080         uint8_t t;
1081
1082         usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
1083
1084         phwr = buf_res.buffer;
1085
1086         /* Receive any events */
1087
1088         usb_pc_cpu_invalidate(&sc->sc_hw.root_pc);
1089
1090         i = sc->sc_event_idx;
1091         j = sc->sc_event_ccs;
1092         t = 2;
1093
1094         while (1) {
1095
1096                 temp = le32toh(phwr->hwr_events[i].dwTrb3);
1097
1098                 k = (temp & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0;
1099
1100                 if (j != k)
1101                         break;
1102
1103                 event = XHCI_TRB_3_TYPE_GET(temp);
1104
1105                 DPRINTFN(10, "event[%u] = %u (0x%016llx 0x%08lx 0x%08lx)\n",
1106                     i, event, (long long)le64toh(phwr->hwr_events[i].qwTrb0),
1107                     (long)le32toh(phwr->hwr_events[i].dwTrb2),
1108                     (long)le32toh(phwr->hwr_events[i].dwTrb3));
1109
1110                 switch (event) {
1111                 case XHCI_TRB_EVENT_TRANSFER:
1112                         xhci_check_transfer(sc, &phwr->hwr_events[i]);
1113                         break;
1114                 case XHCI_TRB_EVENT_CMD_COMPLETE:
1115                         retval |= xhci_check_command(sc, &phwr->hwr_events[i]);
1116                         break;
1117                 default:
1118                         DPRINTF("Unhandled event = %u\n", event);
1119                         break;
1120                 }
1121
1122                 i++;
1123
1124                 if (i == XHCI_MAX_EVENTS) {
1125                         i = 0;
1126                         j ^= 1;
1127
1128                         /* check for timeout */
1129                         if (!--t)
1130                                 break;
1131                 }
1132         }
1133
1134         sc->sc_event_idx = i;
1135         sc->sc_event_ccs = j;
1136
1137         /*
1138          * NOTE: The Event Ring Dequeue Pointer Register is 64-bit
1139          * latched. That means to activate the register we need to
1140          * write both the low and high double word of the 64-bit
1141          * register.
1142          */
1143
1144         addr = buf_res.physaddr;
1145         addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[i];
1146
1147         /* try to clear busy bit */
1148         addr |= XHCI_ERDP_LO_BUSY;
1149
1150         XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr);
1151         XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32));
1152
1153         return (retval);
1154 }
1155
1156 static usb_error_t
1157 xhci_do_command(struct xhci_softc *sc, struct xhci_trb *trb,
1158     uint16_t timeout_ms)
1159 {
1160         struct usb_page_search buf_res;
1161         struct xhci_hw_root *phwr;
1162         uint64_t addr;
1163         uint32_t temp;
1164         uint8_t i;
1165         uint8_t j;
1166         uint8_t timeout = 0;
1167         int err;
1168
1169         XHCI_CMD_ASSERT_LOCKED(sc);
1170
1171         /* get hardware root structure */
1172
1173         usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
1174
1175         phwr = buf_res.buffer;
1176
1177         /* Queue command */
1178
1179         USB_BUS_LOCK(&sc->sc_bus);
1180 retry:
1181         i = sc->sc_command_idx;
1182         j = sc->sc_command_ccs;
1183
1184         DPRINTFN(10, "command[%u] = %u (0x%016llx, 0x%08lx, 0x%08lx)\n",
1185             i, XHCI_TRB_3_TYPE_GET(le32toh(trb->dwTrb3)),
1186             (long long)le64toh(trb->qwTrb0),
1187             (long)le32toh(trb->dwTrb2),
1188             (long)le32toh(trb->dwTrb3));
1189
1190         phwr->hwr_commands[i].qwTrb0 = trb->qwTrb0;
1191         phwr->hwr_commands[i].dwTrb2 = trb->dwTrb2;
1192
1193         usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1194
1195         temp = trb->dwTrb3;
1196
1197         if (j)
1198                 temp |= htole32(XHCI_TRB_3_CYCLE_BIT);
1199         else
1200                 temp &= ~htole32(XHCI_TRB_3_CYCLE_BIT);
1201
1202         temp &= ~htole32(XHCI_TRB_3_TC_BIT);
1203
1204         phwr->hwr_commands[i].dwTrb3 = temp;
1205
1206         usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1207
1208         addr = buf_res.physaddr;
1209         addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[i];
1210
1211         sc->sc_cmd_addr = htole64(addr);
1212
1213         i++;
1214
1215         if (i == (XHCI_MAX_COMMANDS - 1)) {
1216
1217                 if (j) {
1218                         temp = htole32(XHCI_TRB_3_TC_BIT |
1219                             XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) |
1220                             XHCI_TRB_3_CYCLE_BIT);
1221                 } else {
1222                         temp = htole32(XHCI_TRB_3_TC_BIT |
1223                             XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
1224                 }
1225
1226                 phwr->hwr_commands[i].dwTrb3 = temp;
1227
1228                 usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1229
1230                 i = 0;
1231                 j ^= 1;
1232         }
1233
1234         sc->sc_command_idx = i;
1235         sc->sc_command_ccs = j;
1236
1237         XWRITE4(sc, door, XHCI_DOORBELL(0), 0);
1238
1239         err = cv_timedwait(&sc->sc_cmd_cv, &sc->sc_bus.bus_mtx,
1240             USB_MS_TO_TICKS(timeout_ms));
1241
1242         /*
1243          * In some error cases event interrupts are not generated.
1244          * Poll one time to see if the command has completed.
1245          */
1246         if (err != 0 && xhci_interrupt_poll(sc) != 0) {
1247                 DPRINTF("Command was completed when polling\n");
1248                 err = 0;
1249         }
1250         if (err != 0) {
1251                 DPRINTF("Command timeout!\n");
1252                 /*
1253                  * After some weeks of continuous operation, it has
1254                  * been observed that the ASMedia Technology, ASM1042
1255                  * SuperSpeed USB Host Controller can suddenly stop
1256                  * accepting commands via the command queue. Try to
1257                  * first reset the command queue. If that fails do a
1258                  * host controller reset.
1259                  */
1260                 if (timeout == 0 &&
1261                     xhci_reset_command_queue_locked(sc) == 0) {
1262                         temp = le32toh(trb->dwTrb3);
1263
1264                         /*
1265                          * Avoid infinite XHCI reset loops if the set
1266                          * address command fails to respond due to a
1267                          * non-enumerating device:
1268                          */
1269                         if (XHCI_TRB_3_TYPE_GET(temp) == XHCI_TRB_TYPE_ADDRESS_DEVICE &&
1270                             (temp & XHCI_TRB_3_BSR_BIT) == 0) {
1271                                 DPRINTF("Set address timeout\n");
1272                         } else {
1273                                 timeout = 1;
1274                                 goto retry;
1275                         }
1276                 } else {
1277                         DPRINTF("Controller reset!\n");
1278                         usb_bus_reset_async_locked(&sc->sc_bus);
1279                 }
1280                 err = USB_ERR_TIMEOUT;
1281                 trb->dwTrb2 = 0;
1282                 trb->dwTrb3 = 0;
1283         } else {
1284                 temp = le32toh(sc->sc_cmd_result[0]);
1285                 if (XHCI_TRB_2_ERROR_GET(temp) != XHCI_TRB_ERROR_SUCCESS)
1286                         err = USB_ERR_IOERROR;
1287
1288                 trb->dwTrb2 = sc->sc_cmd_result[0];
1289                 trb->dwTrb3 = sc->sc_cmd_result[1];
1290         }
1291
1292         USB_BUS_UNLOCK(&sc->sc_bus);
1293
1294         return (err);
1295 }
1296
1297 #if 0
1298 static usb_error_t
1299 xhci_cmd_nop(struct xhci_softc *sc)
1300 {
1301         struct xhci_trb trb;
1302         uint32_t temp;
1303
1304         DPRINTF("\n");
1305
1306         trb.qwTrb0 = 0;
1307         trb.dwTrb2 = 0;
1308         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NOOP);
1309
1310         trb.dwTrb3 = htole32(temp);
1311
1312         return (xhci_do_command(sc, &trb, 100 /* ms */));
1313 }
1314 #endif
1315
1316 static usb_error_t
1317 xhci_cmd_enable_slot(struct xhci_softc *sc, uint8_t *pslot)
1318 {
1319         struct xhci_trb trb;
1320         uint32_t temp;
1321         usb_error_t err;
1322
1323         DPRINTF("\n");
1324
1325         trb.qwTrb0 = 0;
1326         trb.dwTrb2 = 0;
1327         trb.dwTrb3 = htole32(XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT));
1328
1329         err = xhci_do_command(sc, &trb, 100 /* ms */);
1330         if (err)
1331                 goto done;
1332
1333         temp = le32toh(trb.dwTrb3);
1334
1335         *pslot = XHCI_TRB_3_SLOT_GET(temp);
1336
1337 done:
1338         return (err);
1339 }
1340
1341 static usb_error_t
1342 xhci_cmd_disable_slot(struct xhci_softc *sc, uint8_t slot_id)
1343 {
1344         struct xhci_trb trb;
1345         uint32_t temp;
1346
1347         DPRINTF("\n");
1348
1349         trb.qwTrb0 = 0;
1350         trb.dwTrb2 = 0;
1351         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT) |
1352             XHCI_TRB_3_SLOT_SET(slot_id);
1353
1354         trb.dwTrb3 = htole32(temp);
1355
1356         return (xhci_do_command(sc, &trb, 100 /* ms */));
1357 }
1358
1359 static usb_error_t
1360 xhci_cmd_set_address(struct xhci_softc *sc, uint64_t input_ctx,
1361     uint8_t bsr, uint8_t slot_id)
1362 {
1363         struct xhci_trb trb;
1364         uint32_t temp;
1365
1366         DPRINTF("\n");
1367
1368         trb.qwTrb0 = htole64(input_ctx);
1369         trb.dwTrb2 = 0;
1370         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) |
1371             XHCI_TRB_3_SLOT_SET(slot_id);
1372
1373         if (bsr)
1374                 temp |= XHCI_TRB_3_BSR_BIT;
1375
1376         trb.dwTrb3 = htole32(temp);
1377
1378         return (xhci_do_command(sc, &trb, 500 /* ms */));
1379 }
1380
1381 static usb_error_t
1382 xhci_set_address(struct usb_device *udev, struct mtx *mtx, uint16_t address)
1383 {
1384         struct usb_page_search buf_inp;
1385         struct usb_page_search buf_dev;
1386         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
1387         struct xhci_hw_dev *hdev;
1388         struct xhci_dev_ctx *pdev;
1389         struct xhci_endpoint_ext *pepext;
1390         uint32_t temp;
1391         uint16_t mps;
1392         usb_error_t err;
1393         uint8_t index;
1394
1395         /* the root HUB case is not handled here */
1396         if (udev->parent_hub == NULL)
1397                 return (USB_ERR_INVAL);
1398
1399         index = udev->controller_slot_id;
1400
1401         hdev =  &sc->sc_hw.devs[index];
1402
1403         if (mtx != NULL)
1404                 mtx_unlock(mtx);
1405
1406         XHCI_CMD_LOCK(sc);
1407
1408         switch (hdev->state) {
1409         case XHCI_ST_DEFAULT:
1410         case XHCI_ST_ENABLED:
1411
1412                 hdev->state = XHCI_ST_ENABLED;
1413
1414                 /* set configure mask to slot and EP0 */
1415                 xhci_configure_mask(udev, 3, 0);
1416
1417                 /* configure input slot context structure */
1418                 err = xhci_configure_device(udev);
1419
1420                 if (err != 0) {
1421                         DPRINTF("Could not configure device\n");
1422                         break;
1423                 }
1424
1425                 /* configure input endpoint context structure */
1426                 switch (udev->speed) {
1427                 case USB_SPEED_LOW:
1428                 case USB_SPEED_FULL:
1429                         mps = 8;
1430                         break;
1431                 case USB_SPEED_HIGH:
1432                         mps = 64;
1433                         break;
1434                 default:
1435                         mps = 512;
1436                         break;
1437                 }
1438
1439                 pepext = xhci_get_endpoint_ext(udev,
1440                     &udev->ctrl_ep_desc);
1441
1442                 /* ensure the control endpoint is setup again */
1443                 USB_BUS_LOCK(udev->bus);
1444                 pepext->trb_halted = 1;
1445                 pepext->trb_running = 0;
1446                 USB_BUS_UNLOCK(udev->bus);
1447
1448                 err = xhci_configure_endpoint(udev,
1449                     &udev->ctrl_ep_desc, pepext,
1450                     0, 1, 1, 0, mps, mps, USB_EP_MODE_DEFAULT);
1451
1452                 if (err != 0) {
1453                         DPRINTF("Could not configure default endpoint\n");
1454                         break;
1455                 }
1456
1457                 /* execute set address command */
1458                 usbd_get_page(&hdev->input_pc, 0, &buf_inp);
1459
1460                 err = xhci_cmd_set_address(sc, buf_inp.physaddr,
1461                     (address == 0), index);
1462
1463                 if (err != 0) {
1464                         temp = le32toh(sc->sc_cmd_result[0]);
1465                         if (address == 0 && sc->sc_port_route != NULL &&
1466                             XHCI_TRB_2_ERROR_GET(temp) ==
1467                             XHCI_TRB_ERROR_PARAMETER) {
1468                                 /* LynxPoint XHCI - ports are not switchable */
1469                                 /* Un-route all ports from the XHCI */
1470                                 sc->sc_port_route(sc->sc_bus.parent, 0, ~0);
1471                         }
1472                         DPRINTF("Could not set address "
1473                             "for slot %u.\n", index);
1474                         if (address != 0)
1475                                 break;
1476                 }
1477
1478                 /* update device address to new value */
1479
1480                 usbd_get_page(&hdev->device_pc, 0, &buf_dev);
1481                 pdev = buf_dev.buffer;
1482                 usb_pc_cpu_invalidate(&hdev->device_pc);
1483
1484                 temp = xhci_ctx_get_le32(sc, &pdev->ctx_slot.dwSctx3);
1485                 udev->address = XHCI_SCTX_3_DEV_ADDR_GET(temp);
1486
1487                 /* update device state to new value */
1488
1489                 if (address != 0)
1490                         hdev->state = XHCI_ST_ADDRESSED;
1491                 else
1492                         hdev->state = XHCI_ST_DEFAULT;
1493                 break;
1494
1495         default:
1496                 DPRINTF("Wrong state for set address.\n");
1497                 err = USB_ERR_IOERROR;
1498                 break;
1499         }
1500         XHCI_CMD_UNLOCK(sc);
1501
1502         if (mtx != NULL)
1503                 mtx_lock(mtx);
1504
1505         return (err);
1506 }
1507
1508 static usb_error_t
1509 xhci_cmd_configure_ep(struct xhci_softc *sc, uint64_t input_ctx,
1510     uint8_t deconfigure, uint8_t slot_id)
1511 {
1512         struct xhci_trb trb;
1513         uint32_t temp;
1514
1515         DPRINTF("\n");
1516
1517         trb.qwTrb0 = htole64(input_ctx);
1518         trb.dwTrb2 = 0;
1519         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP) |
1520             XHCI_TRB_3_SLOT_SET(slot_id);
1521
1522         if (deconfigure)
1523                 temp |= XHCI_TRB_3_DCEP_BIT;
1524
1525         trb.dwTrb3 = htole32(temp);
1526
1527         return (xhci_do_command(sc, &trb, 100 /* ms */));
1528 }
1529
1530 static usb_error_t
1531 xhci_cmd_evaluate_ctx(struct xhci_softc *sc, uint64_t input_ctx,
1532     uint8_t slot_id)
1533 {
1534         struct xhci_trb trb;
1535         uint32_t temp;
1536
1537         DPRINTF("\n");
1538
1539         trb.qwTrb0 = htole64(input_ctx);
1540         trb.dwTrb2 = 0;
1541         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX) |
1542             XHCI_TRB_3_SLOT_SET(slot_id);
1543         trb.dwTrb3 = htole32(temp);
1544
1545         return (xhci_do_command(sc, &trb, 100 /* ms */));
1546 }
1547
1548 static usb_error_t
1549 xhci_cmd_reset_ep(struct xhci_softc *sc, uint8_t preserve,
1550     uint8_t ep_id, uint8_t slot_id)
1551 {
1552         struct xhci_trb trb;
1553         uint32_t temp;
1554
1555         DPRINTF("\n");
1556
1557         trb.qwTrb0 = 0;
1558         trb.dwTrb2 = 0;
1559         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP) |
1560             XHCI_TRB_3_SLOT_SET(slot_id) |
1561             XHCI_TRB_3_EP_SET(ep_id);
1562
1563         if (preserve)
1564                 temp |= XHCI_TRB_3_PRSV_BIT;
1565
1566         trb.dwTrb3 = htole32(temp);
1567
1568         return (xhci_do_command(sc, &trb, 100 /* ms */));
1569 }
1570
1571 static usb_error_t
1572 xhci_cmd_set_tr_dequeue_ptr(struct xhci_softc *sc, uint64_t dequeue_ptr,
1573     uint16_t stream_id, uint8_t ep_id, uint8_t slot_id)
1574 {
1575         struct xhci_trb trb;
1576         uint32_t temp;
1577
1578         DPRINTF("\n");
1579
1580         trb.qwTrb0 = htole64(dequeue_ptr);
1581
1582         temp = XHCI_TRB_2_STREAM_SET(stream_id);
1583         trb.dwTrb2 = htole32(temp);
1584
1585         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE) |
1586             XHCI_TRB_3_SLOT_SET(slot_id) |
1587             XHCI_TRB_3_EP_SET(ep_id);
1588         trb.dwTrb3 = htole32(temp);
1589
1590         return (xhci_do_command(sc, &trb, 100 /* ms */));
1591 }
1592
1593 static usb_error_t
1594 xhci_cmd_stop_ep(struct xhci_softc *sc, uint8_t suspend,
1595     uint8_t ep_id, uint8_t slot_id)
1596 {
1597         struct xhci_trb trb;
1598         uint32_t temp;
1599
1600         DPRINTF("\n");
1601
1602         trb.qwTrb0 = 0;
1603         trb.dwTrb2 = 0;
1604         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP) |
1605             XHCI_TRB_3_SLOT_SET(slot_id) |
1606             XHCI_TRB_3_EP_SET(ep_id);
1607
1608         if (suspend)
1609                 temp |= XHCI_TRB_3_SUSP_EP_BIT;
1610
1611         trb.dwTrb3 = htole32(temp);
1612
1613         return (xhci_do_command(sc, &trb, 100 /* ms */));
1614 }
1615
1616 static usb_error_t
1617 xhci_cmd_reset_dev(struct xhci_softc *sc, uint8_t slot_id)
1618 {
1619         struct xhci_trb trb;
1620         uint32_t temp;
1621
1622         DPRINTF("\n");
1623
1624         trb.qwTrb0 = 0;
1625         trb.dwTrb2 = 0;
1626         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_DEVICE) |
1627             XHCI_TRB_3_SLOT_SET(slot_id);
1628
1629         trb.dwTrb3 = htole32(temp);
1630
1631         return (xhci_do_command(sc, &trb, 100 /* ms */));
1632 }
1633
1634 /*------------------------------------------------------------------------*
1635  *      xhci_interrupt - XHCI interrupt handler
1636  *------------------------------------------------------------------------*/
1637 void
1638 xhci_interrupt(struct xhci_softc *sc)
1639 {
1640         uint32_t status;
1641         uint32_t temp;
1642
1643         USB_BUS_LOCK(&sc->sc_bus);
1644
1645         status = XREAD4(sc, oper, XHCI_USBSTS);
1646
1647         /* acknowledge interrupts, if any */
1648         if (status != 0) {
1649                 XWRITE4(sc, oper, XHCI_USBSTS, status);
1650                 DPRINTFN(16, "real interrupt (status=0x%08x)\n", status);
1651         }
1652
1653         temp = XREAD4(sc, runt, XHCI_IMAN(0));
1654
1655         /* force clearing of pending interrupts */
1656         if (temp & XHCI_IMAN_INTR_PEND)
1657                 XWRITE4(sc, runt, XHCI_IMAN(0), temp);
1658
1659         /* check for event(s) */
1660         xhci_interrupt_poll(sc);
1661
1662         if (status & (XHCI_STS_PCD | XHCI_STS_HCH |
1663             XHCI_STS_HSE | XHCI_STS_HCE)) {
1664
1665                 if (status & XHCI_STS_PCD) {
1666                         xhci_root_intr(sc);
1667                 }
1668
1669                 if (status & XHCI_STS_HCH) {
1670                         printf("%s: host controller halted\n",
1671                             __FUNCTION__);
1672                 }
1673
1674                 if (status & XHCI_STS_HSE) {
1675                         printf("%s: host system error\n",
1676                             __FUNCTION__);
1677                 }
1678
1679                 if (status & XHCI_STS_HCE) {
1680                         printf("%s: host controller error\n",
1681                            __FUNCTION__);
1682                 }
1683         }
1684         USB_BUS_UNLOCK(&sc->sc_bus);
1685 }
1686
1687 /*------------------------------------------------------------------------*
1688  *      xhci_timeout - XHCI timeout handler
1689  *------------------------------------------------------------------------*/
1690 static void
1691 xhci_timeout(void *arg)
1692 {
1693         struct usb_xfer *xfer = arg;
1694
1695         DPRINTF("xfer=%p\n", xfer);
1696
1697         USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
1698
1699         /* transfer is transferred */
1700         xhci_device_done(xfer, USB_ERR_TIMEOUT);
1701 }
1702
1703 static void
1704 xhci_do_poll(struct usb_bus *bus)
1705 {
1706         struct xhci_softc *sc = XHCI_BUS2SC(bus);
1707
1708         USB_BUS_LOCK(&sc->sc_bus);
1709         xhci_interrupt_poll(sc);
1710         USB_BUS_UNLOCK(&sc->sc_bus);
1711 }
1712
1713 static void
1714 xhci_setup_generic_chain_sub(struct xhci_std_temp *temp)
1715 {
1716         struct usb_page_search buf_res;
1717         struct xhci_td *td;
1718         struct xhci_td *td_next;
1719         struct xhci_td *td_alt_next;
1720         struct xhci_td *td_first;
1721         uint32_t buf_offset;
1722         uint32_t average;
1723         uint32_t len_old;
1724         uint32_t npkt_off;
1725         uint32_t dword;
1726         uint8_t shortpkt_old;
1727         uint8_t precompute;
1728         uint8_t x;
1729
1730         td_alt_next = NULL;
1731         buf_offset = 0;
1732         shortpkt_old = temp->shortpkt;
1733         len_old = temp->len;
1734         npkt_off = 0;
1735         precompute = 1;
1736
1737 restart:
1738
1739         td = temp->td;
1740         td_next = td_first = temp->td_next;
1741
1742         while (1) {
1743
1744                 if (temp->len == 0) {
1745
1746                         if (temp->shortpkt)
1747                                 break;
1748
1749                         /* send a Zero Length Packet, ZLP, last */
1750
1751                         temp->shortpkt = 1;
1752                         average = 0;
1753
1754                 } else {
1755
1756                         average = temp->average;
1757
1758                         if (temp->len < average) {
1759                                 if (temp->len % temp->max_packet_size) {
1760                                         temp->shortpkt = 1;
1761                                 }
1762                                 average = temp->len;
1763                         }
1764                 }
1765
1766                 if (td_next == NULL)
1767                         panic("%s: out of XHCI transfer descriptors!", __FUNCTION__);
1768
1769                 /* get next TD */
1770
1771                 td = td_next;
1772                 td_next = td->obj_next;
1773
1774                 /* check if we are pre-computing */
1775
1776                 if (precompute) {
1777
1778                         /* update remaining length */
1779
1780                         temp->len -= average;
1781
1782                         continue;
1783                 }
1784                 /* fill out current TD */
1785
1786                 td->len = average;
1787                 td->remainder = 0;
1788                 td->status = 0;
1789
1790                 /* update remaining length */
1791
1792                 temp->len -= average;
1793
1794                 /* reset TRB index */
1795
1796                 x = 0;
1797
1798                 if (temp->trb_type == XHCI_TRB_TYPE_SETUP_STAGE) {
1799                         /* immediate data */
1800
1801                         if (average > 8)
1802                                 average = 8;
1803
1804                         td->td_trb[0].qwTrb0 = 0;
1805
1806                         usbd_copy_out(temp->pc, temp->offset + buf_offset,
1807                            (uint8_t *)(uintptr_t)&td->td_trb[0].qwTrb0,
1808                            average);
1809
1810                         dword = XHCI_TRB_2_BYTES_SET(8) |
1811                             XHCI_TRB_2_TDSZ_SET(0) |
1812                             XHCI_TRB_2_IRQ_SET(0);
1813
1814                         td->td_trb[0].dwTrb2 = htole32(dword);
1815
1816                         dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) |
1817                           XHCI_TRB_3_IDT_BIT | XHCI_TRB_3_CYCLE_BIT;
1818
1819                         /* check wLength */
1820                         if (td->td_trb[0].qwTrb0 &
1821                            htole64(XHCI_TRB_0_WLENGTH_MASK)) {
1822                                 if (td->td_trb[0].qwTrb0 &
1823                                     htole64(XHCI_TRB_0_DIR_IN_MASK))
1824                                         dword |= XHCI_TRB_3_TRT_IN;
1825                                 else
1826                                         dword |= XHCI_TRB_3_TRT_OUT;
1827                         }
1828
1829                         td->td_trb[0].dwTrb3 = htole32(dword);
1830 #ifdef USB_DEBUG
1831                         xhci_dump_trb(&td->td_trb[x]);
1832 #endif
1833                         x++;
1834
1835                 } else do {
1836
1837                         uint32_t npkt;
1838
1839                         /* fill out buffer pointers */
1840
1841                         if (average == 0) {
1842                                 memset(&buf_res, 0, sizeof(buf_res));
1843                         } else {
1844                                 usbd_get_page(temp->pc, temp->offset +
1845                                     buf_offset, &buf_res);
1846
1847                                 /* get length to end of page */
1848                                 if (buf_res.length > average)
1849                                         buf_res.length = average;
1850
1851                                 /* check for maximum length */
1852                                 if (buf_res.length > XHCI_TD_PAGE_SIZE)
1853                                         buf_res.length = XHCI_TD_PAGE_SIZE;
1854
1855                                 npkt_off += buf_res.length;
1856                         }
1857
1858                         /* set up npkt */
1859                         npkt = howmany(len_old - npkt_off,
1860                                        temp->max_packet_size);
1861
1862                         if (npkt == 0)
1863                                 npkt = 1;
1864                         else if (npkt > 31)
1865                                 npkt = 31;
1866
1867                         /* fill out TRB's */
1868                         td->td_trb[x].qwTrb0 =
1869                             htole64((uint64_t)buf_res.physaddr);
1870
1871                         dword =
1872                           XHCI_TRB_2_BYTES_SET(buf_res.length) |
1873                           XHCI_TRB_2_TDSZ_SET(npkt) |
1874                           XHCI_TRB_2_IRQ_SET(0);
1875
1876                         td->td_trb[x].dwTrb2 = htole32(dword);
1877
1878                         switch (temp->trb_type) {
1879                         case XHCI_TRB_TYPE_ISOCH:
1880                                 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1881                                     XHCI_TRB_3_TBC_SET(temp->tbc) |
1882                                     XHCI_TRB_3_TLBPC_SET(temp->tlbpc);
1883                                 if (td != td_first) {
1884                                         dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL);
1885                                 } else if (temp->do_isoc_sync != 0) {
1886                                         temp->do_isoc_sync = 0;
1887                                         /* wait until "isoc_frame" */
1888                                         dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) |
1889                                             XHCI_TRB_3_FRID_SET(temp->isoc_frame / 8);
1890                                 } else {
1891                                         /* start data transfer at next interval */
1892                                         dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) |
1893                                             XHCI_TRB_3_ISO_SIA_BIT;
1894                                 }
1895                                 if (temp->direction == UE_DIR_IN)
1896                                         dword |= XHCI_TRB_3_ISP_BIT;
1897                                 break;
1898                         case XHCI_TRB_TYPE_DATA_STAGE:
1899                                 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1900                                     XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE);
1901                                 if (temp->direction == UE_DIR_IN)
1902                                         dword |= XHCI_TRB_3_DIR_IN | XHCI_TRB_3_ISP_BIT;
1903                                 /*
1904                                  * Section 3.2.9 in the XHCI
1905                                  * specification about control
1906                                  * transfers says that we should use a
1907                                  * normal-TRB if there are more TRBs
1908                                  * extending the data-stage
1909                                  * TRB. Update the "trb_type".
1910                                  */
1911                                 temp->trb_type = XHCI_TRB_TYPE_NORMAL;
1912                                 break;
1913                         case XHCI_TRB_TYPE_STATUS_STAGE:
1914                                 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1915                                     XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE);
1916                                 if (temp->direction == UE_DIR_IN)
1917                                         dword |= XHCI_TRB_3_DIR_IN;
1918                                 break;
1919                         default:        /* XHCI_TRB_TYPE_NORMAL */
1920                                 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1921                                     XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL);
1922                                 if (temp->direction == UE_DIR_IN)
1923                                         dword |= XHCI_TRB_3_ISP_BIT;
1924                                 break;
1925                         }
1926                         td->td_trb[x].dwTrb3 = htole32(dword);
1927
1928                         average -= buf_res.length;
1929                         buf_offset += buf_res.length;
1930 #ifdef USB_DEBUG
1931                         xhci_dump_trb(&td->td_trb[x]);
1932 #endif
1933                         x++;
1934
1935                 } while (average != 0);
1936
1937                 td->td_trb[x-1].dwTrb3 |= htole32(XHCI_TRB_3_IOC_BIT);
1938
1939                 /* store number of data TRB's */
1940
1941                 td->ntrb = x;
1942
1943                 DPRINTF("NTRB=%u\n", x);
1944
1945                 /* fill out link TRB */
1946
1947                 if (td_next != NULL) {
1948                         /* link the current TD with the next one */
1949                         td->td_trb[x].qwTrb0 = htole64((uint64_t)td_next->td_self);
1950                         DPRINTF("LINK=0x%08llx\n", (long long)td_next->td_self);
1951                 } else {
1952                         /* this field will get updated later */
1953                         DPRINTF("NOLINK\n");
1954                 }
1955
1956                 dword = XHCI_TRB_2_IRQ_SET(0);
1957
1958                 td->td_trb[x].dwTrb2 = htole32(dword);
1959
1960                 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) |
1961                     XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_IOC_BIT |
1962                     /*
1963                      * CHAIN-BIT: Ensure that a multi-TRB IN-endpoint
1964                      * frame only receives a single short packet event
1965                      * by setting the CHAIN bit in the LINK field. In
1966                      * addition some XHCI controllers have problems
1967                      * sending a ZLP unless the CHAIN-BIT is set in
1968                      * the LINK TRB.
1969                      */
1970                     XHCI_TRB_3_CHAIN_BIT;
1971
1972                 td->td_trb[x].dwTrb3 = htole32(dword);
1973
1974                 td->alt_next = td_alt_next;
1975 #ifdef USB_DEBUG
1976                 xhci_dump_trb(&td->td_trb[x]);
1977 #endif
1978                 usb_pc_cpu_flush(td->page_cache);
1979         }
1980
1981         if (precompute) {
1982                 precompute = 0;
1983
1984                 /* set up alt next pointer, if any */
1985                 if (temp->last_frame) {
1986                         td_alt_next = NULL;
1987                 } else {
1988                         /* we use this field internally */
1989                         td_alt_next = td_next;
1990                 }
1991
1992                 /* restore */
1993                 temp->shortpkt = shortpkt_old;
1994                 temp->len = len_old;
1995                 goto restart;
1996         }
1997
1998         /*
1999          * Remove cycle bit from the first TRB if we are
2000          * stepping them:
2001          */
2002         if (temp->step_td != 0) {
2003                 td_first->td_trb[0].dwTrb3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT);
2004                 usb_pc_cpu_flush(td_first->page_cache);
2005         }
2006
2007         /* clear TD SIZE to zero, hence this is the last TRB */
2008         /* remove chain bit because this is the last data TRB in the chain */
2009         td->td_trb[td->ntrb - 1].dwTrb2 &= ~htole32(XHCI_TRB_2_TDSZ_SET(31));
2010         td->td_trb[td->ntrb - 1].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT);
2011         /* remove CHAIN-BIT from last LINK TRB */
2012         td->td_trb[td->ntrb].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT);
2013
2014         usb_pc_cpu_flush(td->page_cache);
2015
2016         temp->td = td;
2017         temp->td_next = td_next;
2018 }
2019
2020 static void
2021 xhci_setup_generic_chain(struct usb_xfer *xfer)
2022 {
2023         struct xhci_std_temp temp;
2024         struct xhci_td *td;
2025         uint32_t x;
2026         uint32_t y;
2027         uint8_t mult;
2028
2029         temp.do_isoc_sync = 0;
2030         temp.step_td = 0;
2031         temp.tbc = 0;
2032         temp.tlbpc = 0;
2033         temp.average = xfer->max_hc_frame_size;
2034         temp.max_packet_size = xfer->max_packet_size;
2035         temp.sc = XHCI_BUS2SC(xfer->xroot->bus);
2036         temp.pc = NULL;
2037         temp.last_frame = 0;
2038         temp.offset = 0;
2039         temp.multishort = xfer->flags_int.isochronous_xfr ||
2040             xfer->flags_int.control_xfr ||
2041             xfer->flags_int.short_frames_ok;
2042
2043         /* toggle the DMA set we are using */
2044         xfer->flags_int.curr_dma_set ^= 1;
2045
2046         /* get next DMA set */
2047         td = xfer->td_start[xfer->flags_int.curr_dma_set];
2048
2049         temp.td = NULL;
2050         temp.td_next = td;
2051
2052         xfer->td_transfer_first = td;
2053         xfer->td_transfer_cache = td;
2054
2055         if (xfer->flags_int.isochronous_xfr) {
2056                 uint8_t shift;
2057
2058                 /* compute multiplier for ISOCHRONOUS transfers */
2059                 mult = xfer->endpoint->ecomp ?
2060                     UE_GET_SS_ISO_MULT(xfer->endpoint->ecomp->bmAttributes)
2061                     : 0;
2062                 /* check for USB 2.0 multiplier */
2063                 if (mult == 0) {
2064                         mult = (xfer->endpoint->edesc->
2065                             wMaxPacketSize[1] >> 3) & 3;
2066                 }
2067                 /* range check */
2068                 if (mult > 2)
2069                         mult = 3;
2070                 else
2071                         mult++;
2072
2073                 x = XREAD4(temp.sc, runt, XHCI_MFINDEX);
2074
2075                 DPRINTF("MFINDEX=0x%08x\n", x);
2076
2077                 switch (usbd_get_speed(xfer->xroot->udev)) {
2078                 case USB_SPEED_FULL:
2079                         shift = 3;
2080                         temp.isoc_delta = 8;    /* 1ms */
2081                         x += temp.isoc_delta - 1;
2082                         x &= ~(temp.isoc_delta - 1);
2083                         break;
2084                 default:
2085                         shift = usbd_xfer_get_fps_shift(xfer);
2086                         temp.isoc_delta = 1U << shift;
2087                         x += temp.isoc_delta - 1;
2088                         x &= ~(temp.isoc_delta - 1);
2089                         /* simple frame load balancing */
2090                         x += xfer->endpoint->usb_uframe;
2091                         break;
2092                 }
2093
2094                 y = XHCI_MFINDEX_GET(x - xfer->endpoint->isoc_next);
2095
2096                 if ((xfer->endpoint->is_synced == 0) ||
2097                     (y < (xfer->nframes << shift)) ||
2098                     (XHCI_MFINDEX_GET(-y) >= (128 * 8))) {
2099                         /*
2100                          * If there is data underflow or the pipe
2101                          * queue is empty we schedule the transfer a
2102                          * few frames ahead of the current frame
2103                          * position. Else two isochronous transfers
2104                          * might overlap.
2105                          */
2106                         xfer->endpoint->isoc_next = XHCI_MFINDEX_GET(x + (3 * 8));
2107                         xfer->endpoint->is_synced = 1;
2108                         temp.do_isoc_sync = 1;
2109
2110                         DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
2111                 }
2112
2113                 /* compute isochronous completion time */
2114
2115                 y = XHCI_MFINDEX_GET(xfer->endpoint->isoc_next - (x & ~7));
2116
2117                 xfer->isoc_time_complete =
2118                     usb_isoc_time_expand(&temp.sc->sc_bus, x / 8) +
2119                     (y / 8) + (((xfer->nframes << shift) + 7) / 8);
2120
2121                 x = 0;
2122                 temp.isoc_frame = xfer->endpoint->isoc_next;
2123                 temp.trb_type = XHCI_TRB_TYPE_ISOCH;
2124
2125                 xfer->endpoint->isoc_next += xfer->nframes << shift;
2126
2127         } else if (xfer->flags_int.control_xfr) {
2128
2129                 /* check if we should prepend a setup message */
2130
2131                 if (xfer->flags_int.control_hdr) {
2132
2133                         temp.len = xfer->frlengths[0];
2134                         temp.pc = xfer->frbuffers + 0;
2135                         temp.shortpkt = temp.len ? 1 : 0;
2136                         temp.trb_type = XHCI_TRB_TYPE_SETUP_STAGE;
2137                         temp.direction = 0;
2138
2139                         /* check for last frame */
2140                         if (xfer->nframes == 1) {
2141                                 /* no STATUS stage yet, SETUP is last */
2142                                 if (xfer->flags_int.control_act)
2143                                         temp.last_frame = 1;
2144                         }
2145
2146                         xhci_setup_generic_chain_sub(&temp);
2147                 }
2148                 x = 1;
2149                 mult = 1;
2150                 temp.isoc_delta = 0;
2151                 temp.isoc_frame = 0;
2152                 temp.trb_type = xfer->flags_int.control_did_data ?
2153                     XHCI_TRB_TYPE_NORMAL : XHCI_TRB_TYPE_DATA_STAGE;
2154         } else {
2155                 x = 0;
2156                 mult = 1;
2157                 temp.isoc_delta = 0;
2158                 temp.isoc_frame = 0;
2159                 temp.trb_type = XHCI_TRB_TYPE_NORMAL;
2160         }
2161
2162         if (x != xfer->nframes) {
2163                 /* set up page_cache pointer */
2164                 temp.pc = xfer->frbuffers + x;
2165                 /* set endpoint direction */
2166                 temp.direction = UE_GET_DIR(xfer->endpointno);
2167         }
2168
2169         while (x != xfer->nframes) {
2170
2171                 /* DATA0 / DATA1 message */
2172
2173                 temp.len = xfer->frlengths[x];
2174                 temp.step_td = ((xfer->endpointno & UE_DIR_IN) &&
2175                     x != 0 && temp.multishort == 0);
2176
2177                 x++;
2178
2179                 if (x == xfer->nframes) {
2180                         if (xfer->flags_int.control_xfr) {
2181                                 /* no STATUS stage yet, DATA is last */
2182                                 if (xfer->flags_int.control_act)
2183                                         temp.last_frame = 1;
2184                         } else {
2185                                 temp.last_frame = 1;
2186                         }
2187                 }
2188                 if (temp.len == 0) {
2189
2190                         /* make sure that we send an USB packet */
2191
2192                         temp.shortpkt = 0;
2193
2194                         temp.tbc = 0;
2195                         temp.tlbpc = mult - 1;
2196
2197                 } else if (xfer->flags_int.isochronous_xfr) {
2198
2199                         uint8_t tdpc;
2200
2201                         /*
2202                          * Isochronous transfers don't have short
2203                          * packet termination:
2204                          */
2205
2206                         temp.shortpkt = 1;
2207
2208                         /* isochronous transfers have a transfer limit */
2209
2210                         if (temp.len > xfer->max_frame_size)
2211                                 temp.len = xfer->max_frame_size;
2212
2213                         /* compute TD packet count */
2214                         tdpc = howmany(temp.len, xfer->max_packet_size);
2215
2216                         temp.tbc = howmany(tdpc, mult) - 1;
2217                         temp.tlbpc = (tdpc % mult);
2218
2219                         if (temp.tlbpc == 0)
2220                                 temp.tlbpc = mult - 1;
2221                         else
2222                                 temp.tlbpc--;
2223                 } else {
2224
2225                         /* regular data transfer */
2226
2227                         temp.shortpkt = xfer->flags.force_short_xfer ? 0 : 1;
2228                 }
2229
2230                 xhci_setup_generic_chain_sub(&temp);
2231
2232                 if (xfer->flags_int.isochronous_xfr) {
2233                         temp.offset += xfer->frlengths[x - 1];
2234                         temp.isoc_frame += temp.isoc_delta;
2235                 } else {
2236                         /* get next Page Cache pointer */
2237                         temp.pc = xfer->frbuffers + x;
2238                 }
2239         }
2240
2241         /* check if we should append a status stage */
2242
2243         if (xfer->flags_int.control_xfr &&
2244             !xfer->flags_int.control_act) {
2245
2246                 /*
2247                  * Send a DATA1 message and invert the current
2248                  * endpoint direction.
2249                  */
2250                 if (xhcictlstep || temp.sc->sc_ctlstep) {
2251                         /*
2252                          * Some XHCI controllers will not delay the
2253                          * status stage until the next SOF. Force this
2254                          * behaviour to avoid failed control
2255                          * transfers.
2256                          */
2257                         temp.step_td = (xfer->nframes != 0);
2258                 } else {
2259                         temp.step_td = 0;
2260                 }
2261                 temp.direction = UE_GET_DIR(xfer->endpointno) ^ UE_DIR_IN;
2262                 temp.len = 0;
2263                 temp.pc = NULL;
2264                 temp.shortpkt = 0;
2265                 temp.last_frame = 1;
2266                 temp.trb_type = XHCI_TRB_TYPE_STATUS_STAGE;
2267
2268                 xhci_setup_generic_chain_sub(&temp);
2269         }
2270
2271         td = temp.td;
2272
2273         /* must have at least one frame! */
2274
2275         xfer->td_transfer_last = td;
2276
2277         DPRINTF("first=%p last=%p\n", xfer->td_transfer_first, td);
2278 }
2279
2280 static void
2281 xhci_set_slot_pointer(struct xhci_softc *sc, uint8_t index, uint64_t dev_addr)
2282 {
2283         struct usb_page_search buf_res;
2284         struct xhci_dev_ctx_addr *pdctxa;
2285
2286         usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res);
2287
2288         pdctxa = buf_res.buffer;
2289
2290         DPRINTF("addr[%u]=0x%016llx\n", index, (long long)dev_addr);
2291
2292         pdctxa->qwBaaDevCtxAddr[index] = htole64(dev_addr);
2293
2294         usb_pc_cpu_flush(&sc->sc_hw.ctx_pc);
2295 }
2296
2297 static usb_error_t
2298 xhci_configure_mask(struct usb_device *udev, uint32_t mask, uint8_t drop)
2299 {
2300         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2301         struct usb_page_search buf_inp;
2302         struct xhci_input_dev_ctx *pinp;
2303         uint32_t temp;
2304         uint8_t index;
2305         uint8_t x;
2306
2307         index = udev->controller_slot_id;
2308
2309         usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
2310
2311         pinp = buf_inp.buffer;
2312
2313         if (drop) {
2314                 mask &= XHCI_INCTX_NON_CTRL_MASK;
2315                 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, mask);
2316                 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, 0);
2317         } else {
2318                 /*
2319                  * Some hardware requires that we drop the endpoint
2320                  * context before adding it again:
2321                  */
2322                 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0,
2323                     mask & XHCI_INCTX_NON_CTRL_MASK);
2324
2325                 /* Add new endpoint context */
2326                 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, mask);
2327
2328                 /* find most significant set bit */
2329                 for (x = 31; x != 1; x--) {
2330                         if (mask & (1 << x))
2331                                 break;
2332                 }
2333
2334                 /* adjust */
2335                 x--;
2336
2337                 /* figure out the maximum number of contexts */
2338                 if (x > sc->sc_hw.devs[index].context_num)
2339                         sc->sc_hw.devs[index].context_num = x;
2340                 else
2341                         x = sc->sc_hw.devs[index].context_num;
2342
2343                 /* update number of contexts */
2344                 temp = xhci_ctx_get_le32(sc, &pinp->ctx_slot.dwSctx0);
2345                 temp &= ~XHCI_SCTX_0_CTX_NUM_SET(31);
2346                 temp |= XHCI_SCTX_0_CTX_NUM_SET(x + 1);
2347                 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp);
2348         }
2349         usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc);
2350         return (0);
2351 }
2352
2353 static usb_error_t
2354 xhci_configure_endpoint(struct usb_device *udev,
2355     struct usb_endpoint_descriptor *edesc, struct xhci_endpoint_ext *pepext,
2356     uint16_t interval, uint8_t max_packet_count,
2357     uint8_t mult, uint8_t fps_shift, uint16_t max_packet_size,
2358     uint16_t max_frame_size, uint8_t ep_mode)
2359 {
2360         struct usb_page_search buf_inp;
2361         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2362         struct xhci_input_dev_ctx *pinp;
2363         uint64_t ring_addr = pepext->physaddr;
2364         uint32_t temp;
2365         uint8_t index;
2366         uint8_t epno;
2367         uint8_t type;
2368
2369         index = udev->controller_slot_id;
2370
2371         usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
2372
2373         pinp = buf_inp.buffer;
2374
2375         epno = edesc->bEndpointAddress;
2376         type = edesc->bmAttributes & UE_XFERTYPE;
2377
2378         if (type == UE_CONTROL)
2379                 epno |= UE_DIR_IN;
2380
2381         epno = XHCI_EPNO2EPID(epno);
2382
2383         if (epno == 0)
2384                 return (USB_ERR_NO_PIPE);               /* invalid */
2385
2386         if (max_packet_count == 0)
2387                 return (USB_ERR_BAD_BUFSIZE);
2388
2389         max_packet_count--;
2390
2391         if (mult == 0)
2392                 return (USB_ERR_BAD_BUFSIZE);
2393
2394         /* store endpoint mode */
2395         pepext->trb_ep_mode = ep_mode;
2396         /* store bMaxPacketSize for control endpoints */
2397         pepext->trb_ep_maxp = edesc->wMaxPacketSize[0];
2398         usb_pc_cpu_flush(pepext->page_cache);
2399
2400         if (ep_mode == USB_EP_MODE_STREAMS) {
2401                 temp = XHCI_EPCTX_0_EPSTATE_SET(0) |
2402                     XHCI_EPCTX_0_MAXP_STREAMS_SET(XHCI_MAX_STREAMS_LOG - 1) |
2403                     XHCI_EPCTX_0_LSA_SET(1);
2404
2405                 ring_addr += sizeof(struct xhci_trb) *
2406                     XHCI_MAX_TRANSFERS * XHCI_MAX_STREAMS;
2407         } else {
2408                 temp = XHCI_EPCTX_0_EPSTATE_SET(0) |
2409                     XHCI_EPCTX_0_MAXP_STREAMS_SET(0) |
2410                     XHCI_EPCTX_0_LSA_SET(0);
2411
2412                 ring_addr |= XHCI_EPCTX_2_DCS_SET(1);
2413         }
2414
2415         switch (udev->speed) {
2416         case USB_SPEED_FULL:
2417         case USB_SPEED_LOW:
2418                 /* 1ms -> 125us */
2419                 fps_shift += 3;
2420                 break;
2421         default:
2422                 break;
2423         }
2424
2425         switch (type) {
2426         case UE_INTERRUPT:
2427                 if (fps_shift > 3)
2428                         fps_shift--;
2429                 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift);
2430                 break;
2431         case UE_ISOCHRONOUS:
2432                 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift);
2433
2434                 switch (udev->speed) {
2435                 case USB_SPEED_SUPER:
2436                         if (mult > 3)
2437                                 mult = 3;
2438                         temp |= XHCI_EPCTX_0_MULT_SET(mult - 1);
2439                         max_packet_count /= mult;
2440                         break;
2441                 default:
2442                         break;
2443                 }
2444                 break;
2445         default:
2446                 break;
2447         }
2448
2449         xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx0, temp);
2450
2451         temp =
2452             XHCI_EPCTX_1_HID_SET(0) |
2453             XHCI_EPCTX_1_MAXB_SET(max_packet_count) |
2454             XHCI_EPCTX_1_MAXP_SIZE_SET(max_packet_size);
2455
2456         /*
2457          * Always enable the "three strikes and you are gone" feature
2458          * except for ISOCHRONOUS endpoints. This is suggested by
2459          * section 4.3.3 in the XHCI specification about device slot
2460          * initialisation.
2461          */
2462         if (type != UE_ISOCHRONOUS)
2463                 temp |= XHCI_EPCTX_1_CERR_SET(3);
2464
2465         switch (type) {
2466         case UE_CONTROL:
2467                 temp |= XHCI_EPCTX_1_EPTYPE_SET(4);
2468                 break;
2469         case UE_ISOCHRONOUS:
2470                 temp |= XHCI_EPCTX_1_EPTYPE_SET(1);
2471                 break;
2472         case UE_BULK:
2473                 temp |= XHCI_EPCTX_1_EPTYPE_SET(2);
2474                 break;
2475         default:
2476                 temp |= XHCI_EPCTX_1_EPTYPE_SET(3);
2477                 break;
2478         }
2479
2480         /* check for IN direction */
2481         if (epno & 1)
2482                 temp |= XHCI_EPCTX_1_EPTYPE_SET(4);
2483
2484         xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx1, temp);
2485         xhci_ctx_set_le64(sc, &pinp->ctx_ep[epno - 1].qwEpCtx2, ring_addr);
2486
2487         switch (edesc->bmAttributes & UE_XFERTYPE) {
2488         case UE_INTERRUPT:
2489         case UE_ISOCHRONOUS:
2490                 temp = XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(max_frame_size) |
2491                     XHCI_EPCTX_4_AVG_TRB_LEN_SET(MIN(XHCI_PAGE_SIZE,
2492                     max_frame_size));
2493                 break;
2494         case UE_CONTROL:
2495                 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8);
2496                 break;
2497         default:
2498                 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(XHCI_PAGE_SIZE);
2499                 break;
2500         }
2501
2502         xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx4, temp);
2503
2504 #ifdef USB_DEBUG
2505         xhci_dump_endpoint(sc, &pinp->ctx_ep[epno - 1]);
2506 #endif
2507         usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc);
2508
2509         return (0);             /* success */
2510 }
2511
2512 static usb_error_t
2513 xhci_configure_endpoint_by_xfer(struct usb_xfer *xfer)
2514 {
2515         struct xhci_endpoint_ext *pepext;
2516         struct usb_endpoint_ss_comp_descriptor *ecomp;
2517         usb_stream_t x;
2518
2519         pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2520             xfer->endpoint->edesc);
2521
2522         ecomp = xfer->endpoint->ecomp;
2523
2524         for (x = 0; x != XHCI_MAX_STREAMS; x++) {
2525                 uint64_t temp;
2526
2527                 /* halt any transfers */
2528                 pepext->trb[x * XHCI_MAX_TRANSFERS].dwTrb3 = 0;
2529
2530                 /* compute start of TRB ring for stream "x" */
2531                 temp = pepext->physaddr +
2532                     (x * XHCI_MAX_TRANSFERS * sizeof(struct xhci_trb)) +
2533                     XHCI_SCTX_0_SCT_SEC_TR_RING;
2534
2535                 /* make tree structure */
2536                 pepext->trb[(XHCI_MAX_TRANSFERS *
2537                     XHCI_MAX_STREAMS) + x].qwTrb0 = htole64(temp);
2538
2539                 /* reserved fields */
2540                 pepext->trb[(XHCI_MAX_TRANSFERS *
2541                     XHCI_MAX_STREAMS) + x].dwTrb2 = 0;
2542                 pepext->trb[(XHCI_MAX_TRANSFERS *
2543                     XHCI_MAX_STREAMS) + x].dwTrb3 = 0;
2544         }
2545         usb_pc_cpu_flush(pepext->page_cache);
2546
2547         return (xhci_configure_endpoint(xfer->xroot->udev,
2548             xfer->endpoint->edesc, pepext,
2549             xfer->interval, xfer->max_packet_count,
2550             (ecomp != NULL) ? UE_GET_SS_ISO_MULT(ecomp->bmAttributes) + 1 : 1,
2551             usbd_xfer_get_fps_shift(xfer), xfer->max_packet_size,
2552             xfer->max_frame_size, xfer->endpoint->ep_mode));
2553 }
2554
2555 static usb_error_t
2556 xhci_configure_device(struct usb_device *udev)
2557 {
2558         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2559         struct usb_page_search buf_inp;
2560         struct usb_page_cache *pcinp;
2561         struct xhci_input_dev_ctx *pinp;
2562         struct usb_device *hubdev;
2563         uint32_t temp;
2564         uint32_t route;
2565         uint32_t rh_port;
2566         uint8_t is_hub;
2567         uint8_t index;
2568         uint8_t depth;
2569
2570         index = udev->controller_slot_id;
2571
2572         DPRINTF("index=%u\n", index);
2573
2574         pcinp = &sc->sc_hw.devs[index].input_pc;
2575
2576         usbd_get_page(pcinp, 0, &buf_inp);
2577
2578         pinp = buf_inp.buffer;
2579
2580         rh_port = 0;
2581         route = 0;
2582
2583         /* figure out route string and root HUB port number */
2584
2585         for (hubdev = udev; hubdev != NULL; hubdev = hubdev->parent_hub) {
2586
2587                 if (hubdev->parent_hub == NULL)
2588                         break;
2589
2590                 depth = hubdev->parent_hub->depth;
2591
2592                 /*
2593                  * NOTE: HS/FS/LS devices and the SS root HUB can have
2594                  * more than 15 ports
2595                  */
2596
2597                 rh_port = hubdev->port_no;
2598
2599                 if (depth == 0)
2600                         break;
2601
2602                 if (rh_port > 15)
2603                         rh_port = 15;
2604
2605                 if (depth < 6)
2606                         route |= rh_port << (4 * (depth - 1));
2607         }
2608
2609         DPRINTF("Route=0x%08x\n", route);
2610
2611         temp = XHCI_SCTX_0_ROUTE_SET(route) |
2612             XHCI_SCTX_0_CTX_NUM_SET(
2613             sc->sc_hw.devs[index].context_num + 1);
2614
2615         switch (udev->speed) {
2616         case USB_SPEED_LOW:
2617                 temp |= XHCI_SCTX_0_SPEED_SET(2);
2618                 if (udev->parent_hs_hub != NULL &&
2619                     udev->parent_hs_hub->ddesc.bDeviceProtocol ==
2620                     UDPROTO_HSHUBMTT) {
2621                         DPRINTF("Device inherits MTT\n");
2622                         temp |= XHCI_SCTX_0_MTT_SET(1);
2623                 }
2624                 break;
2625         case USB_SPEED_HIGH:
2626                 temp |= XHCI_SCTX_0_SPEED_SET(3);
2627                 if (sc->sc_hw.devs[index].nports != 0 &&
2628                     udev->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT) {
2629                         DPRINTF("HUB supports MTT\n");
2630                         temp |= XHCI_SCTX_0_MTT_SET(1);
2631                 }
2632                 break;
2633         case USB_SPEED_FULL:
2634                 temp |= XHCI_SCTX_0_SPEED_SET(1);
2635                 if (udev->parent_hs_hub != NULL &&
2636                     udev->parent_hs_hub->ddesc.bDeviceProtocol ==
2637                     UDPROTO_HSHUBMTT) {
2638                         DPRINTF("Device inherits MTT\n");
2639                         temp |= XHCI_SCTX_0_MTT_SET(1);
2640                 }
2641                 break;
2642         default:
2643                 temp |= XHCI_SCTX_0_SPEED_SET(4);
2644                 break;
2645         }
2646
2647         is_hub = sc->sc_hw.devs[index].nports != 0 &&
2648             (udev->speed == USB_SPEED_SUPER ||
2649             udev->speed == USB_SPEED_HIGH);
2650
2651         if (is_hub)
2652                 temp |= XHCI_SCTX_0_HUB_SET(1);
2653
2654         xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp);
2655
2656         temp = XHCI_SCTX_1_RH_PORT_SET(rh_port);
2657
2658         if (is_hub) {
2659                 temp |= XHCI_SCTX_1_NUM_PORTS_SET(
2660                     sc->sc_hw.devs[index].nports);
2661         }
2662
2663         switch (udev->speed) {
2664         case USB_SPEED_SUPER:
2665                 switch (sc->sc_hw.devs[index].state) {
2666                 case XHCI_ST_ADDRESSED:
2667                 case XHCI_ST_CONFIGURED:
2668                         /* enable power save */
2669                         temp |= XHCI_SCTX_1_MAX_EL_SET(sc->sc_exit_lat_max);
2670                         break;
2671                 default:
2672                         /* disable power save */
2673                         break;
2674                 }
2675                 break;
2676         default:
2677                 break;
2678         }
2679
2680         xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx1, temp);
2681
2682         temp = XHCI_SCTX_2_IRQ_TARGET_SET(0);
2683
2684         if (is_hub) {
2685                 temp |= XHCI_SCTX_2_TT_THINK_TIME_SET(
2686                     sc->sc_hw.devs[index].tt);
2687         }
2688
2689         hubdev = udev->parent_hs_hub;
2690
2691         /* check if we should activate the transaction translator */
2692         switch (udev->speed) {
2693         case USB_SPEED_FULL:
2694         case USB_SPEED_LOW:
2695                 if (hubdev != NULL) {
2696                         temp |= XHCI_SCTX_2_TT_HUB_SID_SET(
2697                             hubdev->controller_slot_id);
2698                         temp |= XHCI_SCTX_2_TT_PORT_NUM_SET(
2699                             udev->hs_port_no);
2700                 }
2701                 break;
2702         default:
2703                 break;
2704         }
2705
2706         xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx2, temp);
2707
2708         /*
2709          * These fields should be initialized to zero, according to
2710          * XHCI section 6.2.2 - slot context:
2711          */
2712         temp = XHCI_SCTX_3_DEV_ADDR_SET(0) |
2713             XHCI_SCTX_3_SLOT_STATE_SET(0);
2714
2715         xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx3, temp);
2716
2717 #ifdef USB_DEBUG
2718         xhci_dump_device(sc, &pinp->ctx_slot);
2719 #endif
2720         usb_pc_cpu_flush(pcinp);
2721
2722         return (0);             /* success */
2723 }
2724
2725 static usb_error_t
2726 xhci_alloc_device_ext(struct usb_device *udev)
2727 {
2728         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2729         struct usb_page_search buf_dev;
2730         struct usb_page_search buf_ep;
2731         struct xhci_trb *trb;
2732         struct usb_page_cache *pc;
2733         struct usb_page *pg;
2734         uint64_t addr;
2735         uint8_t index;
2736         uint8_t i;
2737
2738         index = udev->controller_slot_id;
2739
2740         pc = &sc->sc_hw.devs[index].device_pc;
2741         pg = &sc->sc_hw.devs[index].device_pg;
2742
2743         /* need to initialize the page cache */
2744         pc->tag_parent = sc->sc_bus.dma_parent_tag;
2745
2746         if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ?
2747             (2 * sizeof(struct xhci_dev_ctx)) :
2748             sizeof(struct xhci_dev_ctx), XHCI_PAGE_SIZE))
2749                 goto error;
2750
2751         usbd_get_page(pc, 0, &buf_dev);
2752
2753         pc = &sc->sc_hw.devs[index].input_pc;
2754         pg = &sc->sc_hw.devs[index].input_pg;
2755
2756         /* need to initialize the page cache */
2757         pc->tag_parent = sc->sc_bus.dma_parent_tag;
2758
2759         if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ?
2760             (2 * sizeof(struct xhci_input_dev_ctx)) :
2761             sizeof(struct xhci_input_dev_ctx), XHCI_PAGE_SIZE)) {
2762                 goto error;
2763         }
2764
2765         /* initialize all endpoint LINK TRBs */
2766
2767         for (i = 0; i != XHCI_MAX_ENDPOINTS; i++) {
2768
2769                 pc = &sc->sc_hw.devs[index].endpoint_pc[i];
2770                 pg = &sc->sc_hw.devs[index].endpoint_pg[i];
2771
2772                 /* need to initialize the page cache */
2773                 pc->tag_parent = sc->sc_bus.dma_parent_tag;
2774
2775                 if (usb_pc_alloc_mem(pc, pg,
2776                     sizeof(struct xhci_dev_endpoint_trbs), XHCI_TRB_ALIGN)) {
2777                         goto error;
2778                 }
2779
2780                 /* lookup endpoint TRB ring */
2781                 usbd_get_page(pc, 0, &buf_ep);
2782
2783                 /* get TRB pointer */
2784                 trb = buf_ep.buffer;
2785                 trb += XHCI_MAX_TRANSFERS - 1;
2786
2787                 /* get TRB start address */
2788                 addr = buf_ep.physaddr;
2789
2790                 /* create LINK TRB */
2791                 trb->qwTrb0 = htole64(addr);
2792                 trb->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2793                 trb->dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT |
2794                     XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2795
2796                 usb_pc_cpu_flush(pc);
2797         }
2798
2799         xhci_set_slot_pointer(sc, index, buf_dev.physaddr);
2800
2801         return (0);
2802
2803 error:
2804         xhci_free_device_ext(udev);
2805
2806         return (USB_ERR_NOMEM);
2807 }
2808
2809 static void
2810 xhci_free_device_ext(struct usb_device *udev)
2811 {
2812         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2813         uint8_t index;
2814         uint8_t i;
2815
2816         index = udev->controller_slot_id;
2817         xhci_set_slot_pointer(sc, index, 0);
2818
2819         usb_pc_free_mem(&sc->sc_hw.devs[index].device_pc);
2820         usb_pc_free_mem(&sc->sc_hw.devs[index].input_pc);
2821         for (i = 0; i != XHCI_MAX_ENDPOINTS; i++)
2822                 usb_pc_free_mem(&sc->sc_hw.devs[index].endpoint_pc[i]);
2823 }
2824
2825 static struct xhci_endpoint_ext *
2826 xhci_get_endpoint_ext(struct usb_device *udev, struct usb_endpoint_descriptor *edesc)
2827 {
2828         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2829         struct xhci_endpoint_ext *pepext;
2830         struct usb_page_cache *pc;
2831         struct usb_page_search buf_ep;
2832         uint8_t epno;
2833         uint8_t index;
2834
2835         epno = edesc->bEndpointAddress;
2836         if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL)
2837                 epno |= UE_DIR_IN;
2838
2839         epno = XHCI_EPNO2EPID(epno);
2840
2841         index = udev->controller_slot_id;
2842
2843         pc = &sc->sc_hw.devs[index].endpoint_pc[epno];
2844
2845         usbd_get_page(pc, 0, &buf_ep);
2846
2847         pepext = &sc->sc_hw.devs[index].endp[epno];
2848         pepext->page_cache = pc;
2849         pepext->trb = buf_ep.buffer;
2850         pepext->physaddr = buf_ep.physaddr;
2851
2852         return (pepext);
2853 }
2854
2855 static void
2856 xhci_endpoint_doorbell(struct usb_xfer *xfer)
2857 {
2858         struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
2859         uint8_t epno;
2860         uint8_t index;
2861
2862         epno = xfer->endpointno;
2863         if (xfer->flags_int.control_xfr)
2864                 epno |= UE_DIR_IN;
2865
2866         epno = XHCI_EPNO2EPID(epno);
2867         index = xfer->xroot->udev->controller_slot_id;
2868
2869         if (xfer->xroot->udev->flags.self_suspended == 0) {
2870                 XWRITE4(sc, door, XHCI_DOORBELL(index),
2871                     epno | XHCI_DB_SID_SET(xfer->stream_id));
2872         }
2873 }
2874
2875 static void
2876 xhci_transfer_remove(struct usb_xfer *xfer, usb_error_t error)
2877 {
2878         struct xhci_endpoint_ext *pepext;
2879
2880         if (xfer->flags_int.bandwidth_reclaimed) {
2881                 xfer->flags_int.bandwidth_reclaimed = 0;
2882
2883                 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2884                     xfer->endpoint->edesc);
2885
2886                 pepext->trb_used[xfer->stream_id]--;
2887
2888                 pepext->xfer[xfer->qh_pos] = NULL;
2889
2890                 if (error && pepext->trb_running != 0) {
2891                         pepext->trb_halted = 1;
2892                         pepext->trb_running = 0;
2893                 }
2894         }
2895 }
2896
2897 static usb_error_t
2898 xhci_transfer_insert(struct usb_xfer *xfer)
2899 {
2900         struct xhci_td *td_first;
2901         struct xhci_td *td_last;
2902         struct xhci_trb *trb_link;
2903         struct xhci_endpoint_ext *pepext;
2904         uint64_t addr;
2905         usb_stream_t id;
2906         uint8_t i;
2907         uint8_t inext;
2908         uint8_t trb_limit;
2909
2910         DPRINTFN(8, "\n");
2911
2912         id = xfer->stream_id;
2913
2914         /* check if already inserted */
2915         if (xfer->flags_int.bandwidth_reclaimed) {
2916                 DPRINTFN(8, "Already in schedule\n");
2917                 return (0);
2918         }
2919
2920         pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2921             xfer->endpoint->edesc);
2922
2923         td_first = xfer->td_transfer_first;
2924         td_last = xfer->td_transfer_last;
2925         addr = pepext->physaddr;
2926
2927         switch (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) {
2928         case UE_CONTROL:
2929         case UE_INTERRUPT:
2930                 /* single buffered */
2931                 trb_limit = 1;
2932                 break;
2933         default:
2934                 /* multi buffered */
2935                 trb_limit = (XHCI_MAX_TRANSFERS - 2);
2936                 break;
2937         }
2938
2939         if (pepext->trb_used[id] >= trb_limit) {
2940                 DPRINTFN(8, "Too many TDs queued.\n");
2941                 return (USB_ERR_NOMEM);
2942         }
2943
2944         /* check if bMaxPacketSize changed */
2945         if (xfer->flags_int.control_xfr != 0 &&
2946             pepext->trb_ep_maxp != xfer->endpoint->edesc->wMaxPacketSize[0]) {
2947
2948                 DPRINTFN(8, "Reconfigure control endpoint\n");
2949
2950                 /* force driver to reconfigure endpoint */
2951                 pepext->trb_halted = 1;
2952                 pepext->trb_running = 0;
2953         }
2954
2955         /* check for stopped condition, after putting transfer on interrupt queue */
2956         if (pepext->trb_running == 0) {
2957                 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
2958
2959                 DPRINTFN(8, "Not running\n");
2960
2961                 /* start configuration */
2962                 (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus),
2963                     &sc->sc_config_msg[0], &sc->sc_config_msg[1]);
2964                 return (0);
2965         }
2966
2967         pepext->trb_used[id]++;
2968
2969         /* get current TRB index */
2970         i = pepext->trb_index[id];
2971
2972         /* get next TRB index */
2973         inext = (i + 1);
2974
2975         /* the last entry of the ring is a hardcoded link TRB */
2976         if (inext >= (XHCI_MAX_TRANSFERS - 1))
2977                 inext = 0;
2978
2979         /* store next TRB index, before stream ID offset is added */
2980         pepext->trb_index[id] = inext;
2981
2982         /* offset for stream */
2983         i += id * XHCI_MAX_TRANSFERS;
2984         inext += id * XHCI_MAX_TRANSFERS;
2985
2986         /* compute terminating return address */
2987         addr += (inext * sizeof(struct xhci_trb));
2988
2989         /* compute link TRB pointer */
2990         trb_link = td_last->td_trb + td_last->ntrb;
2991
2992         /* update next pointer of last link TRB */
2993         trb_link->qwTrb0 = htole64(addr);
2994         trb_link->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2995         trb_link->dwTrb3 = htole32(XHCI_TRB_3_IOC_BIT |
2996             XHCI_TRB_3_CYCLE_BIT |
2997             XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2998
2999 #ifdef USB_DEBUG
3000         xhci_dump_trb(&td_last->td_trb[td_last->ntrb]);
3001 #endif
3002         usb_pc_cpu_flush(td_last->page_cache);
3003
3004         /* write ahead chain end marker */
3005
3006         pepext->trb[inext].qwTrb0 = 0;
3007         pepext->trb[inext].dwTrb2 = 0;
3008         pepext->trb[inext].dwTrb3 = 0;
3009
3010         /* update next pointer of link TRB */
3011
3012         pepext->trb[i].qwTrb0 = htole64((uint64_t)td_first->td_self);
3013         pepext->trb[i].dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
3014
3015 #ifdef USB_DEBUG
3016         xhci_dump_trb(&pepext->trb[i]);
3017 #endif
3018         usb_pc_cpu_flush(pepext->page_cache);
3019
3020         /* toggle cycle bit which activates the transfer chain */
3021
3022         pepext->trb[i].dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT |
3023             XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
3024
3025         usb_pc_cpu_flush(pepext->page_cache);
3026
3027         DPRINTF("qh_pos = %u\n", i);
3028
3029         pepext->xfer[i] = xfer;
3030
3031         xfer->qh_pos = i;
3032
3033         xfer->flags_int.bandwidth_reclaimed = 1;
3034
3035         xhci_endpoint_doorbell(xfer);
3036
3037         return (0);
3038 }
3039
3040 static void
3041 xhci_root_intr(struct xhci_softc *sc)
3042 {
3043         uint16_t i;
3044
3045         USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
3046
3047         /* clear any old interrupt data */
3048         memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata));
3049
3050         for (i = 1; i <= sc->sc_noport; i++) {
3051                 /* pick out CHANGE bits from the status register */
3052                 if (XREAD4(sc, oper, XHCI_PORTSC(i)) & (
3053                     XHCI_PS_CSC | XHCI_PS_PEC |
3054                     XHCI_PS_OCC | XHCI_PS_WRC |
3055                     XHCI_PS_PRC | XHCI_PS_PLC |
3056                     XHCI_PS_CEC)) {
3057                         sc->sc_hub_idata[i / 8] |= 1 << (i % 8);
3058                         DPRINTF("port %d changed\n", i);
3059                 }
3060         }
3061         uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
3062             sizeof(sc->sc_hub_idata));
3063 }
3064
3065 /*------------------------------------------------------------------------*
3066  *      xhci_device_done - XHCI done handler
3067  *
3068  * NOTE: This function can be called two times in a row on
3069  * the same USB transfer. From close and from interrupt.
3070  *------------------------------------------------------------------------*/
3071 static void
3072 xhci_device_done(struct usb_xfer *xfer, usb_error_t error)
3073 {
3074         DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n",
3075             xfer, xfer->endpoint, error);
3076
3077         /* remove transfer from HW queue */
3078         xhci_transfer_remove(xfer, error);
3079
3080         /* dequeue transfer and start next transfer */
3081         usbd_transfer_done(xfer, error);
3082 }
3083
3084 /*------------------------------------------------------------------------*
3085  * XHCI data transfer support (generic type)
3086  *------------------------------------------------------------------------*/
3087 static void
3088 xhci_device_generic_open(struct usb_xfer *xfer)
3089 {
3090         if (xfer->flags_int.isochronous_xfr) {
3091                 switch (xfer->xroot->udev->speed) {
3092                 case USB_SPEED_FULL:
3093                         break;
3094                 default:
3095                         usb_hs_bandwidth_alloc(xfer);
3096                         break;
3097                 }
3098         }
3099 }
3100
3101 static void
3102 xhci_device_generic_close(struct usb_xfer *xfer)
3103 {
3104         DPRINTF("\n");
3105
3106         xhci_device_done(xfer, USB_ERR_CANCELLED);
3107
3108         if (xfer->flags_int.isochronous_xfr) {
3109                 switch (xfer->xroot->udev->speed) {
3110                 case USB_SPEED_FULL:
3111                         break;
3112                 default:
3113                         usb_hs_bandwidth_free(xfer);
3114                         break;
3115                 }
3116         }
3117 }
3118
3119 static void
3120 xhci_device_generic_multi_enter(struct usb_endpoint *ep,
3121     usb_stream_t stream_id, struct usb_xfer *enter_xfer)
3122 {
3123         struct usb_xfer *xfer;
3124
3125         /* check if there is a current transfer */
3126         xfer = ep->endpoint_q[stream_id].curr;
3127         if (xfer == NULL)
3128                 return;
3129
3130         /*
3131          * Check if the current transfer is started and then pickup
3132          * the next one, if any. Else wait for next start event due to
3133          * block on failure feature.
3134          */
3135         if (!xfer->flags_int.bandwidth_reclaimed)
3136                 return;
3137
3138         xfer = TAILQ_FIRST(&ep->endpoint_q[stream_id].head);
3139         if (xfer == NULL) {
3140                 /*
3141                  * In case of enter we have to consider that the
3142                  * transfer is queued by the USB core after the enter
3143                  * method is called.
3144                  */
3145                 xfer = enter_xfer;
3146
3147                 if (xfer == NULL)
3148                         return;
3149         }
3150
3151         /* try to multi buffer */
3152         xhci_transfer_insert(xfer);
3153 }
3154
3155 static void
3156 xhci_device_generic_enter(struct usb_xfer *xfer)
3157 {
3158         DPRINTF("\n");
3159
3160         /* set up TD's and QH */
3161         xhci_setup_generic_chain(xfer);
3162
3163         xhci_device_generic_multi_enter(xfer->endpoint,
3164             xfer->stream_id, xfer);
3165 }
3166
3167 static void
3168 xhci_device_generic_start(struct usb_xfer *xfer)
3169 {
3170         DPRINTF("\n");
3171
3172         /* try to insert xfer on HW queue */
3173         xhci_transfer_insert(xfer);
3174
3175         /* try to multi buffer */
3176         xhci_device_generic_multi_enter(xfer->endpoint,
3177             xfer->stream_id, NULL);
3178
3179         /* add transfer last on interrupt queue */
3180         usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
3181
3182         /* start timeout, if any */
3183         if (xfer->timeout != 0)
3184                 usbd_transfer_timeout_ms(xfer, &xhci_timeout, xfer->timeout);
3185 }
3186
3187 static const struct usb_pipe_methods xhci_device_generic_methods =
3188 {
3189         .open = xhci_device_generic_open,
3190         .close = xhci_device_generic_close,
3191         .enter = xhci_device_generic_enter,
3192         .start = xhci_device_generic_start,
3193 };
3194
3195 /*------------------------------------------------------------------------*
3196  * xhci root HUB support
3197  *------------------------------------------------------------------------*
3198  * Simulate a hardware HUB by handling all the necessary requests.
3199  *------------------------------------------------------------------------*/
3200
3201 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) }
3202
3203 static const
3204 struct usb_device_descriptor xhci_devd =
3205 {
3206         .bLength = sizeof(xhci_devd),
3207         .bDescriptorType = UDESC_DEVICE,        /* type */
3208         HSETW(.bcdUSB, 0x0300),                 /* USB version */
3209         .bDeviceClass = UDCLASS_HUB,            /* class */
3210         .bDeviceSubClass = UDSUBCLASS_HUB,      /* subclass */
3211         .bDeviceProtocol = UDPROTO_SSHUB,       /* protocol */
3212         .bMaxPacketSize = 9,                    /* max packet size */
3213         HSETW(.idVendor, 0x0000),               /* vendor */
3214         HSETW(.idProduct, 0x0000),              /* product */
3215         HSETW(.bcdDevice, 0x0100),              /* device version */
3216         .iManufacturer = 1,
3217         .iProduct = 2,
3218         .iSerialNumber = 0,
3219         .bNumConfigurations = 1,                /* # of configurations */
3220 };
3221
3222 static const
3223 struct xhci_bos_desc xhci_bosd = {
3224         .bosd = {
3225                 .bLength = sizeof(xhci_bosd.bosd),
3226                 .bDescriptorType = UDESC_BOS,
3227                 HSETW(.wTotalLength, sizeof(xhci_bosd)),
3228                 .bNumDeviceCaps = 3,
3229         },
3230         .usb2extd = {
3231                 .bLength = sizeof(xhci_bosd.usb2extd),
3232                 .bDescriptorType = 1,
3233                 .bDevCapabilityType = 2,
3234                 .bmAttributes[0] = 2,
3235         },
3236         .usbdcd = {
3237                 .bLength = sizeof(xhci_bosd.usbdcd),
3238                 .bDescriptorType = UDESC_DEVICE_CAPABILITY,
3239                 .bDevCapabilityType = 3,
3240                 .bmAttributes = 0, /* XXX */
3241                 HSETW(.wSpeedsSupported, 0x000C),
3242                 .bFunctionalitySupport = 8,
3243                 .bU1DevExitLat = 255,   /* dummy - not used */
3244                 .wU2DevExitLat = { 0x00, 0x08 },
3245         },
3246         .cidd = {
3247                 .bLength = sizeof(xhci_bosd.cidd),
3248                 .bDescriptorType = 1,
3249                 .bDevCapabilityType = 4,
3250                 .bReserved = 0,
3251                 .bContainerID = 0, /* XXX */
3252         },
3253 };
3254
3255 static const
3256 struct xhci_config_desc xhci_confd = {
3257         .confd = {
3258                 .bLength = sizeof(xhci_confd.confd),
3259                 .bDescriptorType = UDESC_CONFIG,
3260                 .wTotalLength[0] = sizeof(xhci_confd),
3261                 .bNumInterface = 1,
3262                 .bConfigurationValue = 1,
3263                 .iConfiguration = 0,
3264                 .bmAttributes = UC_SELF_POWERED,
3265                 .bMaxPower = 0          /* max power */
3266         },
3267         .ifcd = {
3268                 .bLength = sizeof(xhci_confd.ifcd),
3269                 .bDescriptorType = UDESC_INTERFACE,
3270                 .bNumEndpoints = 1,
3271                 .bInterfaceClass = UICLASS_HUB,
3272                 .bInterfaceSubClass = UISUBCLASS_HUB,
3273                 .bInterfaceProtocol = 0,
3274         },
3275         .endpd = {
3276                 .bLength = sizeof(xhci_confd.endpd),
3277                 .bDescriptorType = UDESC_ENDPOINT,
3278                 .bEndpointAddress = UE_DIR_IN | XHCI_INTR_ENDPT,
3279                 .bmAttributes = UE_INTERRUPT,
3280                 .wMaxPacketSize[0] = 2,         /* max 15 ports */
3281                 .bInterval = 255,
3282         },
3283         .endpcd = {
3284                 .bLength = sizeof(xhci_confd.endpcd),
3285                 .bDescriptorType = UDESC_ENDPOINT_SS_COMP,
3286                 .bMaxBurst = 0,
3287                 .bmAttributes = 0,
3288         },
3289 };
3290
3291 static const
3292 struct usb_hub_ss_descriptor xhci_hubd = {
3293         .bLength = sizeof(xhci_hubd),
3294         .bDescriptorType = UDESC_SS_HUB,
3295 };
3296
3297 static usb_error_t
3298 xhci_roothub_exec(struct usb_device *udev,
3299     struct usb_device_request *req, const void **pptr, uint16_t *plength)
3300 {
3301         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3302         const char *str_ptr;
3303         const void *ptr;
3304         uint32_t port;
3305         uint32_t v;
3306         uint16_t len;
3307         uint16_t i;
3308         uint16_t value;
3309         uint16_t index;
3310         uint8_t j;
3311         usb_error_t err;
3312
3313         USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
3314
3315         /* buffer reset */
3316         ptr = (const void *)&sc->sc_hub_desc;
3317         len = 0;
3318         err = 0;
3319
3320         value = UGETW(req->wValue);
3321         index = UGETW(req->wIndex);
3322
3323         DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x "
3324             "wValue=0x%04x wIndex=0x%04x\n",
3325             req->bmRequestType, req->bRequest,
3326             UGETW(req->wLength), value, index);
3327
3328 #define C(x,y) ((x) | ((y) << 8))
3329         switch (C(req->bRequest, req->bmRequestType)) {
3330         case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE):
3331         case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE):
3332         case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT):
3333                 /*
3334                  * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops
3335                  * for the integrated root hub.
3336                  */
3337                 break;
3338         case C(UR_GET_CONFIG, UT_READ_DEVICE):
3339                 len = 1;
3340                 sc->sc_hub_desc.temp[0] = sc->sc_conf;
3341                 break;
3342         case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
3343                 switch (value >> 8) {
3344                 case UDESC_DEVICE:
3345                         if ((value & 0xff) != 0) {
3346                                 err = USB_ERR_IOERROR;
3347                                 goto done;
3348                         }
3349                         len = sizeof(xhci_devd);
3350                         ptr = (const void *)&xhci_devd;
3351                         break;
3352
3353                 case UDESC_BOS:
3354                         if ((value & 0xff) != 0) {
3355                                 err = USB_ERR_IOERROR;
3356                                 goto done;
3357                         }
3358                         len = sizeof(xhci_bosd);
3359                         ptr = (const void *)&xhci_bosd;
3360                         break;
3361
3362                 case UDESC_CONFIG:
3363                         if ((value & 0xff) != 0) {
3364                                 err = USB_ERR_IOERROR;
3365                                 goto done;
3366                         }
3367                         len = sizeof(xhci_confd);
3368                         ptr = (const void *)&xhci_confd;
3369                         break;
3370
3371                 case UDESC_STRING:
3372                         switch (value & 0xff) {
3373                         case 0: /* Language table */
3374                                 str_ptr = "\001";
3375                                 break;
3376
3377                         case 1: /* Vendor */
3378                                 str_ptr = sc->sc_vendor;
3379                                 break;
3380
3381                         case 2: /* Product */
3382                                 str_ptr = "XHCI root HUB";
3383                                 break;
3384
3385                         default:
3386                                 str_ptr = "";
3387                                 break;
3388                         }
3389
3390                         len = usb_make_str_desc(
3391                             sc->sc_hub_desc.temp,
3392                             sizeof(sc->sc_hub_desc.temp),
3393                             str_ptr);
3394                         break;
3395
3396                 default:
3397                         err = USB_ERR_IOERROR;
3398                         goto done;
3399                 }
3400                 break;
3401         case C(UR_GET_INTERFACE, UT_READ_INTERFACE):
3402                 len = 1;
3403                 sc->sc_hub_desc.temp[0] = 0;
3404                 break;
3405         case C(UR_GET_STATUS, UT_READ_DEVICE):
3406                 len = 2;
3407                 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED);
3408                 break;
3409         case C(UR_GET_STATUS, UT_READ_INTERFACE):
3410         case C(UR_GET_STATUS, UT_READ_ENDPOINT):
3411                 len = 2;
3412                 USETW(sc->sc_hub_desc.stat.wStatus, 0);
3413                 break;
3414         case C(UR_SET_ADDRESS, UT_WRITE_DEVICE):
3415                 if (value >= XHCI_MAX_DEVICES) {
3416                         err = USB_ERR_IOERROR;
3417                         goto done;
3418                 }
3419                 break;
3420         case C(UR_SET_CONFIG, UT_WRITE_DEVICE):
3421                 if (value != 0 && value != 1) {
3422                         err = USB_ERR_IOERROR;
3423                         goto done;
3424                 }
3425                 sc->sc_conf = value;
3426                 break;
3427         case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE):
3428                 break;
3429         case C(UR_SET_FEATURE, UT_WRITE_DEVICE):
3430         case C(UR_SET_FEATURE, UT_WRITE_INTERFACE):
3431         case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT):
3432                 err = USB_ERR_IOERROR;
3433                 goto done;
3434         case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE):
3435                 break;
3436         case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT):
3437                 break;
3438                 /* Hub requests */
3439         case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
3440                 break;
3441         case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
3442                 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n");
3443
3444                 if ((index < 1) ||
3445                     (index > sc->sc_noport)) {
3446                         err = USB_ERR_IOERROR;
3447                         goto done;
3448                 }
3449                 port = XHCI_PORTSC(index);
3450
3451                 v = XREAD4(sc, oper, port);
3452                 i = XHCI_PS_PLS_GET(v);
3453                 v &= ~XHCI_PS_CLEAR;
3454
3455                 switch (value) {
3456                 case UHF_C_BH_PORT_RESET:
3457                         XWRITE4(sc, oper, port, v | XHCI_PS_WRC);
3458                         break;
3459                 case UHF_C_PORT_CONFIG_ERROR:
3460                         XWRITE4(sc, oper, port, v | XHCI_PS_CEC);
3461                         break;
3462                 case UHF_C_PORT_SUSPEND:
3463                 case UHF_C_PORT_LINK_STATE:
3464                         XWRITE4(sc, oper, port, v | XHCI_PS_PLC);
3465                         break;
3466                 case UHF_C_PORT_CONNECTION:
3467                         XWRITE4(sc, oper, port, v | XHCI_PS_CSC);
3468                         break;
3469                 case UHF_C_PORT_ENABLE:
3470                         XWRITE4(sc, oper, port, v | XHCI_PS_PEC);
3471                         break;
3472                 case UHF_C_PORT_OVER_CURRENT:
3473                         XWRITE4(sc, oper, port, v | XHCI_PS_OCC);
3474                         break;
3475                 case UHF_C_PORT_RESET:
3476                         XWRITE4(sc, oper, port, v | XHCI_PS_PRC);
3477                         break;
3478                 case UHF_PORT_ENABLE:
3479                         XWRITE4(sc, oper, port, v | XHCI_PS_PED);
3480                         break;
3481                 case UHF_PORT_POWER:
3482                         XWRITE4(sc, oper, port, v & ~XHCI_PS_PP);
3483                         break;
3484                 case UHF_PORT_INDICATOR:
3485                         XWRITE4(sc, oper, port, v & ~XHCI_PS_PIC_SET(3));
3486                         break;
3487                 case UHF_PORT_SUSPEND:
3488
3489                         /* U3 -> U15 */
3490                         if (i == 3) {
3491                                 XWRITE4(sc, oper, port, v |
3492                                     XHCI_PS_PLS_SET(0xF) | XHCI_PS_LWS);
3493                         }
3494
3495                         /* wait 20ms for resume sequence to complete */
3496                         usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50);
3497
3498                         /* U0 */
3499                         XWRITE4(sc, oper, port, v |
3500                             XHCI_PS_PLS_SET(0) | XHCI_PS_LWS);
3501                         break;
3502                 default:
3503                         err = USB_ERR_IOERROR;
3504                         goto done;
3505                 }
3506                 break;
3507
3508         case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
3509                 if ((value & 0xff) != 0) {
3510                         err = USB_ERR_IOERROR;
3511                         goto done;
3512                 }
3513
3514                 v = XREAD4(sc, capa, XHCI_HCSPARAMS0);
3515
3516                 sc->sc_hub_desc.hubd = xhci_hubd;
3517
3518                 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport;
3519
3520                 if (XHCI_HCS0_PPC(v))
3521                         i = UHD_PWR_INDIVIDUAL;
3522                 else
3523                         i = UHD_PWR_GANGED;
3524
3525                 if (XHCI_HCS0_PIND(v))
3526                         i |= UHD_PORT_IND;
3527
3528                 i |= UHD_OC_INDIVIDUAL;
3529
3530                 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i);
3531
3532                 /* see XHCI section 5.4.9: */
3533                 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 10;
3534
3535                 for (j = 1; j <= sc->sc_noport; j++) {
3536
3537                         v = XREAD4(sc, oper, XHCI_PORTSC(j));
3538                         if (v & XHCI_PS_DR) {
3539                                 sc->sc_hub_desc.hubd.
3540                                     DeviceRemovable[j / 8] |= 1U << (j % 8);
3541                         }
3542                 }
3543                 len = sc->sc_hub_desc.hubd.bLength;
3544                 break;
3545
3546         case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
3547                 len = 16;
3548                 memset(sc->sc_hub_desc.temp, 0, 16);
3549                 break;
3550
3551         case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
3552                 DPRINTFN(9, "UR_GET_STATUS i=%d\n", index);
3553
3554                 if ((index < 1) ||
3555                     (index > sc->sc_noport)) {
3556                         err = USB_ERR_IOERROR;
3557                         goto done;
3558                 }
3559
3560                 v = XREAD4(sc, oper, XHCI_PORTSC(index));
3561
3562                 DPRINTFN(9, "port status=0x%08x\n", v);
3563
3564                 i = UPS_PORT_LINK_STATE_SET(XHCI_PS_PLS_GET(v));
3565
3566                 switch (XHCI_PS_SPEED_GET(v)) {
3567                 case 3:
3568                         i |= UPS_HIGH_SPEED;
3569                         break;
3570                 case 2:
3571                         i |= UPS_LOW_SPEED;
3572                         break;
3573                 case 1:
3574                         /* FULL speed */
3575                         break;
3576                 default:
3577                         i |= UPS_OTHER_SPEED;
3578                         break;
3579                 }
3580
3581                 if (v & XHCI_PS_CCS)
3582                         i |= UPS_CURRENT_CONNECT_STATUS;
3583                 if (v & XHCI_PS_PED)
3584                         i |= UPS_PORT_ENABLED;
3585                 if (v & XHCI_PS_OCA)
3586                         i |= UPS_OVERCURRENT_INDICATOR;
3587                 if (v & XHCI_PS_PR)
3588                         i |= UPS_RESET;
3589                 if (v & XHCI_PS_PP) {
3590                         /*
3591                          * The USB 3.0 RH is using the
3592                          * USB 2.0's power bit
3593                          */
3594                         i |= UPS_PORT_POWER;
3595                 }
3596                 USETW(sc->sc_hub_desc.ps.wPortStatus, i);
3597
3598                 i = 0;
3599                 if (v & XHCI_PS_CSC)
3600                         i |= UPS_C_CONNECT_STATUS;
3601                 if (v & XHCI_PS_PEC)
3602                         i |= UPS_C_PORT_ENABLED;
3603                 if (v & XHCI_PS_OCC)
3604                         i |= UPS_C_OVERCURRENT_INDICATOR;
3605                 if (v & XHCI_PS_WRC)
3606                         i |= UPS_C_BH_PORT_RESET;
3607                 if (v & XHCI_PS_PRC)
3608                         i |= UPS_C_PORT_RESET;
3609                 if (v & XHCI_PS_PLC)
3610                         i |= UPS_C_PORT_LINK_STATE;
3611                 if (v & XHCI_PS_CEC)
3612                         i |= UPS_C_PORT_CONFIG_ERROR;
3613
3614                 USETW(sc->sc_hub_desc.ps.wPortChange, i);
3615                 len = sizeof(sc->sc_hub_desc.ps);
3616                 break;
3617
3618         case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
3619                 err = USB_ERR_IOERROR;
3620                 goto done;
3621
3622         case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
3623                 break;
3624
3625         case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
3626
3627                 i = index >> 8;
3628                 index &= 0x00FF;
3629
3630                 if ((index < 1) ||
3631                     (index > sc->sc_noport)) {
3632                         err = USB_ERR_IOERROR;
3633                         goto done;
3634                 }
3635
3636                 port = XHCI_PORTSC(index);
3637                 v = XREAD4(sc, oper, port) & ~XHCI_PS_CLEAR;
3638
3639                 switch (value) {
3640                 case UHF_PORT_U1_TIMEOUT:
3641                         if (XHCI_PS_SPEED_GET(v) != 4) {
3642                                 err = USB_ERR_IOERROR;
3643                                 goto done;
3644                         }
3645                         port = XHCI_PORTPMSC(index);
3646                         v = XREAD4(sc, oper, port);
3647                         v &= ~XHCI_PM3_U1TO_SET(0xFF);
3648                         v |= XHCI_PM3_U1TO_SET(i);
3649                         XWRITE4(sc, oper, port, v);
3650                         break;
3651                 case UHF_PORT_U2_TIMEOUT:
3652                         if (XHCI_PS_SPEED_GET(v) != 4) {
3653                                 err = USB_ERR_IOERROR;
3654                                 goto done;
3655                         }
3656                         port = XHCI_PORTPMSC(index);
3657                         v = XREAD4(sc, oper, port);
3658                         v &= ~XHCI_PM3_U2TO_SET(0xFF);
3659                         v |= XHCI_PM3_U2TO_SET(i);
3660                         XWRITE4(sc, oper, port, v);
3661                         break;
3662                 case UHF_BH_PORT_RESET:
3663                         XWRITE4(sc, oper, port, v | XHCI_PS_WPR);
3664                         break;
3665                 case UHF_PORT_LINK_STATE:
3666                         XWRITE4(sc, oper, port, v |
3667                             XHCI_PS_PLS_SET(i) | XHCI_PS_LWS);
3668                         /* 4ms settle time */
3669                         usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250);
3670                         break;
3671                 case UHF_PORT_ENABLE:
3672                         DPRINTFN(3, "set port enable %d\n", index);
3673                         break;
3674                 case UHF_PORT_SUSPEND:
3675                         DPRINTFN(6, "suspend port %u (LPM=%u)\n", index, i);
3676                         j = XHCI_PS_SPEED_GET(v);
3677                         if ((j < 1) || (j > 3)) {
3678                                 /* non-supported speed */
3679                                 err = USB_ERR_IOERROR;
3680                                 goto done;
3681                         }
3682                         XWRITE4(sc, oper, port, v |
3683                             XHCI_PS_PLS_SET(i ? 2 /* LPM */ : 3) | XHCI_PS_LWS);
3684                         break;
3685                 case UHF_PORT_RESET:
3686                         DPRINTFN(6, "reset port %d\n", index);
3687                         XWRITE4(sc, oper, port, v | XHCI_PS_PR);
3688                         break;
3689                 case UHF_PORT_POWER:
3690                         DPRINTFN(3, "set port power %d\n", index);
3691                         XWRITE4(sc, oper, port, v | XHCI_PS_PP);
3692                         break;
3693                 case UHF_PORT_TEST:
3694                         DPRINTFN(3, "set port test %d\n", index);
3695                         break;
3696                 case UHF_PORT_INDICATOR:
3697                         DPRINTFN(3, "set port indicator %d\n", index);
3698
3699                         v &= ~XHCI_PS_PIC_SET(3);
3700                         v |= XHCI_PS_PIC_SET(1);
3701
3702                         XWRITE4(sc, oper, port, v);
3703                         break;
3704                 default:
3705                         err = USB_ERR_IOERROR;
3706                         goto done;
3707                 }
3708                 break;
3709
3710         case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER):
3711         case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER):
3712         case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER):
3713         case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER):
3714                 break;
3715         default:
3716                 err = USB_ERR_IOERROR;
3717                 goto done;
3718         }
3719 done:
3720         *plength = len;
3721         *pptr = ptr;
3722         return (err);
3723 }
3724
3725 static void
3726 xhci_xfer_setup(struct usb_setup_params *parm)
3727 {
3728         struct usb_page_search page_info;
3729         struct usb_page_cache *pc;
3730         struct usb_xfer *xfer;
3731         void *last_obj;
3732         uint32_t ntd;
3733         uint32_t n;
3734
3735         xfer = parm->curr_xfer;
3736
3737         /*
3738          * The proof for the "ntd" formula is illustrated like this:
3739          *
3740          * +------------------------------------+
3741          * |                                    |
3742          * |         |remainder ->              |
3743          * |   +-----+---+                      |
3744          * |   | xxx | x | frm 0                |
3745          * |   +-----+---++                     |
3746          * |   | xxx | xx | frm 1               |
3747          * |   +-----+----+                     |
3748          * |            ...                     |
3749          * +------------------------------------+
3750          *
3751          * "xxx" means a completely full USB transfer descriptor
3752          *
3753          * "x" and "xx" means a short USB packet
3754          *
3755          * For the remainder of an USB transfer modulo
3756          * "max_data_length" we need two USB transfer descriptors.
3757          * One to transfer the remaining data and one to finalise with
3758          * a zero length packet in case the "force_short_xfer" flag is
3759          * set. We only need two USB transfer descriptors in the case
3760          * where the transfer length of the first one is a factor of
3761          * "max_frame_size". The rest of the needed USB transfer
3762          * descriptors is given by the buffer size divided by the
3763          * maximum data payload.
3764          */
3765         parm->hc_max_packet_size = 0x400;
3766         parm->hc_max_packet_count = 16 * 3;
3767         parm->hc_max_frame_size = XHCI_TD_PAYLOAD_MAX;
3768
3769         xfer->flags_int.bdma_enable = 1;
3770
3771         usbd_transfer_setup_sub(parm);
3772
3773         if (xfer->flags_int.isochronous_xfr) {
3774                 ntd = ((1 * xfer->nframes)
3775                     + (xfer->max_data_length / xfer->max_hc_frame_size));
3776         } else if (xfer->flags_int.control_xfr) {
3777                 ntd = ((2 * xfer->nframes) + 1  /* STATUS */
3778                     + (xfer->max_data_length / xfer->max_hc_frame_size));
3779         } else {
3780                 ntd = ((2 * xfer->nframes)
3781                     + (xfer->max_data_length / xfer->max_hc_frame_size));
3782         }
3783
3784 alloc_dma_set:
3785
3786         if (parm->err)
3787                 return;
3788
3789         /*
3790          * Allocate queue heads and transfer descriptors
3791          */
3792         last_obj = NULL;
3793
3794         if (usbd_transfer_setup_sub_malloc(
3795             parm, &pc, sizeof(struct xhci_td),
3796             XHCI_TD_ALIGN, ntd)) {
3797                 parm->err = USB_ERR_NOMEM;
3798                 return;
3799         }
3800         if (parm->buf) {
3801                 for (n = 0; n != ntd; n++) {
3802                         struct xhci_td *td;
3803
3804                         usbd_get_page(pc + n, 0, &page_info);
3805
3806                         td = page_info.buffer;
3807
3808                         /* init TD */
3809                         td->td_self = page_info.physaddr;
3810                         td->obj_next = last_obj;
3811                         td->page_cache = pc + n;
3812
3813                         last_obj = td;
3814
3815                         usb_pc_cpu_flush(pc + n);
3816                 }
3817         }
3818         xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj;
3819
3820         if (!xfer->flags_int.curr_dma_set) {
3821                 xfer->flags_int.curr_dma_set = 1;
3822                 goto alloc_dma_set;
3823         }
3824 }
3825
3826 static usb_error_t
3827 xhci_configure_reset_endpoint(struct usb_xfer *xfer)
3828 {
3829         struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
3830         struct usb_page_search buf_inp;
3831         struct usb_device *udev;
3832         struct xhci_endpoint_ext *pepext;
3833         struct usb_endpoint_descriptor *edesc;
3834         struct usb_page_cache *pcinp;
3835         usb_error_t err;
3836         usb_stream_t stream_id;
3837         uint8_t index;
3838         uint8_t epno;
3839
3840         pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
3841             xfer->endpoint->edesc);
3842
3843         udev = xfer->xroot->udev;
3844         index = udev->controller_slot_id;
3845
3846         pcinp = &sc->sc_hw.devs[index].input_pc;
3847
3848         usbd_get_page(pcinp, 0, &buf_inp);
3849
3850         edesc = xfer->endpoint->edesc;
3851
3852         epno = edesc->bEndpointAddress;
3853         stream_id = xfer->stream_id;
3854
3855         if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL)
3856                 epno |= UE_DIR_IN;
3857
3858         epno = XHCI_EPNO2EPID(epno);
3859
3860         if (epno == 0)
3861                 return (USB_ERR_NO_PIPE);               /* invalid */
3862
3863         XHCI_CMD_LOCK(sc);
3864
3865         /* configure endpoint */
3866
3867         err = xhci_configure_endpoint_by_xfer(xfer);
3868
3869         if (err != 0) {
3870                 XHCI_CMD_UNLOCK(sc);
3871                 return (err);
3872         }
3873
3874         /*
3875          * Get the endpoint into the stopped state according to the
3876          * endpoint context state diagram in the XHCI specification:
3877          */
3878
3879         err = xhci_cmd_stop_ep(sc, 0, epno, index);
3880
3881         if (err != 0)
3882                 DPRINTF("Could not stop endpoint %u\n", epno);
3883
3884         err = xhci_cmd_reset_ep(sc, 0, epno, index);
3885
3886         if (err != 0)
3887                 DPRINTF("Could not reset endpoint %u\n", epno);
3888
3889         err = xhci_cmd_set_tr_dequeue_ptr(sc,
3890             (pepext->physaddr + (stream_id * sizeof(struct xhci_trb) *
3891             XHCI_MAX_TRANSFERS)) | XHCI_EPCTX_2_DCS_SET(1),
3892             stream_id, epno, index);
3893
3894         if (err != 0)
3895                 DPRINTF("Could not set dequeue ptr for endpoint %u\n", epno);
3896
3897         /*
3898          * Get the endpoint into the running state according to the
3899          * endpoint context state diagram in the XHCI specification:
3900          */
3901
3902         xhci_configure_mask(udev, (1U << epno) | 1U, 0);
3903
3904         if (epno > 1)
3905                 err = xhci_cmd_configure_ep(sc, buf_inp.physaddr, 0, index);
3906         else
3907                 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index);
3908
3909         if (err != 0)
3910                 DPRINTF("Could not configure endpoint %u\n", epno);
3911
3912         XHCI_CMD_UNLOCK(sc);
3913
3914         return (0);
3915 }
3916
3917 static void
3918 xhci_xfer_unsetup(struct usb_xfer *xfer)
3919 {
3920         return;
3921 }
3922
3923 static void
3924 xhci_start_dma_delay(struct usb_xfer *xfer)
3925 {
3926         struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
3927
3928         /* put transfer on interrupt queue (again) */
3929         usbd_transfer_enqueue(&sc->sc_bus.intr_q, xfer);
3930
3931         (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus),
3932             &sc->sc_config_msg[0], &sc->sc_config_msg[1]);
3933 }
3934
3935 static void
3936 xhci_configure_msg(struct usb_proc_msg *pm)
3937 {
3938         struct xhci_softc *sc;
3939         struct xhci_endpoint_ext *pepext;
3940         struct usb_xfer *xfer;
3941
3942         sc = XHCI_BUS2SC(((struct usb_bus_msg *)pm)->bus);
3943
3944 restart:
3945         TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3946
3947                 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
3948                     xfer->endpoint->edesc);
3949
3950                 if ((pepext->trb_halted != 0) ||
3951                     (pepext->trb_running == 0)) {
3952
3953                         uint16_t i;
3954
3955                         /* clear halted and running */
3956                         pepext->trb_halted = 0;
3957                         pepext->trb_running = 0;
3958
3959                         /* nuke remaining buffered transfers */
3960
3961                         for (i = 0; i != (XHCI_MAX_TRANSFERS *
3962                             XHCI_MAX_STREAMS); i++) {
3963                                 /*
3964                                  * NOTE: We need to use the timeout
3965                                  * error code here else existing
3966                                  * isochronous clients can get
3967                                  * confused:
3968                                  */
3969                                 if (pepext->xfer[i] != NULL) {
3970                                         xhci_device_done(pepext->xfer[i],
3971                                             USB_ERR_TIMEOUT);
3972                                 }
3973                         }
3974
3975                         /*
3976                          * NOTE: The USB transfer cannot vanish in
3977                          * this state!
3978                          */
3979
3980                         USB_BUS_UNLOCK(&sc->sc_bus);
3981
3982                         xhci_configure_reset_endpoint(xfer);
3983
3984                         USB_BUS_LOCK(&sc->sc_bus);
3985
3986                         /* check if halted is still cleared */
3987                         if (pepext->trb_halted == 0) {
3988                                 pepext->trb_running = 1;
3989                                 memset(pepext->trb_index, 0,
3990                                     sizeof(pepext->trb_index));
3991                         }
3992                         goto restart;
3993                 }
3994
3995                 if (xfer->flags_int.did_dma_delay) {
3996
3997                         /* remove transfer from interrupt queue (again) */
3998                         usbd_transfer_dequeue(xfer);
3999
4000                         /* we are finally done */
4001                         usb_dma_delay_done_cb(xfer);
4002
4003                         /* queue changed - restart */
4004                         goto restart;
4005                 }
4006         }
4007
4008         TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
4009
4010                 /* try to insert xfer on HW queue */
4011                 xhci_transfer_insert(xfer);
4012
4013                 /* try to multi buffer */
4014                 xhci_device_generic_multi_enter(xfer->endpoint,
4015                     xfer->stream_id, NULL);
4016         }
4017 }
4018
4019 static void
4020 xhci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
4021     struct usb_endpoint *ep)
4022 {
4023         struct xhci_endpoint_ext *pepext;
4024
4025         DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d\n",
4026             ep, udev->address, edesc->bEndpointAddress, udev->flags.usb_mode);
4027
4028         if (udev->parent_hub == NULL) {
4029                 /* root HUB has special endpoint handling */
4030                 return;
4031         }
4032
4033         ep->methods = &xhci_device_generic_methods;
4034
4035         pepext = xhci_get_endpoint_ext(udev, edesc);
4036
4037         USB_BUS_LOCK(udev->bus);
4038         pepext->trb_halted = 1;
4039         pepext->trb_running = 0;
4040         USB_BUS_UNLOCK(udev->bus);
4041 }
4042
4043 static void
4044 xhci_ep_uninit(struct usb_device *udev, struct usb_endpoint *ep)
4045 {
4046
4047 }
4048
4049 static void
4050 xhci_ep_clear_stall(struct usb_device *udev, struct usb_endpoint *ep)
4051 {
4052         struct xhci_endpoint_ext *pepext;
4053
4054         DPRINTF("\n");
4055
4056         if (udev->flags.usb_mode != USB_MODE_HOST) {
4057                 /* not supported */
4058                 return;
4059         }
4060         if (udev->parent_hub == NULL) {
4061                 /* root HUB has special endpoint handling */
4062                 return;
4063         }
4064
4065         pepext = xhci_get_endpoint_ext(udev, ep->edesc);
4066
4067         USB_BUS_LOCK(udev->bus);
4068         pepext->trb_halted = 1;
4069         pepext->trb_running = 0;
4070         USB_BUS_UNLOCK(udev->bus);
4071 }
4072
4073 static usb_error_t
4074 xhci_device_init(struct usb_device *udev)
4075 {
4076         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4077         usb_error_t err;
4078         uint8_t temp;
4079
4080         /* no init for root HUB */
4081         if (udev->parent_hub == NULL)
4082                 return (0);
4083
4084         XHCI_CMD_LOCK(sc);
4085
4086         /* set invalid default */
4087
4088         udev->controller_slot_id = sc->sc_noslot + 1;
4089
4090         /* try to get a new slot ID from the XHCI */
4091
4092         err = xhci_cmd_enable_slot(sc, &temp);
4093
4094         if (err) {
4095                 XHCI_CMD_UNLOCK(sc);
4096                 return (err);
4097         }
4098
4099         if (temp > sc->sc_noslot) {
4100                 XHCI_CMD_UNLOCK(sc);
4101                 return (USB_ERR_BAD_ADDRESS);
4102         }
4103
4104         if (sc->sc_hw.devs[temp].state != XHCI_ST_DISABLED) {
4105                 DPRINTF("slot %u already allocated.\n", temp);
4106                 XHCI_CMD_UNLOCK(sc);
4107                 return (USB_ERR_BAD_ADDRESS);
4108         }
4109
4110         /* store slot ID for later reference */
4111
4112         udev->controller_slot_id = temp;
4113
4114         /* reset data structure */
4115
4116         memset(&sc->sc_hw.devs[temp], 0, sizeof(sc->sc_hw.devs[0]));
4117
4118         /* set mark slot allocated */
4119
4120         sc->sc_hw.devs[temp].state = XHCI_ST_ENABLED;
4121
4122         err = xhci_alloc_device_ext(udev);
4123
4124         XHCI_CMD_UNLOCK(sc);
4125
4126         /* get device into default state */
4127
4128         if (err == 0)
4129                 err = xhci_set_address(udev, NULL, 0);
4130
4131         return (err);
4132 }
4133
4134 static void
4135 xhci_device_uninit(struct usb_device *udev)
4136 {
4137         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4138         uint8_t index;
4139
4140         /* no init for root HUB */
4141         if (udev->parent_hub == NULL)
4142                 return;
4143
4144         XHCI_CMD_LOCK(sc);
4145
4146         index = udev->controller_slot_id;
4147
4148         if (index <= sc->sc_noslot) {
4149                 xhci_cmd_disable_slot(sc, index);
4150                 sc->sc_hw.devs[index].state = XHCI_ST_DISABLED;
4151
4152                 /* free device extension */
4153                 xhci_free_device_ext(udev);
4154         }
4155
4156         XHCI_CMD_UNLOCK(sc);
4157 }
4158
4159 static void
4160 xhci_get_dma_delay(struct usb_device *udev, uint32_t *pus)
4161 {
4162         /*
4163          * Wait until the hardware has finished any possible use of
4164          * the transfer descriptor(s)
4165          */
4166         *pus = 2048;                    /* microseconds */
4167 }
4168
4169 static void
4170 xhci_device_resume(struct usb_device *udev)
4171 {
4172         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4173         uint8_t index;
4174         uint8_t n;
4175         uint8_t p;
4176
4177         DPRINTF("\n");
4178
4179         /* check for root HUB */
4180         if (udev->parent_hub == NULL)
4181                 return;
4182
4183         index = udev->controller_slot_id;
4184
4185         XHCI_CMD_LOCK(sc);
4186
4187         /* blindly resume all endpoints */
4188
4189         USB_BUS_LOCK(udev->bus);
4190
4191         for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) {
4192                 for (p = 0; p != XHCI_MAX_STREAMS; p++) {
4193                         XWRITE4(sc, door, XHCI_DOORBELL(index),
4194                             n | XHCI_DB_SID_SET(p));
4195                 }
4196         }
4197
4198         USB_BUS_UNLOCK(udev->bus);
4199
4200         XHCI_CMD_UNLOCK(sc);
4201 }
4202
4203 static void
4204 xhci_device_suspend(struct usb_device *udev)
4205 {
4206         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4207         uint8_t index;
4208         uint8_t n;
4209         usb_error_t err;
4210
4211         DPRINTF("\n");
4212
4213         /* check for root HUB */
4214         if (udev->parent_hub == NULL)
4215                 return;
4216
4217         index = udev->controller_slot_id;
4218
4219         XHCI_CMD_LOCK(sc);
4220
4221         /* blindly suspend all endpoints */
4222
4223         for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) {
4224                 err = xhci_cmd_stop_ep(sc, 1, n, index);
4225                 if (err != 0) {
4226                         DPRINTF("Failed to suspend endpoint "
4227                             "%u on slot %u (ignored).\n", n, index);
4228                 }
4229         }
4230
4231         XHCI_CMD_UNLOCK(sc);
4232 }
4233
4234 static void
4235 xhci_set_hw_power(struct usb_bus *bus)
4236 {
4237         DPRINTF("\n");
4238 }
4239
4240 static void
4241 xhci_device_state_change(struct usb_device *udev)
4242 {
4243         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4244         struct usb_page_search buf_inp;
4245         usb_error_t err;
4246         uint8_t index;
4247
4248         /* check for root HUB */
4249         if (udev->parent_hub == NULL)
4250                 return;
4251
4252         index = udev->controller_slot_id;
4253
4254         DPRINTF("\n");
4255
4256         if (usb_get_device_state(udev) == USB_STATE_CONFIGURED) {
4257                 err = uhub_query_info(udev, &sc->sc_hw.devs[index].nports,
4258                     &sc->sc_hw.devs[index].tt);
4259                 if (err != 0)
4260                         sc->sc_hw.devs[index].nports = 0;
4261         }
4262
4263         XHCI_CMD_LOCK(sc);
4264
4265         switch (usb_get_device_state(udev)) {
4266         case USB_STATE_POWERED:
4267                 if (sc->sc_hw.devs[index].state == XHCI_ST_DEFAULT)
4268                         break;
4269
4270                 /* set default state */
4271                 sc->sc_hw.devs[index].state = XHCI_ST_DEFAULT;
4272
4273                 /* reset number of contexts */
4274                 sc->sc_hw.devs[index].context_num = 0;
4275
4276                 err = xhci_cmd_reset_dev(sc, index);
4277
4278                 if (err != 0) {
4279                         DPRINTF("Device reset failed "
4280                             "for slot %u.\n", index);
4281                 }
4282                 break;
4283
4284         case USB_STATE_ADDRESSED:
4285                 if (sc->sc_hw.devs[index].state == XHCI_ST_ADDRESSED)
4286                         break;
4287
4288                 sc->sc_hw.devs[index].state = XHCI_ST_ADDRESSED;
4289
4290                 /* set configure mask to slot only */
4291                 xhci_configure_mask(udev, 1, 0);
4292
4293                 /* deconfigure all endpoints, except EP0 */
4294                 err = xhci_cmd_configure_ep(sc, 0, 1, index);
4295
4296                 if (err) {
4297                         DPRINTF("Failed to deconfigure "
4298                             "slot %u.\n", index);
4299                 }
4300                 break;
4301
4302         case USB_STATE_CONFIGURED:
4303                 if (sc->sc_hw.devs[index].state == XHCI_ST_CONFIGURED)
4304                         break;
4305
4306                 /* set configured state */
4307                 sc->sc_hw.devs[index].state = XHCI_ST_CONFIGURED;
4308
4309                 /* reset number of contexts */
4310                 sc->sc_hw.devs[index].context_num = 0;
4311
4312                 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
4313
4314                 xhci_configure_mask(udev, 3, 0);
4315
4316                 err = xhci_configure_device(udev);
4317                 if (err != 0) {
4318                         DPRINTF("Could not configure device "
4319                             "at slot %u.\n", index);
4320                 }
4321
4322                 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index);
4323                 if (err != 0) {
4324                         DPRINTF("Could not evaluate device "
4325                             "context at slot %u.\n", index);
4326                 }
4327                 break;
4328
4329         default:
4330                 break;
4331         }
4332         XHCI_CMD_UNLOCK(sc);
4333 }
4334
4335 static usb_error_t
4336 xhci_set_endpoint_mode(struct usb_device *udev, struct usb_endpoint *ep,
4337     uint8_t ep_mode)
4338 {
4339         switch (ep_mode) {
4340         case USB_EP_MODE_DEFAULT:
4341                 return (0);
4342         case USB_EP_MODE_STREAMS:
4343                 if (xhcistreams == 0 ||
4344                     (ep->edesc->bmAttributes & UE_XFERTYPE) != UE_BULK ||
4345                     udev->speed != USB_SPEED_SUPER)
4346                         return (USB_ERR_INVAL);
4347                 return (0);
4348         default:
4349                 return (USB_ERR_INVAL);
4350         }
4351 }
4352
4353 static const struct usb_bus_methods xhci_bus_methods = {
4354         .endpoint_init = xhci_ep_init,
4355         .endpoint_uninit = xhci_ep_uninit,
4356         .xfer_setup = xhci_xfer_setup,
4357         .xfer_unsetup = xhci_xfer_unsetup,
4358         .get_dma_delay = xhci_get_dma_delay,
4359         .device_init = xhci_device_init,
4360         .device_uninit = xhci_device_uninit,
4361         .device_resume = xhci_device_resume,
4362         .device_suspend = xhci_device_suspend,
4363         .set_hw_power = xhci_set_hw_power,
4364         .roothub_exec = xhci_roothub_exec,
4365         .xfer_poll = xhci_do_poll,
4366         .start_dma_delay = xhci_start_dma_delay,
4367         .set_address = xhci_set_address,
4368         .clear_stall = xhci_ep_clear_stall,
4369         .device_state_change = xhci_device_state_change,
4370         .set_hw_power_sleep = xhci_set_hw_power_sleep,
4371         .set_endpoint_mode = xhci_set_endpoint_mode,
4372 };