2 * Copyright (c) 2015-2016 Kevin Lo <kevlo@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/systm.h>
33 #include <sys/condvar.h>
34 #include <sys/kernel.h>
36 #include <sys/module.h>
37 #include <sys/mutex.h>
38 #include <sys/socket.h>
39 #include <sys/sysctl.h>
40 #include <sys/unistd.h>
43 #include <net/if_var.h>
44 #include <net/if_media.h>
46 #include <dev/mii/mii.h>
47 #include <dev/mii/miivar.h>
49 #include <dev/usb/usb.h>
50 #include <dev/usb/usbdi.h>
51 #include <dev/usb/usbdi_util.h>
54 #define USB_DEBUG_VAR ure_debug
55 #include <dev/usb/usb_debug.h>
56 #include <dev/usb/usb_process.h>
58 #include <dev/usb/net/usb_ethernet.h>
59 #include <dev/usb/net/if_urereg.h>
61 #include "miibus_if.h"
64 static int ure_debug = 0;
66 static SYSCTL_NODE(_hw_usb, OID_AUTO, ure, CTLFLAG_RW, 0, "USB ure");
67 SYSCTL_INT(_hw_usb_ure, OID_AUTO, debug, CTLFLAG_RWTUN, &ure_debug, 0,
71 #define ETHER_IS_ZERO(addr) \
72 (!(addr[0] | addr[1] | addr[2] | addr[3] | addr[4] | addr[5]))
75 * Various supported device vendors/products.
77 static const STRUCT_USB_HOST_ID ure_devs[] = {
78 #define URE_DEV(v,p,i) { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, i) }
79 URE_DEV(LENOVO, RTL8153, 0),
80 URE_DEV(LENOVO, TBT3LAN, 0),
81 URE_DEV(LENOVO, ONELINK, 0),
82 URE_DEV(LENOVO, USBCLAN, 0),
83 URE_DEV(NVIDIA, RTL8153, 0),
84 URE_DEV(REALTEK, RTL8152, URE_FLAG_8152),
85 URE_DEV(REALTEK, RTL8153, 0),
86 URE_DEV(TPLINK, RTL8153, 0),
90 static device_probe_t ure_probe;
91 static device_attach_t ure_attach;
92 static device_detach_t ure_detach;
94 static usb_callback_t ure_bulk_read_callback;
95 static usb_callback_t ure_bulk_write_callback;
97 static miibus_readreg_t ure_miibus_readreg;
98 static miibus_writereg_t ure_miibus_writereg;
99 static miibus_statchg_t ure_miibus_statchg;
101 static uether_fn_t ure_attach_post;
102 static uether_fn_t ure_init;
103 static uether_fn_t ure_stop;
104 static uether_fn_t ure_start;
105 static uether_fn_t ure_tick;
106 static uether_fn_t ure_rxfilter;
108 static int ure_ctl(struct ure_softc *, uint8_t, uint16_t, uint16_t,
110 static int ure_read_mem(struct ure_softc *, uint16_t, uint16_t, void *,
112 static int ure_write_mem(struct ure_softc *, uint16_t, uint16_t, void *,
114 static uint8_t ure_read_1(struct ure_softc *, uint16_t, uint16_t);
115 static uint16_t ure_read_2(struct ure_softc *, uint16_t, uint16_t);
116 static uint32_t ure_read_4(struct ure_softc *, uint16_t, uint16_t);
117 static int ure_write_1(struct ure_softc *, uint16_t, uint16_t, uint32_t);
118 static int ure_write_2(struct ure_softc *, uint16_t, uint16_t, uint32_t);
119 static int ure_write_4(struct ure_softc *, uint16_t, uint16_t, uint32_t);
120 static uint16_t ure_ocp_reg_read(struct ure_softc *, uint16_t);
121 static void ure_ocp_reg_write(struct ure_softc *, uint16_t, uint16_t);
123 static void ure_read_chipver(struct ure_softc *);
124 static int ure_attach_post_sub(struct usb_ether *);
125 static void ure_reset(struct ure_softc *);
126 static int ure_ifmedia_upd(struct ifnet *);
127 static void ure_ifmedia_sts(struct ifnet *, struct ifmediareq *);
128 static int ure_ioctl(struct ifnet *, u_long, caddr_t);
129 static void ure_rtl8152_init(struct ure_softc *);
130 static void ure_rtl8153_init(struct ure_softc *);
131 static void ure_disable_teredo(struct ure_softc *);
132 static void ure_init_fifo(struct ure_softc *);
134 static const struct usb_config ure_config[URE_N_TRANSFER] = {
137 .endpoint = UE_ADDR_ANY,
138 .direction = UE_DIR_OUT,
140 .flags = {.pipe_bof = 1,.force_short_xfer = 1,},
141 .callback = ure_bulk_write_callback,
142 .timeout = 10000, /* 10 seconds */
146 .endpoint = UE_ADDR_ANY,
147 .direction = UE_DIR_IN,
149 .flags = {.pipe_bof = 1,.short_xfer_ok = 1,},
150 .callback = ure_bulk_read_callback,
151 .timeout = 0, /* no timeout */
155 static device_method_t ure_methods[] = {
156 /* Device interface. */
157 DEVMETHOD(device_probe, ure_probe),
158 DEVMETHOD(device_attach, ure_attach),
159 DEVMETHOD(device_detach, ure_detach),
162 DEVMETHOD(miibus_readreg, ure_miibus_readreg),
163 DEVMETHOD(miibus_writereg, ure_miibus_writereg),
164 DEVMETHOD(miibus_statchg, ure_miibus_statchg),
169 static driver_t ure_driver = {
171 .methods = ure_methods,
172 .size = sizeof(struct ure_softc),
175 static devclass_t ure_devclass;
177 DRIVER_MODULE(ure, uhub, ure_driver, ure_devclass, NULL, NULL);
178 DRIVER_MODULE(miibus, ure, miibus_driver, miibus_devclass, NULL, NULL);
179 MODULE_DEPEND(ure, uether, 1, 1, 1);
180 MODULE_DEPEND(ure, usb, 1, 1, 1);
181 MODULE_DEPEND(ure, ether, 1, 1, 1);
182 MODULE_DEPEND(ure, miibus, 1, 1, 1);
183 MODULE_VERSION(ure, 1);
184 USB_PNP_HOST_INFO(ure_devs);
186 static const struct usb_ether_methods ure_ue_methods = {
187 .ue_attach_post = ure_attach_post,
188 .ue_attach_post_sub = ure_attach_post_sub,
189 .ue_start = ure_start,
193 .ue_setmulti = ure_rxfilter,
194 .ue_setpromisc = ure_rxfilter,
195 .ue_mii_upd = ure_ifmedia_upd,
196 .ue_mii_sts = ure_ifmedia_sts,
200 ure_ctl(struct ure_softc *sc, uint8_t rw, uint16_t val, uint16_t index,
203 struct usb_device_request req;
205 URE_LOCK_ASSERT(sc, MA_OWNED);
207 if (rw == URE_CTL_WRITE)
208 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
210 req.bmRequestType = UT_READ_VENDOR_DEVICE;
211 req.bRequest = UR_SET_ADDRESS;
212 USETW(req.wValue, val);
213 USETW(req.wIndex, index);
214 USETW(req.wLength, len);
216 return (uether_do_request(&sc->sc_ue, &req, buf, 1000));
220 ure_read_mem(struct ure_softc *sc, uint16_t addr, uint16_t index,
224 return (ure_ctl(sc, URE_CTL_READ, addr, index, buf, len));
228 ure_write_mem(struct ure_softc *sc, uint16_t addr, uint16_t index,
232 return (ure_ctl(sc, URE_CTL_WRITE, addr, index, buf, len));
236 ure_read_1(struct ure_softc *sc, uint16_t reg, uint16_t index)
242 shift = (reg & 3) << 3;
245 ure_read_mem(sc, reg, index, &temp, 4);
253 ure_read_2(struct ure_softc *sc, uint16_t reg, uint16_t index)
259 shift = (reg & 2) << 3;
262 ure_read_mem(sc, reg, index, &temp, 4);
266 return (val & 0xffff);
270 ure_read_4(struct ure_softc *sc, uint16_t reg, uint16_t index)
274 ure_read_mem(sc, reg, index, &temp, 4);
275 return (UGETDW(temp));
279 ure_write_1(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val)
285 byen = URE_BYTE_EN_BYTE;
291 val <<= (shift << 3);
296 return (ure_write_mem(sc, reg, index | byen, &temp, 4));
300 ure_write_2(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val)
306 byen = URE_BYTE_EN_WORD;
312 val <<= (shift << 3);
317 return (ure_write_mem(sc, reg, index | byen, &temp, 4));
321 ure_write_4(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val)
326 return (ure_write_mem(sc, reg, index | URE_BYTE_EN_DWORD, &temp, 4));
330 ure_ocp_reg_read(struct ure_softc *sc, uint16_t addr)
334 ure_write_2(sc, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000);
335 reg = (addr & 0x0fff) | 0xb000;
337 return (ure_read_2(sc, reg, URE_MCU_TYPE_PLA));
341 ure_ocp_reg_write(struct ure_softc *sc, uint16_t addr, uint16_t data)
345 ure_write_2(sc, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000);
346 reg = (addr & 0x0fff) | 0xb000;
348 ure_write_2(sc, reg, URE_MCU_TYPE_PLA, data);
352 ure_miibus_readreg(device_t dev, int phy, int reg)
354 struct ure_softc *sc;
358 sc = device_get_softc(dev);
359 locked = mtx_owned(&sc->sc_mtx);
363 /* Let the rgephy driver read the URE_GMEDIASTAT register. */
364 if (reg == URE_GMEDIASTAT) {
367 return (ure_read_1(sc, URE_GMEDIASTAT, URE_MCU_TYPE_PLA));
370 val = ure_ocp_reg_read(sc, URE_OCP_BASE_MII + reg * 2);
378 ure_miibus_writereg(device_t dev, int phy, int reg, int val)
380 struct ure_softc *sc;
383 sc = device_get_softc(dev);
384 if (sc->sc_phyno != phy)
387 locked = mtx_owned(&sc->sc_mtx);
391 ure_ocp_reg_write(sc, URE_OCP_BASE_MII + reg * 2, val);
399 ure_miibus_statchg(device_t dev)
401 struct ure_softc *sc;
402 struct mii_data *mii;
406 sc = device_get_softc(dev);
408 locked = mtx_owned(&sc->sc_mtx);
412 ifp = uether_getifp(&sc->sc_ue);
413 if (mii == NULL || ifp == NULL ||
414 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
417 sc->sc_flags &= ~URE_FLAG_LINK;
418 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
419 (IFM_ACTIVE | IFM_AVALID)) {
420 switch (IFM_SUBTYPE(mii->mii_media_active)) {
423 sc->sc_flags |= URE_FLAG_LINK;
426 if ((sc->sc_flags & URE_FLAG_8152) != 0)
428 sc->sc_flags |= URE_FLAG_LINK;
435 /* Lost link, do nothing. */
436 if ((sc->sc_flags & URE_FLAG_LINK) == 0)
444 * Probe for a RTL8152/RTL8153 chip.
447 ure_probe(device_t dev)
449 struct usb_attach_arg *uaa;
451 uaa = device_get_ivars(dev);
452 if (uaa->usb_mode != USB_MODE_HOST)
454 if (uaa->info.bConfigIndex != URE_CONFIG_IDX)
456 if (uaa->info.bIfaceIndex != URE_IFACE_IDX)
459 return (usbd_lookup_id_by_uaa(ure_devs, sizeof(ure_devs), uaa));
463 * Attach the interface. Allocate softc structures, do ifmedia
464 * setup and ethernet/BPF attach.
467 ure_attach(device_t dev)
469 struct usb_attach_arg *uaa = device_get_ivars(dev);
470 struct ure_softc *sc = device_get_softc(dev);
471 struct usb_ether *ue = &sc->sc_ue;
475 sc->sc_flags = USB_GET_DRIVER_INFO(uaa);
476 device_set_usb_desc(dev);
477 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF);
479 iface_index = URE_IFACE_IDX;
480 error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer,
481 ure_config, URE_N_TRANSFER, sc, &sc->sc_mtx);
483 device_printf(dev, "allocating USB transfers failed\n");
489 ue->ue_udev = uaa->device;
490 ue->ue_mtx = &sc->sc_mtx;
491 ue->ue_methods = &ure_ue_methods;
493 error = uether_ifattach(ue);
495 device_printf(dev, "could not attach interface\n");
498 return (0); /* success */
502 return (ENXIO); /* failure */
506 ure_detach(device_t dev)
508 struct ure_softc *sc = device_get_softc(dev);
509 struct usb_ether *ue = &sc->sc_ue;
511 usbd_transfer_unsetup(sc->sc_xfer, URE_N_TRANSFER);
513 mtx_destroy(&sc->sc_mtx);
519 ure_bulk_read_callback(struct usb_xfer *xfer, usb_error_t error)
521 struct ure_softc *sc = usbd_xfer_softc(xfer);
522 struct usb_ether *ue = &sc->sc_ue;
523 struct ifnet *ifp = uether_getifp(ue);
524 struct usb_page_cache *pc;
525 struct ure_rxpkt pkt;
528 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL);
530 switch (USB_GET_STATE(xfer)) {
531 case USB_ST_TRANSFERRED:
532 if (actlen < (int)(sizeof(pkt))) {
533 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
536 pc = usbd_xfer_get_frame(xfer, 0);
537 usbd_copy_out(pc, 0, &pkt, sizeof(pkt));
538 len = le32toh(pkt.ure_pktlen) & URE_RXPKT_LEN_MASK;
539 len -= ETHER_CRC_LEN;
540 if (actlen < (int)(len + sizeof(pkt))) {
541 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
545 uether_rxbuf(ue, pc, sizeof(pkt), len);
549 usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer));
550 usbd_transfer_submit(xfer);
555 DPRINTF("bulk read error, %s\n",
558 if (error != USB_ERR_CANCELLED) {
559 /* try to clear stall first */
560 usbd_xfer_set_stall(xfer);
568 ure_bulk_write_callback(struct usb_xfer *xfer, usb_error_t error)
570 struct ure_softc *sc = usbd_xfer_softc(xfer);
571 struct ifnet *ifp = uether_getifp(&sc->sc_ue);
572 struct usb_page_cache *pc;
574 struct ure_txpkt txpkt;
577 switch (USB_GET_STATE(xfer)) {
578 case USB_ST_TRANSFERRED:
579 DPRINTFN(11, "transfer complete\n");
580 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
584 if ((sc->sc_flags & URE_FLAG_LINK) == 0 ||
585 (ifp->if_drv_flags & IFF_DRV_OACTIVE) != 0) {
587 * don't send anything if there is no link !
591 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
595 len = m->m_pkthdr.len;
596 pc = usbd_xfer_get_frame(xfer, 0);
597 memset(&txpkt, 0, sizeof(txpkt));
598 txpkt.ure_pktlen = htole32((len & URE_TXPKT_LEN_MASK) |
599 URE_TKPKT_TX_FS | URE_TKPKT_TX_LS);
600 usbd_copy_in(pc, pos, &txpkt, sizeof(txpkt));
601 pos += sizeof(txpkt);
602 usbd_m_copy_in(pc, pos, m, 0, m->m_pkthdr.len);
603 pos += m->m_pkthdr.len;
605 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
608 * If there's a BPF listener, bounce a copy
609 * of this frame to him.
615 /* Set frame length. */
616 usbd_xfer_set_frame_len(xfer, 0, pos);
618 usbd_transfer_submit(xfer);
619 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
622 DPRINTFN(11, "transfer error, %s\n",
625 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
626 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
628 if (error != USB_ERR_CANCELLED) {
629 /* try to clear stall first */
630 usbd_xfer_set_stall(xfer);
638 ure_read_chipver(struct ure_softc *sc)
642 ver = ure_read_2(sc, URE_PLA_TCR1, URE_MCU_TYPE_PLA) & URE_VERSION_MASK;
645 sc->sc_chip |= URE_CHIP_VER_4C00;
648 sc->sc_chip |= URE_CHIP_VER_4C10;
651 sc->sc_chip |= URE_CHIP_VER_5C00;
654 sc->sc_chip |= URE_CHIP_VER_5C10;
657 sc->sc_chip |= URE_CHIP_VER_5C20;
660 sc->sc_chip |= URE_CHIP_VER_5C30;
663 device_printf(sc->sc_ue.ue_dev,
664 "unknown version 0x%04x\n", ver);
670 ure_attach_post(struct usb_ether *ue)
672 struct ure_softc *sc = uether_getsc(ue);
676 /* Determine the chip version. */
677 ure_read_chipver(sc);
679 /* Initialize controller and get station address. */
680 if (sc->sc_flags & URE_FLAG_8152)
681 ure_rtl8152_init(sc);
683 ure_rtl8153_init(sc);
685 if ((sc->sc_chip & URE_CHIP_VER_4C00) ||
686 (sc->sc_chip & URE_CHIP_VER_4C10))
687 ure_read_mem(sc, URE_PLA_IDR, URE_MCU_TYPE_PLA,
690 ure_read_mem(sc, URE_PLA_BACKUP, URE_MCU_TYPE_PLA,
693 if (ETHER_IS_ZERO(sc->sc_ue.ue_eaddr)) {
694 device_printf(sc->sc_ue.ue_dev, "MAC assigned randomly\n");
695 arc4rand(sc->sc_ue.ue_eaddr, ETHER_ADDR_LEN, 0);
696 sc->sc_ue.ue_eaddr[0] &= ~0x01; /* unicast */
697 sc->sc_ue.ue_eaddr[0] |= 0x02; /* locally administered */
702 ure_attach_post_sub(struct usb_ether *ue)
704 struct ure_softc *sc;
708 sc = uether_getsc(ue);
710 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
711 ifp->if_start = uether_start;
712 ifp->if_ioctl = ure_ioctl;
713 ifp->if_init = uether_init;
714 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen);
715 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen;
716 IFQ_SET_READY(&ifp->if_snd);
719 error = mii_attach(ue->ue_dev, &ue->ue_miibus, ifp,
720 uether_ifmedia_upd, ue->ue_methods->ue_mii_sts,
721 BMSR_DEFCAPMASK, sc->sc_phyno, MII_OFFSET_ANY, 0);
728 ure_init(struct usb_ether *ue)
730 struct ure_softc *sc = uether_getsc(ue);
731 struct ifnet *ifp = uether_getifp(ue);
733 URE_LOCK_ASSERT(sc, MA_OWNED);
735 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
738 /* Cancel pending I/O. */
743 /* Set MAC address. */
744 ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_CONFIG);
745 ure_write_mem(sc, URE_PLA_IDR, URE_MCU_TYPE_PLA | URE_BYTE_EN_SIX_BYTES,
747 ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_NORAML);
749 /* Reset the packet filter. */
750 ure_write_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA,
751 ure_read_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA) &
752 ~URE_FMC_FCR_MCU_EN);
753 ure_write_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA,
754 ure_read_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA) |
757 /* Enable transmit and receive. */
758 ure_write_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA,
759 ure_read_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA) | URE_CR_RE |
762 ure_write_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA,
763 ure_read_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA) &
766 /* Configure RX filters. */
769 usbd_xfer_set_stall(sc->sc_xfer[URE_BULK_DT_WR]);
771 /* Indicate we are up and running. */
772 ifp->if_drv_flags |= IFF_DRV_RUNNING;
774 /* Switch to selected media. */
775 ure_ifmedia_upd(ifp);
779 ure_tick(struct usb_ether *ue)
781 struct ure_softc *sc = uether_getsc(ue);
782 struct mii_data *mii = GET_MII(sc);
784 URE_LOCK_ASSERT(sc, MA_OWNED);
787 if ((sc->sc_flags & URE_FLAG_LINK) == 0
788 && mii->mii_media_status & IFM_ACTIVE &&
789 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
790 sc->sc_flags |= URE_FLAG_LINK;
796 * Program the 64-bit multicast hash filter.
799 ure_rxfilter(struct usb_ether *ue)
801 struct ure_softc *sc = uether_getsc(ue);
802 struct ifnet *ifp = uether_getifp(ue);
803 struct ifmultiaddr *ifma;
805 uint32_t hashes[2] = { 0, 0 };
807 URE_LOCK_ASSERT(sc, MA_OWNED);
809 rxmode = URE_RCR_APM;
810 if (ifp->if_flags & IFF_BROADCAST)
811 rxmode |= URE_RCR_AB;
812 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) {
813 if (ifp->if_flags & IFF_PROMISC)
814 rxmode |= URE_RCR_AAP;
815 rxmode |= URE_RCR_AM;
816 hashes[0] = hashes[1] = 0xffffffff;
820 rxmode |= URE_RCR_AM;
822 CK_STAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
823 if (ifma->ifma_addr->sa_family != AF_LINK)
825 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
826 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
828 hashes[0] |= (1 << h);
830 hashes[1] |= (1 << (h - 32));
832 if_maddr_runlock(ifp);
834 h = bswap32(hashes[0]);
835 hashes[0] = bswap32(hashes[1]);
837 rxmode |= URE_RCR_AM;
840 ure_write_4(sc, URE_PLA_MAR0, URE_MCU_TYPE_PLA, hashes[0]);
841 ure_write_4(sc, URE_PLA_MAR4, URE_MCU_TYPE_PLA, hashes[1]);
842 ure_write_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, rxmode);
846 ure_start(struct usb_ether *ue)
848 struct ure_softc *sc = uether_getsc(ue);
851 * start the USB transfers, if not already started:
853 usbd_transfer_start(sc->sc_xfer[URE_BULK_DT_RD]);
854 usbd_transfer_start(sc->sc_xfer[URE_BULK_DT_WR]);
858 ure_reset(struct ure_softc *sc)
862 ure_write_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_RST);
864 for (i = 0; i < URE_TIMEOUT; i++) {
865 if (!(ure_read_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA) &
868 uether_pause(&sc->sc_ue, hz / 100);
870 if (i == URE_TIMEOUT)
871 device_printf(sc->sc_ue.ue_dev, "reset never completed\n");
878 ure_ifmedia_upd(struct ifnet *ifp)
880 struct ure_softc *sc = ifp->if_softc;
881 struct mii_data *mii = GET_MII(sc);
882 struct mii_softc *miisc;
885 URE_LOCK_ASSERT(sc, MA_OWNED);
887 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
889 error = mii_mediachg(mii);
894 * Report current media status.
897 ure_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
899 struct ure_softc *sc;
900 struct mii_data *mii;
907 ifmr->ifm_active = mii->mii_media_active;
908 ifmr->ifm_status = mii->mii_media_status;
913 ure_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
915 struct usb_ether *ue = ifp->if_softc;
916 struct ure_softc *sc;
918 int error, mask, reinit;
920 sc = uether_getsc(ue);
921 ifr = (struct ifreq *)data;
924 if (cmd == SIOCSIFCAP) {
926 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
927 if (reinit > 0 && ifp->if_drv_flags & IFF_DRV_RUNNING)
928 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
935 error = uether_ioctl(ifp, cmd, data);
941 ure_rtl8152_init(struct ure_softc *sc)
946 ure_ocp_reg_write(sc, URE_OCP_ALDPS_CONFIG, URE_ENPDNPS | URE_LINKENA |
948 uether_pause(&sc->sc_ue, hz / 50);
950 if (sc->sc_chip & URE_CHIP_VER_4C00) {
951 ure_write_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA,
952 ure_read_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA) &
956 ure_write_2(sc, URE_USB_UPS_CTRL, URE_MCU_TYPE_USB,
957 ure_read_2(sc, URE_USB_UPS_CTRL, URE_MCU_TYPE_USB) &
959 ure_write_2(sc, URE_USB_PM_CTRL_STATUS, URE_MCU_TYPE_USB,
960 ure_read_2(sc, URE_USB_PM_CTRL_STATUS, URE_MCU_TYPE_USB) &
961 ~URE_RESUME_INDICATE);
963 ure_write_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA,
964 ure_read_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA) |
965 URE_TX_10M_IDLE_EN | URE_PFM_PWM_SWITCH);
966 pwrctrl = ure_read_4(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA);
967 pwrctrl &= ~URE_MCU_CLK_RATIO_MASK;
968 pwrctrl |= URE_MCU_CLK_RATIO | URE_D3_CLK_GATED_EN;
969 ure_write_4(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, pwrctrl);
970 ure_write_2(sc, URE_PLA_GPHY_INTR_IMR, URE_MCU_TYPE_PLA,
971 URE_GPHY_STS_MSK | URE_SPEED_DOWN_MSK | URE_SPDWN_RXDV_MSK |
972 URE_SPDWN_LINKCHG_MSK);
974 /* Disable Rx aggregation. */
975 ure_write_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB,
976 ure_read_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB) |
980 ure_ocp_reg_write(sc, URE_OCP_ALDPS_CONFIG, URE_ENPDNPS | URE_LINKENA |
982 uether_pause(&sc->sc_ue, hz / 50);
986 ure_write_1(sc, URE_USB_TX_AGG, URE_MCU_TYPE_USB,
987 URE_TX_AGG_MAX_THRESHOLD);
988 ure_write_4(sc, URE_USB_RX_BUF_TH, URE_MCU_TYPE_USB, URE_RX_THR_HIGH);
989 ure_write_4(sc, URE_USB_TX_DMA, URE_MCU_TYPE_USB,
990 URE_TEST_MODE_DISABLE | URE_TX_SIZE_ADJUST1);
994 ure_rtl8153_init(struct ure_softc *sc)
1000 /* Disable ALDPS. */
1001 ure_ocp_reg_write(sc, URE_OCP_POWER_CFG,
1002 ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) & ~URE_EN_ALDPS);
1003 uether_pause(&sc->sc_ue, hz / 50);
1005 memset(u1u2, 0x00, sizeof(u1u2));
1006 ure_write_mem(sc, URE_USB_TOLERANCE,
1007 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2));
1009 for (i = 0; i < URE_TIMEOUT; i++) {
1010 if (ure_read_2(sc, URE_PLA_BOOT_CTRL, URE_MCU_TYPE_PLA) &
1013 uether_pause(&sc->sc_ue, hz / 100);
1015 if (i == URE_TIMEOUT)
1016 device_printf(sc->sc_ue.ue_dev,
1017 "timeout waiting for chip autoload\n");
1019 for (i = 0; i < URE_TIMEOUT; i++) {
1020 val = ure_ocp_reg_read(sc, URE_OCP_PHY_STATUS) &
1022 if (val == URE_PHY_STAT_LAN_ON || val == URE_PHY_STAT_PWRDN)
1024 uether_pause(&sc->sc_ue, hz / 100);
1026 if (i == URE_TIMEOUT)
1027 device_printf(sc->sc_ue.ue_dev,
1028 "timeout waiting for phy to stabilize\n");
1030 ure_write_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB,
1031 ure_read_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB) &
1034 if (sc->sc_chip & URE_CHIP_VER_5C10) {
1035 val = ure_read_2(sc, URE_USB_SSPHYLINK2, URE_MCU_TYPE_USB);
1036 val &= ~URE_PWD_DN_SCALE_MASK;
1037 val |= URE_PWD_DN_SCALE(96);
1038 ure_write_2(sc, URE_USB_SSPHYLINK2, URE_MCU_TYPE_USB, val);
1040 ure_write_1(sc, URE_USB_USB2PHY, URE_MCU_TYPE_USB,
1041 ure_read_1(sc, URE_USB_USB2PHY, URE_MCU_TYPE_USB) |
1042 URE_USB2PHY_L1 | URE_USB2PHY_SUSPEND);
1043 } else if (sc->sc_chip & URE_CHIP_VER_5C20) {
1044 ure_write_1(sc, URE_PLA_DMY_REG0, URE_MCU_TYPE_PLA,
1045 ure_read_1(sc, URE_PLA_DMY_REG0, URE_MCU_TYPE_PLA) &
1048 if (sc->sc_chip & (URE_CHIP_VER_5C20 | URE_CHIP_VER_5C30)) {
1049 val = ure_read_1(sc, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB);
1050 if (ure_read_2(sc, URE_USB_BURST_SIZE, URE_MCU_TYPE_USB) ==
1052 val &= ~URE_DYNAMIC_BURST;
1054 val |= URE_DYNAMIC_BURST;
1055 ure_write_1(sc, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB, val);
1058 ure_write_1(sc, URE_USB_CSR_DUMMY2, URE_MCU_TYPE_USB,
1059 ure_read_1(sc, URE_USB_CSR_DUMMY2, URE_MCU_TYPE_USB) |
1062 ure_write_2(sc, URE_USB_WDT11_CTRL, URE_MCU_TYPE_USB,
1063 ure_read_2(sc, URE_USB_WDT11_CTRL, URE_MCU_TYPE_USB) &
1066 ure_write_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA,
1067 ure_read_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA) &
1068 ~URE_LED_MODE_MASK);
1070 if ((sc->sc_chip & URE_CHIP_VER_5C10) &&
1071 usbd_get_speed(sc->sc_ue.ue_udev) != USB_SPEED_SUPER)
1072 val = URE_LPM_TIMER_500MS;
1074 val = URE_LPM_TIMER_500US;
1075 ure_write_1(sc, URE_USB_LPM_CTRL, URE_MCU_TYPE_USB,
1076 val | URE_FIFO_EMPTY_1FB | URE_ROK_EXIT_LPM);
1078 val = ure_read_2(sc, URE_USB_AFE_CTRL2, URE_MCU_TYPE_USB);
1079 val &= ~URE_SEN_VAL_MASK;
1080 val |= URE_SEN_VAL_NORMAL | URE_SEL_RXIDLE;
1081 ure_write_2(sc, URE_USB_AFE_CTRL2, URE_MCU_TYPE_USB, val);
1083 ure_write_2(sc, URE_USB_CONNECT_TIMER, URE_MCU_TYPE_USB, 0x0001);
1085 ure_write_2(sc, URE_USB_POWER_CUT, URE_MCU_TYPE_USB,
1086 ure_read_2(sc, URE_USB_POWER_CUT, URE_MCU_TYPE_USB) &
1087 ~(URE_PWR_EN | URE_PHASE2_EN));
1088 ure_write_2(sc, URE_USB_MISC_0, URE_MCU_TYPE_USB,
1089 ure_read_2(sc, URE_USB_MISC_0, URE_MCU_TYPE_USB) &
1092 memset(u1u2, 0xff, sizeof(u1u2));
1093 ure_write_mem(sc, URE_USB_TOLERANCE,
1094 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2));
1096 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA,
1097 URE_ALDPS_SPDWN_RATIO);
1098 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_PLA,
1099 URE_EEE_SPDWN_RATIO);
1100 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL3, URE_MCU_TYPE_PLA,
1101 URE_PKT_AVAIL_SPDWN_EN | URE_SUSPEND_SPDWN_EN |
1102 URE_U1U2_SPDWN_EN | URE_L1_SPDWN_EN);
1103 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL4, URE_MCU_TYPE_PLA,
1104 URE_PWRSAVE_SPDWN_EN | URE_RXDV_SPDWN_EN | URE_TX10MIDLE_EN |
1105 URE_TP100_SPDWN_EN | URE_TP500_SPDWN_EN | URE_TP1000_SPDWN_EN |
1108 val = ure_read_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB);
1109 if (!(sc->sc_chip & (URE_CHIP_VER_5C00 | URE_CHIP_VER_5C10)))
1110 val |= URE_U2P3_ENABLE;
1112 val &= ~URE_U2P3_ENABLE;
1113 ure_write_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, val);
1115 memset(u1u2, 0x00, sizeof(u1u2));
1116 ure_write_mem(sc, URE_USB_TOLERANCE,
1117 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2));
1119 /* Disable ALDPS. */
1120 ure_ocp_reg_write(sc, URE_OCP_POWER_CFG,
1121 ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) & ~URE_EN_ALDPS);
1122 uether_pause(&sc->sc_ue, hz / 50);
1126 /* Disable Rx aggregation. */
1127 ure_write_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB,
1128 ure_read_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB) |
1129 URE_RX_AGG_DISABLE);
1131 val = ure_read_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB);
1132 if (!(sc->sc_chip & (URE_CHIP_VER_5C00 | URE_CHIP_VER_5C10)))
1133 val |= URE_U2P3_ENABLE;
1135 val &= ~URE_U2P3_ENABLE;
1136 ure_write_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, val);
1138 memset(u1u2, 0xff, sizeof(u1u2));
1139 ure_write_mem(sc, URE_USB_TOLERANCE,
1140 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2));
1144 ure_stop(struct usb_ether *ue)
1146 struct ure_softc *sc = uether_getsc(ue);
1147 struct ifnet *ifp = uether_getifp(ue);
1149 URE_LOCK_ASSERT(sc, MA_OWNED);
1151 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1152 sc->sc_flags &= ~URE_FLAG_LINK;
1155 * stop all the transfers, if not already stopped:
1157 usbd_transfer_stop(sc->sc_xfer[URE_BULK_DT_WR]);
1158 usbd_transfer_stop(sc->sc_xfer[URE_BULK_DT_RD]);
1162 ure_disable_teredo(struct ure_softc *sc)
1165 ure_write_4(sc, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA,
1166 ure_read_4(sc, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA) &
1167 ~(URE_TEREDO_SEL | URE_TEREDO_RS_EVENT_MASK | URE_OOB_TEREDO_EN));
1168 ure_write_2(sc, URE_PLA_WDT6_CTRL, URE_MCU_TYPE_PLA,
1170 ure_write_2(sc, URE_PLA_REALWOW_TIMER, URE_MCU_TYPE_PLA, 0);
1171 ure_write_4(sc, URE_PLA_TEREDO_TIMER, URE_MCU_TYPE_PLA, 0);
1175 ure_init_fifo(struct ure_softc *sc)
1177 uint32_t rx_fifo1, rx_fifo2;
1180 ure_write_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA,
1181 ure_read_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA) |
1184 ure_disable_teredo(sc);
1186 ure_write_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA,
1187 ure_read_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA) &
1190 if (!(sc->sc_flags & URE_FLAG_8152)) {
1191 if (sc->sc_chip & (URE_CHIP_VER_5C00 | URE_CHIP_VER_5C10 |
1192 URE_CHIP_VER_5C20)) {
1193 ure_ocp_reg_write(sc, URE_OCP_ADC_CFG,
1194 URE_CKADSEL_L | URE_ADC_EN | URE_EN_EMI_L);
1196 if (sc->sc_chip & URE_CHIP_VER_5C00) {
1197 ure_ocp_reg_write(sc, URE_OCP_EEE_CFG,
1198 ure_ocp_reg_read(sc, URE_OCP_EEE_CFG) &
1199 ~URE_CTAP_SHORT_EN);
1201 ure_ocp_reg_write(sc, URE_OCP_POWER_CFG,
1202 ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) |
1204 ure_ocp_reg_write(sc, URE_OCP_DOWN_SPEED,
1205 ure_ocp_reg_read(sc, URE_OCP_DOWN_SPEED) |
1207 ure_ocp_reg_write(sc, URE_OCP_POWER_CFG,
1208 ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) |
1210 ure_ocp_reg_write(sc, URE_OCP_SRAM_ADDR, URE_SRAM_IMPEDANCE);
1211 ure_ocp_reg_write(sc, URE_OCP_SRAM_DATA, 0x0b13);
1212 ure_write_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA,
1213 ure_read_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA) |
1214 URE_PFM_PWM_SWITCH);
1216 /* Enable LPF corner auto tune. */
1217 ure_ocp_reg_write(sc, URE_OCP_SRAM_ADDR, URE_SRAM_LPF_CFG);
1218 ure_ocp_reg_write(sc, URE_OCP_SRAM_DATA, 0xf70f);
1220 /* Adjust 10M amplitude. */
1221 ure_ocp_reg_write(sc, URE_OCP_SRAM_ADDR, URE_SRAM_10M_AMP1);
1222 ure_ocp_reg_write(sc, URE_OCP_SRAM_DATA, 0x00af);
1223 ure_ocp_reg_write(sc, URE_OCP_SRAM_ADDR, URE_SRAM_10M_AMP2);
1224 ure_ocp_reg_write(sc, URE_OCP_SRAM_DATA, 0x0208);
1229 ure_write_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, 0);
1231 ure_write_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA,
1232 ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) &
1235 ure_write_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA,
1236 ure_read_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA) &
1238 for (i = 0; i < URE_TIMEOUT; i++) {
1239 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) &
1240 URE_LINK_LIST_READY)
1242 uether_pause(&sc->sc_ue, hz / 100);
1244 if (i == URE_TIMEOUT)
1245 device_printf(sc->sc_ue.ue_dev,
1246 "timeout waiting for OOB control\n");
1247 ure_write_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA,
1248 ure_read_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA) |
1250 for (i = 0; i < URE_TIMEOUT; i++) {
1251 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) &
1252 URE_LINK_LIST_READY)
1254 uether_pause(&sc->sc_ue, hz / 100);
1256 if (i == URE_TIMEOUT)
1257 device_printf(sc->sc_ue.ue_dev,
1258 "timeout waiting for OOB control\n");
1260 ure_write_2(sc, URE_PLA_CPCR, URE_MCU_TYPE_PLA,
1261 ure_read_2(sc, URE_PLA_CPCR, URE_MCU_TYPE_PLA) &
1263 ure_write_2(sc, URE_PLA_TCR0, URE_MCU_TYPE_PLA,
1264 ure_read_2(sc, URE_PLA_TCR0, URE_MCU_TYPE_PLA) |
1265 URE_TCR0_AUTO_FIFO);
1267 /* Configure Rx FIFO threshold. */
1268 ure_write_4(sc, URE_PLA_RXFIFO_CTRL0, URE_MCU_TYPE_PLA,
1269 URE_RXFIFO_THR1_NORMAL);
1270 if (usbd_get_speed(sc->sc_ue.ue_udev) == USB_SPEED_FULL) {
1271 rx_fifo1 = URE_RXFIFO_THR2_FULL;
1272 rx_fifo2 = URE_RXFIFO_THR3_FULL;
1274 rx_fifo1 = URE_RXFIFO_THR2_HIGH;
1275 rx_fifo2 = URE_RXFIFO_THR3_HIGH;
1277 ure_write_4(sc, URE_PLA_RXFIFO_CTRL1, URE_MCU_TYPE_PLA, rx_fifo1);
1278 ure_write_4(sc, URE_PLA_RXFIFO_CTRL2, URE_MCU_TYPE_PLA, rx_fifo2);
1280 /* Configure Tx FIFO threshold. */
1281 ure_write_4(sc, URE_PLA_TXFIFO_CTRL, URE_MCU_TYPE_PLA,
1282 URE_TXFIFO_THR_NORMAL);