sys/dev/usb/net/if_ure.c

   1 /*-
   2  * Copyright (c) 2015-2016 Kevin Lo <kevlo@FreeBSD.org>
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  24  * SUCH DAMAGE.
  25  */
  26
  27 #include <sys/cdefs.h>
  28 __FBSDID("$FreeBSD$");
  29
  30 #include <sys/param.h>
  31 #include <sys/systm.h>
  32 #include <sys/bus.h>
  33 #include <sys/condvar.h>
  34 #include <sys/kernel.h>
  35 #include <sys/lock.h>
  36 #include <sys/module.h>
  37 #include <sys/mutex.h>
  38 #include <sys/socket.h>
  39 #include <sys/sysctl.h>
  40 #include <sys/unistd.h>
  41
  42 #include <net/if.h>
  43 #include <net/if_var.h>
  44 #include <net/if_media.h>
  45
  46 #include <dev/mii/mii.h>
  47 #include <dev/mii/miivar.h>
  48
  49 #include <dev/usb/usb.h>
  50 #include <dev/usb/usbdi.h>
  51 #include <dev/usb/usbdi_util.h>
  52 #include "usbdevs.h"
  53
  54 #define USB_DEBUG_VAR   ure_debug
  55 #include <dev/usb/usb_debug.h>
  56 #include <dev/usb/usb_process.h>
  57
  58 #include <dev/usb/net/usb_ethernet.h>
  59 #include <dev/usb/net/if_urereg.h>
  60
  61 #include "miibus_if.h"
  62
  63 #ifdef USB_DEBUG
  64 static int ure_debug = 0;
  65
  66 static SYSCTL_NODE(_hw_usb, OID_AUTO, ure, CTLFLAG_RW, 0, "USB ure");
  67 SYSCTL_INT(_hw_usb_ure, OID_AUTO, debug, CTLFLAG_RWTUN, &ure_debug, 0,
  68     "Debug level");
  69 #endif
  70
  71 /*
  72  * Various supported device vendors/products.
  73  */
  74 static const STRUCT_USB_HOST_ID ure_devs[] = {
  75 #define URE_DEV(v,p,i)  { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, i) }
  76         URE_DEV(LENOVO, RTL8153, 0),
  77         URE_DEV(LENOVO, TBT3LAN, 0),
  78         URE_DEV(LENOVO, ONELINK, 0),
  79         URE_DEV(LENOVO, USBCLAN, 0),
  80         URE_DEV(NVIDIA, RTL8153, 0),
  81         URE_DEV(REALTEK, RTL8152, URE_FLAG_8152),
  82         URE_DEV(REALTEK, RTL8153, 0),
  83         URE_DEV(TPLINK, RTL8153, 0),
  84 #undef URE_DEV
  85 };
  86
  87 static device_probe_t ure_probe;
  88 static device_attach_t ure_attach;
  89 static device_detach_t ure_detach;
  90
  91 static usb_callback_t ure_bulk_read_callback;
  92 static usb_callback_t ure_bulk_write_callback;
  93
  94 static miibus_readreg_t ure_miibus_readreg;
  95 static miibus_writereg_t ure_miibus_writereg;
  96 static miibus_statchg_t ure_miibus_statchg;
  97
  98 static uether_fn_t ure_attach_post;
  99 static uether_fn_t ure_init;
 100 static uether_fn_t ure_stop;
 101 static uether_fn_t ure_start;
 102 static uether_fn_t ure_tick;
 103 static uether_fn_t ure_rxfilter;
 104
 105 static int      ure_ctl(struct ure_softc *, uint8_t, uint16_t, uint16_t,
 106                     void *, int);
 107 static int      ure_read_mem(struct ure_softc *, uint16_t, uint16_t, void *,
 108                     int);
 109 static int      ure_write_mem(struct ure_softc *, uint16_t, uint16_t, void *,
 110                     int);
 111 static uint8_t  ure_read_1(struct ure_softc *, uint16_t, uint16_t);
 112 static uint16_t ure_read_2(struct ure_softc *, uint16_t, uint16_t);
 113 static uint32_t ure_read_4(struct ure_softc *, uint16_t, uint16_t);
 114 static int      ure_write_1(struct ure_softc *, uint16_t, uint16_t, uint32_t);
 115 static int      ure_write_2(struct ure_softc *, uint16_t, uint16_t, uint32_t);
 116 static int      ure_write_4(struct ure_softc *, uint16_t, uint16_t, uint32_t);
 117 static uint16_t ure_ocp_reg_read(struct ure_softc *, uint16_t);
 118 static void     ure_ocp_reg_write(struct ure_softc *, uint16_t, uint16_t);
 119
 120 static void     ure_read_chipver(struct ure_softc *);
 121 static int      ure_attach_post_sub(struct usb_ether *);
 122 static void     ure_reset(struct ure_softc *);
 123 static int      ure_ifmedia_upd(struct ifnet *);
 124 static void     ure_ifmedia_sts(struct ifnet *, struct ifmediareq *);
 125 static int      ure_ioctl(struct ifnet *, u_long, caddr_t);
 126 static void     ure_rtl8152_init(struct ure_softc *);
 127 static void     ure_rtl8153_init(struct ure_softc *);
 128 static void     ure_disable_teredo(struct ure_softc *);
 129 static void     ure_init_fifo(struct ure_softc *);
 130
 131 static const struct usb_config ure_config[URE_N_TRANSFER] = {
 132         [URE_BULK_DT_WR] = {
 133                 .type = UE_BULK,
 134                 .endpoint = UE_ADDR_ANY,
 135                 .direction = UE_DIR_OUT,
 136                 .bufsize = MCLBYTES,
 137                 .flags = {.pipe_bof = 1,.force_short_xfer = 1,},
 138                 .callback = ure_bulk_write_callback,
 139                 .timeout = 10000,       /* 10 seconds */
 140         },
 141         [URE_BULK_DT_RD] = {
 142                 .type = UE_BULK,
 143                 .endpoint = UE_ADDR_ANY,
 144                 .direction = UE_DIR_IN,
 145                 .bufsize = 16384,
 146                 .flags = {.pipe_bof = 1,.short_xfer_ok = 1,},
 147                 .callback = ure_bulk_read_callback,
 148                 .timeout = 0,   /* no timeout */
 149         },
 150 };
 151
 152 static device_method_t ure_methods[] = {
 153         /* Device interface. */
 154         DEVMETHOD(device_probe, ure_probe),
 155         DEVMETHOD(device_attach, ure_attach),
 156         DEVMETHOD(device_detach, ure_detach),
 157
 158         /* MII interface. */
 159         DEVMETHOD(miibus_readreg, ure_miibus_readreg),
 160         DEVMETHOD(miibus_writereg, ure_miibus_writereg),
 161         DEVMETHOD(miibus_statchg, ure_miibus_statchg),
 162
 163         DEVMETHOD_END
 164 };
 165
 166 static driver_t ure_driver = {
 167         .name = "ure",
 168         .methods = ure_methods,
 169         .size = sizeof(struct ure_softc),
 170 };
 171
 172 static devclass_t ure_devclass;
 173
 174 DRIVER_MODULE(ure, uhub, ure_driver, ure_devclass, NULL, NULL);
 175 DRIVER_MODULE(miibus, ure, miibus_driver, miibus_devclass, NULL, NULL);
 176 MODULE_DEPEND(ure, uether, 1, 1, 1);
 177 MODULE_DEPEND(ure, usb, 1, 1, 1);
 178 MODULE_DEPEND(ure, ether, 1, 1, 1);
 179 MODULE_DEPEND(ure, miibus, 1, 1, 1);
 180 MODULE_VERSION(ure, 1);
 181 USB_PNP_HOST_INFO(ure_devs);
 182
 183 static const struct usb_ether_methods ure_ue_methods = {
 184         .ue_attach_post = ure_attach_post,
 185         .ue_attach_post_sub = ure_attach_post_sub,
 186         .ue_start = ure_start,
 187         .ue_init = ure_init,
 188         .ue_stop = ure_stop,
 189         .ue_tick = ure_tick,
 190         .ue_setmulti = ure_rxfilter,
 191         .ue_setpromisc = ure_rxfilter,
 192         .ue_mii_upd = ure_ifmedia_upd,
 193         .ue_mii_sts = ure_ifmedia_sts,
 194 };
 195
 196 static int
 197 ure_ctl(struct ure_softc *sc, uint8_t rw, uint16_t val, uint16_t index,
 198     void *buf, int len)
 199 {
 200         struct usb_device_request req;
 201
 202         URE_LOCK_ASSERT(sc, MA_OWNED);
 203
 204         if (rw == URE_CTL_WRITE)
 205                 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
 206         else
 207                 req.bmRequestType = UT_READ_VENDOR_DEVICE;
 208         req.bRequest = UR_SET_ADDRESS;
 209         USETW(req.wValue, val);
 210         USETW(req.wIndex, index);
 211         USETW(req.wLength, len);
 212
 213         return (uether_do_request(&sc->sc_ue, &req, buf, 1000));
 214 }
 215
 216 static int
 217 ure_read_mem(struct ure_softc *sc, uint16_t addr, uint16_t index,
 218     void *buf, int len)
 219 {
 220
 221         return (ure_ctl(sc, URE_CTL_READ, addr, index, buf, len));
 222 }
 223
 224 static int
 225 ure_write_mem(struct ure_softc *sc, uint16_t addr, uint16_t index,
 226     void *buf, int len)
 227 {
 228
 229         return (ure_ctl(sc, URE_CTL_WRITE, addr, index, buf, len));
 230 }
 231
 232 static uint8_t
 233 ure_read_1(struct ure_softc *sc, uint16_t reg, uint16_t index)
 234 {
 235         uint32_t val;
 236         uint8_t temp[4];
 237         uint8_t shift;
 238
 239         shift = (reg & 3) << 3;
 240         reg &= ~3;
 241
 242         ure_read_mem(sc, reg, index, &temp, 4);
 243         val = UGETDW(temp);
 244         val >>= shift;
 245
 246         return (val & 0xff);
 247 }
 248
 249 static uint16_t
 250 ure_read_2(struct ure_softc *sc, uint16_t reg, uint16_t index)
 251 {
 252         uint32_t val;
 253         uint8_t temp[4];
 254         uint8_t shift;
 255
 256         shift = (reg & 2) << 3;
 257         reg &= ~3;
 258
 259         ure_read_mem(sc, reg, index, &temp, 4);
 260         val = UGETDW(temp);
 261         val >>= shift;
 262
 263         return (val & 0xffff);
 264 }
 265
 266 static uint32_t
 267 ure_read_4(struct ure_softc *sc, uint16_t reg, uint16_t index)
 268 {
 269         uint8_t temp[4];
 270
 271         ure_read_mem(sc, reg, index, &temp, 4);
 272         return (UGETDW(temp));
 273 }
 274
 275 static int
 276 ure_write_1(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val)
 277 {
 278         uint16_t byen;
 279         uint8_t temp[4];
 280         uint8_t shift;
 281
 282         byen = URE_BYTE_EN_BYTE;
 283         shift = reg & 3;
 284         val &= 0xff;
 285
 286         if (reg & 3) {
 287                 byen <<= shift;
 288                 val <<= (shift << 3);
 289                 reg &= ~3;
 290         }
 291
 292         USETDW(temp, val);
 293         return (ure_write_mem(sc, reg, index | byen, &temp, 4));
 294 }
 295
 296 static int
 297 ure_write_2(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val)
 298 {
 299         uint16_t byen;
 300         uint8_t temp[4];
 301         uint8_t shift;
 302
 303         byen = URE_BYTE_EN_WORD;
 304         shift = reg & 2;
 305         val &= 0xffff;
 306
 307         if (reg & 2) {
 308                 byen <<= shift;
 309                 val <<= (shift << 3);
 310                 reg &= ~3;
 311         }
 312
 313         USETDW(temp, val);
 314         return (ure_write_mem(sc, reg, index | byen, &temp, 4));
 315 }
 316
 317 static int
 318 ure_write_4(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val)
 319 {
 320         uint8_t temp[4];
 321
 322         USETDW(temp, val);
 323         return (ure_write_mem(sc, reg, index | URE_BYTE_EN_DWORD, &temp, 4));
 324 }
 325
 326 static uint16_t
 327 ure_ocp_reg_read(struct ure_softc *sc, uint16_t addr)
 328 {
 329         uint16_t reg;
 330
 331         ure_write_2(sc, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000);
 332         reg = (addr & 0x0fff) | 0xb000;
 333
 334         return (ure_read_2(sc, reg, URE_MCU_TYPE_PLA));
 335 }
 336
 337 static void
 338 ure_ocp_reg_write(struct ure_softc *sc, uint16_t addr, uint16_t data)
 339 {
 340         uint16_t reg;
 341
 342         ure_write_2(sc, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000);
 343         reg = (addr & 0x0fff) | 0xb000;
 344
 345         ure_write_2(sc, reg, URE_MCU_TYPE_PLA, data);
 346 }
 347
 348 static int
 349 ure_miibus_readreg(device_t dev, int phy, int reg)
 350 {
 351         struct ure_softc *sc;
 352         uint16_t val;
 353         int locked;
 354
 355         sc = device_get_softc(dev);
 356         locked = mtx_owned(&sc->sc_mtx);
 357         if (!locked)
 358                 URE_LOCK(sc);
 359
 360         /* Let the rgephy driver read the URE_GMEDIASTAT register. */
 361         if (reg == URE_GMEDIASTAT) {
 362                 if (!locked)
 363                         URE_UNLOCK(sc);
 364                 return (ure_read_1(sc, URE_GMEDIASTAT, URE_MCU_TYPE_PLA));
 365         }
 366
 367         val = ure_ocp_reg_read(sc, URE_OCP_BASE_MII + reg * 2);
 368
 369         if (!locked)
 370                 URE_UNLOCK(sc);
 371         return (val);
 372 }
 373
 374 static int
 375 ure_miibus_writereg(device_t dev, int phy, int reg, int val)
 376 {
 377         struct ure_softc *sc;
 378         int locked;
 379
 380         sc = device_get_softc(dev);
 381         if (sc->sc_phyno != phy)
 382                 return (0);
 383
 384         locked = mtx_owned(&sc->sc_mtx);
 385         if (!locked)
 386                 URE_LOCK(sc);
 387
 388         ure_ocp_reg_write(sc, URE_OCP_BASE_MII + reg * 2, val);
 389
 390         if (!locked)
 391                 URE_UNLOCK(sc);
 392         return (0);
 393 }
 394
 395 static void
 396 ure_miibus_statchg(device_t dev)
 397 {
 398         struct ure_softc *sc;
 399         struct mii_data *mii;
 400         struct ifnet *ifp;
 401         int locked;
 402
 403         sc = device_get_softc(dev);
 404         mii = GET_MII(sc);
 405         locked = mtx_owned(&sc->sc_mtx);
 406         if (!locked)
 407                 URE_LOCK(sc);
 408
 409         ifp = uether_getifp(&sc->sc_ue);
 410         if (mii == NULL || ifp == NULL ||
 411             (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
 412                 goto done;
 413
 414         sc->sc_flags &= ~URE_FLAG_LINK;
 415         if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
 416             (IFM_ACTIVE | IFM_AVALID)) {
 417                 switch (IFM_SUBTYPE(mii->mii_media_active)) {
 418                 case IFM_10_T:
 419                 case IFM_100_TX:
 420                         sc->sc_flags |= URE_FLAG_LINK;
 421                         break;
 422                 case IFM_1000_T:
 423                         if ((sc->sc_flags & URE_FLAG_8152) != 0)
 424                                 break;
 425                         sc->sc_flags |= URE_FLAG_LINK;
 426                         break;
 427                 default:
 428                         break;
 429                 }
 430         }
 431
 432         /* Lost link, do nothing. */
 433         if ((sc->sc_flags & URE_FLAG_LINK) == 0)
 434                 goto done;
 435 done:
 436         if (!locked)
 437                 URE_UNLOCK(sc);
 438 }
 439
 440 /*
 441  * Probe for a RTL8152/RTL8153 chip.
 442  */
 443 static int
 444 ure_probe(device_t dev)
 445 {
 446         struct usb_attach_arg *uaa;
 447
 448         uaa = device_get_ivars(dev);
 449         if (uaa->usb_mode != USB_MODE_HOST)
 450                 return (ENXIO);
 451         if (uaa->info.bConfigIndex != URE_CONFIG_IDX)
 452                 return (ENXIO);
 453         if (uaa->info.bIfaceIndex != URE_IFACE_IDX)
 454                 return (ENXIO);
 455
 456         return (usbd_lookup_id_by_uaa(ure_devs, sizeof(ure_devs), uaa));
 457 }
 458
 459 /*
 460  * Attach the interface. Allocate softc structures, do ifmedia
 461  * setup and ethernet/BPF attach.
 462  */
 463 static int
 464 ure_attach(device_t dev)
 465 {
 466         struct usb_attach_arg *uaa = device_get_ivars(dev);
 467         struct ure_softc *sc = device_get_softc(dev);
 468         struct usb_ether *ue = &sc->sc_ue;
 469         uint8_t iface_index;
 470         int error;
 471
 472         sc->sc_flags = USB_GET_DRIVER_INFO(uaa);
 473         device_set_usb_desc(dev);
 474         mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF);
 475
 476         iface_index = URE_IFACE_IDX;
 477         error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer,
 478             ure_config, URE_N_TRANSFER, sc, &sc->sc_mtx);
 479         if (error != 0) {
 480                 device_printf(dev, "allocating USB transfers failed\n");
 481                 goto detach;
 482         }
 483
 484         ue->ue_sc = sc;
 485         ue->ue_dev = dev;
 486         ue->ue_udev = uaa->device;
 487         ue->ue_mtx = &sc->sc_mtx;
 488         ue->ue_methods = &ure_ue_methods;
 489
 490         error = uether_ifattach(ue);
 491         if (error != 0) {
 492                 device_printf(dev, "could not attach interface\n");
 493                 goto detach;
 494         }
 495         return (0);                     /* success */
 496
 497 detach:
 498         ure_detach(dev);
 499         return (ENXIO);                 /* failure */
 500 }
 501
 502 static int
 503 ure_detach(device_t dev)
 504 {
 505         struct ure_softc *sc = device_get_softc(dev);
 506         struct usb_ether *ue = &sc->sc_ue;
 507
 508         usbd_transfer_unsetup(sc->sc_xfer, URE_N_TRANSFER);
 509         uether_ifdetach(ue);
 510         mtx_destroy(&sc->sc_mtx);
 511
 512         return (0);
 513 }
 514
 515 static void
 516 ure_bulk_read_callback(struct usb_xfer *xfer, usb_error_t error)
 517 {
 518         struct ure_softc *sc = usbd_xfer_softc(xfer);
 519         struct usb_ether *ue = &sc->sc_ue;
 520         struct ifnet *ifp = uether_getifp(ue);
 521         struct usb_page_cache *pc;
 522         struct ure_rxpkt pkt;
 523         int actlen, len;
 524
 525         usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL);
 526
 527         switch (USB_GET_STATE(xfer)) {
 528         case USB_ST_TRANSFERRED:
 529                 if (actlen < (int)(sizeof(pkt))) {
 530                         if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
 531                         goto tr_setup;
 532                 }
 533                 pc = usbd_xfer_get_frame(xfer, 0);
 534                 usbd_copy_out(pc, 0, &pkt, sizeof(pkt));
 535                 len = le32toh(pkt.ure_pktlen) & URE_RXPKT_LEN_MASK;
 536                 len -= ETHER_CRC_LEN;
 537                 if (actlen < (int)(len + sizeof(pkt))) {
 538                         if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
 539                         goto tr_setup;
 540                 }
 541
 542                 uether_rxbuf(ue, pc, sizeof(pkt), len);
 543                 /* FALLTHROUGH */
 544         case USB_ST_SETUP:
 545 tr_setup:
 546                 usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer));
 547                 usbd_transfer_submit(xfer);
 548                 uether_rxflush(ue);
 549                 return;
 550
 551         default:                        /* Error */
 552                 DPRINTF("bulk read error, %s\n",
 553                     usbd_errstr(error));
 554
 555                 if (error != USB_ERR_CANCELLED) {
 556                         /* try to clear stall first */
 557                         usbd_xfer_set_stall(xfer);
 558                         goto tr_setup;
 559                 }
 560                 return;
 561         }
 562 }
 563
 564 static void
 565 ure_bulk_write_callback(struct usb_xfer *xfer, usb_error_t error)
 566 {
 567         struct ure_softc *sc = usbd_xfer_softc(xfer);
 568         struct ifnet *ifp = uether_getifp(&sc->sc_ue);
 569         struct usb_page_cache *pc;
 570         struct mbuf *m;
 571         struct ure_txpkt txpkt;
 572         int len, pos;
 573
 574         switch (USB_GET_STATE(xfer)) {
 575         case USB_ST_TRANSFERRED:
 576                 DPRINTFN(11, "transfer complete\n");
 577                 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
 578                 /* FALLTHROUGH */
 579         case USB_ST_SETUP:
 580 tr_setup:
 581                 if ((sc->sc_flags & URE_FLAG_LINK) == 0 ||
 582                     (ifp->if_drv_flags & IFF_DRV_OACTIVE) != 0) {
 583                         /*
 584                          * don't send anything if there is no link !
 585                          */
 586                         return;
 587                 }
 588                 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
 589                 if (m == NULL)
 590                         break;
 591                 pos = 0;
 592                 len = m->m_pkthdr.len;
 593                 pc = usbd_xfer_get_frame(xfer, 0);
 594                 memset(&txpkt, 0, sizeof(txpkt));
 595                 txpkt.ure_pktlen = htole32((len & URE_TXPKT_LEN_MASK) |
 596                     URE_TKPKT_TX_FS | URE_TKPKT_TX_LS);
 597                 usbd_copy_in(pc, pos, &txpkt, sizeof(txpkt));
 598                 pos += sizeof(txpkt);
 599                 usbd_m_copy_in(pc, pos, m, 0, m->m_pkthdr.len);
 600                 pos += m->m_pkthdr.len;
 601
 602                 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
 603
 604                 /*
 605                  * If there's a BPF listener, bounce a copy
 606                  * of this frame to him.
 607                  */
 608                 BPF_MTAP(ifp, m);
 609
 610                 m_freem(m);
 611
 612                 /* Set frame length. */
 613                 usbd_xfer_set_frame_len(xfer, 0, pos);
 614
 615                 usbd_transfer_submit(xfer);
 616                 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
 617                 return;
 618         default:                        /* Error */
 619                 DPRINTFN(11, "transfer error, %s\n",
 620                     usbd_errstr(error));
 621
 622                 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
 623                 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
 624
 625                 if (error != USB_ERR_CANCELLED) {
 626                         /* try to clear stall first */
 627                         usbd_xfer_set_stall(xfer);
 628                         goto tr_setup;
 629                 }
 630                 return;
 631         }
 632 }
 633
 634 static void
 635 ure_read_chipver(struct ure_softc *sc)
 636 {
 637         uint16_t ver;
 638
 639         ver = ure_read_2(sc, URE_PLA_TCR1, URE_MCU_TYPE_PLA) & URE_VERSION_MASK;
 640         switch (ver) {
 641         case 0x4c00:
 642                 sc->sc_chip |= URE_CHIP_VER_4C00;
 643                 break;
 644         case 0x4c10:
 645                 sc->sc_chip |= URE_CHIP_VER_4C10;
 646                 break;
 647         case 0x5c00:
 648                 sc->sc_chip |= URE_CHIP_VER_5C00;
 649                 break;
 650         case 0x5c10:
 651                 sc->sc_chip |= URE_CHIP_VER_5C10;
 652                 break;
 653         case 0x5c20:
 654                 sc->sc_chip |= URE_CHIP_VER_5C20;
 655                 break;
 656         case 0x5c30:
 657                 sc->sc_chip |= URE_CHIP_VER_5C30;
 658                 break;
 659         default:
 660                 device_printf(sc->sc_ue.ue_dev,
 661                     "unknown version 0x%04x\n", ver);
 662                 break;
 663         }
 664 }
 665
 666 static void
 667 ure_attach_post(struct usb_ether *ue)
 668 {
 669         struct ure_softc *sc = uether_getsc(ue);
 670
 671         sc->sc_phyno = 0;
 672
 673         /* Determine the chip version. */
 674         ure_read_chipver(sc);
 675
 676         /* Initialize controller and get station address. */
 677         if (sc->sc_flags & URE_FLAG_8152)
 678                 ure_rtl8152_init(sc);
 679         else
 680                 ure_rtl8153_init(sc);
 681
 682         if ((sc->sc_chip & URE_CHIP_VER_4C00) ||
 683             (sc->sc_chip & URE_CHIP_VER_4C10))
 684                 ure_read_mem(sc, URE_PLA_IDR, URE_MCU_TYPE_PLA,
 685                     ue->ue_eaddr, 8);
 686         else
 687                 ure_read_mem(sc, URE_PLA_BACKUP, URE_MCU_TYPE_PLA,
 688                     ue->ue_eaddr, 8);
 689
 690         if (ETHER_IS_ZERO(sc->sc_ue.ue_eaddr)) {
 691                 device_printf(sc->sc_ue.ue_dev, "MAC assigned randomly\n");
 692                 arc4rand(sc->sc_ue.ue_eaddr, ETHER_ADDR_LEN, 0);
 693                 sc->sc_ue.ue_eaddr[0] &= ~0x01; /* unicast */
 694                 sc->sc_ue.ue_eaddr[0] |= 0x02;  /* locally administered */
 695         }
 696 }
 697
 698 static int
 699 ure_attach_post_sub(struct usb_ether *ue)
 700 {
 701         struct ure_softc *sc;
 702         struct ifnet *ifp;
 703         int error;
 704
 705         sc = uether_getsc(ue);
 706         ifp = ue->ue_ifp;
 707         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
 708         ifp->if_start = uether_start;
 709         ifp->if_ioctl = ure_ioctl;
 710         ifp->if_init = uether_init;
 711         IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen);
 712         ifp->if_snd.ifq_drv_maxlen = ifqmaxlen;
 713         IFQ_SET_READY(&ifp->if_snd);
 714
 715         mtx_lock(&Giant);
 716         error = mii_attach(ue->ue_dev, &ue->ue_miibus, ifp,
 717             uether_ifmedia_upd, ue->ue_methods->ue_mii_sts,
 718             BMSR_DEFCAPMASK, sc->sc_phyno, MII_OFFSET_ANY, 0);
 719         mtx_unlock(&Giant);
 720
 721         return (error);
 722 }
 723
 724 static void
 725 ure_init(struct usb_ether *ue)
 726 {
 727         struct ure_softc *sc = uether_getsc(ue);
 728         struct ifnet *ifp = uether_getifp(ue);
 729
 730         URE_LOCK_ASSERT(sc, MA_OWNED);
 731
 732         if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
 733                 return;
 734
 735         /* Cancel pending I/O. */
 736         ure_stop(ue);
 737
 738         ure_reset(sc);
 739
 740         /* Set MAC address. */
 741         ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_CONFIG);
 742         ure_write_mem(sc, URE_PLA_IDR, URE_MCU_TYPE_PLA | URE_BYTE_EN_SIX_BYTES,
 743             IF_LLADDR(ifp), 8);
 744         ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_NORAML);
 745
 746         /* Reset the packet filter. */
 747         ure_write_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA,
 748             ure_read_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA) &
 749             ~URE_FMC_FCR_MCU_EN);
 750         ure_write_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA,
 751             ure_read_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA) |
 752             URE_FMC_FCR_MCU_EN);
 753
 754         /* Enable transmit and receive. */
 755         ure_write_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA,
 756             ure_read_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA) | URE_CR_RE |
 757             URE_CR_TE);
 758
 759         ure_write_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA,
 760             ure_read_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA) &
 761             ~URE_RXDY_GATED_EN);
 762
 763         /*  Configure RX filters. */
 764         ure_rxfilter(ue);
 765
 766         usbd_xfer_set_stall(sc->sc_xfer[URE_BULK_DT_WR]);
 767
 768         /* Indicate we are up and running. */
 769         ifp->if_drv_flags |= IFF_DRV_RUNNING;
 770
 771         /* Switch to selected media. */
 772         ure_ifmedia_upd(ifp);
 773 }
 774
 775 static void
 776 ure_tick(struct usb_ether *ue)
 777 {
 778         struct ure_softc *sc = uether_getsc(ue);
 779         struct mii_data *mii = GET_MII(sc);
 780
 781         URE_LOCK_ASSERT(sc, MA_OWNED);
 782
 783         mii_tick(mii);
 784         if ((sc->sc_flags & URE_FLAG_LINK) == 0
 785             && mii->mii_media_status & IFM_ACTIVE &&
 786             IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
 787                 sc->sc_flags |= URE_FLAG_LINK;
 788                 ure_start(ue);
 789         }
 790 }
 791
 792 static u_int
 793 ure_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
 794 {
 795         uint32_t h, *hashes = arg;
 796
 797         h = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN) >> 26;
 798         if (h < 32)
 799                 hashes[0] |= (1 << h);
 800         else
 801                 hashes[1] |= (1 << (h - 32));
 802         return (1);
 803 }
 804
 805 /*
 806  * Program the 64-bit multicast hash filter.
 807  */
 808 static void
 809 ure_rxfilter(struct usb_ether *ue)
 810 {
 811         struct ure_softc *sc = uether_getsc(ue);
 812         struct ifnet *ifp = uether_getifp(ue);
 813         uint32_t rxmode;
 814         uint32_t h, hashes[2] = { 0, 0 };
 815
 816         URE_LOCK_ASSERT(sc, MA_OWNED);
 817
 818         rxmode = URE_RCR_APM;
 819         if (ifp->if_flags & IFF_BROADCAST)
 820                  rxmode |= URE_RCR_AB;
 821         if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) {
 822                 if (ifp->if_flags & IFF_PROMISC)
 823                         rxmode |= URE_RCR_AAP;
 824                 rxmode |= URE_RCR_AM;
 825                 hashes[0] = hashes[1] = 0xffffffff;
 826                 goto done;
 827         }
 828
 829         rxmode |= URE_RCR_AM;
 830         if_foreach_llmaddr(ifp, ure_hash_maddr, &hashes);
 831
 832         h = bswap32(hashes[0]);
 833         hashes[0] = bswap32(hashes[1]);
 834         hashes[1] = h;
 835         rxmode |= URE_RCR_AM;
 836
 837 done:
 838         ure_write_4(sc, URE_PLA_MAR0, URE_MCU_TYPE_PLA, hashes[0]);
 839         ure_write_4(sc, URE_PLA_MAR4, URE_MCU_TYPE_PLA, hashes[1]);
 840         ure_write_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, rxmode);
 841 }
 842
 843 static void
 844 ure_start(struct usb_ether *ue)
 845 {
 846         struct ure_softc *sc = uether_getsc(ue);
 847
 848         /*
 849          * start the USB transfers, if not already started:
 850          */
 851         usbd_transfer_start(sc->sc_xfer[URE_BULK_DT_RD]);
 852         usbd_transfer_start(sc->sc_xfer[URE_BULK_DT_WR]);
 853 }
 854
 855 static void
 856 ure_reset(struct ure_softc *sc)
 857 {
 858         int i;
 859
 860         ure_write_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_RST);
 861
 862         for (i = 0; i < URE_TIMEOUT; i++) {
 863                 if (!(ure_read_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA) &
 864                     URE_CR_RST))
 865                         break;
 866                 uether_pause(&sc->sc_ue, hz / 100);
 867         }
 868         if (i == URE_TIMEOUT)
 869                 device_printf(sc->sc_ue.ue_dev, "reset never completed\n");
 870 }
 871
 872 /*
 873  * Set media options.
 874  */
 875 static int
 876 ure_ifmedia_upd(struct ifnet *ifp)
 877 {
 878         struct ure_softc *sc = ifp->if_softc;
 879         struct mii_data *mii = GET_MII(sc);
 880         struct mii_softc *miisc;
 881         int error;
 882
 883         URE_LOCK_ASSERT(sc, MA_OWNED);
 884
 885         LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
 886                 PHY_RESET(miisc);
 887         error = mii_mediachg(mii);
 888         return (error);
 889 }
 890
 891 /*
 892  * Report current media status.
 893  */
 894 static void
 895 ure_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
 896 {
 897         struct ure_softc *sc;
 898         struct mii_data *mii;
 899
 900         sc = ifp->if_softc;
 901         mii = GET_MII(sc);
 902
 903         URE_LOCK(sc);
 904         mii_pollstat(mii);
 905         ifmr->ifm_active = mii->mii_media_active;
 906         ifmr->ifm_status = mii->mii_media_status;
 907         URE_UNLOCK(sc);
 908 }
 909
 910 static int
 911 ure_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
 912 {
 913         struct usb_ether *ue = ifp->if_softc;
 914         struct ure_softc *sc;
 915         struct ifreq *ifr;
 916         int error, mask, reinit;
 917
 918         sc = uether_getsc(ue);
 919         ifr = (struct ifreq *)data;
 920         error = 0;
 921         reinit = 0;
 922         if (cmd == SIOCSIFCAP) {
 923                 URE_LOCK(sc);
 924                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
 925                 if (reinit > 0 && ifp->if_drv_flags & IFF_DRV_RUNNING)
 926                         ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
 927                 else
 928                         reinit = 0;
 929                 URE_UNLOCK(sc);
 930                 if (reinit > 0)
 931                         uether_init(ue);
 932         } else
 933                 error = uether_ioctl(ifp, cmd, data);
 934
 935         return (error);
 936 }
 937
 938 static void
 939 ure_rtl8152_init(struct ure_softc *sc)
 940 {
 941         uint32_t pwrctrl;
 942
 943         /* Disable ALDPS. */
 944         ure_ocp_reg_write(sc, URE_OCP_ALDPS_CONFIG, URE_ENPDNPS | URE_LINKENA |
 945             URE_DIS_SDSAVE);
 946         uether_pause(&sc->sc_ue, hz / 50);
 947
 948         if (sc->sc_chip & URE_CHIP_VER_4C00) {
 949                 ure_write_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA,
 950                     ure_read_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA) &
 951                     ~URE_LED_MODE_MASK);
 952         }
 953
 954         ure_write_2(sc, URE_USB_UPS_CTRL, URE_MCU_TYPE_USB,
 955             ure_read_2(sc, URE_USB_UPS_CTRL, URE_MCU_TYPE_USB) &
 956             ~URE_POWER_CUT);
 957         ure_write_2(sc, URE_USB_PM_CTRL_STATUS, URE_MCU_TYPE_USB,
 958             ure_read_2(sc, URE_USB_PM_CTRL_STATUS, URE_MCU_TYPE_USB) &
 959             ~URE_RESUME_INDICATE);
 960
 961         ure_write_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA,
 962             ure_read_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA) |
 963             URE_TX_10M_IDLE_EN | URE_PFM_PWM_SWITCH);
 964         pwrctrl = ure_read_4(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA);
 965         pwrctrl &= ~URE_MCU_CLK_RATIO_MASK;
 966         pwrctrl |= URE_MCU_CLK_RATIO | URE_D3_CLK_GATED_EN;
 967         ure_write_4(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, pwrctrl);
 968         ure_write_2(sc, URE_PLA_GPHY_INTR_IMR, URE_MCU_TYPE_PLA,
 969             URE_GPHY_STS_MSK | URE_SPEED_DOWN_MSK | URE_SPDWN_RXDV_MSK |
 970             URE_SPDWN_LINKCHG_MSK);
 971
 972         /* Disable Rx aggregation. */
 973         ure_write_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB,
 974             ure_read_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB) |
 975             URE_RX_AGG_DISABLE);
 976
 977         /* Disable ALDPS. */
 978         ure_ocp_reg_write(sc, URE_OCP_ALDPS_CONFIG, URE_ENPDNPS | URE_LINKENA |
 979             URE_DIS_SDSAVE);
 980         uether_pause(&sc->sc_ue, hz / 50);
 981
 982         ure_init_fifo(sc);
 983
 984         ure_write_1(sc, URE_USB_TX_AGG, URE_MCU_TYPE_USB,
 985             URE_TX_AGG_MAX_THRESHOLD);
 986         ure_write_4(sc, URE_USB_RX_BUF_TH, URE_MCU_TYPE_USB, URE_RX_THR_HIGH);
 987         ure_write_4(sc, URE_USB_TX_DMA, URE_MCU_TYPE_USB,
 988             URE_TEST_MODE_DISABLE | URE_TX_SIZE_ADJUST1);
 989 }
 990
 991 static void
 992 ure_rtl8153_init(struct ure_softc *sc)
 993 {
 994         uint16_t val;
 995         uint8_t u1u2[8];
 996         int i;
 997
 998         /* Disable ALDPS. */
 999         ure_ocp_reg_write(sc, URE_OCP_POWER_CFG,
1000             ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) & ~URE_EN_ALDPS);
1001         uether_pause(&sc->sc_ue, hz / 50);
1002
1003         memset(u1u2, 0x00, sizeof(u1u2));
1004         ure_write_mem(sc, URE_USB_TOLERANCE,
1005             URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2));
1006
1007         for (i = 0; i < URE_TIMEOUT; i++) {
1008                 if (ure_read_2(sc, URE_PLA_BOOT_CTRL, URE_MCU_TYPE_PLA) &
1009                     URE_AUTOLOAD_DONE)
1010                         break;
1011                 uether_pause(&sc->sc_ue, hz / 100);
1012         }
1013         if (i == URE_TIMEOUT)
1014                 device_printf(sc->sc_ue.ue_dev,
1015                     "timeout waiting for chip autoload\n");
1016
1017         for (i = 0; i < URE_TIMEOUT; i++) {
1018                 val = ure_ocp_reg_read(sc, URE_OCP_PHY_STATUS) &
1019                     URE_PHY_STAT_MASK;
1020                 if (val == URE_PHY_STAT_LAN_ON || val == URE_PHY_STAT_PWRDN)
1021                         break;
1022                 uether_pause(&sc->sc_ue, hz / 100);
1023         }
1024         if (i == URE_TIMEOUT)
1025                 device_printf(sc->sc_ue.ue_dev,
1026                     "timeout waiting for phy to stabilize\n");
1027
1028         ure_write_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB,
1029             ure_read_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB) &
1030             ~URE_U2P3_ENABLE);
1031
1032         if (sc->sc_chip & URE_CHIP_VER_5C10) {
1033                 val = ure_read_2(sc, URE_USB_SSPHYLINK2, URE_MCU_TYPE_USB);
1034                 val &= ~URE_PWD_DN_SCALE_MASK;
1035                 val |= URE_PWD_DN_SCALE(96);
1036                 ure_write_2(sc, URE_USB_SSPHYLINK2, URE_MCU_TYPE_USB, val);
1037
1038                 ure_write_1(sc, URE_USB_USB2PHY, URE_MCU_TYPE_USB,
1039                     ure_read_1(sc, URE_USB_USB2PHY, URE_MCU_TYPE_USB) |
1040                     URE_USB2PHY_L1 | URE_USB2PHY_SUSPEND);
1041         } else if (sc->sc_chip & URE_CHIP_VER_5C20) {
1042                 ure_write_1(sc, URE_PLA_DMY_REG0, URE_MCU_TYPE_PLA,
1043                     ure_read_1(sc, URE_PLA_DMY_REG0, URE_MCU_TYPE_PLA) &
1044                     ~URE_ECM_ALDPS);
1045         }
1046         if (sc->sc_chip & (URE_CHIP_VER_5C20 | URE_CHIP_VER_5C30)) {
1047                 val = ure_read_1(sc, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB);
1048                 if (ure_read_2(sc, URE_USB_BURST_SIZE, URE_MCU_TYPE_USB) ==
1049                     0)
1050                         val &= ~URE_DYNAMIC_BURST;
1051                 else
1052                         val |= URE_DYNAMIC_BURST;
1053                 ure_write_1(sc, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB, val);
1054         }
1055
1056         ure_write_1(sc, URE_USB_CSR_DUMMY2, URE_MCU_TYPE_USB,
1057             ure_read_1(sc, URE_USB_CSR_DUMMY2, URE_MCU_TYPE_USB) |
1058             URE_EP4_FULL_FC);
1059
1060         ure_write_2(sc, URE_USB_WDT11_CTRL, URE_MCU_TYPE_USB,
1061             ure_read_2(sc, URE_USB_WDT11_CTRL, URE_MCU_TYPE_USB) &
1062             ~URE_TIMER11_EN);
1063
1064         ure_write_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA,
1065             ure_read_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA) &
1066             ~URE_LED_MODE_MASK);
1067
1068         if ((sc->sc_chip & URE_CHIP_VER_5C10) &&
1069             usbd_get_speed(sc->sc_ue.ue_udev) != USB_SPEED_SUPER)
1070                 val = URE_LPM_TIMER_500MS;
1071         else
1072                 val = URE_LPM_TIMER_500US;
1073         ure_write_1(sc, URE_USB_LPM_CTRL, URE_MCU_TYPE_USB,
1074             val | URE_FIFO_EMPTY_1FB | URE_ROK_EXIT_LPM);
1075
1076         val = ure_read_2(sc, URE_USB_AFE_CTRL2, URE_MCU_TYPE_USB);
1077         val &= ~URE_SEN_VAL_MASK;
1078         val |= URE_SEN_VAL_NORMAL | URE_SEL_RXIDLE;
1079         ure_write_2(sc, URE_USB_AFE_CTRL2, URE_MCU_TYPE_USB, val);
1080
1081         ure_write_2(sc, URE_USB_CONNECT_TIMER, URE_MCU_TYPE_USB, 0x0001);
1082
1083         ure_write_2(sc, URE_USB_POWER_CUT, URE_MCU_TYPE_USB,
1084             ure_read_2(sc, URE_USB_POWER_CUT, URE_MCU_TYPE_USB) &
1085             ~(URE_PWR_EN | URE_PHASE2_EN));
1086         ure_write_2(sc, URE_USB_MISC_0, URE_MCU_TYPE_USB,
1087             ure_read_2(sc, URE_USB_MISC_0, URE_MCU_TYPE_USB) &
1088             ~URE_PCUT_STATUS);
1089
1090         memset(u1u2, 0xff, sizeof(u1u2));
1091         ure_write_mem(sc, URE_USB_TOLERANCE,
1092             URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2));
1093
1094         ure_write_2(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA,
1095             URE_ALDPS_SPDWN_RATIO);
1096         ure_write_2(sc, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_PLA,
1097             URE_EEE_SPDWN_RATIO);
1098         ure_write_2(sc, URE_PLA_MAC_PWR_CTRL3, URE_MCU_TYPE_PLA,
1099             URE_PKT_AVAIL_SPDWN_EN | URE_SUSPEND_SPDWN_EN |
1100             URE_U1U2_SPDWN_EN | URE_L1_SPDWN_EN);
1101         ure_write_2(sc, URE_PLA_MAC_PWR_CTRL4, URE_MCU_TYPE_PLA,
1102             URE_PWRSAVE_SPDWN_EN | URE_RXDV_SPDWN_EN | URE_TX10MIDLE_EN |
1103             URE_TP100_SPDWN_EN | URE_TP500_SPDWN_EN | URE_TP1000_SPDWN_EN |
1104             URE_EEE_SPDWN_EN);
1105
1106         val = ure_read_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB);
1107         if (!(sc->sc_chip & (URE_CHIP_VER_5C00 | URE_CHIP_VER_5C10)))
1108                 val |= URE_U2P3_ENABLE;
1109         else
1110                 val &= ~URE_U2P3_ENABLE;
1111         ure_write_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, val);
1112
1113         memset(u1u2, 0x00, sizeof(u1u2));
1114         ure_write_mem(sc, URE_USB_TOLERANCE,
1115             URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2));
1116
1117         /* Disable ALDPS. */
1118         ure_ocp_reg_write(sc, URE_OCP_POWER_CFG,
1119             ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) & ~URE_EN_ALDPS);
1120         uether_pause(&sc->sc_ue, hz / 50);
1121
1122         ure_init_fifo(sc);
1123
1124         /* Disable Rx aggregation. */
1125         ure_write_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB,
1126             ure_read_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB) |
1127             URE_RX_AGG_DISABLE);
1128
1129         val = ure_read_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB);
1130         if (!(sc->sc_chip & (URE_CHIP_VER_5C00 | URE_CHIP_VER_5C10)))
1131                 val |= URE_U2P3_ENABLE;
1132         else
1133                 val &= ~URE_U2P3_ENABLE;
1134         ure_write_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, val);
1135
1136         memset(u1u2, 0xff, sizeof(u1u2));
1137         ure_write_mem(sc, URE_USB_TOLERANCE,
1138             URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2));
1139 }
1140
1141 static void
1142 ure_stop(struct usb_ether *ue)
1143 {
1144         struct ure_softc *sc = uether_getsc(ue);
1145         struct ifnet *ifp = uether_getifp(ue);
1146
1147         URE_LOCK_ASSERT(sc, MA_OWNED);
1148
1149         ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1150         sc->sc_flags &= ~URE_FLAG_LINK;
1151
1152         /*
1153          * stop all the transfers, if not already stopped:
1154          */
1155         usbd_transfer_stop(sc->sc_xfer[URE_BULK_DT_WR]);
1156         usbd_transfer_stop(sc->sc_xfer[URE_BULK_DT_RD]);
1157 }
1158
1159 static void
1160 ure_disable_teredo(struct ure_softc *sc)
1161 {
1162
1163         ure_write_4(sc, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA,
1164             ure_read_4(sc, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA) &
1165             ~(URE_TEREDO_SEL | URE_TEREDO_RS_EVENT_MASK | URE_OOB_TEREDO_EN));
1166         ure_write_2(sc, URE_PLA_WDT6_CTRL, URE_MCU_TYPE_PLA,
1167             URE_WDT6_SET_MODE);
1168         ure_write_2(sc, URE_PLA_REALWOW_TIMER, URE_MCU_TYPE_PLA, 0);
1169         ure_write_4(sc, URE_PLA_TEREDO_TIMER, URE_MCU_TYPE_PLA, 0);
1170 }
1171
1172 static void
1173 ure_init_fifo(struct ure_softc *sc)
1174 {
1175         uint32_t rx_fifo1, rx_fifo2;
1176         int i;
1177
1178         ure_write_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA,
1179             ure_read_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA) |
1180             URE_RXDY_GATED_EN);
1181
1182         ure_disable_teredo(sc);
1183
1184         ure_write_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA,
1185             ure_read_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA) &
1186             ~URE_RCR_ACPT_ALL);
1187
1188         if (!(sc->sc_flags & URE_FLAG_8152)) {
1189                 if (sc->sc_chip & (URE_CHIP_VER_5C00 | URE_CHIP_VER_5C10 |
1190                     URE_CHIP_VER_5C20)) {
1191                                 ure_ocp_reg_write(sc, URE_OCP_ADC_CFG,
1192                                     URE_CKADSEL_L | URE_ADC_EN | URE_EN_EMI_L);
1193                 }
1194                 if (sc->sc_chip & URE_CHIP_VER_5C00) {
1195                         ure_ocp_reg_write(sc, URE_OCP_EEE_CFG,
1196                             ure_ocp_reg_read(sc, URE_OCP_EEE_CFG) &
1197                             ~URE_CTAP_SHORT_EN);
1198                 }
1199                 ure_ocp_reg_write(sc, URE_OCP_POWER_CFG,
1200                     ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) |
1201                     URE_EEE_CLKDIV_EN);
1202                 ure_ocp_reg_write(sc, URE_OCP_DOWN_SPEED,
1203                     ure_ocp_reg_read(sc, URE_OCP_DOWN_SPEED) |
1204                     URE_EN_10M_BGOFF);
1205                 ure_ocp_reg_write(sc, URE_OCP_POWER_CFG,
1206                     ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) |
1207                     URE_EN_10M_PLLOFF);
1208                 ure_ocp_reg_write(sc, URE_OCP_SRAM_ADDR, URE_SRAM_IMPEDANCE);
1209                 ure_ocp_reg_write(sc, URE_OCP_SRAM_DATA, 0x0b13);
1210                 ure_write_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA,
1211                     ure_read_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA) |
1212                     URE_PFM_PWM_SWITCH);
1213
1214                 /* Enable LPF corner auto tune. */
1215                 ure_ocp_reg_write(sc, URE_OCP_SRAM_ADDR, URE_SRAM_LPF_CFG);
1216                 ure_ocp_reg_write(sc, URE_OCP_SRAM_DATA, 0xf70f);
1217
1218                 /* Adjust 10M amplitude. */
1219                 ure_ocp_reg_write(sc, URE_OCP_SRAM_ADDR, URE_SRAM_10M_AMP1);
1220                 ure_ocp_reg_write(sc, URE_OCP_SRAM_DATA, 0x00af);
1221                 ure_ocp_reg_write(sc, URE_OCP_SRAM_ADDR, URE_SRAM_10M_AMP2);
1222                 ure_ocp_reg_write(sc, URE_OCP_SRAM_DATA, 0x0208);
1223         }
1224
1225         ure_reset(sc);
1226
1227         ure_write_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, 0);
1228
1229         ure_write_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA,
1230             ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) &
1231             ~URE_NOW_IS_OOB);
1232
1233         ure_write_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA,
1234             ure_read_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA) &
1235             ~URE_MCU_BORW_EN);
1236         for (i = 0; i < URE_TIMEOUT; i++) {
1237                 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) &
1238                     URE_LINK_LIST_READY)
1239                         break;
1240                 uether_pause(&sc->sc_ue, hz / 100);
1241         }
1242         if (i == URE_TIMEOUT)
1243                 device_printf(sc->sc_ue.ue_dev,
1244                     "timeout waiting for OOB control\n");
1245         ure_write_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA,
1246             ure_read_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA) |
1247             URE_RE_INIT_LL);
1248         for (i = 0; i < URE_TIMEOUT; i++) {
1249                 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) &
1250                     URE_LINK_LIST_READY)
1251                         break;
1252                 uether_pause(&sc->sc_ue, hz / 100);
1253         }
1254         if (i == URE_TIMEOUT)
1255                 device_printf(sc->sc_ue.ue_dev,
1256                     "timeout waiting for OOB control\n");
1257
1258         ure_write_2(sc, URE_PLA_CPCR, URE_MCU_TYPE_PLA,
1259             ure_read_2(sc, URE_PLA_CPCR, URE_MCU_TYPE_PLA) &
1260             ~URE_CPCR_RX_VLAN);
1261         ure_write_2(sc, URE_PLA_TCR0, URE_MCU_TYPE_PLA,
1262             ure_read_2(sc, URE_PLA_TCR0, URE_MCU_TYPE_PLA) |
1263             URE_TCR0_AUTO_FIFO);
1264
1265         /* Configure Rx FIFO threshold. */
1266         ure_write_4(sc, URE_PLA_RXFIFO_CTRL0, URE_MCU_TYPE_PLA,
1267             URE_RXFIFO_THR1_NORMAL);
1268         if (usbd_get_speed(sc->sc_ue.ue_udev) == USB_SPEED_FULL) {
1269                 rx_fifo1 = URE_RXFIFO_THR2_FULL;
1270                 rx_fifo2 = URE_RXFIFO_THR3_FULL;
1271         } else {
1272                 rx_fifo1 = URE_RXFIFO_THR2_HIGH;
1273                 rx_fifo2 = URE_RXFIFO_THR3_HIGH;
1274         }
1275         ure_write_4(sc, URE_PLA_RXFIFO_CTRL1, URE_MCU_TYPE_PLA, rx_fifo1);
1276         ure_write_4(sc, URE_PLA_RXFIFO_CTRL2, URE_MCU_TYPE_PLA, rx_fifo2);
1277
1278         /* Configure Tx FIFO threshold. */
1279         ure_write_4(sc, URE_PLA_TXFIFO_CTRL, URE_MCU_TYPE_PLA,
1280             URE_TXFIFO_THR_NORMAL);
1281 }