sys/gnu/dts/arm/imx6qdl-colibri.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
   2 /*
   3  * Copyright 2014-2020 Toradex
   4  * Copyright 2012 Freescale Semiconductor, Inc.
   5  * Copyright 2011 Linaro Ltd.
   6  */
   7
   8 #include <dt-bindings/gpio/gpio.h>
   9
  10 / {
  11         model = "Toradex Colibri iMX6DL/S Module";
  12         compatible = "toradex,colibri_imx6dl", "fsl,imx6dl";
  13
  14         backlight: backlight {
  15                 compatible = "pwm-backlight";
  16                 pinctrl-names = "default";
  17                 pinctrl-0 = <&pinctrl_gpio_bl_on>;
  18                 pwms = <&pwm3 0 5000000>;
  19                 enable-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>; /* Colibri BL_ON */
  20                 status = "disabled";
  21         };
  22
  23         reg_module_3v3: regulator-module-3v3 {
  24                 compatible = "regulator-fixed";
  25                 regulator-name = "+V3.3";
  26                 regulator-min-microvolt = <3300000>;
  27                 regulator-max-microvolt = <3300000>;
  28                 regulator-always-on;
  29         };
  30
  31         reg_module_3v3_audio: regulator-module-3v3-audio {
  32                 compatible = "regulator-fixed";
  33                 regulator-name = "+V3.3_AUDIO";
  34                 regulator-min-microvolt = <3300000>;
  35                 regulator-max-microvolt = <3300000>;
  36                 regulator-always-on;
  37         };
  38
  39         reg_usb_host_vbus: regulator-usb-host-vbus {
  40                 compatible = "regulator-fixed";
  41                 pinctrl-names = "default";
  42                 pinctrl-0 = <&pinctrl_regulator_usbh_pwr>;
  43                 regulator-name = "usb_host_vbus";
  44                 regulator-min-microvolt = <5000000>;
  45                 regulator-max-microvolt = <5000000>;
  46                 gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; /* USBH_PEN */
  47                 status = "disabled";
  48         };
  49
  50         sound {
  51                 compatible = "fsl,imx-audio-sgtl5000";
  52                 model = "imx6dl-colibri-sgtl5000";
  53                 ssi-controller = <&ssi1>;
  54                 audio-codec = <&codec>;
  55                 audio-routing =
  56                         "Headphone Jack", "HP_OUT",
  57                         "LINE_IN", "Line In Jack",
  58                         "MIC_IN", "Mic Jack",
  59                         "Mic Jack", "Mic Bias";
  60                 mux-int-port = <1>;
  61                 mux-ext-port = <5>;
  62         };
  63
  64         /* Optional S/PDIF in on SODIMM 88 and out on SODIMM 90, 137 or 168 */
  65         sound_spdif: sound-spdif {
  66                 compatible = "fsl,imx-audio-spdif";
  67                 model = "imx-spdif";
  68                 spdif-controller = <&spdif>;
  69                 spdif-in;
  70                 spdif-out;
  71                 status = "disabled";
  72         };
  73 };
  74
  75 &audmux {
  76         pinctrl-names = "default";
  77         pinctrl-0 = <&pinctrl_audmux &pinctrl_mic_gnd>;
  78         status = "okay";
  79 };
  80
  81 /* Optional on SODIMM 55/63 */
  82 &can1 {
  83         pinctrl-names = "default";
  84         pinctrl-0 = <&pinctrl_flexcan1>;
  85         status = "disabled";
  86 };
  87
  88 /* Optional on SODIMM 178/188 */
  89 &can2 {
  90         pinctrl-names = "default";
  91         pinctrl-0 = <&pinctrl_flexcan2>;
  92         status = "disabled";
  93 };
  94
  95 /* Colibri SSP */
  96 &ecspi4 {
  97         cs-gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>;
  98         pinctrl-names = "default";
  99         pinctrl-0 = <&pinctrl_ecspi4>;
 100         status = "disabled";
 101 };
 102
 103 &fec {
 104         pinctrl-names = "default";
 105         pinctrl-0 = <&pinctrl_enet>;
 106         phy-mode = "rmii";
 107         phy-handle = <&ethphy>;
 108         status = "okay";
 109
 110         mdio {
 111                 #address-cells = <1>;
 112                 #size-cells = <0>;
 113
 114                 ethphy: ethernet-phy@0 {
 115                         reg = <0>;
 116                         micrel,led-mode = <0>;
 117                 };
 118         };
 119 };
 120
 121 &hdmi {
 122         pinctrl-names = "default";
 123         pinctrl-0 = <&pinctrl_hdmi_ddc>;
 124         status = "disabled";
 125 };
 126
 127 /*
 128  * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
 129  * touch screen controller
 130  */
 131 &i2c2 {
 132         clock-frequency = <100000>;
 133         pinctrl-names = "default", "gpio";
 134         pinctrl-0 = <&pinctrl_i2c2>;
 135         pinctrl-0 = <&pinctrl_i2c2_gpio>;
 136         scl-gpios = <&gpio2 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 137         sda-gpios = <&gpio3 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 138         status = "okay";
 139
 140         pmic: pfuze100@8 {
 141                 compatible = "fsl,pfuze100";
 142                 reg = <0x08>;
 143
 144                 regulators {
 145                         sw1a_reg: sw1ab {
 146                                 regulator-min-microvolt = <300000>;
 147                                 regulator-max-microvolt = <1875000>;
 148                                 regulator-boot-on;
 149                                 regulator-always-on;
 150                                 regulator-ramp-delay = <6250>;
 151                         };
 152
 153                         sw1c_reg: sw1c {
 154                                 regulator-min-microvolt = <300000>;
 155                                 regulator-max-microvolt = <1875000>;
 156                                 regulator-boot-on;
 157                                 regulator-always-on;
 158                                 regulator-ramp-delay = <6250>;
 159                         };
 160
 161                         sw3a_reg: sw3a {
 162                                 regulator-min-microvolt = <400000>;
 163                                 regulator-max-microvolt = <1975000>;
 164                                 regulator-boot-on;
 165                                 regulator-always-on;
 166                         };
 167
 168                         swbst_reg: swbst {
 169                                 regulator-min-microvolt = <5000000>;
 170                                 regulator-max-microvolt = <5150000>;
 171                                 regulator-boot-on;
 172                                 regulator-always-on;
 173                         };
 174
 175                         snvs_reg: vsnvs {
 176                                 regulator-min-microvolt = <1000000>;
 177                                 regulator-max-microvolt = <3000000>;
 178                                 regulator-boot-on;
 179                                 regulator-always-on;
 180                         };
 181
 182                         vref_reg: vrefddr {
 183                                 regulator-boot-on;
 184                                 regulator-always-on;
 185                         };
 186
 187                         /* vgen1: unused */
 188
 189                         vgen2_reg: vgen2 {
 190                                 regulator-min-microvolt = <800000>;
 191                                 regulator-max-microvolt = <1550000>;
 192                                 regulator-boot-on;
 193                                 regulator-always-on;
 194                         };
 195
 196                         /* vgen3: unused */
 197
 198                         vgen4_reg: vgen4 {
 199                                 regulator-min-microvolt = <1800000>;
 200                                 regulator-max-microvolt = <1800000>;
 201                                 regulator-boot-on;
 202                                 regulator-always-on;
 203                         };
 204
 205                         vgen5_reg: vgen5 {
 206                                 regulator-min-microvolt = <1800000>;
 207                                 regulator-max-microvolt = <3300000>;
 208                                 regulator-boot-on;
 209                                 regulator-always-on;
 210                         };
 211
 212                         vgen6_reg: vgen6 {
 213                                 regulator-min-microvolt = <1800000>;
 214                                 regulator-max-microvolt = <3300000>;
 215                                 regulator-boot-on;
 216                                 regulator-always-on;
 217                         };
 218                 };
 219         };
 220
 221         codec: sgtl5000@a {
 222                 compatible = "fsl,sgtl5000";
 223                 reg = <0x0a>;
 224                 clocks = <&clks IMX6QDL_CLK_CKO>;
 225                 VDDA-supply = <&reg_module_3v3_audio>;
 226                 VDDIO-supply = <&reg_module_3v3>;
 227                 VDDD-supply = <&vgen4_reg>;
 228                 lrclk-strength = <3>;
 229         };
 230
 231         /* STMPE811 touch screen controller */
 232         stmpe811@41 {
 233                 compatible = "st,stmpe811";
 234                 pinctrl-names = "default";
 235                 pinctrl-0 = <&pinctrl_touch_int>;
 236                 reg = <0x41>;
 237                 interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
 238                 interrupt-parent = <&gpio6>;
 239                 interrupt-controller;
 240                 id = <0>;
 241                 blocks = <0x5>;
 242                 irq-trigger = <0x1>;
 243                 /* 3.25 MHz ADC clock speed */
 244                 st,adc-freq = <1>;
 245                 /* 12-bit ADC */
 246                 st,mod-12b = <1>;
 247                 /* internal ADC reference */
 248                 st,ref-sel = <0>;
 249                 /* ADC converstion time: 80 clocks */
 250                 st,sample-time = <4>;
 251
 252                 stmpe_touchscreen {
 253                         compatible = "st,stmpe-ts";
 254                         /* 8 sample average control */
 255                         st,ave-ctrl = <3>;
 256                         /* 7 length fractional part in z */
 257                         st,fraction-z = <7>;
 258                         /*
 259                          * 50 mA typical 80 mA max touchscreen drivers
 260                          * current limit value
 261                          */
 262                         st,i-drive = <1>;
 263                         /* 1 ms panel driver settling time */
 264                         st,settling = <3>;
 265                         /* 5 ms touch detect interrupt delay */
 266                         st,touch-det-delay = <5>;
 267                 };
 268
 269                 stmpe_adc {
 270                         compatible = "st,stmpe-adc";
 271                         /* forbid to use ADC channels 3-0 (touch) */
 272                         st,norequest-mask = <0x0F>;
 273                 };
 274         };
 275 };
 276
 277 /*
 278  * I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board)
 279  */
 280 &i2c3 {
 281         clock-frequency = <100000>;
 282         pinctrl-names = "default", "gpio";
 283         pinctrl-0 = <&pinctrl_i2c3>;
 284         pinctrl-1 = <&pinctrl_i2c3_gpio>;
 285         scl-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 286         sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 287         status = "disabled";
 288 };
 289
 290 /* Colibri PWM<B> */
 291 &pwm1 {
 292         pinctrl-names = "default";
 293         pinctrl-0 = <&pinctrl_pwm1>;
 294         status = "disabled";
 295 };
 296
 297 /* Colibri PWM<D> */
 298 &pwm2 {
 299         pinctrl-names = "default";
 300         pinctrl-0 = <&pinctrl_pwm2>;
 301         status = "disabled";
 302 };
 303
 304 /* Colibri PWM<A> */
 305 &pwm3 {
 306         pinctrl-names = "default";
 307         pinctrl-0 = <&pinctrl_pwm3>;
 308         status = "disabled";
 309 };
 310
 311 /* Colibri PWM<C> */
 312 &pwm4 {
 313         pinctrl-names = "default";
 314         pinctrl-0 = <&pinctrl_pwm4>;
 315         status = "disabled";
 316 };
 317
 318 /* Optional S/PDIF out on SODIMM 137 */
 319 &spdif {
 320         pinctrl-names = "default";
 321         pinctrl-0 = <&pinctrl_spdif>;
 322         status = "disabled";
 323 };
 324
 325 &ssi1 {
 326         status = "okay";
 327 };
 328
 329 /* Colibri UART_A */
 330 &uart1 {
 331         pinctrl-names = "default";
 332         pinctrl-0 = <&pinctrl_uart1_dte &pinctrl_uart1_ctrl>;
 333         fsl,dte-mode;
 334         uart-has-rtscts;
 335         status = "disabled";
 336 };
 337
 338 /* Colibri UART_B */
 339 &uart2 {
 340         pinctrl-names = "default";
 341         pinctrl-0 = <&pinctrl_uart2_dte>;
 342         fsl,dte-mode;
 343         uart-has-rtscts;
 344         status = "disabled";
 345 };
 346
 347 /* Colibri UART_C */
 348 &uart3 {
 349         pinctrl-names = "default";
 350         pinctrl-0 = <&pinctrl_uart3_dte>;
 351         fsl,dte-mode;
 352         status = "disabled";
 353 };
 354
 355 &usbotg {
 356         pinctrl-names = "default";
 357         disable-over-current;
 358         dr_mode = "peripheral";
 359         status = "disabled";
 360 };
 361
 362 /* Colibri MMC */
 363 &usdhc1 {
 364         pinctrl-names = "default";
 365         pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_mmc_cd>;
 366         cd-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; /* MMCD */
 367         disable-wp;
 368         vqmmc-supply = <&reg_module_3v3>;
 369         bus-width = <4>;
 370         no-1-8-v;
 371         status = "disabled";
 372 };
 373
 374 /* eMMC */
 375 &usdhc3 {
 376         pinctrl-names = "default";
 377         pinctrl-0 = <&pinctrl_usdhc3>;
 378         vqmmc-supply = <&reg_module_3v3>;
 379         bus-width = <8>;
 380         no-1-8-v;
 381         non-removable;
 382         status = "okay";
 383 };
 384
 385 &weim {
 386         pinctrl-names = "default";
 387         pinctrl-0 = <&pinctrl_weim_sram  &pinctrl_weim_cs0
 388                      &pinctrl_weim_cs1   &pinctrl_weim_cs2
 389                      &pinctrl_weim_rdnwr &pinctrl_weim_npwe>;
 390         #address-cells = <2>;
 391         #size-cells = <1>;
 392         status = "disabled";
 393 };
 394
 395 &iomuxc {
 396         pinctrl-names = "default";
 397         pinctrl-0 = <&pinctrl_usbh_oc_1>;
 398
 399         pinctrl_audmux: audmuxgrp {
 400                 fsl,pins = <
 401                         MX6QDL_PAD_KEY_COL0__AUD5_TXC   0x130b0
 402                         MX6QDL_PAD_KEY_ROW0__AUD5_TXD   0x130b0
 403                         MX6QDL_PAD_KEY_COL1__AUD5_TXFS  0x130b0
 404                         MX6QDL_PAD_KEY_ROW1__AUD5_RXD   0x130b0
 405                         /* SGTL5000 sys_mclk */
 406                         MX6QDL_PAD_GPIO_0__CCM_CLKO1    0x000b0
 407                 >;
 408         };
 409
 410         pinctrl_cam_mclk: cammclkgrp {
 411                 fsl,pins = <
 412                         /* Parallel Camera CAM sys_mclk */
 413                         MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x00b0
 414                 >;
 415         };
 416
 417         pinctrl_ecspi4: ecspi4grp {
 418                 fsl,pins = <
 419                         MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1
 420                         MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1
 421                         MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1
 422                         /* SPI CS */
 423                         MX6QDL_PAD_EIM_A25__GPIO5_IO02  0x000b1
 424                 >;
 425         };
 426
 427         pinctrl_enet: enetgrp {
 428                 fsl,pins = <
 429                         MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
 430                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
 431                         MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0     0x1b0b0
 432                         MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1     0x1b0b0
 433                         MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER       0x1b0b0
 434                         MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN       0x1b0b0
 435                         MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0     0x1b0b0
 436                         MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1     0x1b0b0
 437                         MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN      0x1b0b0
 438                         MX6QDL_PAD_GPIO_16__ENET_REF_CLK     ((1<<30) | 0x1b0b0)
 439                 >;
 440         };
 441
 442         pinctrl_flexcan1: flexcan1grp {
 443                 fsl,pins = <
 444                         MX6QDL_PAD_GPIO_7__FLEXCAN1_TX          0x1b0b0
 445                         MX6QDL_PAD_GPIO_8__FLEXCAN1_RX          0x1b0b0
 446                 >;
 447         };
 448
 449         pinctrl_flexcan2: flexcan2grp {
 450                 fsl,pins = <
 451                         MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX        0x1b0b0
 452                         MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX        0x1b0b0
 453                 >;
 454         };
 455
 456         pinctrl_gpio_bl_on: gpioblon {
 457                 fsl,pins = <
 458                         MX6QDL_PAD_EIM_D26__GPIO3_IO26          0x1b0b0
 459                 >;
 460         };
 461
 462         pinctrl_gpio_keys: gpiokeys {
 463                 fsl,pins = <
 464                         MX6QDL_PAD_EIM_A16__GPIO2_IO22          0x130b0
 465                 >;
 466         };
 467
 468         pinctrl_hdmi_ddc: hdmiddcgrp {
 469                 fsl,pins = <
 470                         MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1
 471                         MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1
 472                 >;
 473         };
 474
 475         pinctrl_i2c2: i2c2grp {
 476                 fsl,pins = <
 477                         MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
 478                         MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
 479                 >;
 480         };
 481
 482         pinctrl_i2c2_gpio: i2c2grp {
 483                 fsl,pins = <
 484                         MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x4001b8b1
 485                         MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x4001b8b1
 486                 >;
 487         };
 488
 489         pinctrl_i2c3: i2c3grp {
 490                 fsl,pins = <
 491                         MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
 492                         MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
 493                 >;
 494         };
 495
 496         pinctrl_i2c3_gpio: i2c3gpiogrp {
 497                 fsl,pins = <
 498                         MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x4001b8b1
 499                         MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x4001b8b1
 500                 >;
 501         };
 502
 503         pinctrl_ipu1_csi0: ipu1csi0grp { /* Parallel Camera */
 504                 fsl,pins = <
 505                         MX6QDL_PAD_EIM_A17__IPU1_CSI1_DATA12    0xb0b1
 506                         MX6QDL_PAD_EIM_A18__IPU1_CSI1_DATA13    0xb0b1
 507                         MX6QDL_PAD_EIM_A19__IPU1_CSI1_DATA14    0xb0b1
 508                         MX6QDL_PAD_EIM_A20__IPU1_CSI1_DATA15    0xb0b1
 509                         MX6QDL_PAD_EIM_A21__IPU1_CSI1_DATA16    0xb0b1
 510                         MX6QDL_PAD_EIM_A22__IPU1_CSI1_DATA17    0xb0b1
 511                         MX6QDL_PAD_EIM_A23__IPU1_CSI1_DATA18    0xb0b1
 512                         MX6QDL_PAD_EIM_A24__IPU1_CSI1_DATA19    0xb0b1
 513                         MX6QDL_PAD_EIM_D17__IPU1_CSI1_PIXCLK    0xb0b1
 514                         MX6QDL_PAD_EIM_EB3__IPU1_CSI1_HSYNC     0xb0b1
 515                         MX6QDL_PAD_EIM_D29__IPU1_CSI1_VSYNC     0xb0b1
 516                         /* Disable PWM pins on camera interface */
 517                         MX6QDL_PAD_SD4_DAT1__GPIO2_IO09         0x40
 518                         MX6QDL_PAD_GPIO_1__GPIO1_IO01           0x40
 519                 >;
 520         };
 521
 522         pinctrl_ipu1_lcdif: ipu1lcdifgrp {
 523                 fsl,pins = <
 524                         MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK      0xa1
 525                         MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15            0xa1
 526                         MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02             0xa1
 527                         MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03             0xa1
 528                         MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00        0xa1
 529                         MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01        0xa1
 530                         MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02        0xa1
 531                         MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03        0xa1
 532                         MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04        0xa1
 533                         MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05        0xa1
 534                         MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06        0xa1
 535                         MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07        0xa1
 536                         MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08        0xa1
 537                         MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09        0xa1
 538                         MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10       0xa1
 539                         MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11       0xa1
 540                         MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12       0xa1
 541                         MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13       0xa1
 542                         MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14       0xa1
 543                         MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15       0xa1
 544                         MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16       0xa1
 545                         MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17       0xa1
 546                 >;
 547         };
 548
 549         pinctrl_mic_gnd: gpiomicgnd {
 550                 fsl,pins = <
 551                         /* Controls Mic GND, PU or '1' pull Mic GND to GND */
 552                         MX6QDL_PAD_RGMII_TD1__GPIO6_IO21 0x1b0b0
 553                 >;
 554         };
 555
 556         pinctrl_mmc_cd: gpiommccd {
 557                 fsl,pins = <
 558                         MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x1b0b1
 559                 >;
 560         };
 561
 562         pinctrl_pwm1: pwm1grp {
 563                 fsl,pins = <
 564                         MX6QDL_PAD_GPIO_9__PWM1_OUT     0x1b0b1
 565                 >;
 566         };
 567
 568         pinctrl_pwm2: pwm2grp {
 569                 fsl,pins = <
 570                         MX6QDL_PAD_GPIO_1__PWM2_OUT     0x1b0b1
 571                         MX6QDL_PAD_EIM_A21__GPIO2_IO17  0x00040
 572                 >;
 573         };
 574
 575         pinctrl_pwm3: pwm3grp {
 576                 fsl,pins = <
 577                         MX6QDL_PAD_SD4_DAT1__PWM3_OUT   0x1b0b1
 578                         MX6QDL_PAD_EIM_A22__GPIO2_IO16  0x00040
 579                 >;
 580         };
 581
 582         pinctrl_pwm4: pwm4grp {
 583                 fsl,pins = <
 584                         MX6QDL_PAD_SD4_DAT2__PWM4_OUT   0x1b0b1
 585                 >;
 586         };
 587
 588         pinctrl_regulator_usbh_pwr: gpioregusbhpwrgrp {
 589                 fsl,pins = <
 590                         /* USBH_EN */
 591                         MX6QDL_PAD_EIM_D31__GPIO3_IO31  0x0f058
 592                 >;
 593         };
 594
 595         pinctrl_usbh_oc_1: usbhoc1grp {
 596                 fsl,pins = <
 597                         /* USBH_OC */
 598                         MX6QDL_PAD_EIM_D30__GPIO3_IO30          0x1b0b0
 599                 >;
 600         };
 601
 602         pinctrl_spdif: spdifgrp {
 603                 fsl,pins = <
 604                         MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0
 605                 >;
 606         };
 607
 608         pinctrl_touch_int: gpiotouchintgrp {
 609                 fsl,pins = <
 610                         /* STMPE811 interrupt */
 611                         MX6QDL_PAD_RGMII_TD0__GPIO6_IO20 0x1b0b0
 612                 >;
 613         };
 614
 615         pinctrl_uart1_dce: uart1dcegrp {
 616                 fsl,pins = <
 617                         MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
 618                         MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
 619                 >;
 620         };
 621
 622         /* DTE mode */
 623         pinctrl_uart1_dte: uart1dtegrp {
 624                 fsl,pins = <
 625                         MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x1b0b1
 626                         MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x1b0b1
 627                         MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x1b0b1
 628                         MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x1b0b1
 629                 >;
 630         };
 631
 632         /* Additional DTR, DSR, DCD */
 633         pinctrl_uart1_ctrl: uart1ctrlgrp {
 634                 fsl,pins = <
 635                         MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x1b0b0
 636                         MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x1b0b0
 637                         MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x1b0b0
 638                 >;
 639         };
 640
 641         pinctrl_uart2_dte: uart2dtegrp {
 642                 fsl,pins = <
 643                         MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA      0x1b0b1
 644                         MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA      0x1b0b1
 645                         MX6QDL_PAD_SD4_DAT6__UART2_RTS_B        0x1b0b1
 646                         MX6QDL_PAD_SD4_DAT5__UART2_CTS_B        0x1b0b1
 647                 >;
 648         };
 649
 650         pinctrl_uart3_dte: uart3dtegrp {
 651                 fsl,pins = <
 652                         MX6QDL_PAD_SD4_CLK__UART3_TX_DATA       0x1b0b1
 653                         MX6QDL_PAD_SD4_CMD__UART3_RX_DATA       0x1b0b1
 654                 >;
 655         };
 656
 657         pinctrl_usbc_det: usbcdetgrp {
 658                 fsl,pins = <
 659                         /* USBC_DET */
 660                         MX6QDL_PAD_GPIO_17__GPIO7_IO12          0x1b0b0
 661                         /* USBC_DET_EN */
 662                         MX6QDL_PAD_RGMII_TX_CTL__GPIO6_IO26     0x0f058
 663                         /* USBC_DET_OVERWRITE */
 664                         MX6QDL_PAD_RGMII_RXC__GPIO6_IO30        0x0f058
 665                 >;
 666         };
 667
 668         pinctrl_usbc_id_1: usbc_id-1 {
 669                 fsl,pins = <
 670                         /* USBC_ID */
 671                         MX6QDL_PAD_NANDF_D2__GPIO2_IO02         0x1b0b0
 672                 >;
 673         };
 674
 675         pinctrl_usdhc1: usdhc1grp {
 676                 fsl,pins = <
 677                         MX6QDL_PAD_SD1_CMD__SD1_CMD     0x17071
 678                         MX6QDL_PAD_SD1_CLK__SD1_CLK     0x10071
 679                         MX6QDL_PAD_SD1_DAT0__SD1_DATA0  0x17071
 680                         MX6QDL_PAD_SD1_DAT1__SD1_DATA1  0x17071
 681                         MX6QDL_PAD_SD1_DAT2__SD1_DATA2  0x17071
 682                         MX6QDL_PAD_SD1_DAT3__SD1_DATA3  0x17071
 683                 >;
 684         };
 685
 686         pinctrl_usdhc3: usdhc3grp {
 687                 fsl,pins = <
 688                         MX6QDL_PAD_SD3_CMD__SD3_CMD     0x17059
 689                         MX6QDL_PAD_SD3_CLK__SD3_CLK     0x10059
 690                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0  0x17059
 691                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1  0x17059
 692                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2  0x17059
 693                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3  0x17059
 694                         MX6QDL_PAD_SD3_DAT4__SD3_DATA4  0x17059
 695                         MX6QDL_PAD_SD3_DAT5__SD3_DATA5  0x17059
 696                         MX6QDL_PAD_SD3_DAT6__SD3_DATA6  0x17059
 697                         MX6QDL_PAD_SD3_DAT7__SD3_DATA7  0x17059
 698                         /* eMMC reset */
 699                         MX6QDL_PAD_SD3_RST__SD3_RESET   0x17059
 700                 >;
 701         };
 702
 703         pinctrl_weim_cs0: weimcs0grp {
 704                 fsl,pins = <
 705                         /* nEXT_CS0 */
 706                         MX6QDL_PAD_EIM_CS0__EIM_CS0_B   0xb0b1
 707                 >;
 708         };
 709
 710         pinctrl_weim_cs1: weimcs1grp {
 711                 fsl,pins = <
 712                         /* nEXT_CS1 */
 713                         MX6QDL_PAD_EIM_CS1__EIM_CS1_B   0xb0b1
 714                 >;
 715         };
 716
 717         pinctrl_weim_cs2: weimcs2grp {
 718                 fsl,pins = <
 719                         /* nEXT_CS2 */
 720                         MX6QDL_PAD_SD2_DAT1__EIM_CS2_B  0xb0b1
 721                 >;
 722         };
 723
 724         pinctrl_weim_sram: weimsramgrp {
 725                 fsl,pins = <
 726                         MX6QDL_PAD_EIM_OE__EIM_OE_B             0xb0b1
 727                         MX6QDL_PAD_EIM_RW__EIM_RW               0xb0b1
 728                         /* Data */
 729                         MX6QDL_PAD_CSI0_DATA_EN__EIM_DATA00     0x1b0b0
 730                         MX6QDL_PAD_CSI0_VSYNC__EIM_DATA01       0x1b0b0
 731                         MX6QDL_PAD_CSI0_DAT4__EIM_DATA02        0x1b0b0
 732                         MX6QDL_PAD_CSI0_DAT5__EIM_DATA03        0x1b0b0
 733                         MX6QDL_PAD_CSI0_DAT6__EIM_DATA04        0x1b0b0
 734                         MX6QDL_PAD_CSI0_DAT7__EIM_DATA05        0x1b0b0
 735                         MX6QDL_PAD_CSI0_DAT8__EIM_DATA06        0x1b0b0
 736                         MX6QDL_PAD_CSI0_DAT9__EIM_DATA07        0x1b0b0
 737                         MX6QDL_PAD_CSI0_DAT12__EIM_DATA08       0x1b0b0
 738                         MX6QDL_PAD_CSI0_DAT13__EIM_DATA09       0x1b0b0
 739                         MX6QDL_PAD_CSI0_DAT14__EIM_DATA10       0x1b0b0
 740                         MX6QDL_PAD_CSI0_DAT15__EIM_DATA11       0x1b0b0
 741                         MX6QDL_PAD_CSI0_DAT16__EIM_DATA12       0x1b0b0
 742                         MX6QDL_PAD_CSI0_DAT17__EIM_DATA13       0x1b0b0
 743                         MX6QDL_PAD_CSI0_DAT18__EIM_DATA14       0x1b0b0
 744                         MX6QDL_PAD_CSI0_DAT19__EIM_DATA15       0x1b0b0
 745                         /* Address */
 746                         MX6QDL_PAD_EIM_DA15__EIM_AD15           0xb0b1
 747                         MX6QDL_PAD_EIM_DA14__EIM_AD14           0xb0b1
 748                         MX6QDL_PAD_EIM_DA13__EIM_AD13           0xb0b1
 749                         MX6QDL_PAD_EIM_DA12__EIM_AD12           0xb0b1
 750                         MX6QDL_PAD_EIM_DA11__EIM_AD11           0xb0b1
 751                         MX6QDL_PAD_EIM_DA10__EIM_AD10           0xb0b1
 752                         MX6QDL_PAD_EIM_DA9__EIM_AD09            0xb0b1
 753                         MX6QDL_PAD_EIM_DA8__EIM_AD08            0xb0b1
 754                         MX6QDL_PAD_EIM_DA7__EIM_AD07            0xb0b1
 755                         MX6QDL_PAD_EIM_DA6__EIM_AD06            0xb0b1
 756                         MX6QDL_PAD_EIM_DA5__EIM_AD05            0xb0b1
 757                         MX6QDL_PAD_EIM_DA4__EIM_AD04            0xb0b1
 758                         MX6QDL_PAD_EIM_DA3__EIM_AD03            0xb0b1
 759                         MX6QDL_PAD_EIM_DA2__EIM_AD02            0xb0b1
 760                         MX6QDL_PAD_EIM_DA1__EIM_AD01            0xb0b1
 761                         MX6QDL_PAD_EIM_DA0__EIM_AD00            0xb0b1
 762                 >;
 763         };
 764
 765         pinctrl_weim_rdnwr: weimrdnwr {
 766                 fsl,pins = <
 767                         MX6QDL_PAD_SD2_CLK__GPIO1_IO10          0x0040
 768                         MX6QDL_PAD_RGMII_TD3__GPIO6_IO23        0x130b0
 769                 >;
 770         };
 771
 772         pinctrl_weim_npwe: weimnpwe {
 773                 fsl,pins = <
 774                         MX6QDL_PAD_SD2_DAT3__GPIO1_IO12         0x0040
 775                         MX6QDL_PAD_RGMII_TD2__GPIO6_IO22        0x130b0
 776                 >;
 777         };
 778
 779         /* ADDRESS[16:18] [25] used as GPIO */
 780         pinctrl_weim_gpio_1: weimgpio-1 {
 781                 fsl,pins = <
 782                         MX6QDL_PAD_KEY_ROW4__GPIO4_IO15         0x1b0b0
 783                         MX6QDL_PAD_KEY_ROW2__GPIO4_IO11         0x1b0b0
 784                         MX6QDL_PAD_KEY_COL2__GPIO4_IO10         0x1b0b0
 785                         MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17      0x1b0b0
 786                         MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16      0x1b0b0
 787                         MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15      0x1b0b0
 788                         MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14      0x1b0b0
 789                         MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13      0x1b0b0
 790                         MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12      0x1b0b0
 791                         MX6QDL_PAD_NANDF_D1__GPIO2_IO01         0x1b0b0
 792                 >;
 793         };
 794
 795         /* ADDRESS[19:24] used as GPIO */
 796         pinctrl_weim_gpio_2: weimgpio-2 {
 797                 fsl,pins = <
 798                         MX6QDL_PAD_KEY_ROW2__GPIO4_IO11         0x1b0b0
 799                         MX6QDL_PAD_KEY_COL2__GPIO4_IO10         0x1b0b0
 800                         MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17      0x1b0b0
 801                         MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16      0x1b0b0
 802                         MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15      0x1b0b0
 803                         MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14      0x1b0b0
 804                         MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13      0x1b0b0
 805                         MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12      0x1b0b0
 806                         MX6QDL_PAD_NANDF_D1__GPIO2_IO01         0x1b0b0
 807                 >;
 808         };
 809
 810         /* DATA[16:31] used as GPIO */
 811         pinctrl_weim_gpio_3: weimgpio-3 {
 812                 fsl,pins = <
 813                         MX6QDL_PAD_EIM_LBA__GPIO2_IO27          0x1b0b0
 814                         MX6QDL_PAD_EIM_BCLK__GPIO6_IO31         0x1b0b0
 815                         MX6QDL_PAD_NANDF_CS3__GPIO6_IO16        0x1b0b0
 816                         MX6QDL_PAD_NANDF_CS1__GPIO6_IO14        0x1b0b0
 817                         MX6QDL_PAD_NANDF_RB0__GPIO6_IO10        0x1b0b0
 818                         MX6QDL_PAD_NANDF_ALE__GPIO6_IO08        0x1b0b0
 819                         MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09       0x1b0b0
 820                         MX6QDL_PAD_NANDF_CS0__GPIO6_IO11        0x1b0b0
 821                         MX6QDL_PAD_NANDF_CLE__GPIO6_IO07        0x1b0b0
 822                         MX6QDL_PAD_GPIO_19__GPIO4_IO05          0x1b0b0
 823                         MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19        0x1b0b0
 824                         MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18      0x1b0b0
 825                         MX6QDL_PAD_GPIO_4__GPIO1_IO04           0x1b0b0
 826                         MX6QDL_PAD_GPIO_5__GPIO1_IO05           0x1b0b0
 827                         MX6QDL_PAD_GPIO_2__GPIO1_IO02           0x1b0b0
 828                 >;
 829         };
 830
 831         /* DQM[0:3] used as GPIO */
 832         pinctrl_weim_gpio_4: weimgpio-4 {
 833                 fsl,pins = <
 834                         MX6QDL_PAD_EIM_EB0__GPIO2_IO28          0x1b0b0
 835                         MX6QDL_PAD_EIM_EB1__GPIO2_IO29          0x1b0b0
 836                         MX6QDL_PAD_SD2_DAT2__GPIO1_IO13         0x1b0b0
 837                         MX6QDL_PAD_NANDF_D0__GPIO2_IO00         0x1b0b0
 838                 >;
 839         };
 840
 841         /* RDY used as GPIO */
 842         pinctrl_weim_gpio_5: weimgpio-5 {
 843                 fsl,pins = <
 844                         MX6QDL_PAD_EIM_WAIT__GPIO5_IO00         0x1b0b0
 845                 >;
 846         };
 847
 848         /* ADDRESS[16] DATA[30] used as GPIO */
 849         pinctrl_weim_gpio_6: weimgpio-6 {
 850                 fsl,pins = <
 851                         MX6QDL_PAD_KEY_ROW4__GPIO4_IO15         0x1b0b0
 852                         MX6QDL_PAD_KEY_COL4__GPIO4_IO14         0x1b0b0
 853                 >;
 854         };
 855 };