sys/gnu/dts/arm/imx6sl.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 //
   3 // Copyright 2013 Freescale Semiconductor, Inc.
   4
   5 #include <dt-bindings/interrupt-controller/irq.h>
   6 #include "imx6sl-pinfunc.h"
   7 #include <dt-bindings/clock/imx6sl-clock.h>
   8
   9 / {
  10         #address-cells = <1>;
  11         #size-cells = <1>;
  12         /*
  13          * The decompressor and also some bootloaders rely on a
  14          * pre-existing /chosen node to be available to insert the
  15          * command line and merge other ATAGS info.
  16          */
  17         chosen {};
  18
  19         aliases {
  20                 ethernet0 = &fec;
  21                 gpio0 = &gpio1;
  22                 gpio1 = &gpio2;
  23                 gpio2 = &gpio3;
  24                 gpio3 = &gpio4;
  25                 gpio4 = &gpio5;
  26                 i2c0 = &i2c1;
  27                 i2c1 = &i2c2;
  28                 i2c2 = &i2c3;
  29                 mmc0 = &usdhc1;
  30                 mmc1 = &usdhc2;
  31                 mmc2 = &usdhc3;
  32                 mmc3 = &usdhc4;
  33                 serial0 = &uart1;
  34                 serial1 = &uart2;
  35                 serial2 = &uart3;
  36                 serial3 = &uart4;
  37                 serial4 = &uart5;
  38                 spi0 = &ecspi1;
  39                 spi1 = &ecspi2;
  40                 spi2 = &ecspi3;
  41                 spi3 = &ecspi4;
  42                 usbphy0 = &usbphy1;
  43                 usbphy1 = &usbphy2;
  44         };
  45
  46         cpus {
  47                 #address-cells = <1>;
  48                 #size-cells = <0>;
  49
  50                 cpu@0 {
  51                         compatible = "arm,cortex-a9";
  52                         device_type = "cpu";
  53                         reg = <0x0>;
  54                         next-level-cache = <&L2>;
  55                         operating-points = <
  56                                 /* kHz    uV */
  57                                 996000  1275000
  58                                 792000  1175000
  59                                 396000  975000
  60                         >;
  61                         fsl,soc-operating-points = <
  62                                 /* ARM kHz      SOC-PU uV */
  63                                 996000          1225000
  64                                 792000          1175000
  65                                 396000          1175000
  66                         >;
  67                         clock-latency = <61036>; /* two CLK32 periods */
  68                         #cooling-cells = <2>;
  69                         clocks = <&clks IMX6SL_CLK_ARM>, <&clks IMX6SL_CLK_PLL2_PFD2>,
  70                                         <&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_CLK_PLL1_SW>,
  71                                         <&clks IMX6SL_CLK_PLL1_SYS>;
  72                         clock-names = "arm", "pll2_pfd2_396m", "step",
  73                                       "pll1_sw", "pll1_sys";
  74                         arm-supply = <&reg_arm>;
  75                         pu-supply = <&reg_pu>;
  76                         soc-supply = <&reg_soc>;
  77                         nvmem-cells = <&cpu_speed_grade>;
  78                         nvmem-cell-names = "speed_grade";
  79                 };
  80         };
  81
  82         clocks {
  83                 ckil {
  84                         compatible = "fixed-clock";
  85                         #clock-cells = <0>;
  86                         clock-frequency = <32768>;
  87                 };
  88
  89                 osc {
  90                         compatible = "fixed-clock";
  91                         #clock-cells = <0>;
  92                         clock-frequency = <24000000>;
  93                 };
  94         };
  95
  96         tempmon: tempmon {
  97                 compatible = "fsl,imx6q-tempmon";
  98                 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
  99                 interrupt-parent = <&gpc>;
 100                 fsl,tempmon = <&anatop>;
 101                 fsl,tempmon-data = <&ocotp>;
 102                 clocks = <&clks IMX6SL_CLK_PLL3_USB_OTG>;
 103         };
 104
 105         pmu {
 106                 compatible = "arm,cortex-a9-pmu";
 107                 interrupt-parent = <&gpc>;
 108                 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
 109         };
 110
 111         usbphynop1: usbphynop1 {
 112                 compatible = "usb-nop-xceiv";
 113                 #phy-cells = <0>;
 114         };
 115
 116         soc {
 117                 #address-cells = <1>;
 118                 #size-cells = <1>;
 119                 compatible = "simple-bus";
 120                 interrupt-parent = <&gpc>;
 121                 ranges;
 122
 123                 ocram: sram@900000 {
 124                         compatible = "mmio-sram";
 125                         reg = <0x00900000 0x20000>;
 126                         clocks = <&clks IMX6SL_CLK_OCRAM>;
 127                 };
 128
 129                 intc: interrupt-controller@a01000 {
 130                         compatible = "arm,cortex-a9-gic";
 131                         #interrupt-cells = <3>;
 132                         interrupt-controller;
 133                         reg = <0x00a01000 0x1000>,
 134                               <0x00a00100 0x100>;
 135                         interrupt-parent = <&intc>;
 136                 };
 137
 138                 L2: l2-cache@a02000 {
 139                         compatible = "arm,pl310-cache";
 140                         reg = <0x00a02000 0x1000>;
 141                         interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
 142                         cache-unified;
 143                         cache-level = <2>;
 144                         arm,tag-latency = <4 2 3>;
 145                         arm,data-latency = <4 2 3>;
 146                 };
 147
 148                 aips1: bus@2000000 {
 149                         compatible = "fsl,aips-bus", "simple-bus";
 150                         #address-cells = <1>;
 151                         #size-cells = <1>;
 152                         reg = <0x02000000 0x100000>;
 153                         ranges;
 154
 155                         spba: spba-bus@2000000 {
 156                                 compatible = "fsl,spba-bus", "simple-bus";
 157                                 #address-cells = <1>;
 158                                 #size-cells = <1>;
 159                                 reg = <0x02000000 0x40000>;
 160                                 ranges;
 161
 162                                 spdif: spdif@2004000 {
 163                                         compatible = "fsl,imx6sl-spdif",
 164                                                 "fsl,imx35-spdif";
 165                                         reg = <0x02004000 0x4000>;
 166                                         interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
 167                                         dmas = <&sdma 14 18 0>,
 168                                                 <&sdma 15 18 0>;
 169                                         dma-names = "rx", "tx";
 170                                         clocks = <&clks IMX6SL_CLK_SPDIF_GCLK>, <&clks IMX6SL_CLK_OSC>,
 171                                                  <&clks IMX6SL_CLK_SPDIF>, <&clks IMX6SL_CLK_DUMMY>,
 172                                                  <&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_DUMMY>,
 173                                                  <&clks IMX6SL_CLK_IPG>, <&clks IMX6SL_CLK_DUMMY>,
 174                                                  <&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_SPBA>;
 175                                         clock-names = "core", "rxtx0",
 176                                                 "rxtx1", "rxtx2",
 177                                                 "rxtx3", "rxtx4",
 178                                                 "rxtx5", "rxtx6",
 179                                                 "rxtx7", "spba";
 180                                         status = "disabled";
 181                                 };
 182
 183                                 ecspi1: spi@2008000 {
 184                                         #address-cells = <1>;
 185                                         #size-cells = <0>;
 186                                         compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
 187                                         reg = <0x02008000 0x4000>;
 188                                         interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
 189                                         clocks = <&clks IMX6SL_CLK_ECSPI1>,
 190                                                  <&clks IMX6SL_CLK_ECSPI1>;
 191                                         clock-names = "ipg", "per";
 192                                         status = "disabled";
 193                                 };
 194
 195                                 ecspi2: spi@200c000 {
 196                                         #address-cells = <1>;
 197                                         #size-cells = <0>;
 198                                         compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
 199                                         reg = <0x0200c000 0x4000>;
 200                                         interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
 201                                         clocks = <&clks IMX6SL_CLK_ECSPI2>,
 202                                                  <&clks IMX6SL_CLK_ECSPI2>;
 203                                         clock-names = "ipg", "per";
 204                                         status = "disabled";
 205                                 };
 206
 207                                 ecspi3: spi@2010000 {
 208                                         #address-cells = <1>;
 209                                         #size-cells = <0>;
 210                                         compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
 211                                         reg = <0x02010000 0x4000>;
 212                                         interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
 213                                         clocks = <&clks IMX6SL_CLK_ECSPI3>,
 214                                                  <&clks IMX6SL_CLK_ECSPI3>;
 215                                         clock-names = "ipg", "per";
 216                                         status = "disabled";
 217                                 };
 218
 219                                 ecspi4: spi@2014000 {
 220                                         #address-cells = <1>;
 221                                         #size-cells = <0>;
 222                                         compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
 223                                         reg = <0x02014000 0x4000>;
 224                                         interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
 225                                         clocks = <&clks IMX6SL_CLK_ECSPI4>,
 226                                                  <&clks IMX6SL_CLK_ECSPI4>;
 227                                         clock-names = "ipg", "per";
 228                                         status = "disabled";
 229                                 };
 230
 231                                 uart5: serial@2018000 {
 232                                         compatible = "fsl,imx6sl-uart",
 233                                                    "fsl,imx6q-uart", "fsl,imx21-uart";
 234                                         reg = <0x02018000 0x4000>;
 235                                         interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
 236                                         clocks = <&clks IMX6SL_CLK_UART>,
 237                                                  <&clks IMX6SL_CLK_UART_SERIAL>;
 238                                         clock-names = "ipg", "per";
 239                                         dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
 240                                         dma-names = "rx", "tx";
 241                                         status = "disabled";
 242                                 };
 243
 244                                 uart1: serial@2020000 {
 245                                         compatible = "fsl,imx6sl-uart",
 246                                                    "fsl,imx6q-uart", "fsl,imx21-uart";
 247                                         reg = <0x02020000 0x4000>;
 248                                         interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
 249                                         clocks = <&clks IMX6SL_CLK_UART>,
 250                                                  <&clks IMX6SL_CLK_UART_SERIAL>;
 251                                         clock-names = "ipg", "per";
 252                                         dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
 253                                         dma-names = "rx", "tx";
 254                                         status = "disabled";
 255                                 };
 256
 257                                 uart2: serial@2024000 {
 258                                         compatible = "fsl,imx6sl-uart",
 259                                                    "fsl,imx6q-uart", "fsl,imx21-uart";
 260                                         reg = <0x02024000 0x4000>;
 261                                         interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
 262                                         clocks = <&clks IMX6SL_CLK_UART>,
 263                                                  <&clks IMX6SL_CLK_UART_SERIAL>;
 264                                         clock-names = "ipg", "per";
 265                                         dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
 266                                         dma-names = "rx", "tx";
 267                                         status = "disabled";
 268                                 };
 269
 270                                 ssi1: ssi@2028000 {
 271                                         #sound-dai-cells = <0>;
 272                                         compatible = "fsl,imx6sl-ssi",
 273                                                         "fsl,imx51-ssi";
 274                                         reg = <0x02028000 0x4000>;
 275                                         interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
 276                                         clocks = <&clks IMX6SL_CLK_SSI1_IPG>,
 277                                                  <&clks IMX6SL_CLK_SSI1>;
 278                                         clock-names = "ipg", "baud";
 279                                         dmas = <&sdma 37 1 0>,
 280                                                <&sdma 38 1 0>;
 281                                         dma-names = "rx", "tx";
 282                                         fsl,fifo-depth = <15>;
 283                                         status = "disabled";
 284                                 };
 285
 286                                 ssi2: ssi@202c000 {
 287                                         #sound-dai-cells = <0>;
 288                                         compatible = "fsl,imx6sl-ssi",
 289                                                         "fsl,imx51-ssi";
 290                                         reg = <0x0202c000 0x4000>;
 291                                         interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
 292                                         clocks = <&clks IMX6SL_CLK_SSI2_IPG>,
 293                                                  <&clks IMX6SL_CLK_SSI2>;
 294                                         clock-names = "ipg", "baud";
 295                                         dmas = <&sdma 41 1 0>,
 296                                                <&sdma 42 1 0>;
 297                                         dma-names = "rx", "tx";
 298                                         fsl,fifo-depth = <15>;
 299                                         status = "disabled";
 300                                 };
 301
 302                                 ssi3: ssi@2030000 {
 303                                         #sound-dai-cells = <0>;
 304                                         compatible = "fsl,imx6sl-ssi",
 305                                                         "fsl,imx51-ssi";
 306                                         reg = <0x02030000 0x4000>;
 307                                         interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
 308                                         clocks = <&clks IMX6SL_CLK_SSI3_IPG>,
 309                                                  <&clks IMX6SL_CLK_SSI3>;
 310                                         clock-names = "ipg", "baud";
 311                                         dmas = <&sdma 45 1 0>,
 312                                                <&sdma 46 1 0>;
 313                                         dma-names = "rx", "tx";
 314                                         fsl,fifo-depth = <15>;
 315                                         status = "disabled";
 316                                 };
 317
 318                                 uart3: serial@2034000 {
 319                                         compatible = "fsl,imx6sl-uart",
 320                                                    "fsl,imx6q-uart", "fsl,imx21-uart";
 321                                         reg = <0x02034000 0x4000>;
 322                                         interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
 323                                         clocks = <&clks IMX6SL_CLK_UART>,
 324                                                  <&clks IMX6SL_CLK_UART_SERIAL>;
 325                                         clock-names = "ipg", "per";
 326                                         dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
 327                                         dma-names = "rx", "tx";
 328                                         status = "disabled";
 329                                 };
 330
 331                                 uart4: serial@2038000 {
 332                                         compatible = "fsl,imx6sl-uart",
 333                                                    "fsl,imx6q-uart", "fsl,imx21-uart";
 334                                         reg = <0x02038000 0x4000>;
 335                                         interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
 336                                         clocks = <&clks IMX6SL_CLK_UART>,
 337                                                  <&clks IMX6SL_CLK_UART_SERIAL>;
 338                                         clock-names = "ipg", "per";
 339                                         dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
 340                                         dma-names = "rx", "tx";
 341                                         status = "disabled";
 342                                 };
 343                         };
 344
 345                         pwm1: pwm@2080000 {
 346                                 #pwm-cells = <2>;
 347                                 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
 348                                 reg = <0x02080000 0x4000>;
 349                                 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
 350                                 clocks = <&clks IMX6SL_CLK_PERCLK>,
 351                                          <&clks IMX6SL_CLK_PWM1>;
 352                                 clock-names = "ipg", "per";
 353                         };
 354
 355                         pwm2: pwm@2084000 {
 356                                 #pwm-cells = <2>;
 357                                 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
 358                                 reg = <0x02084000 0x4000>;
 359                                 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
 360                                 clocks = <&clks IMX6SL_CLK_PERCLK>,
 361                                          <&clks IMX6SL_CLK_PWM2>;
 362                                 clock-names = "ipg", "per";
 363                         };
 364
 365                         pwm3: pwm@2088000 {
 366                                 #pwm-cells = <2>;
 367                                 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
 368                                 reg = <0x02088000 0x4000>;
 369                                 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
 370                                 clocks = <&clks IMX6SL_CLK_PERCLK>,
 371                                          <&clks IMX6SL_CLK_PWM3>;
 372                                 clock-names = "ipg", "per";
 373                         };
 374
 375                         pwm4: pwm@208c000 {
 376                                 #pwm-cells = <2>;
 377                                 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
 378                                 reg = <0x0208c000 0x4000>;
 379                                 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
 380                                 clocks = <&clks IMX6SL_CLK_PERCLK>,
 381                                          <&clks IMX6SL_CLK_PWM4>;
 382                                 clock-names = "ipg", "per";
 383                         };
 384
 385                         gpt: timer@2098000 {
 386                                 compatible = "fsl,imx6sl-gpt";
 387                                 reg = <0x02098000 0x4000>;
 388                                 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
 389                                 clocks = <&clks IMX6SL_CLK_GPT>,
 390                                          <&clks IMX6SL_CLK_GPT_SERIAL>;
 391                                 clock-names = "ipg", "per";
 392                         };
 393
 394                         gpio1: gpio@209c000 {
 395                                 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
 396                                 reg = <0x0209c000 0x4000>;
 397                                 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
 398                                              <0 67 IRQ_TYPE_LEVEL_HIGH>;
 399                                 gpio-controller;
 400                                 #gpio-cells = <2>;
 401                                 interrupt-controller;
 402                                 #interrupt-cells = <2>;
 403                                 gpio-ranges = <&iomuxc  0 22 1>, <&iomuxc  1 20 2>,
 404                                               <&iomuxc  3 23 1>, <&iomuxc  4 25 1>,
 405                                               <&iomuxc  5 24 1>, <&iomuxc  6 19 1>,
 406                                               <&iomuxc  7 36 2>, <&iomuxc  9 44 8>,
 407                                               <&iomuxc 17 38 6>, <&iomuxc 23 68 4>,
 408                                               <&iomuxc 27 64 4>, <&iomuxc 31 52 1>;
 409                         };
 410
 411                         gpio2: gpio@20a0000 {
 412                                 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
 413                                 reg = <0x020a0000 0x4000>;
 414                                 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
 415                                              <0 69 IRQ_TYPE_LEVEL_HIGH>;
 416                                 gpio-controller;
 417                                 #gpio-cells = <2>;
 418                                 interrupt-controller;
 419                                 #interrupt-cells = <2>;
 420                                 gpio-ranges = <&iomuxc  0  53 3>, <&iomuxc  3  72 2>,
 421                                               <&iomuxc  5  34 2>, <&iomuxc  7  57 4>,
 422                                               <&iomuxc 11  56 1>, <&iomuxc 12  61 3>,
 423                                               <&iomuxc 15 107 1>, <&iomuxc 16 132 2>,
 424                                               <&iomuxc 18 135 1>, <&iomuxc 19 134 1>,
 425                                               <&iomuxc 20 108 2>, <&iomuxc 22 120 1>,
 426                                               <&iomuxc 23 125 7>, <&iomuxc 30 110 2>;
 427                         };
 428
 429                         gpio3: gpio@20a4000 {
 430                                 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
 431                                 reg = <0x020a4000 0x4000>;
 432                                 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
 433                                              <0 71 IRQ_TYPE_LEVEL_HIGH>;
 434                                 gpio-controller;
 435                                 #gpio-cells = <2>;
 436                                 interrupt-controller;
 437                                 #interrupt-cells = <2>;
 438                                 gpio-ranges = <&iomuxc  0 112 8>, <&iomuxc  8 121 4>,
 439                                               <&iomuxc 12  97 4>, <&iomuxc 16 166 3>,
 440                                               <&iomuxc 19  85 2>, <&iomuxc 21 137 2>,
 441                                               <&iomuxc 23 136 1>, <&iomuxc 24  91 1>,
 442                                               <&iomuxc 25  99 1>, <&iomuxc 26  92 1>,
 443                                               <&iomuxc 27 100 1>, <&iomuxc 28  93 1>,
 444                                               <&iomuxc 29 101 1>, <&iomuxc 30  94 1>,
 445                                               <&iomuxc 31 102 1>;
 446                         };
 447
 448                         gpio4: gpio@20a8000 {
 449                                 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
 450                                 reg = <0x020a8000 0x4000>;
 451                                 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
 452                                              <0 73 IRQ_TYPE_LEVEL_HIGH>;
 453                                 gpio-controller;
 454                                 #gpio-cells = <2>;
 455                                 interrupt-controller;
 456                                 #interrupt-cells = <2>;
 457                                 gpio-ranges = <&iomuxc  0  95 1>, <&iomuxc  1 103 1>,
 458                                               <&iomuxc  2  96 1>, <&iomuxc  3 104 1>,
 459                                               <&iomuxc  4  97 1>, <&iomuxc  5 105 1>,
 460                                               <&iomuxc  6  98 1>, <&iomuxc  7 106 1>,
 461                                               <&iomuxc  8  28 1>, <&iomuxc  9  27 1>,
 462                                               <&iomuxc 10  26 1>, <&iomuxc 11  29 1>,
 463                                               <&iomuxc 12  32 1>, <&iomuxc 13  31 1>,
 464                                               <&iomuxc 14  30 1>, <&iomuxc 15  33 1>,
 465                                               <&iomuxc 16  84 1>, <&iomuxc 17  79 2>,
 466                                               <&iomuxc 19  78 1>, <&iomuxc 20  76 1>,
 467                                               <&iomuxc 21  81 2>, <&iomuxc 23  75 1>,
 468                                               <&iomuxc 24  83 1>, <&iomuxc 25  74 1>,
 469                                               <&iomuxc 26  77 1>, <&iomuxc 27 159 1>,
 470                                               <&iomuxc 28 154 1>, <&iomuxc 29 157 1>,
 471                                               <&iomuxc 30 152 1>, <&iomuxc 31 156 1>;
 472                         };
 473
 474                         gpio5: gpio@20ac000 {
 475                                 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
 476                                 reg = <0x020ac000 0x4000>;
 477                                 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
 478                                              <0 75 IRQ_TYPE_LEVEL_HIGH>;
 479                                 gpio-controller;
 480                                 #gpio-cells = <2>;
 481                                 interrupt-controller;
 482                                 #interrupt-cells = <2>;
 483                                 gpio-ranges = <&iomuxc  0 158 1>, <&iomuxc  1 151 1>,
 484                                               <&iomuxc  2 155 1>, <&iomuxc  3 153 1>,
 485                                               <&iomuxc  4 150 1>, <&iomuxc  5 149 1>,
 486                                               <&iomuxc  6 144 1>, <&iomuxc  7 147 1>,
 487                                               <&iomuxc  8 142 1>, <&iomuxc  9 146 1>,
 488                                               <&iomuxc 10 148 1>, <&iomuxc 11 141 1>,
 489                                               <&iomuxc 12 145 1>, <&iomuxc 13 143 1>,
 490                                               <&iomuxc 14 140 1>, <&iomuxc 15 139 1>,
 491                                               <&iomuxc 16 164 2>, <&iomuxc 18 160 1>,
 492                                               <&iomuxc 19 162 1>, <&iomuxc 20 163 1>,
 493                                               <&iomuxc 21 161 1>;
 494                         };
 495
 496                         kpp: keypad@20b8000 {
 497                                 compatible = "fsl,imx6sl-kpp", "fsl,imx21-kpp";
 498                                 reg = <0x020b8000 0x4000>;
 499                                 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
 500                                 clocks = <&clks IMX6SL_CLK_IPG>;
 501                                 status = "disabled";
 502                         };
 503
 504                         wdog1: watchdog@20bc000 {
 505                                 compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
 506                                 reg = <0x020bc000 0x4000>;
 507                                 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
 508                                 clocks = <&clks IMX6SL_CLK_IPG>;
 509                         };
 510
 511                         wdog2: watchdog@20c0000 {
 512                                 compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
 513                                 reg = <0x020c0000 0x4000>;
 514                                 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
 515                                 clocks = <&clks IMX6SL_CLK_IPG>;
 516                                 status = "disabled";
 517                         };
 518
 519                         clks: clock-controller@20c4000 {
 520                                 compatible = "fsl,imx6sl-ccm";
 521                                 reg = <0x020c4000 0x4000>;
 522                                 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
 523                                              <0 88 IRQ_TYPE_LEVEL_HIGH>;
 524                                 #clock-cells = <1>;
 525                         };
 526
 527                         anatop: anatop@20c8000 {
 528                                 compatible = "fsl,imx6sl-anatop",
 529                                              "fsl,imx6q-anatop",
 530                                              "syscon", "simple-mfd";
 531                                 reg = <0x020c8000 0x1000>;
 532                                 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
 533                                              <0 54 IRQ_TYPE_LEVEL_HIGH>,
 534                                              <0 127 IRQ_TYPE_LEVEL_HIGH>;
 535
 536                                 reg_vdd1p1: regulator-1p1 {
 537                                         compatible = "fsl,anatop-regulator";
 538                                         regulator-name = "vdd1p1";
 539                                         regulator-min-microvolt = <1000000>;
 540                                         regulator-max-microvolt = <1200000>;
 541                                         regulator-always-on;
 542                                         anatop-reg-offset = <0x110>;
 543                                         anatop-vol-bit-shift = <8>;
 544                                         anatop-vol-bit-width = <5>;
 545                                         anatop-min-bit-val = <4>;
 546                                         anatop-min-voltage = <800000>;
 547                                         anatop-max-voltage = <1375000>;
 548                                         anatop-enable-bit = <0>;
 549                                 };
 550
 551                                 reg_vdd3p0: regulator-3p0 {
 552                                         compatible = "fsl,anatop-regulator";
 553                                         regulator-name = "vdd3p0";
 554                                         regulator-min-microvolt = <2800000>;
 555                                         regulator-max-microvolt = <3150000>;
 556                                         regulator-always-on;
 557                                         anatop-reg-offset = <0x120>;
 558                                         anatop-vol-bit-shift = <8>;
 559                                         anatop-vol-bit-width = <5>;
 560                                         anatop-min-bit-val = <0>;
 561                                         anatop-min-voltage = <2625000>;
 562                                         anatop-max-voltage = <3400000>;
 563                                         anatop-enable-bit = <0>;
 564                                 };
 565
 566                                 reg_vdd2p5: regulator-2p5 {
 567                                         compatible = "fsl,anatop-regulator";
 568                                         regulator-name = "vdd2p5";
 569                                         regulator-min-microvolt = <2250000>;
 570                                         regulator-max-microvolt = <2750000>;
 571                                         regulator-always-on;
 572                                         anatop-reg-offset = <0x130>;
 573                                         anatop-vol-bit-shift = <8>;
 574                                         anatop-vol-bit-width = <5>;
 575                                         anatop-min-bit-val = <0>;
 576                                         anatop-min-voltage = <2100000>;
 577                                         anatop-max-voltage = <2850000>;
 578                                         anatop-enable-bit = <0>;
 579                                 };
 580
 581                                 reg_arm: regulator-vddcore {
 582                                         compatible = "fsl,anatop-regulator";
 583                                         regulator-name = "vddarm";
 584                                         regulator-min-microvolt = <725000>;
 585                                         regulator-max-microvolt = <1450000>;
 586                                         regulator-always-on;
 587                                         anatop-reg-offset = <0x140>;
 588                                         anatop-vol-bit-shift = <0>;
 589                                         anatop-vol-bit-width = <5>;
 590                                         anatop-delay-reg-offset = <0x170>;
 591                                         anatop-delay-bit-shift = <24>;
 592                                         anatop-delay-bit-width = <2>;
 593                                         anatop-min-bit-val = <1>;
 594                                         anatop-min-voltage = <725000>;
 595                                         anatop-max-voltage = <1450000>;
 596                                 };
 597
 598                                 reg_pu: regulator-vddpu {
 599                                         compatible = "fsl,anatop-regulator";
 600                                         regulator-name = "vddpu";
 601                                         regulator-min-microvolt = <725000>;
 602                                         regulator-max-microvolt = <1450000>;
 603                                         anatop-reg-offset = <0x140>;
 604                                         anatop-vol-bit-shift = <9>;
 605                                         anatop-vol-bit-width = <5>;
 606                                         anatop-delay-reg-offset = <0x170>;
 607                                         anatop-delay-bit-shift = <26>;
 608                                         anatop-delay-bit-width = <2>;
 609                                         anatop-min-bit-val = <1>;
 610                                         anatop-min-voltage = <725000>;
 611                                         anatop-max-voltage = <1450000>;
 612                                 };
 613
 614                                 reg_soc: regulator-vddsoc {
 615                                         compatible = "fsl,anatop-regulator";
 616                                         regulator-name = "vddsoc";
 617                                         regulator-min-microvolt = <725000>;
 618                                         regulator-max-microvolt = <1450000>;
 619                                         regulator-always-on;
 620                                         anatop-reg-offset = <0x140>;
 621                                         anatop-vol-bit-shift = <18>;
 622                                         anatop-vol-bit-width = <5>;
 623                                         anatop-delay-reg-offset = <0x170>;
 624                                         anatop-delay-bit-shift = <28>;
 625                                         anatop-delay-bit-width = <2>;
 626                                         anatop-min-bit-val = <1>;
 627                                         anatop-min-voltage = <725000>;
 628                                         anatop-max-voltage = <1450000>;
 629                                 };
 630                         };
 631
 632                         usbphy1: usbphy@20c9000 {
 633                                 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
 634                                 reg = <0x020c9000 0x1000>;
 635                                 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
 636                                 clocks = <&clks IMX6SL_CLK_USBPHY1>;
 637                                 fsl,anatop = <&anatop>;
 638                         };
 639
 640                         usbphy2: usbphy@20ca000 {
 641                                 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
 642                                 reg = <0x020ca000 0x1000>;
 643                                 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
 644                                 clocks = <&clks IMX6SL_CLK_USBPHY2>;
 645                                 fsl,anatop = <&anatop>;
 646                         };
 647
 648                         snvs: snvs@20cc000 {
 649                                 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
 650                                 reg = <0x020cc000 0x4000>;
 651
 652                                 snvs_rtc: snvs-rtc-lp {
 653                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 654                                         regmap = <&snvs>;
 655                                         offset = <0x34>;
 656                                         interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
 657                                                      <0 20 IRQ_TYPE_LEVEL_HIGH>;
 658                                 };
 659
 660                                 snvs_poweroff: snvs-poweroff {
 661                                         compatible = "syscon-poweroff";
 662                                         regmap = <&snvs>;
 663                                         offset = <0x38>;
 664                                         value = <0x60>;
 665                                         mask = <0x60>;
 666                                         status = "disabled";
 667                                 };
 668                         };
 669
 670                         epit1: epit@20d0000 {
 671                                 reg = <0x020d0000 0x4000>;
 672                                 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
 673                         };
 674
 675                         epit2: epit@20d4000 {
 676                                 reg = <0x020d4000 0x4000>;
 677                                 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
 678                         };
 679
 680                         src: src@20d8000 {
 681                                 compatible = "fsl,imx6sl-src", "fsl,imx51-src";
 682                                 reg = <0x020d8000 0x4000>;
 683                                 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
 684                                              <0 96 IRQ_TYPE_LEVEL_HIGH>;
 685                                 #reset-cells = <1>;
 686                         };
 687
 688                         gpc: gpc@20dc000 {
 689                                 compatible = "fsl,imx6sl-gpc", "fsl,imx6q-gpc";
 690                                 reg = <0x020dc000 0x4000>;
 691                                 interrupt-controller;
 692                                 #interrupt-cells = <3>;
 693                                 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
 694                                 interrupt-parent = <&intc>;
 695                                 clocks = <&clks IMX6SL_CLK_IPG>;
 696                                 clock-names = "ipg";
 697
 698                                 pgc {
 699                                         #address-cells = <1>;
 700                                         #size-cells = <0>;
 701
 702                                         power-domain@0 {
 703                                                 reg = <0>;
 704                                                 #power-domain-cells = <0>;
 705                                         };
 706
 707                                         pd_pu: power-domain@1 {
 708                                                 reg = <1>;
 709                                                 #power-domain-cells = <0>;
 710                                                 power-supply = <&reg_pu>;
 711                                                 clocks = <&clks IMX6SL_CLK_GPU2D_OVG>,
 712                                                          <&clks IMX6SL_CLK_GPU2D_PODF>;
 713                                         };
 714
 715                                         pd_disp: power-domain@2 {
 716                                                 reg = <2>;
 717                                                 #power-domain-cells = <0>;
 718                                                 clocks = <&clks IMX6SL_CLK_LCDIF_AXI>,
 719                                                          <&clks IMX6SL_CLK_LCDIF_PIX>,
 720                                                          <&clks IMX6SL_CLK_EPDC_AXI>,
 721                                                          <&clks IMX6SL_CLK_EPDC_PIX>,
 722                                                          <&clks IMX6SL_CLK_PXP_AXI>;
 723                                         };
 724                                 };
 725                         };
 726
 727                         gpr: iomuxc-gpr@20e0000 {
 728                                 compatible = "fsl,imx6sl-iomuxc-gpr",
 729                                              "fsl,imx6q-iomuxc-gpr", "syscon";
 730                                 reg = <0x020e0000 0x38>;
 731                         };
 732
 733                         iomuxc: pinctrl@20e0000 {
 734                                 compatible = "fsl,imx6sl-iomuxc";
 735                                 reg = <0x020e0000 0x4000>;
 736                         };
 737
 738                         csi: csi@20e4000 {
 739                                 reg = <0x020e4000 0x4000>;
 740                                 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
 741                         };
 742
 743                         spdc: spdc@20e8000 {
 744                                 reg = <0x020e8000 0x4000>;
 745                                 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
 746                         };
 747
 748                         sdma: sdma@20ec000 {
 749                                 compatible = "fsl,imx6sl-sdma", "fsl,imx6q-sdma";
 750                                 reg = <0x020ec000 0x4000>;
 751                                 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
 752                                 clocks = <&clks IMX6SL_CLK_SDMA>,
 753                                          <&clks IMX6SL_CLK_AHB>;
 754                                 clock-names = "ipg", "ahb";
 755                                 #dma-cells = <3>;
 756                                 /* imx6sl reuses imx6q sdma firmware */
 757                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
 758                         };
 759
 760                         pxp: pxp@20f0000 {
 761                                 reg = <0x020f0000 0x4000>;
 762                                 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
 763                         };
 764
 765                         epdc: epdc@20f4000 {
 766                                 reg = <0x020f4000 0x4000>;
 767                                 interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
 768                         };
 769
 770                         lcdif: lcdif@20f8000 {
 771                                 compatible = "fsl,imx6sl-lcdif", "fsl,imx28-lcdif";
 772                                 reg = <0x020f8000 0x4000>;
 773                                 interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
 774                                 clocks = <&clks IMX6SL_CLK_LCDIF_PIX>,
 775                                          <&clks IMX6SL_CLK_LCDIF_AXI>,
 776                                          <&clks IMX6SL_CLK_DUMMY>;
 777                                 clock-names = "pix", "axi", "disp_axi";
 778                                 status = "disabled";
 779                                 power-domains = <&pd_disp>;
 780                         };
 781
 782                         dcp: crypto@20fc000 {
 783                                 compatible = "fsl,imx6sl-dcp", "fsl,imx28-dcp";
 784                                 reg = <0x020fc000 0x4000>;
 785                                 interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>,
 786                                              <0 100 IRQ_TYPE_LEVEL_HIGH>,
 787                                              <0 101 IRQ_TYPE_LEVEL_HIGH>;
 788                         };
 789                 };
 790
 791                 aips2: bus@2100000 {
 792                         compatible = "fsl,aips-bus", "simple-bus";
 793                         #address-cells = <1>;
 794                         #size-cells = <1>;
 795                         reg = <0x02100000 0x100000>;
 796                         ranges;
 797
 798                         usbotg1: usb@2184000 {
 799                                 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
 800                                 reg = <0x02184000 0x200>;
 801                                 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
 802                                 clocks = <&clks IMX6SL_CLK_USBOH3>;
 803                                 fsl,usbphy = <&usbphy1>;
 804                                 fsl,usbmisc = <&usbmisc 0>;
 805                                 ahb-burst-config = <0x0>;
 806                                 tx-burst-size-dword = <0x10>;
 807                                 rx-burst-size-dword = <0x10>;
 808                                 status = "disabled";
 809                         };
 810
 811                         usbotg2: usb@2184200 {
 812                                 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
 813                                 reg = <0x02184200 0x200>;
 814                                 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
 815                                 clocks = <&clks IMX6SL_CLK_USBOH3>;
 816                                 fsl,usbphy = <&usbphy2>;
 817                                 fsl,usbmisc = <&usbmisc 1>;
 818                                 ahb-burst-config = <0x0>;
 819                                 tx-burst-size-dword = <0x10>;
 820                                 rx-burst-size-dword = <0x10>;
 821                                 status = "disabled";
 822                         };
 823
 824                         usbh: usb@2184400 {
 825                                 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
 826                                 reg = <0x02184400 0x200>;
 827                                 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
 828                                 clocks = <&clks IMX6SL_CLK_USBOH3>;
 829                                 fsl,usbphy = <&usbphynop1>;
 830                                 phy_type = "hsic";
 831                                 fsl,usbmisc = <&usbmisc 2>;
 832                                 dr_mode = "host";
 833                                 ahb-burst-config = <0x0>;
 834                                 tx-burst-size-dword = <0x10>;
 835                                 rx-burst-size-dword = <0x10>;
 836                                 status = "disabled";
 837                         };
 838
 839                         usbmisc: usbmisc@2184800 {
 840                                 #index-cells = <1>;
 841                                 compatible = "fsl,imx6sl-usbmisc", "fsl,imx6q-usbmisc";
 842                                 reg = <0x02184800 0x200>;
 843                                 clocks = <&clks IMX6SL_CLK_USBOH3>;
 844                         };
 845
 846                         fec: ethernet@2188000 {
 847                                 compatible = "fsl,imx6sl-fec", "fsl,imx25-fec";
 848                                 reg = <0x02188000 0x4000>;
 849                                 interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>;
 850                                 clocks = <&clks IMX6SL_CLK_ENET>,
 851                                          <&clks IMX6SL_CLK_ENET_REF>;
 852                                 clock-names = "ipg", "ahb";
 853                                 status = "disabled";
 854                         };
 855
 856                         usdhc1: usdhc@2190000 {
 857                                 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
 858                                 reg = <0x02190000 0x4000>;
 859                                 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
 860                                 clocks = <&clks IMX6SL_CLK_USDHC1>,
 861                                          <&clks IMX6SL_CLK_USDHC1>,
 862                                          <&clks IMX6SL_CLK_USDHC1>;
 863                                 clock-names = "ipg", "ahb", "per";
 864                                 bus-width = <4>;
 865                                 status = "disabled";
 866                         };
 867
 868                         usdhc2: usdhc@2194000 {
 869                                 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
 870                                 reg = <0x02194000 0x4000>;
 871                                 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
 872                                 clocks = <&clks IMX6SL_CLK_USDHC2>,
 873                                          <&clks IMX6SL_CLK_USDHC2>,
 874                                          <&clks IMX6SL_CLK_USDHC2>;
 875                                 clock-names = "ipg", "ahb", "per";
 876                                 bus-width = <4>;
 877                                 status = "disabled";
 878                         };
 879
 880                         usdhc3: usdhc@2198000 {
 881                                 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
 882                                 reg = <0x02198000 0x4000>;
 883                                 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
 884                                 clocks = <&clks IMX6SL_CLK_USDHC3>,
 885                                          <&clks IMX6SL_CLK_USDHC3>,
 886                                          <&clks IMX6SL_CLK_USDHC3>;
 887                                 clock-names = "ipg", "ahb", "per";
 888                                 bus-width = <4>;
 889                                 status = "disabled";
 890                         };
 891
 892                         usdhc4: usdhc@219c000 {
 893                                 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
 894                                 reg = <0x0219c000 0x4000>;
 895                                 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
 896                                 clocks = <&clks IMX6SL_CLK_USDHC4>,
 897                                          <&clks IMX6SL_CLK_USDHC4>,
 898                                          <&clks IMX6SL_CLK_USDHC4>;
 899                                 clock-names = "ipg", "ahb", "per";
 900                                 bus-width = <4>;
 901                                 status = "disabled";
 902                         };
 903
 904                         i2c1: i2c@21a0000 {
 905                                 #address-cells = <1>;
 906                                 #size-cells = <0>;
 907                                 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
 908                                 reg = <0x021a0000 0x4000>;
 909                                 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
 910                                 clocks = <&clks IMX6SL_CLK_I2C1>;
 911                                 status = "disabled";
 912                         };
 913
 914                         i2c2: i2c@21a4000 {
 915                                 #address-cells = <1>;
 916                                 #size-cells = <0>;
 917                                 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
 918                                 reg = <0x021a4000 0x4000>;
 919                                 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
 920                                 clocks = <&clks IMX6SL_CLK_I2C2>;
 921                                 status = "disabled";
 922                         };
 923
 924                         i2c3: i2c@21a8000 {
 925                                 #address-cells = <1>;
 926                                 #size-cells = <0>;
 927                                 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
 928                                 reg = <0x021a8000 0x4000>;
 929                                 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
 930                                 clocks = <&clks IMX6SL_CLK_I2C3>;
 931                                 status = "disabled";
 932                         };
 933
 934                         memory-controller@21b0000 {
 935                                 compatible = "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc";
 936                                 reg = <0x021b0000 0x4000>;
 937                                 clocks = <&clks IMX6SL_CLK_MMDC_P0_IPG>;
 938                         };
 939
 940                         rngb: rngb@21b4000 {
 941                                 reg = <0x021b4000 0x4000>;
 942                                 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
 943                         };
 944
 945                         weim: weim@21b8000 {
 946                                 #address-cells = <2>;
 947                                 #size-cells = <1>;
 948                                 reg = <0x021b8000 0x4000>;
 949                                 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
 950                                 fsl,weim-cs-gpr = <&gpr>;
 951                                 status = "disabled";
 952                         };
 953
 954                         ocotp: ocotp-ctrl@21bc000 {
 955                                 compatible = "fsl,imx6sl-ocotp", "syscon";
 956                                 reg = <0x021bc000 0x4000>;
 957                                 clocks = <&clks IMX6SL_CLK_OCOTP>;
 958                                 #address-cells = <1>;
 959                                 #size-cells = <1>;
 960
 961                                 cpu_speed_grade: speed-grade@10 {
 962                                         reg = <0x10 4>;
 963                                 };
 964                         };
 965
 966                         audmux: audmux@21d8000 {
 967                                 compatible = "fsl,imx6sl-audmux", "fsl,imx31-audmux";
 968                                 reg = <0x021d8000 0x4000>;
 969                                 status = "disabled";
 970                         };
 971                 };
 972
 973                 gpu_2d: gpu@2200000 {
 974                         compatible = "vivante,gc";
 975                         reg = <0x02200000 0x4000>;
 976                         interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
 977                         clocks = <&clks IMX6SL_CLK_MMDC_ROOT>,
 978                                  <&clks IMX6SL_CLK_GPU2D_OVG>;
 979                         clock-names = "bus", "core";
 980                         power-domains = <&pd_pu>;
 981                 };
 982
 983                 gpu_vg: gpu@2204000 {
 984                         compatible = "vivante,gc";
 985                         reg = <0x02204000 0x4000>;
 986                         interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
 987                         clocks = <&clks IMX6SL_CLK_MMDC_ROOT>,
 988                                  <&clks IMX6SL_CLK_GPU2D_OVG>;
 989                         clock-names = "bus", "core";
 990                         power-domains = <&pd_pu>;
 991                 };
 992         };
 993 };