sys/gnu/dts/arm64/freescale/fsl-lx2160a.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 //
   3 // Device Tree Include file for Layerscape-LX2160A family SoC.
   4 //
   5 // Copyright 2018 NXP
   6
   7 #include <dt-bindings/gpio/gpio.h>
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9 #include <dt-bindings/thermal/thermal.h>
  10
  11 /memreserve/ 0x80000000 0x00010000;
  12
  13 / {
  14         compatible = "fsl,lx2160a";
  15         interrupt-parent = <&gic>;
  16         #address-cells = <2>;
  17         #size-cells = <2>;
  18
  19         cpus {
  20                 #address-cells = <1>;
  21                 #size-cells = <0>;
  22
  23                 // 8 clusters having 2 Cortex-A72 cores each
  24                 cpu0: cpu@0 {
  25                         device_type = "cpu";
  26                         compatible = "arm,cortex-a72";
  27                         enable-method = "psci";
  28                         reg = <0x0>;
  29                         clocks = <&clockgen 1 0>;
  30                         d-cache-size = <0x8000>;
  31                         d-cache-line-size = <64>;
  32                         d-cache-sets = <128>;
  33                         i-cache-size = <0xC000>;
  34                         i-cache-line-size = <64>;
  35                         i-cache-sets = <192>;
  36                         next-level-cache = <&cluster0_l2>;
  37                         cpu-idle-states = <&cpu_pw15>;
  38                         #cooling-cells = <2>;
  39                 };
  40
  41                 cpu1: cpu@1 {
  42                         device_type = "cpu";
  43                         compatible = "arm,cortex-a72";
  44                         enable-method = "psci";
  45                         reg = <0x1>;
  46                         clocks = <&clockgen 1 0>;
  47                         d-cache-size = <0x8000>;
  48                         d-cache-line-size = <64>;
  49                         d-cache-sets = <128>;
  50                         i-cache-size = <0xC000>;
  51                         i-cache-line-size = <64>;
  52                         i-cache-sets = <192>;
  53                         next-level-cache = <&cluster0_l2>;
  54                         cpu-idle-states = <&cpu_pw15>;
  55                         #cooling-cells = <2>;
  56                 };
  57
  58                 cpu100: cpu@100 {
  59                         device_type = "cpu";
  60                         compatible = "arm,cortex-a72";
  61                         enable-method = "psci";
  62                         reg = <0x100>;
  63                         clocks = <&clockgen 1 1>;
  64                         d-cache-size = <0x8000>;
  65                         d-cache-line-size = <64>;
  66                         d-cache-sets = <128>;
  67                         i-cache-size = <0xC000>;
  68                         i-cache-line-size = <64>;
  69                         i-cache-sets = <192>;
  70                         next-level-cache = <&cluster1_l2>;
  71                         cpu-idle-states = <&cpu_pw15>;
  72                         #cooling-cells = <2>;
  73                 };
  74
  75                 cpu101: cpu@101 {
  76                         device_type = "cpu";
  77                         compatible = "arm,cortex-a72";
  78                         enable-method = "psci";
  79                         reg = <0x101>;
  80                         clocks = <&clockgen 1 1>;
  81                         d-cache-size = <0x8000>;
  82                         d-cache-line-size = <64>;
  83                         d-cache-sets = <128>;
  84                         i-cache-size = <0xC000>;
  85                         i-cache-line-size = <64>;
  86                         i-cache-sets = <192>;
  87                         next-level-cache = <&cluster1_l2>;
  88                         cpu-idle-states = <&cpu_pw15>;
  89                         #cooling-cells = <2>;
  90                 };
  91
  92                 cpu200: cpu@200 {
  93                         device_type = "cpu";
  94                         compatible = "arm,cortex-a72";
  95                         enable-method = "psci";
  96                         reg = <0x200>;
  97                         clocks = <&clockgen 1 2>;
  98                         d-cache-size = <0x8000>;
  99                         d-cache-line-size = <64>;
 100                         d-cache-sets = <128>;
 101                         i-cache-size = <0xC000>;
 102                         i-cache-line-size = <64>;
 103                         i-cache-sets = <192>;
 104                         next-level-cache = <&cluster2_l2>;
 105                         cpu-idle-states = <&cpu_pw15>;
 106                         #cooling-cells = <2>;
 107                 };
 108
 109                 cpu201: cpu@201 {
 110                         device_type = "cpu";
 111                         compatible = "arm,cortex-a72";
 112                         enable-method = "psci";
 113                         reg = <0x201>;
 114                         clocks = <&clockgen 1 2>;
 115                         d-cache-size = <0x8000>;
 116                         d-cache-line-size = <64>;
 117                         d-cache-sets = <128>;
 118                         i-cache-size = <0xC000>;
 119                         i-cache-line-size = <64>;
 120                         i-cache-sets = <192>;
 121                         next-level-cache = <&cluster2_l2>;
 122                         cpu-idle-states = <&cpu_pw15>;
 123                         #cooling-cells = <2>;
 124                 };
 125
 126                 cpu300: cpu@300 {
 127                         device_type = "cpu";
 128                         compatible = "arm,cortex-a72";
 129                         enable-method = "psci";
 130                         reg = <0x300>;
 131                         clocks = <&clockgen 1 3>;
 132                         d-cache-size = <0x8000>;
 133                         d-cache-line-size = <64>;
 134                         d-cache-sets = <128>;
 135                         i-cache-size = <0xC000>;
 136                         i-cache-line-size = <64>;
 137                         i-cache-sets = <192>;
 138                         next-level-cache = <&cluster3_l2>;
 139                         cpu-idle-states = <&cpu_pw15>;
 140                         #cooling-cells = <2>;
 141                 };
 142
 143                 cpu301: cpu@301 {
 144                         device_type = "cpu";
 145                         compatible = "arm,cortex-a72";
 146                         enable-method = "psci";
 147                         reg = <0x301>;
 148                         clocks = <&clockgen 1 3>;
 149                         d-cache-size = <0x8000>;
 150                         d-cache-line-size = <64>;
 151                         d-cache-sets = <128>;
 152                         i-cache-size = <0xC000>;
 153                         i-cache-line-size = <64>;
 154                         i-cache-sets = <192>;
 155                         next-level-cache = <&cluster3_l2>;
 156                         cpu-idle-states = <&cpu_pw15>;
 157                         #cooling-cells = <2>;
 158                 };
 159
 160                 cpu400: cpu@400 {
 161                         device_type = "cpu";
 162                         compatible = "arm,cortex-a72";
 163                         enable-method = "psci";
 164                         reg = <0x400>;
 165                         clocks = <&clockgen 1 4>;
 166                         d-cache-size = <0x8000>;
 167                         d-cache-line-size = <64>;
 168                         d-cache-sets = <128>;
 169                         i-cache-size = <0xC000>;
 170                         i-cache-line-size = <64>;
 171                         i-cache-sets = <192>;
 172                         next-level-cache = <&cluster4_l2>;
 173                         cpu-idle-states = <&cpu_pw15>;
 174                         #cooling-cells = <2>;
 175                 };
 176
 177                 cpu401: cpu@401 {
 178                         device_type = "cpu";
 179                         compatible = "arm,cortex-a72";
 180                         enable-method = "psci";
 181                         reg = <0x401>;
 182                         clocks = <&clockgen 1 4>;
 183                         d-cache-size = <0x8000>;
 184                         d-cache-line-size = <64>;
 185                         d-cache-sets = <128>;
 186                         i-cache-size = <0xC000>;
 187                         i-cache-line-size = <64>;
 188                         i-cache-sets = <192>;
 189                         next-level-cache = <&cluster4_l2>;
 190                         cpu-idle-states = <&cpu_pw15>;
 191                         #cooling-cells = <2>;
 192                 };
 193
 194                 cpu500: cpu@500 {
 195                         device_type = "cpu";
 196                         compatible = "arm,cortex-a72";
 197                         enable-method = "psci";
 198                         reg = <0x500>;
 199                         clocks = <&clockgen 1 5>;
 200                         d-cache-size = <0x8000>;
 201                         d-cache-line-size = <64>;
 202                         d-cache-sets = <128>;
 203                         i-cache-size = <0xC000>;
 204                         i-cache-line-size = <64>;
 205                         i-cache-sets = <192>;
 206                         next-level-cache = <&cluster5_l2>;
 207                         cpu-idle-states = <&cpu_pw15>;
 208                         #cooling-cells = <2>;
 209                 };
 210
 211                 cpu501: cpu@501 {
 212                         device_type = "cpu";
 213                         compatible = "arm,cortex-a72";
 214                         enable-method = "psci";
 215                         reg = <0x501>;
 216                         clocks = <&clockgen 1 5>;
 217                         d-cache-size = <0x8000>;
 218                         d-cache-line-size = <64>;
 219                         d-cache-sets = <128>;
 220                         i-cache-size = <0xC000>;
 221                         i-cache-line-size = <64>;
 222                         i-cache-sets = <192>;
 223                         next-level-cache = <&cluster5_l2>;
 224                         cpu-idle-states = <&cpu_pw15>;
 225                         #cooling-cells = <2>;
 226                 };
 227
 228                 cpu600: cpu@600 {
 229                         device_type = "cpu";
 230                         compatible = "arm,cortex-a72";
 231                         enable-method = "psci";
 232                         reg = <0x600>;
 233                         clocks = <&clockgen 1 6>;
 234                         d-cache-size = <0x8000>;
 235                         d-cache-line-size = <64>;
 236                         d-cache-sets = <128>;
 237                         i-cache-size = <0xC000>;
 238                         i-cache-line-size = <64>;
 239                         i-cache-sets = <192>;
 240                         next-level-cache = <&cluster6_l2>;
 241                         cpu-idle-states = <&cpu_pw15>;
 242                         #cooling-cells = <2>;
 243                 };
 244
 245                 cpu601: cpu@601 {
 246                         device_type = "cpu";
 247                         compatible = "arm,cortex-a72";
 248                         enable-method = "psci";
 249                         reg = <0x601>;
 250                         clocks = <&clockgen 1 6>;
 251                         d-cache-size = <0x8000>;
 252                         d-cache-line-size = <64>;
 253                         d-cache-sets = <128>;
 254                         i-cache-size = <0xC000>;
 255                         i-cache-line-size = <64>;
 256                         i-cache-sets = <192>;
 257                         next-level-cache = <&cluster6_l2>;
 258                         cpu-idle-states = <&cpu_pw15>;
 259                         #cooling-cells = <2>;
 260                 };
 261
 262                 cpu700: cpu@700 {
 263                         device_type = "cpu";
 264                         compatible = "arm,cortex-a72";
 265                         enable-method = "psci";
 266                         reg = <0x700>;
 267                         clocks = <&clockgen 1 7>;
 268                         d-cache-size = <0x8000>;
 269                         d-cache-line-size = <64>;
 270                         d-cache-sets = <128>;
 271                         i-cache-size = <0xC000>;
 272                         i-cache-line-size = <64>;
 273                         i-cache-sets = <192>;
 274                         next-level-cache = <&cluster7_l2>;
 275                         cpu-idle-states = <&cpu_pw15>;
 276                         #cooling-cells = <2>;
 277                 };
 278
 279                 cpu701: cpu@701 {
 280                         device_type = "cpu";
 281                         compatible = "arm,cortex-a72";
 282                         enable-method = "psci";
 283                         reg = <0x701>;
 284                         clocks = <&clockgen 1 7>;
 285                         d-cache-size = <0x8000>;
 286                         d-cache-line-size = <64>;
 287                         d-cache-sets = <128>;
 288                         i-cache-size = <0xC000>;
 289                         i-cache-line-size = <64>;
 290                         i-cache-sets = <192>;
 291                         next-level-cache = <&cluster7_l2>;
 292                         cpu-idle-states = <&cpu_pw15>;
 293                         #cooling-cells = <2>;
 294                 };
 295
 296                 cluster0_l2: l2-cache0 {
 297                         compatible = "cache";
 298                         cache-size = <0x100000>;
 299                         cache-line-size = <64>;
 300                         cache-sets = <1024>;
 301                         cache-level = <2>;
 302                 };
 303
 304                 cluster1_l2: l2-cache1 {
 305                         compatible = "cache";
 306                         cache-size = <0x100000>;
 307                         cache-line-size = <64>;
 308                         cache-sets = <1024>;
 309                         cache-level = <2>;
 310                 };
 311
 312                 cluster2_l2: l2-cache2 {
 313                         compatible = "cache";
 314                         cache-size = <0x100000>;
 315                         cache-line-size = <64>;
 316                         cache-sets = <1024>;
 317                         cache-level = <2>;
 318                 };
 319
 320                 cluster3_l2: l2-cache3 {
 321                         compatible = "cache";
 322                         cache-size = <0x100000>;
 323                         cache-line-size = <64>;
 324                         cache-sets = <1024>;
 325                         cache-level = <2>;
 326                 };
 327
 328                 cluster4_l2: l2-cache4 {
 329                         compatible = "cache";
 330                         cache-size = <0x100000>;
 331                         cache-line-size = <64>;
 332                         cache-sets = <1024>;
 333                         cache-level = <2>;
 334                 };
 335
 336                 cluster5_l2: l2-cache5 {
 337                         compatible = "cache";
 338                         cache-size = <0x100000>;
 339                         cache-line-size = <64>;
 340                         cache-sets = <1024>;
 341                         cache-level = <2>;
 342                 };
 343
 344                 cluster6_l2: l2-cache6 {
 345                         compatible = "cache";
 346                         cache-size = <0x100000>;
 347                         cache-line-size = <64>;
 348                         cache-sets = <1024>;
 349                         cache-level = <2>;
 350                 };
 351
 352                 cluster7_l2: l2-cache7 {
 353                         compatible = "cache";
 354                         cache-size = <0x100000>;
 355                         cache-line-size = <64>;
 356                         cache-sets = <1024>;
 357                         cache-level = <2>;
 358                 };
 359
 360                 cpu_pw15: cpu-pw15 {
 361                         compatible = "arm,idle-state";
 362                         idle-state-name = "PW15";
 363                         arm,psci-suspend-param = <0x0>;
 364                         entry-latency-us = <2000>;
 365                         exit-latency-us = <2000>;
 366                         min-residency-us = <6000>;
 367                   };
 368         };
 369
 370         gic: interrupt-controller@6000000 {
 371                 compatible = "arm,gic-v3";
 372                 reg = <0x0 0x06000000 0 0x10000>, // GIC Dist
 373                         <0x0 0x06200000 0 0x200000>, // GICR (RD_base +
 374                                                      // SGI_base)
 375                         <0x0 0x0c0c0000 0 0x2000>, // GICC
 376                         <0x0 0x0c0d0000 0 0x1000>, // GICH
 377                         <0x0 0x0c0e0000 0 0x20000>; // GICV
 378                 #interrupt-cells = <3>;
 379                 #address-cells = <2>;
 380                 #size-cells = <2>;
 381                 ranges;
 382                 interrupt-controller;
 383                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 384
 385                 its: gic-its@6020000 {
 386                         compatible = "arm,gic-v3-its";
 387                         msi-controller;
 388                         reg = <0x0 0x6020000 0 0x20000>;
 389                 };
 390         };
 391
 392         timer {
 393                 compatible = "arm,armv8-timer";
 394                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
 395                              <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
 396                              <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
 397                              <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
 398         };
 399
 400         pmu {
 401                 compatible = "arm,cortex-a72-pmu";
 402                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
 403         };
 404
 405         psci {
 406                 compatible = "arm,psci-0.2";
 407                 method = "smc";
 408         };
 409
 410         memory@80000000 {
 411                 // DRAM space - 1, size : 2 GB DRAM
 412                 device_type = "memory";
 413                 reg = <0x00000000 0x80000000 0 0x80000000>;
 414         };
 415
 416         ddr1: memory-controller@1080000 {
 417                 compatible = "fsl,qoriq-memory-controller";
 418                 reg = <0x0 0x1080000 0x0 0x1000>;
 419                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 420                 little-endian;
 421         };
 422
 423         ddr2: memory-controller@1090000 {
 424                 compatible = "fsl,qoriq-memory-controller";
 425                 reg = <0x0 0x1090000 0x0 0x1000>;
 426                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 427                 little-endian;
 428         };
 429
 430         // One clock unit-sysclk node which bootloader require during DT fix-up
 431         sysclk: sysclk {
 432                 compatible = "fixed-clock";
 433                 #clock-cells = <0>;
 434                 clock-frequency = <100000000>; // fixed up by bootloader
 435                 clock-output-names = "sysclk";
 436         };
 437
 438         thermal-zones {
 439                 core_thermal1: core-thermal1 {
 440                         polling-delay-passive = <1000>;
 441                         polling-delay = <5000>;
 442                         thermal-sensors = <&tmu 0>;
 443
 444                         trips {
 445                                 core_cluster_alert: core-cluster-alert {
 446                                         temperature = <85000>;
 447                                         hysteresis = <2000>;
 448                                         type = "passive";
 449                                 };
 450
 451                                 core_cluster_crit: core-cluster-crit {
 452                                         temperature = <95000>;
 453                                         hysteresis = <2000>;
 454                                         type = "critical";
 455                                 };
 456                         };
 457
 458                         cooling-maps {
 459                                 map0 {
 460                                         trip = <&core_cluster_alert>;
 461                                         cooling-device =
 462                                                 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 463                                                 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 464                                                 <&cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 465                                                 <&cpu101 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 466                                                 <&cpu200 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 467                                                 <&cpu201 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 468                                                 <&cpu300 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 469                                                 <&cpu301 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 470                                                 <&cpu400 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 471                                                 <&cpu401 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 472                                                 <&cpu500 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 473                                                 <&cpu501 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 474                                                 <&cpu600 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 475                                                 <&cpu601 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 476                                                 <&cpu700 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 477                                                 <&cpu701 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 478                                 };
 479                         };
 480                 };
 481         };
 482
 483         soc {
 484                 compatible = "simple-bus";
 485                 #address-cells = <2>;
 486                 #size-cells = <2>;
 487                 ranges;
 488                 dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
 489
 490                 crypto: crypto@8000000 {
 491                         compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
 492                         fsl,sec-era = <10>;
 493                         #address-cells = <1>;
 494                         #size-cells = <1>;
 495                         ranges = <0x0 0x00 0x8000000 0x100000>;
 496                         reg = <0x00 0x8000000 0x0 0x100000>;
 497                         interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
 498                         dma-coherent;
 499                         status = "disabled";
 500
 501                         sec_jr0: jr@10000 {
 502                                 compatible = "fsl,sec-v5.0-job-ring",
 503                                              "fsl,sec-v4.0-job-ring";
 504                                 reg        = <0x10000 0x10000>;
 505                                 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
 506                         };
 507
 508                         sec_jr1: jr@20000 {
 509                                 compatible = "fsl,sec-v5.0-job-ring",
 510                                              "fsl,sec-v4.0-job-ring";
 511                                 reg        = <0x20000 0x10000>;
 512                                 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
 513                         };
 514
 515                         sec_jr2: jr@30000 {
 516                                 compatible = "fsl,sec-v5.0-job-ring",
 517                                              "fsl,sec-v4.0-job-ring";
 518                                 reg        = <0x30000 0x10000>;
 519                                 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
 520                         };
 521
 522                         sec_jr3: jr@40000 {
 523                                 compatible = "fsl,sec-v5.0-job-ring",
 524                                              "fsl,sec-v4.0-job-ring";
 525                                 reg        = <0x40000 0x10000>;
 526                                 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 527                         };
 528                 };
 529
 530                 clockgen: clock-controller@1300000 {
 531                         compatible = "fsl,lx2160a-clockgen";
 532                         reg = <0 0x1300000 0 0xa0000>;
 533                         #clock-cells = <2>;
 534                         clocks = <&sysclk>;
 535                 };
 536
 537                 dcfg: syscon@1e00000 {
 538                         compatible = "fsl,lx2160a-dcfg", "syscon";
 539                         reg = <0x0 0x1e00000 0x0 0x10000>;
 540                         little-endian;
 541                 };
 542
 543                 tmu: tmu@1f80000 {
 544                         compatible = "fsl,qoriq-tmu";
 545                         reg = <0x0 0x1f80000 0x0 0x10000>;
 546                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 547                         fsl,tmu-range = <0x800000e6 0x8001017d>;
 548                         fsl,tmu-calibration =
 549                                 /* Calibration data group 1 */
 550                                 <0x00000000 0x00000035
 551                                 /* Calibration data group 2 */
 552                                 0x00010001 0x00000154>;
 553                         little-endian;
 554                         #thermal-sensor-cells = <1>;
 555                 };
 556
 557                 i2c0: i2c@2000000 {
 558                         compatible = "fsl,vf610-i2c";
 559                         #address-cells = <1>;
 560                         #size-cells = <0>;
 561                         reg = <0x0 0x2000000 0x0 0x10000>;
 562                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 563                         clock-names = "i2c";
 564                         clocks = <&clockgen 4 15>;
 565                         scl-gpio = <&gpio2 15 GPIO_ACTIVE_HIGH>;
 566                         status = "disabled";
 567                 };
 568
 569                 i2c1: i2c@2010000 {
 570                         compatible = "fsl,vf610-i2c";
 571                         #address-cells = <1>;
 572                         #size-cells = <0>;
 573                         reg = <0x0 0x2010000 0x0 0x10000>;
 574                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 575                         clock-names = "i2c";
 576                         clocks = <&clockgen 4 15>;
 577                         status = "disabled";
 578                 };
 579
 580                 i2c2: i2c@2020000 {
 581                         compatible = "fsl,vf610-i2c";
 582                         #address-cells = <1>;
 583                         #size-cells = <0>;
 584                         reg = <0x0 0x2020000 0x0 0x10000>;
 585                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 586                         clock-names = "i2c";
 587                         clocks = <&clockgen 4 15>;
 588                         status = "disabled";
 589                 };
 590
 591                 i2c3: i2c@2030000 {
 592                         compatible = "fsl,vf610-i2c";
 593                         #address-cells = <1>;
 594                         #size-cells = <0>;
 595                         reg = <0x0 0x2030000 0x0 0x10000>;
 596                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 597                         clock-names = "i2c";
 598                         clocks = <&clockgen 4 15>;
 599                         status = "disabled";
 600                 };
 601
 602                 i2c4: i2c@2040000 {
 603                         compatible = "fsl,vf610-i2c";
 604                         #address-cells = <1>;
 605                         #size-cells = <0>;
 606                         reg = <0x0 0x2040000 0x0 0x10000>;
 607                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 608                         clock-names = "i2c";
 609                         clocks = <&clockgen 4 15>;
 610                         scl-gpio = <&gpio2 16 GPIO_ACTIVE_HIGH>;
 611                         status = "disabled";
 612                 };
 613
 614                 i2c5: i2c@2050000 {
 615                         compatible = "fsl,vf610-i2c";
 616                         #address-cells = <1>;
 617                         #size-cells = <0>;
 618                         reg = <0x0 0x2050000 0x0 0x10000>;
 619                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 620                         clock-names = "i2c";
 621                         clocks = <&clockgen 4 15>;
 622                         status = "disabled";
 623                 };
 624
 625                 i2c6: i2c@2060000 {
 626                         compatible = "fsl,vf610-i2c";
 627                         #address-cells = <1>;
 628                         #size-cells = <0>;
 629                         reg = <0x0 0x2060000 0x0 0x10000>;
 630                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 631                         clock-names = "i2c";
 632                         clocks = <&clockgen 4 15>;
 633                         status = "disabled";
 634                 };
 635
 636                 i2c7: i2c@2070000 {
 637                         compatible = "fsl,vf610-i2c";
 638                         #address-cells = <1>;
 639                         #size-cells = <0>;
 640                         reg = <0x0 0x2070000 0x0 0x10000>;
 641                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 642                         clock-names = "i2c";
 643                         clocks = <&clockgen 4 15>;
 644                         status = "disabled";
 645                 };
 646
 647                 fspi: spi@20c0000 {
 648                         compatible = "nxp,lx2160a-fspi";
 649                         #address-cells = <1>;
 650                         #size-cells = <0>;
 651                         reg = <0x0 0x20c0000 0x0 0x10000>,
 652                               <0x0 0x20000000 0x0 0x10000000>;
 653                         reg-names = "fspi_base", "fspi_mmap";
 654                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 655                         clocks = <&clockgen 4 3>, <&clockgen 4 3>;
 656                         clock-names = "fspi_en", "fspi";
 657                         status = "disabled";
 658                 };
 659
 660                 esdhc0: esdhc@2140000 {
 661                         compatible = "fsl,esdhc";
 662                         reg = <0x0 0x2140000 0x0 0x10000>;
 663                         interrupts = <0 28 0x4>; /* Level high type */
 664                         clocks = <&clockgen 4 1>;
 665                         dma-coherent;
 666                         voltage-ranges = <1800 1800 3300 3300>;
 667                         sdhci,auto-cmd12;
 668                         little-endian;
 669                         bus-width = <4>;
 670                         status = "disabled";
 671                 };
 672
 673                 esdhc1: esdhc@2150000 {
 674                         compatible = "fsl,esdhc";
 675                         reg = <0x0 0x2150000 0x0 0x10000>;
 676                         interrupts = <0 63 0x4>; /* Level high type */
 677                         clocks = <&clockgen 4 1>;
 678                         dma-coherent;
 679                         voltage-ranges = <1800 1800 3300 3300>;
 680                         sdhci,auto-cmd12;
 681                         broken-cd;
 682                         little-endian;
 683                         bus-width = <4>;
 684                         status = "disabled";
 685                 };
 686
 687                 uart0: serial@21c0000 {
 688                         compatible = "arm,sbsa-uart","arm,pl011";
 689                         reg = <0x0 0x21c0000 0x0 0x1000>;
 690                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 691                         current-speed = <115200>;
 692                         status = "disabled";
 693                 };
 694
 695                 uart1: serial@21d0000 {
 696                         compatible = "arm,sbsa-uart","arm,pl011";
 697                         reg = <0x0 0x21d0000 0x0 0x1000>;
 698                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 699                         current-speed = <115200>;
 700                         status = "disabled";
 701                 };
 702
 703                 uart2: serial@21e0000 {
 704                         compatible = "arm,sbsa-uart","arm,pl011";
 705                         reg = <0x0 0x21e0000 0x0 0x1000>;
 706                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 707                         current-speed = <115200>;
 708                         status = "disabled";
 709                 };
 710
 711                 uart3: serial@21f0000 {
 712                         compatible = "arm,sbsa-uart","arm,pl011";
 713                         reg = <0x0 0x21f0000 0x0 0x1000>;
 714                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 715                         current-speed = <115200>;
 716                         status = "disabled";
 717                 };
 718
 719                 gpio0: gpio@2300000 {
 720                         compatible = "fsl,qoriq-gpio";
 721                         reg = <0x0 0x2300000 0x0 0x10000>;
 722                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 723                         gpio-controller;
 724                         little-endian;
 725                         #gpio-cells = <2>;
 726                         interrupt-controller;
 727                         #interrupt-cells = <2>;
 728                 };
 729
 730                 gpio1: gpio@2310000 {
 731                         compatible = "fsl,qoriq-gpio";
 732                         reg = <0x0 0x2310000 0x0 0x10000>;
 733                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 734                         gpio-controller;
 735                         little-endian;
 736                         #gpio-cells = <2>;
 737                         interrupt-controller;
 738                         #interrupt-cells = <2>;
 739                 };
 740
 741                 gpio2: gpio@2320000 {
 742                         compatible = "fsl,qoriq-gpio";
 743                         reg = <0x0 0x2320000 0x0 0x10000>;
 744                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 745                         gpio-controller;
 746                         little-endian;
 747                         #gpio-cells = <2>;
 748                         interrupt-controller;
 749                         #interrupt-cells = <2>;
 750                 };
 751
 752                 gpio3: gpio@2330000 {
 753                         compatible = "fsl,qoriq-gpio";
 754                         reg = <0x0 0x2330000 0x0 0x10000>;
 755                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 756                         gpio-controller;
 757                         little-endian;
 758                         #gpio-cells = <2>;
 759                         interrupt-controller;
 760                         #interrupt-cells = <2>;
 761                 };
 762
 763                 watchdog@23a0000 {
 764                         compatible = "arm,sbsa-gwdt";
 765                         reg = <0x0 0x23a0000 0 0x1000>,
 766                               <0x0 0x2390000 0 0x1000>;
 767                         interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 768                         timeout-sec = <30>;
 769                 };
 770
 771                 usb0: usb@3100000 {
 772                         compatible = "snps,dwc3";
 773                         reg = <0x0 0x3100000 0x0 0x10000>;
 774                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 775                         dr_mode = "host";
 776                         snps,quirk-frame-length-adjustment = <0x20>;
 777                         snps,dis_rxdet_inp3_quirk;
 778                         snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
 779                         status = "disabled";
 780                 };
 781
 782                 usb1: usb@3110000 {
 783                         compatible = "snps,dwc3";
 784                         reg = <0x0 0x3110000 0x0 0x10000>;
 785                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 786                         dr_mode = "host";
 787                         snps,quirk-frame-length-adjustment = <0x20>;
 788                         snps,dis_rxdet_inp3_quirk;
 789                         snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
 790                         status = "disabled";
 791                 };
 792
 793                 sata0: sata@3200000 {
 794                         compatible = "fsl,lx2160a-ahci";
 795                         reg = <0x0 0x3200000 0x0 0x10000>,
 796                               <0x7 0x100520 0x0 0x4>;
 797                         reg-names = "ahci", "sata-ecc";
 798                         interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
 799                         clocks = <&clockgen 4 3>;
 800                         dma-coherent;
 801                         status = "disabled";
 802                 };
 803
 804                 sata1: sata@3210000 {
 805                         compatible = "fsl,lx2160a-ahci";
 806                         reg = <0x0 0x3210000 0x0 0x10000>,
 807                               <0x7 0x100520 0x0 0x4>;
 808                         reg-names = "ahci", "sata-ecc";
 809                         interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
 810                         clocks = <&clockgen 4 3>;
 811                         dma-coherent;
 812                         status = "disabled";
 813                 };
 814
 815                 sata2: sata@3220000 {
 816                         compatible = "fsl,lx2160a-ahci";
 817                         reg = <0x0 0x3220000 0x0 0x10000>,
 818                               <0x7 0x100520 0x0 0x4>;
 819                         reg-names = "ahci", "sata-ecc";
 820                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 821                         clocks = <&clockgen 4 3>;
 822                         dma-coherent;
 823                         status = "disabled";
 824                 };
 825
 826                 sata3: sata@3230000 {
 827                         compatible = "fsl,lx2160a-ahci";
 828                         reg = <0x0 0x3230000 0x0 0x10000>,
 829                               <0x7 0x100520 0x0 0x4>;
 830                         reg-names = "ahci", "sata-ecc";
 831                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 832                         clocks = <&clockgen 4 3>;
 833                         dma-coherent;
 834                         status = "disabled";
 835                 };
 836
 837                 pcie@3400000 {
 838                         compatible = "fsl,lx2160a-pcie";
 839                         reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
 840                                0x80 0x00000000 0x0 0x00001000>; /* configuration space */
 841                         reg-names = "csr_axi_slave", "config_axi_slave";
 842                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
 843                                      <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
 844                                      <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
 845                         interrupt-names = "aer", "pme", "intr";
 846                         #address-cells = <3>;
 847                         #size-cells = <2>;
 848                         device_type = "pci";
 849                         dma-coherent;
 850                         apio-wins = <8>;
 851                         ppio-wins = <8>;
 852                         bus-range = <0x0 0xff>;
 853                         ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 854                         msi-parent = <&its>;
 855                         #interrupt-cells = <1>;
 856                         interrupt-map-mask = <0 0 0 7>;
 857                         interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
 858                                         <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
 859                                         <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
 860                                         <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 861                         iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
 862                         status = "disabled";
 863                 };
 864
 865                 pcie@3500000 {
 866                         compatible = "fsl,lx2160a-pcie";
 867                         reg = <0x00 0x03500000 0x0 0x00100000   /* controller registers */
 868                                0x88 0x00000000 0x0 0x00001000>; /* configuration space */
 869                         reg-names = "csr_axi_slave", "config_axi_slave";
 870                         interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
 871                                      <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
 872                                      <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
 873                         interrupt-names = "aer", "pme", "intr";
 874                         #address-cells = <3>;
 875                         #size-cells = <2>;
 876                         device_type = "pci";
 877                         dma-coherent;
 878                         apio-wins = <8>;
 879                         ppio-wins = <8>;
 880                         bus-range = <0x0 0xff>;
 881                         ranges = <0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 882                         msi-parent = <&its>;
 883                         #interrupt-cells = <1>;
 884                         interrupt-map-mask = <0 0 0 7>;
 885                         interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 886                                         <0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 887                                         <0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 888                                         <0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 889                         iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
 890                         status = "disabled";
 891                 };
 892
 893                 pcie@3600000 {
 894                         compatible = "fsl,lx2160a-pcie";
 895                         reg = <0x00 0x03600000 0x0 0x00100000   /* controller registers */
 896                                0x90 0x00000000 0x0 0x00001000>; /* configuration space */
 897                         reg-names = "csr_axi_slave", "config_axi_slave";
 898                         interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
 899                                      <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
 900                                      <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
 901                         interrupt-names = "aer", "pme", "intr";
 902                         #address-cells = <3>;
 903                         #size-cells = <2>;
 904                         device_type = "pci";
 905                         dma-coherent;
 906                         apio-wins = <256>;
 907                         ppio-wins = <24>;
 908                         bus-range = <0x0 0xff>;
 909                         ranges = <0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 910                         msi-parent = <&its>;
 911                         #interrupt-cells = <1>;
 912                         interrupt-map-mask = <0 0 0 7>;
 913                         interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
 914                                         <0000 0 0 2 &gic 0 0 GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 915                                         <0000 0 0 3 &gic 0 0 GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 916                                         <0000 0 0 4 &gic 0 0 GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
 917                         iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
 918                         status = "disabled";
 919                 };
 920
 921                 pcie@3700000 {
 922                         compatible = "fsl,lx2160a-pcie";
 923                         reg = <0x00 0x03700000 0x0 0x00100000   /* controller registers */
 924                                0x98 0x00000000 0x0 0x00001000>; /* configuration space */
 925                         reg-names = "csr_axi_slave", "config_axi_slave";
 926                         interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
 927                                      <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
 928                                      <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
 929                         interrupt-names = "aer", "pme", "intr";
 930                         #address-cells = <3>;
 931                         #size-cells = <2>;
 932                         device_type = "pci";
 933                         dma-coherent;
 934                         apio-wins = <8>;
 935                         ppio-wins = <8>;
 936                         bus-range = <0x0 0xff>;
 937                         ranges = <0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 938                         msi-parent = <&its>;
 939                         #interrupt-cells = <1>;
 940                         interrupt-map-mask = <0 0 0 7>;
 941                         interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
 942                                         <0000 0 0 2 &gic 0 0 GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
 943                                         <0000 0 0 3 &gic 0 0 GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
 944                                         <0000 0 0 4 &gic 0 0 GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
 945                         iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
 946                         status = "disabled";
 947                 };
 948
 949                 pcie@3800000 {
 950                         compatible = "fsl,lx2160a-pcie";
 951                         reg = <0x00 0x03800000 0x0 0x00100000   /* controller registers */
 952                                0xa0 0x00000000 0x0 0x00001000>; /* configuration space */
 953                         reg-names = "csr_axi_slave", "config_axi_slave";
 954                         interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
 955                                      <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
 956                                      <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
 957                         interrupt-names = "aer", "pme", "intr";
 958                         #address-cells = <3>;
 959                         #size-cells = <2>;
 960                         device_type = "pci";
 961                         dma-coherent;
 962                         apio-wins = <256>;
 963                         ppio-wins = <24>;
 964                         bus-range = <0x0 0xff>;
 965                         ranges = <0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 966                         msi-parent = <&its>;
 967                         #interrupt-cells = <1>;
 968                         interrupt-map-mask = <0 0 0 7>;
 969                         interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
 970                                         <0000 0 0 2 &gic 0 0 GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
 971                                         <0000 0 0 3 &gic 0 0 GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
 972                                         <0000 0 0 4 &gic 0 0 GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
 973                         iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
 974                         status = "disabled";
 975                 };
 976
 977                 pcie@3900000 {
 978                         compatible = "fsl,lx2160a-pcie";
 979                         reg = <0x00 0x03900000 0x0 0x00100000   /* controller registers */
 980                                0xa8 0x00000000 0x0 0x00001000>; /* configuration space */
 981                         reg-names = "csr_axi_slave", "config_axi_slave";
 982                         interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
 983                                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
 984                                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
 985                         interrupt-names = "aer", "pme", "intr";
 986                         #address-cells = <3>;
 987                         #size-cells = <2>;
 988                         device_type = "pci";
 989                         dma-coherent;
 990                         apio-wins = <8>;
 991                         ppio-wins = <8>;
 992                         bus-range = <0x0 0xff>;
 993                         ranges = <0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 994                         msi-parent = <&its>;
 995                         #interrupt-cells = <1>;
 996                         interrupt-map-mask = <0 0 0 7>;
 997                         interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
 998                                         <0000 0 0 2 &gic 0 0 GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
 999                                         <0000 0 0 3 &gic 0 0 GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
1000                                         <0000 0 0 4 &gic 0 0 GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1001                         iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1002                         status = "disabled";
1003                 };
1004
1005                 smmu: iommu@5000000 {
1006                         compatible = "arm,mmu-500";
1007                         reg = <0 0x5000000 0 0x800000>;
1008                         #iommu-cells = <1>;
1009                         #global-interrupts = <14>;
1010                                      // global secure fault
1011                         interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
1012                                      // combined secure
1013                                      <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
1014                                      // global non-secure fault
1015                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
1016                                      // combined non-secure
1017                                      <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
1018                                      // performance counter interrupts 0-9
1019                                      <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
1020                                      <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
1021                                      <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
1022                                      <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
1023                                      <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
1024                                      <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
1025                                      <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
1026                                      <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
1027                                      <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
1028                                      <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
1029                                      // per context interrupt, 64 interrupts
1030                                      <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
1031                                      <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
1032                                      <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
1033                                      <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
1034                                      <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
1035                                      <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
1036                                      <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
1037                                      <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
1038                                      <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
1039                                      <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
1040                                      <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
1041                                      <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
1042                                      <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
1043                                      <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
1044                                      <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
1045                                      <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
1046                                      <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
1047                                      <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
1048                                      <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
1049                                      <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
1050                                      <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
1051                                      <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
1052                                      <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
1053                                      <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
1054                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1055                                      <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
1056                                      <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
1057                                      <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
1058                                      <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
1059                                      <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
1060                                      <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
1061                                      <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
1062                                      <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
1063                                      <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
1064                                      <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
1065                                      <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
1066                                      <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
1067                                      <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
1068                                      <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
1069                                      <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
1070                                      <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
1071                                      <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
1072                                      <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
1073                                      <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
1074                                      <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
1075                                      <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
1076                                      <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
1077                                      <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
1078                                      <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
1079                                      <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
1080                                      <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
1081                                      <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
1082                                      <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
1083                                      <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
1084                                      <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
1085                                      <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
1086                                      <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
1087                                      <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
1088                                      <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
1089                                      <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
1090                                      <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
1091                                      <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
1092                                      <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
1093                                      <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
1094                         dma-coherent;
1095                 };
1096
1097                 console@8340020 {
1098                         compatible = "fsl,dpaa2-console";
1099                         reg = <0x00000000 0x08340020 0 0x2>;
1100                 };
1101
1102                 ptp-timer@8b95000 {
1103                         compatible = "fsl,dpaa2-ptp";
1104                         reg = <0x0 0x8b95000 0x0 0x100>;
1105                         clocks = <&clockgen 4 1>;
1106                         little-endian;
1107                         fsl,extts-fifo;
1108                 };
1109
1110                 /* WRIOP0: 0x8b8_0000, E-MDIO1: 0x1_6000 */
1111                 emdio1: mdio@8b96000 {
1112                         compatible = "fsl,fman-memac-mdio";
1113                         reg = <0x0 0x8b96000 0x0 0x1000>;
1114                         interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
1115                         #address-cells = <1>;
1116                         #size-cells = <0>;
1117                         little-endian;
1118                         status = "disabled";
1119                 };
1120
1121                 emdio2: mdio@8b97000 {
1122                         compatible = "fsl,fman-memac-mdio";
1123                         reg = <0x0 0x8b97000 0x0 0x1000>;
1124                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
1125                         little-endian;
1126                         #address-cells = <1>;
1127                         #size-cells = <0>;
1128                         status = "disabled";
1129                 };
1130
1131                 fsl_mc: fsl-mc@80c000000 {
1132                         compatible = "fsl,qoriq-mc";
1133                         reg = <0x00000008 0x0c000000 0 0x40>,
1134                               <0x00000000 0x08340000 0 0x40000>;
1135                         msi-parent = <&its>;
1136                         /* iommu-map property is fixed up by u-boot */
1137                         iommu-map = <0 &smmu 0 0>;
1138                         dma-coherent;
1139                         #address-cells = <3>;
1140                         #size-cells = <1>;
1141
1142                         /*
1143                          * Region type 0x0 - MC portals
1144                          * Region type 0x1 - QBMAN portals
1145                          */
1146                         ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
1147                                   0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
1148
1149                         /*
1150                          * Define the maximum number of MACs present on the SoC.
1151                          */
1152                         dpmacs {
1153                                 #address-cells = <1>;
1154                                 #size-cells = <0>;
1155
1156                                 dpmac1: dpmac@1 {
1157                                         compatible = "fsl,qoriq-mc-dpmac";
1158                                         reg = <0x1>;
1159                                 };
1160
1161                                 dpmac2: dpmac@2 {
1162                                         compatible = "fsl,qoriq-mc-dpmac";
1163                                         reg = <0x2>;
1164                                 };
1165
1166                                 dpmac3: dpmac@3 {
1167                                         compatible = "fsl,qoriq-mc-dpmac";
1168                                         reg = <0x3>;
1169                                 };
1170
1171                                 dpmac4: dpmac@4 {
1172                                         compatible = "fsl,qoriq-mc-dpmac";
1173                                         reg = <0x4>;
1174                                 };
1175
1176                                 dpmac5: dpmac@5 {
1177                                         compatible = "fsl,qoriq-mc-dpmac";
1178                                         reg = <0x5>;
1179                                 };
1180
1181                                 dpmac6: dpmac@6 {
1182                                         compatible = "fsl,qoriq-mc-dpmac";
1183                                         reg = <0x6>;
1184                                 };
1185
1186                                 dpmac7: dpmac@7 {
1187                                         compatible = "fsl,qoriq-mc-dpmac";
1188                                         reg = <0x7>;
1189                                 };
1190
1191                                 dpmac8: dpmac@8 {
1192                                         compatible = "fsl,qoriq-mc-dpmac";
1193                                         reg = <0x8>;
1194                                 };
1195
1196                                 dpmac9: dpmac@9 {
1197                                         compatible = "fsl,qoriq-mc-dpmac";
1198                                         reg = <0x9>;
1199                                 };
1200
1201                                 dpmac10: dpmac@a {
1202                                         compatible = "fsl,qoriq-mc-dpmac";
1203                                         reg = <0xa>;
1204                                 };
1205
1206                                 dpmac11: dpmac@b {
1207                                         compatible = "fsl,qoriq-mc-dpmac";
1208                                         reg = <0xb>;
1209                                 };
1210
1211                                 dpmac12: dpmac@c {
1212                                         compatible = "fsl,qoriq-mc-dpmac";
1213                                         reg = <0xc>;
1214                                 };
1215
1216                                 dpmac13: dpmac@d {
1217                                         compatible = "fsl,qoriq-mc-dpmac";
1218                                         reg = <0xd>;
1219                                 };
1220
1221                                 dpmac14: dpmac@e {
1222                                         compatible = "fsl,qoriq-mc-dpmac";
1223                                         reg = <0xe>;
1224                                 };
1225
1226                                 dpmac15: dpmac@f {
1227                                         compatible = "fsl,qoriq-mc-dpmac";
1228                                         reg = <0xf>;
1229                                 };
1230
1231                                 dpmac16: dpmac@10 {
1232                                         compatible = "fsl,qoriq-mc-dpmac";
1233                                         reg = <0x10>;
1234                                 };
1235
1236                                 dpmac17: dpmac@11 {
1237                                         compatible = "fsl,qoriq-mc-dpmac";
1238                                         reg = <0x11>;
1239                                 };
1240
1241                                 dpmac18: dpmac@12 {
1242                                         compatible = "fsl,qoriq-mc-dpmac";
1243                                         reg = <0x12>;
1244                                 };
1245                         };
1246                 };
1247         };
1248 };