sys/gnu/dts/arm64/qcom/sdm845.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * SDM845 SoC device tree source
   4  *
   5  * Copyright (c) 2018, The Linux Foundation. All rights reserved.
   6  */
   7
   8 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
   9 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
  10 #include <dt-bindings/clock/qcom,gpucc-sdm845.h>
  11 #include <dt-bindings/clock/qcom,lpass-sdm845.h>
  12 #include <dt-bindings/clock/qcom,rpmh.h>
  13 #include <dt-bindings/clock/qcom,videocc-sdm845.h>
  14 #include <dt-bindings/interconnect/qcom,sdm845.h>
  15 #include <dt-bindings/interrupt-controller/arm-gic.h>
  16 #include <dt-bindings/phy/phy-qcom-qusb2.h>
  17 #include <dt-bindings/power/qcom-rpmpd.h>
  18 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
  19 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
  20 #include <dt-bindings/soc/qcom,apr.h>
  21 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
  22 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
  23 #include <dt-bindings/thermal/thermal.h>
  24
  25 / {
  26         interrupt-parent = <&intc>;
  27
  28         #address-cells = <2>;
  29         #size-cells = <2>;
  30
  31         aliases {
  32                 i2c0 = &i2c0;
  33                 i2c1 = &i2c1;
  34                 i2c2 = &i2c2;
  35                 i2c3 = &i2c3;
  36                 i2c4 = &i2c4;
  37                 i2c5 = &i2c5;
  38                 i2c6 = &i2c6;
  39                 i2c7 = &i2c7;
  40                 i2c8 = &i2c8;
  41                 i2c9 = &i2c9;
  42                 i2c10 = &i2c10;
  43                 i2c11 = &i2c11;
  44                 i2c12 = &i2c12;
  45                 i2c13 = &i2c13;
  46                 i2c14 = &i2c14;
  47                 i2c15 = &i2c15;
  48                 spi0 = &spi0;
  49                 spi1 = &spi1;
  50                 spi2 = &spi2;
  51                 spi3 = &spi3;
  52                 spi4 = &spi4;
  53                 spi5 = &spi5;
  54                 spi6 = &spi6;
  55                 spi7 = &spi7;
  56                 spi8 = &spi8;
  57                 spi9 = &spi9;
  58                 spi10 = &spi10;
  59                 spi11 = &spi11;
  60                 spi12 = &spi12;
  61                 spi13 = &spi13;
  62                 spi14 = &spi14;
  63                 spi15 = &spi15;
  64         };
  65
  66         chosen { };
  67
  68         memory@80000000 {
  69                 device_type = "memory";
  70                 /* We expect the bootloader to fill in the size */
  71                 reg = <0 0x80000000 0 0>;
  72         };
  73
  74         reserved-memory {
  75                 #address-cells = <2>;
  76                 #size-cells = <2>;
  77                 ranges;
  78
  79                 hyp_mem: memory@85700000 {
  80                         reg = <0 0x85700000 0 0x600000>;
  81                         no-map;
  82                 };
  83
  84                 xbl_mem: memory@85e00000 {
  85                         reg = <0 0x85e00000 0 0x100000>;
  86                         no-map;
  87                 };
  88
  89                 aop_mem: memory@85fc0000 {
  90                         reg = <0 0x85fc0000 0 0x20000>;
  91                         no-map;
  92                 };
  93
  94                 aop_cmd_db_mem: memory@85fe0000 {
  95                         compatible = "qcom,cmd-db";
  96                         reg = <0x0 0x85fe0000 0 0x20000>;
  97                         no-map;
  98                 };
  99
 100                 smem_mem: memory@86000000 {
 101                         reg = <0x0 0x86000000 0 0x200000>;
 102                         no-map;
 103                 };
 104
 105                 tz_mem: memory@86200000 {
 106                         reg = <0 0x86200000 0 0x2d00000>;
 107                         no-map;
 108                 };
 109
 110                 rmtfs_mem: memory@88f00000 {
 111                         compatible = "qcom,rmtfs-mem";
 112                         reg = <0 0x88f00000 0 0x200000>;
 113                         no-map;
 114
 115                         qcom,client-id = <1>;
 116                         qcom,vmid = <15>;
 117                 };
 118
 119                 qseecom_mem: memory@8ab00000 {
 120                         reg = <0 0x8ab00000 0 0x1400000>;
 121                         no-map;
 122                 };
 123
 124                 camera_mem: memory@8bf00000 {
 125                         reg = <0 0x8bf00000 0 0x500000>;
 126                         no-map;
 127                 };
 128
 129                 ipa_fw_mem: memory@8c400000 {
 130                         reg = <0 0x8c400000 0 0x10000>;
 131                         no-map;
 132                 };
 133
 134                 ipa_gsi_mem: memory@8c410000 {
 135                         reg = <0 0x8c410000 0 0x5000>;
 136                         no-map;
 137                 };
 138
 139                 gpu_mem: memory@8c415000 {
 140                         reg = <0 0x8c415000 0 0x2000>;
 141                         no-map;
 142                 };
 143
 144                 adsp_mem: memory@8c500000 {
 145                         reg = <0 0x8c500000 0 0x1a00000>;
 146                         no-map;
 147                 };
 148
 149                 wlan_msa_mem: memory@8df00000 {
 150                         reg = <0 0x8df00000 0 0x100000>;
 151                         no-map;
 152                 };
 153
 154                 mpss_region: memory@8e000000 {
 155                         reg = <0 0x8e000000 0 0x7800000>;
 156                         no-map;
 157                 };
 158
 159                 venus_mem: memory@95800000 {
 160                         reg = <0 0x95800000 0 0x500000>;
 161                         no-map;
 162                 };
 163
 164                 cdsp_mem: memory@95d00000 {
 165                         reg = <0 0x95d00000 0 0x800000>;
 166                         no-map;
 167                 };
 168
 169                 mba_region: memory@96500000 {
 170                         reg = <0 0x96500000 0 0x200000>;
 171                         no-map;
 172                 };
 173
 174                 slpi_mem: memory@96700000 {
 175                         reg = <0 0x96700000 0 0x1400000>;
 176                         no-map;
 177                 };
 178
 179                 spss_mem: memory@97b00000 {
 180                         reg = <0 0x97b00000 0 0x100000>;
 181                         no-map;
 182                 };
 183         };
 184
 185         cpus {
 186                 #address-cells = <2>;
 187                 #size-cells = <0>;
 188
 189                 CPU0: cpu@0 {
 190                         device_type = "cpu";
 191                         compatible = "qcom,kryo385";
 192                         reg = <0x0 0x0>;
 193                         enable-method = "psci";
 194                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
 195                                            &LITTLE_CPU_SLEEP_1
 196                                            &CLUSTER_SLEEP_0>;
 197                         capacity-dmips-mhz = <607>;
 198                         dynamic-power-coefficient = <100>;
 199                         qcom,freq-domain = <&cpufreq_hw 0>;
 200                         #cooling-cells = <2>;
 201                         next-level-cache = <&L2_0>;
 202                         L2_0: l2-cache {
 203                                 compatible = "cache";
 204                                 next-level-cache = <&L3_0>;
 205                                 L3_0: l3-cache {
 206                                       compatible = "cache";
 207                                 };
 208                         };
 209                 };
 210
 211                 CPU1: cpu@100 {
 212                         device_type = "cpu";
 213                         compatible = "qcom,kryo385";
 214                         reg = <0x0 0x100>;
 215                         enable-method = "psci";
 216                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
 217                                            &LITTLE_CPU_SLEEP_1
 218                                            &CLUSTER_SLEEP_0>;
 219                         capacity-dmips-mhz = <607>;
 220                         dynamic-power-coefficient = <100>;
 221                         qcom,freq-domain = <&cpufreq_hw 0>;
 222                         #cooling-cells = <2>;
 223                         next-level-cache = <&L2_100>;
 224                         L2_100: l2-cache {
 225                                 compatible = "cache";
 226                                 next-level-cache = <&L3_0>;
 227                         };
 228                 };
 229
 230                 CPU2: cpu@200 {
 231                         device_type = "cpu";
 232                         compatible = "qcom,kryo385";
 233                         reg = <0x0 0x200>;
 234                         enable-method = "psci";
 235                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
 236                                            &LITTLE_CPU_SLEEP_1
 237                                            &CLUSTER_SLEEP_0>;
 238                         capacity-dmips-mhz = <607>;
 239                         dynamic-power-coefficient = <100>;
 240                         qcom,freq-domain = <&cpufreq_hw 0>;
 241                         #cooling-cells = <2>;
 242                         next-level-cache = <&L2_200>;
 243                         L2_200: l2-cache {
 244                                 compatible = "cache";
 245                                 next-level-cache = <&L3_0>;
 246                         };
 247                 };
 248
 249                 CPU3: cpu@300 {
 250                         device_type = "cpu";
 251                         compatible = "qcom,kryo385";
 252                         reg = <0x0 0x300>;
 253                         enable-method = "psci";
 254                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
 255                                            &LITTLE_CPU_SLEEP_1
 256                                            &CLUSTER_SLEEP_0>;
 257                         capacity-dmips-mhz = <607>;
 258                         dynamic-power-coefficient = <100>;
 259                         qcom,freq-domain = <&cpufreq_hw 0>;
 260                         #cooling-cells = <2>;
 261                         next-level-cache = <&L2_300>;
 262                         L2_300: l2-cache {
 263                                 compatible = "cache";
 264                                 next-level-cache = <&L3_0>;
 265                         };
 266                 };
 267
 268                 CPU4: cpu@400 {
 269                         device_type = "cpu";
 270                         compatible = "qcom,kryo385";
 271                         reg = <0x0 0x400>;
 272                         enable-method = "psci";
 273                         capacity-dmips-mhz = <1024>;
 274                         cpu-idle-states = <&BIG_CPU_SLEEP_0
 275                                            &BIG_CPU_SLEEP_1
 276                                            &CLUSTER_SLEEP_0>;
 277                         dynamic-power-coefficient = <396>;
 278                         qcom,freq-domain = <&cpufreq_hw 1>;
 279                         #cooling-cells = <2>;
 280                         next-level-cache = <&L2_400>;
 281                         L2_400: l2-cache {
 282                                 compatible = "cache";
 283                                 next-level-cache = <&L3_0>;
 284                         };
 285                 };
 286
 287                 CPU5: cpu@500 {
 288                         device_type = "cpu";
 289                         compatible = "qcom,kryo385";
 290                         reg = <0x0 0x500>;
 291                         enable-method = "psci";
 292                         capacity-dmips-mhz = <1024>;
 293                         cpu-idle-states = <&BIG_CPU_SLEEP_0
 294                                            &BIG_CPU_SLEEP_1
 295                                            &CLUSTER_SLEEP_0>;
 296                         dynamic-power-coefficient = <396>;
 297                         qcom,freq-domain = <&cpufreq_hw 1>;
 298                         #cooling-cells = <2>;
 299                         next-level-cache = <&L2_500>;
 300                         L2_500: l2-cache {
 301                                 compatible = "cache";
 302                                 next-level-cache = <&L3_0>;
 303                         };
 304                 };
 305
 306                 CPU6: cpu@600 {
 307                         device_type = "cpu";
 308                         compatible = "qcom,kryo385";
 309                         reg = <0x0 0x600>;
 310                         enable-method = "psci";
 311                         capacity-dmips-mhz = <1024>;
 312                         cpu-idle-states = <&BIG_CPU_SLEEP_0
 313                                            &BIG_CPU_SLEEP_1
 314                                            &CLUSTER_SLEEP_0>;
 315                         dynamic-power-coefficient = <396>;
 316                         qcom,freq-domain = <&cpufreq_hw 1>;
 317                         #cooling-cells = <2>;
 318                         next-level-cache = <&L2_600>;
 319                         L2_600: l2-cache {
 320                                 compatible = "cache";
 321                                 next-level-cache = <&L3_0>;
 322                         };
 323                 };
 324
 325                 CPU7: cpu@700 {
 326                         device_type = "cpu";
 327                         compatible = "qcom,kryo385";
 328                         reg = <0x0 0x700>;
 329                         enable-method = "psci";
 330                         capacity-dmips-mhz = <1024>;
 331                         cpu-idle-states = <&BIG_CPU_SLEEP_0
 332                                            &BIG_CPU_SLEEP_1
 333                                            &CLUSTER_SLEEP_0>;
 334                         dynamic-power-coefficient = <396>;
 335                         qcom,freq-domain = <&cpufreq_hw 1>;
 336                         #cooling-cells = <2>;
 337                         next-level-cache = <&L2_700>;
 338                         L2_700: l2-cache {
 339                                 compatible = "cache";
 340                                 next-level-cache = <&L3_0>;
 341                         };
 342                 };
 343
 344                 cpu-map {
 345                         cluster0 {
 346                                 core0 {
 347                                         cpu = <&CPU0>;
 348                                 };
 349
 350                                 core1 {
 351                                         cpu = <&CPU1>;
 352                                 };
 353
 354                                 core2 {
 355                                         cpu = <&CPU2>;
 356                                 };
 357
 358                                 core3 {
 359                                         cpu = <&CPU3>;
 360                                 };
 361
 362                                 core4 {
 363                                         cpu = <&CPU4>;
 364                                 };
 365
 366                                 core5 {
 367                                         cpu = <&CPU5>;
 368                                 };
 369
 370                                 core6 {
 371                                         cpu = <&CPU6>;
 372                                 };
 373
 374                                 core7 {
 375                                         cpu = <&CPU7>;
 376                                 };
 377                         };
 378                 };
 379
 380                 idle-states {
 381                         entry-method = "psci";
 382
 383                         LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
 384                                 compatible = "arm,idle-state";
 385                                 idle-state-name = "little-power-down";
 386                                 arm,psci-suspend-param = <0x40000003>;
 387                                 entry-latency-us = <350>;
 388                                 exit-latency-us = <461>;
 389                                 min-residency-us = <1890>;
 390                                 local-timer-stop;
 391                         };
 392
 393                         LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
 394                                 compatible = "arm,idle-state";
 395                                 idle-state-name = "little-rail-power-down";
 396                                 arm,psci-suspend-param = <0x40000004>;
 397                                 entry-latency-us = <360>;
 398                                 exit-latency-us = <531>;
 399                                 min-residency-us = <3934>;
 400                                 local-timer-stop;
 401                         };
 402
 403                         BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
 404                                 compatible = "arm,idle-state";
 405                                 idle-state-name = "big-power-down";
 406                                 arm,psci-suspend-param = <0x40000003>;
 407                                 entry-latency-us = <264>;
 408                                 exit-latency-us = <621>;
 409                                 min-residency-us = <952>;
 410                                 local-timer-stop;
 411                         };
 412
 413                         BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
 414                                 compatible = "arm,idle-state";
 415                                 idle-state-name = "big-rail-power-down";
 416                                 arm,psci-suspend-param = <0x40000004>;
 417                                 entry-latency-us = <702>;
 418                                 exit-latency-us = <1061>;
 419                                 min-residency-us = <4488>;
 420                                 local-timer-stop;
 421                         };
 422
 423                         CLUSTER_SLEEP_0: cluster-sleep-0 {
 424                                 compatible = "arm,idle-state";
 425                                 idle-state-name = "cluster-power-down";
 426                                 arm,psci-suspend-param = <0x400000F4>;
 427                                 entry-latency-us = <3263>;
 428                                 exit-latency-us = <6562>;
 429                                 min-residency-us = <9987>;
 430                                 local-timer-stop;
 431                         };
 432                 };
 433         };
 434
 435         pmu {
 436                 compatible = "arm,armv8-pmuv3";
 437                 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
 438         };
 439
 440         timer {
 441                 compatible = "arm,armv8-timer";
 442                 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
 443                              <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
 444                              <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
 445                              <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
 446         };
 447
 448         clocks {
 449                 xo_board: xo-board {
 450                         compatible = "fixed-clock";
 451                         #clock-cells = <0>;
 452                         clock-frequency = <38400000>;
 453                         clock-output-names = "xo_board";
 454                 };
 455
 456                 sleep_clk: sleep-clk {
 457                         compatible = "fixed-clock";
 458                         #clock-cells = <0>;
 459                         clock-frequency = <32764>;
 460                 };
 461         };
 462
 463         firmware {
 464                 scm {
 465                         compatible = "qcom,scm-sdm845", "qcom,scm";
 466                 };
 467         };
 468
 469         adsp_pas: remoteproc-adsp {
 470                 compatible = "qcom,sdm845-adsp-pas";
 471
 472                 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
 473                                       <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
 474                                       <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
 475                                       <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
 476                                       <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
 477                 interrupt-names = "wdog", "fatal", "ready",
 478                                   "handover", "stop-ack";
 479
 480                 clocks = <&rpmhcc RPMH_CXO_CLK>;
 481                 clock-names = "xo";
 482
 483                 memory-region = <&adsp_mem>;
 484
 485                 qcom,smem-states = <&adsp_smp2p_out 0>;
 486                 qcom,smem-state-names = "stop";
 487
 488                 status = "disabled";
 489
 490                 glink-edge {
 491                         interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
 492                         label = "lpass";
 493                         qcom,remote-pid = <2>;
 494                         mboxes = <&apss_shared 8>;
 495
 496                         apr {
 497                                 compatible = "qcom,apr-v2";
 498                                 qcom,glink-channels = "apr_audio_svc";
 499                                 qcom,apr-domain = <APR_DOMAIN_ADSP>;
 500                                 #address-cells = <1>;
 501                                 #size-cells = <0>;
 502                                 qcom,intents = <512 20>;
 503
 504                                 apr-service@3 {
 505                                         reg = <APR_SVC_ADSP_CORE>;
 506                                         compatible = "qcom,q6core";
 507                                         qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
 508                                 };
 509
 510                                 q6afe: apr-service@4 {
 511                                         compatible = "qcom,q6afe";
 512                                         reg = <APR_SVC_AFE>;
 513                                         qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
 514                                         q6afedai: dais {
 515                                                 compatible = "qcom,q6afe-dais";
 516                                                 #address-cells = <1>;
 517                                                 #size-cells = <0>;
 518                                                 #sound-dai-cells = <1>;
 519                                         };
 520                                 };
 521
 522                                 q6asm: apr-service@7 {
 523                                         compatible = "qcom,q6asm";
 524                                         reg = <APR_SVC_ASM>;
 525                                         qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
 526                                         q6asmdai: dais {
 527                                                 compatible = "qcom,q6asm-dais";
 528                                                 #address-cells = <1>;
 529                                                 #size-cells = <0>;
 530                                                 #sound-dai-cells = <1>;
 531                                                 iommus = <&apps_smmu 0x1821 0x0>;
 532                                         };
 533                                 };
 534
 535                                 q6adm: apr-service@8 {
 536                                         compatible = "qcom,q6adm";
 537                                         reg = <APR_SVC_ADM>;
 538                                         qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
 539                                         q6routing: routing {
 540                                                 compatible = "qcom,q6adm-routing";
 541                                                 #sound-dai-cells = <0>;
 542                                         };
 543                                 };
 544                         };
 545
 546                         fastrpc {
 547                                 compatible = "qcom,fastrpc";
 548                                 qcom,glink-channels = "fastrpcglink-apps-dsp";
 549                                 label = "adsp";
 550                                 #address-cells = <1>;
 551                                 #size-cells = <0>;
 552
 553                                 compute-cb@3 {
 554                                         compatible = "qcom,fastrpc-compute-cb";
 555                                         reg = <3>;
 556                                         iommus = <&apps_smmu 0x1823 0x0>;
 557                                 };
 558
 559                                 compute-cb@4 {
 560                                         compatible = "qcom,fastrpc-compute-cb";
 561                                         reg = <4>;
 562                                         iommus = <&apps_smmu 0x1824 0x0>;
 563                                 };
 564                         };
 565                 };
 566         };
 567
 568         cdsp_pas: remoteproc-cdsp {
 569                 compatible = "qcom,sdm845-cdsp-pas";
 570
 571                 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
 572                                       <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
 573                                       <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
 574                                       <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
 575                                       <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
 576                 interrupt-names = "wdog", "fatal", "ready",
 577                                   "handover", "stop-ack";
 578
 579                 clocks = <&rpmhcc RPMH_CXO_CLK>;
 580                 clock-names = "xo";
 581
 582                 memory-region = <&cdsp_mem>;
 583
 584                 qcom,smem-states = <&cdsp_smp2p_out 0>;
 585                 qcom,smem-state-names = "stop";
 586
 587                 status = "disabled";
 588
 589                 glink-edge {
 590                         interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>;
 591                         label = "turing";
 592                         qcom,remote-pid = <5>;
 593                         mboxes = <&apss_shared 4>;
 594                         fastrpc {
 595                                 compatible = "qcom,fastrpc";
 596                                 qcom,glink-channels = "fastrpcglink-apps-dsp";
 597                                 label = "cdsp";
 598                                 #address-cells = <1>;
 599                                 #size-cells = <0>;
 600
 601                                 compute-cb@1 {
 602                                         compatible = "qcom,fastrpc-compute-cb";
 603                                         reg = <1>;
 604                                         iommus = <&apps_smmu 0x1401 0x30>;
 605                                 };
 606
 607                                 compute-cb@2 {
 608                                         compatible = "qcom,fastrpc-compute-cb";
 609                                         reg = <2>;
 610                                         iommus = <&apps_smmu 0x1402 0x30>;
 611                                 };
 612
 613                                 compute-cb@3 {
 614                                         compatible = "qcom,fastrpc-compute-cb";
 615                                         reg = <3>;
 616                                         iommus = <&apps_smmu 0x1403 0x30>;
 617                                 };
 618
 619                                 compute-cb@4 {
 620                                         compatible = "qcom,fastrpc-compute-cb";
 621                                         reg = <4>;
 622                                         iommus = <&apps_smmu 0x1404 0x30>;
 623                                 };
 624
 625                                 compute-cb@5 {
 626                                         compatible = "qcom,fastrpc-compute-cb";
 627                                         reg = <5>;
 628                                         iommus = <&apps_smmu 0x1405 0x30>;
 629                                 };
 630
 631                                 compute-cb@6 {
 632                                         compatible = "qcom,fastrpc-compute-cb";
 633                                         reg = <6>;
 634                                         iommus = <&apps_smmu 0x1406 0x30>;
 635                                 };
 636
 637                                 compute-cb@7 {
 638                                         compatible = "qcom,fastrpc-compute-cb";
 639                                         reg = <7>;
 640                                         iommus = <&apps_smmu 0x1407 0x30>;
 641                                 };
 642
 643                                 compute-cb@8 {
 644                                         compatible = "qcom,fastrpc-compute-cb";
 645                                         reg = <8>;
 646                                         iommus = <&apps_smmu 0x1408 0x30>;
 647                                 };
 648                         };
 649                 };
 650         };
 651
 652         tcsr_mutex: hwlock {
 653                 compatible = "qcom,tcsr-mutex";
 654                 syscon = <&tcsr_mutex_regs 0 0x1000>;
 655                 #hwlock-cells = <1>;
 656         };
 657
 658         smem {
 659                 compatible = "qcom,smem";
 660                 memory-region = <&smem_mem>;
 661                 hwlocks = <&tcsr_mutex 3>;
 662         };
 663
 664         smp2p-cdsp {
 665                 compatible = "qcom,smp2p";
 666                 qcom,smem = <94>, <432>;
 667
 668                 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
 669
 670                 mboxes = <&apss_shared 6>;
 671
 672                 qcom,local-pid = <0>;
 673                 qcom,remote-pid = <5>;
 674
 675                 cdsp_smp2p_out: master-kernel {
 676                         qcom,entry-name = "master-kernel";
 677                         #qcom,smem-state-cells = <1>;
 678                 };
 679
 680                 cdsp_smp2p_in: slave-kernel {
 681                         qcom,entry-name = "slave-kernel";
 682
 683                         interrupt-controller;
 684                         #interrupt-cells = <2>;
 685                 };
 686         };
 687
 688         smp2p-lpass {
 689                 compatible = "qcom,smp2p";
 690                 qcom,smem = <443>, <429>;
 691
 692                 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
 693
 694                 mboxes = <&apss_shared 10>;
 695
 696                 qcom,local-pid = <0>;
 697                 qcom,remote-pid = <2>;
 698
 699                 adsp_smp2p_out: master-kernel {
 700                         qcom,entry-name = "master-kernel";
 701                         #qcom,smem-state-cells = <1>;
 702                 };
 703
 704                 adsp_smp2p_in: slave-kernel {
 705                         qcom,entry-name = "slave-kernel";
 706
 707                         interrupt-controller;
 708                         #interrupt-cells = <2>;
 709                 };
 710         };
 711
 712         smp2p-mpss {
 713                 compatible = "qcom,smp2p";
 714                 qcom,smem = <435>, <428>;
 715                 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
 716                 mboxes = <&apss_shared 14>;
 717                 qcom,local-pid = <0>;
 718                 qcom,remote-pid = <1>;
 719
 720                 modem_smp2p_out: master-kernel {
 721                         qcom,entry-name = "master-kernel";
 722                         #qcom,smem-state-cells = <1>;
 723                 };
 724
 725                 modem_smp2p_in: slave-kernel {
 726                         qcom,entry-name = "slave-kernel";
 727                         interrupt-controller;
 728                         #interrupt-cells = <2>;
 729                 };
 730
 731                 ipa_smp2p_out: ipa-ap-to-modem {
 732                         qcom,entry-name = "ipa";
 733                         #qcom,smem-state-cells = <1>;
 734                 };
 735
 736                 ipa_smp2p_in: ipa-modem-to-ap {
 737                         qcom,entry-name = "ipa";
 738                         interrupt-controller;
 739                         #interrupt-cells = <2>;
 740                 };
 741         };
 742
 743         smp2p-slpi {
 744                 compatible = "qcom,smp2p";
 745                 qcom,smem = <481>, <430>;
 746                 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>;
 747                 mboxes = <&apss_shared 26>;
 748                 qcom,local-pid = <0>;
 749                 qcom,remote-pid = <3>;
 750
 751                 slpi_smp2p_out: master-kernel {
 752                         qcom,entry-name = "master-kernel";
 753                         #qcom,smem-state-cells = <1>;
 754                 };
 755
 756                 slpi_smp2p_in: slave-kernel {
 757                         qcom,entry-name = "slave-kernel";
 758                         interrupt-controller;
 759                         #interrupt-cells = <2>;
 760                 };
 761         };
 762
 763         psci {
 764                 compatible = "arm,psci-1.0";
 765                 method = "smc";
 766         };
 767
 768         soc: soc@0 {
 769                 #address-cells = <2>;
 770                 #size-cells = <2>;
 771                 ranges = <0 0 0 0 0x10 0>;
 772                 dma-ranges = <0 0 0 0 0x10 0>;
 773                 compatible = "simple-bus";
 774
 775                 gcc: clock-controller@100000 {
 776                         compatible = "qcom,gcc-sdm845";
 777                         reg = <0 0x00100000 0 0x1f0000>;
 778                         #clock-cells = <1>;
 779                         #reset-cells = <1>;
 780                         #power-domain-cells = <1>;
 781                 };
 782
 783                 qfprom@784000 {
 784                         compatible = "qcom,qfprom";
 785                         reg = <0 0x00784000 0 0x8ff>;
 786                         #address-cells = <1>;
 787                         #size-cells = <1>;
 788
 789                         qusb2p_hstx_trim: hstx-trim-primary@1eb {
 790                                 reg = <0x1eb 0x1>;
 791                                 bits = <1 4>;
 792                         };
 793
 794                         qusb2s_hstx_trim: hstx-trim-secondary@1eb {
 795                                 reg = <0x1eb 0x2>;
 796                                 bits = <6 4>;
 797                         };
 798                 };
 799
 800                 rng: rng@793000 {
 801                         compatible = "qcom,prng-ee";
 802                         reg = <0 0x00793000 0 0x1000>;
 803                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
 804                         clock-names = "core";
 805                 };
 806
 807                 qupv3_id_0: geniqup@8c0000 {
 808                         compatible = "qcom,geni-se-qup";
 809                         reg = <0 0x008c0000 0 0x6000>;
 810                         clock-names = "m-ahb", "s-ahb";
 811                         clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
 812                                  <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
 813                         #address-cells = <2>;
 814                         #size-cells = <2>;
 815                         ranges;
 816                         status = "disabled";
 817
 818                         i2c0: i2c@880000 {
 819                                 compatible = "qcom,geni-i2c";
 820                                 reg = <0 0x00880000 0 0x4000>;
 821                                 clock-names = "se";
 822                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
 823                                 pinctrl-names = "default";
 824                                 pinctrl-0 = <&qup_i2c0_default>;
 825                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
 826                                 #address-cells = <1>;
 827                                 #size-cells = <0>;
 828                                 status = "disabled";
 829                         };
 830
 831                         spi0: spi@880000 {
 832                                 compatible = "qcom,geni-spi";
 833                                 reg = <0 0x00880000 0 0x4000>;
 834                                 clock-names = "se";
 835                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
 836                                 pinctrl-names = "default";
 837                                 pinctrl-0 = <&qup_spi0_default>;
 838                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
 839                                 #address-cells = <1>;
 840                                 #size-cells = <0>;
 841                                 status = "disabled";
 842                         };
 843
 844                         uart0: serial@880000 {
 845                                 compatible = "qcom,geni-uart";
 846                                 reg = <0 0x00880000 0 0x4000>;
 847                                 clock-names = "se";
 848                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
 849                                 pinctrl-names = "default";
 850                                 pinctrl-0 = <&qup_uart0_default>;
 851                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
 852                                 status = "disabled";
 853                         };
 854
 855                         i2c1: i2c@884000 {
 856                                 compatible = "qcom,geni-i2c";
 857                                 reg = <0 0x00884000 0 0x4000>;
 858                                 clock-names = "se";
 859                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
 860                                 pinctrl-names = "default";
 861                                 pinctrl-0 = <&qup_i2c1_default>;
 862                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
 863                                 #address-cells = <1>;
 864                                 #size-cells = <0>;
 865                                 status = "disabled";
 866                         };
 867
 868                         spi1: spi@884000 {
 869                                 compatible = "qcom,geni-spi";
 870                                 reg = <0 0x00884000 0 0x4000>;
 871                                 clock-names = "se";
 872                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
 873                                 pinctrl-names = "default";
 874                                 pinctrl-0 = <&qup_spi1_default>;
 875                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
 876                                 #address-cells = <1>;
 877                                 #size-cells = <0>;
 878                                 status = "disabled";
 879                         };
 880
 881                         uart1: serial@884000 {
 882                                 compatible = "qcom,geni-uart";
 883                                 reg = <0 0x00884000 0 0x4000>;
 884                                 clock-names = "se";
 885                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
 886                                 pinctrl-names = "default";
 887                                 pinctrl-0 = <&qup_uart1_default>;
 888                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
 889                                 status = "disabled";
 890                         };
 891
 892                         i2c2: i2c@888000 {
 893                                 compatible = "qcom,geni-i2c";
 894                                 reg = <0 0x00888000 0 0x4000>;
 895                                 clock-names = "se";
 896                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
 897                                 pinctrl-names = "default";
 898                                 pinctrl-0 = <&qup_i2c2_default>;
 899                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
 900                                 #address-cells = <1>;
 901                                 #size-cells = <0>;
 902                                 status = "disabled";
 903                         };
 904
 905                         spi2: spi@888000 {
 906                                 compatible = "qcom,geni-spi";
 907                                 reg = <0 0x00888000 0 0x4000>;
 908                                 clock-names = "se";
 909                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
 910                                 pinctrl-names = "default";
 911                                 pinctrl-0 = <&qup_spi2_default>;
 912                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
 913                                 #address-cells = <1>;
 914                                 #size-cells = <0>;
 915                                 status = "disabled";
 916                         };
 917
 918                         uart2: serial@888000 {
 919                                 compatible = "qcom,geni-uart";
 920                                 reg = <0 0x00888000 0 0x4000>;
 921                                 clock-names = "se";
 922                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
 923                                 pinctrl-names = "default";
 924                                 pinctrl-0 = <&qup_uart2_default>;
 925                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
 926                                 status = "disabled";
 927                         };
 928
 929                         i2c3: i2c@88c000 {
 930                                 compatible = "qcom,geni-i2c";
 931                                 reg = <0 0x0088c000 0 0x4000>;
 932                                 clock-names = "se";
 933                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
 934                                 pinctrl-names = "default";
 935                                 pinctrl-0 = <&qup_i2c3_default>;
 936                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
 937                                 #address-cells = <1>;
 938                                 #size-cells = <0>;
 939                                 status = "disabled";
 940                         };
 941
 942                         spi3: spi@88c000 {
 943                                 compatible = "qcom,geni-spi";
 944                                 reg = <0 0x0088c000 0 0x4000>;
 945                                 clock-names = "se";
 946                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
 947                                 pinctrl-names = "default";
 948                                 pinctrl-0 = <&qup_spi3_default>;
 949                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
 950                                 #address-cells = <1>;
 951                                 #size-cells = <0>;
 952                                 status = "disabled";
 953                         };
 954
 955                         uart3: serial@88c000 {
 956                                 compatible = "qcom,geni-uart";
 957                                 reg = <0 0x0088c000 0 0x4000>;
 958                                 clock-names = "se";
 959                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
 960                                 pinctrl-names = "default";
 961                                 pinctrl-0 = <&qup_uart3_default>;
 962                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
 963                                 status = "disabled";
 964                         };
 965
 966                         i2c4: i2c@890000 {
 967                                 compatible = "qcom,geni-i2c";
 968                                 reg = <0 0x00890000 0 0x4000>;
 969                                 clock-names = "se";
 970                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
 971                                 pinctrl-names = "default";
 972                                 pinctrl-0 = <&qup_i2c4_default>;
 973                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
 974                                 #address-cells = <1>;
 975                                 #size-cells = <0>;
 976                                 status = "disabled";
 977                         };
 978
 979                         spi4: spi@890000 {
 980                                 compatible = "qcom,geni-spi";
 981                                 reg = <0 0x00890000 0 0x4000>;
 982                                 clock-names = "se";
 983                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
 984                                 pinctrl-names = "default";
 985                                 pinctrl-0 = <&qup_spi4_default>;
 986                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
 987                                 #address-cells = <1>;
 988                                 #size-cells = <0>;
 989                                 status = "disabled";
 990                         };
 991
 992                         uart4: serial@890000 {
 993                                 compatible = "qcom,geni-uart";
 994                                 reg = <0 0x00890000 0 0x4000>;
 995                                 clock-names = "se";
 996                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
 997                                 pinctrl-names = "default";
 998                                 pinctrl-0 = <&qup_uart4_default>;
 999                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1000                                 status = "disabled";
1001                         };
1002
1003                         i2c5: i2c@894000 {
1004                                 compatible = "qcom,geni-i2c";
1005                                 reg = <0 0x00894000 0 0x4000>;
1006                                 clock-names = "se";
1007                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1008                                 pinctrl-names = "default";
1009                                 pinctrl-0 = <&qup_i2c5_default>;
1010                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1011                                 #address-cells = <1>;
1012                                 #size-cells = <0>;
1013                                 status = "disabled";
1014                         };
1015
1016                         spi5: spi@894000 {
1017                                 compatible = "qcom,geni-spi";
1018                                 reg = <0 0x00894000 0 0x4000>;
1019                                 clock-names = "se";
1020                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1021                                 pinctrl-names = "default";
1022                                 pinctrl-0 = <&qup_spi5_default>;
1023                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1024                                 #address-cells = <1>;
1025                                 #size-cells = <0>;
1026                                 status = "disabled";
1027                         };
1028
1029                         uart5: serial@894000 {
1030                                 compatible = "qcom,geni-uart";
1031                                 reg = <0 0x00894000 0 0x4000>;
1032                                 clock-names = "se";
1033                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1034                                 pinctrl-names = "default";
1035                                 pinctrl-0 = <&qup_uart5_default>;
1036                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1037                                 status = "disabled";
1038                         };
1039
1040                         i2c6: i2c@898000 {
1041                                 compatible = "qcom,geni-i2c";
1042                                 reg = <0 0x00898000 0 0x4000>;
1043                                 clock-names = "se";
1044                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1045                                 pinctrl-names = "default";
1046                                 pinctrl-0 = <&qup_i2c6_default>;
1047                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1048                                 #address-cells = <1>;
1049                                 #size-cells = <0>;
1050                                 status = "disabled";
1051                         };
1052
1053                         spi6: spi@898000 {
1054                                 compatible = "qcom,geni-spi";
1055                                 reg = <0 0x00898000 0 0x4000>;
1056                                 clock-names = "se";
1057                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1058                                 pinctrl-names = "default";
1059                                 pinctrl-0 = <&qup_spi6_default>;
1060                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1061                                 #address-cells = <1>;
1062                                 #size-cells = <0>;
1063                                 status = "disabled";
1064                         };
1065
1066                         uart6: serial@898000 {
1067                                 compatible = "qcom,geni-uart";
1068                                 reg = <0 0x00898000 0 0x4000>;
1069                                 clock-names = "se";
1070                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1071                                 pinctrl-names = "default";
1072                                 pinctrl-0 = <&qup_uart6_default>;
1073                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1074                                 status = "disabled";
1075                         };
1076
1077                         i2c7: i2c@89c000 {
1078                                 compatible = "qcom,geni-i2c";
1079                                 reg = <0 0x0089c000 0 0x4000>;
1080                                 clock-names = "se";
1081                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1082                                 pinctrl-names = "default";
1083                                 pinctrl-0 = <&qup_i2c7_default>;
1084                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1085                                 #address-cells = <1>;
1086                                 #size-cells = <0>;
1087                                 status = "disabled";
1088                         };
1089
1090                         spi7: spi@89c000 {
1091                                 compatible = "qcom,geni-spi";
1092                                 reg = <0 0x0089c000 0 0x4000>;
1093                                 clock-names = "se";
1094                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1095                                 pinctrl-names = "default";
1096                                 pinctrl-0 = <&qup_spi7_default>;
1097                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1098                                 #address-cells = <1>;
1099                                 #size-cells = <0>;
1100                                 status = "disabled";
1101                         };
1102
1103                         uart7: serial@89c000 {
1104                                 compatible = "qcom,geni-uart";
1105                                 reg = <0 0x0089c000 0 0x4000>;
1106                                 clock-names = "se";
1107                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1108                                 pinctrl-names = "default";
1109                                 pinctrl-0 = <&qup_uart7_default>;
1110                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1111                                 status = "disabled";
1112                         };
1113                 };
1114
1115                 qupv3_id_1: geniqup@ac0000 {
1116                         compatible = "qcom,geni-se-qup";
1117                         reg = <0 0x00ac0000 0 0x6000>;
1118                         clock-names = "m-ahb", "s-ahb";
1119                         clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1120                                  <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1121                         #address-cells = <2>;
1122                         #size-cells = <2>;
1123                         ranges;
1124                         status = "disabled";
1125
1126                         i2c8: i2c@a80000 {
1127                                 compatible = "qcom,geni-i2c";
1128                                 reg = <0 0x00a80000 0 0x4000>;
1129                                 clock-names = "se";
1130                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1131                                 pinctrl-names = "default";
1132                                 pinctrl-0 = <&qup_i2c8_default>;
1133                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1134                                 #address-cells = <1>;
1135                                 #size-cells = <0>;
1136                                 status = "disabled";
1137                         };
1138
1139                         spi8: spi@a80000 {
1140                                 compatible = "qcom,geni-spi";
1141                                 reg = <0 0x00a80000 0 0x4000>;
1142                                 clock-names = "se";
1143                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1144                                 pinctrl-names = "default";
1145                                 pinctrl-0 = <&qup_spi8_default>;
1146                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1147                                 #address-cells = <1>;
1148                                 #size-cells = <0>;
1149                                 status = "disabled";
1150                         };
1151
1152                         uart8: serial@a80000 {
1153                                 compatible = "qcom,geni-uart";
1154                                 reg = <0 0x00a80000 0 0x4000>;
1155                                 clock-names = "se";
1156                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1157                                 pinctrl-names = "default";
1158                                 pinctrl-0 = <&qup_uart8_default>;
1159                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1160                                 status = "disabled";
1161                         };
1162
1163                         i2c9: i2c@a84000 {
1164                                 compatible = "qcom,geni-i2c";
1165                                 reg = <0 0x00a84000 0 0x4000>;
1166                                 clock-names = "se";
1167                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1168                                 pinctrl-names = "default";
1169                                 pinctrl-0 = <&qup_i2c9_default>;
1170                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1171                                 #address-cells = <1>;
1172                                 #size-cells = <0>;
1173                                 status = "disabled";
1174                         };
1175
1176                         spi9: spi@a84000 {
1177                                 compatible = "qcom,geni-spi";
1178                                 reg = <0 0x00a84000 0 0x4000>;
1179                                 clock-names = "se";
1180                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1181                                 pinctrl-names = "default";
1182                                 pinctrl-0 = <&qup_spi9_default>;
1183                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1184                                 #address-cells = <1>;
1185                                 #size-cells = <0>;
1186                                 status = "disabled";
1187                         };
1188
1189                         uart9: serial@a84000 {
1190                                 compatible = "qcom,geni-debug-uart";
1191                                 reg = <0 0x00a84000 0 0x4000>;
1192                                 clock-names = "se";
1193                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1194                                 pinctrl-names = "default";
1195                                 pinctrl-0 = <&qup_uart9_default>;
1196                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1197                                 status = "disabled";
1198                         };
1199
1200                         i2c10: i2c@a88000 {
1201                                 compatible = "qcom,geni-i2c";
1202                                 reg = <0 0x00a88000 0 0x4000>;
1203                                 clock-names = "se";
1204                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1205                                 pinctrl-names = "default";
1206                                 pinctrl-0 = <&qup_i2c10_default>;
1207                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1208                                 #address-cells = <1>;
1209                                 #size-cells = <0>;
1210                                 status = "disabled";
1211                         };
1212
1213                         spi10: spi@a88000 {
1214                                 compatible = "qcom,geni-spi";
1215                                 reg = <0 0x00a88000 0 0x4000>;
1216                                 clock-names = "se";
1217                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1218                                 pinctrl-names = "default";
1219                                 pinctrl-0 = <&qup_spi10_default>;
1220                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1221                                 #address-cells = <1>;
1222                                 #size-cells = <0>;
1223                                 status = "disabled";
1224                         };
1225
1226                         uart10: serial@a88000 {
1227                                 compatible = "qcom,geni-uart";
1228                                 reg = <0 0x00a88000 0 0x4000>;
1229                                 clock-names = "se";
1230                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1231                                 pinctrl-names = "default";
1232                                 pinctrl-0 = <&qup_uart10_default>;
1233                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1234                                 status = "disabled";
1235                         };
1236
1237                         i2c11: i2c@a8c000 {
1238                                 compatible = "qcom,geni-i2c";
1239                                 reg = <0 0x00a8c000 0 0x4000>;
1240                                 clock-names = "se";
1241                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1242                                 pinctrl-names = "default";
1243                                 pinctrl-0 = <&qup_i2c11_default>;
1244                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1245                                 #address-cells = <1>;
1246                                 #size-cells = <0>;
1247                                 status = "disabled";
1248                         };
1249
1250                         spi11: spi@a8c000 {
1251                                 compatible = "qcom,geni-spi";
1252                                 reg = <0 0x00a8c000 0 0x4000>;
1253                                 clock-names = "se";
1254                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1255                                 pinctrl-names = "default";
1256                                 pinctrl-0 = <&qup_spi11_default>;
1257                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1258                                 #address-cells = <1>;
1259                                 #size-cells = <0>;
1260                                 status = "disabled";
1261                         };
1262
1263                         uart11: serial@a8c000 {
1264                                 compatible = "qcom,geni-uart";
1265                                 reg = <0 0x00a8c000 0 0x4000>;
1266                                 clock-names = "se";
1267                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1268                                 pinctrl-names = "default";
1269                                 pinctrl-0 = <&qup_uart11_default>;
1270                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1271                                 status = "disabled";
1272                         };
1273
1274                         i2c12: i2c@a90000 {
1275                                 compatible = "qcom,geni-i2c";
1276                                 reg = <0 0x00a90000 0 0x4000>;
1277                                 clock-names = "se";
1278                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1279                                 pinctrl-names = "default";
1280                                 pinctrl-0 = <&qup_i2c12_default>;
1281                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1282                                 #address-cells = <1>;
1283                                 #size-cells = <0>;
1284                                 status = "disabled";
1285                         };
1286
1287                         spi12: spi@a90000 {
1288                                 compatible = "qcom,geni-spi";
1289                                 reg = <0 0x00a90000 0 0x4000>;
1290                                 clock-names = "se";
1291                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1292                                 pinctrl-names = "default";
1293                                 pinctrl-0 = <&qup_spi12_default>;
1294                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1295                                 #address-cells = <1>;
1296                                 #size-cells = <0>;
1297                                 status = "disabled";
1298                         };
1299
1300                         uart12: serial@a90000 {
1301                                 compatible = "qcom,geni-uart";
1302                                 reg = <0 0x00a90000 0 0x4000>;
1303                                 clock-names = "se";
1304                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1305                                 pinctrl-names = "default";
1306                                 pinctrl-0 = <&qup_uart12_default>;
1307                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1308                                 status = "disabled";
1309                         };
1310
1311                         i2c13: i2c@a94000 {
1312                                 compatible = "qcom,geni-i2c";
1313                                 reg = <0 0x00a94000 0 0x4000>;
1314                                 clock-names = "se";
1315                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1316                                 pinctrl-names = "default";
1317                                 pinctrl-0 = <&qup_i2c13_default>;
1318                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1319                                 #address-cells = <1>;
1320                                 #size-cells = <0>;
1321                                 status = "disabled";
1322                         };
1323
1324                         spi13: spi@a94000 {
1325                                 compatible = "qcom,geni-spi";
1326                                 reg = <0 0x00a94000 0 0x4000>;
1327                                 clock-names = "se";
1328                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1329                                 pinctrl-names = "default";
1330                                 pinctrl-0 = <&qup_spi13_default>;
1331                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1332                                 #address-cells = <1>;
1333                                 #size-cells = <0>;
1334                                 status = "disabled";
1335                         };
1336
1337                         uart13: serial@a94000 {
1338                                 compatible = "qcom,geni-uart";
1339                                 reg = <0 0x00a94000 0 0x4000>;
1340                                 clock-names = "se";
1341                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1342                                 pinctrl-names = "default";
1343                                 pinctrl-0 = <&qup_uart13_default>;
1344                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1345                                 status = "disabled";
1346                         };
1347
1348                         i2c14: i2c@a98000 {
1349                                 compatible = "qcom,geni-i2c";
1350                                 reg = <0 0x00a98000 0 0x4000>;
1351                                 clock-names = "se";
1352                                 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1353                                 pinctrl-names = "default";
1354                                 pinctrl-0 = <&qup_i2c14_default>;
1355                                 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1356                                 #address-cells = <1>;
1357                                 #size-cells = <0>;
1358                                 status = "disabled";
1359                         };
1360
1361                         spi14: spi@a98000 {
1362                                 compatible = "qcom,geni-spi";
1363                                 reg = <0 0x00a98000 0 0x4000>;
1364                                 clock-names = "se";
1365                                 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1366                                 pinctrl-names = "default";
1367                                 pinctrl-0 = <&qup_spi14_default>;
1368                                 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1369                                 #address-cells = <1>;
1370                                 #size-cells = <0>;
1371                                 status = "disabled";
1372                         };
1373
1374                         uart14: serial@a98000 {
1375                                 compatible = "qcom,geni-uart";
1376                                 reg = <0 0x00a98000 0 0x4000>;
1377                                 clock-names = "se";
1378                                 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1379                                 pinctrl-names = "default";
1380                                 pinctrl-0 = <&qup_uart14_default>;
1381                                 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1382                                 status = "disabled";
1383                         };
1384
1385                         i2c15: i2c@a9c000 {
1386                                 compatible = "qcom,geni-i2c";
1387                                 reg = <0 0x00a9c000 0 0x4000>;
1388                                 clock-names = "se";
1389                                 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
1390                                 pinctrl-names = "default";
1391                                 pinctrl-0 = <&qup_i2c15_default>;
1392                                 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1393                                 #address-cells = <1>;
1394                                 #size-cells = <0>;
1395                                 status = "disabled";
1396                         };
1397
1398                         spi15: spi@a9c000 {
1399                                 compatible = "qcom,geni-spi";
1400                                 reg = <0 0x00a9c000 0 0x4000>;
1401                                 clock-names = "se";
1402                                 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
1403                                 pinctrl-names = "default";
1404                                 pinctrl-0 = <&qup_spi15_default>;
1405                                 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1406                                 #address-cells = <1>;
1407                                 #size-cells = <0>;
1408                                 status = "disabled";
1409                         };
1410
1411                         uart15: serial@a9c000 {
1412                                 compatible = "qcom,geni-uart";
1413                                 reg = <0 0x00a9c000 0 0x4000>;
1414                                 clock-names = "se";
1415                                 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
1416                                 pinctrl-names = "default";
1417                                 pinctrl-0 = <&qup_uart15_default>;
1418                                 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1419                                 status = "disabled";
1420                         };
1421                 };
1422
1423                 system-cache-controller@1100000 {
1424                         compatible = "qcom,sdm845-llcc";
1425                         reg = <0 0x01100000 0 0x200000>, <0 0x01300000 0 0x50000>;
1426                         reg-names = "llcc_base", "llcc_broadcast_base";
1427                         interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
1428                 };
1429
1430                 pcie0: pci@1c00000 {
1431                         compatible = "qcom,pcie-sdm845", "snps,dw-pcie";
1432                         reg = <0 0x01c00000 0 0x2000>,
1433                               <0 0x60000000 0 0xf1d>,
1434                               <0 0x60000f20 0 0xa8>,
1435                               <0 0x60100000 0 0x100000>;
1436                         reg-names = "parf", "dbi", "elbi", "config";
1437                         device_type = "pci";
1438                         linux,pci-domain = <0>;
1439                         bus-range = <0x00 0xff>;
1440                         num-lanes = <1>;
1441
1442                         #address-cells = <3>;
1443                         #size-cells = <2>;
1444
1445                         ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>,
1446                                  <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0xd00000>;
1447
1448                         interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
1449                         interrupt-names = "msi";
1450                         #interrupt-cells = <1>;
1451                         interrupt-map-mask = <0 0 0 0x7>;
1452                         interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1453                                         <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1454                                         <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1455                                         <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1456
1457                         clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
1458                                  <&gcc GCC_PCIE_0_AUX_CLK>,
1459                                  <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1460                                  <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1461                                  <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
1462                                  <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
1463                                  <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
1464                         clock-names = "pipe",
1465                                       "aux",
1466                                       "cfg",
1467                                       "bus_master",
1468                                       "bus_slave",
1469                                       "slave_q2a",
1470                                       "tbu";
1471
1472                         iommus = <&apps_smmu 0x1c10 0xf>;
1473                         iommu-map = <0x0   &apps_smmu 0x1c10 0x1>,
1474                                     <0x100 &apps_smmu 0x1c11 0x1>,
1475                                     <0x200 &apps_smmu 0x1c12 0x1>,
1476                                     <0x300 &apps_smmu 0x1c13 0x1>,
1477                                     <0x400 &apps_smmu 0x1c14 0x1>,
1478                                     <0x500 &apps_smmu 0x1c15 0x1>,
1479                                     <0x600 &apps_smmu 0x1c16 0x1>,
1480                                     <0x700 &apps_smmu 0x1c17 0x1>,
1481                                     <0x800 &apps_smmu 0x1c18 0x1>,
1482                                     <0x900 &apps_smmu 0x1c19 0x1>,
1483                                     <0xa00 &apps_smmu 0x1c1a 0x1>,
1484                                     <0xb00 &apps_smmu 0x1c1b 0x1>,
1485                                     <0xc00 &apps_smmu 0x1c1c 0x1>,
1486                                     <0xd00 &apps_smmu 0x1c1d 0x1>,
1487                                     <0xe00 &apps_smmu 0x1c1e 0x1>,
1488                                     <0xf00 &apps_smmu 0x1c1f 0x1>;
1489
1490                         resets = <&gcc GCC_PCIE_0_BCR>;
1491                         reset-names = "pci";
1492
1493                         power-domains = <&gcc PCIE_0_GDSC>;
1494
1495                         phys = <&pcie0_lane>;
1496                         phy-names = "pciephy";
1497
1498                         status = "disabled";
1499                 };
1500
1501                 pcie0_phy: phy@1c06000 {
1502                         compatible = "qcom,sdm845-qmp-pcie-phy";
1503                         reg = <0 0x01c06000 0 0x18c>;
1504                         #address-cells = <2>;
1505                         #size-cells = <2>;
1506                         ranges;
1507                         clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
1508                                  <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1509                                  <&gcc GCC_PCIE_0_CLKREF_CLK>,
1510                                  <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
1511                         clock-names = "aux", "cfg_ahb", "ref", "refgen";
1512
1513                         resets = <&gcc GCC_PCIE_0_PHY_BCR>;
1514                         reset-names = "phy";
1515
1516                         assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
1517                         assigned-clock-rates = <100000000>;
1518
1519                         status = "disabled";
1520
1521                         pcie0_lane: lanes@1c06200 {
1522                                 reg = <0 0x01c06200 0 0x128>,
1523                                       <0 0x01c06400 0 0x1fc>,
1524                                       <0 0x01c06800 0 0x218>,
1525                                       <0 0x01c06600 0 0x70>;
1526                                 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
1527                                 clock-names = "pipe0";
1528
1529                                 #phy-cells = <0>;
1530                                 clock-output-names = "pcie_0_pipe_clk";
1531                         };
1532                 };
1533
1534                 pcie1: pci@1c08000 {
1535                         compatible = "qcom,pcie-sdm845", "snps,dw-pcie";
1536                         reg = <0 0x01c08000 0 0x2000>,
1537                               <0 0x40000000 0 0xf1d>,
1538                               <0 0x40000f20 0 0xa8>,
1539                               <0 0x40100000 0 0x100000>;
1540                         reg-names = "parf", "dbi", "elbi", "config";
1541                         device_type = "pci";
1542                         linux,pci-domain = <1>;
1543                         bus-range = <0x00 0xff>;
1544                         num-lanes = <1>;
1545
1546                         #address-cells = <3>;
1547                         #size-cells = <2>;
1548
1549                         ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
1550                                  <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
1551
1552                         interrupts = <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>;
1553                         interrupt-names = "msi";
1554                         #interrupt-cells = <1>;
1555                         interrupt-map-mask = <0 0 0 0x7>;
1556                         interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1557                                         <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1558                                         <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1559                                         <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1560
1561                         clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
1562                                  <&gcc GCC_PCIE_1_AUX_CLK>,
1563                                  <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1564                                  <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1565                                  <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
1566                                  <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
1567                                  <&gcc GCC_PCIE_1_CLKREF_CLK>,
1568                                  <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
1569                         clock-names = "pipe",
1570                                       "aux",
1571                                       "cfg",
1572                                       "bus_master",
1573                                       "bus_slave",
1574                                       "slave_q2a",
1575                                       "ref",
1576                                       "tbu";
1577
1578                         assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
1579                         assigned-clock-rates = <19200000>;
1580
1581                         iommus = <&apps_smmu 0x1c00 0xf>;
1582                         iommu-map = <0x0   &apps_smmu 0x1c00 0x1>,
1583                                     <0x100 &apps_smmu 0x1c01 0x1>,
1584                                     <0x200 &apps_smmu 0x1c02 0x1>,
1585                                     <0x300 &apps_smmu 0x1c03 0x1>,
1586                                     <0x400 &apps_smmu 0x1c04 0x1>,
1587                                     <0x500 &apps_smmu 0x1c05 0x1>,
1588                                     <0x600 &apps_smmu 0x1c06 0x1>,
1589                                     <0x700 &apps_smmu 0x1c07 0x1>,
1590                                     <0x800 &apps_smmu 0x1c08 0x1>,
1591                                     <0x900 &apps_smmu 0x1c09 0x1>,
1592                                     <0xa00 &apps_smmu 0x1c0a 0x1>,
1593                                     <0xb00 &apps_smmu 0x1c0b 0x1>,
1594                                     <0xc00 &apps_smmu 0x1c0c 0x1>,
1595                                     <0xd00 &apps_smmu 0x1c0d 0x1>,
1596                                     <0xe00 &apps_smmu 0x1c0e 0x1>,
1597                                     <0xf00 &apps_smmu 0x1c0f 0x1>;
1598
1599                         resets = <&gcc GCC_PCIE_1_BCR>;
1600                         reset-names = "pci";
1601
1602                         power-domains = <&gcc PCIE_1_GDSC>;
1603
1604                         phys = <&pcie1_lane>;
1605                         phy-names = "pciephy";
1606
1607                         status = "disabled";
1608                 };
1609
1610                 pcie1_phy: phy@1c0a000 {
1611                         compatible = "qcom,sdm845-qhp-pcie-phy";
1612                         reg = <0 0x01c0a000 0 0x800>;
1613                         #address-cells = <2>;
1614                         #size-cells = <2>;
1615                         ranges;
1616                         clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
1617                                  <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1618                                  <&gcc GCC_PCIE_1_CLKREF_CLK>,
1619                                  <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
1620                         clock-names = "aux", "cfg_ahb", "ref", "refgen";
1621
1622                         resets = <&gcc GCC_PCIE_1_PHY_BCR>;
1623                         reset-names = "phy";
1624
1625                         assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
1626                         assigned-clock-rates = <100000000>;
1627
1628                         status = "disabled";
1629
1630                         pcie1_lane: lanes@1c06200 {
1631                                 reg = <0 0x01c0a800 0 0x800>,
1632                                       <0 0x01c0a800 0 0x800>,
1633                                       <0 0x01c0b800 0 0x400>;
1634                                 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
1635                                 clock-names = "pipe0";
1636
1637                                 #phy-cells = <0>;
1638                                 clock-output-names = "pcie_1_pipe_clk";
1639                         };
1640                 };
1641
1642                 mem_noc: interconnect@1380000 {
1643                         compatible = "qcom,sdm845-mem-noc";
1644                         reg = <0 0x01380000 0 0x27200>;
1645                         #interconnect-cells = <1>;
1646                         qcom,bcm-voters = <&apps_bcm_voter>;
1647                 };
1648
1649                 dc_noc: interconnect@14e0000 {
1650                         compatible = "qcom,sdm845-dc-noc";
1651                         reg = <0 0x014e0000 0 0x400>;
1652                         #interconnect-cells = <1>;
1653                         qcom,bcm-voters = <&apps_bcm_voter>;
1654                 };
1655
1656                 config_noc: interconnect@1500000 {
1657                         compatible = "qcom,sdm845-config-noc";
1658                         reg = <0 0x01500000 0 0x5080>;
1659                         #interconnect-cells = <1>;
1660                         qcom,bcm-voters = <&apps_bcm_voter>;
1661                 };
1662
1663                 system_noc: interconnect@1620000 {
1664                         compatible = "qcom,sdm845-system-noc";
1665                         reg = <0 0x01620000 0 0x18080>;
1666                         #interconnect-cells = <1>;
1667                         qcom,bcm-voters = <&apps_bcm_voter>;
1668                 };
1669
1670                 aggre1_noc: interconnect@16e0000 {
1671                         compatible = "qcom,sdm845-aggre1-noc";
1672                         reg = <0 0x016e0000 0 0x15080>;
1673                         #interconnect-cells = <1>;
1674                         qcom,bcm-voters = <&apps_bcm_voter>;
1675                 };
1676
1677                 aggre2_noc: interconnect@1700000 {
1678                         compatible = "qcom,sdm845-aggre2-noc";
1679                         reg = <0 0x01700000 0 0x1f300>;
1680                         #interconnect-cells = <1>;
1681                         qcom,bcm-voters = <&apps_bcm_voter>;
1682                 };
1683
1684                 mmss_noc: interconnect@1740000 {
1685                         compatible = "qcom,sdm845-mmss-noc";
1686                         reg = <0 0x01740000 0 0x1c100>;
1687                         #interconnect-cells = <1>;
1688                         qcom,bcm-voters = <&apps_bcm_voter>;
1689                 };
1690
1691                 ufs_mem_hc: ufshc@1d84000 {
1692                         compatible = "qcom,sdm845-ufshc", "qcom,ufshc",
1693                                      "jedec,ufs-2.0";
1694                         reg = <0 0x01d84000 0 0x2500>;
1695                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
1696                         phys = <&ufs_mem_phy_lanes>;
1697                         phy-names = "ufsphy";
1698                         lanes-per-direction = <2>;
1699                         power-domains = <&gcc UFS_PHY_GDSC>;
1700                         #reset-cells = <1>;
1701                         resets = <&gcc GCC_UFS_PHY_BCR>;
1702                         reset-names = "rst";
1703
1704                         iommus = <&apps_smmu 0x100 0xf>;
1705
1706                         clock-names =
1707                                 "core_clk",
1708                                 "bus_aggr_clk",
1709                                 "iface_clk",
1710                                 "core_clk_unipro",
1711                                 "ref_clk",
1712                                 "tx_lane0_sync_clk",
1713                                 "rx_lane0_sync_clk",
1714                                 "rx_lane1_sync_clk";
1715                         clocks =
1716                                 <&gcc GCC_UFS_PHY_AXI_CLK>,
1717                                 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
1718                                 <&gcc GCC_UFS_PHY_AHB_CLK>,
1719                                 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
1720                                 <&rpmhcc RPMH_CXO_CLK>,
1721                                 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
1722                                 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
1723                                 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
1724                         freq-table-hz =
1725                                 <50000000 200000000>,
1726                                 <0 0>,
1727                                 <0 0>,
1728                                 <37500000 150000000>,
1729                                 <0 0>,
1730                                 <0 0>,
1731                                 <0 0>,
1732                                 <0 0>;
1733
1734                         status = "disabled";
1735                 };
1736
1737                 ufs_mem_phy: phy@1d87000 {
1738                         compatible = "qcom,sdm845-qmp-ufs-phy";
1739                         reg = <0 0x01d87000 0 0x18c>;
1740                         #address-cells = <2>;
1741                         #size-cells = <2>;
1742                         ranges;
1743                         clock-names = "ref",
1744                                       "ref_aux";
1745                         clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
1746                                  <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
1747
1748                         resets = <&ufs_mem_hc 0>;
1749                         reset-names = "ufsphy";
1750                         status = "disabled";
1751
1752                         ufs_mem_phy_lanes: lanes@1d87400 {
1753                                 reg = <0 0x01d87400 0 0x108>,
1754                                       <0 0x01d87600 0 0x1e0>,
1755                                       <0 0x01d87c00 0 0x1dc>,
1756                                       <0 0x01d87800 0 0x108>,
1757                                       <0 0x01d87a00 0 0x1e0>;
1758                                 #phy-cells = <0>;
1759                         };
1760                 };
1761
1762                 ipa: ipa@1e40000 {
1763                         compatible = "qcom,sdm845-ipa";
1764                         reg = <0 0x1e40000 0 0x7000>,
1765                               <0 0x1e47000 0 0x2000>,
1766                               <0 0x1e04000 0 0x2c000>;
1767                         reg-names = "ipa-reg",
1768                                     "ipa-shared",
1769                                     "gsi";
1770
1771                         interrupts-extended = <&intc 0 311 IRQ_TYPE_EDGE_RISING>,
1772                                               <&intc 0 432 IRQ_TYPE_LEVEL_HIGH>,
1773                                               <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1774                                               <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
1775                         interrupt-names = "ipa",
1776                                           "gsi",
1777                                           "ipa-clock-query",
1778                                           "ipa-setup-ready";
1779
1780                         clocks = <&rpmhcc RPMH_IPA_CLK>;
1781                         clock-names = "core";
1782
1783                         interconnects = <&aggre2_noc MASTER_IPA &mem_noc SLAVE_EBI1>,
1784                                         <&aggre2_noc MASTER_IPA &system_noc SLAVE_IMEM>,
1785                                         <&gladiator_noc MASTER_APPSS_PROC &config_noc SLAVE_IPA_CFG>;
1786                         interconnect-names = "memory",
1787                                              "imem",
1788                                              "config";
1789
1790                         qcom,smem-states = <&ipa_smp2p_out 0>,
1791                                            <&ipa_smp2p_out 1>;
1792                         qcom,smem-state-names = "ipa-clock-enabled-valid",
1793                                                 "ipa-clock-enabled";
1794
1795                         modem-remoteproc = <&mss_pil>;
1796
1797                         status = "disabled";
1798                 };
1799
1800                 tcsr_mutex_regs: syscon@1f40000 {
1801                         compatible = "syscon";
1802                         reg = <0 0x01f40000 0 0x40000>;
1803                 };
1804
1805                 tlmm: pinctrl@3400000 {
1806                         compatible = "qcom,sdm845-pinctrl";
1807                         reg = <0 0x03400000 0 0xc00000>;
1808                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1809                         gpio-controller;
1810                         #gpio-cells = <2>;
1811                         interrupt-controller;
1812                         #interrupt-cells = <2>;
1813                         gpio-ranges = <&tlmm 0 0 150>;
1814                         wakeup-parent = <&pdc_intc>;
1815
1816                         qspi_clk: qspi-clk {
1817                                 pinmux {
1818                                         pins = "gpio95";
1819                                         function = "qspi_clk";
1820                                 };
1821                         };
1822
1823                         qspi_cs0: qspi-cs0 {
1824                                 pinmux {
1825                                         pins = "gpio90";
1826                                         function = "qspi_cs";
1827                                 };
1828                         };
1829
1830                         qspi_cs1: qspi-cs1 {
1831                                 pinmux {
1832                                         pins = "gpio89";
1833                                         function = "qspi_cs";
1834                                 };
1835                         };
1836
1837                         qspi_data01: qspi-data01 {
1838                                 pinmux-data {
1839                                         pins = "gpio91", "gpio92";
1840                                         function = "qspi_data";
1841                                 };
1842                         };
1843
1844                         qspi_data12: qspi-data12 {
1845                                 pinmux-data {
1846                                         pins = "gpio93", "gpio94";
1847                                         function = "qspi_data";
1848                                 };
1849                         };
1850
1851                         qup_i2c0_default: qup-i2c0-default {
1852                                 pinmux {
1853                                         pins = "gpio0", "gpio1";
1854                                         function = "qup0";
1855                                 };
1856                         };
1857
1858                         qup_i2c1_default: qup-i2c1-default {
1859                                 pinmux {
1860                                         pins = "gpio17", "gpio18";
1861                                         function = "qup1";
1862                                 };
1863                         };
1864
1865                         qup_i2c2_default: qup-i2c2-default {
1866                                 pinmux {
1867                                         pins = "gpio27", "gpio28";
1868                                         function = "qup2";
1869                                 };
1870                         };
1871
1872                         qup_i2c3_default: qup-i2c3-default {
1873                                 pinmux {
1874                                         pins = "gpio41", "gpio42";
1875                                         function = "qup3";
1876                                 };
1877                         };
1878
1879                         qup_i2c4_default: qup-i2c4-default {
1880                                 pinmux {
1881                                         pins = "gpio89", "gpio90";
1882                                         function = "qup4";
1883                                 };
1884                         };
1885
1886                         qup_i2c5_default: qup-i2c5-default {
1887                                 pinmux {
1888                                         pins = "gpio85", "gpio86";
1889                                         function = "qup5";
1890                                 };
1891                         };
1892
1893                         qup_i2c6_default: qup-i2c6-default {
1894                                 pinmux {
1895                                         pins = "gpio45", "gpio46";
1896                                         function = "qup6";
1897                                 };
1898                         };
1899
1900                         qup_i2c7_default: qup-i2c7-default {
1901                                 pinmux {
1902                                         pins = "gpio93", "gpio94";
1903                                         function = "qup7";
1904                                 };
1905                         };
1906
1907                         qup_i2c8_default: qup-i2c8-default {
1908                                 pinmux {
1909                                         pins = "gpio65", "gpio66";
1910                                         function = "qup8";
1911                                 };
1912                         };
1913
1914                         qup_i2c9_default: qup-i2c9-default {
1915                                 pinmux {
1916                                         pins = "gpio6", "gpio7";
1917                                         function = "qup9";
1918                                 };
1919                         };
1920
1921                         qup_i2c10_default: qup-i2c10-default {
1922                                 pinmux {
1923                                         pins = "gpio55", "gpio56";
1924                                         function = "qup10";
1925                                 };
1926                         };
1927
1928                         qup_i2c11_default: qup-i2c11-default {
1929                                 pinmux {
1930                                         pins = "gpio31", "gpio32";
1931                                         function = "qup11";
1932                                 };
1933                         };
1934
1935                         qup_i2c12_default: qup-i2c12-default {
1936                                 pinmux {
1937                                         pins = "gpio49", "gpio50";
1938                                         function = "qup12";
1939                                 };
1940                         };
1941
1942                         qup_i2c13_default: qup-i2c13-default {
1943                                 pinmux {
1944                                         pins = "gpio105", "gpio106";
1945                                         function = "qup13";
1946                                 };
1947                         };
1948
1949                         qup_i2c14_default: qup-i2c14-default {
1950                                 pinmux {
1951                                         pins = "gpio33", "gpio34";
1952                                         function = "qup14";
1953                                 };
1954                         };
1955
1956                         qup_i2c15_default: qup-i2c15-default {
1957                                 pinmux {
1958                                         pins = "gpio81", "gpio82";
1959                                         function = "qup15";
1960                                 };
1961                         };
1962
1963                         qup_spi0_default: qup-spi0-default {
1964                                 pinmux {
1965                                         pins = "gpio0", "gpio1",
1966                                                "gpio2", "gpio3";
1967                                         function = "qup0";
1968                                 };
1969                         };
1970
1971                         qup_spi1_default: qup-spi1-default {
1972                                 pinmux {
1973                                         pins = "gpio17", "gpio18",
1974                                                "gpio19", "gpio20";
1975                                         function = "qup1";
1976                                 };
1977                         };
1978
1979                         qup_spi2_default: qup-spi2-default {
1980                                 pinmux {
1981                                         pins = "gpio27", "gpio28",
1982                                                "gpio29", "gpio30";
1983                                         function = "qup2";
1984                                 };
1985                         };
1986
1987                         qup_spi3_default: qup-spi3-default {
1988                                 pinmux {
1989                                         pins = "gpio41", "gpio42",
1990                                                "gpio43", "gpio44";
1991                                         function = "qup3";
1992                                 };
1993                         };
1994
1995                         qup_spi4_default: qup-spi4-default {
1996                                 pinmux {
1997                                         pins = "gpio89", "gpio90",
1998                                                "gpio91", "gpio92";
1999                                         function = "qup4";
2000                                 };
2001                         };
2002
2003                         qup_spi5_default: qup-spi5-default {
2004                                 pinmux {
2005                                         pins = "gpio85", "gpio86",
2006                                                "gpio87", "gpio88";
2007                                         function = "qup5";
2008                                 };
2009                         };
2010
2011                         qup_spi6_default: qup-spi6-default {
2012                                 pinmux {
2013                                         pins = "gpio45", "gpio46",
2014                                                "gpio47", "gpio48";
2015                                         function = "qup6";
2016                                 };
2017                         };
2018
2019                         qup_spi7_default: qup-spi7-default {
2020                                 pinmux {
2021                                         pins = "gpio93", "gpio94",
2022                                                "gpio95", "gpio96";
2023                                         function = "qup7";
2024                                 };
2025                         };
2026
2027                         qup_spi8_default: qup-spi8-default {
2028                                 pinmux {
2029                                         pins = "gpio65", "gpio66",
2030                                                "gpio67", "gpio68";
2031                                         function = "qup8";
2032                                 };
2033                         };
2034
2035                         qup_spi9_default: qup-spi9-default {
2036                                 pinmux {
2037                                         pins = "gpio6", "gpio7",
2038                                                "gpio4", "gpio5";
2039                                         function = "qup9";
2040                                 };
2041                         };
2042
2043                         qup_spi10_default: qup-spi10-default {
2044                                 pinmux {
2045                                         pins = "gpio55", "gpio56",
2046                                                "gpio53", "gpio54";
2047                                         function = "qup10";
2048                                 };
2049                         };
2050
2051                         qup_spi11_default: qup-spi11-default {
2052                                 pinmux {
2053                                         pins = "gpio31", "gpio32",
2054                                                "gpio33", "gpio34";
2055                                         function = "qup11";
2056                                 };
2057                         };
2058
2059                         qup_spi12_default: qup-spi12-default {
2060                                 pinmux {
2061                                         pins = "gpio49", "gpio50",
2062                                                "gpio51", "gpio52";
2063                                         function = "qup12";
2064                                 };
2065                         };
2066
2067                         qup_spi13_default: qup-spi13-default {
2068                                 pinmux {
2069                                         pins = "gpio105", "gpio106",
2070                                                "gpio107", "gpio108";
2071                                         function = "qup13";
2072                                 };
2073                         };
2074
2075                         qup_spi14_default: qup-spi14-default {
2076                                 pinmux {
2077                                         pins = "gpio33", "gpio34",
2078                                                "gpio31", "gpio32";
2079                                         function = "qup14";
2080                                 };
2081                         };
2082
2083                         qup_spi15_default: qup-spi15-default {
2084                                 pinmux {
2085                                         pins = "gpio81", "gpio82",
2086                                                "gpio83", "gpio84";
2087                                         function = "qup15";
2088                                 };
2089                         };
2090
2091                         qup_uart0_default: qup-uart0-default {
2092                                 pinmux {
2093                                         pins = "gpio2", "gpio3";
2094                                         function = "qup0";
2095                                 };
2096                         };
2097
2098                         qup_uart1_default: qup-uart1-default {
2099                                 pinmux {
2100                                         pins = "gpio19", "gpio20";
2101                                         function = "qup1";
2102                                 };
2103                         };
2104
2105                         qup_uart2_default: qup-uart2-default {
2106                                 pinmux {
2107                                         pins = "gpio29", "gpio30";
2108                                         function = "qup2";
2109                                 };
2110                         };
2111
2112                         qup_uart3_default: qup-uart3-default {
2113                                 pinmux {
2114                                         pins = "gpio43", "gpio44";
2115                                         function = "qup3";
2116                                 };
2117                         };
2118
2119                         qup_uart4_default: qup-uart4-default {
2120                                 pinmux {
2121                                         pins = "gpio91", "gpio92";
2122                                         function = "qup4";
2123                                 };
2124                         };
2125
2126                         qup_uart5_default: qup-uart5-default {
2127                                 pinmux {
2128                                         pins = "gpio87", "gpio88";
2129                                         function = "qup5";
2130                                 };
2131                         };
2132
2133                         qup_uart6_default: qup-uart6-default {
2134                                 pinmux {
2135                                         pins = "gpio47", "gpio48";
2136                                         function = "qup6";
2137                                 };
2138                         };
2139
2140                         qup_uart7_default: qup-uart7-default {
2141                                 pinmux {
2142                                         pins = "gpio95", "gpio96";
2143                                         function = "qup7";
2144                                 };
2145                         };
2146
2147                         qup_uart8_default: qup-uart8-default {
2148                                 pinmux {
2149                                         pins = "gpio67", "gpio68";
2150                                         function = "qup8";
2151                                 };
2152                         };
2153
2154                         qup_uart9_default: qup-uart9-default {
2155                                 pinmux {
2156                                         pins = "gpio4", "gpio5";
2157                                         function = "qup9";
2158                                 };
2159                         };
2160
2161                         qup_uart10_default: qup-uart10-default {
2162                                 pinmux {
2163                                         pins = "gpio53", "gpio54";
2164                                         function = "qup10";
2165                                 };
2166                         };
2167
2168                         qup_uart11_default: qup-uart11-default {
2169                                 pinmux {
2170                                         pins = "gpio33", "gpio34";
2171                                         function = "qup11";
2172                                 };
2173                         };
2174
2175                         qup_uart12_default: qup-uart12-default {
2176                                 pinmux {
2177                                         pins = "gpio51", "gpio52";
2178                                         function = "qup12";
2179                                 };
2180                         };
2181
2182                         qup_uart13_default: qup-uart13-default {
2183                                 pinmux {
2184                                         pins = "gpio107", "gpio108";
2185                                         function = "qup13";
2186                                 };
2187                         };
2188
2189                         qup_uart14_default: qup-uart14-default {
2190                                 pinmux {
2191                                         pins = "gpio31", "gpio32";
2192                                         function = "qup14";
2193                                 };
2194                         };
2195
2196                         qup_uart15_default: qup-uart15-default {
2197                                 pinmux {
2198                                         pins = "gpio83", "gpio84";
2199                                         function = "qup15";
2200                                 };
2201                         };
2202
2203                         quat_mi2s_sleep: quat_mi2s_sleep {
2204                                 mux {
2205                                         pins = "gpio58", "gpio59";
2206                                         function = "gpio";
2207                                 };
2208
2209                                 config {
2210                                         pins = "gpio58", "gpio59";
2211                                         drive-strength = <2>;
2212                                         bias-pull-down;
2213                                         input-enable;
2214                                 };
2215                         };
2216
2217                         quat_mi2s_active: quat_mi2s_active {
2218                                 mux {
2219                                         pins = "gpio58", "gpio59";
2220                                         function = "qua_mi2s";
2221                                 };
2222
2223                                 config {
2224                                         pins = "gpio58", "gpio59";
2225                                         drive-strength = <8>;
2226                                         bias-disable;
2227                                         output-high;
2228                                 };
2229                         };
2230
2231                         quat_mi2s_sd0_sleep: quat_mi2s_sd0_sleep {
2232                                 mux {
2233                                         pins = "gpio60";
2234                                         function = "gpio";
2235                                 };
2236
2237                                 config {
2238                                         pins = "gpio60";
2239                                         drive-strength = <2>;
2240                                         bias-pull-down;
2241                                         input-enable;
2242                                 };
2243                         };
2244
2245                         quat_mi2s_sd0_active: quat_mi2s_sd0_active {
2246                                 mux {
2247                                         pins = "gpio60";
2248                                         function = "qua_mi2s";
2249                                 };
2250
2251                                 config {
2252                                         pins = "gpio60";
2253                                         drive-strength = <8>;
2254                                         bias-disable;
2255                                 };
2256                         };
2257
2258                         quat_mi2s_sd1_sleep: quat_mi2s_sd1_sleep {
2259                                 mux {
2260                                         pins = "gpio61";
2261                                         function = "gpio";
2262                                 };
2263
2264                                 config {
2265                                         pins = "gpio61";
2266                                         drive-strength = <2>;
2267                                         bias-pull-down;
2268                                         input-enable;
2269                                 };
2270                         };
2271
2272                         quat_mi2s_sd1_active: quat_mi2s_sd1_active {
2273                                 mux {
2274                                         pins = "gpio61";
2275                                         function = "qua_mi2s";
2276                                 };
2277
2278                                 config {
2279                                         pins = "gpio61";
2280                                         drive-strength = <8>;
2281                                         bias-disable;
2282                                 };
2283                         };
2284
2285                         quat_mi2s_sd2_sleep: quat_mi2s_sd2_sleep {
2286                                 mux {
2287                                         pins = "gpio62";
2288                                         function = "gpio";
2289                                 };
2290
2291                                 config {
2292                                         pins = "gpio62";
2293                                         drive-strength = <2>;
2294                                         bias-pull-down;
2295                                         input-enable;
2296                                 };
2297                         };
2298
2299                         quat_mi2s_sd2_active: quat_mi2s_sd2_active {
2300                                 mux {
2301                                         pins = "gpio62";
2302                                         function = "qua_mi2s";
2303                                 };
2304
2305                                 config {
2306                                         pins = "gpio62";
2307                                         drive-strength = <8>;
2308                                         bias-disable;
2309                                 };
2310                         };
2311
2312                         quat_mi2s_sd3_sleep: quat_mi2s_sd3_sleep {
2313                                 mux {
2314                                         pins = "gpio63";
2315                                         function = "gpio";
2316                                 };
2317
2318                                 config {
2319                                         pins = "gpio63";
2320                                         drive-strength = <2>;
2321                                         bias-pull-down;
2322                                         input-enable;
2323                                 };
2324                         };
2325
2326                         quat_mi2s_sd3_active: quat_mi2s_sd3_active {
2327                                 mux {
2328                                         pins = "gpio63";
2329                                         function = "qua_mi2s";
2330                                 };
2331
2332                                 config {
2333                                         pins = "gpio63";
2334                                         drive-strength = <8>;
2335                                         bias-disable;
2336                                 };
2337                         };
2338                 };
2339
2340                 mss_pil: remoteproc@4080000 {
2341                         compatible = "qcom,sdm845-mss-pil";
2342                         reg = <0 0x04080000 0 0x408>, <0 0x04180000 0 0x48>;
2343                         reg-names = "qdsp6", "rmb";
2344
2345                         interrupts-extended =
2346                                 <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
2347                                 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2348                                 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2349                                 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2350                                 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
2351                                 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
2352                         interrupt-names = "wdog", "fatal", "ready",
2353                                           "handover", "stop-ack",
2354                                           "shutdown-ack";
2355
2356                         clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
2357                                  <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>,
2358                                  <&gcc GCC_BOOT_ROM_AHB_CLK>,
2359                                  <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>,
2360                                  <&gcc GCC_MSS_SNOC_AXI_CLK>,
2361                                  <&gcc GCC_MSS_MFAB_AXIS_CLK>,
2362                                  <&gcc GCC_PRNG_AHB_CLK>,
2363                                  <&rpmhcc RPMH_CXO_CLK>;
2364                         clock-names = "iface", "bus", "mem", "gpll0_mss",
2365                                       "snoc_axi", "mnoc_axi", "prng", "xo";
2366
2367                         qcom,smem-states = <&modem_smp2p_out 0>;
2368                         qcom,smem-state-names = "stop";
2369
2370                         resets = <&aoss_reset AOSS_CC_MSS_RESTART>,
2371                                  <&pdc_reset PDC_MODEM_SYNC_RESET>;
2372                         reset-names = "mss_restart", "pdc_reset";
2373
2374                         qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>;
2375
2376                         power-domains = <&aoss_qmp 2>,
2377                                         <&rpmhpd SDM845_CX>,
2378                                         <&rpmhpd SDM845_MX>,
2379                                         <&rpmhpd SDM845_MSS>;
2380                         power-domain-names = "load_state", "cx", "mx", "mss";
2381
2382                         mba {
2383                                 memory-region = <&mba_region>;
2384                         };
2385
2386                         mpss {
2387                                 memory-region = <&mpss_region>;
2388                         };
2389
2390                         glink-edge {
2391                                 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
2392                                 label = "modem";
2393                                 qcom,remote-pid = <1>;
2394                                 mboxes = <&apss_shared 12>;
2395                         };
2396                 };
2397
2398                 gpucc: clock-controller@5090000 {
2399                         compatible = "qcom,sdm845-gpucc";
2400                         reg = <0 0x05090000 0 0x9000>;
2401                         #clock-cells = <1>;
2402                         #reset-cells = <1>;
2403                         #power-domain-cells = <1>;
2404                         clocks = <&rpmhcc RPMH_CXO_CLK>,
2405                                  <&gcc GCC_GPU_GPLL0_CLK_SRC>,
2406                                  <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
2407                         clock-names = "bi_tcxo",
2408                                       "gcc_gpu_gpll0_clk_src",
2409                                       "gcc_gpu_gpll0_div_clk_src";
2410                 };
2411
2412                 stm@6002000 {
2413                         compatible = "arm,coresight-stm", "arm,primecell";
2414                         reg = <0 0x06002000 0 0x1000>,
2415                               <0 0x16280000 0 0x180000>;
2416                         reg-names = "stm-base", "stm-stimulus-base";
2417
2418                         clocks = <&aoss_qmp>;
2419                         clock-names = "apb_pclk";
2420
2421                         out-ports {
2422                                 port {
2423                                         stm_out: endpoint {
2424                                                 remote-endpoint =
2425                                                   <&funnel0_in7>;
2426                                         };
2427                                 };
2428                         };
2429                 };
2430
2431                 funnel@6041000 {
2432                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2433                         reg = <0 0x06041000 0 0x1000>;
2434
2435                         clocks = <&aoss_qmp>;
2436                         clock-names = "apb_pclk";
2437
2438                         out-ports {
2439                                 port {
2440                                         funnel0_out: endpoint {
2441                                                 remote-endpoint =
2442                                                   <&merge_funnel_in0>;
2443                                         };
2444                                 };
2445                         };
2446
2447                         in-ports {
2448                                 #address-cells = <1>;
2449                                 #size-cells = <0>;
2450
2451                                 port@7 {
2452                                         reg = <7>;
2453                                         funnel0_in7: endpoint {
2454                                                 remote-endpoint = <&stm_out>;
2455                                         };
2456                                 };
2457                         };
2458                 };
2459
2460                 funnel@6043000 {
2461                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2462                         reg = <0 0x06043000 0 0x1000>;
2463
2464                         clocks = <&aoss_qmp>;
2465                         clock-names = "apb_pclk";
2466
2467                         out-ports {
2468                                 port {
2469                                         funnel2_out: endpoint {
2470                                                 remote-endpoint =
2471                                                   <&merge_funnel_in2>;
2472                                         };
2473                                 };
2474                         };
2475
2476                         in-ports {
2477                                 #address-cells = <1>;
2478                                 #size-cells = <0>;
2479
2480                                 port@5 {
2481                                         reg = <5>;
2482                                         funnel2_in5: endpoint {
2483                                                 remote-endpoint =
2484                                                   <&apss_merge_funnel_out>;
2485                                         };
2486                                 };
2487                         };
2488                 };
2489
2490                 funnel@6045000 {
2491                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2492                         reg = <0 0x06045000 0 0x1000>;
2493
2494                         clocks = <&aoss_qmp>;
2495                         clock-names = "apb_pclk";
2496
2497                         out-ports {
2498                                 port {
2499                                         merge_funnel_out: endpoint {
2500                                                 remote-endpoint = <&etf_in>;
2501                                         };
2502                                 };
2503                         };
2504
2505                         in-ports {
2506                                 #address-cells = <1>;
2507                                 #size-cells = <0>;
2508
2509                                 port@0 {
2510                                         reg = <0>;
2511                                         merge_funnel_in0: endpoint {
2512                                                 remote-endpoint =
2513                                                   <&funnel0_out>;
2514                                         };
2515                                 };
2516
2517                                 port@2 {
2518                                         reg = <2>;
2519                                         merge_funnel_in2: endpoint {
2520                                                 remote-endpoint =
2521                                                   <&funnel2_out>;
2522                                         };
2523                                 };
2524                         };
2525                 };
2526
2527                 replicator@6046000 {
2528                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2529                         reg = <0 0x06046000 0 0x1000>;
2530
2531                         clocks = <&aoss_qmp>;
2532                         clock-names = "apb_pclk";
2533
2534                         out-ports {
2535                                 port {
2536                                         replicator_out: endpoint {
2537                                                 remote-endpoint = <&etr_in>;
2538                                         };
2539                                 };
2540                         };
2541
2542                         in-ports {
2543                                 port {
2544                                         replicator_in: endpoint {
2545                                                 remote-endpoint = <&etf_out>;
2546                                         };
2547                                 };
2548                         };
2549                 };
2550
2551                 etf@6047000 {
2552                         compatible = "arm,coresight-tmc", "arm,primecell";
2553                         reg = <0 0x06047000 0 0x1000>;
2554
2555                         clocks = <&aoss_qmp>;
2556                         clock-names = "apb_pclk";
2557
2558                         out-ports {
2559                                 port {
2560                                         etf_out: endpoint {
2561                                                 remote-endpoint =
2562                                                   <&replicator_in>;
2563                                         };
2564                                 };
2565                         };
2566
2567                         in-ports {
2568                                 #address-cells = <1>;
2569                                 #size-cells = <0>;
2570
2571                                 port@1 {
2572                                         reg = <1>;
2573                                         etf_in: endpoint {
2574                                                 remote-endpoint =
2575                                                   <&merge_funnel_out>;
2576                                         };
2577                                 };
2578                         };
2579                 };
2580
2581                 etr@6048000 {
2582                         compatible = "arm,coresight-tmc", "arm,primecell";
2583                         reg = <0 0x06048000 0 0x1000>;
2584
2585                         clocks = <&aoss_qmp>;
2586                         clock-names = "apb_pclk";
2587                         arm,scatter-gather;
2588
2589                         in-ports {
2590                                 port {
2591                                         etr_in: endpoint {
2592                                                 remote-endpoint =
2593                                                   <&replicator_out>;
2594                                         };
2595                                 };
2596                         };
2597                 };
2598
2599                 etm@7040000 {
2600                         compatible = "arm,coresight-etm4x", "arm,primecell";
2601                         reg = <0 0x07040000 0 0x1000>;
2602
2603                         cpu = <&CPU0>;
2604
2605                         clocks = <&aoss_qmp>;
2606                         clock-names = "apb_pclk";
2607
2608                         out-ports {
2609                                 port {
2610                                         etm0_out: endpoint {
2611                                                 remote-endpoint =
2612                                                   <&apss_funnel_in0>;
2613                                         };
2614                                 };
2615                         };
2616                 };
2617
2618                 etm@7140000 {
2619                         compatible = "arm,coresight-etm4x", "arm,primecell";
2620                         reg = <0 0x07140000 0 0x1000>;
2621
2622                         cpu = <&CPU1>;
2623
2624                         clocks = <&aoss_qmp>;
2625                         clock-names = "apb_pclk";
2626
2627                         out-ports {
2628                                 port {
2629                                         etm1_out: endpoint {
2630                                                 remote-endpoint =
2631                                                   <&apss_funnel_in1>;
2632                                         };
2633                                 };
2634                         };
2635                 };
2636
2637                 etm@7240000 {
2638                         compatible = "arm,coresight-etm4x", "arm,primecell";
2639                         reg = <0 0x07240000 0 0x1000>;
2640
2641                         cpu = <&CPU2>;
2642
2643                         clocks = <&aoss_qmp>;
2644                         clock-names = "apb_pclk";
2645
2646                         out-ports {
2647                                 port {
2648                                         etm2_out: endpoint {
2649                                                 remote-endpoint =
2650                                                   <&apss_funnel_in2>;
2651                                         };
2652                                 };
2653                         };
2654                 };
2655
2656                 etm@7340000 {
2657                         compatible = "arm,coresight-etm4x", "arm,primecell";
2658                         reg = <0 0x07340000 0 0x1000>;
2659
2660                         cpu = <&CPU3>;
2661
2662                         clocks = <&aoss_qmp>;
2663                         clock-names = "apb_pclk";
2664
2665                         out-ports {
2666                                 port {
2667                                         etm3_out: endpoint {
2668                                                 remote-endpoint =
2669                                                   <&apss_funnel_in3>;
2670                                         };
2671                                 };
2672                         };
2673                 };
2674
2675                 etm@7440000 {
2676                         compatible = "arm,coresight-etm4x", "arm,primecell";
2677                         reg = <0 0x07440000 0 0x1000>;
2678
2679                         cpu = <&CPU4>;
2680
2681                         clocks = <&aoss_qmp>;
2682                         clock-names = "apb_pclk";
2683
2684                         out-ports {
2685                                 port {
2686                                         etm4_out: endpoint {
2687                                                 remote-endpoint =
2688                                                   <&apss_funnel_in4>;
2689                                         };
2690                                 };
2691                         };
2692                 };
2693
2694                 etm@7540000 {
2695                         compatible = "arm,coresight-etm4x", "arm,primecell";
2696                         reg = <0 0x07540000 0 0x1000>;
2697
2698                         cpu = <&CPU5>;
2699
2700                         clocks = <&aoss_qmp>;
2701                         clock-names = "apb_pclk";
2702
2703                         out-ports {
2704                                 port {
2705                                         etm5_out: endpoint {
2706                                                 remote-endpoint =
2707                                                   <&apss_funnel_in5>;
2708                                         };
2709                                 };
2710                         };
2711                 };
2712
2713                 etm@7640000 {
2714                         compatible = "arm,coresight-etm4x", "arm,primecell";
2715                         reg = <0 0x07640000 0 0x1000>;
2716
2717                         cpu = <&CPU6>;
2718
2719                         clocks = <&aoss_qmp>;
2720                         clock-names = "apb_pclk";
2721
2722                         out-ports {
2723                                 port {
2724                                         etm6_out: endpoint {
2725                                                 remote-endpoint =
2726                                                   <&apss_funnel_in6>;
2727                                         };
2728                                 };
2729                         };
2730                 };
2731
2732                 etm@7740000 {
2733                         compatible = "arm,coresight-etm4x", "arm,primecell";
2734                         reg = <0 0x07740000 0 0x1000>;
2735
2736                         cpu = <&CPU7>;
2737
2738                         clocks = <&aoss_qmp>;
2739                         clock-names = "apb_pclk";
2740
2741                         out-ports {
2742                                 port {
2743                                         etm7_out: endpoint {
2744                                                 remote-endpoint =
2745                                                   <&apss_funnel_in7>;
2746                                         };
2747                                 };
2748                         };
2749                 };
2750
2751                 funnel@7800000 { /* APSS Funnel */
2752                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2753                         reg = <0 0x07800000 0 0x1000>;
2754
2755                         clocks = <&aoss_qmp>;
2756                         clock-names = "apb_pclk";
2757
2758                         out-ports {
2759                                 port {
2760                                         apss_funnel_out: endpoint {
2761                                                 remote-endpoint =
2762                                                   <&apss_merge_funnel_in>;
2763                                         };
2764                                 };
2765                         };
2766
2767                         in-ports {
2768                                 #address-cells = <1>;
2769                                 #size-cells = <0>;
2770
2771                                 port@0 {
2772                                         reg = <0>;
2773                                         apss_funnel_in0: endpoint {
2774                                                 remote-endpoint =
2775                                                   <&etm0_out>;
2776                                         };
2777                                 };
2778
2779                                 port@1 {
2780                                         reg = <1>;
2781                                         apss_funnel_in1: endpoint {
2782                                                 remote-endpoint =
2783                                                   <&etm1_out>;
2784                                         };
2785                                 };
2786
2787                                 port@2 {
2788                                         reg = <2>;
2789                                         apss_funnel_in2: endpoint {
2790                                                 remote-endpoint =
2791                                                   <&etm2_out>;
2792                                         };
2793                                 };
2794
2795                                 port@3 {
2796                                         reg = <3>;
2797                                         apss_funnel_in3: endpoint {
2798                                                 remote-endpoint =
2799                                                   <&etm3_out>;
2800                                         };
2801                                 };
2802
2803                                 port@4 {
2804                                         reg = <4>;
2805                                         apss_funnel_in4: endpoint {
2806                                                 remote-endpoint =
2807                                                   <&etm4_out>;
2808                                         };
2809                                 };
2810
2811                                 port@5 {
2812                                         reg = <5>;
2813                                         apss_funnel_in5: endpoint {
2814                                                 remote-endpoint =
2815                                                   <&etm5_out>;
2816                                         };
2817                                 };
2818
2819                                 port@6 {
2820                                         reg = <6>;
2821                                         apss_funnel_in6: endpoint {
2822                                                 remote-endpoint =
2823                                                   <&etm6_out>;
2824                                         };
2825                                 };
2826
2827                                 port@7 {
2828                                         reg = <7>;
2829                                         apss_funnel_in7: endpoint {
2830                                                 remote-endpoint =
2831                                                   <&etm7_out>;
2832                                         };
2833                                 };
2834                         };
2835                 };
2836
2837                 funnel@7810000 {
2838                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2839                         reg = <0 0x07810000 0 0x1000>;
2840
2841                         clocks = <&aoss_qmp>;
2842                         clock-names = "apb_pclk";
2843
2844                         out-ports {
2845                                 port {
2846                                         apss_merge_funnel_out: endpoint {
2847                                                 remote-endpoint =
2848                                                   <&funnel2_in5>;
2849                                         };
2850                                 };
2851                         };
2852
2853                         in-ports {
2854                                 port {
2855                                         apss_merge_funnel_in: endpoint {
2856                                                 remote-endpoint =
2857                                                   <&apss_funnel_out>;
2858                                         };
2859                                 };
2860                         };
2861                 };
2862
2863                 sdhc_2: sdhci@8804000 {
2864                         compatible = "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5";
2865                         reg = <0 0x08804000 0 0x1000>;
2866
2867                         interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
2868                                      <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
2869                         interrupt-names = "hc_irq", "pwr_irq";
2870
2871                         clocks = <&gcc GCC_SDCC2_AHB_CLK>,
2872                                  <&gcc GCC_SDCC2_APPS_CLK>;
2873                         clock-names = "iface", "core";
2874                         iommus = <&apps_smmu 0xa0 0xf>;
2875
2876                         status = "disabled";
2877                 };
2878
2879                 qspi: spi@88df000 {
2880                         compatible = "qcom,sdm845-qspi", "qcom,qspi-v1";
2881                         reg = <0 0x088df000 0 0x600>;
2882                         #address-cells = <1>;
2883                         #size-cells = <0>;
2884                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
2885                         clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
2886                                  <&gcc GCC_QSPI_CORE_CLK>;
2887                         clock-names = "iface", "core";
2888                         status = "disabled";
2889                 };
2890
2891                 slim: slim@171c0000 {
2892                         compatible = "qcom,slim-ngd-v2.1.0";
2893                         reg = <0 0x171c0000 0 0x2c000>;
2894                         interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
2895
2896                         qcom,apps-ch-pipes = <0x780000>;
2897                         qcom,ea-pc = <0x270>;
2898                         status = "okay";
2899                         dmas =  <&slimbam 3>, <&slimbam 4>,
2900                                 <&slimbam 5>, <&slimbam 6>;
2901                         dma-names = "rx", "tx", "tx2", "rx2";
2902
2903                         iommus = <&apps_smmu 0x1806 0x0>;
2904                         #address-cells = <1>;
2905                         #size-cells = <0>;
2906
2907                         ngd@1 {
2908                                 reg = <1>;
2909                                 #address-cells = <2>;
2910                                 #size-cells = <0>;
2911
2912                                 wcd9340_ifd: ifd@0{
2913                                         compatible = "slim217,250";
2914                                         reg  = <0 0>;
2915                                 };
2916
2917                                 wcd9340: codec@1{
2918                                         compatible = "slim217,250";
2919                                         reg  = <1 0>;
2920                                         slim-ifc-dev  = <&wcd9340_ifd>;
2921
2922                                         #sound-dai-cells = <1>;
2923
2924                                         interrupts-extended = <&tlmm 54 IRQ_TYPE_LEVEL_HIGH>;
2925                                         interrupt-controller;
2926                                         #interrupt-cells = <1>;
2927
2928                                         #clock-cells = <0>;
2929                                         clock-frequency = <9600000>;
2930                                         clock-output-names = "mclk";
2931                                         qcom,micbias1-millivolt = <1800>;
2932                                         qcom,micbias2-millivolt = <1800>;
2933                                         qcom,micbias3-millivolt = <1800>;
2934                                         qcom,micbias4-millivolt = <1800>;
2935
2936                                         #address-cells = <1>;
2937                                         #size-cells = <1>;
2938
2939                                         wcdgpio: gpio-controller@42 {
2940                                                 compatible = "qcom,wcd9340-gpio";
2941                                                 gpio-controller;
2942                                                 #gpio-cells = <2>;
2943                                                 reg = <0x42 0x2>;
2944                                         };
2945
2946                                         swm: swm@c85 {
2947                                                 compatible = "qcom,soundwire-v1.3.0";
2948                                                 reg = <0xc85 0x40>;
2949                                                 interrupts-extended = <&wcd9340 20>;
2950
2951                                                 qcom,dout-ports = <6>;
2952                                                 qcom,din-ports  = <2>;
2953                                                 qcom,ports-sinterval-low =/bits/ 8  <0x07 0x1F 0x3F 0x7 0x1F 0x3F 0x0F 0x0F>;
2954                                                 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0C 0x6 0x12 0x0D 0x07 0x0A >;
2955                                                 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x1F 0x00 0x00 0x1F 0x00 0x00>;
2956
2957                                                 #sound-dai-cells = <1>;
2958                                                 clocks = <&wcd9340>;
2959                                                 clock-names = "iface";
2960                                                 #address-cells = <2>;
2961                                                 #size-cells = <0>;
2962
2963
2964                                         };
2965                                 };
2966                         };
2967                 };
2968
2969                 sound: sound {
2970                 };
2971
2972                 usb_1_hsphy: phy@88e2000 {
2973                         compatible = "qcom,sdm845-qusb2-phy";
2974                         reg = <0 0x088e2000 0 0x400>;
2975                         status = "disabled";
2976                         #phy-cells = <0>;
2977
2978                         clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2979                                  <&rpmhcc RPMH_CXO_CLK>;
2980                         clock-names = "cfg_ahb", "ref";
2981
2982                         resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2983
2984                         nvmem-cells = <&qusb2p_hstx_trim>;
2985                 };
2986
2987                 usb_2_hsphy: phy@88e3000 {
2988                         compatible = "qcom,sdm845-qusb2-phy";
2989                         reg = <0 0x088e3000 0 0x400>;
2990                         status = "disabled";
2991                         #phy-cells = <0>;
2992
2993                         clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2994                                  <&rpmhcc RPMH_CXO_CLK>;
2995                         clock-names = "cfg_ahb", "ref";
2996
2997                         resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
2998
2999                         nvmem-cells = <&qusb2s_hstx_trim>;
3000                 };
3001
3002                 usb_1_qmpphy: phy@88e9000 {
3003                         compatible = "qcom,sdm845-qmp-usb3-phy";
3004                         reg = <0 0x088e9000 0 0x18c>,
3005                               <0 0x088e8000 0 0x10>;
3006                         reg-names = "reg-base", "dp_com";
3007                         status = "disabled";
3008                         #clock-cells = <1>;
3009                         #address-cells = <2>;
3010                         #size-cells = <2>;
3011                         ranges;
3012
3013                         clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
3014                                  <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3015                                  <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
3016                                  <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
3017                         clock-names = "aux", "cfg_ahb", "ref", "com_aux";
3018
3019                         resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
3020                                  <&gcc GCC_USB3_PHY_PRIM_BCR>;
3021                         reset-names = "phy", "common";
3022
3023                         usb_1_ssphy: lanes@88e9200 {
3024                                 reg = <0 0x088e9200 0 0x128>,
3025                                       <0 0x088e9400 0 0x200>,
3026                                       <0 0x088e9c00 0 0x218>,
3027                                       <0 0x088e9600 0 0x128>,
3028                                       <0 0x088e9800 0 0x200>,
3029                                       <0 0x088e9a00 0 0x100>;
3030                                 #phy-cells = <0>;
3031                                 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
3032                                 clock-names = "pipe0";
3033                                 clock-output-names = "usb3_phy_pipe_clk_src";
3034                         };
3035                 };
3036
3037                 usb_2_qmpphy: phy@88eb000 {
3038                         compatible = "qcom,sdm845-qmp-usb3-uni-phy";
3039                         reg = <0 0x088eb000 0 0x18c>;
3040                         status = "disabled";
3041                         #clock-cells = <1>;
3042                         #address-cells = <2>;
3043                         #size-cells = <2>;
3044                         ranges;
3045
3046                         clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
3047                                  <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3048                                  <&gcc GCC_USB3_SEC_CLKREF_CLK>,
3049                                  <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
3050                         clock-names = "aux", "cfg_ahb", "ref", "com_aux";
3051
3052                         resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
3053                                  <&gcc GCC_USB3_PHY_SEC_BCR>;
3054                         reset-names = "phy", "common";
3055
3056                         usb_2_ssphy: lane@88eb200 {
3057                                 reg = <0 0x088eb200 0 0x128>,
3058                                       <0 0x088eb400 0 0x1fc>,
3059                                       <0 0x088eb800 0 0x218>,
3060                                       <0 0x088eb600 0 0x70>;
3061                                 #phy-cells = <0>;
3062                                 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
3063                                 clock-names = "pipe0";
3064                                 clock-output-names = "usb3_uni_phy_pipe_clk_src";
3065                         };
3066                 };
3067
3068                 usb_1: usb@a6f8800 {
3069                         compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
3070                         reg = <0 0x0a6f8800 0 0x400>;
3071                         status = "disabled";
3072                         #address-cells = <2>;
3073                         #size-cells = <2>;
3074                         ranges;
3075                         dma-ranges;
3076
3077                         clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
3078                                  <&gcc GCC_USB30_PRIM_MASTER_CLK>,
3079                                  <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
3080                                  <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3081                                  <&gcc GCC_USB30_PRIM_SLEEP_CLK>;
3082                         clock-names = "cfg_noc", "core", "iface", "mock_utmi",
3083                                       "sleep";
3084
3085                         assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3086                                           <&gcc GCC_USB30_PRIM_MASTER_CLK>;
3087                         assigned-clock-rates = <19200000>, <150000000>;
3088
3089                         interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
3090                                      <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
3091                                      <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
3092                                      <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
3093                         interrupt-names = "hs_phy_irq", "ss_phy_irq",
3094                                           "dm_hs_phy_irq", "dp_hs_phy_irq";
3095
3096                         power-domains = <&gcc USB30_PRIM_GDSC>;
3097
3098                         resets = <&gcc GCC_USB30_PRIM_BCR>;
3099
3100                         usb_1_dwc3: dwc3@a600000 {
3101                                 compatible = "snps,dwc3";
3102                                 reg = <0 0x0a600000 0 0xcd00>;
3103                                 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
3104                                 iommus = <&apps_smmu 0x740 0>;
3105                                 snps,dis_u2_susphy_quirk;
3106                                 snps,dis_enblslpm_quirk;
3107                                 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
3108                                 phy-names = "usb2-phy", "usb3-phy";
3109                         };
3110                 };
3111
3112                 usb_2: usb@a8f8800 {
3113                         compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
3114                         reg = <0 0x0a8f8800 0 0x400>;
3115                         status = "disabled";
3116                         #address-cells = <2>;
3117                         #size-cells = <2>;
3118                         ranges;
3119                         dma-ranges;
3120
3121                         clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
3122                                  <&gcc GCC_USB30_SEC_MASTER_CLK>,
3123                                  <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
3124                                  <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3125                                  <&gcc GCC_USB30_SEC_SLEEP_CLK>;
3126                         clock-names = "cfg_noc", "core", "iface", "mock_utmi",
3127                                       "sleep";
3128
3129                         assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3130                                           <&gcc GCC_USB30_SEC_MASTER_CLK>;
3131                         assigned-clock-rates = <19200000>, <150000000>;
3132
3133                         interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
3134                                      <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>,
3135                                      <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>,
3136                                      <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>;
3137                         interrupt-names = "hs_phy_irq", "ss_phy_irq",
3138                                           "dm_hs_phy_irq", "dp_hs_phy_irq";
3139
3140                         power-domains = <&gcc USB30_SEC_GDSC>;
3141
3142                         resets = <&gcc GCC_USB30_SEC_BCR>;
3143
3144                         usb_2_dwc3: dwc3@a800000 {
3145                                 compatible = "snps,dwc3";
3146                                 reg = <0 0x0a800000 0 0xcd00>;
3147                                 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
3148                                 iommus = <&apps_smmu 0x760 0>;
3149                                 snps,dis_u2_susphy_quirk;
3150                                 snps,dis_enblslpm_quirk;
3151                                 phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
3152                                 phy-names = "usb2-phy", "usb3-phy";
3153                         };
3154                 };
3155
3156                 venus: video-codec@aa00000 {
3157                         compatible = "qcom,sdm845-venus-v2";
3158                         reg = <0 0x0aa00000 0 0xff000>;
3159                         interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
3160                         power-domains = <&videocc VENUS_GDSC>,
3161                                         <&videocc VCODEC0_GDSC>,
3162                                         <&videocc VCODEC1_GDSC>;
3163                         power-domain-names = "venus", "vcodec0", "vcodec1";
3164                         clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>,
3165                                  <&videocc VIDEO_CC_VENUS_AHB_CLK>,
3166                                  <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>,
3167                                  <&videocc VIDEO_CC_VCODEC0_CORE_CLK>,
3168                                  <&videocc VIDEO_CC_VCODEC0_AXI_CLK>,
3169                                  <&videocc VIDEO_CC_VCODEC1_CORE_CLK>,
3170                                  <&videocc VIDEO_CC_VCODEC1_AXI_CLK>;
3171                         clock-names = "core", "iface", "bus",
3172                                       "vcodec0_core", "vcodec0_bus",
3173                                       "vcodec1_core", "vcodec1_bus";
3174                         iommus = <&apps_smmu 0x10a0 0x8>,
3175                                  <&apps_smmu 0x10b0 0x0>;
3176                         memory-region = <&venus_mem>;
3177
3178                         video-core0 {
3179                                 compatible = "venus-decoder";
3180                         };
3181
3182                         video-core1 {
3183                                 compatible = "venus-encoder";
3184                         };
3185                 };
3186
3187                 videocc: clock-controller@ab00000 {
3188                         compatible = "qcom,sdm845-videocc";
3189                         reg = <0 0x0ab00000 0 0x10000>;
3190                         clocks = <&rpmhcc RPMH_CXO_CLK>;
3191                         clock-names = "bi_tcxo";
3192                         #clock-cells = <1>;
3193                         #power-domain-cells = <1>;
3194                         #reset-cells = <1>;
3195                 };
3196
3197                 mdss: mdss@ae00000 {
3198                         compatible = "qcom,sdm845-mdss";
3199                         reg = <0 0x0ae00000 0 0x1000>;
3200                         reg-names = "mdss";
3201
3202                         power-domains = <&dispcc MDSS_GDSC>;
3203
3204                         clocks = <&gcc GCC_DISP_AHB_CLK>,
3205                                  <&gcc GCC_DISP_AXI_CLK>,
3206                                  <&dispcc DISP_CC_MDSS_MDP_CLK>;
3207                         clock-names = "iface", "bus", "core";
3208
3209                         assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
3210                         assigned-clock-rates = <300000000>;
3211
3212                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
3213                         interrupt-controller;
3214                         #interrupt-cells = <1>;
3215
3216                         iommus = <&apps_smmu 0x880 0x8>,
3217                                  <&apps_smmu 0xc80 0x8>;
3218
3219                         status = "disabled";
3220
3221                         #address-cells = <2>;
3222                         #size-cells = <2>;
3223                         ranges;
3224
3225                         mdss_mdp: mdp@ae01000 {
3226                                 compatible = "qcom,sdm845-dpu";
3227                                 reg = <0 0x0ae01000 0 0x8f000>,
3228                                       <0 0x0aeb0000 0 0x2008>;
3229                                 reg-names = "mdp", "vbif";
3230
3231                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3232                                          <&dispcc DISP_CC_MDSS_AXI_CLK>,
3233                                          <&dispcc DISP_CC_MDSS_MDP_CLK>,
3234                                          <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
3235                                 clock-names = "iface", "bus", "core", "vsync";
3236
3237                                 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
3238                                                   <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
3239                                 assigned-clock-rates = <300000000>,
3240                                                        <19200000>;
3241
3242                                 interrupt-parent = <&mdss>;
3243                                 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
3244
3245                                 status = "disabled";
3246
3247                                 ports {
3248                                         #address-cells = <1>;
3249                                         #size-cells = <0>;
3250
3251                                         port@0 {
3252                                                 reg = <0>;
3253                                                 dpu_intf1_out: endpoint {
3254                                                         remote-endpoint = <&dsi0_in>;
3255                                                 };
3256                                         };
3257
3258                                         port@1 {
3259                                                 reg = <1>;
3260                                                 dpu_intf2_out: endpoint {
3261                                                         remote-endpoint = <&dsi1_in>;
3262                                                 };
3263                                         };
3264                                 };
3265                         };
3266
3267                         dsi0: dsi@ae94000 {
3268                                 compatible = "qcom,mdss-dsi-ctrl";
3269                                 reg = <0 0x0ae94000 0 0x400>;
3270                                 reg-names = "dsi_ctrl";
3271
3272                                 interrupt-parent = <&mdss>;
3273                                 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
3274
3275                                 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
3276                                          <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
3277                                          <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
3278                                          <&dispcc DISP_CC_MDSS_ESC0_CLK>,
3279                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
3280                                          <&dispcc DISP_CC_MDSS_AXI_CLK>;
3281                                 clock-names = "byte",
3282                                               "byte_intf",
3283                                               "pixel",
3284                                               "core",
3285                                               "iface",
3286                                               "bus";
3287
3288                                 phys = <&dsi0_phy>;
3289                                 phy-names = "dsi";
3290
3291                                 status = "disabled";
3292
3293                                 ports {
3294                                         #address-cells = <1>;
3295                                         #size-cells = <0>;
3296
3297                                         port@0 {
3298                                                 reg = <0>;
3299                                                 dsi0_in: endpoint {
3300                                                         remote-endpoint = <&dpu_intf1_out>;
3301                                                 };
3302                                         };
3303
3304                                         port@1 {
3305                                                 reg = <1>;
3306                                                 dsi0_out: endpoint {
3307                                                 };
3308                                         };
3309                                 };
3310                         };
3311
3312                         dsi0_phy: dsi-phy@ae94400 {
3313                                 compatible = "qcom,dsi-phy-10nm";
3314                                 reg = <0 0x0ae94400 0 0x200>,
3315                                       <0 0x0ae94600 0 0x280>,
3316                                       <0 0x0ae94a00 0 0x1e0>;
3317                                 reg-names = "dsi_phy",
3318                                             "dsi_phy_lane",
3319                                             "dsi_pll";
3320
3321                                 #clock-cells = <1>;
3322                                 #phy-cells = <0>;
3323
3324                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3325                                          <&rpmhcc RPMH_CXO_CLK>;
3326                                 clock-names = "iface", "ref";
3327
3328                                 status = "disabled";
3329                         };
3330
3331                         dsi1: dsi@ae96000 {
3332                                 compatible = "qcom,mdss-dsi-ctrl";
3333                                 reg = <0 0x0ae96000 0 0x400>;
3334                                 reg-names = "dsi_ctrl";
3335
3336                                 interrupt-parent = <&mdss>;
3337                                 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
3338
3339                                 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
3340                                          <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
3341                                          <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
3342                                          <&dispcc DISP_CC_MDSS_ESC1_CLK>,
3343                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
3344                                          <&dispcc DISP_CC_MDSS_AXI_CLK>;
3345                                 clock-names = "byte",
3346                                               "byte_intf",
3347                                               "pixel",
3348                                               "core",
3349                                               "iface",
3350                                               "bus";
3351
3352                                 phys = <&dsi1_phy>;
3353                                 phy-names = "dsi";
3354
3355                                 status = "disabled";
3356
3357                                 ports {
3358                                         #address-cells = <1>;
3359                                         #size-cells = <0>;
3360
3361                                         port@0 {
3362                                                 reg = <0>;
3363                                                 dsi1_in: endpoint {
3364                                                         remote-endpoint = <&dpu_intf2_out>;
3365                                                 };
3366                                         };
3367
3368                                         port@1 {
3369                                                 reg = <1>;
3370                                                 dsi1_out: endpoint {
3371                                                 };
3372                                         };
3373                                 };
3374                         };
3375
3376                         dsi1_phy: dsi-phy@ae96400 {
3377                                 compatible = "qcom,dsi-phy-10nm";
3378                                 reg = <0 0x0ae96400 0 0x200>,
3379                                       <0 0x0ae96600 0 0x280>,
3380                                       <0 0x0ae96a00 0 0x10e>;
3381                                 reg-names = "dsi_phy",
3382                                             "dsi_phy_lane",
3383                                             "dsi_pll";
3384
3385                                 #clock-cells = <1>;
3386                                 #phy-cells = <0>;
3387
3388                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3389                                          <&rpmhcc RPMH_CXO_CLK>;
3390                                 clock-names = "iface", "ref";
3391
3392                                 status = "disabled";
3393                         };
3394                 };
3395
3396                 gpu: gpu@5000000 {
3397                         compatible = "qcom,adreno-630.2", "qcom,adreno";
3398                         #stream-id-cells = <16>;
3399
3400                         reg = <0 0x5000000 0 0x40000>, <0 0x509e000 0 0x10>;
3401                         reg-names = "kgsl_3d0_reg_memory", "cx_mem";
3402
3403                         /*
3404                          * Look ma, no clocks! The GPU clocks and power are
3405                          * controlled entirely by the GMU
3406                          */
3407
3408                         interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
3409
3410                         iommus = <&adreno_smmu 0>;
3411
3412                         operating-points-v2 = <&gpu_opp_table>;
3413
3414                         qcom,gmu = <&gmu>;
3415
3416                         gpu_opp_table: opp-table {
3417                                 compatible = "operating-points-v2";
3418
3419                                 opp-710000000 {
3420                                         opp-hz = /bits/ 64 <710000000>;
3421                                         opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3422                                 };
3423
3424                                 opp-675000000 {
3425                                         opp-hz = /bits/ 64 <675000000>;
3426                                         opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3427                                 };
3428
3429                                 opp-596000000 {
3430                                         opp-hz = /bits/ 64 <596000000>;
3431                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3432                                 };
3433
3434                                 opp-520000000 {
3435                                         opp-hz = /bits/ 64 <520000000>;
3436                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3437                                 };
3438
3439                                 opp-414000000 {
3440                                         opp-hz = /bits/ 64 <414000000>;
3441                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3442                                 };
3443
3444                                 opp-342000000 {
3445                                         opp-hz = /bits/ 64 <342000000>;
3446                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3447                                 };
3448
3449                                 opp-257000000 {
3450                                         opp-hz = /bits/ 64 <257000000>;
3451                                         opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3452                                 };
3453                         };
3454                 };
3455
3456                 adreno_smmu: iommu@5040000 {
3457                         compatible = "qcom,sdm845-smmu-v2", "qcom,smmu-v2";
3458                         reg = <0 0x5040000 0 0x10000>;
3459                         #iommu-cells = <1>;
3460                         #global-interrupts = <2>;
3461                         interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
3462                                      <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
3463                                      <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
3464                                      <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
3465                                      <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
3466                                      <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
3467                                      <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
3468                                      <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>,
3469                                      <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>,
3470                                      <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>;
3471                         clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
3472                                  <&gcc GCC_GPU_CFG_AHB_CLK>;
3473                         clock-names = "bus", "iface";
3474
3475                         power-domains = <&gpucc GPU_CX_GDSC>;
3476                 };
3477
3478                 gmu: gmu@506a000 {
3479                         compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
3480
3481                         reg = <0 0x506a000 0 0x30000>,
3482                               <0 0xb280000 0 0x10000>,
3483                               <0 0xb480000 0 0x10000>;
3484                         reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
3485
3486                         interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
3487                                      <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
3488                         interrupt-names = "hfi", "gmu";
3489
3490                         clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
3491                                  <&gpucc GPU_CC_CXO_CLK>,
3492                                  <&gcc GCC_DDRSS_GPU_AXI_CLK>,
3493                                  <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
3494                         clock-names = "gmu", "cxo", "axi", "memnoc";
3495
3496                         power-domains = <&gpucc GPU_CX_GDSC>,
3497                                         <&gpucc GPU_GX_GDSC>;
3498                         power-domain-names = "cx", "gx";
3499
3500                         iommus = <&adreno_smmu 5>;
3501
3502                         operating-points-v2 = <&gmu_opp_table>;
3503
3504                         gmu_opp_table: opp-table {
3505                                 compatible = "operating-points-v2";
3506
3507                                 opp-400000000 {
3508                                         opp-hz = /bits/ 64 <400000000>;
3509                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3510                                 };
3511
3512                                 opp-200000000 {
3513                                         opp-hz = /bits/ 64 <200000000>;
3514                                         opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3515                                 };
3516                         };
3517                 };
3518
3519                 dispcc: clock-controller@af00000 {
3520                         compatible = "qcom,sdm845-dispcc";
3521                         reg = <0 0x0af00000 0 0x10000>;
3522                         clocks = <&rpmhcc RPMH_CXO_CLK>,
3523                                  <&gcc GCC_DISP_GPLL0_CLK_SRC>,
3524                                  <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
3525                                  <&dsi0_phy 0>,
3526                                  <&dsi0_phy 1>,
3527                                  <&dsi1_phy 0>,
3528                                  <&dsi1_phy 1>,
3529                                  <0>,
3530                                  <0>;
3531                         clock-names = "bi_tcxo",
3532                                       "gcc_disp_gpll0_clk_src",
3533                                       "gcc_disp_gpll0_div_clk_src",
3534                                       "dsi0_phy_pll_out_byteclk",
3535                                       "dsi0_phy_pll_out_dsiclk",
3536                                       "dsi1_phy_pll_out_byteclk",
3537                                       "dsi1_phy_pll_out_dsiclk",
3538                                       "dp_link_clk_divsel_ten",
3539                                       "dp_vco_divided_clk_src_mux";
3540                         #clock-cells = <1>;
3541                         #reset-cells = <1>;
3542                         #power-domain-cells = <1>;
3543                 };
3544
3545                 pdc_intc: interrupt-controller@b220000 {
3546                         compatible = "qcom,sdm845-pdc", "qcom,pdc";
3547                         reg = <0 0x0b220000 0 0x30000>;
3548                         qcom,pdc-ranges = <0 480 94>, <94 609 15>, <115 630 7>;
3549                         #interrupt-cells = <2>;
3550                         interrupt-parent = <&intc>;
3551                         interrupt-controller;
3552                 };
3553
3554                 pdc_reset: reset-controller@b2e0000 {
3555                         compatible = "qcom,sdm845-pdc-global";
3556                         reg = <0 0x0b2e0000 0 0x20000>;
3557                         #reset-cells = <1>;
3558                 };
3559
3560                 tsens0: thermal-sensor@c263000 {
3561                         compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
3562                         reg = <0 0x0c263000 0 0x1ff>, /* TM */
3563                               <0 0x0c222000 0 0x1ff>; /* SROT */
3564                         #qcom,sensors = <13>;
3565                         interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
3566                                      <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
3567                         interrupt-names = "uplow", "critical";
3568                         #thermal-sensor-cells = <1>;
3569                 };
3570
3571                 tsens1: thermal-sensor@c265000 {
3572                         compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
3573                         reg = <0 0x0c265000 0 0x1ff>, /* TM */
3574                               <0 0x0c223000 0 0x1ff>; /* SROT */
3575                         #qcom,sensors = <8>;
3576                         interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
3577                                      <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
3578                         interrupt-names = "uplow", "critical";
3579                         #thermal-sensor-cells = <1>;
3580                 };
3581
3582                 aoss_reset: reset-controller@c2a0000 {
3583                         compatible = "qcom,sdm845-aoss-cc";
3584                         reg = <0 0x0c2a0000 0 0x31000>;
3585                         #reset-cells = <1>;
3586                 };
3587
3588                 aoss_qmp: qmp@c300000 {
3589                         compatible = "qcom,sdm845-aoss-qmp";
3590                         reg = <0 0x0c300000 0 0x100000>;
3591                         interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
3592                         mboxes = <&apss_shared 0>;
3593
3594                         #clock-cells = <0>;
3595                         #power-domain-cells = <1>;
3596
3597                         cx_cdev: cx {
3598                                 #cooling-cells = <2>;
3599                         };
3600
3601                         ebi_cdev: ebi {
3602                                 #cooling-cells = <2>;
3603                         };
3604                 };
3605
3606                 spmi_bus: spmi@c440000 {
3607                         compatible = "qcom,spmi-pmic-arb";
3608                         reg = <0 0x0c440000 0 0x1100>,
3609                               <0 0x0c600000 0 0x2000000>,
3610                               <0 0x0e600000 0 0x100000>,
3611                               <0 0x0e700000 0 0xa0000>,
3612                               <0 0x0c40a000 0 0x26000>;
3613                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
3614                         interrupt-names = "periph_irq";
3615                         interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
3616                         qcom,ee = <0>;
3617                         qcom,channel = <0>;
3618                         #address-cells = <2>;
3619                         #size-cells = <0>;
3620                         interrupt-controller;
3621                         #interrupt-cells = <4>;
3622                         cell-index = <0>;
3623                 };
3624
3625                 apps_smmu: iommu@15000000 {
3626                         compatible = "qcom,sdm845-smmu-500", "arm,mmu-500";
3627                         reg = <0 0x15000000 0 0x80000>;
3628                         #iommu-cells = <2>;
3629                         #global-interrupts = <1>;
3630                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
3631                                      <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
3632                                      <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
3633                                      <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
3634                                      <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
3635                                      <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
3636                                      <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
3637                                      <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
3638                                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
3639                                      <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
3640                                      <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
3641                                      <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
3642                                      <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
3643                                      <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
3644                                      <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
3645                                      <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
3646                                      <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
3647                                      <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
3648                                      <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
3649                                      <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
3650                                      <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
3651                                      <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
3652                                      <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
3653                                      <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
3654                                      <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
3655                                      <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
3656                                      <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
3657                                      <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
3658                                      <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
3659                                      <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
3660                                      <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
3661                                      <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
3662                                      <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
3663                                      <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
3664                                      <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
3665                                      <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
3666                                      <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
3667                                      <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
3668                                      <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
3669                                      <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
3670                                      <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
3671                                      <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
3672                                      <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
3673                                      <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
3674                                      <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
3675                                      <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
3676                                      <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
3677                                      <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
3678                                      <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
3679                                      <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
3680                                      <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
3681                                      <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
3682                                      <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
3683                                      <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
3684                                      <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
3685                                      <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
3686                                      <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
3687                                      <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
3688                                      <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
3689                                      <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
3690                                      <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
3691                                      <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
3692                                      <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
3693                                      <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
3694                                      <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
3695                 };
3696
3697                 lpasscc: clock-controller@17014000 {
3698                         compatible = "qcom,sdm845-lpasscc";
3699                         reg = <0 0x17014000 0 0x1f004>, <0 0x17300000 0 0x200>;
3700                         reg-names = "cc", "qdsp6ss";
3701                         #clock-cells = <1>;
3702                         status = "disabled";
3703                 };
3704
3705                 gladiator_noc: interconnect@17900000 {
3706                         compatible = "qcom,sdm845-gladiator-noc";
3707                         reg = <0 0x17900000 0 0xd080>;
3708                         #interconnect-cells = <1>;
3709                         qcom,bcm-voters = <&apps_bcm_voter>;
3710                 };
3711
3712                 watchdog@17980000 {
3713                         compatible = "qcom,apss-wdt-sdm845", "qcom,kpss-wdt";
3714                         reg = <0 0x17980000 0 0x1000>;
3715                         clocks = <&sleep_clk>;
3716                 };
3717
3718                 apss_shared: mailbox@17990000 {
3719                         compatible = "qcom,sdm845-apss-shared";
3720                         reg = <0 0x17990000 0 0x1000>;
3721                         #mbox-cells = <1>;
3722                 };
3723
3724                 apps_rsc: rsc@179c0000 {
3725                         label = "apps_rsc";
3726                         compatible = "qcom,rpmh-rsc";
3727                         reg = <0 0x179c0000 0 0x10000>,
3728                               <0 0x179d0000 0 0x10000>,
3729                               <0 0x179e0000 0 0x10000>;
3730                         reg-names = "drv-0", "drv-1", "drv-2";
3731                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
3732                                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
3733                                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
3734                         qcom,tcs-offset = <0xd00>;
3735                         qcom,drv-id = <2>;
3736                         qcom,tcs-config = <ACTIVE_TCS  2>,
3737                                           <SLEEP_TCS   3>,
3738                                           <WAKE_TCS    3>,
3739                                           <CONTROL_TCS 1>;
3740
3741                         apps_bcm_voter: bcm-voter {
3742                                 compatible = "qcom,bcm-voter";
3743                         };
3744
3745                         rpmhcc: clock-controller {
3746                                 compatible = "qcom,sdm845-rpmh-clk";
3747                                 #clock-cells = <1>;
3748                                 clock-names = "xo";
3749                                 clocks = <&xo_board>;
3750                         };
3751
3752                         rpmhpd: power-controller {
3753                                 compatible = "qcom,sdm845-rpmhpd";
3754                                 #power-domain-cells = <1>;
3755                                 operating-points-v2 = <&rpmhpd_opp_table>;
3756
3757                                 rpmhpd_opp_table: opp-table {
3758                                         compatible = "operating-points-v2";
3759
3760                                         rpmhpd_opp_ret: opp1 {
3761                                                 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
3762                                         };
3763
3764                                         rpmhpd_opp_min_svs: opp2 {
3765                                                 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3766                                         };
3767
3768                                         rpmhpd_opp_low_svs: opp3 {
3769                                                 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3770                                         };
3771
3772                                         rpmhpd_opp_svs: opp4 {
3773                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3774                                         };
3775
3776                                         rpmhpd_opp_svs_l1: opp5 {
3777                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3778                                         };
3779
3780                                         rpmhpd_opp_nom: opp6 {
3781                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3782                                         };
3783
3784                                         rpmhpd_opp_nom_l1: opp7 {
3785                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3786                                         };
3787
3788                                         rpmhpd_opp_nom_l2: opp8 {
3789                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
3790                                         };
3791
3792                                         rpmhpd_opp_turbo: opp9 {
3793                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3794                                         };
3795
3796                                         rpmhpd_opp_turbo_l1: opp10 {
3797                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3798                                         };
3799                                 };
3800                         };
3801                 };
3802
3803                 intc: interrupt-controller@17a00000 {
3804                         compatible = "arm,gic-v3";
3805                         #address-cells = <2>;
3806                         #size-cells = <2>;
3807                         ranges;
3808                         #interrupt-cells = <3>;
3809                         interrupt-controller;
3810                         reg = <0 0x17a00000 0 0x10000>,     /* GICD */
3811                               <0 0x17a60000 0 0x100000>;    /* GICR * 8 */
3812                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
3813
3814                         msi-controller@17a40000 {
3815                                 compatible = "arm,gic-v3-its";
3816                                 msi-controller;
3817                                 #msi-cells = <1>;
3818                                 reg = <0 0x17a40000 0 0x20000>;
3819                                 status = "disabled";
3820                         };
3821                 };
3822
3823                 slimbam: dma@17184000 {
3824                         compatible = "qcom,bam-v1.7.0";
3825                         qcom,controlled-remotely;
3826                         reg = <0 0x17184000 0 0x2a000>;
3827                         num-channels  = <31>;
3828                         interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
3829                         #dma-cells = <1>;
3830                         qcom,ee = <1>;
3831                         qcom,num-ees = <2>;
3832                         iommus = <&apps_smmu 0x1806 0x0>;
3833                 };
3834
3835                 timer@17c90000 {
3836                         #address-cells = <2>;
3837                         #size-cells = <2>;
3838                         ranges;
3839                         compatible = "arm,armv7-timer-mem";
3840                         reg = <0 0x17c90000 0 0x1000>;
3841
3842                         frame@17ca0000 {
3843                                 frame-number = <0>;
3844                                 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
3845                                              <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
3846                                 reg = <0 0x17ca0000 0 0x1000>,
3847                                       <0 0x17cb0000 0 0x1000>;
3848                         };
3849
3850                         frame@17cc0000 {
3851                                 frame-number = <1>;
3852                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
3853                                 reg = <0 0x17cc0000 0 0x1000>;
3854                                 status = "disabled";
3855                         };
3856
3857                         frame@17cd0000 {
3858                                 frame-number = <2>;
3859                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
3860                                 reg = <0 0x17cd0000 0 0x1000>;
3861                                 status = "disabled";
3862                         };
3863
3864                         frame@17ce0000 {
3865                                 frame-number = <3>;
3866                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
3867                                 reg = <0 0x17ce0000 0 0x1000>;
3868                                 status = "disabled";
3869                         };
3870
3871                         frame@17cf0000 {
3872                                 frame-number = <4>;
3873                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
3874                                 reg = <0 0x17cf0000 0 0x1000>;
3875                                 status = "disabled";
3876                         };
3877
3878                         frame@17d00000 {
3879                                 frame-number = <5>;
3880                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
3881                                 reg = <0 0x17d00000 0 0x1000>;
3882                                 status = "disabled";
3883                         };
3884
3885                         frame@17d10000 {
3886                                 frame-number = <6>;
3887                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
3888                                 reg = <0 0x17d10000 0 0x1000>;
3889                                 status = "disabled";
3890                         };
3891                 };
3892
3893                 osm_l3: interconnect@17d41000 {
3894                         compatible = "qcom,sdm845-osm-l3";
3895                         reg = <0 0x17d41000 0 0x1400>;
3896
3897                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
3898                         clock-names = "xo", "alternate";
3899
3900                         #interconnect-cells = <1>;
3901                 };
3902
3903                 cpufreq_hw: cpufreq@17d43000 {
3904                         compatible = "qcom,cpufreq-hw";
3905                         reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>;
3906                         reg-names = "freq-domain0", "freq-domain1";
3907
3908                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
3909                         clock-names = "xo", "alternate";
3910
3911                         #freq-domain-cells = <1>;
3912                 };
3913
3914                 wifi: wifi@18800000 {
3915                         compatible = "qcom,wcn3990-wifi";
3916                         status = "disabled";
3917                         reg = <0 0x18800000 0 0x800000>;
3918                         reg-names = "membase";
3919                         memory-region = <&wlan_msa_mem>;
3920                         clock-names = "cxo_ref_clk_pin";
3921                         clocks = <&rpmhcc RPMH_RF_CLK2>;
3922                         interrupts =
3923                                 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
3924                                 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
3925                                 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
3926                                 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
3927                                 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
3928                                 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
3929                                 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
3930                                 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
3931                                 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
3932                                 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
3933                                 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
3934                                 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
3935                         iommus = <&apps_smmu 0x0040 0x1>;
3936                 };
3937         };
3938
3939         thermal-zones {
3940                 cpu0-thermal {
3941                         polling-delay-passive = <250>;
3942                         polling-delay = <1000>;
3943
3944                         thermal-sensors = <&tsens0 1>;
3945
3946                         trips {
3947                                 cpu0_alert0: trip-point0 {
3948                                         temperature = <90000>;
3949                                         hysteresis = <2000>;
3950                                         type = "passive";
3951                                 };
3952
3953                                 cpu0_alert1: trip-point1 {
3954                                         temperature = <95000>;
3955                                         hysteresis = <2000>;
3956                                         type = "passive";
3957                                 };
3958
3959                                 cpu0_crit: cpu_crit {
3960                                         temperature = <110000>;
3961                                         hysteresis = <1000>;
3962                                         type = "critical";
3963                                 };
3964                         };
3965
3966                         cooling-maps {
3967                                 map0 {
3968                                         trip = <&cpu0_alert0>;
3969                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3970                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3971                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3972                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3973                                 };
3974                                 map1 {
3975                                         trip = <&cpu0_alert1>;
3976                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3977                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3978                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3979                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3980                                 };
3981                         };
3982                 };
3983
3984                 cpu1-thermal {
3985                         polling-delay-passive = <250>;
3986                         polling-delay = <1000>;
3987
3988                         thermal-sensors = <&tsens0 2>;
3989
3990                         trips {
3991                                 cpu1_alert0: trip-point0 {
3992                                         temperature = <90000>;
3993                                         hysteresis = <2000>;
3994                                         type = "passive";
3995                                 };
3996
3997                                 cpu1_alert1: trip-point1 {
3998                                         temperature = <95000>;
3999                                         hysteresis = <2000>;
4000                                         type = "passive";
4001                                 };
4002
4003                                 cpu1_crit: cpu_crit {
4004                                         temperature = <110000>;
4005                                         hysteresis = <1000>;
4006                                         type = "critical";
4007                                 };
4008                         };
4009
4010                         cooling-maps {
4011                                 map0 {
4012                                         trip = <&cpu1_alert0>;
4013                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4014                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4015                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4016                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4017                                 };
4018                                 map1 {
4019                                         trip = <&cpu1_alert1>;
4020                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4021                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4022                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4023                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4024                                 };
4025                         };
4026                 };
4027
4028                 cpu2-thermal {
4029                         polling-delay-passive = <250>;
4030                         polling-delay = <1000>;
4031
4032                         thermal-sensors = <&tsens0 3>;
4033
4034                         trips {
4035                                 cpu2_alert0: trip-point0 {
4036                                         temperature = <90000>;
4037                                         hysteresis = <2000>;
4038                                         type = "passive";
4039                                 };
4040
4041                                 cpu2_alert1: trip-point1 {
4042                                         temperature = <95000>;
4043                                         hysteresis = <2000>;
4044                                         type = "passive";
4045                                 };
4046
4047                                 cpu2_crit: cpu_crit {
4048                                         temperature = <110000>;
4049                                         hysteresis = <1000>;
4050                                         type = "critical";
4051                                 };
4052                         };
4053
4054                         cooling-maps {
4055                                 map0 {
4056                                         trip = <&cpu2_alert0>;
4057                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4058                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4059                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4060                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4061                                 };
4062                                 map1 {
4063                                         trip = <&cpu2_alert1>;
4064                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4065                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4066                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4067                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4068                                 };
4069                         };
4070                 };
4071
4072                 cpu3-thermal {
4073                         polling-delay-passive = <250>;
4074                         polling-delay = <1000>;
4075
4076                         thermal-sensors = <&tsens0 4>;
4077
4078                         trips {
4079                                 cpu3_alert0: trip-point0 {
4080                                         temperature = <90000>;
4081                                         hysteresis = <2000>;
4082                                         type = "passive";
4083                                 };
4084
4085                                 cpu3_alert1: trip-point1 {
4086                                         temperature = <95000>;
4087                                         hysteresis = <2000>;
4088                                         type = "passive";
4089                                 };
4090
4091                                 cpu3_crit: cpu_crit {
4092                                         temperature = <110000>;
4093                                         hysteresis = <1000>;
4094                                         type = "critical";
4095                                 };
4096                         };
4097
4098                         cooling-maps {
4099                                 map0 {
4100                                         trip = <&cpu3_alert0>;
4101                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4102                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4103                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4104                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4105                                 };
4106                                 map1 {
4107                                         trip = <&cpu3_alert1>;
4108                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4109                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4110                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4111                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4112                                 };
4113                         };
4114                 };
4115
4116                 cpu4-thermal {
4117                         polling-delay-passive = <250>;
4118                         polling-delay = <1000>;
4119
4120                         thermal-sensors = <&tsens0 7>;
4121
4122                         trips {
4123                                 cpu4_alert0: trip-point0 {
4124                                         temperature = <90000>;
4125                                         hysteresis = <2000>;
4126                                         type = "passive";
4127                                 };
4128
4129                                 cpu4_alert1: trip-point1 {
4130                                         temperature = <95000>;
4131                                         hysteresis = <2000>;
4132                                         type = "passive";
4133                                 };
4134
4135                                 cpu4_crit: cpu_crit {
4136                                         temperature = <110000>;
4137                                         hysteresis = <1000>;
4138                                         type = "critical";
4139                                 };
4140                         };
4141
4142                         cooling-maps {
4143                                 map0 {
4144                                         trip = <&cpu4_alert0>;
4145                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4146                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4147                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4148                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4149                                 };
4150                                 map1 {
4151                                         trip = <&cpu4_alert1>;
4152                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4153                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4154                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4155                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4156                                 };
4157                         };
4158                 };
4159
4160                 cpu5-thermal {
4161                         polling-delay-passive = <250>;
4162                         polling-delay = <1000>;
4163
4164                         thermal-sensors = <&tsens0 8>;
4165
4166                         trips {
4167                                 cpu5_alert0: trip-point0 {
4168                                         temperature = <90000>;
4169                                         hysteresis = <2000>;
4170                                         type = "passive";
4171                                 };
4172
4173                                 cpu5_alert1: trip-point1 {
4174                                         temperature = <95000>;
4175                                         hysteresis = <2000>;
4176                                         type = "passive";
4177                                 };
4178
4179                                 cpu5_crit: cpu_crit {
4180                                         temperature = <110000>;
4181                                         hysteresis = <1000>;
4182                                         type = "critical";
4183                                 };
4184                         };
4185
4186                         cooling-maps {
4187                                 map0 {
4188                                         trip = <&cpu5_alert0>;
4189                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4190                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4191                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4192                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4193                                 };
4194                                 map1 {
4195                                         trip = <&cpu5_alert1>;
4196                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4197                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4198                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4199                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4200                                 };
4201                         };
4202                 };
4203
4204                 cpu6-thermal {
4205                         polling-delay-passive = <250>;
4206                         polling-delay = <1000>;
4207
4208                         thermal-sensors = <&tsens0 9>;
4209
4210                         trips {
4211                                 cpu6_alert0: trip-point0 {
4212                                         temperature = <90000>;
4213                                         hysteresis = <2000>;
4214                                         type = "passive";
4215                                 };
4216
4217                                 cpu6_alert1: trip-point1 {
4218                                         temperature = <95000>;
4219                                         hysteresis = <2000>;
4220                                         type = "passive";
4221                                 };
4222
4223                                 cpu6_crit: cpu_crit {
4224                                         temperature = <110000>;
4225                                         hysteresis = <1000>;
4226                                         type = "critical";
4227                                 };
4228                         };
4229
4230                         cooling-maps {
4231                                 map0 {
4232                                         trip = <&cpu6_alert0>;
4233                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4234                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4235                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4236                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4237                                 };
4238                                 map1 {
4239                                         trip = <&cpu6_alert1>;
4240                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4241                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4242                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4243                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4244                                 };
4245                         };
4246                 };
4247
4248                 cpu7-thermal {
4249                         polling-delay-passive = <250>;
4250                         polling-delay = <1000>;
4251
4252                         thermal-sensors = <&tsens0 10>;
4253
4254                         trips {
4255                                 cpu7_alert0: trip-point0 {
4256                                         temperature = <90000>;
4257                                         hysteresis = <2000>;
4258                                         type = "passive";
4259                                 };
4260
4261                                 cpu7_alert1: trip-point1 {
4262                                         temperature = <95000>;
4263                                         hysteresis = <2000>;
4264                                         type = "passive";
4265                                 };
4266
4267                                 cpu7_crit: cpu_crit {
4268                                         temperature = <110000>;
4269                                         hysteresis = <1000>;
4270                                         type = "critical";
4271                                 };
4272                         };
4273
4274                         cooling-maps {
4275                                 map0 {
4276                                         trip = <&cpu7_alert0>;
4277                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4278                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4279                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4280                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4281                                 };
4282                                 map1 {
4283                                         trip = <&cpu7_alert1>;
4284                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4285                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4286                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4287                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4288                                 };
4289                         };
4290                 };
4291
4292                 aoss0-thermal {
4293                         polling-delay-passive = <250>;
4294                         polling-delay = <1000>;
4295
4296                         thermal-sensors = <&tsens0 0>;
4297
4298                         trips {
4299                                 aoss0_alert0: trip-point0 {
4300                                         temperature = <90000>;
4301                                         hysteresis = <2000>;
4302                                         type = "hot";
4303                                 };
4304                         };
4305                 };
4306
4307                 cluster0-thermal {
4308                         polling-delay-passive = <250>;
4309                         polling-delay = <1000>;
4310
4311                         thermal-sensors = <&tsens0 5>;
4312
4313                         trips {
4314                                 cluster0_alert0: trip-point0 {
4315                                         temperature = <90000>;
4316                                         hysteresis = <2000>;
4317                                         type = "hot";
4318                                 };
4319                                 cluster0_crit: cluster0_crit {
4320                                         temperature = <110000>;
4321                                         hysteresis = <2000>;
4322                                         type = "critical";
4323                                 };
4324                         };
4325                 };
4326
4327                 cluster1-thermal {
4328                         polling-delay-passive = <250>;
4329                         polling-delay = <1000>;
4330
4331                         thermal-sensors = <&tsens0 6>;
4332
4333                         trips {
4334                                 cluster1_alert0: trip-point0 {
4335                                         temperature = <90000>;
4336                                         hysteresis = <2000>;
4337                                         type = "hot";
4338                                 };
4339                                 cluster1_crit: cluster1_crit {
4340                                         temperature = <110000>;
4341                                         hysteresis = <2000>;
4342                                         type = "critical";
4343                                 };
4344                         };
4345                 };
4346
4347                 gpu-thermal-top {
4348                         polling-delay-passive = <250>;
4349                         polling-delay = <1000>;
4350
4351                         thermal-sensors = <&tsens0 11>;
4352
4353                         trips {
4354                                 gpu1_alert0: trip-point0 {
4355                                         temperature = <90000>;
4356                                         hysteresis = <2000>;
4357                                         type = "hot";
4358                                 };
4359                         };
4360                 };
4361
4362                 gpu-thermal-bottom {
4363                         polling-delay-passive = <250>;
4364                         polling-delay = <1000>;
4365
4366                         thermal-sensors = <&tsens0 12>;
4367
4368                         trips {
4369                                 gpu2_alert0: trip-point0 {
4370                                         temperature = <90000>;
4371                                         hysteresis = <2000>;
4372                                         type = "hot";
4373                                 };
4374                         };
4375                 };
4376
4377                 aoss1-thermal {
4378                         polling-delay-passive = <250>;
4379                         polling-delay = <1000>;
4380
4381                         thermal-sensors = <&tsens1 0>;
4382
4383                         trips {
4384                                 aoss1_alert0: trip-point0 {
4385                                         temperature = <90000>;
4386                                         hysteresis = <2000>;
4387                                         type = "hot";
4388                                 };
4389                         };
4390                 };
4391
4392                 q6-modem-thermal {
4393                         polling-delay-passive = <250>;
4394                         polling-delay = <1000>;
4395
4396                         thermal-sensors = <&tsens1 1>;
4397
4398                         trips {
4399                                 q6_modem_alert0: trip-point0 {
4400                                         temperature = <90000>;
4401                                         hysteresis = <2000>;
4402                                         type = "hot";
4403                                 };
4404                         };
4405                 };
4406
4407                 mem-thermal {
4408                         polling-delay-passive = <250>;
4409                         polling-delay = <1000>;
4410
4411                         thermal-sensors = <&tsens1 2>;
4412
4413                         trips {
4414                                 mem_alert0: trip-point0 {
4415                                         temperature = <90000>;
4416                                         hysteresis = <2000>;
4417                                         type = "hot";
4418                                 };
4419                         };
4420                 };
4421
4422                 wlan-thermal {
4423                         polling-delay-passive = <250>;
4424                         polling-delay = <1000>;
4425
4426                         thermal-sensors = <&tsens1 3>;
4427
4428                         trips {
4429                                 wlan_alert0: trip-point0 {
4430                                         temperature = <90000>;
4431                                         hysteresis = <2000>;
4432                                         type = "hot";
4433                                 };
4434                         };
4435                 };
4436
4437                 q6-hvx-thermal {
4438                         polling-delay-passive = <250>;
4439                         polling-delay = <1000>;
4440
4441                         thermal-sensors = <&tsens1 4>;
4442
4443                         trips {
4444                                 q6_hvx_alert0: trip-point0 {
4445                                         temperature = <90000>;
4446                                         hysteresis = <2000>;
4447                                         type = "hot";
4448                                 };
4449                         };
4450                 };
4451
4452                 camera-thermal {
4453                         polling-delay-passive = <250>;
4454                         polling-delay = <1000>;
4455
4456                         thermal-sensors = <&tsens1 5>;
4457
4458                         trips {
4459                                 camera_alert0: trip-point0 {
4460                                         temperature = <90000>;
4461                                         hysteresis = <2000>;
4462                                         type = "hot";
4463                                 };
4464                         };
4465                 };
4466
4467                 video-thermal {
4468                         polling-delay-passive = <250>;
4469                         polling-delay = <1000>;
4470
4471                         thermal-sensors = <&tsens1 6>;
4472
4473                         trips {
4474                                 video_alert0: trip-point0 {
4475                                         temperature = <90000>;
4476                                         hysteresis = <2000>;
4477                                         type = "hot";
4478                                 };
4479                         };
4480                 };
4481
4482                 modem-thermal {
4483                         polling-delay-passive = <250>;
4484                         polling-delay = <1000>;
4485
4486                         thermal-sensors = <&tsens1 7>;
4487
4488                         trips {
4489                                 modem_alert0: trip-point0 {
4490                                         temperature = <90000>;
4491                                         hysteresis = <2000>;
4492                                         type = "hot";
4493                                 };
4494                         };
4495                 };
4496         };
4497 };