2 * Copyright (c) 2014 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3188_COMMON_H
17 #define _DT_BINDINGS_CLK_ROCKCHIP_RK3188_COMMON_H
19 /* core clocks from */
28 /* sclk gates (special clocks) */
36 #define SCLK_SARADC 71
46 #define SCLK_OTGPHY0 81
47 #define SCLK_OTGPHY1 82
49 #define SCLK_TIMER0 84
50 #define SCLK_TIMER1 85
51 #define SCLK_TIMER2 86
52 #define SCLK_TIMER3 87
53 #define SCLK_TIMER4 88
54 #define SCLK_TIMER5 89
55 #define SCLK_TIMER6 90
60 #define DCLK_LCDC0 190
61 #define DCLK_LCDC1 191
67 #define ACLK_LCDC0 195
68 #define ACLK_LCDC1 196
83 #define PCLK_TIMER0 322
84 #define PCLK_TIMER1 323
85 #define PCLK_TIMER2 324
86 #define PCLK_TIMER3 325
87 #define PCLK_PWM01 326
88 #define PCLK_PWM23 327
91 #define PCLK_SARADC 330
93 #define PCLK_UART0 332
94 #define PCLK_UART1 333
95 #define PCLK_UART2 334
96 #define PCLK_UART3 335
100 #define PCLK_I2C3 339
101 #define PCLK_I2C4 340
102 #define PCLK_GPIO0 341
103 #define PCLK_GPIO1 342
104 #define PCLK_GPIO2 343
105 #define PCLK_GPIO3 344
106 #define PCLK_GPIO4 345
107 #define PCLK_GPIO6 346
108 #define PCLK_EFUSE 347
109 #define PCLK_TZPC 348
110 #define PCLK_TSADC 349
112 #define PCLK_PERI 351
113 #define PCLK_DDRUPCTL 352
114 #define PCLK_PUBL 353
117 #define HCLK_SDMMC 448
118 #define HCLK_SDIO 449
119 #define HCLK_EMMC 450
120 #define HCLK_OTG0 451
121 #define HCLK_EMAC 452
122 #define HCLK_SPDIF 453
123 #define HCLK_I2S0 454
124 #define HCLK_I2S1 455
125 #define HCLK_I2S2 456
126 #define HCLK_OTG1 457
127 #define HCLK_HSIC 458
128 #define HCLK_HSADC 459
129 #define HCLK_PIDF 460
130 #define HCLK_LCDC0 461
131 #define HCLK_LCDC1 462
133 #define HCLK_CIF0 464
136 #define HCLK_NANDC0 467
138 #define HCLK_PERI 469
139 #define HCLK_CIF1 470
140 #define HCLK_VEPU 471
141 #define HCLK_VDPU 472
142 #define HCLK_HDMI 473
144 #define CLK_NR_CLKS (HCLK_HDMI + 1)
146 /* soft-reset indices */
150 #define SRST_MCORE_DBG 7
151 #define SRST_CORE0_DBG 8
152 #define SRST_CORE1_DBG 9
153 #define SRST_CORE0_WDT 12
154 #define SRST_CORE1_WDT 13
155 #define SRST_STRC_SYS 14
158 #define SRST_CPU_AHB 17
159 #define SRST_AHB2APB 19
161 #define SRST_INTMEM 21
163 #define SRST_SPDIF 26
164 #define SRST_TIMER0 27
165 #define SRST_TIMER1 28
166 #define SRST_EFUSE 30
168 #define SRST_GPIO0 32
169 #define SRST_GPIO1 33
170 #define SRST_GPIO2 34
171 #define SRST_GPIO3 35
173 #define SRST_UART0 39
174 #define SRST_UART1 40
175 #define SRST_UART2 41
176 #define SRST_UART3 42
185 #define SRST_DAP_PO 50
187 #define SRST_DAP_SYS 52
188 #define SRST_TPIU_ATB 53
189 #define SRST_PMU_APB 54
192 #define SRST_PERI_AXI 57
193 #define SRST_PERI_AHB 58
194 #define SRST_PERI_APB 59
195 #define SRST_PERI_NIU 60
196 #define SRST_CPU_PERI 61
197 #define SRST_EMEM_PERI 62
198 #define SRST_USB_PERI 63
203 #define SRST_NANC0 68
204 #define SRST_USBOTG0 69
205 #define SRST_USBPHY0 70
206 #define SRST_OTGC0 71
207 #define SRST_USBOTG1 72
208 #define SRST_USBPHY1 73
209 #define SRST_OTGC1 74
210 #define SRST_HSADC 76
211 #define SRST_PIDFILTER 77
212 #define SRST_DDR_MSCH 79
215 #define SRST_SDMMC 81
221 #define SRST_SARADC 87
222 #define SRST_DDRPHY 88
223 #define SRST_DDRPHY_APB 89
224 #define SRST_DDRCTL 90
225 #define SRST_DDRCTL_APB 91
226 #define SRST_DDRPUB 93
228 #define SRST_VIO0_AXI 98
229 #define SRST_VIO0_AHB 99
230 #define SRST_LCDC0_AXI 100
231 #define SRST_LCDC0_AHB 101
232 #define SRST_LCDC0_DCLK 102
233 #define SRST_LCDC1_AXI 103
234 #define SRST_LCDC1_AHB 104
235 #define SRST_LCDC1_DCLK 105
236 #define SRST_IPP_AXI 106
237 #define SRST_IPP_AHB 107
238 #define SRST_RGA_AXI 108
239 #define SRST_RGA_AHB 109
240 #define SRST_CIF0 110
242 #define SRST_VCODEC_AXI 112
243 #define SRST_VCODEC_AHB 113
244 #define SRST_VIO1_AXI 114
245 #define SRST_VCODEC_CPU 115
246 #define SRST_VCODEC_NIU 116
248 #define SRST_GPU_NIU 122
249 #define SRST_TFUN_ATB 125
250 #define SRST_TFUN_APB 126
251 #define SRST_CTI4_APB 127
253 #define SRST_TPIU_APB 128
254 #define SRST_TRACE 129
255 #define SRST_CORE_DBG 130
256 #define SRST_DBG_APB 131
257 #define SRST_CTI0 132
258 #define SRST_CTI0_APB 133
259 #define SRST_CTI1 134
260 #define SRST_CTI1_APB 135
261 #define SRST_PTM_CORE0 136
262 #define SRST_PTM_CORE1 137
263 #define SRST_PTM0 138
264 #define SRST_PTM0_ATB 139
265 #define SRST_PTM1 140
266 #define SRST_PTM1_ATB 141