sys/i386/i386/initcpu.c

   1 /*-
   2  * Copyright (c) KATO Takenori, 1997, 1998.
   3  *
   4  * All rights reserved.  Unpublished rights reserved under the copyright
   5  * laws of Japan.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  *
  11  * 1. Redistributions of source code must retain the above copyright
  12  *    notice, this list of conditions and the following disclaimer as
  13  *    the first lines of this file unmodified.
  14  * 2. Redistributions in binary form must reproduce the above copyright
  15  *    notice, this list of conditions and the following disclaimer in the
  16  *    documentation and/or other materials provided with the distribution.
  17  *
  18  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  19  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  20  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  21  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  22  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  23  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  27  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28  */
  29
  30 #include <sys/cdefs.h>
  31 __FBSDID("$FreeBSD$");
  32
  33 #include "opt_cpu.h"
  34
  35 #include <sys/param.h>
  36 #include <sys/kernel.h>
  37 #include <sys/systm.h>
  38 #include <sys/sysctl.h>
  39
  40 #include <machine/cputypes.h>
  41 #include <machine/md_var.h>
  42 #include <machine/specialreg.h>
  43
  44 #include <vm/vm.h>
  45 #include <vm/pmap.h>
  46
  47 #ifdef I486_CPU
  48 static void init_5x86(void);
  49 static void init_bluelightning(void);
  50 static void init_486dlc(void);
  51 static void init_cy486dx(void);
  52 #ifdef CPU_I486_ON_386
  53 static void init_i486_on_386(void);
  54 #endif
  55 static void init_6x86(void);
  56 #endif /* I486_CPU */
  57
  58 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
  59 static void     enable_K5_wt_alloc(void);
  60 static void     enable_K6_wt_alloc(void);
  61 static void     enable_K6_2_wt_alloc(void);
  62 #endif
  63
  64 #ifdef I686_CPU
  65 static void     init_6x86MX(void);
  66 static void     init_ppro(void);
  67 static void     init_mendocino(void);
  68 #endif
  69
  70 static int      hw_instruction_sse;
  71 SYSCTL_INT(_hw, OID_AUTO, instruction_sse, CTLFLAG_RD,
  72     &hw_instruction_sse, 0, "SIMD/MMX2 instructions available in CPU");
  73 /*
  74  * -1: automatic (default)
  75  *  0: keep enable CLFLUSH
  76  *  1: force disable CLFLUSH
  77  */
  78 static int      hw_clflush_disable = -1;
  79
  80 u_int   cyrix_did;              /* Device ID of Cyrix CPU */
  81
  82 #ifdef I486_CPU
  83 /*
  84  * IBM Blue Lightning
  85  */
  86 static void
  87 init_bluelightning(void)
  88 {
  89         register_t saveintr;
  90
  91 #if defined(PC98) && !defined(CPU_UPGRADE_HW_CACHE)
  92         need_post_dma_flush = 1;
  93 #endif
  94
  95         saveintr = intr_disable();
  96
  97         load_cr0(rcr0() | CR0_CD | CR0_NW);
  98         invd();
  99
 100 #ifdef CPU_BLUELIGHTNING_FPU_OP_CACHE
 101         wrmsr(0x1000, 0x9c92LL);        /* FP operand can be cacheable on Cyrix FPU */
 102 #else
 103         wrmsr(0x1000, 0x1c92LL);        /* Intel FPU */
 104 #endif
 105         /* Enables 13MB and 0-640KB cache. */
 106         wrmsr(0x1001, (0xd0LL << 32) | 0x3ff);
 107 #ifdef CPU_BLUELIGHTNING_3X
 108         wrmsr(0x1002, 0x04000000LL);    /* Enables triple-clock mode. */
 109 #else
 110         wrmsr(0x1002, 0x03000000LL);    /* Enables double-clock mode. */
 111 #endif
 112
 113         /* Enable caching in CR0. */
 114         load_cr0(rcr0() & ~(CR0_CD | CR0_NW));  /* CD = 0 and NW = 0 */
 115         invd();
 116         intr_restore(saveintr);
 117 }
 118
 119 /*
 120  * Cyrix 486SLC/DLC/SR/DR series
 121  */
 122 static void
 123 init_486dlc(void)
 124 {
 125         register_t saveintr;
 126         u_char  ccr0;
 127
 128         saveintr = intr_disable();
 129         invd();
 130
 131         ccr0 = read_cyrix_reg(CCR0);
 132 #ifndef CYRIX_CACHE_WORKS
 133         ccr0 |= CCR0_NC1 | CCR0_BARB;
 134         write_cyrix_reg(CCR0, ccr0);
 135         invd();
 136 #else
 137         ccr0 &= ~CCR0_NC0;
 138 #ifndef CYRIX_CACHE_REALLY_WORKS
 139         ccr0 |= CCR0_NC1 | CCR0_BARB;
 140 #else
 141         ccr0 |= CCR0_NC1;
 142 #endif
 143 #ifdef CPU_DIRECT_MAPPED_CACHE
 144         ccr0 |= CCR0_CO;                        /* Direct mapped mode. */
 145 #endif
 146         write_cyrix_reg(CCR0, ccr0);
 147
 148         /* Clear non-cacheable region. */
 149         write_cyrix_reg(NCR1+2, NCR_SIZE_0K);
 150         write_cyrix_reg(NCR2+2, NCR_SIZE_0K);
 151         write_cyrix_reg(NCR3+2, NCR_SIZE_0K);
 152         write_cyrix_reg(NCR4+2, NCR_SIZE_0K);
 153
 154         write_cyrix_reg(0, 0);  /* dummy write */
 155
 156         /* Enable caching in CR0. */
 157         load_cr0(rcr0() & ~(CR0_CD | CR0_NW));  /* CD = 0 and NW = 0 */
 158         invd();
 159 #endif /* !CYRIX_CACHE_WORKS */
 160         intr_restore(saveintr);
 161 }
 162
 163
 164 /*
 165  * Cyrix 486S/DX series
 166  */
 167 static void
 168 init_cy486dx(void)
 169 {
 170         register_t saveintr;
 171         u_char  ccr2;
 172
 173         saveintr = intr_disable();
 174         invd();
 175
 176         ccr2 = read_cyrix_reg(CCR2);
 177 #ifdef CPU_SUSP_HLT
 178         ccr2 |= CCR2_SUSP_HLT;
 179 #endif
 180
 181 #ifdef PC98
 182         /* Enables WB cache interface pin and Lock NW bit in CR0. */
 183         ccr2 |= CCR2_WB | CCR2_LOCK_NW;
 184         /* Unlock NW bit in CR0. */
 185         write_cyrix_reg(CCR2, ccr2 & ~CCR2_LOCK_NW);
 186         load_cr0((rcr0() & ~CR0_CD) | CR0_NW);  /* CD = 0, NW = 1 */
 187 #endif
 188
 189         write_cyrix_reg(CCR2, ccr2);
 190         intr_restore(saveintr);
 191 }
 192
 193
 194 /*
 195  * Cyrix 5x86
 196  */
 197 static void
 198 init_5x86(void)
 199 {
 200         register_t saveintr;
 201         u_char  ccr2, ccr3, ccr4, pcr0;
 202
 203         saveintr = intr_disable();
 204
 205         load_cr0(rcr0() | CR0_CD | CR0_NW);
 206         wbinvd();
 207
 208         (void)read_cyrix_reg(CCR3);             /* dummy */
 209
 210         /* Initialize CCR2. */
 211         ccr2 = read_cyrix_reg(CCR2);
 212         ccr2 |= CCR2_WB;
 213 #ifdef CPU_SUSP_HLT
 214         ccr2 |= CCR2_SUSP_HLT;
 215 #else
 216         ccr2 &= ~CCR2_SUSP_HLT;
 217 #endif
 218         ccr2 |= CCR2_WT1;
 219         write_cyrix_reg(CCR2, ccr2);
 220
 221         /* Initialize CCR4. */
 222         ccr3 = read_cyrix_reg(CCR3);
 223         write_cyrix_reg(CCR3, CCR3_MAPEN0);
 224
 225         ccr4 = read_cyrix_reg(CCR4);
 226         ccr4 |= CCR4_DTE;
 227         ccr4 |= CCR4_MEM;
 228 #ifdef CPU_FASTER_5X86_FPU
 229         ccr4 |= CCR4_FASTFPE;
 230 #else
 231         ccr4 &= ~CCR4_FASTFPE;
 232 #endif
 233         ccr4 &= ~CCR4_IOMASK;
 234         /********************************************************************
 235          * WARNING: The "BIOS Writers Guide" mentions that I/O recovery time
 236          * should be 0 for errata fix.
 237          ********************************************************************/
 238 #ifdef CPU_IORT
 239         ccr4 |= CPU_IORT & CCR4_IOMASK;
 240 #endif
 241         write_cyrix_reg(CCR4, ccr4);
 242
 243         /* Initialize PCR0. */
 244         /****************************************************************
 245          * WARNING: RSTK_EN and LOOP_EN could make your system unstable.
 246          * BTB_EN might make your system unstable.
 247          ****************************************************************/
 248         pcr0 = read_cyrix_reg(PCR0);
 249 #ifdef CPU_RSTK_EN
 250         pcr0 |= PCR0_RSTK;
 251 #else
 252         pcr0 &= ~PCR0_RSTK;
 253 #endif
 254 #ifdef CPU_BTB_EN
 255         pcr0 |= PCR0_BTB;
 256 #else
 257         pcr0 &= ~PCR0_BTB;
 258 #endif
 259 #ifdef CPU_LOOP_EN
 260         pcr0 |= PCR0_LOOP;
 261 #else
 262         pcr0 &= ~PCR0_LOOP;
 263 #endif
 264
 265         /****************************************************************
 266          * WARNING: if you use a memory mapped I/O device, don't use
 267          * DISABLE_5X86_LSSER option, which may reorder memory mapped
 268          * I/O access.
 269          * IF YOUR MOTHERBOARD HAS PCI BUS, DON'T DISABLE LSSER.
 270          ****************************************************************/
 271 #ifdef CPU_DISABLE_5X86_LSSER
 272         pcr0 &= ~PCR0_LSSER;
 273 #else
 274         pcr0 |= PCR0_LSSER;
 275 #endif
 276         write_cyrix_reg(PCR0, pcr0);
 277
 278         /* Restore CCR3. */
 279         write_cyrix_reg(CCR3, ccr3);
 280
 281         (void)read_cyrix_reg(0x80);             /* dummy */
 282
 283         /* Unlock NW bit in CR0. */
 284         write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW);
 285         load_cr0((rcr0() & ~CR0_CD) | CR0_NW);  /* CD = 0, NW = 1 */
 286         /* Lock NW bit in CR0. */
 287         write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW);
 288
 289         intr_restore(saveintr);
 290 }
 291
 292 #ifdef CPU_I486_ON_386
 293 /*
 294  * There are i486 based upgrade products for i386 machines.
 295  * In this case, BIOS doesn't enable CPU cache.
 296  */
 297 static void
 298 init_i486_on_386(void)
 299 {
 300         register_t saveintr;
 301
 302 #if defined(PC98) && !defined(CPU_UPGRADE_HW_CACHE)
 303         need_post_dma_flush = 1;
 304 #endif
 305
 306         saveintr = intr_disable();
 307
 308         load_cr0(rcr0() & ~(CR0_CD | CR0_NW));  /* CD = 0, NW = 0 */
 309
 310         intr_restore(saveintr);
 311 }
 312 #endif
 313
 314 /*
 315  * Cyrix 6x86
 316  *
 317  * XXX - What should I do here?  Please let me know.
 318  */
 319 static void
 320 init_6x86(void)
 321 {
 322         register_t saveintr;
 323         u_char  ccr3, ccr4;
 324
 325         saveintr = intr_disable();
 326
 327         load_cr0(rcr0() | CR0_CD | CR0_NW);
 328         wbinvd();
 329
 330         /* Initialize CCR0. */
 331         write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) | CCR0_NC1);
 332
 333         /* Initialize CCR1. */
 334 #ifdef CPU_CYRIX_NO_LOCK
 335         write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) | CCR1_NO_LOCK);
 336 #else
 337         write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) & ~CCR1_NO_LOCK);
 338 #endif
 339
 340         /* Initialize CCR2. */
 341 #ifdef CPU_SUSP_HLT
 342         write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_SUSP_HLT);
 343 #else
 344         write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_SUSP_HLT);
 345 #endif
 346
 347         ccr3 = read_cyrix_reg(CCR3);
 348         write_cyrix_reg(CCR3, CCR3_MAPEN0);
 349
 350         /* Initialize CCR4. */
 351         ccr4 = read_cyrix_reg(CCR4);
 352         ccr4 |= CCR4_DTE;
 353         ccr4 &= ~CCR4_IOMASK;
 354 #ifdef CPU_IORT
 355         write_cyrix_reg(CCR4, ccr4 | (CPU_IORT & CCR4_IOMASK));
 356 #else
 357         write_cyrix_reg(CCR4, ccr4 | 7);
 358 #endif
 359
 360         /* Initialize CCR5. */
 361 #ifdef CPU_WT_ALLOC
 362         write_cyrix_reg(CCR5, read_cyrix_reg(CCR5) | CCR5_WT_ALLOC);
 363 #endif
 364
 365         /* Restore CCR3. */
 366         write_cyrix_reg(CCR3, ccr3);
 367
 368         /* Unlock NW bit in CR0. */
 369         write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW);
 370
 371         /*
 372          * Earlier revision of the 6x86 CPU could crash the system if
 373          * L1 cache is in write-back mode.
 374          */
 375         if ((cyrix_did & 0xff00) > 0x1600)
 376                 load_cr0(rcr0() & ~(CR0_CD | CR0_NW));  /* CD = 0 and NW = 0 */
 377         else {
 378                 /* Revision 2.6 and lower. */
 379 #ifdef CYRIX_CACHE_REALLY_WORKS
 380                 load_cr0(rcr0() & ~(CR0_CD | CR0_NW));  /* CD = 0 and NW = 0 */
 381 #else
 382                 load_cr0((rcr0() & ~CR0_CD) | CR0_NW);  /* CD = 0 and NW = 1 */
 383 #endif
 384         }
 385
 386         /* Lock NW bit in CR0. */
 387         write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW);
 388
 389         intr_restore(saveintr);
 390 }
 391 #endif /* I486_CPU */
 392
 393 #ifdef I586_CPU
 394 /*
 395  * Rise mP6
 396  */
 397 static void
 398 init_rise(void)
 399 {
 400
 401         /*
 402          * The CMPXCHG8B instruction is always available but hidden.
 403          */
 404         cpu_feature |= CPUID_CX8;
 405 }
 406
 407 /*
 408  * IDT WinChip C6/2/2A/2B/3
 409  *
 410  * http://www.centtech.com/winchip_bios_writers_guide_v4_0.pdf
 411  */
 412 static void
 413 init_winchip(void)
 414 {
 415         u_int regs[4];
 416         uint64_t fcr;
 417
 418         fcr = rdmsr(0x0107);
 419
 420         /*
 421          * Set ECX8, DSMC, DTLOCK/EDCTLB, EMMX, and ERETSTK and clear DPDC.
 422          */
 423         fcr |= (1 << 1) | (1 << 7) | (1 << 8) | (1 << 9) | (1 << 16);
 424         fcr &= ~(1ULL << 11);
 425
 426         /*
 427          * Additionally, set EBRPRED, E2MMX and EAMD3D for WinChip 2 and 3.
 428          */
 429         if (CPUID_TO_MODEL(cpu_id) >= 8)
 430                 fcr |= (1 << 12) | (1 << 19) | (1 << 20);
 431
 432         wrmsr(0x0107, fcr);
 433         do_cpuid(1, regs);
 434         cpu_feature = regs[3];
 435 }
 436 #endif
 437
 438 #ifdef I686_CPU
 439 /*
 440  * Cyrix 6x86MX (code-named M2)
 441  *
 442  * XXX - What should I do here?  Please let me know.
 443  */
 444 static void
 445 init_6x86MX(void)
 446 {
 447         register_t saveintr;
 448         u_char  ccr3, ccr4;
 449
 450         saveintr = intr_disable();
 451
 452         load_cr0(rcr0() | CR0_CD | CR0_NW);
 453         wbinvd();
 454
 455         /* Initialize CCR0. */
 456         write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) | CCR0_NC1);
 457
 458         /* Initialize CCR1. */
 459 #ifdef CPU_CYRIX_NO_LOCK
 460         write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) | CCR1_NO_LOCK);
 461 #else
 462         write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) & ~CCR1_NO_LOCK);
 463 #endif
 464
 465         /* Initialize CCR2. */
 466 #ifdef CPU_SUSP_HLT
 467         write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_SUSP_HLT);
 468 #else
 469         write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_SUSP_HLT);
 470 #endif
 471
 472         ccr3 = read_cyrix_reg(CCR3);
 473         write_cyrix_reg(CCR3, CCR3_MAPEN0);
 474
 475         /* Initialize CCR4. */
 476         ccr4 = read_cyrix_reg(CCR4);
 477         ccr4 &= ~CCR4_IOMASK;
 478 #ifdef CPU_IORT
 479         write_cyrix_reg(CCR4, ccr4 | (CPU_IORT & CCR4_IOMASK));
 480 #else
 481         write_cyrix_reg(CCR4, ccr4 | 7);
 482 #endif
 483
 484         /* Initialize CCR5. */
 485 #ifdef CPU_WT_ALLOC
 486         write_cyrix_reg(CCR5, read_cyrix_reg(CCR5) | CCR5_WT_ALLOC);
 487 #endif
 488
 489         /* Restore CCR3. */
 490         write_cyrix_reg(CCR3, ccr3);
 491
 492         /* Unlock NW bit in CR0. */
 493         write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW);
 494
 495         load_cr0(rcr0() & ~(CR0_CD | CR0_NW));  /* CD = 0 and NW = 0 */
 496
 497         /* Lock NW bit in CR0. */
 498         write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW);
 499
 500         intr_restore(saveintr);
 501 }
 502
 503 static int ppro_apic_used = -1;
 504
 505 static void
 506 init_ppro(void)
 507 {
 508         u_int64_t       apicbase;
 509
 510         /*
 511          * Local APIC should be disabled if it is not going to be used.
 512          */
 513         if (ppro_apic_used != 1) {
 514                 apicbase = rdmsr(MSR_APICBASE);
 515                 apicbase &= ~APICBASE_ENABLED;
 516                 wrmsr(MSR_APICBASE, apicbase);
 517                 ppro_apic_used = 0;
 518         }
 519 }
 520
 521 /*
 522  * If the local APIC is going to be used after being disabled above,
 523  * re-enable it and don't disable it in the future.
 524  */
 525 void
 526 ppro_reenable_apic(void)
 527 {
 528         u_int64_t       apicbase;
 529
 530         if (ppro_apic_used == 0) {
 531                 apicbase = rdmsr(MSR_APICBASE);
 532                 apicbase |= APICBASE_ENABLED;
 533                 wrmsr(MSR_APICBASE, apicbase);
 534                 ppro_apic_used = 1;
 535         }
 536 }
 537
 538 /*
 539  * Initialize BBL_CR_CTL3 (Control register 3: used to configure the
 540  * L2 cache).
 541  */
 542 static void
 543 init_mendocino(void)
 544 {
 545 #ifdef CPU_PPRO2CELERON
 546         register_t      saveintr;
 547         u_int64_t       bbl_cr_ctl3;
 548
 549         saveintr = intr_disable();
 550
 551         load_cr0(rcr0() | CR0_CD | CR0_NW);
 552         wbinvd();
 553
 554         bbl_cr_ctl3 = rdmsr(MSR_BBL_CR_CTL3);
 555
 556         /* If the L2 cache is configured, do nothing. */
 557         if (!(bbl_cr_ctl3 & 1)) {
 558                 bbl_cr_ctl3 = 0x134052bLL;
 559
 560                 /* Set L2 Cache Latency (Default: 5). */
 561 #ifdef  CPU_CELERON_L2_LATENCY
 562 #if CPU_L2_LATENCY > 15
 563 #error invalid CPU_L2_LATENCY.
 564 #endif
 565                 bbl_cr_ctl3 |= CPU_L2_LATENCY << 1;
 566 #else
 567                 bbl_cr_ctl3 |= 5 << 1;
 568 #endif
 569                 wrmsr(MSR_BBL_CR_CTL3, bbl_cr_ctl3);
 570         }
 571
 572         load_cr0(rcr0() & ~(CR0_CD | CR0_NW));
 573         intr_restore(saveintr);
 574 #endif /* CPU_PPRO2CELERON */
 575 }
 576
 577 /*
 578  * Initialize special VIA features
 579  */
 580 static void
 581 init_via(void)
 582 {
 583         u_int regs[4], val;
 584         uint64_t fcr;
 585
 586         /*
 587          * Explicitly enable CX8 and PGE on C3.
 588          *
 589          * http://www.via.com.tw/download/mainboards/6/13/VIA_C3_EBGA%20datasheet110.pdf
 590          */
 591         if (CPUID_TO_MODEL(cpu_id) <= 9)
 592                 fcr = (1 << 1) | (1 << 7);
 593         else
 594                 fcr = 0;
 595
 596         /*
 597          * Check extended CPUID for PadLock features.
 598          *
 599          * http://www.via.com.tw/en/downloads/whitepapers/initiatives/padlock/programming_guide.pdf
 600          */
 601         do_cpuid(0xc0000000, regs);
 602         if (regs[0] >= 0xc0000001) {
 603                 do_cpuid(0xc0000001, regs);
 604                 val = regs[3];
 605         } else
 606                 val = 0;
 607
 608         /* Enable RNG if present. */
 609         if ((val & VIA_CPUID_HAS_RNG) != 0) {
 610                 via_feature_rng = VIA_HAS_RNG;
 611                 wrmsr(0x110B, rdmsr(0x110B) | VIA_CPUID_DO_RNG);
 612         }
 613
 614         /* Enable PadLock if present. */
 615         if ((val & VIA_CPUID_HAS_ACE) != 0)
 616                 via_feature_xcrypt |= VIA_HAS_AES;
 617         if ((val & VIA_CPUID_HAS_ACE2) != 0)
 618                 via_feature_xcrypt |= VIA_HAS_AESCTR;
 619         if ((val & VIA_CPUID_HAS_PHE) != 0)
 620                 via_feature_xcrypt |= VIA_HAS_SHA;
 621         if ((val & VIA_CPUID_HAS_PMM) != 0)
 622                 via_feature_xcrypt |= VIA_HAS_MM;
 623         if (via_feature_xcrypt != 0)
 624                 fcr |= 1 << 28;
 625
 626         wrmsr(0x1107, rdmsr(0x1107) | fcr);
 627 }
 628
 629 #endif /* I686_CPU */
 630
 631 #if defined(I586_CPU) || defined(I686_CPU)
 632 static void
 633 init_transmeta(void)
 634 {
 635         u_int regs[0];
 636
 637         /* Expose all hidden features. */
 638         wrmsr(0x80860004, rdmsr(0x80860004) | ~0UL);
 639         do_cpuid(1, regs);
 640         cpu_feature = regs[3];
 641 }
 642 #endif
 643
 644 extern int elf32_nxstack;
 645
 646 void
 647 initializecpu(void)
 648 {
 649
 650         switch (cpu) {
 651 #ifdef I486_CPU
 652         case CPU_BLUE:
 653                 init_bluelightning();
 654                 break;
 655         case CPU_486DLC:
 656                 init_486dlc();
 657                 break;
 658         case CPU_CY486DX:
 659                 init_cy486dx();
 660                 break;
 661         case CPU_M1SC:
 662                 init_5x86();
 663                 break;
 664 #ifdef CPU_I486_ON_386
 665         case CPU_486:
 666                 init_i486_on_386();
 667                 break;
 668 #endif
 669         case CPU_M1:
 670                 init_6x86();
 671                 break;
 672 #endif /* I486_CPU */
 673 #ifdef I586_CPU
 674         case CPU_586:
 675                 switch (cpu_vendor_id) {
 676                 case CPU_VENDOR_AMD:
 677 #ifdef CPU_WT_ALLOC
 678                         if (((cpu_id & 0x0f0) > 0) &&
 679                             ((cpu_id & 0x0f0) < 0x60) &&
 680                             ((cpu_id & 0x00f) > 3))
 681                                 enable_K5_wt_alloc();
 682                         else if (((cpu_id & 0x0f0) > 0x80) ||
 683                             (((cpu_id & 0x0f0) == 0x80) &&
 684                                 (cpu_id & 0x00f) > 0x07))
 685                                 enable_K6_2_wt_alloc();
 686                         else if ((cpu_id & 0x0f0) > 0x50)
 687                                 enable_K6_wt_alloc();
 688 #endif
 689                         if ((cpu_id & 0xf0) == 0xa0)
 690                                 /*
 691                                  * Make sure the TSC runs through
 692                                  * suspension, otherwise we can't use
 693                                  * it as timecounter
 694                                  */
 695                                 wrmsr(0x1900, rdmsr(0x1900) | 0x20ULL);
 696                         break;
 697                 case CPU_VENDOR_CENTAUR:
 698                         init_winchip();
 699                         break;
 700                 case CPU_VENDOR_TRANSMETA:
 701                         init_transmeta();
 702                         break;
 703                 case CPU_VENDOR_RISE:
 704                         init_rise();
 705                         break;
 706                 }
 707                 break;
 708 #endif
 709 #ifdef I686_CPU
 710         case CPU_M2:
 711                 init_6x86MX();
 712                 break;
 713         case CPU_686:
 714                 switch (cpu_vendor_id) {
 715                 case CPU_VENDOR_INTEL:
 716                         switch (cpu_id & 0xff0) {
 717                         case 0x610:
 718                                 init_ppro();
 719                                 break;
 720                         case 0x660:
 721                                 init_mendocino();
 722                                 break;
 723                         }
 724                         break;
 725 #ifdef CPU_ATHLON_SSE_HACK
 726                 case CPU_VENDOR_AMD:
 727                         /*
 728                          * Sometimes the BIOS doesn't enable SSE instructions.
 729                          * According to AMD document 20734, the mobile
 730                          * Duron, the (mobile) Athlon 4 and the Athlon MP
 731                          * support SSE. These correspond to cpu_id 0x66X
 732                          * or 0x67X.
 733                          */
 734                         if ((cpu_feature & CPUID_XMM) == 0 &&
 735                             ((cpu_id & ~0xf) == 0x660 ||
 736                              (cpu_id & ~0xf) == 0x670 ||
 737                              (cpu_id & ~0xf) == 0x680)) {
 738                                 u_int regs[4];
 739                                 wrmsr(MSR_HWCR, rdmsr(MSR_HWCR) & ~0x08000);
 740                                 do_cpuid(1, regs);
 741                                 cpu_feature = regs[3];
 742                         }
 743                         break;
 744 #endif
 745                 case CPU_VENDOR_CENTAUR:
 746                         init_via();
 747                         break;
 748                 case CPU_VENDOR_TRANSMETA:
 749                         init_transmeta();
 750                         break;
 751                 }
 752                 break;
 753 #endif
 754         default:
 755                 break;
 756         }
 757         if ((cpu_feature & CPUID_XMM) && (cpu_feature & CPUID_FXSR)) {
 758                 load_cr4(rcr4() | CR4_FXSR | CR4_XMM);
 759                 cpu_fxsr = hw_instruction_sse = 1;
 760         }
 761 #if defined(PAE) || defined(PAE_TABLES)
 762         if ((amd_feature & AMDID_NX) != 0) {
 763                 uint64_t msr;
 764
 765                 msr = rdmsr(MSR_EFER) | EFER_NXE;
 766                 wrmsr(MSR_EFER, msr);
 767                 pg_nx = PG_NX;
 768                 elf32_nxstack = 1;
 769         }
 770 #endif
 771         hw_mds_recalculate();
 772 }
 773
 774 void
 775 initializecpucache(void)
 776 {
 777
 778         /*
 779          * CPUID with %eax = 1, %ebx returns
 780          * Bits 15-8: CLFLUSH line size
 781          *      (Value * 8 = cache line size in bytes)
 782          */
 783         if ((cpu_feature & CPUID_CLFSH) != 0)
 784                 cpu_clflush_line_size = ((cpu_procinfo >> 8) & 0xff) * 8;
 785         /*
 786          * XXXKIB: (temporary) hack to work around traps generated
 787          * when CLFLUSHing APIC register window under virtualization
 788          * environments.  These environments tend to disable the
 789          * CPUID_SS feature even though the native CPU supports it.
 790          */
 791         TUNABLE_INT_FETCH("hw.clflush_disable", &hw_clflush_disable);
 792         if (vm_guest != VM_GUEST_NO && hw_clflush_disable == -1) {
 793                 cpu_feature &= ~CPUID_CLFSH;
 794                 cpu_stdext_feature &= ~CPUID_STDEXT_CLFLUSHOPT;
 795         }
 796         /*
 797          * The kernel's use of CLFLUSH{,OPT} can be disabled manually
 798          * by setting the hw.clflush_disable tunable.
 799          */
 800         if (hw_clflush_disable == 1) {
 801                 cpu_feature &= ~CPUID_CLFSH;
 802                 cpu_stdext_feature &= ~CPUID_STDEXT_CLFLUSHOPT;
 803         }
 804
 805 #if defined(PC98) && !defined(CPU_UPGRADE_HW_CACHE)
 806         /*
 807          * OS should flush L1 cache by itself because no PC-98 supports
 808          * non-Intel CPUs.  Use wbinvd instruction before DMA transfer
 809          * when need_pre_dma_flush = 1, use invd instruction after DMA
 810          * transfer when need_post_dma_flush = 1.  If your CPU upgrade
 811          * product supports hardware cache control, you can add the
 812          * CPU_UPGRADE_HW_CACHE option in your kernel configuration file.
 813          * This option eliminates unneeded cache flush instruction(s).
 814          */
 815         if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
 816                 switch (cpu) {
 817 #ifdef I486_CPU
 818                 case CPU_486DLC:
 819                         need_post_dma_flush = 1;
 820                         break;
 821                 case CPU_M1SC:
 822                         need_pre_dma_flush = 1;
 823                         break;
 824                 case CPU_CY486DX:
 825                         need_pre_dma_flush = 1;
 826 #ifdef CPU_I486_ON_386
 827                         need_post_dma_flush = 1;
 828 #endif
 829                         break;
 830 #endif
 831                 default:
 832                         break;
 833                 }
 834         } else if (cpu_vendor_id == CPU_VENDOR_AMD) {
 835                 switch (cpu_id & 0xFF0) {
 836                 case 0x470:             /* Enhanced Am486DX2 WB */
 837                 case 0x490:             /* Enhanced Am486DX4 WB */
 838                 case 0x4F0:             /* Am5x86 WB */
 839                         need_pre_dma_flush = 1;
 840                         break;
 841                 }
 842         } else if (cpu_vendor_id == CPU_VENDOR_IBM) {
 843                 need_post_dma_flush = 1;
 844         } else {
 845 #ifdef CPU_I486_ON_386
 846                 need_pre_dma_flush = 1;
 847 #endif
 848         }
 849 #endif /* PC98 && !CPU_UPGRADE_HW_CACHE */
 850 }
 851
 852 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
 853 /*
 854  * Enable write allocate feature of AMD processors.
 855  * Following two functions require the Maxmem variable being set.
 856  */
 857 static void
 858 enable_K5_wt_alloc(void)
 859 {
 860         u_int64_t       msr;
 861         register_t      saveintr;
 862
 863         /*
 864          * Write allocate is supported only on models 1, 2, and 3, with
 865          * a stepping of 4 or greater.
 866          */
 867         if (((cpu_id & 0xf0) > 0) && ((cpu_id & 0x0f) > 3)) {
 868                 saveintr = intr_disable();
 869                 msr = rdmsr(0x83);              /* HWCR */
 870                 wrmsr(0x83, msr & !(0x10));
 871
 872                 /*
 873                  * We have to tell the chip where the top of memory is,
 874                  * since video cards could have frame bufferes there,
 875                  * memory-mapped I/O could be there, etc.
 876                  */
 877                 if(Maxmem > 0)
 878                   msr = Maxmem / 16;
 879                 else
 880                   msr = 0;
 881                 msr |= AMD_WT_ALLOC_TME | AMD_WT_ALLOC_FRE;
 882 #ifdef PC98
 883                 if (!(inb(0x43b) & 4)) {
 884                         wrmsr(0x86, 0x0ff00f0);
 885                         msr |= AMD_WT_ALLOC_PRE;
 886                 }
 887 #else
 888                 /*
 889                  * There is no way to know wheter 15-16M hole exists or not.
 890                  * Therefore, we disable write allocate for this range.
 891                  */
 892                         wrmsr(0x86, 0x0ff00f0);
 893                         msr |= AMD_WT_ALLOC_PRE;
 894 #endif
 895                 wrmsr(0x85, msr);
 896
 897                 msr=rdmsr(0x83);
 898                 wrmsr(0x83, msr|0x10); /* enable write allocate */
 899                 intr_restore(saveintr);
 900         }
 901 }
 902
 903 static void
 904 enable_K6_wt_alloc(void)
 905 {
 906         quad_t  size;
 907         u_int64_t       whcr;
 908         register_t      saveintr;
 909
 910         saveintr = intr_disable();
 911         wbinvd();
 912
 913 #ifdef CPU_DISABLE_CACHE
 914         /*
 915          * Certain K6-2 box becomes unstable when write allocation is
 916          * enabled.
 917          */
 918         /*
 919          * The AMD-K6 processer provides the 64-bit Test Register 12(TR12),
 920          * but only the Cache Inhibit(CI) (bit 3 of TR12) is suppported.
 921          * All other bits in TR12 have no effect on the processer's operation.
 922          * The I/O Trap Restart function (bit 9 of TR12) is always enabled
 923          * on the AMD-K6.
 924          */
 925         wrmsr(0x0000000e, (u_int64_t)0x0008);
 926 #endif
 927         /* Don't assume that memory size is aligned with 4M. */
 928         if (Maxmem > 0)
 929           size = ((Maxmem >> 8) + 3) >> 2;
 930         else
 931           size = 0;
 932
 933         /* Limit is 508M bytes. */
 934         if (size > 0x7f)
 935                 size = 0x7f;
 936         whcr = (rdmsr(0xc0000082) & ~(0x7fLL << 1)) | (size << 1);
 937
 938 #if defined(PC98) || defined(NO_MEMORY_HOLE)
 939         if (whcr & (0x7fLL << 1)) {
 940 #ifdef PC98
 941                 /*
 942                  * If bit 2 of port 0x43b is 0, disable wrte allocate for the
 943                  * 15-16M range.
 944                  */
 945                 if (!(inb(0x43b) & 4))
 946                         whcr &= ~0x0001LL;
 947                 else
 948 #endif
 949                         whcr |=  0x0001LL;
 950         }
 951 #else
 952         /*
 953          * There is no way to know wheter 15-16M hole exists or not.
 954          * Therefore, we disable write allocate for this range.
 955          */
 956         whcr &= ~0x0001LL;
 957 #endif
 958         wrmsr(0x0c0000082, whcr);
 959
 960         intr_restore(saveintr);
 961 }
 962
 963 static void
 964 enable_K6_2_wt_alloc(void)
 965 {
 966         quad_t  size;
 967         u_int64_t       whcr;
 968         register_t      saveintr;
 969
 970         saveintr = intr_disable();
 971         wbinvd();
 972
 973 #ifdef CPU_DISABLE_CACHE
 974         /*
 975          * Certain K6-2 box becomes unstable when write allocation is
 976          * enabled.
 977          */
 978         /*
 979          * The AMD-K6 processer provides the 64-bit Test Register 12(TR12),
 980          * but only the Cache Inhibit(CI) (bit 3 of TR12) is suppported.
 981          * All other bits in TR12 have no effect on the processer's operation.
 982          * The I/O Trap Restart function (bit 9 of TR12) is always enabled
 983          * on the AMD-K6.
 984          */
 985         wrmsr(0x0000000e, (u_int64_t)0x0008);
 986 #endif
 987         /* Don't assume that memory size is aligned with 4M. */
 988         if (Maxmem > 0)
 989           size = ((Maxmem >> 8) + 3) >> 2;
 990         else
 991           size = 0;
 992
 993         /* Limit is 4092M bytes. */
 994         if (size > 0x3fff)
 995                 size = 0x3ff;
 996         whcr = (rdmsr(0xc0000082) & ~(0x3ffLL << 22)) | (size << 22);
 997
 998 #if defined(PC98) || defined(NO_MEMORY_HOLE)
 999         if (whcr & (0x3ffLL << 22)) {
1000 #ifdef PC98
1001                 /*
1002                  * If bit 2 of port 0x43b is 0, disable wrte allocate for the
1003                  * 15-16M range.
1004                  */
1005                 if (!(inb(0x43b) & 4))
1006                         whcr &= ~(1LL << 16);
1007                 else
1008 #endif
1009                         whcr |=  1LL << 16;
1010         }
1011 #else
1012         /*
1013          * There is no way to know wheter 15-16M hole exists or not.
1014          * Therefore, we disable write allocate for this range.
1015          */
1016         whcr &= ~(1LL << 16);
1017 #endif
1018         wrmsr(0x0c0000082, whcr);
1019
1020         intr_restore(saveintr);
1021 }
1022 #endif /* I585_CPU && CPU_WT_ALLOC */
1023
1024 #include "opt_ddb.h"
1025 #ifdef DDB
1026 #include <ddb/ddb.h>
1027
1028 DB_SHOW_COMMAND(cyrixreg, cyrixreg)
1029 {
1030         register_t saveintr;
1031         u_int   cr0;
1032         u_char  ccr1, ccr2, ccr3;
1033         u_char  ccr0 = 0, ccr4 = 0, ccr5 = 0, pcr0 = 0;
1034
1035         cr0 = rcr0();
1036         if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
1037                 saveintr = intr_disable();
1038
1039
1040                 if ((cpu != CPU_M1SC) && (cpu != CPU_CY486DX)) {
1041                         ccr0 = read_cyrix_reg(CCR0);
1042                 }
1043                 ccr1 = read_cyrix_reg(CCR1);
1044                 ccr2 = read_cyrix_reg(CCR2);
1045                 ccr3 = read_cyrix_reg(CCR3);
1046                 if ((cpu == CPU_M1SC) || (cpu == CPU_M1) || (cpu == CPU_M2)) {
1047                         write_cyrix_reg(CCR3, CCR3_MAPEN0);
1048                         ccr4 = read_cyrix_reg(CCR4);
1049                         if ((cpu == CPU_M1) || (cpu == CPU_M2))
1050                                 ccr5 = read_cyrix_reg(CCR5);
1051                         else
1052                                 pcr0 = read_cyrix_reg(PCR0);
1053                         write_cyrix_reg(CCR3, ccr3);            /* Restore CCR3. */
1054                 }
1055                 intr_restore(saveintr);
1056
1057                 if ((cpu != CPU_M1SC) && (cpu != CPU_CY486DX))
1058                         printf("CCR0=%x, ", (u_int)ccr0);
1059
1060                 printf("CCR1=%x, CCR2=%x, CCR3=%x",
1061                         (u_int)ccr1, (u_int)ccr2, (u_int)ccr3);
1062                 if ((cpu == CPU_M1SC) || (cpu == CPU_M1) || (cpu == CPU_M2)) {
1063                         printf(", CCR4=%x, ", (u_int)ccr4);
1064                         if (cpu == CPU_M1SC)
1065                                 printf("PCR0=%x\n", pcr0);
1066                         else
1067                                 printf("CCR5=%x\n", ccr5);
1068                 }
1069         }
1070         printf("CR0=%x\n", cr0);
1071 }
1072 #endif /* DDB */