sys/x86/x86/identcpu.c

   1 /*-
   2  * Copyright (c) 1992 Terrence R. Lambert.
   3  * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
   4  * Copyright (c) 1997 KATO Takenori.
   5  * All rights reserved.
   6  *
   7  * This code is derived from software contributed to Berkeley by
   8  * William Jolitz.
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  * 3. All advertising materials mentioning features or use of this software
  19  *    must display the following acknowledgement:
  20  *      This product includes software developed by the University of
  21  *      California, Berkeley and its contributors.
  22  * 4. Neither the name of the University nor the names of its contributors
  23  *    may be used to endorse or promote products derived from this software
  24  *    without specific prior written permission.
  25  *
  26  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  27  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  28  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  29  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  30  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  31  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  32  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  33  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  34  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  35  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  36  * SUCH DAMAGE.
  37  *
  38  *      from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp
  39  */
  40
  41 #include <sys/cdefs.h>
  42 __FBSDID("$FreeBSD$");
  43
  44 #include "opt_cpu.h"
  45
  46 #include <sys/param.h>
  47 #include <sys/bus.h>
  48 #include <sys/cpu.h>
  49 #include <sys/eventhandler.h>
  50 #include <sys/limits.h>
  51 #include <sys/systm.h>
  52 #include <sys/kernel.h>
  53 #include <sys/sysctl.h>
  54 #include <sys/power.h>
  55
  56 #include <vm/vm.h>
  57 #include <vm/pmap.h>
  58
  59 #include <machine/asmacros.h>
  60 #include <machine/clock.h>
  61 #include <machine/cputypes.h>
  62 #include <machine/frame.h>
  63 #include <machine/intr_machdep.h>
  64 #include <machine/md_var.h>
  65 #include <machine/segments.h>
  66 #include <machine/specialreg.h>
  67
  68 #include <amd64/vmm/intel/vmx_controls.h>
  69 #include <x86/isa/icu.h>
  70 #include <x86/vmware.h>
  71
  72 #ifdef __i386__
  73 #define IDENTBLUE_CYRIX486      0
  74 #define IDENTBLUE_IBMCPU        1
  75 #define IDENTBLUE_CYRIXM2       2
  76
  77 static void identifycyrix(void);
  78 static void print_transmeta_info(void);
  79 #endif
  80 static u_int find_cpu_vendor_id(void);
  81 static void print_AMD_info(void);
  82 static void print_INTEL_info(void);
  83 static void print_INTEL_TLB(u_int data);
  84 static void print_hypervisor_info(void);
  85 static void print_svm_info(void);
  86 static void print_via_padlock_info(void);
  87 static void print_vmx_info(void);
  88
  89 #ifdef __i386__
  90 int     cpu;                    /* Are we 386, 386sx, 486, etc? */
  91 int     cpu_class;
  92 #endif
  93 u_int   cpu_feature;            /* Feature flags */
  94 u_int   cpu_feature2;           /* Feature flags */
  95 u_int   amd_feature;            /* AMD feature flags */
  96 u_int   amd_feature2;           /* AMD feature flags */
  97 u_int   amd_rascap;             /* AMD RAS capabilities */
  98 u_int   amd_pminfo;             /* AMD advanced power management info */
  99 u_int   amd_extended_feature_extensions;
 100 u_int   via_feature_rng;        /* VIA RNG features */
 101 u_int   via_feature_xcrypt;     /* VIA ACE features */
 102 u_int   cpu_high;               /* Highest arg to CPUID */
 103 u_int   cpu_exthigh;            /* Highest arg to extended CPUID */
 104 u_int   cpu_id;                 /* Stepping ID */
 105 u_int   cpu_procinfo;           /* HyperThreading Info / Brand Index / CLFUSH */
 106 u_int   cpu_procinfo2;          /* Multicore info */
 107 char    cpu_vendor[20];         /* CPU Origin code */
 108 u_int   cpu_vendor_id;          /* CPU vendor ID */
 109 u_int   cpu_fxsr;               /* SSE enabled */
 110 u_int   cpu_mxcsr_mask;         /* Valid bits in mxcsr */
 111 u_int   cpu_clflush_line_size = 32;
 112 u_int   cpu_stdext_feature;     /* %ebx */
 113 u_int   cpu_stdext_feature2;    /* %ecx */
 114 u_int   cpu_stdext_feature3;    /* %edx */
 115 uint64_t cpu_ia32_arch_caps;
 116 u_int   cpu_max_ext_state_size;
 117 u_int   cpu_mon_mwait_flags;    /* MONITOR/MWAIT flags (CPUID.05H.ECX) */
 118 u_int   cpu_mon_min_size;       /* MONITOR minimum range size, bytes */
 119 u_int   cpu_mon_max_size;       /* MONITOR minimum range size, bytes */
 120 u_int   cpu_maxphyaddr;         /* Max phys addr width in bits */
 121 char machine[] = MACHINE;
 122
 123 SYSCTL_UINT(_hw, OID_AUTO, via_feature_rng, CTLFLAG_RD,
 124     &via_feature_rng, 0,
 125     "VIA RNG feature available in CPU");
 126 SYSCTL_UINT(_hw, OID_AUTO, via_feature_xcrypt, CTLFLAG_RD,
 127     &via_feature_xcrypt, 0,
 128     "VIA xcrypt feature available in CPU");
 129
 130 #ifdef __amd64__
 131 #ifdef SCTL_MASK32
 132 extern int adaptive_machine_arch;
 133 #endif
 134
 135 static int
 136 sysctl_hw_machine(SYSCTL_HANDLER_ARGS)
 137 {
 138 #ifdef SCTL_MASK32
 139         static const char machine32[] = "i386";
 140 #endif
 141         int error;
 142
 143 #ifdef SCTL_MASK32
 144         if ((req->flags & SCTL_MASK32) != 0 && adaptive_machine_arch)
 145                 error = SYSCTL_OUT(req, machine32, sizeof(machine32));
 146         else
 147 #endif
 148                 error = SYSCTL_OUT(req, machine, sizeof(machine));
 149         return (error);
 150
 151 }
 152 SYSCTL_PROC(_hw, HW_MACHINE, machine, CTLTYPE_STRING | CTLFLAG_RD |
 153     CTLFLAG_MPSAFE, NULL, 0, sysctl_hw_machine, "A", "Machine class");
 154 #else
 155 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD,
 156     machine, 0, "Machine class");
 157 #endif
 158
 159 static char cpu_model[128];
 160 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD | CTLFLAG_MPSAFE,
 161     cpu_model, 0, "Machine model");
 162
 163 static int hw_clockrate;
 164 SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD,
 165     &hw_clockrate, 0, "CPU instruction clock rate");
 166
 167 u_int hv_base;
 168 u_int hv_high;
 169 char hv_vendor[16];
 170 SYSCTL_STRING(_hw, OID_AUTO, hv_vendor, CTLFLAG_RD | CTLFLAG_MPSAFE, hv_vendor,
 171     0, "Hypervisor vendor");
 172
 173 static eventhandler_tag tsc_post_tag;
 174
 175 static char cpu_brand[48];
 176
 177 #ifdef __i386__
 178 #define MAX_BRAND_INDEX 8
 179
 180 static const char *cpu_brandtable[MAX_BRAND_INDEX + 1] = {
 181         NULL,                   /* No brand */
 182         "Intel Celeron",
 183         "Intel Pentium III",
 184         "Intel Pentium III Xeon",
 185         NULL,
 186         NULL,
 187         NULL,
 188         NULL,
 189         "Intel Pentium 4"
 190 };
 191
 192 static struct {
 193         char    *cpu_name;
 194         int     cpu_class;
 195 } cpus[] = {
 196         { "Intel 80286",        CPUCLASS_286 },         /* CPU_286   */
 197         { "i386SX",             CPUCLASS_386 },         /* CPU_386SX */
 198         { "i386DX",             CPUCLASS_386 },         /* CPU_386   */
 199         { "i486SX",             CPUCLASS_486 },         /* CPU_486SX */
 200         { "i486DX",             CPUCLASS_486 },         /* CPU_486   */
 201         { "Pentium",            CPUCLASS_586 },         /* CPU_586   */
 202         { "Cyrix 486",          CPUCLASS_486 },         /* CPU_486DLC */
 203         { "Pentium Pro",        CPUCLASS_686 },         /* CPU_686 */
 204         { "Cyrix 5x86",         CPUCLASS_486 },         /* CPU_M1SC */
 205         { "Cyrix 6x86",         CPUCLASS_486 },         /* CPU_M1 */
 206         { "Blue Lightning",     CPUCLASS_486 },         /* CPU_BLUE */
 207         { "Cyrix 6x86MX",       CPUCLASS_686 },         /* CPU_M2 */
 208         { "NexGen 586",         CPUCLASS_386 },         /* CPU_NX586 (XXX) */
 209         { "Cyrix 486S/DX",      CPUCLASS_486 },         /* CPU_CY486DX */
 210         { "Pentium II",         CPUCLASS_686 },         /* CPU_PII */
 211         { "Pentium III",        CPUCLASS_686 },         /* CPU_PIII */
 212         { "Pentium 4",          CPUCLASS_686 },         /* CPU_P4 */
 213 };
 214 #endif
 215
 216 static struct {
 217         char    *vendor;
 218         u_int   vendor_id;
 219 } cpu_vendors[] = {
 220         { INTEL_VENDOR_ID,      CPU_VENDOR_INTEL },     /* GenuineIntel */
 221         { AMD_VENDOR_ID,        CPU_VENDOR_AMD },       /* AuthenticAMD */
 222         { CENTAUR_VENDOR_ID,    CPU_VENDOR_CENTAUR },   /* CentaurHauls */
 223 #ifdef __i386__
 224         { NSC_VENDOR_ID,        CPU_VENDOR_NSC },       /* Geode by NSC */
 225         { CYRIX_VENDOR_ID,      CPU_VENDOR_CYRIX },     /* CyrixInstead */
 226         { TRANSMETA_VENDOR_ID,  CPU_VENDOR_TRANSMETA }, /* GenuineTMx86 */
 227         { SIS_VENDOR_ID,        CPU_VENDOR_SIS },       /* SiS SiS SiS  */
 228         { UMC_VENDOR_ID,        CPU_VENDOR_UMC },       /* UMC UMC UMC  */
 229         { NEXGEN_VENDOR_ID,     CPU_VENDOR_NEXGEN },    /* NexGenDriven */
 230         { RISE_VENDOR_ID,       CPU_VENDOR_RISE },      /* RiseRiseRise */
 231 #if 0
 232         /* XXX CPUID 8000_0000h and 8086_0000h, not 0000_0000h */
 233         { "TransmetaCPU",       CPU_VENDOR_TRANSMETA },
 234 #endif
 235 #endif
 236 };
 237
 238 void
 239 printcpuinfo(void)
 240 {
 241         u_int regs[4], i;
 242         char *brand;
 243
 244         printf("CPU: ");
 245 #ifdef __i386__
 246         cpu_class = cpus[cpu].cpu_class;
 247         strncpy(cpu_model, cpus[cpu].cpu_name, sizeof (cpu_model));
 248 #else
 249         strncpy(cpu_model, "Hammer", sizeof (cpu_model));
 250 #endif
 251
 252         /* Check for extended CPUID information and a processor name. */
 253         if (cpu_exthigh >= 0x80000004) {
 254                 brand = cpu_brand;
 255                 for (i = 0x80000002; i < 0x80000005; i++) {
 256                         do_cpuid(i, regs);
 257                         memcpy(brand, regs, sizeof(regs));
 258                         brand += sizeof(regs);
 259                 }
 260         }
 261
 262         switch (cpu_vendor_id) {
 263         case CPU_VENDOR_INTEL:
 264 #ifdef __i386__
 265                 if ((cpu_id & 0xf00) > 0x300) {
 266                         u_int brand_index;
 267
 268                         cpu_model[0] = '\0';
 269
 270                         switch (cpu_id & 0x3000) {
 271                         case 0x1000:
 272                                 strcpy(cpu_model, "Overdrive ");
 273                                 break;
 274                         case 0x2000:
 275                                 strcpy(cpu_model, "Dual ");
 276                                 break;
 277                         }
 278
 279                         switch (cpu_id & 0xf00) {
 280                         case 0x400:
 281                                 strcat(cpu_model, "i486 ");
 282                                 /* Check the particular flavor of 486 */
 283                                 switch (cpu_id & 0xf0) {
 284                                 case 0x00:
 285                                 case 0x10:
 286                                         strcat(cpu_model, "DX");
 287                                         break;
 288                                 case 0x20:
 289                                         strcat(cpu_model, "SX");
 290                                         break;
 291                                 case 0x30:
 292                                         strcat(cpu_model, "DX2");
 293                                         break;
 294                                 case 0x40:
 295                                         strcat(cpu_model, "SL");
 296                                         break;
 297                                 case 0x50:
 298                                         strcat(cpu_model, "SX2");
 299                                         break;
 300                                 case 0x70:
 301                                         strcat(cpu_model,
 302                                             "DX2 Write-Back Enhanced");
 303                                         break;
 304                                 case 0x80:
 305                                         strcat(cpu_model, "DX4");
 306                                         break;
 307                                 }
 308                                 break;
 309                         case 0x500:
 310                                 /* Check the particular flavor of 586 */
 311                                 strcat(cpu_model, "Pentium");
 312                                 switch (cpu_id & 0xf0) {
 313                                 case 0x00:
 314                                         strcat(cpu_model, " A-step");
 315                                         break;
 316                                 case 0x10:
 317                                         strcat(cpu_model, "/P5");
 318                                         break;
 319                                 case 0x20:
 320                                         strcat(cpu_model, "/P54C");
 321                                         break;
 322                                 case 0x30:
 323                                         strcat(cpu_model, "/P24T");
 324                                         break;
 325                                 case 0x40:
 326                                         strcat(cpu_model, "/P55C");
 327                                         break;
 328                                 case 0x70:
 329                                         strcat(cpu_model, "/P54C");
 330                                         break;
 331                                 case 0x80:
 332                                         strcat(cpu_model, "/P55C (quarter-micron)");
 333                                         break;
 334                                 default:
 335                                         /* nothing */
 336                                         break;
 337                                 }
 338 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
 339                                 /*
 340                                  * XXX - If/when Intel fixes the bug, this
 341                                  * should also check the version of the
 342                                  * CPU, not just that it's a Pentium.
 343                                  */
 344                                 has_f00f_bug = 1;
 345 #endif
 346                                 break;
 347                         case 0x600:
 348                                 /* Check the particular flavor of 686 */
 349                                 switch (cpu_id & 0xf0) {
 350                                 case 0x00:
 351                                         strcat(cpu_model, "Pentium Pro A-step");
 352                                         break;
 353                                 case 0x10:
 354                                         strcat(cpu_model, "Pentium Pro");
 355                                         break;
 356                                 case 0x30:
 357                                 case 0x50:
 358                                 case 0x60:
 359                                         strcat(cpu_model,
 360                                 "Pentium II/Pentium II Xeon/Celeron");
 361                                         cpu = CPU_PII;
 362                                         break;
 363                                 case 0x70:
 364                                 case 0x80:
 365                                 case 0xa0:
 366                                 case 0xb0:
 367                                         strcat(cpu_model,
 368                                         "Pentium III/Pentium III Xeon/Celeron");
 369                                         cpu = CPU_PIII;
 370                                         break;
 371                                 default:
 372                                         strcat(cpu_model, "Unknown 80686");
 373                                         break;
 374                                 }
 375                                 break;
 376                         case 0xf00:
 377                                 strcat(cpu_model, "Pentium 4");
 378                                 cpu = CPU_P4;
 379                                 break;
 380                         default:
 381                                 strcat(cpu_model, "unknown");
 382                                 break;
 383                         }
 384
 385                         /*
 386                          * If we didn't get a brand name from the extended
 387                          * CPUID, try to look it up in the brand table.
 388                          */
 389                         if (cpu_high > 0 && *cpu_brand == '\0') {
 390                                 brand_index = cpu_procinfo & CPUID_BRAND_INDEX;
 391                                 if (brand_index <= MAX_BRAND_INDEX &&
 392                                     cpu_brandtable[brand_index] != NULL)
 393                                         strcpy(cpu_brand,
 394                                             cpu_brandtable[brand_index]);
 395                         }
 396                 }
 397 #else
 398                 /* Please make up your mind folks! */
 399                 strcat(cpu_model, "EM64T");
 400 #endif
 401                 break;
 402         case CPU_VENDOR_AMD:
 403                 /*
 404                  * Values taken from AMD Processor Recognition
 405                  * http://www.amd.com/K6/k6docs/pdf/20734g.pdf
 406                  * (also describes ``Features'' encodings.
 407                  */
 408                 strcpy(cpu_model, "AMD ");
 409 #ifdef __i386__
 410                 switch (cpu_id & 0xFF0) {
 411                 case 0x410:
 412                         strcat(cpu_model, "Standard Am486DX");
 413                         break;
 414                 case 0x430:
 415                         strcat(cpu_model, "Enhanced Am486DX2 Write-Through");
 416                         break;
 417                 case 0x470:
 418                         strcat(cpu_model, "Enhanced Am486DX2 Write-Back");
 419                         break;
 420                 case 0x480:
 421                         strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Through");
 422                         break;
 423                 case 0x490:
 424                         strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Back");
 425                         break;
 426                 case 0x4E0:
 427                         strcat(cpu_model, "Am5x86 Write-Through");
 428                         break;
 429                 case 0x4F0:
 430                         strcat(cpu_model, "Am5x86 Write-Back");
 431                         break;
 432                 case 0x500:
 433                         strcat(cpu_model, "K5 model 0");
 434                         break;
 435                 case 0x510:
 436                         strcat(cpu_model, "K5 model 1");
 437                         break;
 438                 case 0x520:
 439                         strcat(cpu_model, "K5 PR166 (model 2)");
 440                         break;
 441                 case 0x530:
 442                         strcat(cpu_model, "K5 PR200 (model 3)");
 443                         break;
 444                 case 0x560:
 445                         strcat(cpu_model, "K6");
 446                         break;
 447                 case 0x570:
 448                         strcat(cpu_model, "K6 266 (model 1)");
 449                         break;
 450                 case 0x580:
 451                         strcat(cpu_model, "K6-2");
 452                         break;
 453                 case 0x590:
 454                         strcat(cpu_model, "K6-III");
 455                         break;
 456                 case 0x5a0:
 457                         strcat(cpu_model, "Geode LX");
 458                         break;
 459                 default:
 460                         strcat(cpu_model, "Unknown");
 461                         break;
 462                 }
 463 #else
 464                 if ((cpu_id & 0xf00) == 0xf00)
 465                         strcat(cpu_model, "AMD64 Processor");
 466                 else
 467                         strcat(cpu_model, "Unknown");
 468 #endif
 469                 break;
 470 #ifdef __i386__
 471         case CPU_VENDOR_CYRIX:
 472                 strcpy(cpu_model, "Cyrix ");
 473                 switch (cpu_id & 0xff0) {
 474                 case 0x440:
 475                         strcat(cpu_model, "MediaGX");
 476                         break;
 477                 case 0x520:
 478                         strcat(cpu_model, "6x86");
 479                         break;
 480                 case 0x540:
 481                         cpu_class = CPUCLASS_586;
 482                         strcat(cpu_model, "GXm");
 483                         break;
 484                 case 0x600:
 485                         strcat(cpu_model, "6x86MX");
 486                         break;
 487                 default:
 488                         /*
 489                          * Even though CPU supports the cpuid
 490                          * instruction, it can be disabled.
 491                          * Therefore, this routine supports all Cyrix
 492                          * CPUs.
 493                          */
 494                         switch (cyrix_did & 0xf0) {
 495                         case 0x00:
 496                                 switch (cyrix_did & 0x0f) {
 497                                 case 0x00:
 498                                         strcat(cpu_model, "486SLC");
 499                                         break;
 500                                 case 0x01:
 501                                         strcat(cpu_model, "486DLC");
 502                                         break;
 503                                 case 0x02:
 504                                         strcat(cpu_model, "486SLC2");
 505                                         break;
 506                                 case 0x03:
 507                                         strcat(cpu_model, "486DLC2");
 508                                         break;
 509                                 case 0x04:
 510                                         strcat(cpu_model, "486SRx");
 511                                         break;
 512                                 case 0x05:
 513                                         strcat(cpu_model, "486DRx");
 514                                         break;
 515                                 case 0x06:
 516                                         strcat(cpu_model, "486SRx2");
 517                                         break;
 518                                 case 0x07:
 519                                         strcat(cpu_model, "486DRx2");
 520                                         break;
 521                                 case 0x08:
 522                                         strcat(cpu_model, "486SRu");
 523                                         break;
 524                                 case 0x09:
 525                                         strcat(cpu_model, "486DRu");
 526                                         break;
 527                                 case 0x0a:
 528                                         strcat(cpu_model, "486SRu2");
 529                                         break;
 530                                 case 0x0b:
 531                                         strcat(cpu_model, "486DRu2");
 532                                         break;
 533                                 default:
 534                                         strcat(cpu_model, "Unknown");
 535                                         break;
 536                                 }
 537                                 break;
 538                         case 0x10:
 539                                 switch (cyrix_did & 0x0f) {
 540                                 case 0x00:
 541                                         strcat(cpu_model, "486S");
 542                                         break;
 543                                 case 0x01:
 544                                         strcat(cpu_model, "486S2");
 545                                         break;
 546                                 case 0x02:
 547                                         strcat(cpu_model, "486Se");
 548                                         break;
 549                                 case 0x03:
 550                                         strcat(cpu_model, "486S2e");
 551                                         break;
 552                                 case 0x0a:
 553                                         strcat(cpu_model, "486DX");
 554                                         break;
 555                                 case 0x0b:
 556                                         strcat(cpu_model, "486DX2");
 557                                         break;
 558                                 case 0x0f:
 559                                         strcat(cpu_model, "486DX4");
 560                                         break;
 561                                 default:
 562                                         strcat(cpu_model, "Unknown");
 563                                         break;
 564                                 }
 565                                 break;
 566                         case 0x20:
 567                                 if ((cyrix_did & 0x0f) < 8)
 568                                         strcat(cpu_model, "6x86");      /* Where did you get it? */
 569                                 else
 570                                         strcat(cpu_model, "5x86");
 571                                 break;
 572                         case 0x30:
 573                                 strcat(cpu_model, "6x86");
 574                                 break;
 575                         case 0x40:
 576                                 if ((cyrix_did & 0xf000) == 0x3000) {
 577                                         cpu_class = CPUCLASS_586;
 578                                         strcat(cpu_model, "GXm");
 579                                 } else
 580                                         strcat(cpu_model, "MediaGX");
 581                                 break;
 582                         case 0x50:
 583                                 strcat(cpu_model, "6x86MX");
 584                                 break;
 585                         case 0xf0:
 586                                 switch (cyrix_did & 0x0f) {
 587                                 case 0x0d:
 588                                         strcat(cpu_model, "Overdrive CPU");
 589                                         break;
 590                                 case 0x0e:
 591                                         strcpy(cpu_model, "Texas Instruments 486SXL");
 592                                         break;
 593                                 case 0x0f:
 594                                         strcat(cpu_model, "486SLC/DLC");
 595                                         break;
 596                                 default:
 597                                         strcat(cpu_model, "Unknown");
 598                                         break;
 599                                 }
 600                                 break;
 601                         default:
 602                                 strcat(cpu_model, "Unknown");
 603                                 break;
 604                         }
 605                         break;
 606                 }
 607                 break;
 608         case CPU_VENDOR_RISE:
 609                 strcpy(cpu_model, "Rise ");
 610                 switch (cpu_id & 0xff0) {
 611                 case 0x500:     /* 6401 and 6441 (Kirin) */
 612                 case 0x520:     /* 6510 (Lynx) */
 613                         strcat(cpu_model, "mP6");
 614                         break;
 615                 default:
 616                         strcat(cpu_model, "Unknown");
 617                 }
 618                 break;
 619 #endif
 620         case CPU_VENDOR_CENTAUR:
 621 #ifdef __i386__
 622                 switch (cpu_id & 0xff0) {
 623                 case 0x540:
 624                         strcpy(cpu_model, "IDT WinChip C6");
 625                         break;
 626                 case 0x580:
 627                         strcpy(cpu_model, "IDT WinChip 2");
 628                         break;
 629                 case 0x590:
 630                         strcpy(cpu_model, "IDT WinChip 3");
 631                         break;
 632                 case 0x660:
 633                         strcpy(cpu_model, "VIA C3 Samuel");
 634                         break;
 635                 case 0x670:
 636                         if (cpu_id & 0x8)
 637                                 strcpy(cpu_model, "VIA C3 Ezra");
 638                         else
 639                                 strcpy(cpu_model, "VIA C3 Samuel 2");
 640                         break;
 641                 case 0x680:
 642                         strcpy(cpu_model, "VIA C3 Ezra-T");
 643                         break;
 644                 case 0x690:
 645                         strcpy(cpu_model, "VIA C3 Nehemiah");
 646                         break;
 647                 case 0x6a0:
 648                 case 0x6d0:
 649                         strcpy(cpu_model, "VIA C7 Esther");
 650                         break;
 651                 case 0x6f0:
 652                         strcpy(cpu_model, "VIA Nano");
 653                         break;
 654                 default:
 655                         strcpy(cpu_model, "VIA/IDT Unknown");
 656                 }
 657 #else
 658                 strcpy(cpu_model, "VIA ");
 659                 if ((cpu_id & 0xff0) == 0x6f0)
 660                         strcat(cpu_model, "Nano Processor");
 661                 else
 662                         strcat(cpu_model, "Unknown");
 663 #endif
 664                 break;
 665 #ifdef __i386__
 666         case CPU_VENDOR_IBM:
 667                 strcpy(cpu_model, "Blue Lightning CPU");
 668                 break;
 669         case CPU_VENDOR_NSC:
 670                 switch (cpu_id & 0xff0) {
 671                 case 0x540:
 672                         strcpy(cpu_model, "Geode SC1100");
 673                         cpu = CPU_GEODE1100;
 674                         break;
 675                 default:
 676                         strcpy(cpu_model, "Geode/NSC unknown");
 677                         break;
 678                 }
 679                 break;
 680 #endif
 681         default:
 682                 strcat(cpu_model, "Unknown");
 683                 break;
 684         }
 685
 686         /*
 687          * Replace cpu_model with cpu_brand minus leading spaces if
 688          * we have one.
 689          */
 690         brand = cpu_brand;
 691         while (*brand == ' ')
 692                 ++brand;
 693         if (*brand != '\0')
 694                 strcpy(cpu_model, brand);
 695
 696         printf("%s (", cpu_model);
 697         if (tsc_freq != 0) {
 698                 hw_clockrate = (tsc_freq + 5000) / 1000000;
 699                 printf("%jd.%02d-MHz ",
 700                     (intmax_t)(tsc_freq + 4999) / 1000000,
 701                     (u_int)((tsc_freq + 4999) / 10000) % 100);
 702         }
 703 #ifdef __i386__
 704         switch(cpu_class) {
 705         case CPUCLASS_286:
 706                 printf("286");
 707                 break;
 708         case CPUCLASS_386:
 709                 printf("386");
 710                 break;
 711 #if defined(I486_CPU)
 712         case CPUCLASS_486:
 713                 printf("486");
 714                 break;
 715 #endif
 716 #if defined(I586_CPU)
 717         case CPUCLASS_586:
 718                 printf("586");
 719                 break;
 720 #endif
 721 #if defined(I686_CPU)
 722         case CPUCLASS_686:
 723                 printf("686");
 724                 break;
 725 #endif
 726         default:
 727                 printf("Unknown");      /* will panic below... */
 728         }
 729 #else
 730         printf("K8");
 731 #endif
 732         printf("-class CPU)\n");
 733         if (*cpu_vendor)
 734                 printf("  Origin=\"%s\"", cpu_vendor);
 735         if (cpu_id)
 736                 printf("  Id=0x%x", cpu_id);
 737
 738         if (cpu_vendor_id == CPU_VENDOR_INTEL ||
 739             cpu_vendor_id == CPU_VENDOR_AMD ||
 740             cpu_vendor_id == CPU_VENDOR_CENTAUR ||
 741 #ifdef __i386__
 742             cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
 743             cpu_vendor_id == CPU_VENDOR_RISE ||
 744             cpu_vendor_id == CPU_VENDOR_NSC ||
 745             (cpu_vendor_id == CPU_VENDOR_CYRIX && ((cpu_id & 0xf00) > 0x500)) ||
 746 #endif
 747             0) {
 748                 printf("  Family=0x%x", CPUID_TO_FAMILY(cpu_id));
 749                 printf("  Model=0x%x", CPUID_TO_MODEL(cpu_id));
 750                 printf("  Stepping=%u", cpu_id & CPUID_STEPPING);
 751 #ifdef __i386__
 752                 if (cpu_vendor_id == CPU_VENDOR_CYRIX)
 753                         printf("\n  DIR=0x%04x", cyrix_did);
 754 #endif
 755
 756                 /*
 757                  * AMD CPUID Specification
 758                  * http://support.amd.com/us/Embedded_TechDocs/25481.pdf
 759                  *
 760                  * Intel Processor Identification and CPUID Instruction
 761                  * http://www.intel.com/assets/pdf/appnote/241618.pdf
 762                  */
 763                 if (cpu_high > 0) {
 764
 765                         /*
 766                          * Here we should probably set up flags indicating
 767                          * whether or not various features are available.
 768                          * The interesting ones are probably VME, PSE, PAE,
 769                          * and PGE.  The code already assumes without bothering
 770                          * to check that all CPUs >= Pentium have a TSC and
 771                          * MSRs.
 772                          */
 773                         printf("\n  Features=0x%b", cpu_feature,
 774                         "\020"
 775                         "\001FPU"       /* Integral FPU */
 776                         "\002VME"       /* Extended VM86 mode support */
 777                         "\003DE"        /* Debugging Extensions (CR4.DE) */
 778                         "\004PSE"       /* 4MByte page tables */
 779                         "\005TSC"       /* Timestamp counter */
 780                         "\006MSR"       /* Machine specific registers */
 781                         "\007PAE"       /* Physical address extension */
 782                         "\010MCE"       /* Machine Check support */
 783                         "\011CX8"       /* CMPEXCH8 instruction */
 784                         "\012APIC"      /* SMP local APIC */
 785                         "\013oldMTRR"   /* Previous implementation of MTRR */
 786                         "\014SEP"       /* Fast System Call */
 787                         "\015MTRR"      /* Memory Type Range Registers */
 788                         "\016PGE"       /* PG_G (global bit) support */
 789                         "\017MCA"       /* Machine Check Architecture */
 790                         "\020CMOV"      /* CMOV instruction */
 791                         "\021PAT"       /* Page attributes table */
 792                         "\022PSE36"     /* 36 bit address space support */
 793                         "\023PN"        /* Processor Serial number */
 794                         "\024CLFLUSH"   /* Has the CLFLUSH instruction */
 795                         "\025<b20>"
 796                         "\026DTS"       /* Debug Trace Store */
 797                         "\027ACPI"      /* ACPI support */
 798                         "\030MMX"       /* MMX instructions */
 799                         "\031FXSR"      /* FXSAVE/FXRSTOR */
 800                         "\032SSE"       /* Streaming SIMD Extensions */
 801                         "\033SSE2"      /* Streaming SIMD Extensions #2 */
 802                         "\034SS"        /* Self snoop */
 803                         "\035HTT"       /* Hyperthreading (see EBX bit 16-23) */
 804                         "\036TM"        /* Thermal Monitor clock slowdown */
 805                         "\037IA64"      /* CPU can execute IA64 instructions */
 806                         "\040PBE"       /* Pending Break Enable */
 807                         );
 808
 809                         if (cpu_feature2 != 0) {
 810                                 printf("\n  Features2=0x%b", cpu_feature2,
 811                                 "\020"
 812                                 "\001SSE3"      /* SSE3 */
 813                                 "\002PCLMULQDQ" /* Carry-Less Mul Quadword */
 814                                 "\003DTES64"    /* 64-bit Debug Trace */
 815                                 "\004MON"       /* MONITOR/MWAIT Instructions */
 816                                 "\005DS_CPL"    /* CPL Qualified Debug Store */
 817                                 "\006VMX"       /* Virtual Machine Extensions */
 818                                 "\007SMX"       /* Safer Mode Extensions */
 819                                 "\010EST"       /* Enhanced SpeedStep */
 820                                 "\011TM2"       /* Thermal Monitor 2 */
 821                                 "\012SSSE3"     /* SSSE3 */
 822                                 "\013CNXT-ID"   /* L1 context ID available */
 823                                 "\014SDBG"      /* IA32 silicon debug */
 824                                 "\015FMA"       /* Fused Multiply Add */
 825                                 "\016CX16"      /* CMPXCHG16B Instruction */
 826                                 "\017xTPR"      /* Send Task Priority Messages*/
 827                                 "\020PDCM"      /* Perf/Debug Capability MSR */
 828                                 "\021<b16>"
 829                                 "\022PCID"      /* Process-context Identifiers*/
 830                                 "\023DCA"       /* Direct Cache Access */
 831                                 "\024SSE4.1"    /* SSE 4.1 */
 832                                 "\025SSE4.2"    /* SSE 4.2 */
 833                                 "\026x2APIC"    /* xAPIC Extensions */
 834                                 "\027MOVBE"     /* MOVBE Instruction */
 835                                 "\030POPCNT"    /* POPCNT Instruction */
 836                                 "\031TSCDLT"    /* TSC-Deadline Timer */
 837                                 "\032AESNI"     /* AES Crypto */
 838                                 "\033XSAVE"     /* XSAVE/XRSTOR States */
 839                                 "\034OSXSAVE"   /* OS-Enabled State Management*/
 840                                 "\035AVX"       /* Advanced Vector Extensions */
 841                                 "\036F16C"      /* Half-precision conversions */
 842                                 "\037RDRAND"    /* RDRAND Instruction */
 843                                 "\040HV"        /* Hypervisor */
 844                                 );
 845                         }
 846
 847                         if (amd_feature != 0) {
 848                                 printf("\n  AMD Features=0x%b", amd_feature,
 849                                 "\020"          /* in hex */
 850                                 "\001<s0>"      /* Same */
 851                                 "\002<s1>"      /* Same */
 852                                 "\003<s2>"      /* Same */
 853                                 "\004<s3>"      /* Same */
 854                                 "\005<s4>"      /* Same */
 855                                 "\006<s5>"      /* Same */
 856                                 "\007<s6>"      /* Same */
 857                                 "\010<s7>"      /* Same */
 858                                 "\011<s8>"      /* Same */
 859                                 "\012<s9>"      /* Same */
 860                                 "\013<b10>"     /* Undefined */
 861                                 "\014SYSCALL"   /* Have SYSCALL/SYSRET */
 862                                 "\015<s12>"     /* Same */
 863                                 "\016<s13>"     /* Same */
 864                                 "\017<s14>"     /* Same */
 865                                 "\020<s15>"     /* Same */
 866                                 "\021<s16>"     /* Same */
 867                                 "\022<s17>"     /* Same */
 868                                 "\023<b18>"     /* Reserved, unknown */
 869                                 "\024MP"        /* Multiprocessor Capable */
 870                                 "\025NX"        /* Has EFER.NXE, NX */
 871                                 "\026<b21>"     /* Undefined */
 872                                 "\027MMX+"      /* AMD MMX Extensions */
 873                                 "\030<s23>"     /* Same */
 874                                 "\031<s24>"     /* Same */
 875                                 "\032FFXSR"     /* Fast FXSAVE/FXRSTOR */
 876                                 "\033Page1GB"   /* 1-GB large page support */
 877                                 "\034RDTSCP"    /* RDTSCP */
 878                                 "\035<b28>"     /* Undefined */
 879                                 "\036LM"        /* 64 bit long mode */
 880                                 "\0373DNow!+"   /* AMD 3DNow! Extensions */
 881                                 "\0403DNow!"    /* AMD 3DNow! */
 882                                 );
 883                         }
 884
 885                         if (amd_feature2 != 0) {
 886                                 printf("\n  AMD Features2=0x%b", amd_feature2,
 887                                 "\020"
 888                                 "\001LAHF"      /* LAHF/SAHF in long mode */
 889                                 "\002CMP"       /* CMP legacy */
 890                                 "\003SVM"       /* Secure Virtual Mode */
 891                                 "\004ExtAPIC"   /* Extended APIC register */
 892                                 "\005CR8"       /* CR8 in legacy mode */
 893                                 "\006ABM"       /* LZCNT instruction */
 894                                 "\007SSE4A"     /* SSE4A */
 895                                 "\010MAS"       /* Misaligned SSE mode */
 896                                 "\011Prefetch"  /* 3DNow! Prefetch/PrefetchW */
 897                                 "\012OSVW"      /* OS visible workaround */
 898                                 "\013IBS"       /* Instruction based sampling */
 899                                 "\014XOP"       /* XOP extended instructions */
 900                                 "\015SKINIT"    /* SKINIT/STGI */
 901                                 "\016WDT"       /* Watchdog timer */
 902                                 "\017<b14>"
 903                                 "\020LWP"       /* Lightweight Profiling */
 904                                 "\021FMA4"      /* 4-operand FMA instructions */
 905                                 "\022TCE"       /* Translation Cache Extension */
 906                                 "\023<b18>"
 907                                 "\024NodeId"    /* NodeId MSR support */
 908                                 "\025<b20>"
 909                                 "\026TBM"       /* Trailing Bit Manipulation */
 910                                 "\027Topology"  /* Topology Extensions */
 911                                 "\030PCXC"      /* Core perf count */
 912                                 "\031PNXC"      /* NB perf count */
 913                                 "\032<b25>"
 914                                 "\033DBE"       /* Data Breakpoint extension */
 915                                 "\034PTSC"      /* Performance TSC */
 916                                 "\035PL2I"      /* L2I perf count */
 917                                 "\036MWAITX"    /* MONITORX/MWAITX instructions */
 918                                 "\037<b30>"
 919                                 "\040<b31>"
 920                                 );
 921                         }
 922
 923                         if (cpu_stdext_feature != 0) {
 924                                 printf("\n  Structured Extended Features=0x%b",
 925                                     cpu_stdext_feature,
 926                                        "\020"
 927                                        /* RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */
 928                                        "\001FSGSBASE"
 929                                        "\002TSCADJ"
 930                                        "\003SGX"
 931                                        /* Bit Manipulation Instructions */
 932                                        "\004BMI1"
 933                                        /* Hardware Lock Elision */
 934                                        "\005HLE"
 935                                        /* Advanced Vector Instructions 2 */
 936                                        "\006AVX2"
 937                                        /* FDP_EXCPTN_ONLY */
 938                                        "\007FDPEXC"
 939                                        /* Supervisor Mode Execution Prot. */
 940                                        "\010SMEP"
 941                                        /* Bit Manipulation Instructions */
 942                                        "\011BMI2"
 943                                        "\012ERMS"
 944                                        /* Invalidate Processor Context ID */
 945                                        "\013INVPCID"
 946                                        /* Restricted Transactional Memory */
 947                                        "\014RTM"
 948                                        "\015PQM"
 949                                        "\016NFPUSG"
 950                                        /* Intel Memory Protection Extensions */
 951                                        "\017MPX"
 952                                        "\020PQE"
 953                                        /* AVX512 Foundation */
 954                                        "\021AVX512F"
 955                                        "\022AVX512DQ"
 956                                        /* Enhanced NRBG */
 957                                        "\023RDSEED"
 958                                        /* ADCX + ADOX */
 959                                        "\024ADX"
 960                                        /* Supervisor Mode Access Prevention */
 961                                        "\025SMAP"
 962                                        "\026AVX512IFMA"
 963                                        "\027PCOMMIT"
 964                                        "\030CLFLUSHOPT"
 965                                        "\031CLWB"
 966                                        "\032PROCTRACE"
 967                                        "\033AVX512PF"
 968                                        "\034AVX512ER"
 969                                        "\035AVX512CD"
 970                                        "\036SHA"
 971                                        "\037AVX512BW"
 972                                        "\040AVX512VL"
 973                                        );
 974                         }
 975
 976                         if (cpu_stdext_feature2 != 0) {
 977                                 printf("\n  Structured Extended Features2=0x%b",
 978                                     cpu_stdext_feature2,
 979                                        "\020"
 980                                        "\001PREFETCHWT1"
 981                                        "\002AVX512VBMI"
 982                                        "\003UMIP"
 983                                        "\004PKU"
 984                                        "\005OSPKE"
 985                                        "\006WAITPKG"
 986                                        "\011GFNI"
 987                                        "\027RDPID"
 988                                        "\032CLDEMOTE"
 989                                        "\034MOVDIRI"
 990                                        "\035MOVDIRI64B"
 991                                        "\037SGXLC"
 992                                        );
 993                         }
 994
 995                         if (cpu_stdext_feature3 != 0) {
 996                                 printf("\n  Structured Extended Features3=0x%b",
 997                                     cpu_stdext_feature3,
 998                                        "\020"
 999                                        "\013MD_CLEAR"
1000                                        "\016TSXFA"
1001                                        "\033IBPB"
1002                                        "\034STIBP"
1003                                        "\035L1DFL"
1004                                        "\036ARCH_CAP"
1005                                        "\037CORE_CAP"
1006                                        "\040SSBD"
1007                                        );
1008                         }
1009
1010                         if ((cpu_feature2 & CPUID2_XSAVE) != 0) {
1011                                 cpuid_count(0xd, 0x1, regs);
1012                                 if (regs[0] != 0) {
1013                                         printf("\n  XSAVE Features=0x%b",
1014                                             regs[0],
1015                                             "\020"
1016                                             "\001XSAVEOPT"
1017                                             "\002XSAVEC"
1018                                             "\003XINUSE"
1019                                             "\004XSAVES");
1020                                 }
1021                         }
1022
1023                         if (cpu_ia32_arch_caps != 0) {
1024                                 printf("\n  IA32_ARCH_CAPS=0x%b",
1025                                     (u_int)cpu_ia32_arch_caps,
1026                                        "\020"
1027                                        "\001RDCL_NO"
1028                                        "\002IBRS_ALL"
1029                                        "\003RSBA"
1030                                        "\004SKIP_L1DFL_VME"
1031                                        "\005SSB_NO"
1032                                        );
1033                         }
1034
1035                         if (amd_extended_feature_extensions != 0) {
1036                                 u_int amd_fe_masked;
1037
1038                                 amd_fe_masked = amd_extended_feature_extensions;
1039                                 if ((amd_fe_masked & AMDFEID_IBRS) == 0)
1040                                         amd_fe_masked &=
1041                                             ~(AMDFEID_IBRS_ALWAYSON |
1042                                                 AMDFEID_PREFER_IBRS);
1043                                 if ((amd_fe_masked & AMDFEID_STIBP) == 0)
1044                                         amd_fe_masked &=
1045                                             ~AMDFEID_STIBP_ALWAYSON;
1046
1047                                 printf("\n  "
1048                                     "AMD Extended Feature Extensions ID EBX="
1049                                     "0x%b", amd_fe_masked,
1050                                     "\020"
1051                                     "\001CLZERO"
1052                                     "\002IRPerf"
1053                                     "\003XSaveErPtr"
1054                                     "\015IBPB"
1055                                     "\017IBRS"
1056                                     "\020STIBP"
1057                                     "\021IBRS_ALWAYSON"
1058                                     "\022STIBP_ALWAYSON"
1059                                     "\023PREFER_IBRS"
1060                                     "\031SSBD"
1061                                     "\032VIRT_SSBD"
1062                                     "\033SSB_NO"
1063                                     );
1064                         }
1065
1066                         if (via_feature_rng != 0 || via_feature_xcrypt != 0)
1067                                 print_via_padlock_info();
1068
1069                         if (cpu_feature2 & CPUID2_VMX)
1070                                 print_vmx_info();
1071
1072                         if (amd_feature2 & AMDID2_SVM)
1073                                 print_svm_info();
1074
1075                         if ((cpu_feature & CPUID_HTT) &&
1076                             cpu_vendor_id == CPU_VENDOR_AMD)
1077                                 cpu_feature &= ~CPUID_HTT;
1078
1079                         /*
1080                          * If this CPU supports P-state invariant TSC then
1081                          * mention the capability.
1082                          */
1083                         if (tsc_is_invariant) {
1084                                 printf("\n  TSC: P-state invariant");
1085                                 if (tsc_perf_stat)
1086                                         printf(", performance statistics");
1087                         }
1088                 }
1089 #ifdef __i386__
1090         } else if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
1091                 printf("  DIR=0x%04x", cyrix_did);
1092                 printf("  Stepping=%u", (cyrix_did & 0xf000) >> 12);
1093                 printf("  Revision=%u", (cyrix_did & 0x0f00) >> 8);
1094 #ifndef CYRIX_CACHE_REALLY_WORKS
1095                 if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700)
1096                         printf("\n  CPU cache: write-through mode");
1097 #endif
1098 #endif
1099         }
1100
1101         /* Avoid ugly blank lines: only print newline when we have to. */
1102         if (*cpu_vendor || cpu_id)
1103                 printf("\n");
1104
1105         if (bootverbose) {
1106                 if (cpu_vendor_id == CPU_VENDOR_AMD)
1107                         print_AMD_info();
1108                 else if (cpu_vendor_id == CPU_VENDOR_INTEL)
1109                         print_INTEL_info();
1110 #ifdef __i386__
1111                 else if (cpu_vendor_id == CPU_VENDOR_TRANSMETA)
1112                         print_transmeta_info();
1113 #endif
1114         }
1115
1116         print_hypervisor_info();
1117 }
1118
1119 #ifdef __i386__
1120 void
1121 panicifcpuunsupported(void)
1122 {
1123
1124 #if !defined(lint)
1125 #if !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU)
1126 #error This kernel is not configured for one of the supported CPUs
1127 #endif
1128 #else /* lint */
1129 #endif /* lint */
1130         /*
1131          * Now that we have told the user what they have,
1132          * let them know if that machine type isn't configured.
1133          */
1134         switch (cpu_class) {
1135         case CPUCLASS_286:      /* a 286 should not make it this far, anyway */
1136         case CPUCLASS_386:
1137 #if !defined(I486_CPU)
1138         case CPUCLASS_486:
1139 #endif
1140 #if !defined(I586_CPU)
1141         case CPUCLASS_586:
1142 #endif
1143 #if !defined(I686_CPU)
1144         case CPUCLASS_686:
1145 #endif
1146                 panic("CPU class not configured");
1147         default:
1148                 break;
1149         }
1150 }
1151
1152 static  volatile u_int trap_by_rdmsr;
1153
1154 /*
1155  * Special exception 6 handler.
1156  * The rdmsr instruction generates invalid opcodes fault on 486-class
1157  * Cyrix CPU.  Stacked eip register points the rdmsr instruction in the
1158  * function identblue() when this handler is called.  Stacked eip should
1159  * be advanced.
1160  */
1161 inthand_t       bluetrap6;
1162 #ifdef __GNUCLIKE_ASM
1163 __asm
1164 ("                                                                      \n\
1165         .text                                                           \n\
1166         .p2align 2,0x90                                                 \n\
1167         .type   " __XSTRING(CNAME(bluetrap6)) ",@function               \n\
1168 " __XSTRING(CNAME(bluetrap6)) ":                                        \n\
1169         ss                                                              \n\
1170         movl    $0xa8c1d," __XSTRING(CNAME(trap_by_rdmsr)) "            \n\
1171         addl    $2, (%esp)      /* rdmsr is a 2-byte instruction */     \n\
1172         iret                                                            \n\
1173 ");
1174 #endif
1175
1176 /*
1177  * Special exception 13 handler.
1178  * Accessing non-existent MSR generates general protection fault.
1179  */
1180 inthand_t       bluetrap13;
1181 #ifdef __GNUCLIKE_ASM
1182 __asm
1183 ("                                                                      \n\
1184         .text                                                           \n\
1185         .p2align 2,0x90                                                 \n\
1186         .type   " __XSTRING(CNAME(bluetrap13)) ",@function              \n\
1187 " __XSTRING(CNAME(bluetrap13)) ":                                       \n\
1188         ss                                                              \n\
1189         movl    $0xa89c4," __XSTRING(CNAME(trap_by_rdmsr)) "            \n\
1190         popl    %eax            /* discard error code */                \n\
1191         addl    $2, (%esp)      /* rdmsr is a 2-byte instruction */     \n\
1192         iret                                                            \n\
1193 ");
1194 #endif
1195
1196 /*
1197  * Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not
1198  * support cpuid instruction.  This function should be called after
1199  * loading interrupt descriptor table register.
1200  *
1201  * I don't like this method that handles fault, but I couldn't get
1202  * information for any other methods.  Does blue giant know?
1203  */
1204 static int
1205 identblue(void)
1206 {
1207
1208         trap_by_rdmsr = 0;
1209
1210         /*
1211          * Cyrix 486-class CPU does not support rdmsr instruction.
1212          * The rdmsr instruction generates invalid opcode fault, and exception
1213          * will be trapped by bluetrap6() on Cyrix 486-class CPU.  The
1214          * bluetrap6() set the magic number to trap_by_rdmsr.
1215          */
1216         setidt(IDT_UD, bluetrap6, SDT_SYS386TGT, SEL_KPL,
1217             GSEL(GCODE_SEL, SEL_KPL));
1218
1219         /*
1220          * Certain BIOS disables cpuid instruction of Cyrix 6x86MX CPU.
1221          * In this case, rdmsr generates general protection fault, and
1222          * exception will be trapped by bluetrap13().
1223          */
1224         setidt(IDT_GP, bluetrap13, SDT_SYS386TGT, SEL_KPL,
1225             GSEL(GCODE_SEL, SEL_KPL));
1226
1227         rdmsr(0x1002);          /* Cyrix CPU generates fault. */
1228
1229         if (trap_by_rdmsr == 0xa8c1d)
1230                 return IDENTBLUE_CYRIX486;
1231         else if (trap_by_rdmsr == 0xa89c4)
1232                 return IDENTBLUE_CYRIXM2;
1233         return IDENTBLUE_IBMCPU;
1234 }
1235
1236
1237 /*
1238  * identifycyrix() set lower 16 bits of cyrix_did as follows:
1239  *
1240  *  F E D C B A 9 8 7 6 5 4 3 2 1 0
1241  * +-------+-------+---------------+
1242  * |  SID  |  RID  |   Device ID   |
1243  * |    (DIR 1)    |    (DIR 0)    |
1244  * +-------+-------+---------------+
1245  */
1246 static void
1247 identifycyrix(void)
1248 {
1249         register_t saveintr;
1250         int     ccr2_test = 0, dir_test = 0;
1251         u_char  ccr2, ccr3;
1252
1253         saveintr = intr_disable();
1254
1255         ccr2 = read_cyrix_reg(CCR2);
1256         write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW);
1257         read_cyrix_reg(CCR2);
1258         if (read_cyrix_reg(CCR2) != ccr2)
1259                 ccr2_test = 1;
1260         write_cyrix_reg(CCR2, ccr2);
1261
1262         ccr3 = read_cyrix_reg(CCR3);
1263         write_cyrix_reg(CCR3, ccr3 ^ CCR3_MAPEN3);
1264         read_cyrix_reg(CCR3);
1265         if (read_cyrix_reg(CCR3) != ccr3)
1266                 dir_test = 1;                                   /* CPU supports DIRs. */
1267         write_cyrix_reg(CCR3, ccr3);
1268
1269         if (dir_test) {
1270                 /* Device ID registers are available. */
1271                 cyrix_did = read_cyrix_reg(DIR1) << 8;
1272                 cyrix_did += read_cyrix_reg(DIR0);
1273         } else if (ccr2_test)
1274                 cyrix_did = 0x0010;             /* 486S A-step */
1275         else
1276                 cyrix_did = 0x00ff;             /* Old 486SLC/DLC and TI486SXLC/SXL */
1277
1278         intr_restore(saveintr);
1279 }
1280 #endif
1281
1282 /* Update TSC freq with the value indicated by the caller. */
1283 static void
1284 tsc_freq_changed(void *arg __unused, const struct cf_level *level, int status)
1285 {
1286
1287         /* If there was an error during the transition, don't do anything. */
1288         if (status != 0)
1289                 return;
1290
1291         /* Total setting for this level gives the new frequency in MHz. */
1292         hw_clockrate = level->total_set.freq;
1293 }
1294
1295 static void
1296 hook_tsc_freq(void *arg __unused)
1297 {
1298
1299         if (tsc_is_invariant)
1300                 return;
1301
1302         tsc_post_tag = EVENTHANDLER_REGISTER(cpufreq_post_change,
1303             tsc_freq_changed, NULL, EVENTHANDLER_PRI_ANY);
1304 }
1305
1306 SYSINIT(hook_tsc_freq, SI_SUB_CONFIGURE, SI_ORDER_ANY, hook_tsc_freq, NULL);
1307
1308 static const struct {
1309         const char *    vm_bname;
1310         int             vm_guest;
1311 } vm_bnames[] = {
1312         { "QEMU",       VM_GUEST_VM },          /* QEMU */
1313         { "Plex86",     VM_GUEST_VM },          /* Plex86 */
1314         { "Bochs",      VM_GUEST_VM },          /* Bochs */
1315         { "Xen",        VM_GUEST_XEN },         /* Xen */
1316         { "BHYVE",      VM_GUEST_BHYVE },       /* bhyve */
1317         { "Seabios",    VM_GUEST_KVM },         /* KVM */
1318 };
1319
1320 static const struct {
1321         const char *    vm_pname;
1322         int             vm_guest;
1323 } vm_pnames[] = {
1324         { "VMware Virtual Platform",    VM_GUEST_VMWARE },
1325         { "Virtual Machine",            VM_GUEST_VM }, /* Microsoft VirtualPC */
1326         { "VirtualBox",                 VM_GUEST_VBOX },
1327         { "Parallels Virtual Platform", VM_GUEST_PARALLELS },
1328         { "KVM",                        VM_GUEST_KVM },
1329 };
1330
1331 static struct {
1332         const char      *vm_cpuid;
1333         int             vm_guest;
1334 } vm_cpuids[] = {
1335         { "XENXENXEN",          VM_GUEST_XEN },         /* XEN */
1336         { "Microsoft Hv",       VM_GUEST_HV },          /* Microsoft Hyper-V */
1337         { "VMwareVMware",       VM_GUEST_VMWARE },      /* VMware VM */
1338         { "KVMKVMKVM",          VM_GUEST_KVM },         /* KVM */
1339         { "bhyve bhyve ",       VM_GUEST_BHYVE },       /* bhyve */
1340         { "VBoxVBoxVBox",       VM_GUEST_VBOX },        /* VirtualBox */
1341 };
1342
1343 static void
1344 identify_hypervisor_cpuid_base(void)
1345 {
1346         u_int leaf, regs[4];
1347         int i;
1348
1349         /*
1350          * [RFC] CPUID usage for interaction between Hypervisors and Linux.
1351          * http://lkml.org/lkml/2008/10/1/246
1352          *
1353          * KB1009458: Mechanisms to determine if software is running in
1354          * a VMware virtual machine
1355          * http://kb.vmware.com/kb/1009458
1356          *
1357          * Search for a hypervisor that we recognize. If we cannot find
1358          * a specific hypervisor, return the first information about the
1359          * hypervisor that we found, as others may be able to use.
1360          */
1361         for (leaf = 0x40000000; leaf < 0x40010000; leaf += 0x100) {
1362                 do_cpuid(leaf, regs);
1363
1364                 /*
1365                  * KVM from Linux kernels prior to commit
1366                  * 57c22e5f35aa4b9b2fe11f73f3e62bbf9ef36190 set %eax
1367                  * to 0 rather than a valid hv_high value.  Check for
1368                  * the KVM signature bytes and fixup %eax to the
1369                  * highest supported leaf in that case.
1370                  */
1371                 if (regs[0] == 0 && regs[1] == 0x4b4d564b &&
1372                     regs[2] == 0x564b4d56 && regs[3] == 0x0000004d)
1373                         regs[0] = leaf + 1;
1374
1375                 if (regs[0] >= leaf) {
1376                         for (i = 0; i < nitems(vm_cpuids); i++)
1377                                 if (strncmp((const char *)&regs[1],
1378                                     vm_cpuids[i].vm_cpuid, 12) == 0) {
1379                                         vm_guest = vm_cpuids[i].vm_guest;
1380                                         break;
1381                                 }
1382
1383                         /*
1384                          * If this is the first entry or we found a
1385                          * specific hypervisor, record the base, high value,
1386                          * and vendor identifier.
1387                          */
1388                         if (vm_guest != VM_GUEST_VM || leaf == 0x40000000) {
1389                                 hv_base = leaf;
1390                                 hv_high = regs[0];
1391                                 ((u_int *)&hv_vendor)[0] = regs[1];
1392                                 ((u_int *)&hv_vendor)[1] = regs[2];
1393                                 ((u_int *)&hv_vendor)[2] = regs[3];
1394                                 hv_vendor[12] = '\0';
1395
1396                                 /*
1397                                  * If we found a specific hypervisor, then
1398                                  * we are finished.
1399                                  */
1400                                 if (vm_guest != VM_GUEST_VM)
1401                                         return;
1402                         }
1403                 }
1404         }
1405 }
1406
1407 void
1408 identify_hypervisor(void)
1409 {
1410         u_int regs[4];
1411         char *p;
1412         int i;
1413
1414         /*
1415          * If CPUID2_HV is set, we are running in a hypervisor environment.
1416          */
1417         if (cpu_feature2 & CPUID2_HV) {
1418                 vm_guest = VM_GUEST_VM;
1419                 identify_hypervisor_cpuid_base();
1420
1421                 /* If we have a definitive vendor, we can return now. */
1422                 if (*hv_vendor != '\0')
1423                         return;
1424         }
1425
1426         /*
1427          * Examine SMBIOS strings for older hypervisors.
1428          */
1429         p = kern_getenv("smbios.system.serial");
1430         if (p != NULL) {
1431                 if (strncmp(p, "VMware-", 7) == 0 || strncmp(p, "VMW", 3) == 0) {
1432                         vmware_hvcall(VMW_HVCMD_GETVERSION, regs);
1433                         if (regs[1] == VMW_HVMAGIC) {
1434                                 vm_guest = VM_GUEST_VMWARE;
1435                                 freeenv(p);
1436                                 return;
1437                         }
1438                 }
1439                 freeenv(p);
1440         }
1441
1442         /*
1443          * XXX: Some of these entries may not be needed since they were
1444          * added to FreeBSD before the checks above.
1445          */
1446         p = kern_getenv("smbios.bios.vendor");
1447         if (p != NULL) {
1448                 for (i = 0; i < nitems(vm_bnames); i++)
1449                         if (strcmp(p, vm_bnames[i].vm_bname) == 0) {
1450                                 vm_guest = vm_bnames[i].vm_guest;
1451                                 /* If we have a specific match, return */
1452                                 if (vm_guest != VM_GUEST_VM) {
1453                                         freeenv(p);
1454                                         return;
1455                                 }
1456                                 /*
1457                                  * We are done with bnames, but there might be
1458                                  * a more specific match in the pnames
1459                                  */
1460                                 break;
1461                         }
1462                 freeenv(p);
1463         }
1464         p = kern_getenv("smbios.system.product");
1465         if (p != NULL) {
1466                 for (i = 0; i < nitems(vm_pnames); i++)
1467                         if (strcmp(p, vm_pnames[i].vm_pname) == 0) {
1468                                 vm_guest = vm_pnames[i].vm_guest;
1469                                 freeenv(p);
1470                                 return;
1471                         }
1472                 freeenv(p);
1473         }
1474 }
1475
1476 bool
1477 fix_cpuid(void)
1478 {
1479         uint64_t msr;
1480
1481         /*
1482          * Clear "Limit CPUID Maxval" bit and return true if the caller should
1483          * get the largest standard CPUID function number again if it is set
1484          * from BIOS.  It is necessary for probing correct CPU topology later
1485          * and for the correct operation of the AVX-aware userspace.
1486          */
1487         if (cpu_vendor_id == CPU_VENDOR_INTEL &&
1488             ((CPUID_TO_FAMILY(cpu_id) == 0xf &&
1489             CPUID_TO_MODEL(cpu_id) >= 0x3) ||
1490             (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
1491             CPUID_TO_MODEL(cpu_id) >= 0xe))) {
1492                 msr = rdmsr(MSR_IA32_MISC_ENABLE);
1493                 if ((msr & IA32_MISC_EN_LIMCPUID) != 0) {
1494                         msr &= ~IA32_MISC_EN_LIMCPUID;
1495                         wrmsr(MSR_IA32_MISC_ENABLE, msr);
1496                         return (true);
1497                 }
1498         }
1499
1500         /*
1501          * Re-enable AMD Topology Extension that could be disabled by BIOS
1502          * on some notebook processors.  Without the extension it's really
1503          * hard to determine the correct CPU cache topology.
1504          * See BIOS and Kernel Developer’s Guide (BKDG) for AMD Family 15h
1505          * Models 60h-6Fh Processors, Publication # 50742.
1506          */
1507         if (vm_guest == VM_GUEST_NO && cpu_vendor_id == CPU_VENDOR_AMD &&
1508             CPUID_TO_FAMILY(cpu_id) == 0x15) {
1509                 msr = rdmsr(MSR_EXTFEATURES);
1510                 if ((msr & ((uint64_t)1 << 54)) == 0) {
1511                         msr |= (uint64_t)1 << 54;
1512                         wrmsr(MSR_EXTFEATURES, msr);
1513                         return (true);
1514                 }
1515         }
1516         return (false);
1517 }
1518
1519 void
1520 identify_cpu1(void)
1521 {
1522         u_int regs[4];
1523
1524         do_cpuid(0, regs);
1525         cpu_high = regs[0];
1526         ((u_int *)&cpu_vendor)[0] = regs[1];
1527         ((u_int *)&cpu_vendor)[1] = regs[3];
1528         ((u_int *)&cpu_vendor)[2] = regs[2];
1529         cpu_vendor[12] = '\0';
1530
1531         do_cpuid(1, regs);
1532         cpu_id = regs[0];
1533         cpu_procinfo = regs[1];
1534         cpu_feature = regs[3];
1535         cpu_feature2 = regs[2];
1536 }
1537
1538 void
1539 identify_cpu2(void)
1540 {
1541         u_int regs[4], cpu_stdext_disable;
1542
1543         if (cpu_high >= 7) {
1544                 cpuid_count(7, 0, regs);
1545                 cpu_stdext_feature = regs[1];
1546
1547                 /*
1548                  * Some hypervisors failed to filter out unsupported
1549                  * extended features.  Allow to disable the
1550                  * extensions, activation of which requires setting a
1551                  * bit in CR4, and which VM monitors do not support.
1552                  */
1553                 cpu_stdext_disable = 0;
1554                 TUNABLE_INT_FETCH("hw.cpu_stdext_disable", &cpu_stdext_disable);
1555                 cpu_stdext_feature &= ~cpu_stdext_disable;
1556
1557                 cpu_stdext_feature2 = regs[2];
1558                 cpu_stdext_feature3 = regs[3];
1559
1560                 if ((cpu_stdext_feature3 & CPUID_STDEXT3_ARCH_CAP) != 0)
1561                         cpu_ia32_arch_caps = rdmsr(MSR_IA32_ARCH_CAP);
1562         }
1563 }
1564
1565 void
1566 identify_cpu_fixup_bsp(void)
1567 {
1568         u_int regs[4];
1569
1570         cpu_vendor_id = find_cpu_vendor_id();
1571
1572         if (fix_cpuid()) {
1573                 do_cpuid(0, regs);
1574                 cpu_high = regs[0];
1575         }
1576 }
1577
1578 /*
1579  * Final stage of CPU identification.
1580  */
1581 void
1582 finishidentcpu(void)
1583 {
1584         u_int regs[4];
1585 #ifdef __i386__
1586         u_char ccr3;
1587 #endif
1588
1589         identify_cpu_fixup_bsp();
1590
1591         if (cpu_high >= 5 && (cpu_feature2 & CPUID2_MON) != 0) {
1592                 do_cpuid(5, regs);
1593                 cpu_mon_mwait_flags = regs[2];
1594                 cpu_mon_min_size = regs[0] &  CPUID5_MON_MIN_SIZE;
1595                 cpu_mon_max_size = regs[1] &  CPUID5_MON_MAX_SIZE;
1596         }
1597
1598         identify_cpu2();
1599
1600 #ifdef __i386__
1601         if (cpu_high > 0 &&
1602             (cpu_vendor_id == CPU_VENDOR_INTEL ||
1603              cpu_vendor_id == CPU_VENDOR_AMD ||
1604              cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
1605              cpu_vendor_id == CPU_VENDOR_CENTAUR ||
1606              cpu_vendor_id == CPU_VENDOR_NSC)) {
1607                 do_cpuid(0x80000000, regs);
1608                 if (regs[0] >= 0x80000000)
1609                         cpu_exthigh = regs[0];
1610         }
1611 #else
1612         if (cpu_vendor_id == CPU_VENDOR_INTEL ||
1613             cpu_vendor_id == CPU_VENDOR_AMD ||
1614             cpu_vendor_id == CPU_VENDOR_CENTAUR) {
1615                 do_cpuid(0x80000000, regs);
1616                 cpu_exthigh = regs[0];
1617         }
1618 #endif
1619         if (cpu_exthigh >= 0x80000001) {
1620                 do_cpuid(0x80000001, regs);
1621                 amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff);
1622                 amd_feature2 = regs[2];
1623         }
1624         if (cpu_exthigh >= 0x80000007) {
1625                 do_cpuid(0x80000007, regs);
1626                 amd_rascap = regs[1];
1627                 amd_pminfo = regs[3];
1628         }
1629         if (cpu_exthigh >= 0x80000008) {
1630                 do_cpuid(0x80000008, regs);
1631                 cpu_maxphyaddr = regs[0] & 0xff;
1632                 amd_extended_feature_extensions = regs[1];
1633                 cpu_procinfo2 = regs[2];
1634         } else {
1635                 cpu_maxphyaddr = (cpu_feature & CPUID_PAE) != 0 ? 36 : 32;
1636         }
1637
1638 #ifdef __i386__
1639         if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
1640                 if (cpu == CPU_486) {
1641                         /*
1642                          * These conditions are equivalent to:
1643                          *     - CPU does not support cpuid instruction.
1644                          *     - Cyrix/IBM CPU is detected.
1645                          */
1646                         if (identblue() == IDENTBLUE_IBMCPU) {
1647                                 strcpy(cpu_vendor, "IBM");
1648                                 cpu_vendor_id = CPU_VENDOR_IBM;
1649                                 cpu = CPU_BLUE;
1650                                 return;
1651                         }
1652                 }
1653                 switch (cpu_id & 0xf00) {
1654                 case 0x600:
1655                         /*
1656                          * Cyrix's datasheet does not describe DIRs.
1657                          * Therefor, I assume it does not have them
1658                          * and use the result of the cpuid instruction.
1659                          * XXX they seem to have it for now at least. -Peter
1660                          */
1661                         identifycyrix();
1662                         cpu = CPU_M2;
1663                         break;
1664                 default:
1665                         identifycyrix();
1666                         /*
1667                          * This routine contains a trick.
1668                          * Don't check (cpu_id & 0x00f0) == 0x50 to detect M2, now.
1669                          */
1670                         switch (cyrix_did & 0x00f0) {
1671                         case 0x00:
1672                         case 0xf0:
1673                                 cpu = CPU_486DLC;
1674                                 break;
1675                         case 0x10:
1676                                 cpu = CPU_CY486DX;
1677                                 break;
1678                         case 0x20:
1679                                 if ((cyrix_did & 0x000f) < 8)
1680                                         cpu = CPU_M1;
1681                                 else
1682                                         cpu = CPU_M1SC;
1683                                 break;
1684                         case 0x30:
1685                                 cpu = CPU_M1;
1686                                 break;
1687                         case 0x40:
1688                                 /* MediaGX CPU */
1689                                 cpu = CPU_M1SC;
1690                                 break;
1691                         default:
1692                                 /* M2 and later CPUs are treated as M2. */
1693                                 cpu = CPU_M2;
1694
1695                                 /*
1696                                  * enable cpuid instruction.
1697                                  */
1698                                 ccr3 = read_cyrix_reg(CCR3);
1699                                 write_cyrix_reg(CCR3, CCR3_MAPEN0);
1700                                 write_cyrix_reg(CCR4, read_cyrix_reg(CCR4) | CCR4_CPUID);
1701                                 write_cyrix_reg(CCR3, ccr3);
1702
1703                                 do_cpuid(0, regs);
1704                                 cpu_high = regs[0];     /* eax */
1705                                 do_cpuid(1, regs);
1706                                 cpu_id = regs[0];       /* eax */
1707                                 cpu_feature = regs[3];  /* edx */
1708                                 break;
1709                         }
1710                 }
1711         } else if (cpu == CPU_486 && *cpu_vendor == '\0') {
1712                 /*
1713                  * There are BlueLightning CPUs that do not change
1714                  * undefined flags by dividing 5 by 2.  In this case,
1715                  * the CPU identification routine in locore.s leaves
1716                  * cpu_vendor null string and puts CPU_486 into the
1717                  * cpu.
1718                  */
1719                 if (identblue() == IDENTBLUE_IBMCPU) {
1720                         strcpy(cpu_vendor, "IBM");
1721                         cpu_vendor_id = CPU_VENDOR_IBM;
1722                         cpu = CPU_BLUE;
1723                         return;
1724                 }
1725         }
1726 #endif
1727 }
1728
1729 int
1730 pti_get_default(void)
1731 {
1732
1733         if (strcmp(cpu_vendor, AMD_VENDOR_ID) == 0)
1734                 return (0);
1735         if ((cpu_ia32_arch_caps & IA32_ARCH_CAP_RDCL_NO) != 0)
1736                 return (0);
1737         return (1);
1738 }
1739
1740 static u_int
1741 find_cpu_vendor_id(void)
1742 {
1743         int     i;
1744
1745         for (i = 0; i < nitems(cpu_vendors); i++)
1746                 if (strcmp(cpu_vendor, cpu_vendors[i].vendor) == 0)
1747                         return (cpu_vendors[i].vendor_id);
1748         return (0);
1749 }
1750
1751 static void
1752 print_AMD_assoc(int i)
1753 {
1754         if (i == 255)
1755                 printf(", fully associative\n");
1756         else
1757                 printf(", %d-way associative\n", i);
1758 }
1759
1760 static void
1761 print_AMD_l2_assoc(int i)
1762 {
1763         switch (i & 0x0f) {
1764         case 0: printf(", disabled/not present\n"); break;
1765         case 1: printf(", direct mapped\n"); break;
1766         case 2: printf(", 2-way associative\n"); break;
1767         case 4: printf(", 4-way associative\n"); break;
1768         case 6: printf(", 8-way associative\n"); break;
1769         case 8: printf(", 16-way associative\n"); break;
1770         case 15: printf(", fully associative\n"); break;
1771         default: printf(", reserved configuration\n"); break;
1772         }
1773 }
1774
1775 static void
1776 print_AMD_info(void)
1777 {
1778 #ifdef __i386__
1779         uint64_t amd_whcr;
1780 #endif
1781         u_int regs[4];
1782
1783         if (cpu_exthigh >= 0x80000005) {
1784                 do_cpuid(0x80000005, regs);
1785                 printf("L1 2MB data TLB: %d entries", (regs[0] >> 16) & 0xff);
1786                 print_AMD_assoc(regs[0] >> 24);
1787
1788                 printf("L1 2MB instruction TLB: %d entries", regs[0] & 0xff);
1789                 print_AMD_assoc((regs[0] >> 8) & 0xff);
1790
1791                 printf("L1 4KB data TLB: %d entries", (regs[1] >> 16) & 0xff);
1792                 print_AMD_assoc(regs[1] >> 24);
1793
1794                 printf("L1 4KB instruction TLB: %d entries", regs[1] & 0xff);
1795                 print_AMD_assoc((regs[1] >> 8) & 0xff);
1796
1797                 printf("L1 data cache: %d kbytes", regs[2] >> 24);
1798                 printf(", %d bytes/line", regs[2] & 0xff);
1799                 printf(", %d lines/tag", (regs[2] >> 8) & 0xff);
1800                 print_AMD_assoc((regs[2] >> 16) & 0xff);
1801
1802                 printf("L1 instruction cache: %d kbytes", regs[3] >> 24);
1803                 printf(", %d bytes/line", regs[3] & 0xff);
1804                 printf(", %d lines/tag", (regs[3] >> 8) & 0xff);
1805                 print_AMD_assoc((regs[3] >> 16) & 0xff);
1806         }
1807
1808         if (cpu_exthigh >= 0x80000006) {
1809                 do_cpuid(0x80000006, regs);
1810                 if ((regs[0] >> 16) != 0) {
1811                         printf("L2 2MB data TLB: %d entries",
1812                             (regs[0] >> 16) & 0xfff);
1813                         print_AMD_l2_assoc(regs[0] >> 28);
1814                         printf("L2 2MB instruction TLB: %d entries",
1815                             regs[0] & 0xfff);
1816                         print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
1817                 } else {
1818                         printf("L2 2MB unified TLB: %d entries",
1819                             regs[0] & 0xfff);
1820                         print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
1821                 }
1822                 if ((regs[1] >> 16) != 0) {
1823                         printf("L2 4KB data TLB: %d entries",
1824                             (regs[1] >> 16) & 0xfff);
1825                         print_AMD_l2_assoc(regs[1] >> 28);
1826
1827                         printf("L2 4KB instruction TLB: %d entries",
1828                             (regs[1] >> 16) & 0xfff);
1829                         print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
1830                 } else {
1831                         printf("L2 4KB unified TLB: %d entries",
1832                             (regs[1] >> 16) & 0xfff);
1833                         print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
1834                 }
1835                 printf("L2 unified cache: %d kbytes", regs[2] >> 16);
1836                 printf(", %d bytes/line", regs[2] & 0xff);
1837                 printf(", %d lines/tag", (regs[2] >> 8) & 0x0f);
1838                 print_AMD_l2_assoc((regs[2] >> 12) & 0x0f);
1839         }
1840
1841 #ifdef __i386__
1842         if (((cpu_id & 0xf00) == 0x500)
1843             && (((cpu_id & 0x0f0) > 0x80)
1844                 || (((cpu_id & 0x0f0) == 0x80)
1845                     && (cpu_id & 0x00f) > 0x07))) {
1846                 /* K6-2(new core [Stepping 8-F]), K6-III or later */
1847                 amd_whcr = rdmsr(0xc0000082);
1848                 if (!(amd_whcr & (0x3ff << 22))) {
1849                         printf("Write Allocate Disable\n");
1850                 } else {
1851                         printf("Write Allocate Enable Limit: %dM bytes\n",
1852                             (u_int32_t)((amd_whcr & (0x3ff << 22)) >> 22) * 4);
1853                         printf("Write Allocate 15-16M bytes: %s\n",
1854                             (amd_whcr & (1 << 16)) ? "Enable" : "Disable");
1855                 }
1856         } else if (((cpu_id & 0xf00) == 0x500)
1857                    && ((cpu_id & 0x0f0) > 0x50)) {
1858                 /* K6, K6-2(old core) */
1859                 amd_whcr = rdmsr(0xc0000082);
1860                 if (!(amd_whcr & (0x7f << 1))) {
1861                         printf("Write Allocate Disable\n");
1862                 } else {
1863                         printf("Write Allocate Enable Limit: %dM bytes\n",
1864                             (u_int32_t)((amd_whcr & (0x7f << 1)) >> 1) * 4);
1865                         printf("Write Allocate 15-16M bytes: %s\n",
1866                             (amd_whcr & 0x0001) ? "Enable" : "Disable");
1867                         printf("Hardware Write Allocate Control: %s\n",
1868                             (amd_whcr & 0x0100) ? "Enable" : "Disable");
1869                 }
1870         }
1871 #endif
1872         /*
1873          * Opteron Rev E shows a bug as in very rare occasions a read memory
1874          * barrier is not performed as expected if it is followed by a
1875          * non-atomic read-modify-write instruction.
1876          * As long as that bug pops up very rarely (intensive machine usage
1877          * on other operating systems generally generates one unexplainable
1878          * crash any 2 months) and as long as a model specific fix would be
1879          * impractical at this stage, print out a warning string if the broken
1880          * model and family are identified.
1881          */
1882         if (CPUID_TO_FAMILY(cpu_id) == 0xf && CPUID_TO_MODEL(cpu_id) >= 0x20 &&
1883             CPUID_TO_MODEL(cpu_id) <= 0x3f)
1884                 printf("WARNING: This architecture revision has known SMP "
1885                     "hardware bugs which may cause random instability\n");
1886 }
1887
1888 static void
1889 print_INTEL_info(void)
1890 {
1891         u_int regs[4];
1892         u_int rounds, regnum;
1893         u_int nwaycode, nway;
1894
1895         if (cpu_high >= 2) {
1896                 rounds = 0;
1897                 do {
1898                         do_cpuid(0x2, regs);
1899                         if (rounds == 0 && (rounds = (regs[0] & 0xff)) == 0)
1900                                 break;  /* we have a buggy CPU */
1901
1902                         for (regnum = 0; regnum <= 3; ++regnum) {
1903                                 if (regs[regnum] & (1<<31))
1904                                         continue;
1905                                 if (regnum != 0)
1906                                         print_INTEL_TLB(regs[regnum] & 0xff);
1907                                 print_INTEL_TLB((regs[regnum] >> 8) & 0xff);
1908                                 print_INTEL_TLB((regs[regnum] >> 16) & 0xff);
1909                                 print_INTEL_TLB((regs[regnum] >> 24) & 0xff);
1910                         }
1911                 } while (--rounds > 0);
1912         }
1913
1914         if (cpu_exthigh >= 0x80000006) {
1915                 do_cpuid(0x80000006, regs);
1916                 nwaycode = (regs[2] >> 12) & 0x0f;
1917                 if (nwaycode >= 0x02 && nwaycode <= 0x08)
1918                         nway = 1 << (nwaycode / 2);
1919                 else
1920                         nway = 0;
1921                 printf("L2 cache: %u kbytes, %u-way associative, %u bytes/line\n",
1922                     (regs[2] >> 16) & 0xffff, nway, regs[2] & 0xff);
1923         }
1924 }
1925
1926 static void
1927 print_INTEL_TLB(u_int data)
1928 {
1929         switch (data) {
1930         case 0x0:
1931         case 0x40:
1932         default:
1933                 break;
1934         case 0x1:
1935                 printf("Instruction TLB: 4 KB pages, 4-way set associative, 32 entries\n");
1936                 break;
1937         case 0x2:
1938                 printf("Instruction TLB: 4 MB pages, fully associative, 2 entries\n");
1939                 break;
1940         case 0x3:
1941                 printf("Data TLB: 4 KB pages, 4-way set associative, 64 entries\n");
1942                 break;
1943         case 0x4:
1944                 printf("Data TLB: 4 MB Pages, 4-way set associative, 8 entries\n");
1945                 break;
1946         case 0x6:
1947                 printf("1st-level instruction cache: 8 KB, 4-way set associative, 32 byte line size\n");
1948                 break;
1949         case 0x8:
1950                 printf("1st-level instruction cache: 16 KB, 4-way set associative, 32 byte line size\n");
1951                 break;
1952         case 0x9:
1953                 printf("1st-level instruction cache: 32 KB, 4-way set associative, 64 byte line size\n");
1954                 break;
1955         case 0xa:
1956                 printf("1st-level data cache: 8 KB, 2-way set associative, 32 byte line size\n");
1957                 break;
1958         case 0xb:
1959                 printf("Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries\n");
1960                 break;
1961         case 0xc:
1962                 printf("1st-level data cache: 16 KB, 4-way set associative, 32 byte line size\n");
1963                 break;
1964         case 0xd:
1965                 printf("1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size");
1966                 break;
1967         case 0xe:
1968                 printf("1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size\n");
1969                 break;
1970         case 0x1d:
1971                 printf("2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size\n");
1972                 break;
1973         case 0x21:
1974                 printf("2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size\n");
1975                 break;
1976         case 0x22:
1977                 printf("3rd-level cache: 512 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1978                 break;
1979         case 0x23:
1980                 printf("3rd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n");
1981                 break;
1982         case 0x24:
1983                 printf("2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size\n");
1984                 break;
1985         case 0x25:
1986                 printf("3rd-level cache: 2 MB, 8-way set associative, sectored cache, 64 byte line size\n");
1987                 break;
1988         case 0x29:
1989                 printf("3rd-level cache: 4 MB, 8-way set associative, sectored cache, 64 byte line size\n");
1990                 break;
1991         case 0x2c:
1992                 printf("1st-level data cache: 32 KB, 8-way set associative, 64 byte line size\n");
1993                 break;
1994         case 0x30:
1995                 printf("1st-level instruction cache: 32 KB, 8-way set associative, 64 byte line size\n");
1996                 break;
1997         case 0x39: /* De-listed in SDM rev. 54 */
1998                 printf("2nd-level cache: 128 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1999                 break;
2000         case 0x3b: /* De-listed in SDM rev. 54 */
2001                 printf("2nd-level cache: 128 KB, 2-way set associative, sectored cache, 64 byte line size\n");
2002                 break;
2003         case 0x3c: /* De-listed in SDM rev. 54 */
2004                 printf("2nd-level cache: 256 KB, 4-way set associative, sectored cache, 64 byte line size\n");
2005                 break;
2006         case 0x41:
2007                 printf("2nd-level cache: 128 KB, 4-way set associative, 32 byte line size\n");
2008                 break;
2009         case 0x42:
2010                 printf("2nd-level cache: 256 KB, 4-way set associative, 32 byte line size\n");
2011                 break;
2012         case 0x43:
2013                 printf("2nd-level cache: 512 KB, 4-way set associative, 32 byte line size\n");
2014                 break;
2015         case 0x44:
2016                 printf("2nd-level cache: 1 MB, 4-way set associative, 32 byte line size\n");
2017                 break;
2018         case 0x45:
2019                 printf("2nd-level cache: 2 MB, 4-way set associative, 32 byte line size\n");
2020                 break;
2021         case 0x46:
2022                 printf("3rd-level cache: 4 MB, 4-way set associative, 64 byte line size\n");
2023                 break;
2024         case 0x47:
2025                 printf("3rd-level cache: 8 MB, 8-way set associative, 64 byte line size\n");
2026                 break;
2027         case 0x48:
2028                 printf("2nd-level cache: 3MByte, 12-way set associative, 64 byte line size\n");
2029                 break;
2030         case 0x49:
2031                 if (CPUID_TO_FAMILY(cpu_id) == 0xf &&
2032                     CPUID_TO_MODEL(cpu_id) == 0x6)
2033                         printf("3rd-level cache: 4MB, 16-way set associative, 64-byte line size\n");
2034                 else
2035                         printf("2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size");
2036                 break;
2037         case 0x4a:
2038                 printf("3rd-level cache: 6MByte, 12-way set associative, 64 byte line size\n");
2039                 break;
2040         case 0x4b:
2041                 printf("3rd-level cache: 8MByte, 16-way set associative, 64 byte line size\n");
2042                 break;
2043         case 0x4c:
2044                 printf("3rd-level cache: 12MByte, 12-way set associative, 64 byte line size\n");
2045                 break;
2046         case 0x4d:
2047                 printf("3rd-level cache: 16MByte, 16-way set associative, 64 byte line size\n");
2048                 break;
2049         case 0x4e:
2050                 printf("2nd-level cache: 6MByte, 24-way set associative, 64 byte line size\n");
2051                 break;
2052         case 0x4f:
2053                 printf("Instruction TLB: 4 KByte pages, 32 entries\n");
2054                 break;
2055         case 0x50:
2056                 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 64 entries\n");
2057                 break;
2058         case 0x51:
2059                 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 128 entries\n");
2060                 break;
2061         case 0x52:
2062                 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 256 entries\n");
2063                 break;
2064         case 0x55:
2065                 printf("Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries\n");
2066                 break;
2067         case 0x56:
2068                 printf("Data TLB0: 4 MByte pages, 4-way set associative, 16 entries\n");
2069                 break;
2070         case 0x57:
2071                 printf("Data TLB0: 4 KByte pages, 4-way associative, 16 entries\n");
2072                 break;
2073         case 0x59:
2074                 printf("Data TLB0: 4 KByte pages, fully associative, 16 entries\n");
2075                 break;
2076         case 0x5a:
2077                 printf("Data TLB0: 2-MByte or 4 MByte pages, 4-way set associative, 32 entries\n");
2078                 break;
2079         case 0x5b:
2080                 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 64 entries\n");
2081                 break;
2082         case 0x5c:
2083                 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 128 entries\n");
2084                 break;
2085         case 0x5d:
2086                 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 256 entries\n");
2087                 break;
2088         case 0x60:
2089                 printf("1st-level data cache: 16 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2090                 break;
2091         case 0x61:
2092                 printf("Instruction TLB: 4 KByte pages, fully associative, 48 entries\n");
2093                 break;
2094         case 0x63:
2095                 printf("Data TLB: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries and a separate array with 1 GByte pages, 4-way set associative, 4 entries\n");
2096                 break;
2097         case 0x64:
2098                 printf("Data TLB: 4 KBytes pages, 4-way set associative, 512 entries\n");
2099                 break;
2100         case 0x66:
2101                 printf("1st-level data cache: 8 KB, 4-way set associative, sectored cache, 64 byte line size\n");
2102                 break;
2103         case 0x67:
2104                 printf("1st-level data cache: 16 KB, 4-way set associative, sectored cache, 64 byte line size\n");
2105                 break;
2106         case 0x68:
2107                 printf("1st-level data cache: 32 KB, 4 way set associative, sectored cache, 64 byte line size\n");
2108                 break;
2109         case 0x6a:
2110                 printf("uTLB: 4KByte pages, 8-way set associative, 64 entries\n");
2111                 break;
2112         case 0x6b:
2113                 printf("DTLB: 4KByte pages, 8-way set associative, 256 entries\n");
2114                 break;
2115         case 0x6c:
2116                 printf("DTLB: 2M/4M pages, 8-way set associative, 128 entries\n");
2117                 break;
2118         case 0x6d:
2119                 printf("DTLB: 1 GByte pages, fully associative, 16 entries\n");
2120                 break;
2121         case 0x70:
2122                 printf("Trace cache: 12K-uops, 8-way set associative\n");
2123                 break;
2124         case 0x71:
2125                 printf("Trace cache: 16K-uops, 8-way set associative\n");
2126                 break;
2127         case 0x72:
2128                 printf("Trace cache: 32K-uops, 8-way set associative\n");
2129                 break;
2130         case 0x76:
2131                 printf("Instruction TLB: 2M/4M pages, fully associative, 8 entries\n");
2132                 break;
2133         case 0x78:
2134                 printf("2nd-level cache: 1 MB, 4-way set associative, 64-byte line size\n");
2135                 break;
2136         case 0x79:
2137                 printf("2nd-level cache: 128 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2138                 break;
2139         case 0x7a:
2140                 printf("2nd-level cache: 256 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2141                 break;
2142         case 0x7b:
2143                 printf("2nd-level cache: 512 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2144                 break;
2145         case 0x7c:
2146                 printf("2nd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n");
2147                 break;
2148         case 0x7d:
2149                 printf("2nd-level cache: 2-MB, 8-way set associative, 64-byte line size\n");
2150                 break;
2151         case 0x7f:
2152                 printf("2nd-level cache: 512-KB, 2-way set associative, 64-byte line size\n");
2153                 break;
2154         case 0x80:
2155                 printf("2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size\n");
2156                 break;
2157         case 0x82:
2158                 printf("2nd-level cache: 256 KB, 8-way set associative, 32 byte line size\n");
2159                 break;
2160         case 0x83:
2161                 printf("2nd-level cache: 512 KB, 8-way set associative, 32 byte line size\n");
2162                 break;
2163         case 0x84:
2164                 printf("2nd-level cache: 1 MB, 8-way set associative, 32 byte line size\n");
2165                 break;
2166         case 0x85:
2167                 printf("2nd-level cache: 2 MB, 8-way set associative, 32 byte line size\n");
2168                 break;
2169         case 0x86:
2170                 printf("2nd-level cache: 512 KB, 4-way set associative, 64 byte line size\n");
2171                 break;
2172         case 0x87:
2173                 printf("2nd-level cache: 1 MB, 8-way set associative, 64 byte line size\n");
2174                 break;
2175         case 0xa0:
2176                 printf("DTLB: 4k pages, fully associative, 32 entries\n");
2177                 break;
2178         case 0xb0:
2179                 printf("Instruction TLB: 4 KB Pages, 4-way set associative, 128 entries\n");
2180                 break;
2181         case 0xb1:
2182                 printf("Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries\n");
2183                 break;
2184         case 0xb2:
2185                 printf("Instruction TLB: 4KByte pages, 4-way set associative, 64 entries\n");
2186                 break;
2187         case 0xb3:
2188                 printf("Data TLB: 4 KB Pages, 4-way set associative, 128 entries\n");
2189                 break;
2190         case 0xb4:
2191                 printf("Data TLB1: 4 KByte pages, 4-way associative, 256 entries\n");
2192                 break;
2193         case 0xb5:
2194                 printf("Instruction TLB: 4KByte pages, 8-way set associative, 64 entries\n");
2195                 break;
2196         case 0xb6:
2197                 printf("Instruction TLB: 4KByte pages, 8-way set associative, 128 entries\n");
2198                 break;
2199         case 0xba:
2200                 printf("Data TLB1: 4 KByte pages, 4-way associative, 64 entries\n");
2201                 break;
2202         case 0xc0:
2203                 printf("Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries\n");
2204                 break;
2205         case 0xc1:
2206                 printf("Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries\n");
2207                 break;
2208         case 0xc2:
2209                 printf("DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries\n");
2210                 break;
2211         case 0xc3:
2212                 printf("Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative, 1536 entries. Also 1GBbyte pages, 4-way, 16 entries\n");
2213                 break;
2214         case 0xc4:
2215                 printf("DTLB: 2M/4M Byte pages, 4-way associative, 32 entries\n");
2216                 break;
2217         case 0xca:
2218                 printf("Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries\n");
2219                 break;
2220         case 0xd0:
2221                 printf("3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size\n");
2222                 break;
2223         case 0xd1:
2224                 printf("3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size\n");
2225                 break;
2226         case 0xd2:
2227                 printf("3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size\n");
2228                 break;
2229         case 0xd6:
2230                 printf("3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size\n");
2231                 break;
2232         case 0xd7:
2233                 printf("3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size\n");
2234                 break;
2235         case 0xd8:
2236                 printf("3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size\n");
2237                 break;
2238         case 0xdc:
2239                 printf("3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size\n");
2240                 break;
2241         case 0xdd:
2242                 printf("3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size\n");
2243                 break;
2244         case 0xde:
2245                 printf("3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size\n");
2246                 break;
2247         case 0xe2:
2248                 printf("3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size\n");
2249                 break;
2250         case 0xe3:
2251                 printf("3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size\n");
2252                 break;
2253         case 0xe4:
2254                 printf("3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size\n");
2255                 break;
2256         case 0xea:
2257                 printf("3rd-level cache: 12MByte, 24-way set associative, 64 byte line size\n");
2258                 break;
2259         case 0xeb:
2260                 printf("3rd-level cache: 18MByte, 24-way set associative, 64 byte line size\n");
2261                 break;
2262         case 0xec:
2263                 printf("3rd-level cache: 24MByte, 24-way set associative, 64 byte line size\n");
2264                 break;
2265         case 0xf0:
2266                 printf("64-Byte prefetching\n");
2267                 break;
2268         case 0xf1:
2269                 printf("128-Byte prefetching\n");
2270                 break;
2271         }
2272 }
2273
2274 static void
2275 print_svm_info(void)
2276 {
2277         u_int features, regs[4];
2278         uint64_t msr;
2279         int comma;
2280
2281         printf("\n  SVM: ");
2282         do_cpuid(0x8000000A, regs);
2283         features = regs[3];
2284
2285         msr = rdmsr(MSR_VM_CR);
2286         if ((msr & VM_CR_SVMDIS) == VM_CR_SVMDIS)
2287                 printf("(disabled in BIOS) ");
2288
2289         if (!bootverbose) {
2290                 comma = 0;
2291                 if (features & (1 << 0)) {
2292                         printf("%sNP", comma ? "," : "");
2293                         comma = 1;
2294                 }
2295                 if (features & (1 << 3)) {
2296                         printf("%sNRIP", comma ? "," : "");
2297                         comma = 1;
2298                 }
2299                 if (features & (1 << 5)) {
2300                         printf("%sVClean", comma ? "," : "");
2301                         comma = 1;
2302                 }
2303                 if (features & (1 << 6)) {
2304                         printf("%sAFlush", comma ? "," : "");
2305                         comma = 1;
2306                 }
2307                 if (features & (1 << 7)) {
2308                         printf("%sDAssist", comma ? "," : "");
2309                         comma = 1;
2310                 }
2311                 printf("%sNAsids=%d", comma ? "," : "", regs[1]);
2312                 return;
2313         }
2314
2315         printf("Features=0x%b", features,
2316                "\020"
2317                "\001NP"                 /* Nested paging */
2318                "\002LbrVirt"            /* LBR virtualization */
2319                "\003SVML"               /* SVM lock */
2320                "\004NRIPS"              /* NRIP save */
2321                "\005TscRateMsr"         /* MSR based TSC rate control */
2322                "\006VmcbClean"          /* VMCB clean bits */
2323                "\007FlushByAsid"        /* Flush by ASID */
2324                "\010DecodeAssist"       /* Decode assist */
2325                "\011<b8>"
2326                "\012<b9>"
2327                "\013PauseFilter"        /* PAUSE intercept filter */
2328                "\014EncryptedMcodePatch"
2329                "\015PauseFilterThreshold" /* PAUSE filter threshold */
2330                "\016AVIC"               /* virtual interrupt controller */
2331                "\017<b14>"
2332                "\020V_VMSAVE_VMLOAD"
2333                "\021vGIF"
2334                "\022<b17>"
2335                "\023<b18>"
2336                "\024<b19>"
2337                "\025<b20>"
2338                "\026<b21>"
2339                "\027<b22>"
2340                "\030<b23>"
2341                "\031<b24>"
2342                "\032<b25>"
2343                "\033<b26>"
2344                "\034<b27>"
2345                "\035<b28>"
2346                "\036<b29>"
2347                "\037<b30>"
2348                "\040<b31>"
2349                 );
2350         printf("\nRevision=%d, ASIDs=%d", regs[0] & 0xff, regs[1]);
2351 }
2352
2353 #ifdef __i386__
2354 static void
2355 print_transmeta_info(void)
2356 {
2357         u_int regs[4], nreg = 0;
2358
2359         do_cpuid(0x80860000, regs);
2360         nreg = regs[0];
2361         if (nreg >= 0x80860001) {
2362                 do_cpuid(0x80860001, regs);
2363                 printf("  Processor revision %u.%u.%u.%u\n",
2364                        (regs[1] >> 24) & 0xff,
2365                        (regs[1] >> 16) & 0xff,
2366                        (regs[1] >> 8) & 0xff,
2367                        regs[1] & 0xff);
2368         }
2369         if (nreg >= 0x80860002) {
2370                 do_cpuid(0x80860002, regs);
2371                 printf("  Code Morphing Software revision %u.%u.%u-%u-%u\n",
2372                        (regs[1] >> 24) & 0xff,
2373                        (regs[1] >> 16) & 0xff,
2374                        (regs[1] >> 8) & 0xff,
2375                        regs[1] & 0xff,
2376                        regs[2]);
2377         }
2378         if (nreg >= 0x80860006) {
2379                 char info[65];
2380                 do_cpuid(0x80860003, (u_int*) &info[0]);
2381                 do_cpuid(0x80860004, (u_int*) &info[16]);
2382                 do_cpuid(0x80860005, (u_int*) &info[32]);
2383                 do_cpuid(0x80860006, (u_int*) &info[48]);
2384                 info[64] = 0;
2385                 printf("  %s\n", info);
2386         }
2387 }
2388 #endif
2389
2390 static void
2391 print_via_padlock_info(void)
2392 {
2393         u_int regs[4];
2394
2395         do_cpuid(0xc0000001, regs);
2396         printf("\n  VIA Padlock Features=0x%b", regs[3],
2397         "\020"
2398         "\003RNG"               /* RNG */
2399         "\007AES"               /* ACE */
2400         "\011AES-CTR"           /* ACE2 */
2401         "\013SHA1,SHA256"       /* PHE */
2402         "\015RSA"               /* PMM */
2403         );
2404 }
2405
2406 static uint32_t
2407 vmx_settable(uint64_t basic, int msr, int true_msr)
2408 {
2409         uint64_t val;
2410
2411         if (basic & (1ULL << 55))
2412                 val = rdmsr(true_msr);
2413         else
2414                 val = rdmsr(msr);
2415
2416         /* Just report the controls that can be set to 1. */
2417         return (val >> 32);
2418 }
2419
2420 static void
2421 print_vmx_info(void)
2422 {
2423         uint64_t basic, msr;
2424         uint32_t entry, exit, mask, pin, proc, proc2;
2425         int comma;
2426
2427         printf("\n  VT-x: ");
2428         msr = rdmsr(MSR_IA32_FEATURE_CONTROL);
2429         if (!(msr & IA32_FEATURE_CONTROL_VMX_EN))
2430                 printf("(disabled in BIOS) ");
2431         basic = rdmsr(MSR_VMX_BASIC);
2432         pin = vmx_settable(basic, MSR_VMX_PINBASED_CTLS,
2433             MSR_VMX_TRUE_PINBASED_CTLS);
2434         proc = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS,
2435             MSR_VMX_TRUE_PROCBASED_CTLS);
2436         if (proc & PROCBASED_SECONDARY_CONTROLS)
2437                 proc2 = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS2,
2438                     MSR_VMX_PROCBASED_CTLS2);
2439         else
2440                 proc2 = 0;
2441         exit = vmx_settable(basic, MSR_VMX_EXIT_CTLS, MSR_VMX_TRUE_EXIT_CTLS);
2442         entry = vmx_settable(basic, MSR_VMX_ENTRY_CTLS, MSR_VMX_TRUE_ENTRY_CTLS);
2443
2444         if (!bootverbose) {
2445                 comma = 0;
2446                 if (exit & VM_EXIT_SAVE_PAT && exit & VM_EXIT_LOAD_PAT &&
2447                     entry & VM_ENTRY_LOAD_PAT) {
2448                         printf("%sPAT", comma ? "," : "");
2449                         comma = 1;
2450                 }
2451                 if (proc & PROCBASED_HLT_EXITING) {
2452                         printf("%sHLT", comma ? "," : "");
2453                         comma = 1;
2454                 }
2455                 if (proc & PROCBASED_MTF) {
2456                         printf("%sMTF", comma ? "," : "");
2457                         comma = 1;
2458                 }
2459                 if (proc & PROCBASED_PAUSE_EXITING) {
2460                         printf("%sPAUSE", comma ? "," : "");
2461                         comma = 1;
2462                 }
2463                 if (proc2 & PROCBASED2_ENABLE_EPT) {
2464                         printf("%sEPT", comma ? "," : "");
2465                         comma = 1;
2466                 }
2467                 if (proc2 & PROCBASED2_UNRESTRICTED_GUEST) {
2468                         printf("%sUG", comma ? "," : "");
2469                         comma = 1;
2470                 }
2471                 if (proc2 & PROCBASED2_ENABLE_VPID) {
2472                         printf("%sVPID", comma ? "," : "");
2473                         comma = 1;
2474                 }
2475                 if (proc & PROCBASED_USE_TPR_SHADOW &&
2476                     proc2 & PROCBASED2_VIRTUALIZE_APIC_ACCESSES &&
2477                     proc2 & PROCBASED2_VIRTUALIZE_X2APIC_MODE &&
2478                     proc2 & PROCBASED2_APIC_REGISTER_VIRTUALIZATION &&
2479                     proc2 & PROCBASED2_VIRTUAL_INTERRUPT_DELIVERY) {
2480                         printf("%sVID", comma ? "," : "");
2481                         comma = 1;
2482                         if (pin & PINBASED_POSTED_INTERRUPT)
2483                                 printf(",PostIntr");
2484                 }
2485                 return;
2486         }
2487
2488         mask = basic >> 32;
2489         printf("Basic Features=0x%b", mask,
2490         "\020"
2491         "\02132PA"              /* 32-bit physical addresses */
2492         "\022SMM"               /* SMM dual-monitor */
2493         "\027INS/OUTS"          /* VM-exit info for INS and OUTS */
2494         "\030TRUE"              /* TRUE_CTLS MSRs */
2495         );
2496         printf("\n        Pin-Based Controls=0x%b", pin,
2497         "\020"
2498         "\001ExtINT"            /* External-interrupt exiting */
2499         "\004NMI"               /* NMI exiting */
2500         "\006VNMI"              /* Virtual NMIs */
2501         "\007PreTmr"            /* Activate VMX-preemption timer */
2502         "\010PostIntr"          /* Process posted interrupts */
2503         );
2504         printf("\n        Primary Processor Controls=0x%b", proc,
2505         "\020"
2506         "\003INTWIN"            /* Interrupt-window exiting */
2507         "\004TSCOff"            /* Use TSC offsetting */
2508         "\010HLT"               /* HLT exiting */
2509         "\012INVLPG"            /* INVLPG exiting */
2510         "\013MWAIT"             /* MWAIT exiting */
2511         "\014RDPMC"             /* RDPMC exiting */
2512         "\015RDTSC"             /* RDTSC exiting */
2513         "\020CR3-LD"            /* CR3-load exiting */
2514         "\021CR3-ST"            /* CR3-store exiting */
2515         "\024CR8-LD"            /* CR8-load exiting */
2516         "\025CR8-ST"            /* CR8-store exiting */
2517         "\026TPR"               /* Use TPR shadow */
2518         "\027NMIWIN"            /* NMI-window exiting */
2519         "\030MOV-DR"            /* MOV-DR exiting */
2520         "\031IO"                /* Unconditional I/O exiting */
2521         "\032IOmap"             /* Use I/O bitmaps */
2522         "\034MTF"               /* Monitor trap flag */
2523         "\035MSRmap"            /* Use MSR bitmaps */
2524         "\036MONITOR"           /* MONITOR exiting */
2525         "\037PAUSE"             /* PAUSE exiting */
2526         );
2527         if (proc & PROCBASED_SECONDARY_CONTROLS)
2528                 printf("\n        Secondary Processor Controls=0x%b", proc2,
2529                 "\020"
2530                 "\001APIC"              /* Virtualize APIC accesses */
2531                 "\002EPT"               /* Enable EPT */
2532                 "\003DT"                /* Descriptor-table exiting */
2533                 "\004RDTSCP"            /* Enable RDTSCP */
2534                 "\005x2APIC"            /* Virtualize x2APIC mode */
2535                 "\006VPID"              /* Enable VPID */
2536                 "\007WBINVD"            /* WBINVD exiting */
2537                 "\010UG"                /* Unrestricted guest */
2538                 "\011APIC-reg"          /* APIC-register virtualization */
2539                 "\012VID"               /* Virtual-interrupt delivery */
2540                 "\013PAUSE-loop"        /* PAUSE-loop exiting */
2541                 "\014RDRAND"            /* RDRAND exiting */
2542                 "\015INVPCID"           /* Enable INVPCID */
2543                 "\016VMFUNC"            /* Enable VM functions */
2544                 "\017VMCS"              /* VMCS shadowing */
2545                 "\020EPT#VE"            /* EPT-violation #VE */
2546                 "\021XSAVES"            /* Enable XSAVES/XRSTORS */
2547                 );
2548         printf("\n        Exit Controls=0x%b", mask,
2549         "\020"
2550         "\003DR"                /* Save debug controls */
2551                                 /* Ignore Host address-space size */
2552         "\015PERF"              /* Load MSR_PERF_GLOBAL_CTRL */
2553         "\020AckInt"            /* Acknowledge interrupt on exit */
2554         "\023PAT-SV"            /* Save MSR_PAT */
2555         "\024PAT-LD"            /* Load MSR_PAT */
2556         "\025EFER-SV"           /* Save MSR_EFER */
2557         "\026EFER-LD"           /* Load MSR_EFER */
2558         "\027PTMR-SV"           /* Save VMX-preemption timer value */
2559         );
2560         printf("\n        Entry Controls=0x%b", mask,
2561         "\020"
2562         "\003DR"                /* Save debug controls */
2563                                 /* Ignore IA-32e mode guest */
2564                                 /* Ignore Entry to SMM */
2565                                 /* Ignore Deactivate dual-monitor treatment */
2566         "\016PERF"              /* Load MSR_PERF_GLOBAL_CTRL */
2567         "\017PAT"               /* Load MSR_PAT */
2568         "\020EFER"              /* Load MSR_EFER */
2569         );
2570         if (proc & PROCBASED_SECONDARY_CONTROLS &&
2571             (proc2 & (PROCBASED2_ENABLE_EPT | PROCBASED2_ENABLE_VPID)) != 0) {
2572                 msr = rdmsr(MSR_VMX_EPT_VPID_CAP);
2573                 mask = msr;
2574                 printf("\n        EPT Features=0x%b", mask,
2575                 "\020"
2576                 "\001XO"                /* Execute-only translations */
2577                 "\007PW4"               /* Page-walk length of 4 */
2578                 "\011UC"                /* EPT paging-structure mem can be UC */
2579                 "\017WB"                /* EPT paging-structure mem can be WB */
2580                 "\0212M"                /* EPT PDE can map a 2-Mbyte page */
2581                 "\0221G"                /* EPT PDPTE can map a 1-Gbyte page */
2582                 "\025INVEPT"            /* INVEPT is supported */
2583                 "\026AD"                /* Accessed and dirty flags for EPT */
2584                 "\032single"            /* INVEPT single-context type */
2585                 "\033all"               /* INVEPT all-context type */
2586                 );
2587                 mask = msr >> 32;
2588                 printf("\n        VPID Features=0x%b", mask,
2589                 "\020"
2590                 "\001INVVPID"           /* INVVPID is supported */
2591                 "\011individual"        /* INVVPID individual-address type */
2592                 "\012single"            /* INVVPID single-context type */
2593                 "\013all"               /* INVVPID all-context type */
2594                  /* INVVPID single-context-retaining-globals type */
2595                 "\014single-globals"
2596                 );
2597         }
2598 }
2599
2600 static void
2601 print_hypervisor_info(void)
2602 {
2603
2604         if (*hv_vendor != '\0')
2605                 printf("Hypervisor: Origin = \"%s\"\n", hv_vendor);
2606 }
2607
2608 /*
2609  * Returns the maximum physical address that can be used with the
2610  * current system.
2611  */
2612 vm_paddr_t
2613 cpu_getmaxphyaddr(void)
2614 {
2615
2616 #if defined(__i386__)
2617         if (!pae_mode)
2618                 return (0xffffffff);
2619 #endif
2620         return ((1ULL << cpu_maxphyaddr) - 1);
2621 }