sys/x86/x86/identcpu.c

   1 /*-
   2  * Copyright (c) 1992 Terrence R. Lambert.
   3  * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
   4  * Copyright (c) 1997 KATO Takenori.
   5  * All rights reserved.
   6  *
   7  * This code is derived from software contributed to Berkeley by
   8  * William Jolitz.
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  * 3. All advertising materials mentioning features or use of this software
  19  *    must display the following acknowledgement:
  20  *      This product includes software developed by the University of
  21  *      California, Berkeley and its contributors.
  22  * 4. Neither the name of the University nor the names of its contributors
  23  *    may be used to endorse or promote products derived from this software
  24  *    without specific prior written permission.
  25  *
  26  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  27  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  28  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  29  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  30  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  31  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  32  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  33  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  34  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  35  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  36  * SUCH DAMAGE.
  37  *
  38  *      from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp
  39  */
  40
  41 #include <sys/cdefs.h>
  42 __FBSDID("$FreeBSD$");
  43
  44 #include "opt_cpu.h"
  45
  46 #include <sys/param.h>
  47 #include <sys/bus.h>
  48 #include <sys/cpu.h>
  49 #include <sys/eventhandler.h>
  50 #include <sys/limits.h>
  51 #include <sys/systm.h>
  52 #include <sys/kernel.h>
  53 #include <sys/sysctl.h>
  54 #include <sys/power.h>
  55
  56 #include <machine/asmacros.h>
  57 #include <machine/clock.h>
  58 #include <machine/cputypes.h>
  59 #include <machine/frame.h>
  60 #include <machine/intr_machdep.h>
  61 #include <machine/md_var.h>
  62 #include <machine/segments.h>
  63 #include <machine/specialreg.h>
  64
  65 #include <amd64/vmm/intel/vmx_controls.h>
  66 #include <x86/isa/icu.h>
  67 #include <x86/vmware.h>
  68
  69 #ifdef __i386__
  70 #define IDENTBLUE_CYRIX486      0
  71 #define IDENTBLUE_IBMCPU        1
  72 #define IDENTBLUE_CYRIXM2       2
  73
  74 static void identifycyrix(void);
  75 static void print_transmeta_info(void);
  76 #endif
  77 static u_int find_cpu_vendor_id(void);
  78 static void print_AMD_info(void);
  79 static void print_INTEL_info(void);
  80 static void print_INTEL_TLB(u_int data);
  81 static void print_hypervisor_info(void);
  82 static void print_svm_info(void);
  83 static void print_via_padlock_info(void);
  84 static void print_vmx_info(void);
  85
  86 #ifdef __i386__
  87 int     cpu;                    /* Are we 386, 386sx, 486, etc? */
  88 int     cpu_class;
  89 #endif
  90 u_int   cpu_feature;            /* Feature flags */
  91 u_int   cpu_feature2;           /* Feature flags */
  92 u_int   amd_feature;            /* AMD feature flags */
  93 u_int   amd_feature2;           /* AMD feature flags */
  94 u_int   amd_rascap;             /* AMD RAS capabilities */
  95 u_int   amd_pminfo;             /* AMD advanced power management info */
  96 u_int   amd_extended_feature_extensions;
  97 u_int   via_feature_rng;        /* VIA RNG features */
  98 u_int   via_feature_xcrypt;     /* VIA ACE features */
  99 u_int   cpu_high;               /* Highest arg to CPUID */
 100 u_int   cpu_exthigh;            /* Highest arg to extended CPUID */
 101 u_int   cpu_id;                 /* Stepping ID */
 102 u_int   cpu_procinfo;           /* HyperThreading Info / Brand Index / CLFUSH */
 103 u_int   cpu_procinfo2;          /* Multicore info */
 104 char    cpu_vendor[20];         /* CPU Origin code */
 105 u_int   cpu_vendor_id;          /* CPU vendor ID */
 106 u_int   cpu_fxsr;               /* SSE enabled */
 107 u_int   cpu_mxcsr_mask;         /* Valid bits in mxcsr */
 108 u_int   cpu_clflush_line_size = 32;
 109 u_int   cpu_stdext_feature;     /* %ebx */
 110 u_int   cpu_stdext_feature2;    /* %ecx */
 111 u_int   cpu_stdext_feature3;    /* %edx */
 112 uint64_t cpu_ia32_arch_caps;
 113 u_int   cpu_max_ext_state_size;
 114 u_int   cpu_mon_mwait_flags;    /* MONITOR/MWAIT flags (CPUID.05H.ECX) */
 115 u_int   cpu_mon_min_size;       /* MONITOR minimum range size, bytes */
 116 u_int   cpu_mon_max_size;       /* MONITOR minimum range size, bytes */
 117 u_int   cpu_maxphyaddr;         /* Max phys addr width in bits */
 118 char machine[] = MACHINE;
 119
 120 SYSCTL_UINT(_hw, OID_AUTO, via_feature_rng, CTLFLAG_RD,
 121     &via_feature_rng, 0,
 122     "VIA RNG feature available in CPU");
 123 SYSCTL_UINT(_hw, OID_AUTO, via_feature_xcrypt, CTLFLAG_RD,
 124     &via_feature_xcrypt, 0,
 125     "VIA xcrypt feature available in CPU");
 126
 127 #ifdef __amd64__
 128 #ifdef SCTL_MASK32
 129 extern int adaptive_machine_arch;
 130 #endif
 131
 132 static int
 133 sysctl_hw_machine(SYSCTL_HANDLER_ARGS)
 134 {
 135 #ifdef SCTL_MASK32
 136         static const char machine32[] = "i386";
 137 #endif
 138         int error;
 139
 140 #ifdef SCTL_MASK32
 141         if ((req->flags & SCTL_MASK32) != 0 && adaptive_machine_arch)
 142                 error = SYSCTL_OUT(req, machine32, sizeof(machine32));
 143         else
 144 #endif
 145                 error = SYSCTL_OUT(req, machine, sizeof(machine));
 146         return (error);
 147
 148 }
 149 SYSCTL_PROC(_hw, HW_MACHINE, machine, CTLTYPE_STRING | CTLFLAG_RD |
 150     CTLFLAG_MPSAFE, NULL, 0, sysctl_hw_machine, "A", "Machine class");
 151 #else
 152 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD,
 153     machine, 0, "Machine class");
 154 #endif
 155
 156 static char cpu_model[128];
 157 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD | CTLFLAG_MPSAFE,
 158     cpu_model, 0, "Machine model");
 159
 160 static int hw_clockrate;
 161 SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD,
 162     &hw_clockrate, 0, "CPU instruction clock rate");
 163
 164 u_int hv_high;
 165 char hv_vendor[16];
 166 SYSCTL_STRING(_hw, OID_AUTO, hv_vendor, CTLFLAG_RD | CTLFLAG_MPSAFE, hv_vendor,
 167     0, "Hypervisor vendor");
 168
 169 static eventhandler_tag tsc_post_tag;
 170
 171 static char cpu_brand[48];
 172
 173 #ifdef __i386__
 174 #define MAX_BRAND_INDEX 8
 175
 176 static const char *cpu_brandtable[MAX_BRAND_INDEX + 1] = {
 177         NULL,                   /* No brand */
 178         "Intel Celeron",
 179         "Intel Pentium III",
 180         "Intel Pentium III Xeon",
 181         NULL,
 182         NULL,
 183         NULL,
 184         NULL,
 185         "Intel Pentium 4"
 186 };
 187
 188 static struct {
 189         char    *cpu_name;
 190         int     cpu_class;
 191 } cpus[] = {
 192         { "Intel 80286",        CPUCLASS_286 },         /* CPU_286   */
 193         { "i386SX",             CPUCLASS_386 },         /* CPU_386SX */
 194         { "i386DX",             CPUCLASS_386 },         /* CPU_386   */
 195         { "i486SX",             CPUCLASS_486 },         /* CPU_486SX */
 196         { "i486DX",             CPUCLASS_486 },         /* CPU_486   */
 197         { "Pentium",            CPUCLASS_586 },         /* CPU_586   */
 198         { "Cyrix 486",          CPUCLASS_486 },         /* CPU_486DLC */
 199         { "Pentium Pro",        CPUCLASS_686 },         /* CPU_686 */
 200         { "Cyrix 5x86",         CPUCLASS_486 },         /* CPU_M1SC */
 201         { "Cyrix 6x86",         CPUCLASS_486 },         /* CPU_M1 */
 202         { "Blue Lightning",     CPUCLASS_486 },         /* CPU_BLUE */
 203         { "Cyrix 6x86MX",       CPUCLASS_686 },         /* CPU_M2 */
 204         { "NexGen 586",         CPUCLASS_386 },         /* CPU_NX586 (XXX) */
 205         { "Cyrix 486S/DX",      CPUCLASS_486 },         /* CPU_CY486DX */
 206         { "Pentium II",         CPUCLASS_686 },         /* CPU_PII */
 207         { "Pentium III",        CPUCLASS_686 },         /* CPU_PIII */
 208         { "Pentium 4",          CPUCLASS_686 },         /* CPU_P4 */
 209 };
 210 #endif
 211
 212 static struct {
 213         char    *vendor;
 214         u_int   vendor_id;
 215 } cpu_vendors[] = {
 216         { INTEL_VENDOR_ID,      CPU_VENDOR_INTEL },     /* GenuineIntel */
 217         { AMD_VENDOR_ID,        CPU_VENDOR_AMD },       /* AuthenticAMD */
 218         { CENTAUR_VENDOR_ID,    CPU_VENDOR_CENTAUR },   /* CentaurHauls */
 219 #ifdef __i386__
 220         { NSC_VENDOR_ID,        CPU_VENDOR_NSC },       /* Geode by NSC */
 221         { CYRIX_VENDOR_ID,      CPU_VENDOR_CYRIX },     /* CyrixInstead */
 222         { TRANSMETA_VENDOR_ID,  CPU_VENDOR_TRANSMETA }, /* GenuineTMx86 */
 223         { SIS_VENDOR_ID,        CPU_VENDOR_SIS },       /* SiS SiS SiS  */
 224         { UMC_VENDOR_ID,        CPU_VENDOR_UMC },       /* UMC UMC UMC  */
 225         { NEXGEN_VENDOR_ID,     CPU_VENDOR_NEXGEN },    /* NexGenDriven */
 226         { RISE_VENDOR_ID,       CPU_VENDOR_RISE },      /* RiseRiseRise */
 227 #if 0
 228         /* XXX CPUID 8000_0000h and 8086_0000h, not 0000_0000h */
 229         { "TransmetaCPU",       CPU_VENDOR_TRANSMETA },
 230 #endif
 231 #endif
 232 };
 233
 234 void
 235 printcpuinfo(void)
 236 {
 237         u_int regs[4], i;
 238         char *brand;
 239
 240         printf("CPU: ");
 241 #ifdef __i386__
 242         cpu_class = cpus[cpu].cpu_class;
 243         strncpy(cpu_model, cpus[cpu].cpu_name, sizeof (cpu_model));
 244 #else
 245         strncpy(cpu_model, "Hammer", sizeof (cpu_model));
 246 #endif
 247
 248         /* Check for extended CPUID information and a processor name. */
 249         if (cpu_exthigh >= 0x80000004) {
 250                 brand = cpu_brand;
 251                 for (i = 0x80000002; i < 0x80000005; i++) {
 252                         do_cpuid(i, regs);
 253                         memcpy(brand, regs, sizeof(regs));
 254                         brand += sizeof(regs);
 255                 }
 256         }
 257
 258         switch (cpu_vendor_id) {
 259         case CPU_VENDOR_INTEL:
 260 #ifdef __i386__
 261                 if ((cpu_id & 0xf00) > 0x300) {
 262                         u_int brand_index;
 263
 264                         cpu_model[0] = '\0';
 265
 266                         switch (cpu_id & 0x3000) {
 267                         case 0x1000:
 268                                 strcpy(cpu_model, "Overdrive ");
 269                                 break;
 270                         case 0x2000:
 271                                 strcpy(cpu_model, "Dual ");
 272                                 break;
 273                         }
 274
 275                         switch (cpu_id & 0xf00) {
 276                         case 0x400:
 277                                 strcat(cpu_model, "i486 ");
 278                                 /* Check the particular flavor of 486 */
 279                                 switch (cpu_id & 0xf0) {
 280                                 case 0x00:
 281                                 case 0x10:
 282                                         strcat(cpu_model, "DX");
 283                                         break;
 284                                 case 0x20:
 285                                         strcat(cpu_model, "SX");
 286                                         break;
 287                                 case 0x30:
 288                                         strcat(cpu_model, "DX2");
 289                                         break;
 290                                 case 0x40:
 291                                         strcat(cpu_model, "SL");
 292                                         break;
 293                                 case 0x50:
 294                                         strcat(cpu_model, "SX2");
 295                                         break;
 296                                 case 0x70:
 297                                         strcat(cpu_model,
 298                                             "DX2 Write-Back Enhanced");
 299                                         break;
 300                                 case 0x80:
 301                                         strcat(cpu_model, "DX4");
 302                                         break;
 303                                 }
 304                                 break;
 305                         case 0x500:
 306                                 /* Check the particular flavor of 586 */
 307                                 strcat(cpu_model, "Pentium");
 308                                 switch (cpu_id & 0xf0) {
 309                                 case 0x00:
 310                                         strcat(cpu_model, " A-step");
 311                                         break;
 312                                 case 0x10:
 313                                         strcat(cpu_model, "/P5");
 314                                         break;
 315                                 case 0x20:
 316                                         strcat(cpu_model, "/P54C");
 317                                         break;
 318                                 case 0x30:
 319                                         strcat(cpu_model, "/P24T");
 320                                         break;
 321                                 case 0x40:
 322                                         strcat(cpu_model, "/P55C");
 323                                         break;
 324                                 case 0x70:
 325                                         strcat(cpu_model, "/P54C");
 326                                         break;
 327                                 case 0x80:
 328                                         strcat(cpu_model, "/P55C (quarter-micron)");
 329                                         break;
 330                                 default:
 331                                         /* nothing */
 332                                         break;
 333                                 }
 334 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
 335                                 /*
 336                                  * XXX - If/when Intel fixes the bug, this
 337                                  * should also check the version of the
 338                                  * CPU, not just that it's a Pentium.
 339                                  */
 340                                 has_f00f_bug = 1;
 341 #endif
 342                                 break;
 343                         case 0x600:
 344                                 /* Check the particular flavor of 686 */
 345                                 switch (cpu_id & 0xf0) {
 346                                 case 0x00:
 347                                         strcat(cpu_model, "Pentium Pro A-step");
 348                                         break;
 349                                 case 0x10:
 350                                         strcat(cpu_model, "Pentium Pro");
 351                                         break;
 352                                 case 0x30:
 353                                 case 0x50:
 354                                 case 0x60:
 355                                         strcat(cpu_model,
 356                                 "Pentium II/Pentium II Xeon/Celeron");
 357                                         cpu = CPU_PII;
 358                                         break;
 359                                 case 0x70:
 360                                 case 0x80:
 361                                 case 0xa0:
 362                                 case 0xb0:
 363                                         strcat(cpu_model,
 364                                         "Pentium III/Pentium III Xeon/Celeron");
 365                                         cpu = CPU_PIII;
 366                                         break;
 367                                 default:
 368                                         strcat(cpu_model, "Unknown 80686");
 369                                         break;
 370                                 }
 371                                 break;
 372                         case 0xf00:
 373                                 strcat(cpu_model, "Pentium 4");
 374                                 cpu = CPU_P4;
 375                                 break;
 376                         default:
 377                                 strcat(cpu_model, "unknown");
 378                                 break;
 379                         }
 380
 381                         /*
 382                          * If we didn't get a brand name from the extended
 383                          * CPUID, try to look it up in the brand table.
 384                          */
 385                         if (cpu_high > 0 && *cpu_brand == '\0') {
 386                                 brand_index = cpu_procinfo & CPUID_BRAND_INDEX;
 387                                 if (brand_index <= MAX_BRAND_INDEX &&
 388                                     cpu_brandtable[brand_index] != NULL)
 389                                         strcpy(cpu_brand,
 390                                             cpu_brandtable[brand_index]);
 391                         }
 392                 }
 393 #else
 394                 /* Please make up your mind folks! */
 395                 strcat(cpu_model, "EM64T");
 396 #endif
 397                 break;
 398         case CPU_VENDOR_AMD:
 399                 /*
 400                  * Values taken from AMD Processor Recognition
 401                  * http://www.amd.com/K6/k6docs/pdf/20734g.pdf
 402                  * (also describes ``Features'' encodings.
 403                  */
 404                 strcpy(cpu_model, "AMD ");
 405 #ifdef __i386__
 406                 switch (cpu_id & 0xFF0) {
 407                 case 0x410:
 408                         strcat(cpu_model, "Standard Am486DX");
 409                         break;
 410                 case 0x430:
 411                         strcat(cpu_model, "Enhanced Am486DX2 Write-Through");
 412                         break;
 413                 case 0x470:
 414                         strcat(cpu_model, "Enhanced Am486DX2 Write-Back");
 415                         break;
 416                 case 0x480:
 417                         strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Through");
 418                         break;
 419                 case 0x490:
 420                         strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Back");
 421                         break;
 422                 case 0x4E0:
 423                         strcat(cpu_model, "Am5x86 Write-Through");
 424                         break;
 425                 case 0x4F0:
 426                         strcat(cpu_model, "Am5x86 Write-Back");
 427                         break;
 428                 case 0x500:
 429                         strcat(cpu_model, "K5 model 0");
 430                         break;
 431                 case 0x510:
 432                         strcat(cpu_model, "K5 model 1");
 433                         break;
 434                 case 0x520:
 435                         strcat(cpu_model, "K5 PR166 (model 2)");
 436                         break;
 437                 case 0x530:
 438                         strcat(cpu_model, "K5 PR200 (model 3)");
 439                         break;
 440                 case 0x560:
 441                         strcat(cpu_model, "K6");
 442                         break;
 443                 case 0x570:
 444                         strcat(cpu_model, "K6 266 (model 1)");
 445                         break;
 446                 case 0x580:
 447                         strcat(cpu_model, "K6-2");
 448                         break;
 449                 case 0x590:
 450                         strcat(cpu_model, "K6-III");
 451                         break;
 452                 case 0x5a0:
 453                         strcat(cpu_model, "Geode LX");
 454                         break;
 455                 default:
 456                         strcat(cpu_model, "Unknown");
 457                         break;
 458                 }
 459 #else
 460                 if ((cpu_id & 0xf00) == 0xf00)
 461                         strcat(cpu_model, "AMD64 Processor");
 462                 else
 463                         strcat(cpu_model, "Unknown");
 464 #endif
 465                 break;
 466 #ifdef __i386__
 467         case CPU_VENDOR_CYRIX:
 468                 strcpy(cpu_model, "Cyrix ");
 469                 switch (cpu_id & 0xff0) {
 470                 case 0x440:
 471                         strcat(cpu_model, "MediaGX");
 472                         break;
 473                 case 0x520:
 474                         strcat(cpu_model, "6x86");
 475                         break;
 476                 case 0x540:
 477                         cpu_class = CPUCLASS_586;
 478                         strcat(cpu_model, "GXm");
 479                         break;
 480                 case 0x600:
 481                         strcat(cpu_model, "6x86MX");
 482                         break;
 483                 default:
 484                         /*
 485                          * Even though CPU supports the cpuid
 486                          * instruction, it can be disabled.
 487                          * Therefore, this routine supports all Cyrix
 488                          * CPUs.
 489                          */
 490                         switch (cyrix_did & 0xf0) {
 491                         case 0x00:
 492                                 switch (cyrix_did & 0x0f) {
 493                                 case 0x00:
 494                                         strcat(cpu_model, "486SLC");
 495                                         break;
 496                                 case 0x01:
 497                                         strcat(cpu_model, "486DLC");
 498                                         break;
 499                                 case 0x02:
 500                                         strcat(cpu_model, "486SLC2");
 501                                         break;
 502                                 case 0x03:
 503                                         strcat(cpu_model, "486DLC2");
 504                                         break;
 505                                 case 0x04:
 506                                         strcat(cpu_model, "486SRx");
 507                                         break;
 508                                 case 0x05:
 509                                         strcat(cpu_model, "486DRx");
 510                                         break;
 511                                 case 0x06:
 512                                         strcat(cpu_model, "486SRx2");
 513                                         break;
 514                                 case 0x07:
 515                                         strcat(cpu_model, "486DRx2");
 516                                         break;
 517                                 case 0x08:
 518                                         strcat(cpu_model, "486SRu");
 519                                         break;
 520                                 case 0x09:
 521                                         strcat(cpu_model, "486DRu");
 522                                         break;
 523                                 case 0x0a:
 524                                         strcat(cpu_model, "486SRu2");
 525                                         break;
 526                                 case 0x0b:
 527                                         strcat(cpu_model, "486DRu2");
 528                                         break;
 529                                 default:
 530                                         strcat(cpu_model, "Unknown");
 531                                         break;
 532                                 }
 533                                 break;
 534                         case 0x10:
 535                                 switch (cyrix_did & 0x0f) {
 536                                 case 0x00:
 537                                         strcat(cpu_model, "486S");
 538                                         break;
 539                                 case 0x01:
 540                                         strcat(cpu_model, "486S2");
 541                                         break;
 542                                 case 0x02:
 543                                         strcat(cpu_model, "486Se");
 544                                         break;
 545                                 case 0x03:
 546                                         strcat(cpu_model, "486S2e");
 547                                         break;
 548                                 case 0x0a:
 549                                         strcat(cpu_model, "486DX");
 550                                         break;
 551                                 case 0x0b:
 552                                         strcat(cpu_model, "486DX2");
 553                                         break;
 554                                 case 0x0f:
 555                                         strcat(cpu_model, "486DX4");
 556                                         break;
 557                                 default:
 558                                         strcat(cpu_model, "Unknown");
 559                                         break;
 560                                 }
 561                                 break;
 562                         case 0x20:
 563                                 if ((cyrix_did & 0x0f) < 8)
 564                                         strcat(cpu_model, "6x86");      /* Where did you get it? */
 565                                 else
 566                                         strcat(cpu_model, "5x86");
 567                                 break;
 568                         case 0x30:
 569                                 strcat(cpu_model, "6x86");
 570                                 break;
 571                         case 0x40:
 572                                 if ((cyrix_did & 0xf000) == 0x3000) {
 573                                         cpu_class = CPUCLASS_586;
 574                                         strcat(cpu_model, "GXm");
 575                                 } else
 576                                         strcat(cpu_model, "MediaGX");
 577                                 break;
 578                         case 0x50:
 579                                 strcat(cpu_model, "6x86MX");
 580                                 break;
 581                         case 0xf0:
 582                                 switch (cyrix_did & 0x0f) {
 583                                 case 0x0d:
 584                                         strcat(cpu_model, "Overdrive CPU");
 585                                         break;
 586                                 case 0x0e:
 587                                         strcpy(cpu_model, "Texas Instruments 486SXL");
 588                                         break;
 589                                 case 0x0f:
 590                                         strcat(cpu_model, "486SLC/DLC");
 591                                         break;
 592                                 default:
 593                                         strcat(cpu_model, "Unknown");
 594                                         break;
 595                                 }
 596                                 break;
 597                         default:
 598                                 strcat(cpu_model, "Unknown");
 599                                 break;
 600                         }
 601                         break;
 602                 }
 603                 break;
 604         case CPU_VENDOR_RISE:
 605                 strcpy(cpu_model, "Rise ");
 606                 switch (cpu_id & 0xff0) {
 607                 case 0x500:     /* 6401 and 6441 (Kirin) */
 608                 case 0x520:     /* 6510 (Lynx) */
 609                         strcat(cpu_model, "mP6");
 610                         break;
 611                 default:
 612                         strcat(cpu_model, "Unknown");
 613                 }
 614                 break;
 615 #endif
 616         case CPU_VENDOR_CENTAUR:
 617 #ifdef __i386__
 618                 switch (cpu_id & 0xff0) {
 619                 case 0x540:
 620                         strcpy(cpu_model, "IDT WinChip C6");
 621                         break;
 622                 case 0x580:
 623                         strcpy(cpu_model, "IDT WinChip 2");
 624                         break;
 625                 case 0x590:
 626                         strcpy(cpu_model, "IDT WinChip 3");
 627                         break;
 628                 case 0x660:
 629                         strcpy(cpu_model, "VIA C3 Samuel");
 630                         break;
 631                 case 0x670:
 632                         if (cpu_id & 0x8)
 633                                 strcpy(cpu_model, "VIA C3 Ezra");
 634                         else
 635                                 strcpy(cpu_model, "VIA C3 Samuel 2");
 636                         break;
 637                 case 0x680:
 638                         strcpy(cpu_model, "VIA C3 Ezra-T");
 639                         break;
 640                 case 0x690:
 641                         strcpy(cpu_model, "VIA C3 Nehemiah");
 642                         break;
 643                 case 0x6a0:
 644                 case 0x6d0:
 645                         strcpy(cpu_model, "VIA C7 Esther");
 646                         break;
 647                 case 0x6f0:
 648                         strcpy(cpu_model, "VIA Nano");
 649                         break;
 650                 default:
 651                         strcpy(cpu_model, "VIA/IDT Unknown");
 652                 }
 653 #else
 654                 strcpy(cpu_model, "VIA ");
 655                 if ((cpu_id & 0xff0) == 0x6f0)
 656                         strcat(cpu_model, "Nano Processor");
 657                 else
 658                         strcat(cpu_model, "Unknown");
 659 #endif
 660                 break;
 661 #ifdef __i386__
 662         case CPU_VENDOR_IBM:
 663                 strcpy(cpu_model, "Blue Lightning CPU");
 664                 break;
 665         case CPU_VENDOR_NSC:
 666                 switch (cpu_id & 0xff0) {
 667                 case 0x540:
 668                         strcpy(cpu_model, "Geode SC1100");
 669                         cpu = CPU_GEODE1100;
 670                         break;
 671                 default:
 672                         strcpy(cpu_model, "Geode/NSC unknown");
 673                         break;
 674                 }
 675                 break;
 676 #endif
 677         default:
 678                 strcat(cpu_model, "Unknown");
 679                 break;
 680         }
 681
 682         /*
 683          * Replace cpu_model with cpu_brand minus leading spaces if
 684          * we have one.
 685          */
 686         brand = cpu_brand;
 687         while (*brand == ' ')
 688                 ++brand;
 689         if (*brand != '\0')
 690                 strcpy(cpu_model, brand);
 691
 692         printf("%s (", cpu_model);
 693         if (tsc_freq != 0) {
 694                 hw_clockrate = (tsc_freq + 5000) / 1000000;
 695                 printf("%jd.%02d-MHz ",
 696                     (intmax_t)(tsc_freq + 4999) / 1000000,
 697                     (u_int)((tsc_freq + 4999) / 10000) % 100);
 698         }
 699 #ifdef __i386__
 700         switch(cpu_class) {
 701         case CPUCLASS_286:
 702                 printf("286");
 703                 break;
 704         case CPUCLASS_386:
 705                 printf("386");
 706                 break;
 707 #if defined(I486_CPU)
 708         case CPUCLASS_486:
 709                 printf("486");
 710                 break;
 711 #endif
 712 #if defined(I586_CPU)
 713         case CPUCLASS_586:
 714                 printf("586");
 715                 break;
 716 #endif
 717 #if defined(I686_CPU)
 718         case CPUCLASS_686:
 719                 printf("686");
 720                 break;
 721 #endif
 722         default:
 723                 printf("Unknown");      /* will panic below... */
 724         }
 725 #else
 726         printf("K8");
 727 #endif
 728         printf("-class CPU)\n");
 729         if (*cpu_vendor)
 730                 printf("  Origin=\"%s\"", cpu_vendor);
 731         if (cpu_id)
 732                 printf("  Id=0x%x", cpu_id);
 733
 734         if (cpu_vendor_id == CPU_VENDOR_INTEL ||
 735             cpu_vendor_id == CPU_VENDOR_AMD ||
 736             cpu_vendor_id == CPU_VENDOR_CENTAUR ||
 737 #ifdef __i386__
 738             cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
 739             cpu_vendor_id == CPU_VENDOR_RISE ||
 740             cpu_vendor_id == CPU_VENDOR_NSC ||
 741             (cpu_vendor_id == CPU_VENDOR_CYRIX && ((cpu_id & 0xf00) > 0x500)) ||
 742 #endif
 743             0) {
 744                 printf("  Family=0x%x", CPUID_TO_FAMILY(cpu_id));
 745                 printf("  Model=0x%x", CPUID_TO_MODEL(cpu_id));
 746                 printf("  Stepping=%u", cpu_id & CPUID_STEPPING);
 747 #ifdef __i386__
 748                 if (cpu_vendor_id == CPU_VENDOR_CYRIX)
 749                         printf("\n  DIR=0x%04x", cyrix_did);
 750 #endif
 751
 752                 /*
 753                  * AMD CPUID Specification
 754                  * http://support.amd.com/us/Embedded_TechDocs/25481.pdf
 755                  *
 756                  * Intel Processor Identification and CPUID Instruction
 757                  * http://www.intel.com/assets/pdf/appnote/241618.pdf
 758                  */
 759                 if (cpu_high > 0) {
 760
 761                         /*
 762                          * Here we should probably set up flags indicating
 763                          * whether or not various features are available.
 764                          * The interesting ones are probably VME, PSE, PAE,
 765                          * and PGE.  The code already assumes without bothering
 766                          * to check that all CPUs >= Pentium have a TSC and
 767                          * MSRs.
 768                          */
 769                         printf("\n  Features=0x%b", cpu_feature,
 770                         "\020"
 771                         "\001FPU"       /* Integral FPU */
 772                         "\002VME"       /* Extended VM86 mode support */
 773                         "\003DE"        /* Debugging Extensions (CR4.DE) */
 774                         "\004PSE"       /* 4MByte page tables */
 775                         "\005TSC"       /* Timestamp counter */
 776                         "\006MSR"       /* Machine specific registers */
 777                         "\007PAE"       /* Physical address extension */
 778                         "\010MCE"       /* Machine Check support */
 779                         "\011CX8"       /* CMPEXCH8 instruction */
 780                         "\012APIC"      /* SMP local APIC */
 781                         "\013oldMTRR"   /* Previous implementation of MTRR */
 782                         "\014SEP"       /* Fast System Call */
 783                         "\015MTRR"      /* Memory Type Range Registers */
 784                         "\016PGE"       /* PG_G (global bit) support */
 785                         "\017MCA"       /* Machine Check Architecture */
 786                         "\020CMOV"      /* CMOV instruction */
 787                         "\021PAT"       /* Page attributes table */
 788                         "\022PSE36"     /* 36 bit address space support */
 789                         "\023PN"        /* Processor Serial number */
 790                         "\024CLFLUSH"   /* Has the CLFLUSH instruction */
 791                         "\025<b20>"
 792                         "\026DTS"       /* Debug Trace Store */
 793                         "\027ACPI"      /* ACPI support */
 794                         "\030MMX"       /* MMX instructions */
 795                         "\031FXSR"      /* FXSAVE/FXRSTOR */
 796                         "\032SSE"       /* Streaming SIMD Extensions */
 797                         "\033SSE2"      /* Streaming SIMD Extensions #2 */
 798                         "\034SS"        /* Self snoop */
 799                         "\035HTT"       /* Hyperthreading (see EBX bit 16-23) */
 800                         "\036TM"        /* Thermal Monitor clock slowdown */
 801                         "\037IA64"      /* CPU can execute IA64 instructions */
 802                         "\040PBE"       /* Pending Break Enable */
 803                         );
 804
 805                         if (cpu_feature2 != 0) {
 806                                 printf("\n  Features2=0x%b", cpu_feature2,
 807                                 "\020"
 808                                 "\001SSE3"      /* SSE3 */
 809                                 "\002PCLMULQDQ" /* Carry-Less Mul Quadword */
 810                                 "\003DTES64"    /* 64-bit Debug Trace */
 811                                 "\004MON"       /* MONITOR/MWAIT Instructions */
 812                                 "\005DS_CPL"    /* CPL Qualified Debug Store */
 813                                 "\006VMX"       /* Virtual Machine Extensions */
 814                                 "\007SMX"       /* Safer Mode Extensions */
 815                                 "\010EST"       /* Enhanced SpeedStep */
 816                                 "\011TM2"       /* Thermal Monitor 2 */
 817                                 "\012SSSE3"     /* SSSE3 */
 818                                 "\013CNXT-ID"   /* L1 context ID available */
 819                                 "\014SDBG"      /* IA32 silicon debug */
 820                                 "\015FMA"       /* Fused Multiply Add */
 821                                 "\016CX16"      /* CMPXCHG16B Instruction */
 822                                 "\017xTPR"      /* Send Task Priority Messages*/
 823                                 "\020PDCM"      /* Perf/Debug Capability MSR */
 824                                 "\021<b16>"
 825                                 "\022PCID"      /* Process-context Identifiers*/
 826                                 "\023DCA"       /* Direct Cache Access */
 827                                 "\024SSE4.1"    /* SSE 4.1 */
 828                                 "\025SSE4.2"    /* SSE 4.2 */
 829                                 "\026x2APIC"    /* xAPIC Extensions */
 830                                 "\027MOVBE"     /* MOVBE Instruction */
 831                                 "\030POPCNT"    /* POPCNT Instruction */
 832                                 "\031TSCDLT"    /* TSC-Deadline Timer */
 833                                 "\032AESNI"     /* AES Crypto */
 834                                 "\033XSAVE"     /* XSAVE/XRSTOR States */
 835                                 "\034OSXSAVE"   /* OS-Enabled State Management*/
 836                                 "\035AVX"       /* Advanced Vector Extensions */
 837                                 "\036F16C"      /* Half-precision conversions */
 838                                 "\037RDRAND"    /* RDRAND Instruction */
 839                                 "\040HV"        /* Hypervisor */
 840                                 );
 841                         }
 842
 843                         if (amd_feature != 0) {
 844                                 printf("\n  AMD Features=0x%b", amd_feature,
 845                                 "\020"          /* in hex */
 846                                 "\001<s0>"      /* Same */
 847                                 "\002<s1>"      /* Same */
 848                                 "\003<s2>"      /* Same */
 849                                 "\004<s3>"      /* Same */
 850                                 "\005<s4>"      /* Same */
 851                                 "\006<s5>"      /* Same */
 852                                 "\007<s6>"      /* Same */
 853                                 "\010<s7>"      /* Same */
 854                                 "\011<s8>"      /* Same */
 855                                 "\012<s9>"      /* Same */
 856                                 "\013<b10>"     /* Undefined */
 857                                 "\014SYSCALL"   /* Have SYSCALL/SYSRET */
 858                                 "\015<s12>"     /* Same */
 859                                 "\016<s13>"     /* Same */
 860                                 "\017<s14>"     /* Same */
 861                                 "\020<s15>"     /* Same */
 862                                 "\021<s16>"     /* Same */
 863                                 "\022<s17>"     /* Same */
 864                                 "\023<b18>"     /* Reserved, unknown */
 865                                 "\024MP"        /* Multiprocessor Capable */
 866                                 "\025NX"        /* Has EFER.NXE, NX */
 867                                 "\026<b21>"     /* Undefined */
 868                                 "\027MMX+"      /* AMD MMX Extensions */
 869                                 "\030<s23>"     /* Same */
 870                                 "\031<s24>"     /* Same */
 871                                 "\032FFXSR"     /* Fast FXSAVE/FXRSTOR */
 872                                 "\033Page1GB"   /* 1-GB large page support */
 873                                 "\034RDTSCP"    /* RDTSCP */
 874                                 "\035<b28>"     /* Undefined */
 875                                 "\036LM"        /* 64 bit long mode */
 876                                 "\0373DNow!+"   /* AMD 3DNow! Extensions */
 877                                 "\0403DNow!"    /* AMD 3DNow! */
 878                                 );
 879                         }
 880
 881                         if (amd_feature2 != 0) {
 882                                 printf("\n  AMD Features2=0x%b", amd_feature2,
 883                                 "\020"
 884                                 "\001LAHF"      /* LAHF/SAHF in long mode */
 885                                 "\002CMP"       /* CMP legacy */
 886                                 "\003SVM"       /* Secure Virtual Mode */
 887                                 "\004ExtAPIC"   /* Extended APIC register */
 888                                 "\005CR8"       /* CR8 in legacy mode */
 889                                 "\006ABM"       /* LZCNT instruction */
 890                                 "\007SSE4A"     /* SSE4A */
 891                                 "\010MAS"       /* Misaligned SSE mode */
 892                                 "\011Prefetch"  /* 3DNow! Prefetch/PrefetchW */
 893                                 "\012OSVW"      /* OS visible workaround */
 894                                 "\013IBS"       /* Instruction based sampling */
 895                                 "\014XOP"       /* XOP extended instructions */
 896                                 "\015SKINIT"    /* SKINIT/STGI */
 897                                 "\016WDT"       /* Watchdog timer */
 898                                 "\017<b14>"
 899                                 "\020LWP"       /* Lightweight Profiling */
 900                                 "\021FMA4"      /* 4-operand FMA instructions */
 901                                 "\022TCE"       /* Translation Cache Extension */
 902                                 "\023<b18>"
 903                                 "\024NodeId"    /* NodeId MSR support */
 904                                 "\025<b20>"
 905                                 "\026TBM"       /* Trailing Bit Manipulation */
 906                                 "\027Topology"  /* Topology Extensions */
 907                                 "\030PCXC"      /* Core perf count */
 908                                 "\031PNXC"      /* NB perf count */
 909                                 "\032<b25>"
 910                                 "\033DBE"       /* Data Breakpoint extension */
 911                                 "\034PTSC"      /* Performance TSC */
 912                                 "\035PL2I"      /* L2I perf count */
 913                                 "\036MWAITX"    /* MONITORX/MWAITX instructions */
 914                                 "\037<b30>"
 915                                 "\040<b31>"
 916                                 );
 917                         }
 918
 919                         if (cpu_stdext_feature != 0) {
 920                                 printf("\n  Structured Extended Features=0x%b",
 921                                     cpu_stdext_feature,
 922                                        "\020"
 923                                        /* RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */
 924                                        "\001FSGSBASE"
 925                                        "\002TSCADJ"
 926                                        "\003SGX"
 927                                        /* Bit Manipulation Instructions */
 928                                        "\004BMI1"
 929                                        /* Hardware Lock Elision */
 930                                        "\005HLE"
 931                                        /* Advanced Vector Instructions 2 */
 932                                        "\006AVX2"
 933                                        /* FDP_EXCPTN_ONLY */
 934                                        "\007FDPEXC"
 935                                        /* Supervisor Mode Execution Prot. */
 936                                        "\010SMEP"
 937                                        /* Bit Manipulation Instructions */
 938                                        "\011BMI2"
 939                                        "\012ERMS"
 940                                        /* Invalidate Processor Context ID */
 941                                        "\013INVPCID"
 942                                        /* Restricted Transactional Memory */
 943                                        "\014RTM"
 944                                        "\015PQM"
 945                                        "\016NFPUSG"
 946                                        /* Intel Memory Protection Extensions */
 947                                        "\017MPX"
 948                                        "\020PQE"
 949                                        /* AVX512 Foundation */
 950                                        "\021AVX512F"
 951                                        "\022AVX512DQ"
 952                                        /* Enhanced NRBG */
 953                                        "\023RDSEED"
 954                                        /* ADCX + ADOX */
 955                                        "\024ADX"
 956                                        /* Supervisor Mode Access Prevention */
 957                                        "\025SMAP"
 958                                        "\026AVX512IFMA"
 959                                        "\027PCOMMIT"
 960                                        "\030CLFLUSHOPT"
 961                                        "\031CLWB"
 962                                        "\032PROCTRACE"
 963                                        "\033AVX512PF"
 964                                        "\034AVX512ER"
 965                                        "\035AVX512CD"
 966                                        "\036SHA"
 967                                        "\037AVX512BW"
 968                                        "\040AVX512VL"
 969                                        );
 970                         }
 971
 972                         if (cpu_stdext_feature2 != 0) {
 973                                 printf("\n  Structured Extended Features2=0x%b",
 974                                     cpu_stdext_feature2,
 975                                        "\020"
 976                                        "\001PREFETCHWT1"
 977                                        "\002AVX512VBMI"
 978                                        "\003UMIP"
 979                                        "\004PKU"
 980                                        "\005OSPKE"
 981                                        "\027RDPID"
 982                                        "\037SGXLC"
 983                                        );
 984                         }
 985
 986                         if (cpu_stdext_feature3 != 0) {
 987                                 printf("\n  Structured Extended Features3=0x%b",
 988                                     cpu_stdext_feature3,
 989                                        "\020"
 990                                        "\033IBPB"
 991                                        "\034STIBP"
 992                                        "\036ARCH_CAP"
 993                                        );
 994                         }
 995
 996                         if ((cpu_feature2 & CPUID2_XSAVE) != 0) {
 997                                 cpuid_count(0xd, 0x1, regs);
 998                                 if (regs[0] != 0) {
 999                                         printf("\n  XSAVE Features=0x%b",
1000                                             regs[0],
1001                                             "\020"
1002                                             "\001XSAVEOPT"
1003                                             "\002XSAVEC"
1004                                             "\003XINUSE"
1005                                             "\004XSAVES");
1006                                 }
1007                         }
1008
1009                         if (cpu_ia32_arch_caps != 0) {
1010                                 printf("\n  IA32_ARCH_CAPS=0x%b",
1011                                     (u_int)cpu_ia32_arch_caps,
1012                                        "\020"
1013                                        "\001RDCL_NO"
1014                                        "\002IBRS_ALL"
1015                                        );
1016                         }
1017
1018                         if (amd_extended_feature_extensions != 0) {
1019                                 printf("\n  "
1020                                     "AMD Extended Feature Extensions ID EBX="
1021                                     "0x%b", amd_extended_feature_extensions,
1022                                     "\020"
1023                                     "\001CLZERO"
1024                                     "\002IRPerf"
1025                                     "\003XSaveErPtr");
1026                         }
1027
1028                         if (via_feature_rng != 0 || via_feature_xcrypt != 0)
1029                                 print_via_padlock_info();
1030
1031                         if (cpu_feature2 & CPUID2_VMX)
1032                                 print_vmx_info();
1033
1034                         if (amd_feature2 & AMDID2_SVM)
1035                                 print_svm_info();
1036
1037                         if ((cpu_feature & CPUID_HTT) &&
1038                             cpu_vendor_id == CPU_VENDOR_AMD)
1039                                 cpu_feature &= ~CPUID_HTT;
1040
1041                         /*
1042                          * If this CPU supports P-state invariant TSC then
1043                          * mention the capability.
1044                          */
1045                         if (tsc_is_invariant) {
1046                                 printf("\n  TSC: P-state invariant");
1047                                 if (tsc_perf_stat)
1048                                         printf(", performance statistics");
1049                         }
1050                 }
1051 #ifdef __i386__
1052         } else if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
1053                 printf("  DIR=0x%04x", cyrix_did);
1054                 printf("  Stepping=%u", (cyrix_did & 0xf000) >> 12);
1055                 printf("  Revision=%u", (cyrix_did & 0x0f00) >> 8);
1056 #ifndef CYRIX_CACHE_REALLY_WORKS
1057                 if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700)
1058                         printf("\n  CPU cache: write-through mode");
1059 #endif
1060 #endif
1061         }
1062
1063         /* Avoid ugly blank lines: only print newline when we have to. */
1064         if (*cpu_vendor || cpu_id)
1065                 printf("\n");
1066
1067         if (bootverbose) {
1068                 if (cpu_vendor_id == CPU_VENDOR_AMD)
1069                         print_AMD_info();
1070                 else if (cpu_vendor_id == CPU_VENDOR_INTEL)
1071                         print_INTEL_info();
1072 #ifdef __i386__
1073                 else if (cpu_vendor_id == CPU_VENDOR_TRANSMETA)
1074                         print_transmeta_info();
1075 #endif
1076         }
1077
1078         print_hypervisor_info();
1079 }
1080
1081 #ifdef __i386__
1082 void
1083 panicifcpuunsupported(void)
1084 {
1085
1086 #if !defined(lint)
1087 #if !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU)
1088 #error This kernel is not configured for one of the supported CPUs
1089 #endif
1090 #else /* lint */
1091 #endif /* lint */
1092         /*
1093          * Now that we have told the user what they have,
1094          * let them know if that machine type isn't configured.
1095          */
1096         switch (cpu_class) {
1097         case CPUCLASS_286:      /* a 286 should not make it this far, anyway */
1098         case CPUCLASS_386:
1099 #if !defined(I486_CPU)
1100         case CPUCLASS_486:
1101 #endif
1102 #if !defined(I586_CPU)
1103         case CPUCLASS_586:
1104 #endif
1105 #if !defined(I686_CPU)
1106         case CPUCLASS_686:
1107 #endif
1108                 panic("CPU class not configured");
1109         default:
1110                 break;
1111         }
1112 }
1113
1114 static  volatile u_int trap_by_rdmsr;
1115
1116 /*
1117  * Special exception 6 handler.
1118  * The rdmsr instruction generates invalid opcodes fault on 486-class
1119  * Cyrix CPU.  Stacked eip register points the rdmsr instruction in the
1120  * function identblue() when this handler is called.  Stacked eip should
1121  * be advanced.
1122  */
1123 inthand_t       bluetrap6;
1124 #ifdef __GNUCLIKE_ASM
1125 __asm
1126 ("                                                                      \n\
1127         .text                                                           \n\
1128         .p2align 2,0x90                                                 \n\
1129         .type   " __XSTRING(CNAME(bluetrap6)) ",@function               \n\
1130 " __XSTRING(CNAME(bluetrap6)) ":                                        \n\
1131         ss                                                              \n\
1132         movl    $0xa8c1d," __XSTRING(CNAME(trap_by_rdmsr)) "            \n\
1133         addl    $2, (%esp)      /* rdmsr is a 2-byte instruction */     \n\
1134         iret                                                            \n\
1135 ");
1136 #endif
1137
1138 /*
1139  * Special exception 13 handler.
1140  * Accessing non-existent MSR generates general protection fault.
1141  */
1142 inthand_t       bluetrap13;
1143 #ifdef __GNUCLIKE_ASM
1144 __asm
1145 ("                                                                      \n\
1146         .text                                                           \n\
1147         .p2align 2,0x90                                                 \n\
1148         .type   " __XSTRING(CNAME(bluetrap13)) ",@function              \n\
1149 " __XSTRING(CNAME(bluetrap13)) ":                                       \n\
1150         ss                                                              \n\
1151         movl    $0xa89c4," __XSTRING(CNAME(trap_by_rdmsr)) "            \n\
1152         popl    %eax            /* discard error code */                \n\
1153         addl    $2, (%esp)      /* rdmsr is a 2-byte instruction */     \n\
1154         iret                                                            \n\
1155 ");
1156 #endif
1157
1158 /*
1159  * Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not
1160  * support cpuid instruction.  This function should be called after
1161  * loading interrupt descriptor table register.
1162  *
1163  * I don't like this method that handles fault, but I couldn't get
1164  * information for any other methods.  Does blue giant know?
1165  */
1166 static int
1167 identblue(void)
1168 {
1169
1170         trap_by_rdmsr = 0;
1171
1172         /*
1173          * Cyrix 486-class CPU does not support rdmsr instruction.
1174          * The rdmsr instruction generates invalid opcode fault, and exception
1175          * will be trapped by bluetrap6() on Cyrix 486-class CPU.  The
1176          * bluetrap6() set the magic number to trap_by_rdmsr.
1177          */
1178         setidt(IDT_UD, bluetrap6, SDT_SYS386TGT, SEL_KPL,
1179             GSEL(GCODE_SEL, SEL_KPL));
1180
1181         /*
1182          * Certain BIOS disables cpuid instruction of Cyrix 6x86MX CPU.
1183          * In this case, rdmsr generates general protection fault, and
1184          * exception will be trapped by bluetrap13().
1185          */
1186         setidt(IDT_GP, bluetrap13, SDT_SYS386TGT, SEL_KPL,
1187             GSEL(GCODE_SEL, SEL_KPL));
1188
1189         rdmsr(0x1002);          /* Cyrix CPU generates fault. */
1190
1191         if (trap_by_rdmsr == 0xa8c1d)
1192                 return IDENTBLUE_CYRIX486;
1193         else if (trap_by_rdmsr == 0xa89c4)
1194                 return IDENTBLUE_CYRIXM2;
1195         return IDENTBLUE_IBMCPU;
1196 }
1197
1198
1199 /*
1200  * identifycyrix() set lower 16 bits of cyrix_did as follows:
1201  *
1202  *  F E D C B A 9 8 7 6 5 4 3 2 1 0
1203  * +-------+-------+---------------+
1204  * |  SID  |  RID  |   Device ID   |
1205  * |    (DIR 1)    |    (DIR 0)    |
1206  * +-------+-------+---------------+
1207  */
1208 static void
1209 identifycyrix(void)
1210 {
1211         register_t saveintr;
1212         int     ccr2_test = 0, dir_test = 0;
1213         u_char  ccr2, ccr3;
1214
1215         saveintr = intr_disable();
1216
1217         ccr2 = read_cyrix_reg(CCR2);
1218         write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW);
1219         read_cyrix_reg(CCR2);
1220         if (read_cyrix_reg(CCR2) != ccr2)
1221                 ccr2_test = 1;
1222         write_cyrix_reg(CCR2, ccr2);
1223
1224         ccr3 = read_cyrix_reg(CCR3);
1225         write_cyrix_reg(CCR3, ccr3 ^ CCR3_MAPEN3);
1226         read_cyrix_reg(CCR3);
1227         if (read_cyrix_reg(CCR3) != ccr3)
1228                 dir_test = 1;                                   /* CPU supports DIRs. */
1229         write_cyrix_reg(CCR3, ccr3);
1230
1231         if (dir_test) {
1232                 /* Device ID registers are available. */
1233                 cyrix_did = read_cyrix_reg(DIR1) << 8;
1234                 cyrix_did += read_cyrix_reg(DIR0);
1235         } else if (ccr2_test)
1236                 cyrix_did = 0x0010;             /* 486S A-step */
1237         else
1238                 cyrix_did = 0x00ff;             /* Old 486SLC/DLC and TI486SXLC/SXL */
1239
1240         intr_restore(saveintr);
1241 }
1242 #endif
1243
1244 /* Update TSC freq with the value indicated by the caller. */
1245 static void
1246 tsc_freq_changed(void *arg __unused, const struct cf_level *level, int status)
1247 {
1248
1249         /* If there was an error during the transition, don't do anything. */
1250         if (status != 0)
1251                 return;
1252
1253         /* Total setting for this level gives the new frequency in MHz. */
1254         hw_clockrate = level->total_set.freq;
1255 }
1256
1257 static void
1258 hook_tsc_freq(void *arg __unused)
1259 {
1260
1261         if (tsc_is_invariant)
1262                 return;
1263
1264         tsc_post_tag = EVENTHANDLER_REGISTER(cpufreq_post_change,
1265             tsc_freq_changed, NULL, EVENTHANDLER_PRI_ANY);
1266 }
1267
1268 SYSINIT(hook_tsc_freq, SI_SUB_CONFIGURE, SI_ORDER_ANY, hook_tsc_freq, NULL);
1269
1270 static const char *const vm_bnames[] = {
1271         "QEMU",                         /* QEMU */
1272         "Plex86",                       /* Plex86 */
1273         "Bochs",                        /* Bochs */
1274         "Xen",                          /* Xen */
1275         "BHYVE",                        /* bhyve */
1276         "Seabios",                      /* KVM */
1277         NULL
1278 };
1279
1280 static const char *const vm_pnames[] = {
1281         "VMware Virtual Platform",      /* VMWare VM */
1282         "Virtual Machine",              /* Microsoft VirtualPC */
1283         "VirtualBox",                   /* Sun xVM VirtualBox */
1284         "Parallels Virtual Platform",   /* Parallels VM */
1285         "KVM",                          /* KVM */
1286         NULL
1287 };
1288
1289 void
1290 identify_hypervisor(void)
1291 {
1292         u_int regs[4];
1293         char *p;
1294         int i;
1295
1296         /*
1297          * [RFC] CPUID usage for interaction between Hypervisors and Linux.
1298          * http://lkml.org/lkml/2008/10/1/246
1299          *
1300          * KB1009458: Mechanisms to determine if software is running in
1301          * a VMware virtual machine
1302          * http://kb.vmware.com/kb/1009458
1303          */
1304         if (cpu_feature2 & CPUID2_HV) {
1305                 vm_guest = VM_GUEST_VM;
1306                 do_cpuid(0x40000000, regs);
1307
1308                 /*
1309                  * KVM from Linux kernels prior to commit
1310                  * 57c22e5f35aa4b9b2fe11f73f3e62bbf9ef36190 set %eax
1311                  * to 0 rather than a valid hv_high value.  Check for
1312                  * the KVM signature bytes and fixup %eax to the
1313                  * highest supported leaf in that case.
1314                  */
1315                 if (regs[0] == 0 && regs[1] == 0x4b4d564b &&
1316                     regs[2] == 0x564b4d56 && regs[3] == 0x0000004d)
1317                         regs[0] = 0x40000001;
1318
1319                 if (regs[0] >= 0x40000000) {
1320                         hv_high = regs[0];
1321                         ((u_int *)&hv_vendor)[0] = regs[1];
1322                         ((u_int *)&hv_vendor)[1] = regs[2];
1323                         ((u_int *)&hv_vendor)[2] = regs[3];
1324                         hv_vendor[12] = '\0';
1325                         if (strcmp(hv_vendor, "VMwareVMware") == 0)
1326                                 vm_guest = VM_GUEST_VMWARE;
1327                         else if (strcmp(hv_vendor, "Microsoft Hv") == 0)
1328                                 vm_guest = VM_GUEST_HV;
1329                         else if (strcmp(hv_vendor, "KVMKVMKVM") == 0)
1330                                 vm_guest = VM_GUEST_KVM;
1331                         else if (strcmp(hv_vendor, "bhyve bhyve") == 0)
1332                                 vm_guest = VM_GUEST_BHYVE;
1333                 }
1334                 return;
1335         }
1336
1337         /*
1338          * Examine SMBIOS strings for older hypervisors.
1339          */
1340         p = kern_getenv("smbios.system.serial");
1341         if (p != NULL) {
1342                 if (strncmp(p, "VMware-", 7) == 0 || strncmp(p, "VMW", 3) == 0) {
1343                         vmware_hvcall(VMW_HVCMD_GETVERSION, regs);
1344                         if (regs[1] == VMW_HVMAGIC) {
1345                                 vm_guest = VM_GUEST_VMWARE;
1346                                 freeenv(p);
1347                                 return;
1348                         }
1349                 }
1350                 freeenv(p);
1351         }
1352
1353         /*
1354          * XXX: Some of these entries may not be needed since they were
1355          * added to FreeBSD before the checks above.
1356          */
1357         p = kern_getenv("smbios.bios.vendor");
1358         if (p != NULL) {
1359                 for (i = 0; vm_bnames[i] != NULL; i++)
1360                         if (strcmp(p, vm_bnames[i]) == 0) {
1361                                 vm_guest = VM_GUEST_VM;
1362                                 freeenv(p);
1363                                 return;
1364                         }
1365                 freeenv(p);
1366         }
1367         p = kern_getenv("smbios.system.product");
1368         if (p != NULL) {
1369                 for (i = 0; vm_pnames[i] != NULL; i++)
1370                         if (strcmp(p, vm_pnames[i]) == 0) {
1371                                 vm_guest = VM_GUEST_VM;
1372                                 freeenv(p);
1373                                 return;
1374                         }
1375                 freeenv(p);
1376         }
1377 }
1378
1379 bool
1380 fix_cpuid(void)
1381 {
1382         uint64_t msr;
1383
1384         /*
1385          * Clear "Limit CPUID Maxval" bit and return true if the caller should
1386          * get the largest standard CPUID function number again if it is set
1387          * from BIOS.  It is necessary for probing correct CPU topology later
1388          * and for the correct operation of the AVX-aware userspace.
1389          */
1390         if (cpu_vendor_id == CPU_VENDOR_INTEL &&
1391             ((CPUID_TO_FAMILY(cpu_id) == 0xf &&
1392             CPUID_TO_MODEL(cpu_id) >= 0x3) ||
1393             (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
1394             CPUID_TO_MODEL(cpu_id) >= 0xe))) {
1395                 msr = rdmsr(MSR_IA32_MISC_ENABLE);
1396                 if ((msr & IA32_MISC_EN_LIMCPUID) != 0) {
1397                         msr &= ~IA32_MISC_EN_LIMCPUID;
1398                         wrmsr(MSR_IA32_MISC_ENABLE, msr);
1399                         return (true);
1400                 }
1401         }
1402
1403         /*
1404          * Re-enable AMD Topology Extension that could be disabled by BIOS
1405          * on some notebook processors.  Without the extension it's really
1406          * hard to determine the correct CPU cache topology.
1407          * See BIOS and Kernel Developer’s Guide (BKDG) for AMD Family 15h
1408          * Models 60h-6Fh Processors, Publication # 50742.
1409          */
1410         if (vm_guest == VM_GUEST_NO && cpu_vendor_id == CPU_VENDOR_AMD &&
1411             CPUID_TO_FAMILY(cpu_id) == 0x15) {
1412                 msr = rdmsr(MSR_EXTFEATURES);
1413                 if ((msr & ((uint64_t)1 << 54)) == 0) {
1414                         msr |= (uint64_t)1 << 54;
1415                         wrmsr(MSR_EXTFEATURES, msr);
1416                         return (true);
1417                 }
1418         }
1419         return (false);
1420 }
1421
1422 void
1423 identify_cpu1(void)
1424 {
1425         u_int regs[4];
1426
1427         do_cpuid(0, regs);
1428         cpu_high = regs[0];
1429         ((u_int *)&cpu_vendor)[0] = regs[1];
1430         ((u_int *)&cpu_vendor)[1] = regs[3];
1431         ((u_int *)&cpu_vendor)[2] = regs[2];
1432         cpu_vendor[12] = '\0';
1433
1434         do_cpuid(1, regs);
1435         cpu_id = regs[0];
1436         cpu_procinfo = regs[1];
1437         cpu_feature = regs[3];
1438         cpu_feature2 = regs[2];
1439 }
1440
1441 void
1442 identify_cpu2(void)
1443 {
1444         u_int regs[4], cpu_stdext_disable;
1445
1446         if (cpu_high >= 7) {
1447                 cpuid_count(7, 0, regs);
1448                 cpu_stdext_feature = regs[1];
1449
1450                 /*
1451                  * Some hypervisors failed to filter out unsupported
1452                  * extended features.  Allow to disable the
1453                  * extensions, activation of which requires setting a
1454                  * bit in CR4, and which VM monitors do not support.
1455                  */
1456                 cpu_stdext_disable = 0;
1457                 TUNABLE_INT_FETCH("hw.cpu_stdext_disable", &cpu_stdext_disable);
1458                 cpu_stdext_feature &= ~cpu_stdext_disable;
1459
1460                 cpu_stdext_feature2 = regs[2];
1461                 cpu_stdext_feature3 = regs[3];
1462
1463                 if ((cpu_stdext_feature3 & CPUID_STDEXT3_ARCH_CAP) != 0)
1464                         cpu_ia32_arch_caps = rdmsr(MSR_IA32_ARCH_CAP);
1465         }
1466 }
1467
1468 /*
1469  * Final stage of CPU identification.
1470  */
1471 void
1472 finishidentcpu(void)
1473 {
1474         u_int regs[4];
1475 #ifdef __i386__
1476         u_char ccr3;
1477 #endif
1478
1479         cpu_vendor_id = find_cpu_vendor_id();
1480
1481         if (fix_cpuid()) {
1482                 do_cpuid(0, regs);
1483                 cpu_high = regs[0];
1484         }
1485
1486         if (cpu_high >= 5 && (cpu_feature2 & CPUID2_MON) != 0) {
1487                 do_cpuid(5, regs);
1488                 cpu_mon_mwait_flags = regs[2];
1489                 cpu_mon_min_size = regs[0] &  CPUID5_MON_MIN_SIZE;
1490                 cpu_mon_max_size = regs[1] &  CPUID5_MON_MAX_SIZE;
1491         }
1492
1493         identify_cpu2();
1494
1495 #ifdef __i386__
1496         if (cpu_high > 0 &&
1497             (cpu_vendor_id == CPU_VENDOR_INTEL ||
1498              cpu_vendor_id == CPU_VENDOR_AMD ||
1499              cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
1500              cpu_vendor_id == CPU_VENDOR_CENTAUR ||
1501              cpu_vendor_id == CPU_VENDOR_NSC)) {
1502                 do_cpuid(0x80000000, regs);
1503                 if (regs[0] >= 0x80000000)
1504                         cpu_exthigh = regs[0];
1505         }
1506 #else
1507         if (cpu_vendor_id == CPU_VENDOR_INTEL ||
1508             cpu_vendor_id == CPU_VENDOR_AMD ||
1509             cpu_vendor_id == CPU_VENDOR_CENTAUR) {
1510                 do_cpuid(0x80000000, regs);
1511                 cpu_exthigh = regs[0];
1512         }
1513 #endif
1514         if (cpu_exthigh >= 0x80000001) {
1515                 do_cpuid(0x80000001, regs);
1516                 amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff);
1517                 amd_feature2 = regs[2];
1518         }
1519         if (cpu_exthigh >= 0x80000007) {
1520                 do_cpuid(0x80000007, regs);
1521                 amd_rascap = regs[1];
1522                 amd_pminfo = regs[3];
1523         }
1524         if (cpu_exthigh >= 0x80000008) {
1525                 do_cpuid(0x80000008, regs);
1526                 cpu_maxphyaddr = regs[0] & 0xff;
1527                 amd_extended_feature_extensions = regs[1];
1528                 cpu_procinfo2 = regs[2];
1529         } else {
1530                 cpu_maxphyaddr = (cpu_feature & CPUID_PAE) != 0 ? 36 : 32;
1531         }
1532
1533 #ifdef __i386__
1534         if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
1535                 if (cpu == CPU_486) {
1536                         /*
1537                          * These conditions are equivalent to:
1538                          *     - CPU does not support cpuid instruction.
1539                          *     - Cyrix/IBM CPU is detected.
1540                          */
1541                         if (identblue() == IDENTBLUE_IBMCPU) {
1542                                 strcpy(cpu_vendor, "IBM");
1543                                 cpu_vendor_id = CPU_VENDOR_IBM;
1544                                 cpu = CPU_BLUE;
1545                                 return;
1546                         }
1547                 }
1548                 switch (cpu_id & 0xf00) {
1549                 case 0x600:
1550                         /*
1551                          * Cyrix's datasheet does not describe DIRs.
1552                          * Therefor, I assume it does not have them
1553                          * and use the result of the cpuid instruction.
1554                          * XXX they seem to have it for now at least. -Peter
1555                          */
1556                         identifycyrix();
1557                         cpu = CPU_M2;
1558                         break;
1559                 default:
1560                         identifycyrix();
1561                         /*
1562                          * This routine contains a trick.
1563                          * Don't check (cpu_id & 0x00f0) == 0x50 to detect M2, now.
1564                          */
1565                         switch (cyrix_did & 0x00f0) {
1566                         case 0x00:
1567                         case 0xf0:
1568                                 cpu = CPU_486DLC;
1569                                 break;
1570                         case 0x10:
1571                                 cpu = CPU_CY486DX;
1572                                 break;
1573                         case 0x20:
1574                                 if ((cyrix_did & 0x000f) < 8)
1575                                         cpu = CPU_M1;
1576                                 else
1577                                         cpu = CPU_M1SC;
1578                                 break;
1579                         case 0x30:
1580                                 cpu = CPU_M1;
1581                                 break;
1582                         case 0x40:
1583                                 /* MediaGX CPU */
1584                                 cpu = CPU_M1SC;
1585                                 break;
1586                         default:
1587                                 /* M2 and later CPUs are treated as M2. */
1588                                 cpu = CPU_M2;
1589
1590                                 /*
1591                                  * enable cpuid instruction.
1592                                  */
1593                                 ccr3 = read_cyrix_reg(CCR3);
1594                                 write_cyrix_reg(CCR3, CCR3_MAPEN0);
1595                                 write_cyrix_reg(CCR4, read_cyrix_reg(CCR4) | CCR4_CPUID);
1596                                 write_cyrix_reg(CCR3, ccr3);
1597
1598                                 do_cpuid(0, regs);
1599                                 cpu_high = regs[0];     /* eax */
1600                                 do_cpuid(1, regs);
1601                                 cpu_id = regs[0];       /* eax */
1602                                 cpu_feature = regs[3];  /* edx */
1603                                 break;
1604                         }
1605                 }
1606         } else if (cpu == CPU_486 && *cpu_vendor == '\0') {
1607                 /*
1608                  * There are BlueLightning CPUs that do not change
1609                  * undefined flags by dividing 5 by 2.  In this case,
1610                  * the CPU identification routine in locore.s leaves
1611                  * cpu_vendor null string and puts CPU_486 into the
1612                  * cpu.
1613                  */
1614                 if (identblue() == IDENTBLUE_IBMCPU) {
1615                         strcpy(cpu_vendor, "IBM");
1616                         cpu_vendor_id = CPU_VENDOR_IBM;
1617                         cpu = CPU_BLUE;
1618                         return;
1619                 }
1620         }
1621 #endif
1622 }
1623
1624 int
1625 pti_get_default(void)
1626 {
1627
1628         if (strcmp(cpu_vendor, AMD_VENDOR_ID) == 0)
1629                 return (0);
1630         if ((cpu_ia32_arch_caps & IA32_ARCH_CAP_RDCL_NO) != 0)
1631                 return (0);
1632         return (1);
1633 }
1634
1635 static u_int
1636 find_cpu_vendor_id(void)
1637 {
1638         int     i;
1639
1640         for (i = 0; i < nitems(cpu_vendors); i++)
1641                 if (strcmp(cpu_vendor, cpu_vendors[i].vendor) == 0)
1642                         return (cpu_vendors[i].vendor_id);
1643         return (0);
1644 }
1645
1646 static void
1647 print_AMD_assoc(int i)
1648 {
1649         if (i == 255)
1650                 printf(", fully associative\n");
1651         else
1652                 printf(", %d-way associative\n", i);
1653 }
1654
1655 static void
1656 print_AMD_l2_assoc(int i)
1657 {
1658         switch (i & 0x0f) {
1659         case 0: printf(", disabled/not present\n"); break;
1660         case 1: printf(", direct mapped\n"); break;
1661         case 2: printf(", 2-way associative\n"); break;
1662         case 4: printf(", 4-way associative\n"); break;
1663         case 6: printf(", 8-way associative\n"); break;
1664         case 8: printf(", 16-way associative\n"); break;
1665         case 15: printf(", fully associative\n"); break;
1666         default: printf(", reserved configuration\n"); break;
1667         }
1668 }
1669
1670 static void
1671 print_AMD_info(void)
1672 {
1673 #ifdef __i386__
1674         uint64_t amd_whcr;
1675 #endif
1676         u_int regs[4];
1677
1678         if (cpu_exthigh >= 0x80000005) {
1679                 do_cpuid(0x80000005, regs);
1680                 printf("L1 2MB data TLB: %d entries", (regs[0] >> 16) & 0xff);
1681                 print_AMD_assoc(regs[0] >> 24);
1682
1683                 printf("L1 2MB instruction TLB: %d entries", regs[0] & 0xff);
1684                 print_AMD_assoc((regs[0] >> 8) & 0xff);
1685
1686                 printf("L1 4KB data TLB: %d entries", (regs[1] >> 16) & 0xff);
1687                 print_AMD_assoc(regs[1] >> 24);
1688
1689                 printf("L1 4KB instruction TLB: %d entries", regs[1] & 0xff);
1690                 print_AMD_assoc((regs[1] >> 8) & 0xff);
1691
1692                 printf("L1 data cache: %d kbytes", regs[2] >> 24);
1693                 printf(", %d bytes/line", regs[2] & 0xff);
1694                 printf(", %d lines/tag", (regs[2] >> 8) & 0xff);
1695                 print_AMD_assoc((regs[2] >> 16) & 0xff);
1696
1697                 printf("L1 instruction cache: %d kbytes", regs[3] >> 24);
1698                 printf(", %d bytes/line", regs[3] & 0xff);
1699                 printf(", %d lines/tag", (regs[3] >> 8) & 0xff);
1700                 print_AMD_assoc((regs[3] >> 16) & 0xff);
1701         }
1702
1703         if (cpu_exthigh >= 0x80000006) {
1704                 do_cpuid(0x80000006, regs);
1705                 if ((regs[0] >> 16) != 0) {
1706                         printf("L2 2MB data TLB: %d entries",
1707                             (regs[0] >> 16) & 0xfff);
1708                         print_AMD_l2_assoc(regs[0] >> 28);
1709                         printf("L2 2MB instruction TLB: %d entries",
1710                             regs[0] & 0xfff);
1711                         print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
1712                 } else {
1713                         printf("L2 2MB unified TLB: %d entries",
1714                             regs[0] & 0xfff);
1715                         print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
1716                 }
1717                 if ((regs[1] >> 16) != 0) {
1718                         printf("L2 4KB data TLB: %d entries",
1719                             (regs[1] >> 16) & 0xfff);
1720                         print_AMD_l2_assoc(regs[1] >> 28);
1721
1722                         printf("L2 4KB instruction TLB: %d entries",
1723                             (regs[1] >> 16) & 0xfff);
1724                         print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
1725                 } else {
1726                         printf("L2 4KB unified TLB: %d entries",
1727                             (regs[1] >> 16) & 0xfff);
1728                         print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
1729                 }
1730                 printf("L2 unified cache: %d kbytes", regs[2] >> 16);
1731                 printf(", %d bytes/line", regs[2] & 0xff);
1732                 printf(", %d lines/tag", (regs[2] >> 8) & 0x0f);
1733                 print_AMD_l2_assoc((regs[2] >> 12) & 0x0f);
1734         }
1735
1736 #ifdef __i386__
1737         if (((cpu_id & 0xf00) == 0x500)
1738             && (((cpu_id & 0x0f0) > 0x80)
1739                 || (((cpu_id & 0x0f0) == 0x80)
1740                     && (cpu_id & 0x00f) > 0x07))) {
1741                 /* K6-2(new core [Stepping 8-F]), K6-III or later */
1742                 amd_whcr = rdmsr(0xc0000082);
1743                 if (!(amd_whcr & (0x3ff << 22))) {
1744                         printf("Write Allocate Disable\n");
1745                 } else {
1746                         printf("Write Allocate Enable Limit: %dM bytes\n",
1747                             (u_int32_t)((amd_whcr & (0x3ff << 22)) >> 22) * 4);
1748                         printf("Write Allocate 15-16M bytes: %s\n",
1749                             (amd_whcr & (1 << 16)) ? "Enable" : "Disable");
1750                 }
1751         } else if (((cpu_id & 0xf00) == 0x500)
1752                    && ((cpu_id & 0x0f0) > 0x50)) {
1753                 /* K6, K6-2(old core) */
1754                 amd_whcr = rdmsr(0xc0000082);
1755                 if (!(amd_whcr & (0x7f << 1))) {
1756                         printf("Write Allocate Disable\n");
1757                 } else {
1758                         printf("Write Allocate Enable Limit: %dM bytes\n",
1759                             (u_int32_t)((amd_whcr & (0x7f << 1)) >> 1) * 4);
1760                         printf("Write Allocate 15-16M bytes: %s\n",
1761                             (amd_whcr & 0x0001) ? "Enable" : "Disable");
1762                         printf("Hardware Write Allocate Control: %s\n",
1763                             (amd_whcr & 0x0100) ? "Enable" : "Disable");
1764                 }
1765         }
1766 #endif
1767         /*
1768          * Opteron Rev E shows a bug as in very rare occasions a read memory
1769          * barrier is not performed as expected if it is followed by a
1770          * non-atomic read-modify-write instruction.
1771          * As long as that bug pops up very rarely (intensive machine usage
1772          * on other operating systems generally generates one unexplainable
1773          * crash any 2 months) and as long as a model specific fix would be
1774          * impractical at this stage, print out a warning string if the broken
1775          * model and family are identified.
1776          */
1777         if (CPUID_TO_FAMILY(cpu_id) == 0xf && CPUID_TO_MODEL(cpu_id) >= 0x20 &&
1778             CPUID_TO_MODEL(cpu_id) <= 0x3f)
1779                 printf("WARNING: This architecture revision has known SMP "
1780                     "hardware bugs which may cause random instability\n");
1781 }
1782
1783 static void
1784 print_INTEL_info(void)
1785 {
1786         u_int regs[4];
1787         u_int rounds, regnum;
1788         u_int nwaycode, nway;
1789
1790         if (cpu_high >= 2) {
1791                 rounds = 0;
1792                 do {
1793                         do_cpuid(0x2, regs);
1794                         if (rounds == 0 && (rounds = (regs[0] & 0xff)) == 0)
1795                                 break;  /* we have a buggy CPU */
1796
1797                         for (regnum = 0; regnum <= 3; ++regnum) {
1798                                 if (regs[regnum] & (1<<31))
1799                                         continue;
1800                                 if (regnum != 0)
1801                                         print_INTEL_TLB(regs[regnum] & 0xff);
1802                                 print_INTEL_TLB((regs[regnum] >> 8) & 0xff);
1803                                 print_INTEL_TLB((regs[regnum] >> 16) & 0xff);
1804                                 print_INTEL_TLB((regs[regnum] >> 24) & 0xff);
1805                         }
1806                 } while (--rounds > 0);
1807         }
1808
1809         if (cpu_exthigh >= 0x80000006) {
1810                 do_cpuid(0x80000006, regs);
1811                 nwaycode = (regs[2] >> 12) & 0x0f;
1812                 if (nwaycode >= 0x02 && nwaycode <= 0x08)
1813                         nway = 1 << (nwaycode / 2);
1814                 else
1815                         nway = 0;
1816                 printf("L2 cache: %u kbytes, %u-way associative, %u bytes/line\n",
1817                     (regs[2] >> 16) & 0xffff, nway, regs[2] & 0xff);
1818         }
1819 }
1820
1821 static void
1822 print_INTEL_TLB(u_int data)
1823 {
1824         switch (data) {
1825         case 0x0:
1826         case 0x40:
1827         default:
1828                 break;
1829         case 0x1:
1830                 printf("Instruction TLB: 4 KB pages, 4-way set associative, 32 entries\n");
1831                 break;
1832         case 0x2:
1833                 printf("Instruction TLB: 4 MB pages, fully associative, 2 entries\n");
1834                 break;
1835         case 0x3:
1836                 printf("Data TLB: 4 KB pages, 4-way set associative, 64 entries\n");
1837                 break;
1838         case 0x4:
1839                 printf("Data TLB: 4 MB Pages, 4-way set associative, 8 entries\n");
1840                 break;
1841         case 0x6:
1842                 printf("1st-level instruction cache: 8 KB, 4-way set associative, 32 byte line size\n");
1843                 break;
1844         case 0x8:
1845                 printf("1st-level instruction cache: 16 KB, 4-way set associative, 32 byte line size\n");
1846                 break;
1847         case 0x9:
1848                 printf("1st-level instruction cache: 32 KB, 4-way set associative, 64 byte line size\n");
1849                 break;
1850         case 0xa:
1851                 printf("1st-level data cache: 8 KB, 2-way set associative, 32 byte line size\n");
1852                 break;
1853         case 0xb:
1854                 printf("Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries\n");
1855                 break;
1856         case 0xc:
1857                 printf("1st-level data cache: 16 KB, 4-way set associative, 32 byte line size\n");
1858                 break;
1859         case 0xd:
1860                 printf("1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size");
1861                 break;
1862         case 0xe:
1863                 printf("1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size\n");
1864                 break;
1865         case 0x1d:
1866                 printf("2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size\n");
1867                 break;
1868         case 0x21:
1869                 printf("2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size\n");
1870                 break;
1871         case 0x22:
1872                 printf("3rd-level cache: 512 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1873                 break;
1874         case 0x23:
1875                 printf("3rd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n");
1876                 break;
1877         case 0x24:
1878                 printf("2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size\n");
1879                 break;
1880         case 0x25:
1881                 printf("3rd-level cache: 2 MB, 8-way set associative, sectored cache, 64 byte line size\n");
1882                 break;
1883         case 0x29:
1884                 printf("3rd-level cache: 4 MB, 8-way set associative, sectored cache, 64 byte line size\n");
1885                 break;
1886         case 0x2c:
1887                 printf("1st-level data cache: 32 KB, 8-way set associative, 64 byte line size\n");
1888                 break;
1889         case 0x30:
1890                 printf("1st-level instruction cache: 32 KB, 8-way set associative, 64 byte line size\n");
1891                 break;
1892         case 0x39: /* De-listed in SDM rev. 54 */
1893                 printf("2nd-level cache: 128 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1894                 break;
1895         case 0x3b: /* De-listed in SDM rev. 54 */
1896                 printf("2nd-level cache: 128 KB, 2-way set associative, sectored cache, 64 byte line size\n");
1897                 break;
1898         case 0x3c: /* De-listed in SDM rev. 54 */
1899                 printf("2nd-level cache: 256 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1900                 break;
1901         case 0x41:
1902                 printf("2nd-level cache: 128 KB, 4-way set associative, 32 byte line size\n");
1903                 break;
1904         case 0x42:
1905                 printf("2nd-level cache: 256 KB, 4-way set associative, 32 byte line size\n");
1906                 break;
1907         case 0x43:
1908                 printf("2nd-level cache: 512 KB, 4-way set associative, 32 byte line size\n");
1909                 break;
1910         case 0x44:
1911                 printf("2nd-level cache: 1 MB, 4-way set associative, 32 byte line size\n");
1912                 break;
1913         case 0x45:
1914                 printf("2nd-level cache: 2 MB, 4-way set associative, 32 byte line size\n");
1915                 break;
1916         case 0x46:
1917                 printf("3rd-level cache: 4 MB, 4-way set associative, 64 byte line size\n");
1918                 break;
1919         case 0x47:
1920                 printf("3rd-level cache: 8 MB, 8-way set associative, 64 byte line size\n");
1921                 break;
1922         case 0x48:
1923                 printf("2nd-level cache: 3MByte, 12-way set associative, 64 byte line size\n");
1924                 break;
1925         case 0x49:
1926                 if (CPUID_TO_FAMILY(cpu_id) == 0xf &&
1927                     CPUID_TO_MODEL(cpu_id) == 0x6)
1928                         printf("3rd-level cache: 4MB, 16-way set associative, 64-byte line size\n");
1929                 else
1930                         printf("2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size");
1931                 break;
1932         case 0x4a:
1933                 printf("3rd-level cache: 6MByte, 12-way set associative, 64 byte line size\n");
1934                 break;
1935         case 0x4b:
1936                 printf("3rd-level cache: 8MByte, 16-way set associative, 64 byte line size\n");
1937                 break;
1938         case 0x4c:
1939                 printf("3rd-level cache: 12MByte, 12-way set associative, 64 byte line size\n");
1940                 break;
1941         case 0x4d:
1942                 printf("3rd-level cache: 16MByte, 16-way set associative, 64 byte line size\n");
1943                 break;
1944         case 0x4e:
1945                 printf("2nd-level cache: 6MByte, 24-way set associative, 64 byte line size\n");
1946                 break;
1947         case 0x4f:
1948                 printf("Instruction TLB: 4 KByte pages, 32 entries\n");
1949                 break;
1950         case 0x50:
1951                 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 64 entries\n");
1952                 break;
1953         case 0x51:
1954                 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 128 entries\n");
1955                 break;
1956         case 0x52:
1957                 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 256 entries\n");
1958                 break;
1959         case 0x55:
1960                 printf("Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries\n");
1961                 break;
1962         case 0x56:
1963                 printf("Data TLB0: 4 MByte pages, 4-way set associative, 16 entries\n");
1964                 break;
1965         case 0x57:
1966                 printf("Data TLB0: 4 KByte pages, 4-way associative, 16 entries\n");
1967                 break;
1968         case 0x59:
1969                 printf("Data TLB0: 4 KByte pages, fully associative, 16 entries\n");
1970                 break;
1971         case 0x5a:
1972                 printf("Data TLB0: 2-MByte or 4 MByte pages, 4-way set associative, 32 entries\n");
1973                 break;
1974         case 0x5b:
1975                 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 64 entries\n");
1976                 break;
1977         case 0x5c:
1978                 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 128 entries\n");
1979                 break;
1980         case 0x5d:
1981                 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 256 entries\n");
1982                 break;
1983         case 0x60:
1984                 printf("1st-level data cache: 16 KB, 8-way set associative, sectored cache, 64 byte line size\n");
1985                 break;
1986         case 0x61:
1987                 printf("Instruction TLB: 4 KByte pages, fully associative, 48 entries\n");
1988                 break;
1989         case 0x63:
1990                 printf("Data TLB: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries and a separate array with 1 GByte pages, 4-way set associative, 4 entries\n");
1991                 break;
1992         case 0x64:
1993                 printf("Data TLB: 4 KBytes pages, 4-way set associative, 512 entries\n");
1994                 break;
1995         case 0x66:
1996                 printf("1st-level data cache: 8 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1997                 break;
1998         case 0x67:
1999                 printf("1st-level data cache: 16 KB, 4-way set associative, sectored cache, 64 byte line size\n");
2000                 break;
2001         case 0x68:
2002                 printf("1st-level data cache: 32 KB, 4 way set associative, sectored cache, 64 byte line size\n");
2003                 break;
2004         case 0x6a:
2005                 printf("uTLB: 4KByte pages, 8-way set associative, 64 entries\n");
2006                 break;
2007         case 0x6b:
2008                 printf("DTLB: 4KByte pages, 8-way set associative, 256 entries\n");
2009                 break;
2010         case 0x6c:
2011                 printf("DTLB: 2M/4M pages, 8-way set associative, 128 entries\n");
2012                 break;
2013         case 0x6d:
2014                 printf("DTLB: 1 GByte pages, fully associative, 16 entries\n");
2015                 break;
2016         case 0x70:
2017                 printf("Trace cache: 12K-uops, 8-way set associative\n");
2018                 break;
2019         case 0x71:
2020                 printf("Trace cache: 16K-uops, 8-way set associative\n");
2021                 break;
2022         case 0x72:
2023                 printf("Trace cache: 32K-uops, 8-way set associative\n");
2024                 break;
2025         case 0x76:
2026                 printf("Instruction TLB: 2M/4M pages, fully associative, 8 entries\n");
2027                 break;
2028         case 0x78:
2029                 printf("2nd-level cache: 1 MB, 4-way set associative, 64-byte line size\n");
2030                 break;
2031         case 0x79:
2032                 printf("2nd-level cache: 128 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2033                 break;
2034         case 0x7a:
2035                 printf("2nd-level cache: 256 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2036                 break;
2037         case 0x7b:
2038                 printf("2nd-level cache: 512 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2039                 break;
2040         case 0x7c:
2041                 printf("2nd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n");
2042                 break;
2043         case 0x7d:
2044                 printf("2nd-level cache: 2-MB, 8-way set associative, 64-byte line size\n");
2045                 break;
2046         case 0x7f:
2047                 printf("2nd-level cache: 512-KB, 2-way set associative, 64-byte line size\n");
2048                 break;
2049         case 0x80:
2050                 printf("2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size\n");
2051                 break;
2052         case 0x82:
2053                 printf("2nd-level cache: 256 KB, 8-way set associative, 32 byte line size\n");
2054                 break;
2055         case 0x83:
2056                 printf("2nd-level cache: 512 KB, 8-way set associative, 32 byte line size\n");
2057                 break;
2058         case 0x84:
2059                 printf("2nd-level cache: 1 MB, 8-way set associative, 32 byte line size\n");
2060                 break;
2061         case 0x85:
2062                 printf("2nd-level cache: 2 MB, 8-way set associative, 32 byte line size\n");
2063                 break;
2064         case 0x86:
2065                 printf("2nd-level cache: 512 KB, 4-way set associative, 64 byte line size\n");
2066                 break;
2067         case 0x87:
2068                 printf("2nd-level cache: 1 MB, 8-way set associative, 64 byte line size\n");
2069                 break;
2070         case 0xa0:
2071                 printf("DTLB: 4k pages, fully associative, 32 entries\n");
2072                 break;
2073         case 0xb0:
2074                 printf("Instruction TLB: 4 KB Pages, 4-way set associative, 128 entries\n");
2075                 break;
2076         case 0xb1:
2077                 printf("Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries\n");
2078                 break;
2079         case 0xb2:
2080                 printf("Instruction TLB: 4KByte pages, 4-way set associative, 64 entries\n");
2081                 break;
2082         case 0xb3:
2083                 printf("Data TLB: 4 KB Pages, 4-way set associative, 128 entries\n");
2084                 break;
2085         case 0xb4:
2086                 printf("Data TLB1: 4 KByte pages, 4-way associative, 256 entries\n");
2087                 break;
2088         case 0xb5:
2089                 printf("Instruction TLB: 4KByte pages, 8-way set associative, 64 entries\n");
2090                 break;
2091         case 0xb6:
2092                 printf("Instruction TLB: 4KByte pages, 8-way set associative, 128 entries\n");
2093                 break;
2094         case 0xba:
2095                 printf("Data TLB1: 4 KByte pages, 4-way associative, 64 entries\n");
2096                 break;
2097         case 0xc0:
2098                 printf("Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries\n");
2099                 break;
2100         case 0xc1:
2101                 printf("Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries\n");
2102                 break;
2103         case 0xc2:
2104                 printf("DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries\n");
2105                 break;
2106         case 0xc3:
2107                 printf("Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative, 1536 entries. Also 1GBbyte pages, 4-way, 16 entries\n");
2108                 break;
2109         case 0xc4:
2110                 printf("DTLB: 2M/4M Byte pages, 4-way associative, 32 entries\n");
2111                 break;
2112         case 0xca:
2113                 printf("Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries\n");
2114                 break;
2115         case 0xd0:
2116                 printf("3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size\n");
2117                 break;
2118         case 0xd1:
2119                 printf("3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size\n");
2120                 break;
2121         case 0xd2:
2122                 printf("3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size\n");
2123                 break;
2124         case 0xd6:
2125                 printf("3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size\n");
2126                 break;
2127         case 0xd7:
2128                 printf("3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size\n");
2129                 break;
2130         case 0xd8:
2131                 printf("3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size\n");
2132                 break;
2133         case 0xdc:
2134                 printf("3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size\n");
2135                 break;
2136         case 0xdd:
2137                 printf("3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size\n");
2138                 break;
2139         case 0xde:
2140                 printf("3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size\n");
2141                 break;
2142         case 0xe2:
2143                 printf("3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size\n");
2144                 break;
2145         case 0xe3:
2146                 printf("3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size\n");
2147                 break;
2148         case 0xe4:
2149                 printf("3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size\n");
2150                 break;
2151         case 0xea:
2152                 printf("3rd-level cache: 12MByte, 24-way set associative, 64 byte line size\n");
2153                 break;
2154         case 0xeb:
2155                 printf("3rd-level cache: 18MByte, 24-way set associative, 64 byte line size\n");
2156                 break;
2157         case 0xec:
2158                 printf("3rd-level cache: 24MByte, 24-way set associative, 64 byte line size\n");
2159                 break;
2160         case 0xf0:
2161                 printf("64-Byte prefetching\n");
2162                 break;
2163         case 0xf1:
2164                 printf("128-Byte prefetching\n");
2165                 break;
2166         }
2167 }
2168
2169 static void
2170 print_svm_info(void)
2171 {
2172         u_int features, regs[4];
2173         uint64_t msr;
2174         int comma;
2175
2176         printf("\n  SVM: ");
2177         do_cpuid(0x8000000A, regs);
2178         features = regs[3];
2179
2180         msr = rdmsr(MSR_VM_CR);
2181         if ((msr & VM_CR_SVMDIS) == VM_CR_SVMDIS)
2182                 printf("(disabled in BIOS) ");
2183
2184         if (!bootverbose) {
2185                 comma = 0;
2186                 if (features & (1 << 0)) {
2187                         printf("%sNP", comma ? "," : "");
2188                         comma = 1;
2189                 }
2190                 if (features & (1 << 3)) {
2191                         printf("%sNRIP", comma ? "," : "");
2192                         comma = 1;
2193                 }
2194                 if (features & (1 << 5)) {
2195                         printf("%sVClean", comma ? "," : "");
2196                         comma = 1;
2197                 }
2198                 if (features & (1 << 6)) {
2199                         printf("%sAFlush", comma ? "," : "");
2200                         comma = 1;
2201                 }
2202                 if (features & (1 << 7)) {
2203                         printf("%sDAssist", comma ? "," : "");
2204                         comma = 1;
2205                 }
2206                 printf("%sNAsids=%d", comma ? "," : "", regs[1]);
2207                 return;
2208         }
2209
2210         printf("Features=0x%b", features,
2211                "\020"
2212                "\001NP"                 /* Nested paging */
2213                "\002LbrVirt"            /* LBR virtualization */
2214                "\003SVML"               /* SVM lock */
2215                "\004NRIPS"              /* NRIP save */
2216                "\005TscRateMsr"         /* MSR based TSC rate control */
2217                "\006VmcbClean"          /* VMCB clean bits */
2218                "\007FlushByAsid"        /* Flush by ASID */
2219                "\010DecodeAssist"       /* Decode assist */
2220                "\011<b8>"
2221                "\012<b9>"
2222                "\013PauseFilter"        /* PAUSE intercept filter */
2223                "\014EncryptedMcodePatch"
2224                "\015PauseFilterThreshold" /* PAUSE filter threshold */
2225                "\016AVIC"               /* virtual interrupt controller */
2226                "\017<b14>"
2227                "\020V_VMSAVE_VMLOAD"
2228                "\021vGIF"
2229                "\022<b17>"
2230                "\023<b18>"
2231                "\024<b19>"
2232                "\025<b20>"
2233                "\026<b21>"
2234                "\027<b22>"
2235                "\030<b23>"
2236                "\031<b24>"
2237                "\032<b25>"
2238                "\033<b26>"
2239                "\034<b27>"
2240                "\035<b28>"
2241                "\036<b29>"
2242                "\037<b30>"
2243                "\040<b31>"
2244                 );
2245         printf("\nRevision=%d, ASIDs=%d", regs[0] & 0xff, regs[1]);
2246 }
2247
2248 #ifdef __i386__
2249 static void
2250 print_transmeta_info(void)
2251 {
2252         u_int regs[4], nreg = 0;
2253
2254         do_cpuid(0x80860000, regs);
2255         nreg = regs[0];
2256         if (nreg >= 0x80860001) {
2257                 do_cpuid(0x80860001, regs);
2258                 printf("  Processor revision %u.%u.%u.%u\n",
2259                        (regs[1] >> 24) & 0xff,
2260                        (regs[1] >> 16) & 0xff,
2261                        (regs[1] >> 8) & 0xff,
2262                        regs[1] & 0xff);
2263         }
2264         if (nreg >= 0x80860002) {
2265                 do_cpuid(0x80860002, regs);
2266                 printf("  Code Morphing Software revision %u.%u.%u-%u-%u\n",
2267                        (regs[1] >> 24) & 0xff,
2268                        (regs[1] >> 16) & 0xff,
2269                        (regs[1] >> 8) & 0xff,
2270                        regs[1] & 0xff,
2271                        regs[2]);
2272         }
2273         if (nreg >= 0x80860006) {
2274                 char info[65];
2275                 do_cpuid(0x80860003, (u_int*) &info[0]);
2276                 do_cpuid(0x80860004, (u_int*) &info[16]);
2277                 do_cpuid(0x80860005, (u_int*) &info[32]);
2278                 do_cpuid(0x80860006, (u_int*) &info[48]);
2279                 info[64] = 0;
2280                 printf("  %s\n", info);
2281         }
2282 }
2283 #endif
2284
2285 static void
2286 print_via_padlock_info(void)
2287 {
2288         u_int regs[4];
2289
2290         do_cpuid(0xc0000001, regs);
2291         printf("\n  VIA Padlock Features=0x%b", regs[3],
2292         "\020"
2293         "\003RNG"               /* RNG */
2294         "\007AES"               /* ACE */
2295         "\011AES-CTR"           /* ACE2 */
2296         "\013SHA1,SHA256"       /* PHE */
2297         "\015RSA"               /* PMM */
2298         );
2299 }
2300
2301 static uint32_t
2302 vmx_settable(uint64_t basic, int msr, int true_msr)
2303 {
2304         uint64_t val;
2305
2306         if (basic & (1ULL << 55))
2307                 val = rdmsr(true_msr);
2308         else
2309                 val = rdmsr(msr);
2310
2311         /* Just report the controls that can be set to 1. */
2312         return (val >> 32);
2313 }
2314
2315 static void
2316 print_vmx_info(void)
2317 {
2318         uint64_t basic, msr;
2319         uint32_t entry, exit, mask, pin, proc, proc2;
2320         int comma;
2321
2322         printf("\n  VT-x: ");
2323         msr = rdmsr(MSR_IA32_FEATURE_CONTROL);
2324         if (!(msr & IA32_FEATURE_CONTROL_VMX_EN))
2325                 printf("(disabled in BIOS) ");
2326         basic = rdmsr(MSR_VMX_BASIC);
2327         pin = vmx_settable(basic, MSR_VMX_PINBASED_CTLS,
2328             MSR_VMX_TRUE_PINBASED_CTLS);
2329         proc = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS,
2330             MSR_VMX_TRUE_PROCBASED_CTLS);
2331         if (proc & PROCBASED_SECONDARY_CONTROLS)
2332                 proc2 = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS2,
2333                     MSR_VMX_PROCBASED_CTLS2);
2334         else
2335                 proc2 = 0;
2336         exit = vmx_settable(basic, MSR_VMX_EXIT_CTLS, MSR_VMX_TRUE_EXIT_CTLS);
2337         entry = vmx_settable(basic, MSR_VMX_ENTRY_CTLS, MSR_VMX_TRUE_ENTRY_CTLS);
2338
2339         if (!bootverbose) {
2340                 comma = 0;
2341                 if (exit & VM_EXIT_SAVE_PAT && exit & VM_EXIT_LOAD_PAT &&
2342                     entry & VM_ENTRY_LOAD_PAT) {
2343                         printf("%sPAT", comma ? "," : "");
2344                         comma = 1;
2345                 }
2346                 if (proc & PROCBASED_HLT_EXITING) {
2347                         printf("%sHLT", comma ? "," : "");
2348                         comma = 1;
2349                 }
2350                 if (proc & PROCBASED_MTF) {
2351                         printf("%sMTF", comma ? "," : "");
2352                         comma = 1;
2353                 }
2354                 if (proc & PROCBASED_PAUSE_EXITING) {
2355                         printf("%sPAUSE", comma ? "," : "");
2356                         comma = 1;
2357                 }
2358                 if (proc2 & PROCBASED2_ENABLE_EPT) {
2359                         printf("%sEPT", comma ? "," : "");
2360                         comma = 1;
2361                 }
2362                 if (proc2 & PROCBASED2_UNRESTRICTED_GUEST) {
2363                         printf("%sUG", comma ? "," : "");
2364                         comma = 1;
2365                 }
2366                 if (proc2 & PROCBASED2_ENABLE_VPID) {
2367                         printf("%sVPID", comma ? "," : "");
2368                         comma = 1;
2369                 }
2370                 if (proc & PROCBASED_USE_TPR_SHADOW &&
2371                     proc2 & PROCBASED2_VIRTUALIZE_APIC_ACCESSES &&
2372                     proc2 & PROCBASED2_VIRTUALIZE_X2APIC_MODE &&
2373                     proc2 & PROCBASED2_APIC_REGISTER_VIRTUALIZATION &&
2374                     proc2 & PROCBASED2_VIRTUAL_INTERRUPT_DELIVERY) {
2375                         printf("%sVID", comma ? "," : "");
2376                         comma = 1;
2377                         if (pin & PINBASED_POSTED_INTERRUPT)
2378                                 printf(",PostIntr");
2379                 }
2380                 return;
2381         }
2382
2383         mask = basic >> 32;
2384         printf("Basic Features=0x%b", mask,
2385         "\020"
2386         "\02132PA"              /* 32-bit physical addresses */
2387         "\022SMM"               /* SMM dual-monitor */
2388         "\027INS/OUTS"          /* VM-exit info for INS and OUTS */
2389         "\030TRUE"              /* TRUE_CTLS MSRs */
2390         );
2391         printf("\n        Pin-Based Controls=0x%b", pin,
2392         "\020"
2393         "\001ExtINT"            /* External-interrupt exiting */
2394         "\004NMI"               /* NMI exiting */
2395         "\006VNMI"              /* Virtual NMIs */
2396         "\007PreTmr"            /* Activate VMX-preemption timer */
2397         "\010PostIntr"          /* Process posted interrupts */
2398         );
2399         printf("\n        Primary Processor Controls=0x%b", proc,
2400         "\020"
2401         "\003INTWIN"            /* Interrupt-window exiting */
2402         "\004TSCOff"            /* Use TSC offsetting */
2403         "\010HLT"               /* HLT exiting */
2404         "\012INVLPG"            /* INVLPG exiting */
2405         "\013MWAIT"             /* MWAIT exiting */
2406         "\014RDPMC"             /* RDPMC exiting */
2407         "\015RDTSC"             /* RDTSC exiting */
2408         "\020CR3-LD"            /* CR3-load exiting */
2409         "\021CR3-ST"            /* CR3-store exiting */
2410         "\024CR8-LD"            /* CR8-load exiting */
2411         "\025CR8-ST"            /* CR8-store exiting */
2412         "\026TPR"               /* Use TPR shadow */
2413         "\027NMIWIN"            /* NMI-window exiting */
2414         "\030MOV-DR"            /* MOV-DR exiting */
2415         "\031IO"                /* Unconditional I/O exiting */
2416         "\032IOmap"             /* Use I/O bitmaps */
2417         "\034MTF"               /* Monitor trap flag */
2418         "\035MSRmap"            /* Use MSR bitmaps */
2419         "\036MONITOR"           /* MONITOR exiting */
2420         "\037PAUSE"             /* PAUSE exiting */
2421         );
2422         if (proc & PROCBASED_SECONDARY_CONTROLS)
2423                 printf("\n        Secondary Processor Controls=0x%b", proc2,
2424                 "\020"
2425                 "\001APIC"              /* Virtualize APIC accesses */
2426                 "\002EPT"               /* Enable EPT */
2427                 "\003DT"                /* Descriptor-table exiting */
2428                 "\004RDTSCP"            /* Enable RDTSCP */
2429                 "\005x2APIC"            /* Virtualize x2APIC mode */
2430                 "\006VPID"              /* Enable VPID */
2431                 "\007WBINVD"            /* WBINVD exiting */
2432                 "\010UG"                /* Unrestricted guest */
2433                 "\011APIC-reg"          /* APIC-register virtualization */
2434                 "\012VID"               /* Virtual-interrupt delivery */
2435                 "\013PAUSE-loop"        /* PAUSE-loop exiting */
2436                 "\014RDRAND"            /* RDRAND exiting */
2437                 "\015INVPCID"           /* Enable INVPCID */
2438                 "\016VMFUNC"            /* Enable VM functions */
2439                 "\017VMCS"              /* VMCS shadowing */
2440                 "\020EPT#VE"            /* EPT-violation #VE */
2441                 "\021XSAVES"            /* Enable XSAVES/XRSTORS */
2442                 );
2443         printf("\n        Exit Controls=0x%b", mask,
2444         "\020"
2445         "\003DR"                /* Save debug controls */
2446                                 /* Ignore Host address-space size */
2447         "\015PERF"              /* Load MSR_PERF_GLOBAL_CTRL */
2448         "\020AckInt"            /* Acknowledge interrupt on exit */
2449         "\023PAT-SV"            /* Save MSR_PAT */
2450         "\024PAT-LD"            /* Load MSR_PAT */
2451         "\025EFER-SV"           /* Save MSR_EFER */
2452         "\026EFER-LD"           /* Load MSR_EFER */
2453         "\027PTMR-SV"           /* Save VMX-preemption timer value */
2454         );
2455         printf("\n        Entry Controls=0x%b", mask,
2456         "\020"
2457         "\003DR"                /* Save debug controls */
2458                                 /* Ignore IA-32e mode guest */
2459                                 /* Ignore Entry to SMM */
2460                                 /* Ignore Deactivate dual-monitor treatment */
2461         "\016PERF"              /* Load MSR_PERF_GLOBAL_CTRL */
2462         "\017PAT"               /* Load MSR_PAT */
2463         "\020EFER"              /* Load MSR_EFER */
2464         );
2465         if (proc & PROCBASED_SECONDARY_CONTROLS &&
2466             (proc2 & (PROCBASED2_ENABLE_EPT | PROCBASED2_ENABLE_VPID)) != 0) {
2467                 msr = rdmsr(MSR_VMX_EPT_VPID_CAP);
2468                 mask = msr;
2469                 printf("\n        EPT Features=0x%b", mask,
2470                 "\020"
2471                 "\001XO"                /* Execute-only translations */
2472                 "\007PW4"               /* Page-walk length of 4 */
2473                 "\011UC"                /* EPT paging-structure mem can be UC */
2474                 "\017WB"                /* EPT paging-structure mem can be WB */
2475                 "\0212M"                /* EPT PDE can map a 2-Mbyte page */
2476                 "\0221G"                /* EPT PDPTE can map a 1-Gbyte page */
2477                 "\025INVEPT"            /* INVEPT is supported */
2478                 "\026AD"                /* Accessed and dirty flags for EPT */
2479                 "\032single"            /* INVEPT single-context type */
2480                 "\033all"               /* INVEPT all-context type */
2481                 );
2482                 mask = msr >> 32;
2483                 printf("\n        VPID Features=0x%b", mask,
2484                 "\020"
2485                 "\001INVVPID"           /* INVVPID is supported */
2486                 "\011individual"        /* INVVPID individual-address type */
2487                 "\012single"            /* INVVPID single-context type */
2488                 "\013all"               /* INVVPID all-context type */
2489                  /* INVVPID single-context-retaining-globals type */
2490                 "\014single-globals"
2491                 );
2492         }
2493 }
2494
2495 static void
2496 print_hypervisor_info(void)
2497 {
2498
2499         if (*hv_vendor)
2500                 printf("Hypervisor: Origin = \"%s\"\n", hv_vendor);
2501 }