sys/x86/x86/identcpu.c

   1 /*-
   2  * Copyright (c) 1992 Terrence R. Lambert.
   3  * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
   4  * Copyright (c) 1997 KATO Takenori.
   5  * All rights reserved.
   6  *
   7  * This code is derived from software contributed to Berkeley by
   8  * William Jolitz.
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  * 3. All advertising materials mentioning features or use of this software
  19  *    must display the following acknowledgement:
  20  *      This product includes software developed by the University of
  21  *      California, Berkeley and its contributors.
  22  * 4. Neither the name of the University nor the names of its contributors
  23  *    may be used to endorse or promote products derived from this software
  24  *    without specific prior written permission.
  25  *
  26  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  27  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  28  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  29  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  30  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  31  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  32  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  33  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  34  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  35  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  36  * SUCH DAMAGE.
  37  *
  38  *      from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp
  39  */
  40
  41 #include <sys/cdefs.h>
  42 __FBSDID("$FreeBSD$");
  43
  44 #include "opt_cpu.h"
  45
  46 #include <sys/param.h>
  47 #include <sys/bus.h>
  48 #include <sys/cpu.h>
  49 #include <sys/eventhandler.h>
  50 #include <sys/limits.h>
  51 #include <sys/systm.h>
  52 #include <sys/kernel.h>
  53 #include <sys/sysctl.h>
  54 #include <sys/power.h>
  55
  56 #include <vm/vm.h>
  57 #include <vm/pmap.h>
  58
  59 #include <machine/asmacros.h>
  60 #include <machine/clock.h>
  61 #include <machine/cputypes.h>
  62 #include <machine/frame.h>
  63 #include <machine/intr_machdep.h>
  64 #include <machine/md_var.h>
  65 #include <machine/segments.h>
  66 #include <machine/specialreg.h>
  67
  68 #include <amd64/vmm/intel/vmx_controls.h>
  69 #include <x86/isa/icu.h>
  70 #include <x86/vmware.h>
  71
  72 #ifdef __i386__
  73 #define IDENTBLUE_CYRIX486      0
  74 #define IDENTBLUE_IBMCPU        1
  75 #define IDENTBLUE_CYRIXM2       2
  76
  77 static void identifycyrix(void);
  78 static void print_transmeta_info(void);
  79 #endif
  80 static u_int find_cpu_vendor_id(void);
  81 static void print_AMD_info(void);
  82 static void print_INTEL_info(void);
  83 static void print_INTEL_TLB(u_int data);
  84 static void print_hypervisor_info(void);
  85 static void print_svm_info(void);
  86 static void print_via_padlock_info(void);
  87 static void print_vmx_info(void);
  88
  89 #ifdef __i386__
  90 int     cpu;                    /* Are we 386, 386sx, 486, etc? */
  91 int     cpu_class;
  92 #endif
  93 u_int   cpu_feature;            /* Feature flags */
  94 u_int   cpu_feature2;           /* Feature flags */
  95 u_int   amd_feature;            /* AMD feature flags */
  96 u_int   amd_feature2;           /* AMD feature flags */
  97 u_int   amd_rascap;             /* AMD RAS capabilities */
  98 u_int   amd_pminfo;             /* AMD advanced power management info */
  99 u_int   amd_extended_feature_extensions;
 100 u_int   via_feature_rng;        /* VIA RNG features */
 101 u_int   via_feature_xcrypt;     /* VIA ACE features */
 102 u_int   cpu_high;               /* Highest arg to CPUID */
 103 u_int   cpu_exthigh;            /* Highest arg to extended CPUID */
 104 u_int   cpu_id;                 /* Stepping ID */
 105 u_int   cpu_procinfo;           /* HyperThreading Info / Brand Index / CLFUSH */
 106 u_int   cpu_procinfo2;          /* Multicore info */
 107 char    cpu_vendor[20];         /* CPU Origin code */
 108 u_int   cpu_vendor_id;          /* CPU vendor ID */
 109 u_int   cpu_fxsr;               /* SSE enabled */
 110 u_int   cpu_mxcsr_mask;         /* Valid bits in mxcsr */
 111 u_int   cpu_clflush_line_size = 32;
 112 u_int   cpu_stdext_feature;     /* %ebx */
 113 u_int   cpu_stdext_feature2;    /* %ecx */
 114 u_int   cpu_stdext_feature3;    /* %edx */
 115 uint64_t cpu_ia32_arch_caps;
 116 u_int   cpu_max_ext_state_size;
 117 u_int   cpu_mon_mwait_flags;    /* MONITOR/MWAIT flags (CPUID.05H.ECX) */
 118 u_int   cpu_mon_min_size;       /* MONITOR minimum range size, bytes */
 119 u_int   cpu_mon_max_size;       /* MONITOR minimum range size, bytes */
 120 u_int   cpu_maxphyaddr;         /* Max phys addr width in bits */
 121 char machine[] = MACHINE;
 122
 123 SYSCTL_UINT(_hw, OID_AUTO, via_feature_rng, CTLFLAG_RD,
 124     &via_feature_rng, 0,
 125     "VIA RNG feature available in CPU");
 126 SYSCTL_UINT(_hw, OID_AUTO, via_feature_xcrypt, CTLFLAG_RD,
 127     &via_feature_xcrypt, 0,
 128     "VIA xcrypt feature available in CPU");
 129
 130 #ifdef __amd64__
 131 #ifdef SCTL_MASK32
 132 extern int adaptive_machine_arch;
 133 #endif
 134
 135 static int
 136 sysctl_hw_machine(SYSCTL_HANDLER_ARGS)
 137 {
 138 #ifdef SCTL_MASK32
 139         static const char machine32[] = "i386";
 140 #endif
 141         int error;
 142
 143 #ifdef SCTL_MASK32
 144         if ((req->flags & SCTL_MASK32) != 0 && adaptive_machine_arch)
 145                 error = SYSCTL_OUT(req, machine32, sizeof(machine32));
 146         else
 147 #endif
 148                 error = SYSCTL_OUT(req, machine, sizeof(machine));
 149         return (error);
 150
 151 }
 152 SYSCTL_PROC(_hw, HW_MACHINE, machine, CTLTYPE_STRING | CTLFLAG_RD |
 153     CTLFLAG_MPSAFE, NULL, 0, sysctl_hw_machine, "A", "Machine class");
 154 #else
 155 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD,
 156     machine, 0, "Machine class");
 157 #endif
 158
 159 static char cpu_model[128];
 160 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD | CTLFLAG_MPSAFE,
 161     cpu_model, 0, "Machine model");
 162
 163 static int hw_clockrate;
 164 SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD,
 165     &hw_clockrate, 0, "CPU instruction clock rate");
 166
 167 u_int hv_high;
 168 char hv_vendor[16];
 169 SYSCTL_STRING(_hw, OID_AUTO, hv_vendor, CTLFLAG_RD | CTLFLAG_MPSAFE, hv_vendor,
 170     0, "Hypervisor vendor");
 171
 172 static eventhandler_tag tsc_post_tag;
 173
 174 static char cpu_brand[48];
 175
 176 #ifdef __i386__
 177 #define MAX_BRAND_INDEX 8
 178
 179 static const char *cpu_brandtable[MAX_BRAND_INDEX + 1] = {
 180         NULL,                   /* No brand */
 181         "Intel Celeron",
 182         "Intel Pentium III",
 183         "Intel Pentium III Xeon",
 184         NULL,
 185         NULL,
 186         NULL,
 187         NULL,
 188         "Intel Pentium 4"
 189 };
 190
 191 static struct {
 192         char    *cpu_name;
 193         int     cpu_class;
 194 } cpus[] = {
 195         { "Intel 80286",        CPUCLASS_286 },         /* CPU_286   */
 196         { "i386SX",             CPUCLASS_386 },         /* CPU_386SX */
 197         { "i386DX",             CPUCLASS_386 },         /* CPU_386   */
 198         { "i486SX",             CPUCLASS_486 },         /* CPU_486SX */
 199         { "i486DX",             CPUCLASS_486 },         /* CPU_486   */
 200         { "Pentium",            CPUCLASS_586 },         /* CPU_586   */
 201         { "Cyrix 486",          CPUCLASS_486 },         /* CPU_486DLC */
 202         { "Pentium Pro",        CPUCLASS_686 },         /* CPU_686 */
 203         { "Cyrix 5x86",         CPUCLASS_486 },         /* CPU_M1SC */
 204         { "Cyrix 6x86",         CPUCLASS_486 },         /* CPU_M1 */
 205         { "Blue Lightning",     CPUCLASS_486 },         /* CPU_BLUE */
 206         { "Cyrix 6x86MX",       CPUCLASS_686 },         /* CPU_M2 */
 207         { "NexGen 586",         CPUCLASS_386 },         /* CPU_NX586 (XXX) */
 208         { "Cyrix 486S/DX",      CPUCLASS_486 },         /* CPU_CY486DX */
 209         { "Pentium II",         CPUCLASS_686 },         /* CPU_PII */
 210         { "Pentium III",        CPUCLASS_686 },         /* CPU_PIII */
 211         { "Pentium 4",          CPUCLASS_686 },         /* CPU_P4 */
 212 };
 213 #endif
 214
 215 static struct {
 216         char    *vendor;
 217         u_int   vendor_id;
 218 } cpu_vendors[] = {
 219         { INTEL_VENDOR_ID,      CPU_VENDOR_INTEL },     /* GenuineIntel */
 220         { AMD_VENDOR_ID,        CPU_VENDOR_AMD },       /* AuthenticAMD */
 221         { CENTAUR_VENDOR_ID,    CPU_VENDOR_CENTAUR },   /* CentaurHauls */
 222 #ifdef __i386__
 223         { NSC_VENDOR_ID,        CPU_VENDOR_NSC },       /* Geode by NSC */
 224         { CYRIX_VENDOR_ID,      CPU_VENDOR_CYRIX },     /* CyrixInstead */
 225         { TRANSMETA_VENDOR_ID,  CPU_VENDOR_TRANSMETA }, /* GenuineTMx86 */
 226         { SIS_VENDOR_ID,        CPU_VENDOR_SIS },       /* SiS SiS SiS  */
 227         { UMC_VENDOR_ID,        CPU_VENDOR_UMC },       /* UMC UMC UMC  */
 228         { NEXGEN_VENDOR_ID,     CPU_VENDOR_NEXGEN },    /* NexGenDriven */
 229         { RISE_VENDOR_ID,       CPU_VENDOR_RISE },      /* RiseRiseRise */
 230 #if 0
 231         /* XXX CPUID 8000_0000h and 8086_0000h, not 0000_0000h */
 232         { "TransmetaCPU",       CPU_VENDOR_TRANSMETA },
 233 #endif
 234 #endif
 235 };
 236
 237 void
 238 printcpuinfo(void)
 239 {
 240         u_int regs[4], i;
 241         char *brand;
 242
 243         printf("CPU: ");
 244 #ifdef __i386__
 245         cpu_class = cpus[cpu].cpu_class;
 246         strncpy(cpu_model, cpus[cpu].cpu_name, sizeof (cpu_model));
 247 #else
 248         strncpy(cpu_model, "Hammer", sizeof (cpu_model));
 249 #endif
 250
 251         /* Check for extended CPUID information and a processor name. */
 252         if (cpu_exthigh >= 0x80000004) {
 253                 brand = cpu_brand;
 254                 for (i = 0x80000002; i < 0x80000005; i++) {
 255                         do_cpuid(i, regs);
 256                         memcpy(brand, regs, sizeof(regs));
 257                         brand += sizeof(regs);
 258                 }
 259         }
 260
 261         switch (cpu_vendor_id) {
 262         case CPU_VENDOR_INTEL:
 263 #ifdef __i386__
 264                 if ((cpu_id & 0xf00) > 0x300) {
 265                         u_int brand_index;
 266
 267                         cpu_model[0] = '\0';
 268
 269                         switch (cpu_id & 0x3000) {
 270                         case 0x1000:
 271                                 strcpy(cpu_model, "Overdrive ");
 272                                 break;
 273                         case 0x2000:
 274                                 strcpy(cpu_model, "Dual ");
 275                                 break;
 276                         }
 277
 278                         switch (cpu_id & 0xf00) {
 279                         case 0x400:
 280                                 strcat(cpu_model, "i486 ");
 281                                 /* Check the particular flavor of 486 */
 282                                 switch (cpu_id & 0xf0) {
 283                                 case 0x00:
 284                                 case 0x10:
 285                                         strcat(cpu_model, "DX");
 286                                         break;
 287                                 case 0x20:
 288                                         strcat(cpu_model, "SX");
 289                                         break;
 290                                 case 0x30:
 291                                         strcat(cpu_model, "DX2");
 292                                         break;
 293                                 case 0x40:
 294                                         strcat(cpu_model, "SL");
 295                                         break;
 296                                 case 0x50:
 297                                         strcat(cpu_model, "SX2");
 298                                         break;
 299                                 case 0x70:
 300                                         strcat(cpu_model,
 301                                             "DX2 Write-Back Enhanced");
 302                                         break;
 303                                 case 0x80:
 304                                         strcat(cpu_model, "DX4");
 305                                         break;
 306                                 }
 307                                 break;
 308                         case 0x500:
 309                                 /* Check the particular flavor of 586 */
 310                                 strcat(cpu_model, "Pentium");
 311                                 switch (cpu_id & 0xf0) {
 312                                 case 0x00:
 313                                         strcat(cpu_model, " A-step");
 314                                         break;
 315                                 case 0x10:
 316                                         strcat(cpu_model, "/P5");
 317                                         break;
 318                                 case 0x20:
 319                                         strcat(cpu_model, "/P54C");
 320                                         break;
 321                                 case 0x30:
 322                                         strcat(cpu_model, "/P24T");
 323                                         break;
 324                                 case 0x40:
 325                                         strcat(cpu_model, "/P55C");
 326                                         break;
 327                                 case 0x70:
 328                                         strcat(cpu_model, "/P54C");
 329                                         break;
 330                                 case 0x80:
 331                                         strcat(cpu_model, "/P55C (quarter-micron)");
 332                                         break;
 333                                 default:
 334                                         /* nothing */
 335                                         break;
 336                                 }
 337 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
 338                                 /*
 339                                  * XXX - If/when Intel fixes the bug, this
 340                                  * should also check the version of the
 341                                  * CPU, not just that it's a Pentium.
 342                                  */
 343                                 has_f00f_bug = 1;
 344 #endif
 345                                 break;
 346                         case 0x600:
 347                                 /* Check the particular flavor of 686 */
 348                                 switch (cpu_id & 0xf0) {
 349                                 case 0x00:
 350                                         strcat(cpu_model, "Pentium Pro A-step");
 351                                         break;
 352                                 case 0x10:
 353                                         strcat(cpu_model, "Pentium Pro");
 354                                         break;
 355                                 case 0x30:
 356                                 case 0x50:
 357                                 case 0x60:
 358                                         strcat(cpu_model,
 359                                 "Pentium II/Pentium II Xeon/Celeron");
 360                                         cpu = CPU_PII;
 361                                         break;
 362                                 case 0x70:
 363                                 case 0x80:
 364                                 case 0xa0:
 365                                 case 0xb0:
 366                                         strcat(cpu_model,
 367                                         "Pentium III/Pentium III Xeon/Celeron");
 368                                         cpu = CPU_PIII;
 369                                         break;
 370                                 default:
 371                                         strcat(cpu_model, "Unknown 80686");
 372                                         break;
 373                                 }
 374                                 break;
 375                         case 0xf00:
 376                                 strcat(cpu_model, "Pentium 4");
 377                                 cpu = CPU_P4;
 378                                 break;
 379                         default:
 380                                 strcat(cpu_model, "unknown");
 381                                 break;
 382                         }
 383
 384                         /*
 385                          * If we didn't get a brand name from the extended
 386                          * CPUID, try to look it up in the brand table.
 387                          */
 388                         if (cpu_high > 0 && *cpu_brand == '\0') {
 389                                 brand_index = cpu_procinfo & CPUID_BRAND_INDEX;
 390                                 if (brand_index <= MAX_BRAND_INDEX &&
 391                                     cpu_brandtable[brand_index] != NULL)
 392                                         strcpy(cpu_brand,
 393                                             cpu_brandtable[brand_index]);
 394                         }
 395                 }
 396 #else
 397                 /* Please make up your mind folks! */
 398                 strcat(cpu_model, "EM64T");
 399 #endif
 400                 break;
 401         case CPU_VENDOR_AMD:
 402                 /*
 403                  * Values taken from AMD Processor Recognition
 404                  * http://www.amd.com/K6/k6docs/pdf/20734g.pdf
 405                  * (also describes ``Features'' encodings.
 406                  */
 407                 strcpy(cpu_model, "AMD ");
 408 #ifdef __i386__
 409                 switch (cpu_id & 0xFF0) {
 410                 case 0x410:
 411                         strcat(cpu_model, "Standard Am486DX");
 412                         break;
 413                 case 0x430:
 414                         strcat(cpu_model, "Enhanced Am486DX2 Write-Through");
 415                         break;
 416                 case 0x470:
 417                         strcat(cpu_model, "Enhanced Am486DX2 Write-Back");
 418                         break;
 419                 case 0x480:
 420                         strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Through");
 421                         break;
 422                 case 0x490:
 423                         strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Back");
 424                         break;
 425                 case 0x4E0:
 426                         strcat(cpu_model, "Am5x86 Write-Through");
 427                         break;
 428                 case 0x4F0:
 429                         strcat(cpu_model, "Am5x86 Write-Back");
 430                         break;
 431                 case 0x500:
 432                         strcat(cpu_model, "K5 model 0");
 433                         break;
 434                 case 0x510:
 435                         strcat(cpu_model, "K5 model 1");
 436                         break;
 437                 case 0x520:
 438                         strcat(cpu_model, "K5 PR166 (model 2)");
 439                         break;
 440                 case 0x530:
 441                         strcat(cpu_model, "K5 PR200 (model 3)");
 442                         break;
 443                 case 0x560:
 444                         strcat(cpu_model, "K6");
 445                         break;
 446                 case 0x570:
 447                         strcat(cpu_model, "K6 266 (model 1)");
 448                         break;
 449                 case 0x580:
 450                         strcat(cpu_model, "K6-2");
 451                         break;
 452                 case 0x590:
 453                         strcat(cpu_model, "K6-III");
 454                         break;
 455                 case 0x5a0:
 456                         strcat(cpu_model, "Geode LX");
 457                         break;
 458                 default:
 459                         strcat(cpu_model, "Unknown");
 460                         break;
 461                 }
 462 #else
 463                 if ((cpu_id & 0xf00) == 0xf00)
 464                         strcat(cpu_model, "AMD64 Processor");
 465                 else
 466                         strcat(cpu_model, "Unknown");
 467 #endif
 468                 break;
 469 #ifdef __i386__
 470         case CPU_VENDOR_CYRIX:
 471                 strcpy(cpu_model, "Cyrix ");
 472                 switch (cpu_id & 0xff0) {
 473                 case 0x440:
 474                         strcat(cpu_model, "MediaGX");
 475                         break;
 476                 case 0x520:
 477                         strcat(cpu_model, "6x86");
 478                         break;
 479                 case 0x540:
 480                         cpu_class = CPUCLASS_586;
 481                         strcat(cpu_model, "GXm");
 482                         break;
 483                 case 0x600:
 484                         strcat(cpu_model, "6x86MX");
 485                         break;
 486                 default:
 487                         /*
 488                          * Even though CPU supports the cpuid
 489                          * instruction, it can be disabled.
 490                          * Therefore, this routine supports all Cyrix
 491                          * CPUs.
 492                          */
 493                         switch (cyrix_did & 0xf0) {
 494                         case 0x00:
 495                                 switch (cyrix_did & 0x0f) {
 496                                 case 0x00:
 497                                         strcat(cpu_model, "486SLC");
 498                                         break;
 499                                 case 0x01:
 500                                         strcat(cpu_model, "486DLC");
 501                                         break;
 502                                 case 0x02:
 503                                         strcat(cpu_model, "486SLC2");
 504                                         break;
 505                                 case 0x03:
 506                                         strcat(cpu_model, "486DLC2");
 507                                         break;
 508                                 case 0x04:
 509                                         strcat(cpu_model, "486SRx");
 510                                         break;
 511                                 case 0x05:
 512                                         strcat(cpu_model, "486DRx");
 513                                         break;
 514                                 case 0x06:
 515                                         strcat(cpu_model, "486SRx2");
 516                                         break;
 517                                 case 0x07:
 518                                         strcat(cpu_model, "486DRx2");
 519                                         break;
 520                                 case 0x08:
 521                                         strcat(cpu_model, "486SRu");
 522                                         break;
 523                                 case 0x09:
 524                                         strcat(cpu_model, "486DRu");
 525                                         break;
 526                                 case 0x0a:
 527                                         strcat(cpu_model, "486SRu2");
 528                                         break;
 529                                 case 0x0b:
 530                                         strcat(cpu_model, "486DRu2");
 531                                         break;
 532                                 default:
 533                                         strcat(cpu_model, "Unknown");
 534                                         break;
 535                                 }
 536                                 break;
 537                         case 0x10:
 538                                 switch (cyrix_did & 0x0f) {
 539                                 case 0x00:
 540                                         strcat(cpu_model, "486S");
 541                                         break;
 542                                 case 0x01:
 543                                         strcat(cpu_model, "486S2");
 544                                         break;
 545                                 case 0x02:
 546                                         strcat(cpu_model, "486Se");
 547                                         break;
 548                                 case 0x03:
 549                                         strcat(cpu_model, "486S2e");
 550                                         break;
 551                                 case 0x0a:
 552                                         strcat(cpu_model, "486DX");
 553                                         break;
 554                                 case 0x0b:
 555                                         strcat(cpu_model, "486DX2");
 556                                         break;
 557                                 case 0x0f:
 558                                         strcat(cpu_model, "486DX4");
 559                                         break;
 560                                 default:
 561                                         strcat(cpu_model, "Unknown");
 562                                         break;
 563                                 }
 564                                 break;
 565                         case 0x20:
 566                                 if ((cyrix_did & 0x0f) < 8)
 567                                         strcat(cpu_model, "6x86");      /* Where did you get it? */
 568                                 else
 569                                         strcat(cpu_model, "5x86");
 570                                 break;
 571                         case 0x30:
 572                                 strcat(cpu_model, "6x86");
 573                                 break;
 574                         case 0x40:
 575                                 if ((cyrix_did & 0xf000) == 0x3000) {
 576                                         cpu_class = CPUCLASS_586;
 577                                         strcat(cpu_model, "GXm");
 578                                 } else
 579                                         strcat(cpu_model, "MediaGX");
 580                                 break;
 581                         case 0x50:
 582                                 strcat(cpu_model, "6x86MX");
 583                                 break;
 584                         case 0xf0:
 585                                 switch (cyrix_did & 0x0f) {
 586                                 case 0x0d:
 587                                         strcat(cpu_model, "Overdrive CPU");
 588                                         break;
 589                                 case 0x0e:
 590                                         strcpy(cpu_model, "Texas Instruments 486SXL");
 591                                         break;
 592                                 case 0x0f:
 593                                         strcat(cpu_model, "486SLC/DLC");
 594                                         break;
 595                                 default:
 596                                         strcat(cpu_model, "Unknown");
 597                                         break;
 598                                 }
 599                                 break;
 600                         default:
 601                                 strcat(cpu_model, "Unknown");
 602                                 break;
 603                         }
 604                         break;
 605                 }
 606                 break;
 607         case CPU_VENDOR_RISE:
 608                 strcpy(cpu_model, "Rise ");
 609                 switch (cpu_id & 0xff0) {
 610                 case 0x500:     /* 6401 and 6441 (Kirin) */
 611                 case 0x520:     /* 6510 (Lynx) */
 612                         strcat(cpu_model, "mP6");
 613                         break;
 614                 default:
 615                         strcat(cpu_model, "Unknown");
 616                 }
 617                 break;
 618 #endif
 619         case CPU_VENDOR_CENTAUR:
 620 #ifdef __i386__
 621                 switch (cpu_id & 0xff0) {
 622                 case 0x540:
 623                         strcpy(cpu_model, "IDT WinChip C6");
 624                         break;
 625                 case 0x580:
 626                         strcpy(cpu_model, "IDT WinChip 2");
 627                         break;
 628                 case 0x590:
 629                         strcpy(cpu_model, "IDT WinChip 3");
 630                         break;
 631                 case 0x660:
 632                         strcpy(cpu_model, "VIA C3 Samuel");
 633                         break;
 634                 case 0x670:
 635                         if (cpu_id & 0x8)
 636                                 strcpy(cpu_model, "VIA C3 Ezra");
 637                         else
 638                                 strcpy(cpu_model, "VIA C3 Samuel 2");
 639                         break;
 640                 case 0x680:
 641                         strcpy(cpu_model, "VIA C3 Ezra-T");
 642                         break;
 643                 case 0x690:
 644                         strcpy(cpu_model, "VIA C3 Nehemiah");
 645                         break;
 646                 case 0x6a0:
 647                 case 0x6d0:
 648                         strcpy(cpu_model, "VIA C7 Esther");
 649                         break;
 650                 case 0x6f0:
 651                         strcpy(cpu_model, "VIA Nano");
 652                         break;
 653                 default:
 654                         strcpy(cpu_model, "VIA/IDT Unknown");
 655                 }
 656 #else
 657                 strcpy(cpu_model, "VIA ");
 658                 if ((cpu_id & 0xff0) == 0x6f0)
 659                         strcat(cpu_model, "Nano Processor");
 660                 else
 661                         strcat(cpu_model, "Unknown");
 662 #endif
 663                 break;
 664 #ifdef __i386__
 665         case CPU_VENDOR_IBM:
 666                 strcpy(cpu_model, "Blue Lightning CPU");
 667                 break;
 668         case CPU_VENDOR_NSC:
 669                 switch (cpu_id & 0xff0) {
 670                 case 0x540:
 671                         strcpy(cpu_model, "Geode SC1100");
 672                         cpu = CPU_GEODE1100;
 673                         break;
 674                 default:
 675                         strcpy(cpu_model, "Geode/NSC unknown");
 676                         break;
 677                 }
 678                 break;
 679 #endif
 680         default:
 681                 strcat(cpu_model, "Unknown");
 682                 break;
 683         }
 684
 685         /*
 686          * Replace cpu_model with cpu_brand minus leading spaces if
 687          * we have one.
 688          */
 689         brand = cpu_brand;
 690         while (*brand == ' ')
 691                 ++brand;
 692         if (*brand != '\0')
 693                 strcpy(cpu_model, brand);
 694
 695         printf("%s (", cpu_model);
 696         if (tsc_freq != 0) {
 697                 hw_clockrate = (tsc_freq + 5000) / 1000000;
 698                 printf("%jd.%02d-MHz ",
 699                     (intmax_t)(tsc_freq + 4999) / 1000000,
 700                     (u_int)((tsc_freq + 4999) / 10000) % 100);
 701         }
 702 #ifdef __i386__
 703         switch(cpu_class) {
 704         case CPUCLASS_286:
 705                 printf("286");
 706                 break;
 707         case CPUCLASS_386:
 708                 printf("386");
 709                 break;
 710 #if defined(I486_CPU)
 711         case CPUCLASS_486:
 712                 printf("486");
 713                 break;
 714 #endif
 715 #if defined(I586_CPU)
 716         case CPUCLASS_586:
 717                 printf("586");
 718                 break;
 719 #endif
 720 #if defined(I686_CPU)
 721         case CPUCLASS_686:
 722                 printf("686");
 723                 break;
 724 #endif
 725         default:
 726                 printf("Unknown");      /* will panic below... */
 727         }
 728 #else
 729         printf("K8");
 730 #endif
 731         printf("-class CPU)\n");
 732         if (*cpu_vendor)
 733                 printf("  Origin=\"%s\"", cpu_vendor);
 734         if (cpu_id)
 735                 printf("  Id=0x%x", cpu_id);
 736
 737         if (cpu_vendor_id == CPU_VENDOR_INTEL ||
 738             cpu_vendor_id == CPU_VENDOR_AMD ||
 739             cpu_vendor_id == CPU_VENDOR_CENTAUR ||
 740 #ifdef __i386__
 741             cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
 742             cpu_vendor_id == CPU_VENDOR_RISE ||
 743             cpu_vendor_id == CPU_VENDOR_NSC ||
 744             (cpu_vendor_id == CPU_VENDOR_CYRIX && ((cpu_id & 0xf00) > 0x500)) ||
 745 #endif
 746             0) {
 747                 printf("  Family=0x%x", CPUID_TO_FAMILY(cpu_id));
 748                 printf("  Model=0x%x", CPUID_TO_MODEL(cpu_id));
 749                 printf("  Stepping=%u", cpu_id & CPUID_STEPPING);
 750 #ifdef __i386__
 751                 if (cpu_vendor_id == CPU_VENDOR_CYRIX)
 752                         printf("\n  DIR=0x%04x", cyrix_did);
 753 #endif
 754
 755                 /*
 756                  * AMD CPUID Specification
 757                  * http://support.amd.com/us/Embedded_TechDocs/25481.pdf
 758                  *
 759                  * Intel Processor Identification and CPUID Instruction
 760                  * http://www.intel.com/assets/pdf/appnote/241618.pdf
 761                  */
 762                 if (cpu_high > 0) {
 763
 764                         /*
 765                          * Here we should probably set up flags indicating
 766                          * whether or not various features are available.
 767                          * The interesting ones are probably VME, PSE, PAE,
 768                          * and PGE.  The code already assumes without bothering
 769                          * to check that all CPUs >= Pentium have a TSC and
 770                          * MSRs.
 771                          */
 772                         printf("\n  Features=0x%b", cpu_feature,
 773                         "\020"
 774                         "\001FPU"       /* Integral FPU */
 775                         "\002VME"       /* Extended VM86 mode support */
 776                         "\003DE"        /* Debugging Extensions (CR4.DE) */
 777                         "\004PSE"       /* 4MByte page tables */
 778                         "\005TSC"       /* Timestamp counter */
 779                         "\006MSR"       /* Machine specific registers */
 780                         "\007PAE"       /* Physical address extension */
 781                         "\010MCE"       /* Machine Check support */
 782                         "\011CX8"       /* CMPEXCH8 instruction */
 783                         "\012APIC"      /* SMP local APIC */
 784                         "\013oldMTRR"   /* Previous implementation of MTRR */
 785                         "\014SEP"       /* Fast System Call */
 786                         "\015MTRR"      /* Memory Type Range Registers */
 787                         "\016PGE"       /* PG_G (global bit) support */
 788                         "\017MCA"       /* Machine Check Architecture */
 789                         "\020CMOV"      /* CMOV instruction */
 790                         "\021PAT"       /* Page attributes table */
 791                         "\022PSE36"     /* 36 bit address space support */
 792                         "\023PN"        /* Processor Serial number */
 793                         "\024CLFLUSH"   /* Has the CLFLUSH instruction */
 794                         "\025<b20>"
 795                         "\026DTS"       /* Debug Trace Store */
 796                         "\027ACPI"      /* ACPI support */
 797                         "\030MMX"       /* MMX instructions */
 798                         "\031FXSR"      /* FXSAVE/FXRSTOR */
 799                         "\032SSE"       /* Streaming SIMD Extensions */
 800                         "\033SSE2"      /* Streaming SIMD Extensions #2 */
 801                         "\034SS"        /* Self snoop */
 802                         "\035HTT"       /* Hyperthreading (see EBX bit 16-23) */
 803                         "\036TM"        /* Thermal Monitor clock slowdown */
 804                         "\037IA64"      /* CPU can execute IA64 instructions */
 805                         "\040PBE"       /* Pending Break Enable */
 806                         );
 807
 808                         if (cpu_feature2 != 0) {
 809                                 printf("\n  Features2=0x%b", cpu_feature2,
 810                                 "\020"
 811                                 "\001SSE3"      /* SSE3 */
 812                                 "\002PCLMULQDQ" /* Carry-Less Mul Quadword */
 813                                 "\003DTES64"    /* 64-bit Debug Trace */
 814                                 "\004MON"       /* MONITOR/MWAIT Instructions */
 815                                 "\005DS_CPL"    /* CPL Qualified Debug Store */
 816                                 "\006VMX"       /* Virtual Machine Extensions */
 817                                 "\007SMX"       /* Safer Mode Extensions */
 818                                 "\010EST"       /* Enhanced SpeedStep */
 819                                 "\011TM2"       /* Thermal Monitor 2 */
 820                                 "\012SSSE3"     /* SSSE3 */
 821                                 "\013CNXT-ID"   /* L1 context ID available */
 822                                 "\014SDBG"      /* IA32 silicon debug */
 823                                 "\015FMA"       /* Fused Multiply Add */
 824                                 "\016CX16"      /* CMPXCHG16B Instruction */
 825                                 "\017xTPR"      /* Send Task Priority Messages*/
 826                                 "\020PDCM"      /* Perf/Debug Capability MSR */
 827                                 "\021<b16>"
 828                                 "\022PCID"      /* Process-context Identifiers*/
 829                                 "\023DCA"       /* Direct Cache Access */
 830                                 "\024SSE4.1"    /* SSE 4.1 */
 831                                 "\025SSE4.2"    /* SSE 4.2 */
 832                                 "\026x2APIC"    /* xAPIC Extensions */
 833                                 "\027MOVBE"     /* MOVBE Instruction */
 834                                 "\030POPCNT"    /* POPCNT Instruction */
 835                                 "\031TSCDLT"    /* TSC-Deadline Timer */
 836                                 "\032AESNI"     /* AES Crypto */
 837                                 "\033XSAVE"     /* XSAVE/XRSTOR States */
 838                                 "\034OSXSAVE"   /* OS-Enabled State Management*/
 839                                 "\035AVX"       /* Advanced Vector Extensions */
 840                                 "\036F16C"      /* Half-precision conversions */
 841                                 "\037RDRAND"    /* RDRAND Instruction */
 842                                 "\040HV"        /* Hypervisor */
 843                                 );
 844                         }
 845
 846                         if (amd_feature != 0) {
 847                                 printf("\n  AMD Features=0x%b", amd_feature,
 848                                 "\020"          /* in hex */
 849                                 "\001<s0>"      /* Same */
 850                                 "\002<s1>"      /* Same */
 851                                 "\003<s2>"      /* Same */
 852                                 "\004<s3>"      /* Same */
 853                                 "\005<s4>"      /* Same */
 854                                 "\006<s5>"      /* Same */
 855                                 "\007<s6>"      /* Same */
 856                                 "\010<s7>"      /* Same */
 857                                 "\011<s8>"      /* Same */
 858                                 "\012<s9>"      /* Same */
 859                                 "\013<b10>"     /* Undefined */
 860                                 "\014SYSCALL"   /* Have SYSCALL/SYSRET */
 861                                 "\015<s12>"     /* Same */
 862                                 "\016<s13>"     /* Same */
 863                                 "\017<s14>"     /* Same */
 864                                 "\020<s15>"     /* Same */
 865                                 "\021<s16>"     /* Same */
 866                                 "\022<s17>"     /* Same */
 867                                 "\023<b18>"     /* Reserved, unknown */
 868                                 "\024MP"        /* Multiprocessor Capable */
 869                                 "\025NX"        /* Has EFER.NXE, NX */
 870                                 "\026<b21>"     /* Undefined */
 871                                 "\027MMX+"      /* AMD MMX Extensions */
 872                                 "\030<s23>"     /* Same */
 873                                 "\031<s24>"     /* Same */
 874                                 "\032FFXSR"     /* Fast FXSAVE/FXRSTOR */
 875                                 "\033Page1GB"   /* 1-GB large page support */
 876                                 "\034RDTSCP"    /* RDTSCP */
 877                                 "\035<b28>"     /* Undefined */
 878                                 "\036LM"        /* 64 bit long mode */
 879                                 "\0373DNow!+"   /* AMD 3DNow! Extensions */
 880                                 "\0403DNow!"    /* AMD 3DNow! */
 881                                 );
 882                         }
 883
 884                         if (amd_feature2 != 0) {
 885                                 printf("\n  AMD Features2=0x%b", amd_feature2,
 886                                 "\020"
 887                                 "\001LAHF"      /* LAHF/SAHF in long mode */
 888                                 "\002CMP"       /* CMP legacy */
 889                                 "\003SVM"       /* Secure Virtual Mode */
 890                                 "\004ExtAPIC"   /* Extended APIC register */
 891                                 "\005CR8"       /* CR8 in legacy mode */
 892                                 "\006ABM"       /* LZCNT instruction */
 893                                 "\007SSE4A"     /* SSE4A */
 894                                 "\010MAS"       /* Misaligned SSE mode */
 895                                 "\011Prefetch"  /* 3DNow! Prefetch/PrefetchW */
 896                                 "\012OSVW"      /* OS visible workaround */
 897                                 "\013IBS"       /* Instruction based sampling */
 898                                 "\014XOP"       /* XOP extended instructions */
 899                                 "\015SKINIT"    /* SKINIT/STGI */
 900                                 "\016WDT"       /* Watchdog timer */
 901                                 "\017<b14>"
 902                                 "\020LWP"       /* Lightweight Profiling */
 903                                 "\021FMA4"      /* 4-operand FMA instructions */
 904                                 "\022TCE"       /* Translation Cache Extension */
 905                                 "\023<b18>"
 906                                 "\024NodeId"    /* NodeId MSR support */
 907                                 "\025<b20>"
 908                                 "\026TBM"       /* Trailing Bit Manipulation */
 909                                 "\027Topology"  /* Topology Extensions */
 910                                 "\030PCXC"      /* Core perf count */
 911                                 "\031PNXC"      /* NB perf count */
 912                                 "\032<b25>"
 913                                 "\033DBE"       /* Data Breakpoint extension */
 914                                 "\034PTSC"      /* Performance TSC */
 915                                 "\035PL2I"      /* L2I perf count */
 916                                 "\036MWAITX"    /* MONITORX/MWAITX instructions */
 917                                 "\037<b30>"
 918                                 "\040<b31>"
 919                                 );
 920                         }
 921
 922                         if (cpu_stdext_feature != 0) {
 923                                 printf("\n  Structured Extended Features=0x%b",
 924                                     cpu_stdext_feature,
 925                                        "\020"
 926                                        /* RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */
 927                                        "\001FSGSBASE"
 928                                        "\002TSCADJ"
 929                                        "\003SGX"
 930                                        /* Bit Manipulation Instructions */
 931                                        "\004BMI1"
 932                                        /* Hardware Lock Elision */
 933                                        "\005HLE"
 934                                        /* Advanced Vector Instructions 2 */
 935                                        "\006AVX2"
 936                                        /* FDP_EXCPTN_ONLY */
 937                                        "\007FDPEXC"
 938                                        /* Supervisor Mode Execution Prot. */
 939                                        "\010SMEP"
 940                                        /* Bit Manipulation Instructions */
 941                                        "\011BMI2"
 942                                        "\012ERMS"
 943                                        /* Invalidate Processor Context ID */
 944                                        "\013INVPCID"
 945                                        /* Restricted Transactional Memory */
 946                                        "\014RTM"
 947                                        "\015PQM"
 948                                        "\016NFPUSG"
 949                                        /* Intel Memory Protection Extensions */
 950                                        "\017MPX"
 951                                        "\020PQE"
 952                                        /* AVX512 Foundation */
 953                                        "\021AVX512F"
 954                                        "\022AVX512DQ"
 955                                        /* Enhanced NRBG */
 956                                        "\023RDSEED"
 957                                        /* ADCX + ADOX */
 958                                        "\024ADX"
 959                                        /* Supervisor Mode Access Prevention */
 960                                        "\025SMAP"
 961                                        "\026AVX512IFMA"
 962                                        "\027PCOMMIT"
 963                                        "\030CLFLUSHOPT"
 964                                        "\031CLWB"
 965                                        "\032PROCTRACE"
 966                                        "\033AVX512PF"
 967                                        "\034AVX512ER"
 968                                        "\035AVX512CD"
 969                                        "\036SHA"
 970                                        "\037AVX512BW"
 971                                        "\040AVX512VL"
 972                                        );
 973                         }
 974
 975                         if (cpu_stdext_feature2 != 0) {
 976                                 printf("\n  Structured Extended Features2=0x%b",
 977                                     cpu_stdext_feature2,
 978                                        "\020"
 979                                        "\001PREFETCHWT1"
 980                                        "\002AVX512VBMI"
 981                                        "\003UMIP"
 982                                        "\004PKU"
 983                                        "\005OSPKE"
 984                                        "\006WAITPKG"
 985                                        "\011GFNI"
 986                                        "\027RDPID"
 987                                        "\032CLDEMOTE"
 988                                        "\034MOVDIRI"
 989                                        "\035MOVDIRI64B"
 990                                        "\037SGXLC"
 991                                        );
 992                         }
 993
 994                         if (cpu_stdext_feature3 != 0) {
 995                                 printf("\n  Structured Extended Features3=0x%b",
 996                                     cpu_stdext_feature3,
 997                                        "\020"
 998                                        "\013MD_CLEAR"
 999                                        "\016TSXFA"
1000                                        "\033IBPB"
1001                                        "\034STIBP"
1002                                        "\035L1DFL"
1003                                        "\036ARCH_CAP"
1004                                        "\037CORE_CAP"
1005                                        "\040SSBD"
1006                                        );
1007                         }
1008
1009                         if ((cpu_feature2 & CPUID2_XSAVE) != 0) {
1010                                 cpuid_count(0xd, 0x1, regs);
1011                                 if (regs[0] != 0) {
1012                                         printf("\n  XSAVE Features=0x%b",
1013                                             regs[0],
1014                                             "\020"
1015                                             "\001XSAVEOPT"
1016                                             "\002XSAVEC"
1017                                             "\003XINUSE"
1018                                             "\004XSAVES");
1019                                 }
1020                         }
1021
1022                         if (cpu_ia32_arch_caps != 0) {
1023                                 printf("\n  IA32_ARCH_CAPS=0x%b",
1024                                     (u_int)cpu_ia32_arch_caps,
1025                                        "\020"
1026                                        "\001RDCL_NO"
1027                                        "\002IBRS_ALL"
1028                                        "\003RSBA"
1029                                        "\004SKIP_L1DFL_VME"
1030                                        "\005SSB_NO"
1031                                        );
1032                         }
1033
1034                         if (amd_extended_feature_extensions != 0) {
1035                                 u_int amd_fe_masked;
1036
1037                                 amd_fe_masked = amd_extended_feature_extensions;
1038                                 if ((amd_fe_masked & AMDFEID_IBRS) == 0)
1039                                         amd_fe_masked &=
1040                                             ~(AMDFEID_IBRS_ALWAYSON |
1041                                                 AMDFEID_PREFER_IBRS);
1042                                 if ((amd_fe_masked & AMDFEID_STIBP) == 0)
1043                                         amd_fe_masked &=
1044                                             ~AMDFEID_STIBP_ALWAYSON;
1045
1046                                 printf("\n  "
1047                                     "AMD Extended Feature Extensions ID EBX="
1048                                     "0x%b", amd_fe_masked,
1049                                     "\020"
1050                                     "\001CLZERO"
1051                                     "\002IRPerf"
1052                                     "\003XSaveErPtr"
1053                                     "\015IBPB"
1054                                     "\017IBRS"
1055                                     "\020STIBP"
1056                                     "\021IBRS_ALWAYSON"
1057                                     "\022STIBP_ALWAYSON"
1058                                     "\023PREFER_IBRS"
1059                                     "\031SSBD"
1060                                     "\032VIRT_SSBD"
1061                                     "\033SSB_NO"
1062                                     );
1063                         }
1064
1065                         if (via_feature_rng != 0 || via_feature_xcrypt != 0)
1066                                 print_via_padlock_info();
1067
1068                         if (cpu_feature2 & CPUID2_VMX)
1069                                 print_vmx_info();
1070
1071                         if (amd_feature2 & AMDID2_SVM)
1072                                 print_svm_info();
1073
1074                         if ((cpu_feature & CPUID_HTT) &&
1075                             cpu_vendor_id == CPU_VENDOR_AMD)
1076                                 cpu_feature &= ~CPUID_HTT;
1077
1078                         /*
1079                          * If this CPU supports P-state invariant TSC then
1080                          * mention the capability.
1081                          */
1082                         if (tsc_is_invariant) {
1083                                 printf("\n  TSC: P-state invariant");
1084                                 if (tsc_perf_stat)
1085                                         printf(", performance statistics");
1086                         }
1087                 }
1088 #ifdef __i386__
1089         } else if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
1090                 printf("  DIR=0x%04x", cyrix_did);
1091                 printf("  Stepping=%u", (cyrix_did & 0xf000) >> 12);
1092                 printf("  Revision=%u", (cyrix_did & 0x0f00) >> 8);
1093 #ifndef CYRIX_CACHE_REALLY_WORKS
1094                 if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700)
1095                         printf("\n  CPU cache: write-through mode");
1096 #endif
1097 #endif
1098         }
1099
1100         /* Avoid ugly blank lines: only print newline when we have to. */
1101         if (*cpu_vendor || cpu_id)
1102                 printf("\n");
1103
1104         if (bootverbose) {
1105                 if (cpu_vendor_id == CPU_VENDOR_AMD)
1106                         print_AMD_info();
1107                 else if (cpu_vendor_id == CPU_VENDOR_INTEL)
1108                         print_INTEL_info();
1109 #ifdef __i386__
1110                 else if (cpu_vendor_id == CPU_VENDOR_TRANSMETA)
1111                         print_transmeta_info();
1112 #endif
1113         }
1114
1115         print_hypervisor_info();
1116 }
1117
1118 #ifdef __i386__
1119 void
1120 panicifcpuunsupported(void)
1121 {
1122
1123 #if !defined(lint)
1124 #if !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU)
1125 #error This kernel is not configured for one of the supported CPUs
1126 #endif
1127 #else /* lint */
1128 #endif /* lint */
1129         /*
1130          * Now that we have told the user what they have,
1131          * let them know if that machine type isn't configured.
1132          */
1133         switch (cpu_class) {
1134         case CPUCLASS_286:      /* a 286 should not make it this far, anyway */
1135         case CPUCLASS_386:
1136 #if !defined(I486_CPU)
1137         case CPUCLASS_486:
1138 #endif
1139 #if !defined(I586_CPU)
1140         case CPUCLASS_586:
1141 #endif
1142 #if !defined(I686_CPU)
1143         case CPUCLASS_686:
1144 #endif
1145                 panic("CPU class not configured");
1146         default:
1147                 break;
1148         }
1149 }
1150
1151 static  volatile u_int trap_by_rdmsr;
1152
1153 /*
1154  * Special exception 6 handler.
1155  * The rdmsr instruction generates invalid opcodes fault on 486-class
1156  * Cyrix CPU.  Stacked eip register points the rdmsr instruction in the
1157  * function identblue() when this handler is called.  Stacked eip should
1158  * be advanced.
1159  */
1160 inthand_t       bluetrap6;
1161 #ifdef __GNUCLIKE_ASM
1162 __asm
1163 ("                                                                      \n\
1164         .text                                                           \n\
1165         .p2align 2,0x90                                                 \n\
1166         .type   " __XSTRING(CNAME(bluetrap6)) ",@function               \n\
1167 " __XSTRING(CNAME(bluetrap6)) ":                                        \n\
1168         ss                                                              \n\
1169         movl    $0xa8c1d," __XSTRING(CNAME(trap_by_rdmsr)) "            \n\
1170         addl    $2, (%esp)      /* rdmsr is a 2-byte instruction */     \n\
1171         iret                                                            \n\
1172 ");
1173 #endif
1174
1175 /*
1176  * Special exception 13 handler.
1177  * Accessing non-existent MSR generates general protection fault.
1178  */
1179 inthand_t       bluetrap13;
1180 #ifdef __GNUCLIKE_ASM
1181 __asm
1182 ("                                                                      \n\
1183         .text                                                           \n\
1184         .p2align 2,0x90                                                 \n\
1185         .type   " __XSTRING(CNAME(bluetrap13)) ",@function              \n\
1186 " __XSTRING(CNAME(bluetrap13)) ":                                       \n\
1187         ss                                                              \n\
1188         movl    $0xa89c4," __XSTRING(CNAME(trap_by_rdmsr)) "            \n\
1189         popl    %eax            /* discard error code */                \n\
1190         addl    $2, (%esp)      /* rdmsr is a 2-byte instruction */     \n\
1191         iret                                                            \n\
1192 ");
1193 #endif
1194
1195 /*
1196  * Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not
1197  * support cpuid instruction.  This function should be called after
1198  * loading interrupt descriptor table register.
1199  *
1200  * I don't like this method that handles fault, but I couldn't get
1201  * information for any other methods.  Does blue giant know?
1202  */
1203 static int
1204 identblue(void)
1205 {
1206
1207         trap_by_rdmsr = 0;
1208
1209         /*
1210          * Cyrix 486-class CPU does not support rdmsr instruction.
1211          * The rdmsr instruction generates invalid opcode fault, and exception
1212          * will be trapped by bluetrap6() on Cyrix 486-class CPU.  The
1213          * bluetrap6() set the magic number to trap_by_rdmsr.
1214          */
1215         setidt(IDT_UD, bluetrap6, SDT_SYS386TGT, SEL_KPL,
1216             GSEL(GCODE_SEL, SEL_KPL));
1217
1218         /*
1219          * Certain BIOS disables cpuid instruction of Cyrix 6x86MX CPU.
1220          * In this case, rdmsr generates general protection fault, and
1221          * exception will be trapped by bluetrap13().
1222          */
1223         setidt(IDT_GP, bluetrap13, SDT_SYS386TGT, SEL_KPL,
1224             GSEL(GCODE_SEL, SEL_KPL));
1225
1226         rdmsr(0x1002);          /* Cyrix CPU generates fault. */
1227
1228         if (trap_by_rdmsr == 0xa8c1d)
1229                 return IDENTBLUE_CYRIX486;
1230         else if (trap_by_rdmsr == 0xa89c4)
1231                 return IDENTBLUE_CYRIXM2;
1232         return IDENTBLUE_IBMCPU;
1233 }
1234
1235
1236 /*
1237  * identifycyrix() set lower 16 bits of cyrix_did as follows:
1238  *
1239  *  F E D C B A 9 8 7 6 5 4 3 2 1 0
1240  * +-------+-------+---------------+
1241  * |  SID  |  RID  |   Device ID   |
1242  * |    (DIR 1)    |    (DIR 0)    |
1243  * +-------+-------+---------------+
1244  */
1245 static void
1246 identifycyrix(void)
1247 {
1248         register_t saveintr;
1249         int     ccr2_test = 0, dir_test = 0;
1250         u_char  ccr2, ccr3;
1251
1252         saveintr = intr_disable();
1253
1254         ccr2 = read_cyrix_reg(CCR2);
1255         write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW);
1256         read_cyrix_reg(CCR2);
1257         if (read_cyrix_reg(CCR2) != ccr2)
1258                 ccr2_test = 1;
1259         write_cyrix_reg(CCR2, ccr2);
1260
1261         ccr3 = read_cyrix_reg(CCR3);
1262         write_cyrix_reg(CCR3, ccr3 ^ CCR3_MAPEN3);
1263         read_cyrix_reg(CCR3);
1264         if (read_cyrix_reg(CCR3) != ccr3)
1265                 dir_test = 1;                                   /* CPU supports DIRs. */
1266         write_cyrix_reg(CCR3, ccr3);
1267
1268         if (dir_test) {
1269                 /* Device ID registers are available. */
1270                 cyrix_did = read_cyrix_reg(DIR1) << 8;
1271                 cyrix_did += read_cyrix_reg(DIR0);
1272         } else if (ccr2_test)
1273                 cyrix_did = 0x0010;             /* 486S A-step */
1274         else
1275                 cyrix_did = 0x00ff;             /* Old 486SLC/DLC and TI486SXLC/SXL */
1276
1277         intr_restore(saveintr);
1278 }
1279 #endif
1280
1281 /* Update TSC freq with the value indicated by the caller. */
1282 static void
1283 tsc_freq_changed(void *arg __unused, const struct cf_level *level, int status)
1284 {
1285
1286         /* If there was an error during the transition, don't do anything. */
1287         if (status != 0)
1288                 return;
1289
1290         /* Total setting for this level gives the new frequency in MHz. */
1291         hw_clockrate = level->total_set.freq;
1292 }
1293
1294 static void
1295 hook_tsc_freq(void *arg __unused)
1296 {
1297
1298         if (tsc_is_invariant)
1299                 return;
1300
1301         tsc_post_tag = EVENTHANDLER_REGISTER(cpufreq_post_change,
1302             tsc_freq_changed, NULL, EVENTHANDLER_PRI_ANY);
1303 }
1304
1305 SYSINIT(hook_tsc_freq, SI_SUB_CONFIGURE, SI_ORDER_ANY, hook_tsc_freq, NULL);
1306
1307 static const char *const vm_bnames[] = {
1308         "QEMU",                         /* QEMU */
1309         "Plex86",                       /* Plex86 */
1310         "Bochs",                        /* Bochs */
1311         "Xen",                          /* Xen */
1312         "BHYVE",                        /* bhyve */
1313         "Seabios",                      /* KVM */
1314         NULL
1315 };
1316
1317 static const char *const vm_pnames[] = {
1318         "VMware Virtual Platform",      /* VMWare VM */
1319         "Virtual Machine",              /* Microsoft VirtualPC */
1320         "VirtualBox",                   /* Sun xVM VirtualBox */
1321         "Parallels Virtual Platform",   /* Parallels VM */
1322         "KVM",                          /* KVM */
1323         NULL
1324 };
1325
1326 void
1327 identify_hypervisor(void)
1328 {
1329         u_int regs[4];
1330         char *p;
1331         int i;
1332
1333         /*
1334          * [RFC] CPUID usage for interaction between Hypervisors and Linux.
1335          * http://lkml.org/lkml/2008/10/1/246
1336          *
1337          * KB1009458: Mechanisms to determine if software is running in
1338          * a VMware virtual machine
1339          * http://kb.vmware.com/kb/1009458
1340          */
1341         if (cpu_feature2 & CPUID2_HV) {
1342                 vm_guest = VM_GUEST_VM;
1343                 do_cpuid(0x40000000, regs);
1344
1345                 /*
1346                  * KVM from Linux kernels prior to commit
1347                  * 57c22e5f35aa4b9b2fe11f73f3e62bbf9ef36190 set %eax
1348                  * to 0 rather than a valid hv_high value.  Check for
1349                  * the KVM signature bytes and fixup %eax to the
1350                  * highest supported leaf in that case.
1351                  */
1352                 if (regs[0] == 0 && regs[1] == 0x4b4d564b &&
1353                     regs[2] == 0x564b4d56 && regs[3] == 0x0000004d)
1354                         regs[0] = 0x40000001;
1355
1356                 if (regs[0] >= 0x40000000) {
1357                         hv_high = regs[0];
1358                         ((u_int *)&hv_vendor)[0] = regs[1];
1359                         ((u_int *)&hv_vendor)[1] = regs[2];
1360                         ((u_int *)&hv_vendor)[2] = regs[3];
1361                         hv_vendor[12] = '\0';
1362                         if (strcmp(hv_vendor, "VMwareVMware") == 0)
1363                                 vm_guest = VM_GUEST_VMWARE;
1364                         else if (strcmp(hv_vendor, "Microsoft Hv") == 0)
1365                                 vm_guest = VM_GUEST_HV;
1366                         else if (strcmp(hv_vendor, "KVMKVMKVM") == 0)
1367                                 vm_guest = VM_GUEST_KVM;
1368                         else if (strcmp(hv_vendor, "bhyve bhyve ") == 0)
1369                                 vm_guest = VM_GUEST_BHYVE;
1370                 }
1371                 return;
1372         }
1373
1374         /*
1375          * Examine SMBIOS strings for older hypervisors.
1376          */
1377         p = kern_getenv("smbios.system.serial");
1378         if (p != NULL) {
1379                 if (strncmp(p, "VMware-", 7) == 0 || strncmp(p, "VMW", 3) == 0) {
1380                         vmware_hvcall(VMW_HVCMD_GETVERSION, regs);
1381                         if (regs[1] == VMW_HVMAGIC) {
1382                                 vm_guest = VM_GUEST_VMWARE;
1383                                 freeenv(p);
1384                                 return;
1385                         }
1386                 }
1387                 freeenv(p);
1388         }
1389
1390         /*
1391          * XXX: Some of these entries may not be needed since they were
1392          * added to FreeBSD before the checks above.
1393          */
1394         p = kern_getenv("smbios.bios.vendor");
1395         if (p != NULL) {
1396                 for (i = 0; vm_bnames[i] != NULL; i++)
1397                         if (strcmp(p, vm_bnames[i]) == 0) {
1398                                 vm_guest = VM_GUEST_VM;
1399                                 freeenv(p);
1400                                 return;
1401                         }
1402                 freeenv(p);
1403         }
1404         p = kern_getenv("smbios.system.product");
1405         if (p != NULL) {
1406                 for (i = 0; vm_pnames[i] != NULL; i++)
1407                         if (strcmp(p, vm_pnames[i]) == 0) {
1408                                 vm_guest = VM_GUEST_VM;
1409                                 freeenv(p);
1410                                 return;
1411                         }
1412                 freeenv(p);
1413         }
1414 }
1415
1416 bool
1417 fix_cpuid(void)
1418 {
1419         uint64_t msr;
1420
1421         /*
1422          * Clear "Limit CPUID Maxval" bit and return true if the caller should
1423          * get the largest standard CPUID function number again if it is set
1424          * from BIOS.  It is necessary for probing correct CPU topology later
1425          * and for the correct operation of the AVX-aware userspace.
1426          */
1427         if (cpu_vendor_id == CPU_VENDOR_INTEL &&
1428             ((CPUID_TO_FAMILY(cpu_id) == 0xf &&
1429             CPUID_TO_MODEL(cpu_id) >= 0x3) ||
1430             (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
1431             CPUID_TO_MODEL(cpu_id) >= 0xe))) {
1432                 msr = rdmsr(MSR_IA32_MISC_ENABLE);
1433                 if ((msr & IA32_MISC_EN_LIMCPUID) != 0) {
1434                         msr &= ~IA32_MISC_EN_LIMCPUID;
1435                         wrmsr(MSR_IA32_MISC_ENABLE, msr);
1436                         return (true);
1437                 }
1438         }
1439
1440         /*
1441          * Re-enable AMD Topology Extension that could be disabled by BIOS
1442          * on some notebook processors.  Without the extension it's really
1443          * hard to determine the correct CPU cache topology.
1444          * See BIOS and Kernel Developer’s Guide (BKDG) for AMD Family 15h
1445          * Models 60h-6Fh Processors, Publication # 50742.
1446          */
1447         if (vm_guest == VM_GUEST_NO && cpu_vendor_id == CPU_VENDOR_AMD &&
1448             CPUID_TO_FAMILY(cpu_id) == 0x15) {
1449                 msr = rdmsr(MSR_EXTFEATURES);
1450                 if ((msr & ((uint64_t)1 << 54)) == 0) {
1451                         msr |= (uint64_t)1 << 54;
1452                         wrmsr(MSR_EXTFEATURES, msr);
1453                         return (true);
1454                 }
1455         }
1456         return (false);
1457 }
1458
1459 void
1460 identify_cpu1(void)
1461 {
1462         u_int regs[4];
1463
1464         do_cpuid(0, regs);
1465         cpu_high = regs[0];
1466         ((u_int *)&cpu_vendor)[0] = regs[1];
1467         ((u_int *)&cpu_vendor)[1] = regs[3];
1468         ((u_int *)&cpu_vendor)[2] = regs[2];
1469         cpu_vendor[12] = '\0';
1470
1471         do_cpuid(1, regs);
1472         cpu_id = regs[0];
1473         cpu_procinfo = regs[1];
1474         cpu_feature = regs[3];
1475         cpu_feature2 = regs[2];
1476 }
1477
1478 void
1479 identify_cpu2(void)
1480 {
1481         u_int regs[4], cpu_stdext_disable;
1482
1483         if (cpu_high >= 7) {
1484                 cpuid_count(7, 0, regs);
1485                 cpu_stdext_feature = regs[1];
1486
1487                 /*
1488                  * Some hypervisors failed to filter out unsupported
1489                  * extended features.  Allow to disable the
1490                  * extensions, activation of which requires setting a
1491                  * bit in CR4, and which VM monitors do not support.
1492                  */
1493                 cpu_stdext_disable = 0;
1494                 TUNABLE_INT_FETCH("hw.cpu_stdext_disable", &cpu_stdext_disable);
1495                 cpu_stdext_feature &= ~cpu_stdext_disable;
1496
1497                 cpu_stdext_feature2 = regs[2];
1498                 cpu_stdext_feature3 = regs[3];
1499
1500                 if ((cpu_stdext_feature3 & CPUID_STDEXT3_ARCH_CAP) != 0)
1501                         cpu_ia32_arch_caps = rdmsr(MSR_IA32_ARCH_CAP);
1502         }
1503 }
1504
1505 void
1506 identify_cpu_fixup_bsp(void)
1507 {
1508         u_int regs[4];
1509
1510         cpu_vendor_id = find_cpu_vendor_id();
1511
1512         if (fix_cpuid()) {
1513                 do_cpuid(0, regs);
1514                 cpu_high = regs[0];
1515         }
1516 }
1517
1518 /*
1519  * Final stage of CPU identification.
1520  */
1521 void
1522 finishidentcpu(void)
1523 {
1524         u_int regs[4];
1525 #ifdef __i386__
1526         u_char ccr3;
1527 #endif
1528
1529         identify_cpu_fixup_bsp();
1530
1531         if (cpu_high >= 5 && (cpu_feature2 & CPUID2_MON) != 0) {
1532                 do_cpuid(5, regs);
1533                 cpu_mon_mwait_flags = regs[2];
1534                 cpu_mon_min_size = regs[0] &  CPUID5_MON_MIN_SIZE;
1535                 cpu_mon_max_size = regs[1] &  CPUID5_MON_MAX_SIZE;
1536         }
1537
1538         identify_cpu2();
1539
1540 #ifdef __i386__
1541         if (cpu_high > 0 &&
1542             (cpu_vendor_id == CPU_VENDOR_INTEL ||
1543              cpu_vendor_id == CPU_VENDOR_AMD ||
1544              cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
1545              cpu_vendor_id == CPU_VENDOR_CENTAUR ||
1546              cpu_vendor_id == CPU_VENDOR_NSC)) {
1547                 do_cpuid(0x80000000, regs);
1548                 if (regs[0] >= 0x80000000)
1549                         cpu_exthigh = regs[0];
1550         }
1551 #else
1552         if (cpu_vendor_id == CPU_VENDOR_INTEL ||
1553             cpu_vendor_id == CPU_VENDOR_AMD ||
1554             cpu_vendor_id == CPU_VENDOR_CENTAUR) {
1555                 do_cpuid(0x80000000, regs);
1556                 cpu_exthigh = regs[0];
1557         }
1558 #endif
1559         if (cpu_exthigh >= 0x80000001) {
1560                 do_cpuid(0x80000001, regs);
1561                 amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff);
1562                 amd_feature2 = regs[2];
1563         }
1564         if (cpu_exthigh >= 0x80000007) {
1565                 do_cpuid(0x80000007, regs);
1566                 amd_rascap = regs[1];
1567                 amd_pminfo = regs[3];
1568         }
1569         if (cpu_exthigh >= 0x80000008) {
1570                 do_cpuid(0x80000008, regs);
1571                 cpu_maxphyaddr = regs[0] & 0xff;
1572                 amd_extended_feature_extensions = regs[1];
1573                 cpu_procinfo2 = regs[2];
1574         } else {
1575                 cpu_maxphyaddr = (cpu_feature & CPUID_PAE) != 0 ? 36 : 32;
1576         }
1577
1578 #ifdef __i386__
1579         if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
1580                 if (cpu == CPU_486) {
1581                         /*
1582                          * These conditions are equivalent to:
1583                          *     - CPU does not support cpuid instruction.
1584                          *     - Cyrix/IBM CPU is detected.
1585                          */
1586                         if (identblue() == IDENTBLUE_IBMCPU) {
1587                                 strcpy(cpu_vendor, "IBM");
1588                                 cpu_vendor_id = CPU_VENDOR_IBM;
1589                                 cpu = CPU_BLUE;
1590                                 return;
1591                         }
1592                 }
1593                 switch (cpu_id & 0xf00) {
1594                 case 0x600:
1595                         /*
1596                          * Cyrix's datasheet does not describe DIRs.
1597                          * Therefor, I assume it does not have them
1598                          * and use the result of the cpuid instruction.
1599                          * XXX they seem to have it for now at least. -Peter
1600                          */
1601                         identifycyrix();
1602                         cpu = CPU_M2;
1603                         break;
1604                 default:
1605                         identifycyrix();
1606                         /*
1607                          * This routine contains a trick.
1608                          * Don't check (cpu_id & 0x00f0) == 0x50 to detect M2, now.
1609                          */
1610                         switch (cyrix_did & 0x00f0) {
1611                         case 0x00:
1612                         case 0xf0:
1613                                 cpu = CPU_486DLC;
1614                                 break;
1615                         case 0x10:
1616                                 cpu = CPU_CY486DX;
1617                                 break;
1618                         case 0x20:
1619                                 if ((cyrix_did & 0x000f) < 8)
1620                                         cpu = CPU_M1;
1621                                 else
1622                                         cpu = CPU_M1SC;
1623                                 break;
1624                         case 0x30:
1625                                 cpu = CPU_M1;
1626                                 break;
1627                         case 0x40:
1628                                 /* MediaGX CPU */
1629                                 cpu = CPU_M1SC;
1630                                 break;
1631                         default:
1632                                 /* M2 and later CPUs are treated as M2. */
1633                                 cpu = CPU_M2;
1634
1635                                 /*
1636                                  * enable cpuid instruction.
1637                                  */
1638                                 ccr3 = read_cyrix_reg(CCR3);
1639                                 write_cyrix_reg(CCR3, CCR3_MAPEN0);
1640                                 write_cyrix_reg(CCR4, read_cyrix_reg(CCR4) | CCR4_CPUID);
1641                                 write_cyrix_reg(CCR3, ccr3);
1642
1643                                 do_cpuid(0, regs);
1644                                 cpu_high = regs[0];     /* eax */
1645                                 do_cpuid(1, regs);
1646                                 cpu_id = regs[0];       /* eax */
1647                                 cpu_feature = regs[3];  /* edx */
1648                                 break;
1649                         }
1650                 }
1651         } else if (cpu == CPU_486 && *cpu_vendor == '\0') {
1652                 /*
1653                  * There are BlueLightning CPUs that do not change
1654                  * undefined flags by dividing 5 by 2.  In this case,
1655                  * the CPU identification routine in locore.s leaves
1656                  * cpu_vendor null string and puts CPU_486 into the
1657                  * cpu.
1658                  */
1659                 if (identblue() == IDENTBLUE_IBMCPU) {
1660                         strcpy(cpu_vendor, "IBM");
1661                         cpu_vendor_id = CPU_VENDOR_IBM;
1662                         cpu = CPU_BLUE;
1663                         return;
1664                 }
1665         }
1666 #endif
1667 }
1668
1669 int
1670 pti_get_default(void)
1671 {
1672
1673         if (strcmp(cpu_vendor, AMD_VENDOR_ID) == 0)
1674                 return (0);
1675         if ((cpu_ia32_arch_caps & IA32_ARCH_CAP_RDCL_NO) != 0)
1676                 return (0);
1677         return (1);
1678 }
1679
1680 static u_int
1681 find_cpu_vendor_id(void)
1682 {
1683         int     i;
1684
1685         for (i = 0; i < nitems(cpu_vendors); i++)
1686                 if (strcmp(cpu_vendor, cpu_vendors[i].vendor) == 0)
1687                         return (cpu_vendors[i].vendor_id);
1688         return (0);
1689 }
1690
1691 static void
1692 print_AMD_assoc(int i)
1693 {
1694         if (i == 255)
1695                 printf(", fully associative\n");
1696         else
1697                 printf(", %d-way associative\n", i);
1698 }
1699
1700 static void
1701 print_AMD_l2_assoc(int i)
1702 {
1703         switch (i & 0x0f) {
1704         case 0: printf(", disabled/not present\n"); break;
1705         case 1: printf(", direct mapped\n"); break;
1706         case 2: printf(", 2-way associative\n"); break;
1707         case 4: printf(", 4-way associative\n"); break;
1708         case 6: printf(", 8-way associative\n"); break;
1709         case 8: printf(", 16-way associative\n"); break;
1710         case 15: printf(", fully associative\n"); break;
1711         default: printf(", reserved configuration\n"); break;
1712         }
1713 }
1714
1715 static void
1716 print_AMD_info(void)
1717 {
1718 #ifdef __i386__
1719         uint64_t amd_whcr;
1720 #endif
1721         u_int regs[4];
1722
1723         if (cpu_exthigh >= 0x80000005) {
1724                 do_cpuid(0x80000005, regs);
1725                 printf("L1 2MB data TLB: %d entries", (regs[0] >> 16) & 0xff);
1726                 print_AMD_assoc(regs[0] >> 24);
1727
1728                 printf("L1 2MB instruction TLB: %d entries", regs[0] & 0xff);
1729                 print_AMD_assoc((regs[0] >> 8) & 0xff);
1730
1731                 printf("L1 4KB data TLB: %d entries", (regs[1] >> 16) & 0xff);
1732                 print_AMD_assoc(regs[1] >> 24);
1733
1734                 printf("L1 4KB instruction TLB: %d entries", regs[1] & 0xff);
1735                 print_AMD_assoc((regs[1] >> 8) & 0xff);
1736
1737                 printf("L1 data cache: %d kbytes", regs[2] >> 24);
1738                 printf(", %d bytes/line", regs[2] & 0xff);
1739                 printf(", %d lines/tag", (regs[2] >> 8) & 0xff);
1740                 print_AMD_assoc((regs[2] >> 16) & 0xff);
1741
1742                 printf("L1 instruction cache: %d kbytes", regs[3] >> 24);
1743                 printf(", %d bytes/line", regs[3] & 0xff);
1744                 printf(", %d lines/tag", (regs[3] >> 8) & 0xff);
1745                 print_AMD_assoc((regs[3] >> 16) & 0xff);
1746         }
1747
1748         if (cpu_exthigh >= 0x80000006) {
1749                 do_cpuid(0x80000006, regs);
1750                 if ((regs[0] >> 16) != 0) {
1751                         printf("L2 2MB data TLB: %d entries",
1752                             (regs[0] >> 16) & 0xfff);
1753                         print_AMD_l2_assoc(regs[0] >> 28);
1754                         printf("L2 2MB instruction TLB: %d entries",
1755                             regs[0] & 0xfff);
1756                         print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
1757                 } else {
1758                         printf("L2 2MB unified TLB: %d entries",
1759                             regs[0] & 0xfff);
1760                         print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
1761                 }
1762                 if ((regs[1] >> 16) != 0) {
1763                         printf("L2 4KB data TLB: %d entries",
1764                             (regs[1] >> 16) & 0xfff);
1765                         print_AMD_l2_assoc(regs[1] >> 28);
1766
1767                         printf("L2 4KB instruction TLB: %d entries",
1768                             (regs[1] >> 16) & 0xfff);
1769                         print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
1770                 } else {
1771                         printf("L2 4KB unified TLB: %d entries",
1772                             (regs[1] >> 16) & 0xfff);
1773                         print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
1774                 }
1775                 printf("L2 unified cache: %d kbytes", regs[2] >> 16);
1776                 printf(", %d bytes/line", regs[2] & 0xff);
1777                 printf(", %d lines/tag", (regs[2] >> 8) & 0x0f);
1778                 print_AMD_l2_assoc((regs[2] >> 12) & 0x0f);
1779         }
1780
1781 #ifdef __i386__
1782         if (((cpu_id & 0xf00) == 0x500)
1783             && (((cpu_id & 0x0f0) > 0x80)
1784                 || (((cpu_id & 0x0f0) == 0x80)
1785                     && (cpu_id & 0x00f) > 0x07))) {
1786                 /* K6-2(new core [Stepping 8-F]), K6-III or later */
1787                 amd_whcr = rdmsr(0xc0000082);
1788                 if (!(amd_whcr & (0x3ff << 22))) {
1789                         printf("Write Allocate Disable\n");
1790                 } else {
1791                         printf("Write Allocate Enable Limit: %dM bytes\n",
1792                             (u_int32_t)((amd_whcr & (0x3ff << 22)) >> 22) * 4);
1793                         printf("Write Allocate 15-16M bytes: %s\n",
1794                             (amd_whcr & (1 << 16)) ? "Enable" : "Disable");
1795                 }
1796         } else if (((cpu_id & 0xf00) == 0x500)
1797                    && ((cpu_id & 0x0f0) > 0x50)) {
1798                 /* K6, K6-2(old core) */
1799                 amd_whcr = rdmsr(0xc0000082);
1800                 if (!(amd_whcr & (0x7f << 1))) {
1801                         printf("Write Allocate Disable\n");
1802                 } else {
1803                         printf("Write Allocate Enable Limit: %dM bytes\n",
1804                             (u_int32_t)((amd_whcr & (0x7f << 1)) >> 1) * 4);
1805                         printf("Write Allocate 15-16M bytes: %s\n",
1806                             (amd_whcr & 0x0001) ? "Enable" : "Disable");
1807                         printf("Hardware Write Allocate Control: %s\n",
1808                             (amd_whcr & 0x0100) ? "Enable" : "Disable");
1809                 }
1810         }
1811 #endif
1812         /*
1813          * Opteron Rev E shows a bug as in very rare occasions a read memory
1814          * barrier is not performed as expected if it is followed by a
1815          * non-atomic read-modify-write instruction.
1816          * As long as that bug pops up very rarely (intensive machine usage
1817          * on other operating systems generally generates one unexplainable
1818          * crash any 2 months) and as long as a model specific fix would be
1819          * impractical at this stage, print out a warning string if the broken
1820          * model and family are identified.
1821          */
1822         if (CPUID_TO_FAMILY(cpu_id) == 0xf && CPUID_TO_MODEL(cpu_id) >= 0x20 &&
1823             CPUID_TO_MODEL(cpu_id) <= 0x3f)
1824                 printf("WARNING: This architecture revision has known SMP "
1825                     "hardware bugs which may cause random instability\n");
1826 }
1827
1828 static void
1829 print_INTEL_info(void)
1830 {
1831         u_int regs[4];
1832         u_int rounds, regnum;
1833         u_int nwaycode, nway;
1834
1835         if (cpu_high >= 2) {
1836                 rounds = 0;
1837                 do {
1838                         do_cpuid(0x2, regs);
1839                         if (rounds == 0 && (rounds = (regs[0] & 0xff)) == 0)
1840                                 break;  /* we have a buggy CPU */
1841
1842                         for (regnum = 0; regnum <= 3; ++regnum) {
1843                                 if (regs[regnum] & (1<<31))
1844                                         continue;
1845                                 if (regnum != 0)
1846                                         print_INTEL_TLB(regs[regnum] & 0xff);
1847                                 print_INTEL_TLB((regs[regnum] >> 8) & 0xff);
1848                                 print_INTEL_TLB((regs[regnum] >> 16) & 0xff);
1849                                 print_INTEL_TLB((regs[regnum] >> 24) & 0xff);
1850                         }
1851                 } while (--rounds > 0);
1852         }
1853
1854         if (cpu_exthigh >= 0x80000006) {
1855                 do_cpuid(0x80000006, regs);
1856                 nwaycode = (regs[2] >> 12) & 0x0f;
1857                 if (nwaycode >= 0x02 && nwaycode <= 0x08)
1858                         nway = 1 << (nwaycode / 2);
1859                 else
1860                         nway = 0;
1861                 printf("L2 cache: %u kbytes, %u-way associative, %u bytes/line\n",
1862                     (regs[2] >> 16) & 0xffff, nway, regs[2] & 0xff);
1863         }
1864 }
1865
1866 static void
1867 print_INTEL_TLB(u_int data)
1868 {
1869         switch (data) {
1870         case 0x0:
1871         case 0x40:
1872         default:
1873                 break;
1874         case 0x1:
1875                 printf("Instruction TLB: 4 KB pages, 4-way set associative, 32 entries\n");
1876                 break;
1877         case 0x2:
1878                 printf("Instruction TLB: 4 MB pages, fully associative, 2 entries\n");
1879                 break;
1880         case 0x3:
1881                 printf("Data TLB: 4 KB pages, 4-way set associative, 64 entries\n");
1882                 break;
1883         case 0x4:
1884                 printf("Data TLB: 4 MB Pages, 4-way set associative, 8 entries\n");
1885                 break;
1886         case 0x6:
1887                 printf("1st-level instruction cache: 8 KB, 4-way set associative, 32 byte line size\n");
1888                 break;
1889         case 0x8:
1890                 printf("1st-level instruction cache: 16 KB, 4-way set associative, 32 byte line size\n");
1891                 break;
1892         case 0x9:
1893                 printf("1st-level instruction cache: 32 KB, 4-way set associative, 64 byte line size\n");
1894                 break;
1895         case 0xa:
1896                 printf("1st-level data cache: 8 KB, 2-way set associative, 32 byte line size\n");
1897                 break;
1898         case 0xb:
1899                 printf("Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries\n");
1900                 break;
1901         case 0xc:
1902                 printf("1st-level data cache: 16 KB, 4-way set associative, 32 byte line size\n");
1903                 break;
1904         case 0xd:
1905                 printf("1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size");
1906                 break;
1907         case 0xe:
1908                 printf("1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size\n");
1909                 break;
1910         case 0x1d:
1911                 printf("2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size\n");
1912                 break;
1913         case 0x21:
1914                 printf("2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size\n");
1915                 break;
1916         case 0x22:
1917                 printf("3rd-level cache: 512 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1918                 break;
1919         case 0x23:
1920                 printf("3rd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n");
1921                 break;
1922         case 0x24:
1923                 printf("2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size\n");
1924                 break;
1925         case 0x25:
1926                 printf("3rd-level cache: 2 MB, 8-way set associative, sectored cache, 64 byte line size\n");
1927                 break;
1928         case 0x29:
1929                 printf("3rd-level cache: 4 MB, 8-way set associative, sectored cache, 64 byte line size\n");
1930                 break;
1931         case 0x2c:
1932                 printf("1st-level data cache: 32 KB, 8-way set associative, 64 byte line size\n");
1933                 break;
1934         case 0x30:
1935                 printf("1st-level instruction cache: 32 KB, 8-way set associative, 64 byte line size\n");
1936                 break;
1937         case 0x39: /* De-listed in SDM rev. 54 */
1938                 printf("2nd-level cache: 128 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1939                 break;
1940         case 0x3b: /* De-listed in SDM rev. 54 */
1941                 printf("2nd-level cache: 128 KB, 2-way set associative, sectored cache, 64 byte line size\n");
1942                 break;
1943         case 0x3c: /* De-listed in SDM rev. 54 */
1944                 printf("2nd-level cache: 256 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1945                 break;
1946         case 0x41:
1947                 printf("2nd-level cache: 128 KB, 4-way set associative, 32 byte line size\n");
1948                 break;
1949         case 0x42:
1950                 printf("2nd-level cache: 256 KB, 4-way set associative, 32 byte line size\n");
1951                 break;
1952         case 0x43:
1953                 printf("2nd-level cache: 512 KB, 4-way set associative, 32 byte line size\n");
1954                 break;
1955         case 0x44:
1956                 printf("2nd-level cache: 1 MB, 4-way set associative, 32 byte line size\n");
1957                 break;
1958         case 0x45:
1959                 printf("2nd-level cache: 2 MB, 4-way set associative, 32 byte line size\n");
1960                 break;
1961         case 0x46:
1962                 printf("3rd-level cache: 4 MB, 4-way set associative, 64 byte line size\n");
1963                 break;
1964         case 0x47:
1965                 printf("3rd-level cache: 8 MB, 8-way set associative, 64 byte line size\n");
1966                 break;
1967         case 0x48:
1968                 printf("2nd-level cache: 3MByte, 12-way set associative, 64 byte line size\n");
1969                 break;
1970         case 0x49:
1971                 if (CPUID_TO_FAMILY(cpu_id) == 0xf &&
1972                     CPUID_TO_MODEL(cpu_id) == 0x6)
1973                         printf("3rd-level cache: 4MB, 16-way set associative, 64-byte line size\n");
1974                 else
1975                         printf("2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size");
1976                 break;
1977         case 0x4a:
1978                 printf("3rd-level cache: 6MByte, 12-way set associative, 64 byte line size\n");
1979                 break;
1980         case 0x4b:
1981                 printf("3rd-level cache: 8MByte, 16-way set associative, 64 byte line size\n");
1982                 break;
1983         case 0x4c:
1984                 printf("3rd-level cache: 12MByte, 12-way set associative, 64 byte line size\n");
1985                 break;
1986         case 0x4d:
1987                 printf("3rd-level cache: 16MByte, 16-way set associative, 64 byte line size\n");
1988                 break;
1989         case 0x4e:
1990                 printf("2nd-level cache: 6MByte, 24-way set associative, 64 byte line size\n");
1991                 break;
1992         case 0x4f:
1993                 printf("Instruction TLB: 4 KByte pages, 32 entries\n");
1994                 break;
1995         case 0x50:
1996                 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 64 entries\n");
1997                 break;
1998         case 0x51:
1999                 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 128 entries\n");
2000                 break;
2001         case 0x52:
2002                 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 256 entries\n");
2003                 break;
2004         case 0x55:
2005                 printf("Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries\n");
2006                 break;
2007         case 0x56:
2008                 printf("Data TLB0: 4 MByte pages, 4-way set associative, 16 entries\n");
2009                 break;
2010         case 0x57:
2011                 printf("Data TLB0: 4 KByte pages, 4-way associative, 16 entries\n");
2012                 break;
2013         case 0x59:
2014                 printf("Data TLB0: 4 KByte pages, fully associative, 16 entries\n");
2015                 break;
2016         case 0x5a:
2017                 printf("Data TLB0: 2-MByte or 4 MByte pages, 4-way set associative, 32 entries\n");
2018                 break;
2019         case 0x5b:
2020                 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 64 entries\n");
2021                 break;
2022         case 0x5c:
2023                 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 128 entries\n");
2024                 break;
2025         case 0x5d:
2026                 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 256 entries\n");
2027                 break;
2028         case 0x60:
2029                 printf("1st-level data cache: 16 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2030                 break;
2031         case 0x61:
2032                 printf("Instruction TLB: 4 KByte pages, fully associative, 48 entries\n");
2033                 break;
2034         case 0x63:
2035                 printf("Data TLB: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries and a separate array with 1 GByte pages, 4-way set associative, 4 entries\n");
2036                 break;
2037         case 0x64:
2038                 printf("Data TLB: 4 KBytes pages, 4-way set associative, 512 entries\n");
2039                 break;
2040         case 0x66:
2041                 printf("1st-level data cache: 8 KB, 4-way set associative, sectored cache, 64 byte line size\n");
2042                 break;
2043         case 0x67:
2044                 printf("1st-level data cache: 16 KB, 4-way set associative, sectored cache, 64 byte line size\n");
2045                 break;
2046         case 0x68:
2047                 printf("1st-level data cache: 32 KB, 4 way set associative, sectored cache, 64 byte line size\n");
2048                 break;
2049         case 0x6a:
2050                 printf("uTLB: 4KByte pages, 8-way set associative, 64 entries\n");
2051                 break;
2052         case 0x6b:
2053                 printf("DTLB: 4KByte pages, 8-way set associative, 256 entries\n");
2054                 break;
2055         case 0x6c:
2056                 printf("DTLB: 2M/4M pages, 8-way set associative, 128 entries\n");
2057                 break;
2058         case 0x6d:
2059                 printf("DTLB: 1 GByte pages, fully associative, 16 entries\n");
2060                 break;
2061         case 0x70:
2062                 printf("Trace cache: 12K-uops, 8-way set associative\n");
2063                 break;
2064         case 0x71:
2065                 printf("Trace cache: 16K-uops, 8-way set associative\n");
2066                 break;
2067         case 0x72:
2068                 printf("Trace cache: 32K-uops, 8-way set associative\n");
2069                 break;
2070         case 0x76:
2071                 printf("Instruction TLB: 2M/4M pages, fully associative, 8 entries\n");
2072                 break;
2073         case 0x78:
2074                 printf("2nd-level cache: 1 MB, 4-way set associative, 64-byte line size\n");
2075                 break;
2076         case 0x79:
2077                 printf("2nd-level cache: 128 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2078                 break;
2079         case 0x7a:
2080                 printf("2nd-level cache: 256 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2081                 break;
2082         case 0x7b:
2083                 printf("2nd-level cache: 512 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2084                 break;
2085         case 0x7c:
2086                 printf("2nd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n");
2087                 break;
2088         case 0x7d:
2089                 printf("2nd-level cache: 2-MB, 8-way set associative, 64-byte line size\n");
2090                 break;
2091         case 0x7f:
2092                 printf("2nd-level cache: 512-KB, 2-way set associative, 64-byte line size\n");
2093                 break;
2094         case 0x80:
2095                 printf("2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size\n");
2096                 break;
2097         case 0x82:
2098                 printf("2nd-level cache: 256 KB, 8-way set associative, 32 byte line size\n");
2099                 break;
2100         case 0x83:
2101                 printf("2nd-level cache: 512 KB, 8-way set associative, 32 byte line size\n");
2102                 break;
2103         case 0x84:
2104                 printf("2nd-level cache: 1 MB, 8-way set associative, 32 byte line size\n");
2105                 break;
2106         case 0x85:
2107                 printf("2nd-level cache: 2 MB, 8-way set associative, 32 byte line size\n");
2108                 break;
2109         case 0x86:
2110                 printf("2nd-level cache: 512 KB, 4-way set associative, 64 byte line size\n");
2111                 break;
2112         case 0x87:
2113                 printf("2nd-level cache: 1 MB, 8-way set associative, 64 byte line size\n");
2114                 break;
2115         case 0xa0:
2116                 printf("DTLB: 4k pages, fully associative, 32 entries\n");
2117                 break;
2118         case 0xb0:
2119                 printf("Instruction TLB: 4 KB Pages, 4-way set associative, 128 entries\n");
2120                 break;
2121         case 0xb1:
2122                 printf("Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries\n");
2123                 break;
2124         case 0xb2:
2125                 printf("Instruction TLB: 4KByte pages, 4-way set associative, 64 entries\n");
2126                 break;
2127         case 0xb3:
2128                 printf("Data TLB: 4 KB Pages, 4-way set associative, 128 entries\n");
2129                 break;
2130         case 0xb4:
2131                 printf("Data TLB1: 4 KByte pages, 4-way associative, 256 entries\n");
2132                 break;
2133         case 0xb5:
2134                 printf("Instruction TLB: 4KByte pages, 8-way set associative, 64 entries\n");
2135                 break;
2136         case 0xb6:
2137                 printf("Instruction TLB: 4KByte pages, 8-way set associative, 128 entries\n");
2138                 break;
2139         case 0xba:
2140                 printf("Data TLB1: 4 KByte pages, 4-way associative, 64 entries\n");
2141                 break;
2142         case 0xc0:
2143                 printf("Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries\n");
2144                 break;
2145         case 0xc1:
2146                 printf("Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries\n");
2147                 break;
2148         case 0xc2:
2149                 printf("DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries\n");
2150                 break;
2151         case 0xc3:
2152                 printf("Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative, 1536 entries. Also 1GBbyte pages, 4-way, 16 entries\n");
2153                 break;
2154         case 0xc4:
2155                 printf("DTLB: 2M/4M Byte pages, 4-way associative, 32 entries\n");
2156                 break;
2157         case 0xca:
2158                 printf("Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries\n");
2159                 break;
2160         case 0xd0:
2161                 printf("3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size\n");
2162                 break;
2163         case 0xd1:
2164                 printf("3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size\n");
2165                 break;
2166         case 0xd2:
2167                 printf("3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size\n");
2168                 break;
2169         case 0xd6:
2170                 printf("3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size\n");
2171                 break;
2172         case 0xd7:
2173                 printf("3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size\n");
2174                 break;
2175         case 0xd8:
2176                 printf("3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size\n");
2177                 break;
2178         case 0xdc:
2179                 printf("3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size\n");
2180                 break;
2181         case 0xdd:
2182                 printf("3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size\n");
2183                 break;
2184         case 0xde:
2185                 printf("3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size\n");
2186                 break;
2187         case 0xe2:
2188                 printf("3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size\n");
2189                 break;
2190         case 0xe3:
2191                 printf("3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size\n");
2192                 break;
2193         case 0xe4:
2194                 printf("3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size\n");
2195                 break;
2196         case 0xea:
2197                 printf("3rd-level cache: 12MByte, 24-way set associative, 64 byte line size\n");
2198                 break;
2199         case 0xeb:
2200                 printf("3rd-level cache: 18MByte, 24-way set associative, 64 byte line size\n");
2201                 break;
2202         case 0xec:
2203                 printf("3rd-level cache: 24MByte, 24-way set associative, 64 byte line size\n");
2204                 break;
2205         case 0xf0:
2206                 printf("64-Byte prefetching\n");
2207                 break;
2208         case 0xf1:
2209                 printf("128-Byte prefetching\n");
2210                 break;
2211         }
2212 }
2213
2214 static void
2215 print_svm_info(void)
2216 {
2217         u_int features, regs[4];
2218         uint64_t msr;
2219         int comma;
2220
2221         printf("\n  SVM: ");
2222         do_cpuid(0x8000000A, regs);
2223         features = regs[3];
2224
2225         msr = rdmsr(MSR_VM_CR);
2226         if ((msr & VM_CR_SVMDIS) == VM_CR_SVMDIS)
2227                 printf("(disabled in BIOS) ");
2228
2229         if (!bootverbose) {
2230                 comma = 0;
2231                 if (features & (1 << 0)) {
2232                         printf("%sNP", comma ? "," : "");
2233                         comma = 1;
2234                 }
2235                 if (features & (1 << 3)) {
2236                         printf("%sNRIP", comma ? "," : "");
2237                         comma = 1;
2238                 }
2239                 if (features & (1 << 5)) {
2240                         printf("%sVClean", comma ? "," : "");
2241                         comma = 1;
2242                 }
2243                 if (features & (1 << 6)) {
2244                         printf("%sAFlush", comma ? "," : "");
2245                         comma = 1;
2246                 }
2247                 if (features & (1 << 7)) {
2248                         printf("%sDAssist", comma ? "," : "");
2249                         comma = 1;
2250                 }
2251                 printf("%sNAsids=%d", comma ? "," : "", regs[1]);
2252                 return;
2253         }
2254
2255         printf("Features=0x%b", features,
2256                "\020"
2257                "\001NP"                 /* Nested paging */
2258                "\002LbrVirt"            /* LBR virtualization */
2259                "\003SVML"               /* SVM lock */
2260                "\004NRIPS"              /* NRIP save */
2261                "\005TscRateMsr"         /* MSR based TSC rate control */
2262                "\006VmcbClean"          /* VMCB clean bits */
2263                "\007FlushByAsid"        /* Flush by ASID */
2264                "\010DecodeAssist"       /* Decode assist */
2265                "\011<b8>"
2266                "\012<b9>"
2267                "\013PauseFilter"        /* PAUSE intercept filter */
2268                "\014EncryptedMcodePatch"
2269                "\015PauseFilterThreshold" /* PAUSE filter threshold */
2270                "\016AVIC"               /* virtual interrupt controller */
2271                "\017<b14>"
2272                "\020V_VMSAVE_VMLOAD"
2273                "\021vGIF"
2274                "\022<b17>"
2275                "\023<b18>"
2276                "\024<b19>"
2277                "\025<b20>"
2278                "\026<b21>"
2279                "\027<b22>"
2280                "\030<b23>"
2281                "\031<b24>"
2282                "\032<b25>"
2283                "\033<b26>"
2284                "\034<b27>"
2285                "\035<b28>"
2286                "\036<b29>"
2287                "\037<b30>"
2288                "\040<b31>"
2289                 );
2290         printf("\nRevision=%d, ASIDs=%d", regs[0] & 0xff, regs[1]);
2291 }
2292
2293 #ifdef __i386__
2294 static void
2295 print_transmeta_info(void)
2296 {
2297         u_int regs[4], nreg = 0;
2298
2299         do_cpuid(0x80860000, regs);
2300         nreg = regs[0];
2301         if (nreg >= 0x80860001) {
2302                 do_cpuid(0x80860001, regs);
2303                 printf("  Processor revision %u.%u.%u.%u\n",
2304                        (regs[1] >> 24) & 0xff,
2305                        (regs[1] >> 16) & 0xff,
2306                        (regs[1] >> 8) & 0xff,
2307                        regs[1] & 0xff);
2308         }
2309         if (nreg >= 0x80860002) {
2310                 do_cpuid(0x80860002, regs);
2311                 printf("  Code Morphing Software revision %u.%u.%u-%u-%u\n",
2312                        (regs[1] >> 24) & 0xff,
2313                        (regs[1] >> 16) & 0xff,
2314                        (regs[1] >> 8) & 0xff,
2315                        regs[1] & 0xff,
2316                        regs[2]);
2317         }
2318         if (nreg >= 0x80860006) {
2319                 char info[65];
2320                 do_cpuid(0x80860003, (u_int*) &info[0]);
2321                 do_cpuid(0x80860004, (u_int*) &info[16]);
2322                 do_cpuid(0x80860005, (u_int*) &info[32]);
2323                 do_cpuid(0x80860006, (u_int*) &info[48]);
2324                 info[64] = 0;
2325                 printf("  %s\n", info);
2326         }
2327 }
2328 #endif
2329
2330 static void
2331 print_via_padlock_info(void)
2332 {
2333         u_int regs[4];
2334
2335         do_cpuid(0xc0000001, regs);
2336         printf("\n  VIA Padlock Features=0x%b", regs[3],
2337         "\020"
2338         "\003RNG"               /* RNG */
2339         "\007AES"               /* ACE */
2340         "\011AES-CTR"           /* ACE2 */
2341         "\013SHA1,SHA256"       /* PHE */
2342         "\015RSA"               /* PMM */
2343         );
2344 }
2345
2346 static uint32_t
2347 vmx_settable(uint64_t basic, int msr, int true_msr)
2348 {
2349         uint64_t val;
2350
2351         if (basic & (1ULL << 55))
2352                 val = rdmsr(true_msr);
2353         else
2354                 val = rdmsr(msr);
2355
2356         /* Just report the controls that can be set to 1. */
2357         return (val >> 32);
2358 }
2359
2360 static void
2361 print_vmx_info(void)
2362 {
2363         uint64_t basic, msr;
2364         uint32_t entry, exit, mask, pin, proc, proc2;
2365         int comma;
2366
2367         printf("\n  VT-x: ");
2368         msr = rdmsr(MSR_IA32_FEATURE_CONTROL);
2369         if (!(msr & IA32_FEATURE_CONTROL_VMX_EN))
2370                 printf("(disabled in BIOS) ");
2371         basic = rdmsr(MSR_VMX_BASIC);
2372         pin = vmx_settable(basic, MSR_VMX_PINBASED_CTLS,
2373             MSR_VMX_TRUE_PINBASED_CTLS);
2374         proc = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS,
2375             MSR_VMX_TRUE_PROCBASED_CTLS);
2376         if (proc & PROCBASED_SECONDARY_CONTROLS)
2377                 proc2 = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS2,
2378                     MSR_VMX_PROCBASED_CTLS2);
2379         else
2380                 proc2 = 0;
2381         exit = vmx_settable(basic, MSR_VMX_EXIT_CTLS, MSR_VMX_TRUE_EXIT_CTLS);
2382         entry = vmx_settable(basic, MSR_VMX_ENTRY_CTLS, MSR_VMX_TRUE_ENTRY_CTLS);
2383
2384         if (!bootverbose) {
2385                 comma = 0;
2386                 if (exit & VM_EXIT_SAVE_PAT && exit & VM_EXIT_LOAD_PAT &&
2387                     entry & VM_ENTRY_LOAD_PAT) {
2388                         printf("%sPAT", comma ? "," : "");
2389                         comma = 1;
2390                 }
2391                 if (proc & PROCBASED_HLT_EXITING) {
2392                         printf("%sHLT", comma ? "," : "");
2393                         comma = 1;
2394                 }
2395                 if (proc & PROCBASED_MTF) {
2396                         printf("%sMTF", comma ? "," : "");
2397                         comma = 1;
2398                 }
2399                 if (proc & PROCBASED_PAUSE_EXITING) {
2400                         printf("%sPAUSE", comma ? "," : "");
2401                         comma = 1;
2402                 }
2403                 if (proc2 & PROCBASED2_ENABLE_EPT) {
2404                         printf("%sEPT", comma ? "," : "");
2405                         comma = 1;
2406                 }
2407                 if (proc2 & PROCBASED2_UNRESTRICTED_GUEST) {
2408                         printf("%sUG", comma ? "," : "");
2409                         comma = 1;
2410                 }
2411                 if (proc2 & PROCBASED2_ENABLE_VPID) {
2412                         printf("%sVPID", comma ? "," : "");
2413                         comma = 1;
2414                 }
2415                 if (proc & PROCBASED_USE_TPR_SHADOW &&
2416                     proc2 & PROCBASED2_VIRTUALIZE_APIC_ACCESSES &&
2417                     proc2 & PROCBASED2_VIRTUALIZE_X2APIC_MODE &&
2418                     proc2 & PROCBASED2_APIC_REGISTER_VIRTUALIZATION &&
2419                     proc2 & PROCBASED2_VIRTUAL_INTERRUPT_DELIVERY) {
2420                         printf("%sVID", comma ? "," : "");
2421                         comma = 1;
2422                         if (pin & PINBASED_POSTED_INTERRUPT)
2423                                 printf(",PostIntr");
2424                 }
2425                 return;
2426         }
2427
2428         mask = basic >> 32;
2429         printf("Basic Features=0x%b", mask,
2430         "\020"
2431         "\02132PA"              /* 32-bit physical addresses */
2432         "\022SMM"               /* SMM dual-monitor */
2433         "\027INS/OUTS"          /* VM-exit info for INS and OUTS */
2434         "\030TRUE"              /* TRUE_CTLS MSRs */
2435         );
2436         printf("\n        Pin-Based Controls=0x%b", pin,
2437         "\020"
2438         "\001ExtINT"            /* External-interrupt exiting */
2439         "\004NMI"               /* NMI exiting */
2440         "\006VNMI"              /* Virtual NMIs */
2441         "\007PreTmr"            /* Activate VMX-preemption timer */
2442         "\010PostIntr"          /* Process posted interrupts */
2443         );
2444         printf("\n        Primary Processor Controls=0x%b", proc,
2445         "\020"
2446         "\003INTWIN"            /* Interrupt-window exiting */
2447         "\004TSCOff"            /* Use TSC offsetting */
2448         "\010HLT"               /* HLT exiting */
2449         "\012INVLPG"            /* INVLPG exiting */
2450         "\013MWAIT"             /* MWAIT exiting */
2451         "\014RDPMC"             /* RDPMC exiting */
2452         "\015RDTSC"             /* RDTSC exiting */
2453         "\020CR3-LD"            /* CR3-load exiting */
2454         "\021CR3-ST"            /* CR3-store exiting */
2455         "\024CR8-LD"            /* CR8-load exiting */
2456         "\025CR8-ST"            /* CR8-store exiting */
2457         "\026TPR"               /* Use TPR shadow */
2458         "\027NMIWIN"            /* NMI-window exiting */
2459         "\030MOV-DR"            /* MOV-DR exiting */
2460         "\031IO"                /* Unconditional I/O exiting */
2461         "\032IOmap"             /* Use I/O bitmaps */
2462         "\034MTF"               /* Monitor trap flag */
2463         "\035MSRmap"            /* Use MSR bitmaps */
2464         "\036MONITOR"           /* MONITOR exiting */
2465         "\037PAUSE"             /* PAUSE exiting */
2466         );
2467         if (proc & PROCBASED_SECONDARY_CONTROLS)
2468                 printf("\n        Secondary Processor Controls=0x%b", proc2,
2469                 "\020"
2470                 "\001APIC"              /* Virtualize APIC accesses */
2471                 "\002EPT"               /* Enable EPT */
2472                 "\003DT"                /* Descriptor-table exiting */
2473                 "\004RDTSCP"            /* Enable RDTSCP */
2474                 "\005x2APIC"            /* Virtualize x2APIC mode */
2475                 "\006VPID"              /* Enable VPID */
2476                 "\007WBINVD"            /* WBINVD exiting */
2477                 "\010UG"                /* Unrestricted guest */
2478                 "\011APIC-reg"          /* APIC-register virtualization */
2479                 "\012VID"               /* Virtual-interrupt delivery */
2480                 "\013PAUSE-loop"        /* PAUSE-loop exiting */
2481                 "\014RDRAND"            /* RDRAND exiting */
2482                 "\015INVPCID"           /* Enable INVPCID */
2483                 "\016VMFUNC"            /* Enable VM functions */
2484                 "\017VMCS"              /* VMCS shadowing */
2485                 "\020EPT#VE"            /* EPT-violation #VE */
2486                 "\021XSAVES"            /* Enable XSAVES/XRSTORS */
2487                 );
2488         printf("\n        Exit Controls=0x%b", mask,
2489         "\020"
2490         "\003DR"                /* Save debug controls */
2491                                 /* Ignore Host address-space size */
2492         "\015PERF"              /* Load MSR_PERF_GLOBAL_CTRL */
2493         "\020AckInt"            /* Acknowledge interrupt on exit */
2494         "\023PAT-SV"            /* Save MSR_PAT */
2495         "\024PAT-LD"            /* Load MSR_PAT */
2496         "\025EFER-SV"           /* Save MSR_EFER */
2497         "\026EFER-LD"           /* Load MSR_EFER */
2498         "\027PTMR-SV"           /* Save VMX-preemption timer value */
2499         );
2500         printf("\n        Entry Controls=0x%b", mask,
2501         "\020"
2502         "\003DR"                /* Save debug controls */
2503                                 /* Ignore IA-32e mode guest */
2504                                 /* Ignore Entry to SMM */
2505                                 /* Ignore Deactivate dual-monitor treatment */
2506         "\016PERF"              /* Load MSR_PERF_GLOBAL_CTRL */
2507         "\017PAT"               /* Load MSR_PAT */
2508         "\020EFER"              /* Load MSR_EFER */
2509         );
2510         if (proc & PROCBASED_SECONDARY_CONTROLS &&
2511             (proc2 & (PROCBASED2_ENABLE_EPT | PROCBASED2_ENABLE_VPID)) != 0) {
2512                 msr = rdmsr(MSR_VMX_EPT_VPID_CAP);
2513                 mask = msr;
2514                 printf("\n        EPT Features=0x%b", mask,
2515                 "\020"
2516                 "\001XO"                /* Execute-only translations */
2517                 "\007PW4"               /* Page-walk length of 4 */
2518                 "\011UC"                /* EPT paging-structure mem can be UC */
2519                 "\017WB"                /* EPT paging-structure mem can be WB */
2520                 "\0212M"                /* EPT PDE can map a 2-Mbyte page */
2521                 "\0221G"                /* EPT PDPTE can map a 1-Gbyte page */
2522                 "\025INVEPT"            /* INVEPT is supported */
2523                 "\026AD"                /* Accessed and dirty flags for EPT */
2524                 "\032single"            /* INVEPT single-context type */
2525                 "\033all"               /* INVEPT all-context type */
2526                 );
2527                 mask = msr >> 32;
2528                 printf("\n        VPID Features=0x%b", mask,
2529                 "\020"
2530                 "\001INVVPID"           /* INVVPID is supported */
2531                 "\011individual"        /* INVVPID individual-address type */
2532                 "\012single"            /* INVVPID single-context type */
2533                 "\013all"               /* INVVPID all-context type */
2534                  /* INVVPID single-context-retaining-globals type */
2535                 "\014single-globals"
2536                 );
2537         }
2538 }
2539
2540 static void
2541 print_hypervisor_info(void)
2542 {
2543
2544         if (*hv_vendor)
2545                 printf("Hypervisor: Origin = \"%s\"\n", hv_vendor);
2546 }
2547
2548 /*
2549  * Returns the maximum physical address that can be used with the
2550  * current system.
2551  */
2552 vm_paddr_t
2553 cpu_getmaxphyaddr(void)
2554 {
2555
2556 #if defined(__i386__)
2557         if (!pae_mode)
2558                 return (0xffffffff);
2559 #endif
2560         return ((1ULL << cpu_maxphyaddr) - 1);
2561 }