1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple=mips -mcpu=mips2 -relocation-model=pic \
3 ; RUN: | FileCheck %s -check-prefixes=GP32,GP32R0R1
4 ; RUN: llc < %s -mtriple=mips -mcpu=mips32 -relocation-model=pic \
5 ; RUN: | FileCheck %s -check-prefixes=GP32,GP32R0R1
6 ; RUN: llc < %s -mtriple=mips -mcpu=mips32r2 -relocation-model=pic \
7 ; RUN: | FileCheck %s -check-prefixes=GP32,GP32R2R5
8 ; RUN: llc < %s -mtriple=mips -mcpu=mips32r3 -relocation-model=pic \
9 ; RUN: | FileCheck %s -check-prefixes=GP32,GP32R2R5
10 ; RUN: llc < %s -mtriple=mips -mcpu=mips32r5 -relocation-model=pic \
11 ; RUN: | FileCheck %s -check-prefixes=GP32,GP32R2R5
12 ; RUN: llc < %s -mtriple=mips -mcpu=mips32r6 -relocation-model=pic \
13 ; RUN: | FileCheck %s -check-prefix=GP32R6
15 ; RUN: llc < %s -mtriple=mips64 -mcpu=mips3 -relocation-model=pic \
16 ; RUN: | FileCheck %s -check-prefixes=GP64,GP64R0R1
17 ; RUN: llc < %s -mtriple=mips64 -mcpu=mips4 -relocation-model=pic \
18 ; RUN: | FileCheck %s -check-prefixes=GP64,GP64R0R1
19 ; RUN: llc < %s -mtriple=mips64 -mcpu=mips64 -relocation-model=pic \
20 ; RUN: | FileCheck %s -check-prefixes=GP64,GP64R0R2
21 ; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r2 -relocation-model=pic \
22 ; RUN: | FileCheck %s -check-prefixes=GP64,GP64R2R5
23 ; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r3 -relocation-model=pic \
24 ; RUN: | FileCheck %s -check-prefixes=GP64,GP64R2R5
25 ; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r5 -relocation-model=pic \
26 ; RUN: | FileCheck %s -check-prefixes=GP64,GP64R2R5
27 ; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r6 -relocation-model=pic \
28 ; RUN: | FileCheck %s -check-prefix=GP64R6
30 ; RUN: llc < %s -mtriple=mips -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic \
31 ; RUN: | FileCheck %s -check-prefix=MMR3
32 ; RUN: llc < %s -mtriple=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic \
33 ; RUN: | FileCheck %s -check-prefix=MMR6
35 define zeroext i1 @udiv_i1(i1 zeroext %a, i1 zeroext %b) {
36 ; GP32-LABEL: udiv_i1:
37 ; GP32: # %bb.0: # %entry
39 ; GP32-NEXT: move $2, $4
41 ; GP32R6-LABEL: udiv_i1:
42 ; GP32R6: # %bb.0: # %entry
44 ; GP32R6-NEXT: move $2, $4
46 ; GP64-LABEL: udiv_i1:
47 ; GP64: # %bb.0: # %entry
49 ; GP64-NEXT: move $2, $4
51 ; GP64R6-LABEL: udiv_i1:
52 ; GP64R6: # %bb.0: # %entry
54 ; GP64R6-NEXT: move $2, $4
56 ; MMR3-LABEL: udiv_i1:
57 ; MMR3: # %bb.0: # %entry
58 ; MMR3-NEXT: move $2, $4
61 ; MMR6-LABEL: udiv_i1:
62 ; MMR6: # %bb.0: # %entry
63 ; MMR6-NEXT: move $2, $4
70 define zeroext i8 @udiv_i8(i8 zeroext %a, i8 zeroext %b) {
71 ; GP32-LABEL: udiv_i8:
72 ; GP32: # %bb.0: # %entry
73 ; GP32-NEXT: divu $zero, $4, $5
74 ; GP32-NEXT: teq $5, $zero, 7
78 ; GP32R6-LABEL: udiv_i8:
79 ; GP32R6: # %bb.0: # %entry
80 ; GP32R6-NEXT: divu $2, $4, $5
81 ; GP32R6-NEXT: teq $5, $zero, 7
82 ; GP32R6-NEXT: jrc $ra
84 ; GP64-LABEL: udiv_i8:
85 ; GP64: # %bb.0: # %entry
86 ; GP64-NEXT: divu $zero, $4, $5
87 ; GP64-NEXT: teq $5, $zero, 7
91 ; GP64R6-LABEL: udiv_i8:
92 ; GP64R6: # %bb.0: # %entry
93 ; GP64R6-NEXT: divu $2, $4, $5
94 ; GP64R6-NEXT: teq $5, $zero, 7
95 ; GP64R6-NEXT: jrc $ra
97 ; MMR3-LABEL: udiv_i8:
98 ; MMR3: # %bb.0: # %entry
99 ; MMR3-NEXT: divu $zero, $4, $5
100 ; MMR3-NEXT: teq $5, $zero, 7
101 ; MMR3-NEXT: mflo16 $2
104 ; MMR6-LABEL: udiv_i8:
105 ; MMR6: # %bb.0: # %entry
106 ; MMR6-NEXT: divu $2, $4, $5
107 ; MMR6-NEXT: teq $5, $zero, 7
114 define zeroext i16 @udiv_i16(i16 zeroext %a, i16 zeroext %b) {
115 ; GP32-LABEL: udiv_i16:
116 ; GP32: # %bb.0: # %entry
117 ; GP32-NEXT: divu $zero, $4, $5
118 ; GP32-NEXT: teq $5, $zero, 7
122 ; GP32R6-LABEL: udiv_i16:
123 ; GP32R6: # %bb.0: # %entry
124 ; GP32R6-NEXT: divu $2, $4, $5
125 ; GP32R6-NEXT: teq $5, $zero, 7
126 ; GP32R6-NEXT: jrc $ra
128 ; GP64-LABEL: udiv_i16:
129 ; GP64: # %bb.0: # %entry
130 ; GP64-NEXT: divu $zero, $4, $5
131 ; GP64-NEXT: teq $5, $zero, 7
135 ; GP64R6-LABEL: udiv_i16:
136 ; GP64R6: # %bb.0: # %entry
137 ; GP64R6-NEXT: divu $2, $4, $5
138 ; GP64R6-NEXT: teq $5, $zero, 7
139 ; GP64R6-NEXT: jrc $ra
141 ; MMR3-LABEL: udiv_i16:
142 ; MMR3: # %bb.0: # %entry
143 ; MMR3-NEXT: divu $zero, $4, $5
144 ; MMR3-NEXT: teq $5, $zero, 7
145 ; MMR3-NEXT: mflo16 $2
148 ; MMR6-LABEL: udiv_i16:
149 ; MMR6: # %bb.0: # %entry
150 ; MMR6-NEXT: divu $2, $4, $5
151 ; MMR6-NEXT: teq $5, $zero, 7
158 define signext i32 @udiv_i32(i32 signext %a, i32 signext %b) {
159 ; GP32-LABEL: udiv_i32:
160 ; GP32: # %bb.0: # %entry
161 ; GP32-NEXT: divu $zero, $4, $5
162 ; GP32-NEXT: teq $5, $zero, 7
166 ; GP32R6-LABEL: udiv_i32:
167 ; GP32R6: # %bb.0: # %entry
168 ; GP32R6-NEXT: divu $2, $4, $5
169 ; GP32R6-NEXT: teq $5, $zero, 7
170 ; GP32R6-NEXT: jrc $ra
172 ; GP64-LABEL: udiv_i32:
173 ; GP64: # %bb.0: # %entry
174 ; GP64-NEXT: divu $zero, $4, $5
175 ; GP64-NEXT: teq $5, $zero, 7
179 ; GP64R6-LABEL: udiv_i32:
180 ; GP64R6: # %bb.0: # %entry
181 ; GP64R6-NEXT: divu $2, $4, $5
182 ; GP64R6-NEXT: teq $5, $zero, 7
183 ; GP64R6-NEXT: jrc $ra
185 ; MMR3-LABEL: udiv_i32:
186 ; MMR3: # %bb.0: # %entry
187 ; MMR3-NEXT: divu $zero, $4, $5
188 ; MMR3-NEXT: teq $5, $zero, 7
189 ; MMR3-NEXT: mflo16 $2
192 ; MMR6-LABEL: udiv_i32:
193 ; MMR6: # %bb.0: # %entry
194 ; MMR6-NEXT: divu $2, $4, $5
195 ; MMR6-NEXT: teq $5, $zero, 7
202 define signext i64 @udiv_i64(i64 signext %a, i64 signext %b) {
203 ; GP32-LABEL: udiv_i64:
204 ; GP32: # %bb.0: # %entry
205 ; GP32-NEXT: lui $2, %hi(_gp_disp)
206 ; GP32-NEXT: addiu $2, $2, %lo(_gp_disp)
207 ; GP32-NEXT: addiu $sp, $sp, -24
208 ; GP32-NEXT: .cfi_def_cfa_offset 24
209 ; GP32-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
210 ; GP32-NEXT: .cfi_offset 31, -4
211 ; GP32-NEXT: addu $gp, $2, $25
212 ; GP32-NEXT: lw $25, %call16(__udivdi3)($gp)
213 ; GP32-NEXT: jalr $25
215 ; GP32-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
217 ; GP32-NEXT: addiu $sp, $sp, 24
219 ; GP32R6-LABEL: udiv_i64:
220 ; GP32R6: # %bb.0: # %entry
221 ; GP32R6-NEXT: lui $2, %hi(_gp_disp)
222 ; GP32R6-NEXT: addiu $2, $2, %lo(_gp_disp)
223 ; GP32R6-NEXT: addiu $sp, $sp, -24
224 ; GP32R6-NEXT: .cfi_def_cfa_offset 24
225 ; GP32R6-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
226 ; GP32R6-NEXT: .cfi_offset 31, -4
227 ; GP32R6-NEXT: addu $gp, $2, $25
228 ; GP32R6-NEXT: lw $25, %call16(__udivdi3)($gp)
229 ; GP32R6-NEXT: jalrc $25
230 ; GP32R6-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
231 ; GP32R6-NEXT: jr $ra
232 ; GP32R6-NEXT: addiu $sp, $sp, 24
234 ; GP64-LABEL: udiv_i64:
235 ; GP64: # %bb.0: # %entry
236 ; GP64-NEXT: ddivu $zero, $4, $5
237 ; GP64-NEXT: teq $5, $zero, 7
241 ; GP64R6-LABEL: udiv_i64:
242 ; GP64R6: # %bb.0: # %entry
243 ; GP64R6-NEXT: ddivu $2, $4, $5
244 ; GP64R6-NEXT: teq $5, $zero, 7
245 ; GP64R6-NEXT: jrc $ra
247 ; MMR3-LABEL: udiv_i64:
248 ; MMR3: # %bb.0: # %entry
249 ; MMR3-NEXT: lui $2, %hi(_gp_disp)
250 ; MMR3-NEXT: addiu $2, $2, %lo(_gp_disp)
251 ; MMR3-NEXT: addiusp -24
252 ; MMR3-NEXT: .cfi_def_cfa_offset 24
253 ; MMR3-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
254 ; MMR3-NEXT: .cfi_offset 31, -4
255 ; MMR3-NEXT: addu $2, $2, $25
256 ; MMR3-NEXT: lw $25, %call16(__udivdi3)($2)
257 ; MMR3-NEXT: move $gp, $2
258 ; MMR3-NEXT: jalr $25
260 ; MMR3-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
261 ; MMR3-NEXT: addiusp 24
264 ; MMR6-LABEL: udiv_i64:
265 ; MMR6: # %bb.0: # %entry
266 ; MMR6-NEXT: lui $2, %hi(_gp_disp)
267 ; MMR6-NEXT: addiu $2, $2, %lo(_gp_disp)
268 ; MMR6-NEXT: addiu $sp, $sp, -24
269 ; MMR6-NEXT: .cfi_def_cfa_offset 24
270 ; MMR6-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
271 ; MMR6-NEXT: .cfi_offset 31, -4
272 ; MMR6-NEXT: addu $2, $2, $25
273 ; MMR6-NEXT: lw $25, %call16(__udivdi3)($2)
274 ; MMR6-NEXT: move $gp, $2
275 ; MMR6-NEXT: jalr $25
276 ; MMR6-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
277 ; MMR6-NEXT: addiu $sp, $sp, 24
284 define signext i128 @udiv_i128(i128 signext %a, i128 signext %b) {
285 ; GP32-LABEL: udiv_i128:
286 ; GP32: # %bb.0: # %entry
287 ; GP32-NEXT: lui $2, %hi(_gp_disp)
288 ; GP32-NEXT: addiu $2, $2, %lo(_gp_disp)
289 ; GP32-NEXT: addiu $sp, $sp, -40
290 ; GP32-NEXT: .cfi_def_cfa_offset 40
291 ; GP32-NEXT: sw $ra, 36($sp) # 4-byte Folded Spill
292 ; GP32-NEXT: .cfi_offset 31, -4
293 ; GP32-NEXT: addu $gp, $2, $25
294 ; GP32-NEXT: lw $1, 60($sp)
295 ; GP32-NEXT: lw $2, 64($sp)
296 ; GP32-NEXT: lw $3, 68($sp)
297 ; GP32-NEXT: sw $3, 28($sp)
298 ; GP32-NEXT: sw $2, 24($sp)
299 ; GP32-NEXT: sw $1, 20($sp)
300 ; GP32-NEXT: lw $1, 56($sp)
301 ; GP32-NEXT: sw $1, 16($sp)
302 ; GP32-NEXT: lw $25, %call16(__udivti3)($gp)
303 ; GP32-NEXT: jalr $25
305 ; GP32-NEXT: lw $ra, 36($sp) # 4-byte Folded Reload
307 ; GP32-NEXT: addiu $sp, $sp, 40
309 ; GP32R6-LABEL: udiv_i128:
310 ; GP32R6: # %bb.0: # %entry
311 ; GP32R6-NEXT: lui $2, %hi(_gp_disp)
312 ; GP32R6-NEXT: addiu $2, $2, %lo(_gp_disp)
313 ; GP32R6-NEXT: addiu $sp, $sp, -40
314 ; GP32R6-NEXT: .cfi_def_cfa_offset 40
315 ; GP32R6-NEXT: sw $ra, 36($sp) # 4-byte Folded Spill
316 ; GP32R6-NEXT: .cfi_offset 31, -4
317 ; GP32R6-NEXT: addu $gp, $2, $25
318 ; GP32R6-NEXT: lw $1, 60($sp)
319 ; GP32R6-NEXT: lw $2, 64($sp)
320 ; GP32R6-NEXT: lw $3, 68($sp)
321 ; GP32R6-NEXT: sw $3, 28($sp)
322 ; GP32R6-NEXT: sw $2, 24($sp)
323 ; GP32R6-NEXT: sw $1, 20($sp)
324 ; GP32R6-NEXT: lw $1, 56($sp)
325 ; GP32R6-NEXT: sw $1, 16($sp)
326 ; GP32R6-NEXT: lw $25, %call16(__udivti3)($gp)
327 ; GP32R6-NEXT: jalrc $25
328 ; GP32R6-NEXT: lw $ra, 36($sp) # 4-byte Folded Reload
329 ; GP32R6-NEXT: jr $ra
330 ; GP32R6-NEXT: addiu $sp, $sp, 40
332 ; GP64-LABEL: udiv_i128:
333 ; GP64: # %bb.0: # %entry
334 ; GP64-NEXT: daddiu $sp, $sp, -16
335 ; GP64-NEXT: .cfi_def_cfa_offset 16
336 ; GP64-NEXT: sd $ra, 8($sp) # 8-byte Folded Spill
337 ; GP64-NEXT: sd $gp, 0($sp) # 8-byte Folded Spill
338 ; GP64-NEXT: .cfi_offset 31, -8
339 ; GP64-NEXT: .cfi_offset 28, -16
340 ; GP64-NEXT: lui $1, %hi(%neg(%gp_rel(udiv_i128)))
341 ; GP64-NEXT: daddu $1, $1, $25
342 ; GP64-NEXT: daddiu $gp, $1, %lo(%neg(%gp_rel(udiv_i128)))
343 ; GP64-NEXT: ld $25, %call16(__udivti3)($gp)
344 ; GP64-NEXT: jalr $25
346 ; GP64-NEXT: ld $gp, 0($sp) # 8-byte Folded Reload
347 ; GP64-NEXT: ld $ra, 8($sp) # 8-byte Folded Reload
349 ; GP64-NEXT: daddiu $sp, $sp, 16
351 ; GP64R6-LABEL: udiv_i128:
352 ; GP64R6: # %bb.0: # %entry
353 ; GP64R6-NEXT: daddiu $sp, $sp, -16
354 ; GP64R6-NEXT: .cfi_def_cfa_offset 16
355 ; GP64R6-NEXT: sd $ra, 8($sp) # 8-byte Folded Spill
356 ; GP64R6-NEXT: sd $gp, 0($sp) # 8-byte Folded Spill
357 ; GP64R6-NEXT: .cfi_offset 31, -8
358 ; GP64R6-NEXT: .cfi_offset 28, -16
359 ; GP64R6-NEXT: lui $1, %hi(%neg(%gp_rel(udiv_i128)))
360 ; GP64R6-NEXT: daddu $1, $1, $25
361 ; GP64R6-NEXT: daddiu $gp, $1, %lo(%neg(%gp_rel(udiv_i128)))
362 ; GP64R6-NEXT: ld $25, %call16(__udivti3)($gp)
363 ; GP64R6-NEXT: jalrc $25
364 ; GP64R6-NEXT: ld $gp, 0($sp) # 8-byte Folded Reload
365 ; GP64R6-NEXT: ld $ra, 8($sp) # 8-byte Folded Reload
366 ; GP64R6-NEXT: jr $ra
367 ; GP64R6-NEXT: daddiu $sp, $sp, 16
369 ; MMR3-LABEL: udiv_i128:
370 ; MMR3: # %bb.0: # %entry
371 ; MMR3-NEXT: lui $2, %hi(_gp_disp)
372 ; MMR3-NEXT: addiu $2, $2, %lo(_gp_disp)
373 ; MMR3-NEXT: addiusp -48
374 ; MMR3-NEXT: .cfi_def_cfa_offset 48
375 ; MMR3-NEXT: sw $ra, 44($sp) # 4-byte Folded Spill
376 ; MMR3-NEXT: swp $16, 36($sp)
377 ; MMR3-NEXT: .cfi_offset 31, -4
378 ; MMR3-NEXT: .cfi_offset 17, -8
379 ; MMR3-NEXT: .cfi_offset 16, -12
380 ; MMR3-NEXT: addu $16, $2, $25
381 ; MMR3-NEXT: move $1, $7
382 ; MMR3-NEXT: lw $7, 68($sp)
383 ; MMR3-NEXT: lw $17, 72($sp)
384 ; MMR3-NEXT: lw $3, 76($sp)
385 ; MMR3-NEXT: move $2, $sp
386 ; MMR3-NEXT: sw16 $3, 28($2)
387 ; MMR3-NEXT: sw16 $17, 24($2)
388 ; MMR3-NEXT: sw16 $7, 20($2)
389 ; MMR3-NEXT: lw $3, 64($sp)
390 ; MMR3-NEXT: sw16 $3, 16($2)
391 ; MMR3-NEXT: lw $25, %call16(__udivti3)($16)
392 ; MMR3-NEXT: move $7, $1
393 ; MMR3-NEXT: move $gp, $16
394 ; MMR3-NEXT: jalr $25
396 ; MMR3-NEXT: lwp $16, 36($sp)
397 ; MMR3-NEXT: lw $ra, 44($sp) # 4-byte Folded Reload
398 ; MMR3-NEXT: addiusp 48
401 ; MMR6-LABEL: udiv_i128:
402 ; MMR6: # %bb.0: # %entry
403 ; MMR6-NEXT: lui $2, %hi(_gp_disp)
404 ; MMR6-NEXT: addiu $2, $2, %lo(_gp_disp)
405 ; MMR6-NEXT: addiu $sp, $sp, -48
406 ; MMR6-NEXT: .cfi_def_cfa_offset 48
407 ; MMR6-NEXT: sw $ra, 44($sp) # 4-byte Folded Spill
408 ; MMR6-NEXT: sw $17, 40($sp) # 4-byte Folded Spill
409 ; MMR6-NEXT: sw $16, 36($sp) # 4-byte Folded Spill
410 ; MMR6-NEXT: .cfi_offset 31, -4
411 ; MMR6-NEXT: .cfi_offset 17, -8
412 ; MMR6-NEXT: .cfi_offset 16, -12
413 ; MMR6-NEXT: addu $16, $2, $25
414 ; MMR6-NEXT: move $1, $7
415 ; MMR6-NEXT: lw $7, 68($sp)
416 ; MMR6-NEXT: lw $17, 72($sp)
417 ; MMR6-NEXT: lw $3, 76($sp)
418 ; MMR6-NEXT: move $2, $sp
419 ; MMR6-NEXT: sw16 $3, 28($2)
420 ; MMR6-NEXT: sw16 $17, 24($2)
421 ; MMR6-NEXT: sw16 $7, 20($2)
422 ; MMR6-NEXT: lw $3, 64($sp)
423 ; MMR6-NEXT: sw16 $3, 16($2)
424 ; MMR6-NEXT: lw $25, %call16(__udivti3)($16)
425 ; MMR6-NEXT: move $7, $1
426 ; MMR6-NEXT: move $gp, $16
427 ; MMR6-NEXT: jalr $25
428 ; MMR6-NEXT: lw $16, 36($sp) # 4-byte Folded Reload
429 ; MMR6-NEXT: lw $17, 40($sp) # 4-byte Folded Reload
430 ; MMR6-NEXT: lw $ra, 44($sp) # 4-byte Folded Reload
431 ; MMR6-NEXT: addiu $sp, $sp, 48
434 %r = udiv i128 %a, %b