1 // RUN: not llvm-mc -triple=thumbv8m.base -show-encoding < %s 2>%t \
2 // RUN: | FileCheck --check-prefix=CHECK-BASELINE --check-prefix=CHECK %s
3 // RUN: FileCheck --check-prefix=UNDEF-BASELINE --check-prefix=UNDEF < %t %s
4 // RUN: not llvm-mc -triple=thumbv8m.main -show-encoding < %s 2>%t \
5 // RUN: | FileCheck --check-prefix=CHECK-MAINLINE --check-prefix=CHECK %s
6 // RUN: FileCheck --check-prefix=UNDEF-MAINLINE --check-prefix=UNDEF < %t %s
7 // RUN: not llvm-mc -triple=thumbv8m.main -mattr=+dsp -show-encoding < %s 2>%t \
8 // RUN: | FileCheck --check-prefix=CHECK-MAINLINE_DSP --check-prefix=CHECK %s
9 // RUN: FileCheck --check-prefix=UNDEF-MAINLINE_DSP --check-prefix=UNDEF < %t %s
11 // Simple check that baseline is v6M and mainline is v7M
12 // UNDEF-BASELINE: error: instruction requires: thumb2
13 // UNDEF-MAINLINE-NOT: error: instruction requires:
14 // UNDEF-MAINLINE_DSP-NOT: error: instruction requires:
17 // Check that .arm is invalid
18 // UNDEF: target does not support ARM mode
21 // And only +dsp has DSP and instructions
22 // UNDEF-BASELINE: error: instruction requires: dsp thumb2
23 // UNDEF-MAINLINE: error: instruction requires: dsp
24 // UNDEF-MAINLINE_DSP-NOT: error: instruction requires:
26 // UNDEF-BASELINE: error: instruction requires: dsp thumb2
27 // UNDEF-MAINLINE: error: instruction requires: dsp
28 // UNDEF-MAINLINE_DSP-NOT: error: instruction requires:
31 // Instruction availibility checks
33 // 'Barrier instructions'
35 // CHECK: isb sy @ encoding: [0xbf,0xf3,0x6f,0x8f]
38 // 'Code optimization'
40 // CHECK: cbz r3, .Ltmp0 @ encoding: [0x03'A',0xb1'A']
41 // CHECK-NEXT: @ fixup A - offset: 0, value: .Ltmp0, kind: fixup_arm_thumb_cb
44 // CHECK: cbnz r3, .Ltmp0 @ encoding: [0x03'A',0xb9'A']
45 // CHECK-NEXT: @ fixup A - offset: 0, value: .Ltmp0, kind: fixup_arm_thumb_cb
48 // CHECK: b.w .Ltmp0 @ encoding: [A,0xf0'A',A,0x90'A']
49 // CHECK-NEXT: @ fixup A - offset: 0, value: .Ltmp0, kind: fixup_t2_uncondbranch
52 // CHECK: sdiv r1, r2, r3 @ encoding: [0x92,0xfb,0xf3,0xf1]
55 // CHECK: udiv r1, r2, r3 @ encoding: [0xb2,0xfb,0xf3,0xf1]
58 // 'Exclusives from ARMv7-M'
60 // CHECK: clrex @ encoding: [0xbf,0xf3,0x2f,0x8f]
63 // CHECK: ldrex r1, [r2, #4] @ encoding: [0x52,0xe8,0x01,0x1f]
66 // CHECK: ldrexb r1, [r2] @ encoding: [0xd2,0xe8,0x4f,0x1f]
69 // CHECK: ldrexh r1, [r2] @ encoding: [0xd2,0xe8,0x5f,0x1f]
72 // UNDEF-BASELINE: error: instruction requires: !armv*m thumb2
73 // UNDEF-MAINLINE: error: instruction requires: !armv*m
76 // CHECK: strex r1, r2, [r3, #4] @ encoding: [0x43,0xe8,0x01,0x21]
77 strex r1, r2, [r3, #4]
79 // CHECK: strexb r1, r2, [r3] @ encoding: [0xc3,0xe8,0x41,0x2f]
82 // CHECK: strexh r1, r2, [r3] @ encoding: [0xc3,0xe8,0x51,0x2f]
85 // UNDEF-BASELINE: error: instruction requires: !armv*m thumb2
86 // UNDEF-MAINLINE: error: instruction requires: !armv*m
87 strexd r0, r1, r2, [r3]
91 // CHECK: movw r1, #65535 @ encoding: [0x4f,0xf6,0xff,0x71]
94 // CHECK: movt r1, #65535 @ encoding: [0xcf,0xf6,0xff,0x71]
97 // 'Acquire/Release from ARMv8-A'
99 // CHECK: lda r1, [r2] @ encoding: [0xd2,0xe8,0xaf,0x1f]
102 // CHECK: ldab r1, [r2] @ encoding: [0xd2,0xe8,0x8f,0x1f]
105 // CHECK: ldah r1, [r2] @ encoding: [0xd2,0xe8,0x9f,0x1f]
108 // CHECK: stl r1, [r3] @ encoding: [0xc3,0xe8,0xaf,0x1f]
111 // CHECK: stlb r1, [r3] @ encoding: [0xc3,0xe8,0x8f,0x1f]
114 // CHECK: stlh r1, [r3] @ encoding: [0xc3,0xe8,0x9f,0x1f]
117 // CHECK: ldaex r1, [r2] @ encoding: [0xd2,0xe8,0xef,0x1f]
120 // CHECK: ldaexb r1, [r2] @ encoding: [0xd2,0xe8,0xcf,0x1f]
123 // CHECK: ldaexh r1, [r2] @ encoding: [0xd2,0xe8,0xdf,0x1f]
126 // UNDEF: error: instruction requires: !armv*m
129 // CHECK: stlex r1, r2, [r3] @ encoding: [0xc3,0xe8,0xe1,0x2f]
132 // CHECK: stlexb r1, r2, [r3] @ encoding: [0xc3,0xe8,0xc1,0x2f]
135 // CHECK: stlexh r1, r2, [r3] @ encoding: [0xc3,0xe8,0xd1,0x2f]
138 // UNDEF: error: instruction requires: !armv*m
139 stlexd r0, r1, r2, [r2]
141 // ARMv8-M Security Extensions
143 // CHECK: sg @ encoding: [0x7f,0xe9,0x7f,0xe9]
146 // CHECK: bxns r0 @ encoding: [0x04,0x47]
149 // UNDEF-BASELINE: error: invalid instruction
150 // UNDEF-BASELINE: error: conditional execution not supported in Thumb1
151 // CHECK-MAINLINE: it eq @ encoding: [0x08,0xbf]
152 // CHECK-MAINLINE: bxnseq r1 @ encoding: [0x0c,0x47]
156 // CHECK: bxns lr @ encoding: [0x74,0x47]
159 // CHECK: blxns r0 @ encoding: [0x84,0x47]
162 // UNDEF-BASELINE: error: invalid instruction
163 // UNDEF-BASELINE: error: conditional execution not supported in Thumb1
164 // CHECK-MAINLINE: it eq @ encoding: [0x08,0xbf]
165 // CHECK-MAINLINE: blxnseq r1 @ encoding: [0x8c,0x47]
169 // CHECK: tt r0, r1 @ encoding: [0x41,0xe8,0x00,0xf0]
172 // CHECK: tt r0, sp @ encoding: [0x4d,0xe8,0x00,0xf0]
175 // CHECK: tta r0, r1 @ encoding: [0x41,0xe8,0x80,0xf0]
178 // CHECK: ttt r0, r1 @ encoding: [0x41,0xe8,0x40,0xf0]
181 // CHECK: ttat r0, r1 @ encoding: [0x41,0xe8,0xc0,0xf0]
184 // 'Lazy Load/Store Multiple'
186 // UNDEF-BASELINE: error: instruction requires: armv8m.main
187 // CHECK-MAINLINE: vlldm r5 @ encoding: [0x35,0xec,0x00,0x0a]
188 // CHECK-MAINLINE_DSP: vlldm r5 @ encoding: [0x35,0xec,0x00,0x0a]
191 // UNDEF-BASELINE: error: instruction requires: armv8m.main
192 // CHECK-MAINLINE: vlstm r10 @ encoding: [0x2a,0xec,0x00,0x0a]
193 // CHECK-MAINLINE_DSP: vlstm r10 @ encoding: [0x2a,0xec,0x00,0x0a]
199 // CHECK: mrs r1, msp_ns @ encoding: [0xef,0xf3,0x88,0x81]
201 // CHECK: msr psp_ns, r2 @ encoding: [0x82,0xf3,0x89,0x88]
203 // CHECK: mrs r3, primask_ns @ encoding: [0xef,0xf3,0x90,0x83]
205 // CHECK: msr control_ns, r4 @ encoding: [0x84,0xf3,0x94,0x88]
207 // CHECK: mrs r5, sp_ns @ encoding: [0xef,0xf3,0x98,0x85]
209 // CHECK: mrs r6, msplim @ encoding: [0xef,0xf3,0x0a,0x86]
211 // CHECK: mrs r7, psplim @ encoding: [0xef,0xf3,0x0b,0x87]
213 // CHECK: msr msplim, r8 @ encoding: [0x88,0xf3,0x0a,0x88]
215 // CHECK: msr psplim, r9 @ encoding: [0x89,0xf3,0x0b,0x88]
218 // CHECK: mrs r10, msplim_ns @ encoding: [0xef,0xf3,0x8a,0x8a]
220 // CHECK: msr psplim_ns, r11 @ encoding: [0x8b,0xf3,0x8b,0x88]
222 // CHECK-MAINLINE: mrs r12, basepri_ns @ encoding: [0xef,0xf3,0x91,0x8c]
223 // UNDEF-BASELINE: error: invalid operand for instruction
224 MSR FAULTMASK_NS, r14
225 // CHECK-MAINLINE: msr faultmask_ns, lr @ encoding: [0x8e,0xf3,0x93,0x88]
226 // UNDEF-BASELINE: error: invalid operand for instruction
228 // Unpredictable SYSm's
230 // CHECK: mrs r8, 146 @ encoding: [0xef,0xf3,0x92,0x88]
232 // CHECK: msr 146, r8 @ encoding: [0x88,0xf3,0x92,0x80]
234 // Invalid operand tests
235 // UNDEF: error: too many operands for instruction
238 // UNDEF: error: too many operands for instruction
241 // UNDEF: error: too many operands for instruction
242 // UNDEF: bxns r0, r1
244 // UNDEF: error: too many operands for instruction
245 // UNDEF: blxns r0, #0
247 // UNDEF: error: operand must be a register in range [r0, r14]
248 // UNDEF: blxns label
250 // UNDEF: error: too many operands for instruction
251 // UNDEF: tt r0, r1, r2
253 // UNDEF: error: operand must be a register in range [r0, r14]
254 // UNDEF: tt r0, [r1]
256 // UNDEF: error: too many operands for instruction
257 // UNDEF: tt r0, r1, #4
259 // UNDEF: error: operand must be a register in range [r0, r14]
263 // Unpredictable operands
264 // UNDEF: error: operand must be a register in range [r0, r14]
267 // UNDEF: error: operand must be a register in range [r0, r12] or r14
270 // UNDEF: error: operand must be a register in range [r0, r12] or r14
273 // UNDEF: error: operand must be a register in range [r0, r14]
277 // UNDEF-BASELINE: error: invalid instruction
278 // UNDEF-MAINLINE: error: operand must be a register in range [r0, r14]
282 // UNDEF-BASELINE: error: invalid instruction
283 // UNDEF-MAINLINE: error: operand must be a register in range [r0, r14]