test/MC/Mips/micromips/valid-fp64.s

   1 # RUN: llvm-mc -arch=mips -mcpu=mips32r3 -mattr=+micromips,+fp64 -show-encoding -show-inst %s \
   2 # RUN: | FileCheck %s
   3
   4 abs.d   $f0, $f12     # CHECK: abs.d  $f0, $f12      # encoding: [0x54,0x0c,0x23,0x7b]
   5                       # CHECK-NEXT:                  # <MCInst #{{[0-9]+}} FABS_D64_MM
   6 abs.s   $f0, $f12     # CHECK: abs.s  $f0, $f12      # encoding: [0x54,0x0c,0x03,0x7b]
   7                       # CHECK-NEXT:                  # <MCInst #{{[0-9]+}} FABS_S_MM
   8 add.d   $f0, $f2, $f4 # CHECK: add.d   $f0, $f2, $f4 # encoding: [0x54,0x82,0x01,0x30]
   9                       # CHECK-NEXT:                  # <MCInst #{{[0-9]+}} FADD_D64_MM
  10 cvt.d.s $f0, $f2      # CHECK: cvt.d.s $f0, $f2      # encoding: [0x54,0x02,0x13,0x7b]
  11                       # CHECK-NEXT:                  # <MCInst #{{[0-9]+}} CVT_D64_S_MM
  12 cvt.d.w $f0, $f2      # CHECK: cvt.d.w $f0, $f2      # encoding: [0x54,0x02,0x33,0x7b]
  13                       # CHECK-NEXT:                  # <MCInst #{{[0-9]+}} CVT_D64_W_MM
  14 cvt.s.d $f0, $f2      # CHECK: cvt.s.d $f0, $f2      # encoding: [0x54,0x02,0x1b,0x7b]
  15                       # CHECK-NEXT:                  # <MCInst #{{[0-9]+}} CVT_S_D64_MM
  16 cvt.w.d $f0, $f2      # CHECK: cvt.w.d $f0, $f2      # encoding: [0x54,0x02,0x49,0x3b]
  17                       # CHECK-NEXT:                  # <MCInst #{{[0-9]+}} CVT_W_D64_MM
  18 cvt.l.s $f4, $f2      # CHECK:  cvt.l.s $f4, $f2     # encoding: [0x54,0x82,0x01,0x3b]
  19                       # CHECK-NEXT:                  # <MCInst #{{[0-9]+}} CVT_L_S_MM
  20 cvt.l.d $f4, $f2      # CHECK:  cvt.l.d $f4, $f2     # encoding: [0x54,0x82,0x41,0x3b]
  21                       # CHECK-NEXT:                  # <MCInst #{{[0-9]+}} CVT_L_D64_MM
  22 div.d   $f0, $f2, $f4 # CHECK: div.d   $f0, $f2, $f4 # encoding: [0x54,0x82,0x01,0xf0]
  23                       # CHECK-NEXT:                  # <MCInst #{{[0-9]+}} FDIV_D64_MM
  24 mfhc1   $4, $f0       # CHECK: mfhc1   $4, $f0       # encoding: [0x54,0x80,0x30,0x3b]
  25                       # CHECK-NEXT:                  # <MCInst #{{[0-9]+}} MFHC1_D64_MM
  26 mov.d   $f0, $f2      # CHECK: mov.d   $f0, $f2      # encoding: [0x54,0x02,0x20,0x7b]
  27                       # CHECK-NEXT:                  # <MCInst #{{[0-9]+}} FMOV_D64_MM
  28 mthc1   $4, $f0       # CHECK: mthc1   $4, $f0       # encoding: [0x54,0x80,0x38,0x3b]
  29                       # CHECK-NEXT:                  # <MCInst #{{[0-9]+}} MTHC1_D64_MM
  30 mul.d   $f0, $f2, $f4 # CHECK: mul.d $f0, $f2, $f4   # encoding: [0x54,0x82,0x01,0xb0]
  31                       # CHECK-NEXT:                  # <MCInst #{{[0-9]+}} FMUL_D64_MM
  32 neg.d   $f0, $f2      # CHECK: neg.d   $f0, $f2      # encoding: [0x54,0x02,0x2b,0x7b]
  33                       # CHECK-NEXT:                  # <MCInst #{{[0-9]+}} FNEG_D64_MM
  34 sqrt.d  $f0, $f12     # CHECK: sqrt.d $f0, $f12      # encoding: [0x54,0x0c,0x4a,0x3b]
  35                       # CHECK-NEXT:                  # <MCInst #{{[0-9]+}} FSQRT_D64_MM
  36 sqrt.s  $f0, $f12     # CHECK: sqrt.s $f0, $f12      # encoding: [0x54,0x0c,0x0a,0x3b]
  37                       # CHECK-NEXT:                  # <MCInst #{{[0-9]+}} FSQRT_S_MM
  38 sub.d   $f0, $f2, $f4 # CHECK: sub.d $f0, $f2, $f4   # encoding: [0x54,0x82,0x01,0x70]
  39                       # CHECK-NEXT:                  # <MCInst #{{[0-9]+}} FSUB_D64_MM