1 //===- InstrInfoEmitter.cpp - Generate a Instruction Set Desc. --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend is responsible for emitting a description of the target
11 // instruction set for the code generator.
13 //===----------------------------------------------------------------------===//
15 #include "CodeGenDAGPatterns.h"
16 #include "CodeGenInstruction.h"
17 #include "CodeGenSchedule.h"
18 #include "CodeGenTarget.h"
19 #include "PredicateExpander.h"
20 #include "SequenceToOffsetTable.h"
21 #include "TableGenBackends.h"
22 #include "llvm/ADT/ArrayRef.h"
23 #include "llvm/ADT/StringExtras.h"
24 #include "llvm/Support/Casting.h"
25 #include "llvm/Support/raw_ostream.h"
26 #include "llvm/TableGen/Error.h"
27 #include "llvm/TableGen/Record.h"
28 #include "llvm/TableGen/TableGenBackend.h"
40 class InstrInfoEmitter {
41 RecordKeeper &Records;
42 CodeGenDAGPatterns CDP;
43 const CodeGenSchedModels &SchedModels;
46 InstrInfoEmitter(RecordKeeper &R):
47 Records(R), CDP(R), SchedModels(CDP.getTargetInfo().getSchedModels()) {}
49 // run - Output the instruction set description.
50 void run(raw_ostream &OS);
53 void emitEnums(raw_ostream &OS);
55 typedef std::map<std::vector<std::string>, unsigned> OperandInfoMapTy;
57 /// The keys of this map are maps which have OpName enum values as their keys
58 /// and instruction operand indices as their values. The values of this map
59 /// are lists of instruction names.
60 typedef std::map<std::map<unsigned, unsigned>,
61 std::vector<std::string>> OpNameMapTy;
62 typedef std::map<std::string, unsigned>::iterator StrUintMapIter;
64 /// Generate member functions in the target-specific GenInstrInfo class.
66 /// This method is used to custom expand TIIPredicate definitions.
67 /// See file llvm/Target/TargetInstPredicates.td for a description of what is
68 /// a TIIPredicate and how to use it.
69 void emitTIIHelperMethods(raw_ostream &OS, StringRef TargetName,
70 bool ExpandDefinition = true);
72 /// Expand TIIPredicate definitions to functions that accept a const MCInst
74 void emitMCIIHelperMethods(raw_ostream &OS, StringRef TargetName);
75 void emitRecord(const CodeGenInstruction &Inst, unsigned Num,
77 std::map<std::vector<Record*>, unsigned> &EL,
78 const OperandInfoMapTy &OpInfo,
80 void emitOperandTypesEnum(raw_ostream &OS, const CodeGenTarget &Target);
81 void initOperandMapData(
82 ArrayRef<const CodeGenInstruction *> NumberedInstructions,
84 std::map<std::string, unsigned> &Operands,
85 OpNameMapTy &OperandMap);
86 void emitOperandNameMappings(raw_ostream &OS, const CodeGenTarget &Target,
87 ArrayRef<const CodeGenInstruction*> NumberedInstructions);
89 // Operand information.
90 void EmitOperandInfo(raw_ostream &OS, OperandInfoMapTy &OperandInfoIDs);
91 std::vector<std::string> GetOperandInfo(const CodeGenInstruction &Inst);
94 } // end anonymous namespace
96 static void PrintDefList(const std::vector<Record*> &Uses,
97 unsigned Num, raw_ostream &OS) {
98 OS << "static const MCPhysReg ImplicitList" << Num << "[] = { ";
99 for (Record *U : Uses)
100 OS << getQualifiedName(U) << ", ";
104 //===----------------------------------------------------------------------===//
105 // Operand Info Emission.
106 //===----------------------------------------------------------------------===//
108 std::vector<std::string>
109 InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) {
110 std::vector<std::string> Result;
112 for (auto &Op : Inst.Operands) {
113 // Handle aggregate operands and normal operands the same way by expanding
114 // either case into a list of operands for this op.
115 std::vector<CGIOperandList::OperandInfo> OperandList;
117 // This might be a multiple operand thing. Targets like X86 have
118 // registers in their multi-operand operands. It may also be an anonymous
119 // operand, which has a single operand, but no declared class for the
121 DagInit *MIOI = Op.MIOperandInfo;
123 if (!MIOI || MIOI->getNumArgs() == 0) {
124 // Single, anonymous, operand.
125 OperandList.push_back(Op);
127 for (unsigned j = 0, e = Op.MINumOperands; j != e; ++j) {
128 OperandList.push_back(Op);
130 auto *OpR = cast<DefInit>(MIOI->getArg(j))->getDef();
131 OperandList.back().Rec = OpR;
135 for (unsigned j = 0, e = OperandList.size(); j != e; ++j) {
136 Record *OpR = OperandList[j].Rec;
139 if (OpR->isSubClassOf("RegisterOperand"))
140 OpR = OpR->getValueAsDef("RegClass");
141 if (OpR->isSubClassOf("RegisterClass"))
142 Res += getQualifiedName(OpR) + "RegClassID, ";
143 else if (OpR->isSubClassOf("PointerLikeRegClass"))
144 Res += utostr(OpR->getValueAsInt("RegClassKind")) + ", ";
146 // -1 means the operand does not have a fixed register class.
149 // Fill in applicable flags.
152 // Ptr value whose register class is resolved via callback.
153 if (OpR->isSubClassOf("PointerLikeRegClass"))
154 Res += "|(1<<MCOI::LookupPtrRegClass)";
156 // Predicate operands. Check to see if the original unexpanded operand
157 // was of type PredicateOp.
158 if (Op.Rec->isSubClassOf("PredicateOp"))
159 Res += "|(1<<MCOI::Predicate)";
161 // Optional def operands. Check to see if the original unexpanded operand
162 // was of type OptionalDefOperand.
163 if (Op.Rec->isSubClassOf("OptionalDefOperand"))
164 Res += "|(1<<MCOI::OptionalDef)";
166 // Fill in operand type.
168 assert(!Op.OperandType.empty() && "Invalid operand type.");
169 Res += Op.OperandType;
171 // Fill in constraint info.
174 const CGIOperandList::ConstraintInfo &Constraint =
176 if (Constraint.isNone())
178 else if (Constraint.isEarlyClobber())
179 Res += "(1 << MCOI::EARLY_CLOBBER)";
181 assert(Constraint.isTied());
182 Res += "((" + utostr(Constraint.getTiedOperand()) +
183 " << 16) | (1 << MCOI::TIED_TO))";
186 Result.push_back(Res);
193 void InstrInfoEmitter::EmitOperandInfo(raw_ostream &OS,
194 OperandInfoMapTy &OperandInfoIDs) {
195 // ID #0 is for no operand info.
196 unsigned OperandListNum = 0;
197 OperandInfoIDs[std::vector<std::string>()] = ++OperandListNum;
200 const CodeGenTarget &Target = CDP.getTargetInfo();
201 for (const CodeGenInstruction *Inst : Target.getInstructionsByEnumValue()) {
202 std::vector<std::string> OperandInfo = GetOperandInfo(*Inst);
203 unsigned &N = OperandInfoIDs[OperandInfo];
204 if (N != 0) continue;
206 N = ++OperandListNum;
207 OS << "static const MCOperandInfo OperandInfo" << N << "[] = { ";
208 for (const std::string &Info : OperandInfo)
209 OS << "{ " << Info << " }, ";
214 /// Initialize data structures for generating operand name mappings.
216 /// \param Operands [out] A map used to generate the OpName enum with operand
217 /// names as its keys and operand enum values as its values.
218 /// \param OperandMap [out] A map for representing the operand name mappings for
219 /// each instructions. This is used to generate the OperandMap table as
220 /// well as the getNamedOperandIdx() function.
221 void InstrInfoEmitter::initOperandMapData(
222 ArrayRef<const CodeGenInstruction *> NumberedInstructions,
224 std::map<std::string, unsigned> &Operands,
225 OpNameMapTy &OperandMap) {
226 unsigned NumOperands = 0;
227 for (const CodeGenInstruction *Inst : NumberedInstructions) {
228 if (!Inst->TheDef->getValueAsBit("UseNamedOperandTable"))
230 std::map<unsigned, unsigned> OpList;
231 for (const auto &Info : Inst->Operands) {
232 StrUintMapIter I = Operands.find(Info.Name);
234 if (I == Operands.end()) {
235 I = Operands.insert(Operands.begin(),
236 std::pair<std::string, unsigned>(Info.Name, NumOperands++));
238 OpList[I->second] = Info.MIOperandNo;
240 OperandMap[OpList].push_back(Namespace.str() + "::" +
241 Inst->TheDef->getName().str());
245 /// Generate a table and function for looking up the indices of operands by
248 /// This code generates:
249 /// - An enum in the llvm::TargetNamespace::OpName namespace, with one entry
250 /// for each operand name.
251 /// - A 2-dimensional table called OperandMap for mapping OpName enum values to
253 /// - A function called getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx)
254 /// for looking up the operand index for an instruction, given a value from
256 void InstrInfoEmitter::emitOperandNameMappings(raw_ostream &OS,
257 const CodeGenTarget &Target,
258 ArrayRef<const CodeGenInstruction*> NumberedInstructions) {
259 StringRef Namespace = Target.getInstNamespace();
260 std::string OpNameNS = "OpName";
261 // Map of operand names to their enumeration value. This will be used to
262 // generate the OpName enum.
263 std::map<std::string, unsigned> Operands;
264 OpNameMapTy OperandMap;
266 initOperandMapData(NumberedInstructions, Namespace, Operands, OperandMap);
268 OS << "#ifdef GET_INSTRINFO_OPERAND_ENUM\n";
269 OS << "#undef GET_INSTRINFO_OPERAND_ENUM\n";
270 OS << "namespace llvm {\n";
271 OS << "namespace " << Namespace << " {\n";
272 OS << "namespace " << OpNameNS << " {\n";
274 for (const auto &Op : Operands)
275 OS << " " << Op.first << " = " << Op.second << ",\n";
277 OS << "OPERAND_LAST";
279 OS << "} // end namespace OpName\n";
280 OS << "} // end namespace " << Namespace << "\n";
281 OS << "} // end namespace llvm\n";
282 OS << "#endif //GET_INSTRINFO_OPERAND_ENUM\n\n";
284 OS << "#ifdef GET_INSTRINFO_NAMED_OPS\n";
285 OS << "#undef GET_INSTRINFO_NAMED_OPS\n";
286 OS << "namespace llvm {\n";
287 OS << "namespace " << Namespace << " {\n";
288 OS << "LLVM_READONLY\n";
289 OS << "int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) {\n";
290 if (!Operands.empty()) {
291 OS << " static const int16_t OperandMap [][" << Operands.size()
293 for (const auto &Entry : OperandMap) {
294 const std::map<unsigned, unsigned> &OpList = Entry.first;
297 // Emit a row of the OperandMap table
298 for (unsigned i = 0, e = Operands.size(); i != e; ++i)
299 OS << (OpList.count(i) == 0 ? -1 : (int)OpList.find(i)->second) << ", ";
305 OS << " switch(Opcode) {\n";
306 unsigned TableIndex = 0;
307 for (const auto &Entry : OperandMap) {
308 for (const std::string &Name : Entry.second)
309 OS << " case " << Name << ":\n";
311 OS << " return OperandMap[" << TableIndex++ << "][NamedIdx];\n";
313 OS << " default: return -1;\n";
316 // There are no operands, so no need to emit anything
317 OS << " return -1;\n";
320 OS << "} // end namespace " << Namespace << "\n";
321 OS << "} // end namespace llvm\n";
322 OS << "#endif //GET_INSTRINFO_NAMED_OPS\n\n";
325 /// Generate an enum for all the operand types for this target, under the
326 /// llvm::TargetNamespace::OpTypes namespace.
327 /// Operand types are all definitions derived of the Operand Target.td class.
328 void InstrInfoEmitter::emitOperandTypesEnum(raw_ostream &OS,
329 const CodeGenTarget &Target) {
331 StringRef Namespace = Target.getInstNamespace();
332 std::vector<Record *> Operands = Records.getAllDerivedDefinitions("Operand");
334 OS << "#ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM\n";
335 OS << "#undef GET_INSTRINFO_OPERAND_TYPES_ENUM\n";
336 OS << "namespace llvm {\n";
337 OS << "namespace " << Namespace << " {\n";
338 OS << "namespace OpTypes {\n";
339 OS << "enum OperandType {\n";
341 unsigned EnumVal = 0;
342 for (const Record *Op : Operands) {
343 if (!Op->isAnonymous())
344 OS << " " << Op->getName() << " = " << EnumVal << ",\n";
348 OS << " OPERAND_TYPE_LIST_END" << "\n};\n";
349 OS << "} // end namespace OpTypes\n";
350 OS << "} // end namespace " << Namespace << "\n";
351 OS << "} // end namespace llvm\n";
352 OS << "#endif // GET_INSTRINFO_OPERAND_TYPES_ENUM\n\n";
355 void InstrInfoEmitter::emitMCIIHelperMethods(raw_ostream &OS,
356 StringRef TargetName) {
357 RecVec TIIPredicates = Records.getAllDerivedDefinitions("TIIPredicate");
358 if (TIIPredicates.empty())
361 OS << "#ifdef GET_INSTRINFO_MC_HELPER_DECLS\n";
362 OS << "#undef GET_INSTRINFO_MC_HELPER_DECLS\n\n";
364 OS << "namespace llvm {\n";
365 OS << "class MCInst;\n\n";
367 OS << "namespace " << TargetName << "_MC {\n\n";
369 for (const Record *Rec : TIIPredicates) {
370 OS << "bool " << Rec->getValueAsString("FunctionName")
371 << "(const MCInst &MI);\n";
374 OS << "\n} // end " << TargetName << "_MC namespace\n";
375 OS << "} // end llvm namespace\n\n";
377 OS << "#endif // GET_INSTRINFO_MC_HELPER_DECLS\n\n";
379 OS << "#ifdef GET_INSTRINFO_MC_HELPERS\n";
380 OS << "#undef GET_INSTRINFO_MC_HELPERS\n\n";
382 OS << "namespace llvm {\n";
383 OS << "namespace " << TargetName << "_MC {\n\n";
385 PredicateExpander PE(TargetName);
386 PE.setExpandForMC(true);
388 for (const Record *Rec : TIIPredicates) {
389 OS << "bool " << Rec->getValueAsString("FunctionName");
390 OS << "(const MCInst &MI) {\n";
392 OS.indent(PE.getIndentLevel() * 2);
393 PE.expandStatement(OS, Rec->getValueAsDef("Body"));
397 OS << "} // end " << TargetName << "_MC namespace\n";
398 OS << "} // end llvm namespace\n\n";
400 OS << "#endif // GET_GENISTRINFO_MC_HELPERS\n";
403 void InstrInfoEmitter::emitTIIHelperMethods(raw_ostream &OS,
404 StringRef TargetName,
405 bool ExpandDefinition) {
406 RecVec TIIPredicates = Records.getAllDerivedDefinitions("TIIPredicate");
407 if (TIIPredicates.empty())
410 PredicateExpander PE(TargetName);
411 PE.setExpandForMC(false);
413 for (const Record *Rec : TIIPredicates) {
414 OS << (ExpandDefinition ? "" : "static ") << "bool ";
415 if (ExpandDefinition)
416 OS << TargetName << "InstrInfo::";
417 OS << Rec->getValueAsString("FunctionName");
418 OS << "(const MachineInstr &MI)";
419 if (!ExpandDefinition) {
425 OS.indent(PE.getIndentLevel() * 2);
426 PE.expandStatement(OS, Rec->getValueAsDef("Body"));
431 //===----------------------------------------------------------------------===//
433 //===----------------------------------------------------------------------===//
435 // run - Emit the main instruction description records for the target...
436 void InstrInfoEmitter::run(raw_ostream &OS) {
437 emitSourceFileHeader("Target Instruction Enum Values and Descriptors", OS);
440 OS << "#ifdef GET_INSTRINFO_MC_DESC\n";
441 OS << "#undef GET_INSTRINFO_MC_DESC\n";
443 OS << "namespace llvm {\n\n";
445 CodeGenTarget &Target = CDP.getTargetInfo();
446 const std::string &TargetName = Target.getName();
447 Record *InstrInfo = Target.getInstructionSet();
449 // Keep track of all of the def lists we have emitted already.
450 std::map<std::vector<Record*>, unsigned> EmittedLists;
451 unsigned ListNumber = 0;
453 // Emit all of the instruction's implicit uses and defs.
454 for (const CodeGenInstruction *II : Target.getInstructionsByEnumValue()) {
455 Record *Inst = II->TheDef;
456 std::vector<Record*> Uses = Inst->getValueAsListOfDefs("Uses");
458 unsigned &IL = EmittedLists[Uses];
459 if (!IL) PrintDefList(Uses, IL = ++ListNumber, OS);
461 std::vector<Record*> Defs = Inst->getValueAsListOfDefs("Defs");
463 unsigned &IL = EmittedLists[Defs];
464 if (!IL) PrintDefList(Defs, IL = ++ListNumber, OS);
468 OperandInfoMapTy OperandInfoIDs;
470 // Emit all of the operand info records.
471 EmitOperandInfo(OS, OperandInfoIDs);
473 // Emit all of the MCInstrDesc records in their ENUM ordering.
475 OS << "\nextern const MCInstrDesc " << TargetName << "Insts[] = {\n";
476 ArrayRef<const CodeGenInstruction*> NumberedInstructions =
477 Target.getInstructionsByEnumValue();
479 SequenceToOffsetTable<std::string> InstrNames;
481 for (const CodeGenInstruction *Inst : NumberedInstructions) {
482 // Keep a list of the instruction names.
483 InstrNames.add(Inst->TheDef->getName());
484 // Emit the record into the table.
485 emitRecord(*Inst, Num++, InstrInfo, EmittedLists, OperandInfoIDs, OS);
489 // Emit the array of instruction names.
491 OS << "extern const char " << TargetName << "InstrNameData[] = {\n";
492 InstrNames.emit(OS, printChar);
495 OS << "extern const unsigned " << TargetName <<"InstrNameIndices[] = {";
497 for (const CodeGenInstruction *Inst : NumberedInstructions) {
498 // Newline every eight entries.
501 OS << InstrNames.get(Inst->TheDef->getName()) << "U, ";
507 // MCInstrInfo initialization routine.
508 OS << "static inline void Init" << TargetName
509 << "MCInstrInfo(MCInstrInfo *II) {\n";
510 OS << " II->InitMCInstrInfo(" << TargetName << "Insts, "
511 << TargetName << "InstrNameIndices, " << TargetName << "InstrNameData, "
512 << NumberedInstructions.size() << ");\n}\n\n";
514 OS << "} // end llvm namespace\n";
516 OS << "#endif // GET_INSTRINFO_MC_DESC\n\n";
518 // Create a TargetInstrInfo subclass to hide the MC layer initialization.
519 OS << "#ifdef GET_INSTRINFO_HEADER\n";
520 OS << "#undef GET_INSTRINFO_HEADER\n";
522 std::string ClassName = TargetName + "GenInstrInfo";
523 OS << "namespace llvm {\n";
524 OS << "struct " << ClassName << " : public TargetInstrInfo {\n"
525 << " explicit " << ClassName
526 << "(int CFSetupOpcode = -1, int CFDestroyOpcode = -1, int CatchRetOpcode = -1, int ReturnOpcode = -1);\n"
527 << " ~" << ClassName << "() override = default;\n";
530 OS << "\n};\n} // end llvm namespace\n";
532 OS << "#endif // GET_INSTRINFO_HEADER\n\n";
534 OS << "#ifdef GET_INSTRINFO_HELPER_DECLS\n";
535 OS << "#undef GET_INSTRINFO_HELPER_DECLS\n\n";
536 emitTIIHelperMethods(OS, TargetName, /* ExpandDefintion = */false);
538 OS << "#endif // GET_INSTRINFO_HELPER_DECLS\n\n";
540 OS << "#ifdef GET_INSTRINFO_HELPERS\n";
541 OS << "#undef GET_INSTRINFO_HELPERS\n\n";
542 emitTIIHelperMethods(OS, TargetName, /* ExpandDefintion = */true);
543 OS << "#endif // GET_INSTRINFO_HELPERS\n\n";
545 OS << "#ifdef GET_INSTRINFO_CTOR_DTOR\n";
546 OS << "#undef GET_INSTRINFO_CTOR_DTOR\n";
548 OS << "namespace llvm {\n";
549 OS << "extern const MCInstrDesc " << TargetName << "Insts[];\n";
550 OS << "extern const unsigned " << TargetName << "InstrNameIndices[];\n";
551 OS << "extern const char " << TargetName << "InstrNameData[];\n";
552 OS << ClassName << "::" << ClassName
553 << "(int CFSetupOpcode, int CFDestroyOpcode, int CatchRetOpcode, int ReturnOpcode)\n"
554 << " : TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {\n"
555 << " InitMCInstrInfo(" << TargetName << "Insts, " << TargetName
556 << "InstrNameIndices, " << TargetName << "InstrNameData, "
557 << NumberedInstructions.size() << ");\n}\n";
558 OS << "} // end llvm namespace\n";
560 OS << "#endif // GET_INSTRINFO_CTOR_DTOR\n\n";
562 emitOperandNameMappings(OS, Target, NumberedInstructions);
564 emitOperandTypesEnum(OS, Target);
566 emitMCIIHelperMethods(OS, TargetName);
569 void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
571 std::map<std::vector<Record*>, unsigned> &EmittedLists,
572 const OperandInfoMapTy &OpInfo,
575 if (!Inst.Operands.empty())
576 // Each logical operand can be multiple MI operands.
577 MinOperands = Inst.Operands.back().MIOperandNo +
578 Inst.Operands.back().MINumOperands;
581 OS << Num << ",\t" << MinOperands << ",\t"
582 << Inst.Operands.NumDefs << ",\t"
583 << Inst.TheDef->getValueAsInt("Size") << ",\t"
584 << SchedModels.getSchedClassIdx(Inst) << ",\t0";
586 CodeGenTarget &Target = CDP.getTargetInfo();
588 // Emit all of the target independent flags...
589 if (Inst.isPseudo) OS << "|(1ULL<<MCID::Pseudo)";
590 if (Inst.isReturn) OS << "|(1ULL<<MCID::Return)";
591 if (Inst.isEHScopeReturn) OS << "|(1ULL<<MCID::EHScopeReturn)";
592 if (Inst.isBranch) OS << "|(1ULL<<MCID::Branch)";
593 if (Inst.isIndirectBranch) OS << "|(1ULL<<MCID::IndirectBranch)";
594 if (Inst.isCompare) OS << "|(1ULL<<MCID::Compare)";
595 if (Inst.isMoveImm) OS << "|(1ULL<<MCID::MoveImm)";
596 if (Inst.isMoveReg) OS << "|(1ULL<<MCID::MoveReg)";
597 if (Inst.isBitcast) OS << "|(1ULL<<MCID::Bitcast)";
598 if (Inst.isAdd) OS << "|(1ULL<<MCID::Add)";
599 if (Inst.isTrap) OS << "|(1ULL<<MCID::Trap)";
600 if (Inst.isSelect) OS << "|(1ULL<<MCID::Select)";
601 if (Inst.isBarrier) OS << "|(1ULL<<MCID::Barrier)";
602 if (Inst.hasDelaySlot) OS << "|(1ULL<<MCID::DelaySlot)";
603 if (Inst.isCall) OS << "|(1ULL<<MCID::Call)";
604 if (Inst.canFoldAsLoad) OS << "|(1ULL<<MCID::FoldableAsLoad)";
605 if (Inst.mayLoad) OS << "|(1ULL<<MCID::MayLoad)";
606 if (Inst.mayStore) OS << "|(1ULL<<MCID::MayStore)";
607 if (Inst.isPredicable) OS << "|(1ULL<<MCID::Predicable)";
608 if (Inst.isConvertibleToThreeAddress) OS << "|(1ULL<<MCID::ConvertibleTo3Addr)";
609 if (Inst.isCommutable) OS << "|(1ULL<<MCID::Commutable)";
610 if (Inst.isTerminator) OS << "|(1ULL<<MCID::Terminator)";
611 if (Inst.isReMaterializable) OS << "|(1ULL<<MCID::Rematerializable)";
612 if (Inst.isNotDuplicable) OS << "|(1ULL<<MCID::NotDuplicable)";
613 if (Inst.Operands.hasOptionalDef) OS << "|(1ULL<<MCID::HasOptionalDef)";
614 if (Inst.usesCustomInserter) OS << "|(1ULL<<MCID::UsesCustomInserter)";
615 if (Inst.hasPostISelHook) OS << "|(1ULL<<MCID::HasPostISelHook)";
616 if (Inst.Operands.isVariadic)OS << "|(1ULL<<MCID::Variadic)";
617 if (Inst.hasSideEffects) OS << "|(1ULL<<MCID::UnmodeledSideEffects)";
618 if (Inst.isAsCheapAsAMove) OS << "|(1ULL<<MCID::CheapAsAMove)";
619 if (!Target.getAllowRegisterRenaming() || Inst.hasExtraSrcRegAllocReq)
620 OS << "|(1ULL<<MCID::ExtraSrcRegAllocReq)";
621 if (!Target.getAllowRegisterRenaming() || Inst.hasExtraDefRegAllocReq)
622 OS << "|(1ULL<<MCID::ExtraDefRegAllocReq)";
623 if (Inst.isRegSequence) OS << "|(1ULL<<MCID::RegSequence)";
624 if (Inst.isExtractSubreg) OS << "|(1ULL<<MCID::ExtractSubreg)";
625 if (Inst.isInsertSubreg) OS << "|(1ULL<<MCID::InsertSubreg)";
626 if (Inst.isConvergent) OS << "|(1ULL<<MCID::Convergent)";
627 if (Inst.variadicOpsAreDefs) OS << "|(1ULL<<MCID::VariadicOpsAreDefs)";
629 // Emit all of the target-specific flags...
630 BitsInit *TSF = Inst.TheDef->getValueAsBitsInit("TSFlags");
632 PrintFatalError("no TSFlags?");
634 for (unsigned i = 0, e = TSF->getNumBits(); i != e; ++i) {
635 if (const auto *Bit = dyn_cast<BitInit>(TSF->getBit(i)))
636 Value |= uint64_t(Bit->getValue()) << i;
638 PrintFatalError("Invalid TSFlags bit in " + Inst.TheDef->getName());
644 // Emit the implicit uses and defs lists...
645 std::vector<Record*> UseList = Inst.TheDef->getValueAsListOfDefs("Uses");
649 OS << "ImplicitList" << EmittedLists[UseList] << ", ";
651 std::vector<Record*> DefList = Inst.TheDef->getValueAsListOfDefs("Defs");
655 OS << "ImplicitList" << EmittedLists[DefList] << ", ";
657 // Emit the operand info.
658 std::vector<std::string> OperandInfo = GetOperandInfo(Inst);
659 if (OperandInfo.empty())
662 OS << "OperandInfo" << OpInfo.find(OperandInfo)->second;
664 if (Inst.HasComplexDeprecationPredicate)
665 // Emit a function pointer to the complex predicate method.
667 << ",&get" << Inst.DeprecatedReason << "DeprecationInfo";
668 else if (!Inst.DeprecatedReason.empty())
669 // Emit the Subtarget feature.
670 OS << ", " << Target.getInstNamespace() << "::" << Inst.DeprecatedReason
673 // Instruction isn't deprecated.
674 OS << ", -1 ,nullptr";
676 OS << " }, // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n";
679 // emitEnums - Print out enum values for all of the instructions.
680 void InstrInfoEmitter::emitEnums(raw_ostream &OS) {
681 OS << "#ifdef GET_INSTRINFO_ENUM\n";
682 OS << "#undef GET_INSTRINFO_ENUM\n";
684 OS << "namespace llvm {\n\n";
686 CodeGenTarget Target(Records);
688 // We must emit the PHI opcode first...
689 StringRef Namespace = Target.getInstNamespace();
691 if (Namespace.empty())
692 PrintFatalError("No instructions defined!");
694 OS << "namespace " << Namespace << " {\n";
697 for (const CodeGenInstruction *Inst : Target.getInstructionsByEnumValue())
698 OS << " " << Inst->TheDef->getName() << "\t= " << Num++ << ",\n";
699 OS << " INSTRUCTION_LIST_END = " << Num << "\n";
701 OS << "} // end " << Namespace << " namespace\n";
702 OS << "} // end llvm namespace\n";
703 OS << "#endif // GET_INSTRINFO_ENUM\n\n";
705 OS << "#ifdef GET_INSTRINFO_SCHED_ENUM\n";
706 OS << "#undef GET_INSTRINFO_SCHED_ENUM\n";
707 OS << "namespace llvm {\n\n";
708 OS << "namespace " << Namespace << " {\n";
709 OS << "namespace Sched {\n";
712 for (const auto &Class : SchedModels.explicit_classes())
713 OS << " " << Class.Name << "\t= " << Num++ << ",\n";
714 OS << " SCHED_LIST_END = " << Num << "\n";
716 OS << "} // end Sched namespace\n";
717 OS << "} // end " << Namespace << " namespace\n";
718 OS << "} // end llvm namespace\n";
720 OS << "#endif // GET_INSTRINFO_SCHED_ENUM\n\n";
725 void EmitInstrInfo(RecordKeeper &RK, raw_ostream &OS) {
726 InstrInfoEmitter(RK).run(OS);
727 EmitMapTable(RK, OS);
730 } // end llvm namespace