1 /* tc-arm.c -- Assemble for the ARM
2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
4 Free Software Foundation, Inc.
5 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
6 Modified by David Taylor (dtaylor@armltd.co.uk)
7 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
8 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
9 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
11 This file is part of GAS, the GNU Assembler.
13 GAS is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 2, or (at your option)
18 GAS is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with GAS; see the file COPYING. If not, write to the Free
25 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
32 #include "safe-ctype.h"
36 #include "opcode/arm.h"
40 #include "dw2gencfi.h"
43 #include "dwarf2dbg.h"
45 #define WARN_DEPRECATED 1
48 /* Must be at least the size of the largest unwind opcode (currently two). */
49 #define ARM_OPCODE_CHUNK_SIZE 8
51 /* This structure holds the unwinding state. */
56 symbolS * table_entry;
57 symbolS * personality_routine;
58 int personality_index;
59 /* The segment containing the function. */
62 /* Opcodes generated from this function. */
63 unsigned char * opcodes;
66 /* The number of bytes pushed to the stack. */
68 /* We don't add stack adjustment opcodes immediately so that we can merge
69 multiple adjustments. We can also omit the final adjustment
70 when using a frame pointer. */
71 offsetT pending_offset;
72 /* These two fields are set by both unwind_movsp and unwind_setfp. They
73 hold the reg+offset to use when restoring sp from a frame pointer. */
76 /* Nonzero if an unwind_setfp directive has been seen. */
78 /* Nonzero if the last opcode restores sp from fp_reg. */
79 unsigned sp_restored:1;
82 /* Bit N indicates that an R_ARM_NONE relocation has been output for
83 __aeabi_unwind_cpp_prN already if set. This enables dependencies to be
84 emitted only once per section, to save unnecessary bloat. */
85 static unsigned int marked_pr_dependency = 0;
89 /* Results from operand parsing worker functions. */
93 PARSE_OPERAND_SUCCESS,
95 PARSE_OPERAND_FAIL_NO_BACKTRACK
96 } parse_operand_result;
101 ARM_FLOAT_ABI_SOFTFP,
105 /* Types of processor to assemble for. */
107 #if defined __XSCALE__
108 #define CPU_DEFAULT ARM_ARCH_XSCALE
110 #if defined __thumb__
111 #define CPU_DEFAULT ARM_ARCH_V5T
118 # define FPU_DEFAULT FPU_ARCH_FPA
119 # elif defined (TE_NetBSD)
121 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
123 /* Legacy a.out format. */
124 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
126 # elif defined (TE_VXWORKS)
127 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
129 /* For backwards compatibility, default to FPA. */
130 # define FPU_DEFAULT FPU_ARCH_FPA
132 #endif /* ifndef FPU_DEFAULT */
134 #define streq(a, b) (strcmp (a, b) == 0)
136 static arm_feature_set cpu_variant;
137 static arm_feature_set arm_arch_used;
138 static arm_feature_set thumb_arch_used;
140 /* Flags stored in private area of BFD structure. */
141 static int uses_apcs_26 = FALSE;
142 static int atpcs = FALSE;
143 static int support_interwork = FALSE;
144 static int uses_apcs_float = FALSE;
145 static int pic_code = FALSE;
147 /* Variables that we set while parsing command-line options. Once all
148 options have been read we re-process these values to set the real
150 static const arm_feature_set *legacy_cpu = NULL;
151 static const arm_feature_set *legacy_fpu = NULL;
153 static const arm_feature_set *mcpu_cpu_opt = NULL;
154 static const arm_feature_set *mcpu_fpu_opt = NULL;
155 static const arm_feature_set *march_cpu_opt = NULL;
156 static const arm_feature_set *march_fpu_opt = NULL;
157 static const arm_feature_set *mfpu_opt = NULL;
158 static const arm_feature_set *object_arch = NULL;
160 /* Constants for known architecture features. */
161 static const arm_feature_set fpu_default = FPU_DEFAULT;
162 static const arm_feature_set fpu_arch_vfp_v1 = FPU_ARCH_VFP_V1;
163 static const arm_feature_set fpu_arch_vfp_v2 = FPU_ARCH_VFP_V2;
164 static const arm_feature_set fpu_arch_vfp_v3 = FPU_ARCH_VFP_V3;
165 static const arm_feature_set fpu_arch_neon_v1 = FPU_ARCH_NEON_V1;
166 static const arm_feature_set fpu_arch_fpa = FPU_ARCH_FPA;
167 static const arm_feature_set fpu_any_hard = FPU_ANY_HARD;
168 static const arm_feature_set fpu_arch_maverick = FPU_ARCH_MAVERICK;
169 static const arm_feature_set fpu_endian_pure = FPU_ARCH_ENDIAN_PURE;
172 static const arm_feature_set cpu_default = CPU_DEFAULT;
175 static const arm_feature_set arm_ext_v1 = ARM_FEATURE (ARM_EXT_V1, 0);
176 static const arm_feature_set arm_ext_v2 = ARM_FEATURE (ARM_EXT_V1, 0);
177 static const arm_feature_set arm_ext_v2s = ARM_FEATURE (ARM_EXT_V2S, 0);
178 static const arm_feature_set arm_ext_v3 = ARM_FEATURE (ARM_EXT_V3, 0);
179 static const arm_feature_set arm_ext_v3m = ARM_FEATURE (ARM_EXT_V3M, 0);
180 static const arm_feature_set arm_ext_v4 = ARM_FEATURE (ARM_EXT_V4, 0);
181 static const arm_feature_set arm_ext_v4t = ARM_FEATURE (ARM_EXT_V4T, 0);
182 static const arm_feature_set arm_ext_v5 = ARM_FEATURE (ARM_EXT_V5, 0);
183 static const arm_feature_set arm_ext_v4t_5 =
184 ARM_FEATURE (ARM_EXT_V4T | ARM_EXT_V5, 0);
185 static const arm_feature_set arm_ext_v5t = ARM_FEATURE (ARM_EXT_V5T, 0);
186 static const arm_feature_set arm_ext_v5e = ARM_FEATURE (ARM_EXT_V5E, 0);
187 static const arm_feature_set arm_ext_v5exp = ARM_FEATURE (ARM_EXT_V5ExP, 0);
188 static const arm_feature_set arm_ext_v5j = ARM_FEATURE (ARM_EXT_V5J, 0);
189 static const arm_feature_set arm_ext_v6 = ARM_FEATURE (ARM_EXT_V6, 0);
190 static const arm_feature_set arm_ext_v6k = ARM_FEATURE (ARM_EXT_V6K, 0);
191 static const arm_feature_set arm_ext_v6z = ARM_FEATURE (ARM_EXT_V6Z, 0);
192 static const arm_feature_set arm_ext_v6t2 = ARM_FEATURE (ARM_EXT_V6T2, 0);
193 static const arm_feature_set arm_ext_v6_notm = ARM_FEATURE (ARM_EXT_V6_NOTM, 0);
194 static const arm_feature_set arm_ext_div = ARM_FEATURE (ARM_EXT_DIV, 0);
195 static const arm_feature_set arm_ext_v7 = ARM_FEATURE (ARM_EXT_V7, 0);
196 static const arm_feature_set arm_ext_v7a = ARM_FEATURE (ARM_EXT_V7A, 0);
197 static const arm_feature_set arm_ext_v7r = ARM_FEATURE (ARM_EXT_V7R, 0);
198 static const arm_feature_set arm_ext_v7m = ARM_FEATURE (ARM_EXT_V7M, 0);
200 static const arm_feature_set arm_arch_any = ARM_ANY;
201 static const arm_feature_set arm_arch_full = ARM_FEATURE (-1, -1);
202 static const arm_feature_set arm_arch_t2 = ARM_ARCH_THUMB2;
203 static const arm_feature_set arm_arch_none = ARM_ARCH_NONE;
205 static const arm_feature_set arm_cext_iwmmxt2 =
206 ARM_FEATURE (0, ARM_CEXT_IWMMXT2);
207 static const arm_feature_set arm_cext_iwmmxt =
208 ARM_FEATURE (0, ARM_CEXT_IWMMXT);
209 static const arm_feature_set arm_cext_xscale =
210 ARM_FEATURE (0, ARM_CEXT_XSCALE);
211 static const arm_feature_set arm_cext_maverick =
212 ARM_FEATURE (0, ARM_CEXT_MAVERICK);
213 static const arm_feature_set fpu_fpa_ext_v1 = ARM_FEATURE (0, FPU_FPA_EXT_V1);
214 static const arm_feature_set fpu_fpa_ext_v2 = ARM_FEATURE (0, FPU_FPA_EXT_V2);
215 static const arm_feature_set fpu_vfp_ext_v1xd =
216 ARM_FEATURE (0, FPU_VFP_EXT_V1xD);
217 static const arm_feature_set fpu_vfp_ext_v1 = ARM_FEATURE (0, FPU_VFP_EXT_V1);
218 static const arm_feature_set fpu_vfp_ext_v2 = ARM_FEATURE (0, FPU_VFP_EXT_V2);
219 static const arm_feature_set fpu_vfp_ext_v3 = ARM_FEATURE (0, FPU_VFP_EXT_V3);
220 static const arm_feature_set fpu_neon_ext_v1 = ARM_FEATURE (0, FPU_NEON_EXT_V1);
221 static const arm_feature_set fpu_vfp_v3_or_neon_ext =
222 ARM_FEATURE (0, FPU_NEON_EXT_V1 | FPU_VFP_EXT_V3);
224 static int mfloat_abi_opt = -1;
225 /* Record user cpu selection for object attributes. */
226 static arm_feature_set selected_cpu = ARM_ARCH_NONE;
227 /* Must be long enough to hold any of the names in arm_cpus. */
228 static char selected_cpu_name[16];
231 static int meabi_flags = EABI_DEFAULT;
233 static int meabi_flags = EF_ARM_EABI_UNKNOWN;
239 return (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4);
244 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
245 symbolS * GOT_symbol;
248 /* 0: assemble for ARM,
249 1: assemble for Thumb,
250 2: assemble for Thumb even though target CPU does not support thumb
252 static int thumb_mode = 0;
254 /* If unified_syntax is true, we are processing the new unified
255 ARM/Thumb syntax. Important differences from the old ARM mode:
257 - Immediate operands do not require a # prefix.
258 - Conditional affixes always appear at the end of the
259 instruction. (For backward compatibility, those instructions
260 that formerly had them in the middle, continue to accept them
262 - The IT instruction may appear, and if it does is validated
263 against subsequent conditional affixes. It does not generate
266 Important differences from the old Thumb mode:
268 - Immediate operands do not require a # prefix.
269 - Most of the V6T2 instructions are only available in unified mode.
270 - The .N and .W suffixes are recognized and honored (it is an error
271 if they cannot be honored).
272 - All instructions set the flags if and only if they have an 's' affix.
273 - Conditional affixes may be used. They are validated against
274 preceding IT instructions. Unlike ARM mode, you cannot use a
275 conditional affix except in the scope of an IT instruction. */
277 static bfd_boolean unified_syntax = FALSE;
292 enum neon_el_type type;
296 #define NEON_MAX_TYPE_ELS 4
300 struct neon_type_el el[NEON_MAX_TYPE_ELS];
307 unsigned long instruction;
311 /* "uncond_value" is set to the value in place of the conditional field in
312 unconditional versions of the instruction, or -1 if nothing is
315 struct neon_type vectype;
316 /* Set to the opcode if the instruction needs relaxation.
317 Zero if the instruction is not relaxed. */
321 bfd_reloc_code_real_type type;
330 struct neon_type_el vectype;
331 unsigned present : 1; /* Operand present. */
332 unsigned isreg : 1; /* Operand was a register. */
333 unsigned immisreg : 1; /* .imm field is a second register. */
334 unsigned isscalar : 1; /* Operand is a (Neon) scalar. */
335 unsigned immisalign : 1; /* Immediate is an alignment specifier. */
336 unsigned immisfloat : 1; /* Immediate was parsed as a float. */
337 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
338 instructions. This allows us to disambiguate ARM <-> vector insns. */
339 unsigned regisimm : 1; /* 64-bit immediate, reg forms high 32 bits. */
340 unsigned isvec : 1; /* Is a single, double or quad VFP/Neon reg. */
341 unsigned isquad : 1; /* Operand is Neon quad-precision register. */
342 unsigned issingle : 1; /* Operand is VFP single-precision register. */
343 unsigned hasreloc : 1; /* Operand has relocation suffix. */
344 unsigned writeback : 1; /* Operand has trailing ! */
345 unsigned preind : 1; /* Preindexed address. */
346 unsigned postind : 1; /* Postindexed address. */
347 unsigned negative : 1; /* Index register was negated. */
348 unsigned shifted : 1; /* Shift applied to operation. */
349 unsigned shift_kind : 3; /* Shift operation (enum shift_kind). */
353 static struct arm_it inst;
355 #define NUM_FLOAT_VALS 8
357 const char * fp_const[] =
359 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
362 /* Number of littlenums required to hold an extended precision number. */
363 #define MAX_LITTLENUMS 6
365 LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS];
375 #define CP_T_X 0x00008000
376 #define CP_T_Y 0x00400000
378 #define CONDS_BIT 0x00100000
379 #define LOAD_BIT 0x00100000
381 #define DOUBLE_LOAD_FLAG 0x00000001
385 const char * template;
389 #define COND_ALWAYS 0xE
393 const char *template;
397 struct asm_barrier_opt
399 const char *template;
403 /* The bit that distinguishes CPSR and SPSR. */
404 #define SPSR_BIT (1 << 22)
406 /* The individual PSR flag bits. */
407 #define PSR_c (1 << 16)
408 #define PSR_x (1 << 17)
409 #define PSR_s (1 << 18)
410 #define PSR_f (1 << 19)
415 bfd_reloc_code_real_type reloc;
420 VFP_REG_Sd, VFP_REG_Sm, VFP_REG_Sn,
421 VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn
426 VFP_LDSTMIA, VFP_LDSTMDB, VFP_LDSTMIAX, VFP_LDSTMDBX
429 /* Bits for DEFINED field in neon_typed_alias. */
430 #define NTA_HASTYPE 1
431 #define NTA_HASINDEX 2
433 struct neon_typed_alias
435 unsigned char defined;
437 struct neon_type_el eltype;
440 /* ARM register categories. This includes coprocessor numbers and various
441 architecture extensions' registers. */
467 /* Structure for a hash table entry for a register.
468 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
469 information which states whether a vector type or index is specified (for a
470 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
474 unsigned char number;
476 unsigned char builtin;
477 struct neon_typed_alias *neon;
480 /* Diagnostics used when we don't get a register of the expected type. */
481 const char *const reg_expected_msgs[] =
483 N_("ARM register expected"),
484 N_("bad or missing co-processor number"),
485 N_("co-processor register expected"),
486 N_("FPA register expected"),
487 N_("VFP single precision register expected"),
488 N_("VFP/Neon double precision register expected"),
489 N_("Neon quad precision register expected"),
490 N_("VFP single or double precision register expected"),
491 N_("Neon double or quad precision register expected"),
492 N_("VFP single, double or Neon quad precision register expected"),
493 N_("VFP system register expected"),
494 N_("Maverick MVF register expected"),
495 N_("Maverick MVD register expected"),
496 N_("Maverick MVFX register expected"),
497 N_("Maverick MVDX register expected"),
498 N_("Maverick MVAX register expected"),
499 N_("Maverick DSPSC register expected"),
500 N_("iWMMXt data register expected"),
501 N_("iWMMXt control register expected"),
502 N_("iWMMXt scalar register expected"),
503 N_("XScale accumulator register expected"),
506 /* Some well known registers that we refer to directly elsewhere. */
511 /* ARM instructions take 4bytes in the object file, Thumb instructions
517 /* Basic string to match. */
518 const char *template;
520 /* Parameters to instruction. */
521 unsigned char operands[8];
523 /* Conditional tag - see opcode_lookup. */
524 unsigned int tag : 4;
526 /* Basic instruction code. */
527 unsigned int avalue : 28;
529 /* Thumb-format instruction code. */
532 /* Which architecture variant provides this instruction. */
533 const arm_feature_set *avariant;
534 const arm_feature_set *tvariant;
536 /* Function to call to encode instruction in ARM format. */
537 void (* aencode) (void);
539 /* Function to call to encode instruction in Thumb format. */
540 void (* tencode) (void);
543 /* Defines for various bits that we will want to toggle. */
544 #define INST_IMMEDIATE 0x02000000
545 #define OFFSET_REG 0x02000000
546 #define HWOFFSET_IMM 0x00400000
547 #define SHIFT_BY_REG 0x00000010
548 #define PRE_INDEX 0x01000000
549 #define INDEX_UP 0x00800000
550 #define WRITE_BACK 0x00200000
551 #define LDM_TYPE_2_OR_3 0x00400000
552 #define CPSI_MMOD 0x00020000
554 #define LITERAL_MASK 0xf000f000
555 #define OPCODE_MASK 0xfe1fffff
556 #define V4_STR_BIT 0x00000020
558 #define T2_SUBS_PC_LR 0xf3de8f00
560 #define DATA_OP_SHIFT 21
562 #define T2_OPCODE_MASK 0xfe1fffff
563 #define T2_DATA_OP_SHIFT 21
565 /* Codes to distinguish the arithmetic instructions. */
576 #define OPCODE_CMP 10
577 #define OPCODE_CMN 11
578 #define OPCODE_ORR 12
579 #define OPCODE_MOV 13
580 #define OPCODE_BIC 14
581 #define OPCODE_MVN 15
583 #define T2_OPCODE_AND 0
584 #define T2_OPCODE_BIC 1
585 #define T2_OPCODE_ORR 2
586 #define T2_OPCODE_ORN 3
587 #define T2_OPCODE_EOR 4
588 #define T2_OPCODE_ADD 8
589 #define T2_OPCODE_ADC 10
590 #define T2_OPCODE_SBC 11
591 #define T2_OPCODE_SUB 13
592 #define T2_OPCODE_RSB 14
594 #define T_OPCODE_MUL 0x4340
595 #define T_OPCODE_TST 0x4200
596 #define T_OPCODE_CMN 0x42c0
597 #define T_OPCODE_NEG 0x4240
598 #define T_OPCODE_MVN 0x43c0
600 #define T_OPCODE_ADD_R3 0x1800
601 #define T_OPCODE_SUB_R3 0x1a00
602 #define T_OPCODE_ADD_HI 0x4400
603 #define T_OPCODE_ADD_ST 0xb000
604 #define T_OPCODE_SUB_ST 0xb080
605 #define T_OPCODE_ADD_SP 0xa800
606 #define T_OPCODE_ADD_PC 0xa000
607 #define T_OPCODE_ADD_I8 0x3000
608 #define T_OPCODE_SUB_I8 0x3800
609 #define T_OPCODE_ADD_I3 0x1c00
610 #define T_OPCODE_SUB_I3 0x1e00
612 #define T_OPCODE_ASR_R 0x4100
613 #define T_OPCODE_LSL_R 0x4080
614 #define T_OPCODE_LSR_R 0x40c0
615 #define T_OPCODE_ROR_R 0x41c0
616 #define T_OPCODE_ASR_I 0x1000
617 #define T_OPCODE_LSL_I 0x0000
618 #define T_OPCODE_LSR_I 0x0800
620 #define T_OPCODE_MOV_I8 0x2000
621 #define T_OPCODE_CMP_I8 0x2800
622 #define T_OPCODE_CMP_LR 0x4280
623 #define T_OPCODE_MOV_HR 0x4600
624 #define T_OPCODE_CMP_HR 0x4500
626 #define T_OPCODE_LDR_PC 0x4800
627 #define T_OPCODE_LDR_SP 0x9800
628 #define T_OPCODE_STR_SP 0x9000
629 #define T_OPCODE_LDR_IW 0x6800
630 #define T_OPCODE_STR_IW 0x6000
631 #define T_OPCODE_LDR_IH 0x8800
632 #define T_OPCODE_STR_IH 0x8000
633 #define T_OPCODE_LDR_IB 0x7800
634 #define T_OPCODE_STR_IB 0x7000
635 #define T_OPCODE_LDR_RW 0x5800
636 #define T_OPCODE_STR_RW 0x5000
637 #define T_OPCODE_LDR_RH 0x5a00
638 #define T_OPCODE_STR_RH 0x5200
639 #define T_OPCODE_LDR_RB 0x5c00
640 #define T_OPCODE_STR_RB 0x5400
642 #define T_OPCODE_PUSH 0xb400
643 #define T_OPCODE_POP 0xbc00
645 #define T_OPCODE_BRANCH 0xe000
647 #define THUMB_SIZE 2 /* Size of thumb instruction. */
648 #define THUMB_PP_PC_LR 0x0100
649 #define THUMB_LOAD_BIT 0x0800
650 #define THUMB2_LOAD_BIT 0x00100000
652 #define BAD_ARGS _("bad arguments to instruction")
653 #define BAD_PC _("r15 not allowed here")
654 #define BAD_SP _("r13 not allowed here")
655 #define BAD_COND _("instruction cannot be conditional")
656 #define BAD_OVERLAP _("registers may not be the same")
657 #define BAD_HIREG _("lo register required")
658 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
659 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
660 #define BAD_BRANCH _("branch must be last instruction in IT block")
661 #define BAD_NOT_IT _("instruction not allowed in IT block")
662 #define BAD_FPU _("selected FPU does not support instruction")
663 #define BAD_VMRS _("APSR_nzcv may only be used with fpscr")
665 static struct hash_control *arm_ops_hsh;
666 static struct hash_control *arm_cond_hsh;
667 static struct hash_control *arm_shift_hsh;
668 static struct hash_control *arm_psr_hsh;
669 static struct hash_control *arm_v7m_psr_hsh;
670 static struct hash_control *arm_reg_hsh;
671 static struct hash_control *arm_reloc_hsh;
672 static struct hash_control *arm_barrier_opt_hsh;
674 /* Stuff needed to resolve the label ambiguity
684 symbolS * last_label_seen;
685 static int label_is_thumb_function_name = FALSE;
687 /* Literal pool structure. Held on a per-section
688 and per-sub-section basis. */
690 #define MAX_LITERAL_POOL_SIZE 1024
691 typedef struct literal_pool
693 expressionS literals [MAX_LITERAL_POOL_SIZE];
694 unsigned int next_free_entry;
699 struct literal_pool * next;
702 /* Pointer to a linked list of literal pools. */
703 literal_pool * list_of_pools = NULL;
705 /* State variables for IT block handling. */
706 static bfd_boolean current_it_mask = 0;
707 static int current_cc;
712 /* This array holds the chars that always start a comment. If the
713 pre-processor is disabled, these aren't very useful. */
714 const char comment_chars[] = "@";
716 /* This array holds the chars that only start a comment at the beginning of
717 a line. If the line seems to have the form '# 123 filename'
718 .line and .file directives will appear in the pre-processed output. */
719 /* Note that input_file.c hand checks for '#' at the beginning of the
720 first line of the input file. This is because the compiler outputs
721 #NO_APP at the beginning of its output. */
722 /* Also note that comments like this one will always work. */
723 const char line_comment_chars[] = "#";
725 const char line_separator_chars[] = ";";
727 /* Chars that can be used to separate mant
728 from exp in floating point numbers. */
729 const char EXP_CHARS[] = "eE";
731 /* Chars that mean this number is a floating point constant. */
735 const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
737 /* Prefix characters that indicate the start of an immediate
739 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
741 /* Separator character handling. */
743 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
746 skip_past_char (char ** str, char c)
756 #define skip_past_comma(str) skip_past_char (str, ',')
758 /* Arithmetic expressions (possibly involving symbols). */
760 /* Return TRUE if anything in the expression is a bignum. */
763 walk_no_bignums (symbolS * sp)
765 if (symbol_get_value_expression (sp)->X_op == O_big)
768 if (symbol_get_value_expression (sp)->X_add_symbol)
770 return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol)
771 || (symbol_get_value_expression (sp)->X_op_symbol
772 && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol)));
778 static int in_my_get_expression = 0;
780 /* Third argument to my_get_expression. */
781 #define GE_NO_PREFIX 0
782 #define GE_IMM_PREFIX 1
783 #define GE_OPT_PREFIX 2
784 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
785 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
786 #define GE_OPT_PREFIX_BIG 3
789 my_get_expression (expressionS * ep, char ** str, int prefix_mode)
794 /* In unified syntax, all prefixes are optional. */
796 prefix_mode = (prefix_mode == GE_OPT_PREFIX_BIG) ? prefix_mode
801 case GE_NO_PREFIX: break;
803 if (!is_immediate_prefix (**str))
805 inst.error = _("immediate expression requires a # prefix");
811 case GE_OPT_PREFIX_BIG:
812 if (is_immediate_prefix (**str))
818 memset (ep, 0, sizeof (expressionS));
820 save_in = input_line_pointer;
821 input_line_pointer = *str;
822 in_my_get_expression = 1;
823 seg = expression (ep);
824 in_my_get_expression = 0;
826 if (ep->X_op == O_illegal)
828 /* We found a bad expression in md_operand(). */
829 *str = input_line_pointer;
830 input_line_pointer = save_in;
831 if (inst.error == NULL)
832 inst.error = _("bad expression");
837 if (seg != absolute_section
838 && seg != text_section
839 && seg != data_section
840 && seg != bss_section
841 && seg != undefined_section)
843 inst.error = _("bad segment");
844 *str = input_line_pointer;
845 input_line_pointer = save_in;
850 /* Get rid of any bignums now, so that we don't generate an error for which
851 we can't establish a line number later on. Big numbers are never valid
852 in instructions, which is where this routine is always called. */
853 if (prefix_mode != GE_OPT_PREFIX_BIG
854 && (ep->X_op == O_big
856 && (walk_no_bignums (ep->X_add_symbol)
858 && walk_no_bignums (ep->X_op_symbol))))))
860 inst.error = _("invalid constant");
861 *str = input_line_pointer;
862 input_line_pointer = save_in;
866 *str = input_line_pointer;
867 input_line_pointer = save_in;
871 /* Turn a string in input_line_pointer into a floating point constant
872 of type TYPE, and store the appropriate bytes in *LITP. The number
873 of LITTLENUMS emitted is stored in *SIZEP. An error message is
874 returned, or NULL on OK.
876 Note that fp constants aren't represent in the normal way on the ARM.
877 In big endian mode, things are as expected. However, in little endian
878 mode fp constants are big-endian word-wise, and little-endian byte-wise
879 within the words. For example, (double) 1.1 in big endian mode is
880 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
881 the byte sequence 99 99 f1 3f 9a 99 99 99.
883 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
886 md_atof (int type, char * litP, int * sizeP)
889 LITTLENUM_TYPE words[MAX_LITTLENUMS];
921 return _("bad call to MD_ATOF()");
924 t = atof_ieee (input_line_pointer, type, words);
926 input_line_pointer = t;
929 if (target_big_endian)
931 for (i = 0; i < prec; i++)
933 md_number_to_chars (litP, (valueT) words[i], 2);
939 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
940 for (i = prec - 1; i >= 0; i--)
942 md_number_to_chars (litP, (valueT) words[i], 2);
946 /* For a 4 byte float the order of elements in `words' is 1 0.
947 For an 8 byte float the order is 1 0 3 2. */
948 for (i = 0; i < prec; i += 2)
950 md_number_to_chars (litP, (valueT) words[i + 1], 2);
951 md_number_to_chars (litP + 2, (valueT) words[i], 2);
959 /* We handle all bad expressions here, so that we can report the faulty
960 instruction in the error message. */
962 md_operand (expressionS * expr)
964 if (in_my_get_expression)
965 expr->X_op = O_illegal;
968 /* Immediate values. */
970 /* Generic immediate-value read function for use in directives.
971 Accepts anything that 'expression' can fold to a constant.
972 *val receives the number. */
975 immediate_for_directive (int *val)
978 exp.X_op = O_illegal;
980 if (is_immediate_prefix (*input_line_pointer))
982 input_line_pointer++;
986 if (exp.X_op != O_constant)
988 as_bad (_("expected #constant"));
989 ignore_rest_of_line ();
992 *val = exp.X_add_number;
997 /* Register parsing. */
999 /* Generic register parser. CCP points to what should be the
1000 beginning of a register name. If it is indeed a valid register
1001 name, advance CCP over it and return the reg_entry structure;
1002 otherwise return NULL. Does not issue diagnostics. */
1004 static struct reg_entry *
1005 arm_reg_parse_multi (char **ccp)
1009 struct reg_entry *reg;
1011 #ifdef REGISTER_PREFIX
1012 if (*start != REGISTER_PREFIX)
1016 #ifdef OPTIONAL_REGISTER_PREFIX
1017 if (*start == OPTIONAL_REGISTER_PREFIX)
1022 if (!ISALPHA (*p) || !is_name_beginner (*p))
1027 while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_');
1029 reg = (struct reg_entry *) hash_find_n (arm_reg_hsh, start, p - start);
1039 arm_reg_alt_syntax (char **ccp, char *start, struct reg_entry *reg,
1040 enum arm_reg_type type)
1042 /* Alternative syntaxes are accepted for a few register classes. */
1049 /* Generic coprocessor register names are allowed for these. */
1050 if (reg && reg->type == REG_TYPE_CN)
1055 /* For backward compatibility, a bare number is valid here. */
1057 unsigned long processor = strtoul (start, ccp, 10);
1058 if (*ccp != start && processor <= 15)
1062 case REG_TYPE_MMXWC:
1063 /* WC includes WCG. ??? I'm not sure this is true for all
1064 instructions that take WC registers. */
1065 if (reg && reg->type == REG_TYPE_MMXWCG)
1076 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1077 return value is the register number or FAIL. */
1080 arm_reg_parse (char **ccp, enum arm_reg_type type)
1083 struct reg_entry *reg = arm_reg_parse_multi (ccp);
1086 /* Do not allow a scalar (reg+index) to parse as a register. */
1087 if (reg && reg->neon && (reg->neon->defined & NTA_HASINDEX))
1090 if (reg && reg->type == type)
1093 if ((ret = arm_reg_alt_syntax (ccp, start, reg, type)) != FAIL)
1100 /* Parse a Neon type specifier. *STR should point at the leading '.'
1101 character. Does no verification at this stage that the type fits the opcode
1108 Can all be legally parsed by this function.
1110 Fills in neon_type struct pointer with parsed information, and updates STR
1111 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1112 type, FAIL if not. */
1115 parse_neon_type (struct neon_type *type, char **str)
1122 while (type->elems < NEON_MAX_TYPE_ELS)
1124 enum neon_el_type thistype = NT_untyped;
1125 unsigned thissize = -1u;
1132 /* Just a size without an explicit type. */
1136 switch (TOLOWER (*ptr))
1138 case 'i': thistype = NT_integer; break;
1139 case 'f': thistype = NT_float; break;
1140 case 'p': thistype = NT_poly; break;
1141 case 's': thistype = NT_signed; break;
1142 case 'u': thistype = NT_unsigned; break;
1144 thistype = NT_float;
1149 as_bad (_("unexpected character `%c' in type specifier"), *ptr);
1155 /* .f is an abbreviation for .f32. */
1156 if (thistype == NT_float && !ISDIGIT (*ptr))
1161 thissize = strtoul (ptr, &ptr, 10);
1163 if (thissize != 8 && thissize != 16 && thissize != 32
1166 as_bad (_("bad size %d in type specifier"), thissize);
1174 type->el[type->elems].type = thistype;
1175 type->el[type->elems].size = thissize;
1180 /* Empty/missing type is not a successful parse. */
1181 if (type->elems == 0)
1189 /* Errors may be set multiple times during parsing or bit encoding
1190 (particularly in the Neon bits), but usually the earliest error which is set
1191 will be the most meaningful. Avoid overwriting it with later (cascading)
1192 errors by calling this function. */
1195 first_error (const char *err)
1201 /* Parse a single type, e.g. ".s32", leading period included. */
1203 parse_neon_operand_type (struct neon_type_el *vectype, char **ccp)
1206 struct neon_type optype;
1210 if (parse_neon_type (&optype, &str) == SUCCESS)
1212 if (optype.elems == 1)
1213 *vectype = optype.el[0];
1216 first_error (_("only one type should be specified for operand"));
1222 first_error (_("vector type expected"));
1234 /* Special meanings for indices (which have a range of 0-7), which will fit into
1237 #define NEON_ALL_LANES 15
1238 #define NEON_INTERLEAVE_LANES 14
1240 /* Parse either a register or a scalar, with an optional type. Return the
1241 register number, and optionally fill in the actual type of the register
1242 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1243 type/index information in *TYPEINFO. */
1246 parse_typed_reg_or_scalar (char **ccp, enum arm_reg_type type,
1247 enum arm_reg_type *rtype,
1248 struct neon_typed_alias *typeinfo)
1251 struct reg_entry *reg = arm_reg_parse_multi (&str);
1252 struct neon_typed_alias atype;
1253 struct neon_type_el parsetype;
1257 atype.eltype.type = NT_invtype;
1258 atype.eltype.size = -1;
1260 /* Try alternate syntax for some types of register. Note these are mutually
1261 exclusive with the Neon syntax extensions. */
1264 int altreg = arm_reg_alt_syntax (&str, *ccp, reg, type);
1272 /* Undo polymorphism when a set of register types may be accepted. */
1273 if ((type == REG_TYPE_NDQ
1274 && (reg->type == REG_TYPE_NQ || reg->type == REG_TYPE_VFD))
1275 || (type == REG_TYPE_VFSD
1276 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD))
1277 || (type == REG_TYPE_NSDQ
1278 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD
1279 || reg->type == REG_TYPE_NQ))
1280 || (type == REG_TYPE_MMXWC
1281 && (reg->type == REG_TYPE_MMXWCG)))
1284 if (type != reg->type)
1290 if (parse_neon_operand_type (&parsetype, &str) == SUCCESS)
1292 if ((atype.defined & NTA_HASTYPE) != 0)
1294 first_error (_("can't redefine type for operand"));
1297 atype.defined |= NTA_HASTYPE;
1298 atype.eltype = parsetype;
1301 if (skip_past_char (&str, '[') == SUCCESS)
1303 if (type != REG_TYPE_VFD)
1305 first_error (_("only D registers may be indexed"));
1309 if ((atype.defined & NTA_HASINDEX) != 0)
1311 first_error (_("can't change index for operand"));
1315 atype.defined |= NTA_HASINDEX;
1317 if (skip_past_char (&str, ']') == SUCCESS)
1318 atype.index = NEON_ALL_LANES;
1323 my_get_expression (&exp, &str, GE_NO_PREFIX);
1325 if (exp.X_op != O_constant)
1327 first_error (_("constant expression required"));
1331 if (skip_past_char (&str, ']') == FAIL)
1334 atype.index = exp.X_add_number;
1349 /* Like arm_reg_parse, but allow allow the following extra features:
1350 - If RTYPE is non-zero, return the (possibly restricted) type of the
1351 register (e.g. Neon double or quad reg when either has been requested).
1352 - If this is a Neon vector type with additional type information, fill
1353 in the struct pointed to by VECTYPE (if non-NULL).
1354 This function will fault on encountering a scalar.
1358 arm_typed_reg_parse (char **ccp, enum arm_reg_type type,
1359 enum arm_reg_type *rtype, struct neon_type_el *vectype)
1361 struct neon_typed_alias atype;
1363 int reg = parse_typed_reg_or_scalar (&str, type, rtype, &atype);
1368 /* Do not allow a scalar (reg+index) to parse as a register. */
1369 if ((atype.defined & NTA_HASINDEX) != 0)
1371 first_error (_("register operand expected, but got scalar"));
1376 *vectype = atype.eltype;
1383 #define NEON_SCALAR_REG(X) ((X) >> 4)
1384 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1386 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1387 have enough information to be able to do a good job bounds-checking. So, we
1388 just do easy checks here, and do further checks later. */
1391 parse_scalar (char **ccp, int elsize, struct neon_type_el *type)
1395 struct neon_typed_alias atype;
1397 reg = parse_typed_reg_or_scalar (&str, REG_TYPE_VFD, NULL, &atype);
1399 if (reg == FAIL || (atype.defined & NTA_HASINDEX) == 0)
1402 if (atype.index == NEON_ALL_LANES)
1404 first_error (_("scalar must have an index"));
1407 else if (atype.index >= 64 / elsize)
1409 first_error (_("scalar index out of range"));
1414 *type = atype.eltype;
1418 return reg * 16 + atype.index;
1421 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1423 parse_reg_list (char ** strp)
1425 char * str = * strp;
1429 /* We come back here if we get ranges concatenated by '+' or '|'. */
1444 if ((reg = arm_reg_parse (&str, REG_TYPE_RN)) == FAIL)
1446 first_error (_(reg_expected_msgs[REG_TYPE_RN]));
1456 first_error (_("bad range in register list"));
1460 for (i = cur_reg + 1; i < reg; i++)
1462 if (range & (1 << i))
1464 (_("Warning: duplicated register (r%d) in register list"),
1472 if (range & (1 << reg))
1473 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1475 else if (reg <= cur_reg)
1476 as_tsktsk (_("Warning: register range not in ascending order"));
1481 while (skip_past_comma (&str) != FAIL
1482 || (in_range = 1, *str++ == '-'));
1487 first_error (_("missing `}'"));
1495 if (my_get_expression (&expr, &str, GE_NO_PREFIX))
1498 if (expr.X_op == O_constant)
1500 if (expr.X_add_number
1501 != (expr.X_add_number & 0x0000ffff))
1503 inst.error = _("invalid register mask");
1507 if ((range & expr.X_add_number) != 0)
1509 int regno = range & expr.X_add_number;
1512 regno = (1 << regno) - 1;
1514 (_("Warning: duplicated register (r%d) in register list"),
1518 range |= expr.X_add_number;
1522 if (inst.reloc.type != 0)
1524 inst.error = _("expression too complex");
1528 memcpy (&inst.reloc.exp, &expr, sizeof (expressionS));
1529 inst.reloc.type = BFD_RELOC_ARM_MULTI;
1530 inst.reloc.pc_rel = 0;
1534 if (*str == '|' || *str == '+')
1540 while (another_range);
1546 /* Types of registers in a list. */
1555 /* Parse a VFP register list. If the string is invalid return FAIL.
1556 Otherwise return the number of registers, and set PBASE to the first
1557 register. Parses registers of type ETYPE.
1558 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1559 - Q registers can be used to specify pairs of D registers
1560 - { } can be omitted from around a singleton register list
1561 FIXME: This is not implemented, as it would require backtracking in
1564 This could be done (the meaning isn't really ambiguous), but doesn't
1565 fit in well with the current parsing framework.
1566 - 32 D registers may be used (also true for VFPv3).
1567 FIXME: Types are ignored in these register lists, which is probably a
1571 parse_vfp_reg_list (char **ccp, unsigned int *pbase, enum reg_list_els etype)
1576 enum arm_reg_type regtype = 0;
1580 unsigned long mask = 0;
1585 inst.error = _("expecting {");
1594 regtype = REG_TYPE_VFS;
1599 regtype = REG_TYPE_VFD;
1602 case REGLIST_NEON_D:
1603 regtype = REG_TYPE_NDQ;
1607 if (etype != REGLIST_VFP_S)
1609 /* VFPv3 allows 32 D registers. */
1610 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v3))
1614 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
1617 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
1624 base_reg = max_regs;
1628 int setmask = 1, addregs = 1;
1630 new_base = arm_typed_reg_parse (&str, regtype, ®type, NULL);
1632 if (new_base == FAIL)
1634 first_error (_(reg_expected_msgs[regtype]));
1638 if (new_base >= max_regs)
1640 first_error (_("register out of range in list"));
1644 /* Note: a value of 2 * n is returned for the register Q<n>. */
1645 if (regtype == REG_TYPE_NQ)
1651 if (new_base < base_reg)
1652 base_reg = new_base;
1654 if (mask & (setmask << new_base))
1656 first_error (_("invalid register list"));
1660 if ((mask >> new_base) != 0 && ! warned)
1662 as_tsktsk (_("register list not in ascending order"));
1666 mask |= setmask << new_base;
1669 if (*str == '-') /* We have the start of a range expression */
1675 if ((high_range = arm_typed_reg_parse (&str, regtype, NULL, NULL))
1678 inst.error = gettext (reg_expected_msgs[regtype]);
1682 if (high_range >= max_regs)
1684 first_error (_("register out of range in list"));
1688 if (regtype == REG_TYPE_NQ)
1689 high_range = high_range + 1;
1691 if (high_range <= new_base)
1693 inst.error = _("register range not in ascending order");
1697 for (new_base += addregs; new_base <= high_range; new_base += addregs)
1699 if (mask & (setmask << new_base))
1701 inst.error = _("invalid register list");
1705 mask |= setmask << new_base;
1710 while (skip_past_comma (&str) != FAIL);
1714 /* Sanity check -- should have raised a parse error above. */
1715 if (count == 0 || count > max_regs)
1720 /* Final test -- the registers must be consecutive. */
1722 for (i = 0; i < count; i++)
1724 if ((mask & (1u << i)) == 0)
1726 inst.error = _("non-contiguous register range");
1736 /* True if two alias types are the same. */
1739 neon_alias_types_same (struct neon_typed_alias *a, struct neon_typed_alias *b)
1747 if (a->defined != b->defined)
1750 if ((a->defined & NTA_HASTYPE) != 0
1751 && (a->eltype.type != b->eltype.type
1752 || a->eltype.size != b->eltype.size))
1755 if ((a->defined & NTA_HASINDEX) != 0
1756 && (a->index != b->index))
1762 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1763 The base register is put in *PBASE.
1764 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1766 The register stride (minus one) is put in bit 4 of the return value.
1767 Bits [6:5] encode the list length (minus one).
1768 The type of the list elements is put in *ELTYPE, if non-NULL. */
1770 #define NEON_LANE(X) ((X) & 0xf)
1771 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1772 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1775 parse_neon_el_struct_list (char **str, unsigned *pbase,
1776 struct neon_type_el *eltype)
1783 int leading_brace = 0;
1784 enum arm_reg_type rtype = REG_TYPE_NDQ;
1786 const char *const incr_error = "register stride must be 1 or 2";
1787 const char *const type_error = "mismatched element/structure types in list";
1788 struct neon_typed_alias firsttype;
1790 if (skip_past_char (&ptr, '{') == SUCCESS)
1795 struct neon_typed_alias atype;
1796 int getreg = parse_typed_reg_or_scalar (&ptr, rtype, &rtype, &atype);
1800 first_error (_(reg_expected_msgs[rtype]));
1807 if (rtype == REG_TYPE_NQ)
1814 else if (reg_incr == -1)
1816 reg_incr = getreg - base_reg;
1817 if (reg_incr < 1 || reg_incr > 2)
1819 first_error (_(incr_error));
1823 else if (getreg != base_reg + reg_incr * count)
1825 first_error (_(incr_error));
1829 if (!neon_alias_types_same (&atype, &firsttype))
1831 first_error (_(type_error));
1835 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
1839 struct neon_typed_alias htype;
1840 int hireg, dregs = (rtype == REG_TYPE_NQ) ? 2 : 1;
1842 lane = NEON_INTERLEAVE_LANES;
1843 else if (lane != NEON_INTERLEAVE_LANES)
1845 first_error (_(type_error));
1850 else if (reg_incr != 1)
1852 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
1856 hireg = parse_typed_reg_or_scalar (&ptr, rtype, NULL, &htype);
1859 first_error (_(reg_expected_msgs[rtype]));
1862 if (!neon_alias_types_same (&htype, &firsttype))
1864 first_error (_(type_error));
1867 count += hireg + dregs - getreg;
1871 /* If we're using Q registers, we can't use [] or [n] syntax. */
1872 if (rtype == REG_TYPE_NQ)
1878 if ((atype.defined & NTA_HASINDEX) != 0)
1882 else if (lane != atype.index)
1884 first_error (_(type_error));
1888 else if (lane == -1)
1889 lane = NEON_INTERLEAVE_LANES;
1890 else if (lane != NEON_INTERLEAVE_LANES)
1892 first_error (_(type_error));
1897 while ((count != 1 || leading_brace) && skip_past_comma (&ptr) != FAIL);
1899 /* No lane set by [x]. We must be interleaving structures. */
1901 lane = NEON_INTERLEAVE_LANES;
1904 if (lane == -1 || base_reg == -1 || count < 1 || count > 4
1905 || (count > 1 && reg_incr == -1))
1907 first_error (_("error parsing element/structure list"));
1911 if ((count > 1 || leading_brace) && skip_past_char (&ptr, '}') == FAIL)
1913 first_error (_("expected }"));
1921 *eltype = firsttype.eltype;
1926 return lane | ((reg_incr - 1) << 4) | ((count - 1) << 5);
1929 /* Parse an explicit relocation suffix on an expression. This is
1930 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
1931 arm_reloc_hsh contains no entries, so this function can only
1932 succeed if there is no () after the word. Returns -1 on error,
1933 BFD_RELOC_UNUSED if there wasn't any suffix. */
1935 parse_reloc (char **str)
1937 struct reloc_entry *r;
1941 return BFD_RELOC_UNUSED;
1946 while (*q && *q != ')' && *q != ',')
1951 if ((r = hash_find_n (arm_reloc_hsh, p, q - p)) == NULL)
1958 /* Directives: register aliases. */
1960 static struct reg_entry *
1961 insert_reg_alias (char *str, int number, int type)
1963 struct reg_entry *new;
1966 if ((new = hash_find (arm_reg_hsh, str)) != 0)
1969 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str);
1971 /* Only warn about a redefinition if it's not defined as the
1973 else if (new->number != number || new->type != type)
1974 as_warn (_("ignoring redefinition of register alias '%s'"), str);
1979 name = xstrdup (str);
1980 new = xmalloc (sizeof (struct reg_entry));
1983 new->number = number;
1985 new->builtin = FALSE;
1988 if (hash_insert (arm_reg_hsh, name, (PTR) new))
1995 insert_neon_reg_alias (char *str, int number, int type,
1996 struct neon_typed_alias *atype)
1998 struct reg_entry *reg = insert_reg_alias (str, number, type);
2002 first_error (_("attempt to redefine typed alias"));
2008 reg->neon = xmalloc (sizeof (struct neon_typed_alias));
2009 *reg->neon = *atype;
2013 /* Look for the .req directive. This is of the form:
2015 new_register_name .req existing_register_name
2017 If we find one, or if it looks sufficiently like one that we want to
2018 handle any error here, return non-zero. Otherwise return zero. */
2021 create_register_alias (char * newname, char *p)
2023 struct reg_entry *old;
2024 char *oldname, *nbuf;
2027 /* The input scrubber ensures that whitespace after the mnemonic is
2028 collapsed to single spaces. */
2030 if (strncmp (oldname, " .req ", 6) != 0)
2034 if (*oldname == '\0')
2037 old = hash_find (arm_reg_hsh, oldname);
2040 as_warn (_("unknown register '%s' -- .req ignored"), oldname);
2044 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2045 the desired alias name, and p points to its end. If not, then
2046 the desired alias name is in the global original_case_string. */
2047 #ifdef TC_CASE_SENSITIVE
2050 newname = original_case_string;
2051 nlen = strlen (newname);
2054 nbuf = alloca (nlen + 1);
2055 memcpy (nbuf, newname, nlen);
2058 /* Create aliases under the new name as stated; an all-lowercase
2059 version of the new name; and an all-uppercase version of the new
2061 insert_reg_alias (nbuf, old->number, old->type);
2063 for (p = nbuf; *p; p++)
2066 if (strncmp (nbuf, newname, nlen))
2067 insert_reg_alias (nbuf, old->number, old->type);
2069 for (p = nbuf; *p; p++)
2072 if (strncmp (nbuf, newname, nlen))
2073 insert_reg_alias (nbuf, old->number, old->type);
2078 /* Create a Neon typed/indexed register alias using directives, e.g.:
2083 These typed registers can be used instead of the types specified after the
2084 Neon mnemonic, so long as all operands given have types. Types can also be
2085 specified directly, e.g.:
2086 vadd d0.s32, d1.s32, d2.s32
2090 create_neon_reg_alias (char *newname, char *p)
2092 enum arm_reg_type basetype;
2093 struct reg_entry *basereg;
2094 struct reg_entry mybasereg;
2095 struct neon_type ntype;
2096 struct neon_typed_alias typeinfo;
2097 char *namebuf, *nameend;
2100 typeinfo.defined = 0;
2101 typeinfo.eltype.type = NT_invtype;
2102 typeinfo.eltype.size = -1;
2103 typeinfo.index = -1;
2107 if (strncmp (p, " .dn ", 5) == 0)
2108 basetype = REG_TYPE_VFD;
2109 else if (strncmp (p, " .qn ", 5) == 0)
2110 basetype = REG_TYPE_NQ;
2119 basereg = arm_reg_parse_multi (&p);
2121 if (basereg && basereg->type != basetype)
2123 as_bad (_("bad type for register"));
2127 if (basereg == NULL)
2130 /* Try parsing as an integer. */
2131 my_get_expression (&exp, &p, GE_NO_PREFIX);
2132 if (exp.X_op != O_constant)
2134 as_bad (_("expression must be constant"));
2137 basereg = &mybasereg;
2138 basereg->number = (basetype == REG_TYPE_NQ) ? exp.X_add_number * 2
2144 typeinfo = *basereg->neon;
2146 if (parse_neon_type (&ntype, &p) == SUCCESS)
2148 /* We got a type. */
2149 if (typeinfo.defined & NTA_HASTYPE)
2151 as_bad (_("can't redefine the type of a register alias"));
2155 typeinfo.defined |= NTA_HASTYPE;
2156 if (ntype.elems != 1)
2158 as_bad (_("you must specify a single type only"));
2161 typeinfo.eltype = ntype.el[0];
2164 if (skip_past_char (&p, '[') == SUCCESS)
2167 /* We got a scalar index. */
2169 if (typeinfo.defined & NTA_HASINDEX)
2171 as_bad (_("can't redefine the index of a scalar alias"));
2175 my_get_expression (&exp, &p, GE_NO_PREFIX);
2177 if (exp.X_op != O_constant)
2179 as_bad (_("scalar index must be constant"));
2183 typeinfo.defined |= NTA_HASINDEX;
2184 typeinfo.index = exp.X_add_number;
2186 if (skip_past_char (&p, ']') == FAIL)
2188 as_bad (_("expecting ]"));
2193 namelen = nameend - newname;
2194 namebuf = alloca (namelen + 1);
2195 strncpy (namebuf, newname, namelen);
2196 namebuf[namelen] = '\0';
2198 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2199 typeinfo.defined != 0 ? &typeinfo : NULL);
2201 /* Insert name in all uppercase. */
2202 for (p = namebuf; *p; p++)
2205 if (strncmp (namebuf, newname, namelen))
2206 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2207 typeinfo.defined != 0 ? &typeinfo : NULL);
2209 /* Insert name in all lowercase. */
2210 for (p = namebuf; *p; p++)
2213 if (strncmp (namebuf, newname, namelen))
2214 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2215 typeinfo.defined != 0 ? &typeinfo : NULL);
2220 /* Should never be called, as .req goes between the alias and the
2221 register name, not at the beginning of the line. */
2223 s_req (int a ATTRIBUTE_UNUSED)
2225 as_bad (_("invalid syntax for .req directive"));
2229 s_dn (int a ATTRIBUTE_UNUSED)
2231 as_bad (_("invalid syntax for .dn directive"));
2235 s_qn (int a ATTRIBUTE_UNUSED)
2237 as_bad (_("invalid syntax for .qn directive"));
2240 /* The .unreq directive deletes an alias which was previously defined
2241 by .req. For example:
2247 s_unreq (int a ATTRIBUTE_UNUSED)
2252 name = input_line_pointer;
2254 while (*input_line_pointer != 0
2255 && *input_line_pointer != ' '
2256 && *input_line_pointer != '\n')
2257 ++input_line_pointer;
2259 saved_char = *input_line_pointer;
2260 *input_line_pointer = 0;
2263 as_bad (_("invalid syntax for .unreq directive"));
2266 struct reg_entry *reg = hash_find (arm_reg_hsh, name);
2269 as_bad (_("unknown register alias '%s'"), name);
2270 else if (reg->builtin)
2271 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
2275 hash_delete (arm_reg_hsh, name);
2276 free ((char *) reg->name);
2283 *input_line_pointer = saved_char;
2284 demand_empty_rest_of_line ();
2287 /* Directives: Instruction set selection. */
2290 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2291 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2292 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2293 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2295 static enum mstate mapstate = MAP_UNDEFINED;
2298 mapping_state (enum mstate state)
2301 const char * symname;
2304 if (mapstate == state)
2305 /* The mapping symbol has already been emitted.
2306 There is nothing else to do. */
2315 type = BSF_NO_FLAGS;
2319 type = BSF_NO_FLAGS;
2323 type = BSF_NO_FLAGS;
2331 seg_info (now_seg)->tc_segment_info_data.mapstate = state;
2333 symbolP = symbol_new (symname, now_seg, (valueT) frag_now_fix (), frag_now);
2334 symbol_table_insert (symbolP);
2335 symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL;
2340 THUMB_SET_FUNC (symbolP, 0);
2341 ARM_SET_THUMB (symbolP, 0);
2342 ARM_SET_INTERWORK (symbolP, support_interwork);
2346 THUMB_SET_FUNC (symbolP, 1);
2347 ARM_SET_THUMB (symbolP, 1);
2348 ARM_SET_INTERWORK (symbolP, support_interwork);
2357 #define mapping_state(x) /* nothing */
2360 /* Find the real, Thumb encoded start of a Thumb function. */
2363 find_real_start (symbolS * symbolP)
2366 const char * name = S_GET_NAME (symbolP);
2367 symbolS * new_target;
2369 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2370 #define STUB_NAME ".real_start_of"
2375 /* The compiler may generate BL instructions to local labels because
2376 it needs to perform a branch to a far away location. These labels
2377 do not have a corresponding ".real_start_of" label. We check
2378 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2379 the ".real_start_of" convention for nonlocal branches. */
2380 if (S_IS_LOCAL (symbolP) || name[0] == '.')
2383 real_start = ACONCAT ((STUB_NAME, name, NULL));
2384 new_target = symbol_find (real_start);
2386 if (new_target == NULL)
2388 as_warn ("Failed to find real start of function: %s\n", name);
2389 new_target = symbolP;
2396 opcode_select (int width)
2403 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
2404 as_bad (_("selected processor does not support THUMB opcodes"));
2407 /* No need to force the alignment, since we will have been
2408 coming from ARM mode, which is word-aligned. */
2409 record_alignment (now_seg, 1);
2411 mapping_state (MAP_THUMB);
2417 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
2418 as_bad (_("selected processor does not support ARM opcodes"));
2423 frag_align (2, 0, 0);
2425 record_alignment (now_seg, 1);
2427 mapping_state (MAP_ARM);
2431 as_bad (_("invalid instruction size selected (%d)"), width);
2436 s_arm (int ignore ATTRIBUTE_UNUSED)
2439 demand_empty_rest_of_line ();
2443 s_thumb (int ignore ATTRIBUTE_UNUSED)
2446 demand_empty_rest_of_line ();
2450 s_code (int unused ATTRIBUTE_UNUSED)
2454 temp = get_absolute_expression ();
2459 opcode_select (temp);
2463 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp);
2468 s_force_thumb (int ignore ATTRIBUTE_UNUSED)
2470 /* If we are not already in thumb mode go into it, EVEN if
2471 the target processor does not support thumb instructions.
2472 This is used by gcc/config/arm/lib1funcs.asm for example
2473 to compile interworking support functions even if the
2474 target processor should not support interworking. */
2478 record_alignment (now_seg, 1);
2481 demand_empty_rest_of_line ();
2485 s_thumb_func (int ignore ATTRIBUTE_UNUSED)
2489 /* The following label is the name/address of the start of a Thumb function.
2490 We need to know this for the interworking support. */
2491 label_is_thumb_function_name = TRUE;
2494 /* Perform a .set directive, but also mark the alias as
2495 being a thumb function. */
2498 s_thumb_set (int equiv)
2500 /* XXX the following is a duplicate of the code for s_set() in read.c
2501 We cannot just call that code as we need to get at the symbol that
2508 /* Especial apologies for the random logic:
2509 This just grew, and could be parsed much more simply!
2511 name = input_line_pointer;
2512 delim = get_symbol_end ();
2513 end_name = input_line_pointer;
2516 if (*input_line_pointer != ',')
2519 as_bad (_("expected comma after name \"%s\""), name);
2521 ignore_rest_of_line ();
2525 input_line_pointer++;
2528 if (name[0] == '.' && name[1] == '\0')
2530 /* XXX - this should not happen to .thumb_set. */
2534 if ((symbolP = symbol_find (name)) == NULL
2535 && (symbolP = md_undefined_symbol (name)) == NULL)
2538 /* When doing symbol listings, play games with dummy fragments living
2539 outside the normal fragment chain to record the file and line info
2541 if (listing & LISTING_SYMBOLS)
2543 extern struct list_info_struct * listing_tail;
2544 fragS * dummy_frag = xmalloc (sizeof (fragS));
2546 memset (dummy_frag, 0, sizeof (fragS));
2547 dummy_frag->fr_type = rs_fill;
2548 dummy_frag->line = listing_tail;
2549 symbolP = symbol_new (name, undefined_section, 0, dummy_frag);
2550 dummy_frag->fr_symbol = symbolP;
2554 symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag);
2557 /* "set" symbols are local unless otherwise specified. */
2558 SF_SET_LOCAL (symbolP);
2559 #endif /* OBJ_COFF */
2560 } /* Make a new symbol. */
2562 symbol_table_insert (symbolP);
2567 && S_IS_DEFINED (symbolP)
2568 && S_GET_SEGMENT (symbolP) != reg_section)
2569 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP));
2571 pseudo_set (symbolP);
2573 demand_empty_rest_of_line ();
2575 /* XXX Now we come to the Thumb specific bit of code. */
2577 THUMB_SET_FUNC (symbolP, 1);
2578 ARM_SET_THUMB (symbolP, 1);
2579 #if defined OBJ_ELF || defined OBJ_COFF
2580 ARM_SET_INTERWORK (symbolP, support_interwork);
2584 /* Directives: Mode selection. */
2586 /* .syntax [unified|divided] - choose the new unified syntax
2587 (same for Arm and Thumb encoding, modulo slight differences in what
2588 can be represented) or the old divergent syntax for each mode. */
2590 s_syntax (int unused ATTRIBUTE_UNUSED)
2594 name = input_line_pointer;
2595 delim = get_symbol_end ();
2597 if (!strcasecmp (name, "unified"))
2598 unified_syntax = TRUE;
2599 else if (!strcasecmp (name, "divided"))
2600 unified_syntax = FALSE;
2603 as_bad (_("unrecognized syntax mode \"%s\""), name);
2606 *input_line_pointer = delim;
2607 demand_empty_rest_of_line ();
2610 /* Directives: sectioning and alignment. */
2612 /* Same as s_align_ptwo but align 0 => align 2. */
2615 s_align (int unused ATTRIBUTE_UNUSED)
2620 long max_alignment = 15;
2622 temp = get_absolute_expression ();
2623 if (temp > max_alignment)
2624 as_bad (_("alignment too large: %d assumed"), temp = max_alignment);
2627 as_bad (_("alignment negative. 0 assumed."));
2631 if (*input_line_pointer == ',')
2633 input_line_pointer++;
2634 temp_fill = get_absolute_expression ();
2646 /* Only make a frag if we HAVE to. */
2647 if (temp && !need_pass_2)
2649 if (!fill_p && subseg_text_p (now_seg))
2650 frag_align_code (temp, 0);
2652 frag_align (temp, (int) temp_fill, 0);
2654 demand_empty_rest_of_line ();
2656 record_alignment (now_seg, temp);
2660 s_bss (int ignore ATTRIBUTE_UNUSED)
2662 /* We don't support putting frags in the BSS segment, we fake it by
2663 marking in_bss, then looking at s_skip for clues. */
2664 subseg_set (bss_section, 0);
2665 demand_empty_rest_of_line ();
2666 mapping_state (MAP_DATA);
2670 s_even (int ignore ATTRIBUTE_UNUSED)
2672 /* Never make frag if expect extra pass. */
2674 frag_align (1, 0, 0);
2676 record_alignment (now_seg, 1);
2678 demand_empty_rest_of_line ();
2681 /* Directives: Literal pools. */
2683 static literal_pool *
2684 find_literal_pool (void)
2686 literal_pool * pool;
2688 for (pool = list_of_pools; pool != NULL; pool = pool->next)
2690 if (pool->section == now_seg
2691 && pool->sub_section == now_subseg)
2698 static literal_pool *
2699 find_or_make_literal_pool (void)
2701 /* Next literal pool ID number. */
2702 static unsigned int latest_pool_num = 1;
2703 literal_pool * pool;
2705 pool = find_literal_pool ();
2709 /* Create a new pool. */
2710 pool = xmalloc (sizeof (* pool));
2714 pool->next_free_entry = 0;
2715 pool->section = now_seg;
2716 pool->sub_section = now_subseg;
2717 pool->next = list_of_pools;
2718 pool->symbol = NULL;
2720 /* Add it to the list. */
2721 list_of_pools = pool;
2724 /* New pools, and emptied pools, will have a NULL symbol. */
2725 if (pool->symbol == NULL)
2727 pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section,
2728 (valueT) 0, &zero_address_frag);
2729 pool->id = latest_pool_num ++;
2736 /* Add the literal in the global 'inst'
2737 structure to the relevent literal pool. */
2740 add_to_lit_pool (void)
2742 literal_pool * pool;
2745 pool = find_or_make_literal_pool ();
2747 /* Check if this literal value is already in the pool. */
2748 for (entry = 0; entry < pool->next_free_entry; entry ++)
2750 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
2751 && (inst.reloc.exp.X_op == O_constant)
2752 && (pool->literals[entry].X_add_number
2753 == inst.reloc.exp.X_add_number)
2754 && (pool->literals[entry].X_unsigned
2755 == inst.reloc.exp.X_unsigned))
2758 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
2759 && (inst.reloc.exp.X_op == O_symbol)
2760 && (pool->literals[entry].X_add_number
2761 == inst.reloc.exp.X_add_number)
2762 && (pool->literals[entry].X_add_symbol
2763 == inst.reloc.exp.X_add_symbol)
2764 && (pool->literals[entry].X_op_symbol
2765 == inst.reloc.exp.X_op_symbol))
2769 /* Do we need to create a new entry? */
2770 if (entry == pool->next_free_entry)
2772 if (entry >= MAX_LITERAL_POOL_SIZE)
2774 inst.error = _("literal pool overflow");
2778 pool->literals[entry] = inst.reloc.exp;
2779 pool->next_free_entry += 1;
2782 inst.reloc.exp.X_op = O_symbol;
2783 inst.reloc.exp.X_add_number = ((int) entry) * 4;
2784 inst.reloc.exp.X_add_symbol = pool->symbol;
2789 /* Can't use symbol_new here, so have to create a symbol and then at
2790 a later date assign it a value. Thats what these functions do. */
2793 symbol_locate (symbolS * symbolP,
2794 const char * name, /* It is copied, the caller can modify. */
2795 segT segment, /* Segment identifier (SEG_<something>). */
2796 valueT valu, /* Symbol value. */
2797 fragS * frag) /* Associated fragment. */
2799 unsigned int name_length;
2800 char * preserved_copy_of_name;
2802 name_length = strlen (name) + 1; /* +1 for \0. */
2803 obstack_grow (¬es, name, name_length);
2804 preserved_copy_of_name = obstack_finish (¬es);
2806 #ifdef tc_canonicalize_symbol_name
2807 preserved_copy_of_name =
2808 tc_canonicalize_symbol_name (preserved_copy_of_name);
2811 S_SET_NAME (symbolP, preserved_copy_of_name);
2813 S_SET_SEGMENT (symbolP, segment);
2814 S_SET_VALUE (symbolP, valu);
2815 symbol_clear_list_pointers (symbolP);
2817 symbol_set_frag (symbolP, frag);
2819 /* Link to end of symbol chain. */
2821 extern int symbol_table_frozen;
2823 if (symbol_table_frozen)
2827 symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP);
2829 obj_symbol_new_hook (symbolP);
2831 #ifdef tc_symbol_new_hook
2832 tc_symbol_new_hook (symbolP);
2836 verify_symbol_chain (symbol_rootP, symbol_lastP);
2837 #endif /* DEBUG_SYMS */
2842 s_ltorg (int ignored ATTRIBUTE_UNUSED)
2845 literal_pool * pool;
2848 pool = find_literal_pool ();
2850 || pool->symbol == NULL
2851 || pool->next_free_entry == 0)
2854 mapping_state (MAP_DATA);
2856 /* Align pool as you have word accesses.
2857 Only make a frag if we have to. */
2859 frag_align (2, 0, 0);
2861 record_alignment (now_seg, 2);
2863 sprintf (sym_name, "$$lit_\002%x", pool->id);
2865 symbol_locate (pool->symbol, sym_name, now_seg,
2866 (valueT) frag_now_fix (), frag_now);
2867 symbol_table_insert (pool->symbol);
2869 ARM_SET_THUMB (pool->symbol, thumb_mode);
2871 #if defined OBJ_COFF || defined OBJ_ELF
2872 ARM_SET_INTERWORK (pool->symbol, support_interwork);
2875 for (entry = 0; entry < pool->next_free_entry; entry ++)
2876 /* First output the expression in the instruction to the pool. */
2877 emit_expr (&(pool->literals[entry]), 4); /* .word */
2879 /* Mark the pool as empty. */
2880 pool->next_free_entry = 0;
2881 pool->symbol = NULL;
2885 /* Forward declarations for functions below, in the MD interface
2887 static void fix_new_arm (fragS *, int, short, expressionS *, int, int);
2888 static valueT create_unwind_entry (int);
2889 static void start_unwind_section (const segT, int);
2890 static void add_unwind_opcode (valueT, int);
2891 static void flush_pending_unwind (void);
2893 /* Directives: Data. */
2896 s_arm_elf_cons (int nbytes)
2900 #ifdef md_flush_pending_output
2901 md_flush_pending_output ();
2904 if (is_it_end_of_statement ())
2906 demand_empty_rest_of_line ();
2910 #ifdef md_cons_align
2911 md_cons_align (nbytes);
2914 mapping_state (MAP_DATA);
2918 char *base = input_line_pointer;
2922 if (exp.X_op != O_symbol)
2923 emit_expr (&exp, (unsigned int) nbytes);
2926 char *before_reloc = input_line_pointer;
2927 reloc = parse_reloc (&input_line_pointer);
2930 as_bad (_("unrecognized relocation suffix"));
2931 ignore_rest_of_line ();
2934 else if (reloc == BFD_RELOC_UNUSED)
2935 emit_expr (&exp, (unsigned int) nbytes);
2938 reloc_howto_type *howto = bfd_reloc_type_lookup (stdoutput, reloc);
2939 int size = bfd_get_reloc_size (howto);
2941 if (reloc == BFD_RELOC_ARM_PLT32)
2943 as_bad (_("(plt) is only valid on branch targets"));
2944 reloc = BFD_RELOC_UNUSED;
2949 as_bad (_("%s relocations do not fit in %d bytes"),
2950 howto->name, nbytes);
2953 /* We've parsed an expression stopping at O_symbol.
2954 But there may be more expression left now that we
2955 have parsed the relocation marker. Parse it again.
2956 XXX Surely there is a cleaner way to do this. */
2957 char *p = input_line_pointer;
2959 char *save_buf = alloca (input_line_pointer - base);
2960 memcpy (save_buf, base, input_line_pointer - base);
2961 memmove (base + (input_line_pointer - before_reloc),
2962 base, before_reloc - base);
2964 input_line_pointer = base + (input_line_pointer-before_reloc);
2966 memcpy (base, save_buf, p - base);
2968 offset = nbytes - size;
2969 p = frag_more ((int) nbytes);
2970 fix_new_exp (frag_now, p - frag_now->fr_literal + offset,
2971 size, &exp, 0, reloc);
2976 while (*input_line_pointer++ == ',');
2978 /* Put terminator back into stream. */
2979 input_line_pointer --;
2980 demand_empty_rest_of_line ();
2984 /* Parse a .rel31 directive. */
2987 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED)
2994 if (*input_line_pointer == '1')
2995 highbit = 0x80000000;
2996 else if (*input_line_pointer != '0')
2997 as_bad (_("expected 0 or 1"));
2999 input_line_pointer++;
3000 if (*input_line_pointer != ',')
3001 as_bad (_("missing comma"));
3002 input_line_pointer++;
3004 #ifdef md_flush_pending_output
3005 md_flush_pending_output ();
3008 #ifdef md_cons_align
3012 mapping_state (MAP_DATA);
3017 md_number_to_chars (p, highbit, 4);
3018 fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 1,
3019 BFD_RELOC_ARM_PREL31);
3021 demand_empty_rest_of_line ();
3024 /* Directives: AEABI stack-unwind tables. */
3026 /* Parse an unwind_fnstart directive. Simply records the current location. */
3029 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED)
3031 demand_empty_rest_of_line ();
3032 /* Mark the start of the function. */
3033 unwind.proc_start = expr_build_dot ();
3035 /* Reset the rest of the unwind info. */
3036 unwind.opcode_count = 0;
3037 unwind.table_entry = NULL;
3038 unwind.personality_routine = NULL;
3039 unwind.personality_index = -1;
3040 unwind.frame_size = 0;
3041 unwind.fp_offset = 0;
3044 unwind.sp_restored = 0;
3048 /* Parse a handlerdata directive. Creates the exception handling table entry
3049 for the function. */
3052 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED)
3054 demand_empty_rest_of_line ();
3055 if (unwind.table_entry)
3056 as_bad (_("dupicate .handlerdata directive"));
3058 create_unwind_entry (1);
3061 /* Parse an unwind_fnend directive. Generates the index table entry. */
3064 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED)
3070 demand_empty_rest_of_line ();
3072 /* Add eh table entry. */
3073 if (unwind.table_entry == NULL)
3074 val = create_unwind_entry (0);
3078 /* Add index table entry. This is two words. */
3079 start_unwind_section (unwind.saved_seg, 1);
3080 frag_align (2, 0, 0);
3081 record_alignment (now_seg, 2);
3083 ptr = frag_more (8);
3085 where = frag_now_fix () - 8;
3087 /* Self relative offset of the function start. */
3088 fix_new (frag_now, where, 4, unwind.proc_start, 0, 1,
3089 BFD_RELOC_ARM_PREL31);
3091 /* Indicate dependency on EHABI-defined personality routines to the
3092 linker, if it hasn't been done already. */
3093 if (unwind.personality_index >= 0 && unwind.personality_index < 3
3094 && !(marked_pr_dependency & (1 << unwind.personality_index)))
3096 static const char *const name[] = {
3097 "__aeabi_unwind_cpp_pr0",
3098 "__aeabi_unwind_cpp_pr1",
3099 "__aeabi_unwind_cpp_pr2"
3101 symbolS *pr = symbol_find_or_make (name[unwind.personality_index]);
3102 fix_new (frag_now, where, 0, pr, 0, 1, BFD_RELOC_NONE);
3103 marked_pr_dependency |= 1 << unwind.personality_index;
3104 seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency
3105 = marked_pr_dependency;
3109 /* Inline exception table entry. */
3110 md_number_to_chars (ptr + 4, val, 4);
3112 /* Self relative offset of the table entry. */
3113 fix_new (frag_now, where + 4, 4, unwind.table_entry, 0, 1,
3114 BFD_RELOC_ARM_PREL31);
3116 /* Restore the original section. */
3117 subseg_set (unwind.saved_seg, unwind.saved_subseg);
3121 /* Parse an unwind_cantunwind directive. */
3124 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED)
3126 demand_empty_rest_of_line ();
3127 if (unwind.personality_routine || unwind.personality_index != -1)
3128 as_bad (_("personality routine specified for cantunwind frame"));
3130 unwind.personality_index = -2;
3134 /* Parse a personalityindex directive. */
3137 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED)
3141 if (unwind.personality_routine || unwind.personality_index != -1)
3142 as_bad (_("duplicate .personalityindex directive"));
3146 if (exp.X_op != O_constant
3147 || exp.X_add_number < 0 || exp.X_add_number > 15)
3149 as_bad (_("bad personality routine number"));
3150 ignore_rest_of_line ();
3154 unwind.personality_index = exp.X_add_number;
3156 demand_empty_rest_of_line ();
3160 /* Parse a personality directive. */
3163 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED)
3167 if (unwind.personality_routine || unwind.personality_index != -1)
3168 as_bad (_("duplicate .personality directive"));
3170 name = input_line_pointer;
3171 c = get_symbol_end ();
3172 p = input_line_pointer;
3173 unwind.personality_routine = symbol_find_or_make (name);
3175 demand_empty_rest_of_line ();
3179 /* Parse a directive saving core registers. */
3182 s_arm_unwind_save_core (void)
3188 range = parse_reg_list (&input_line_pointer);
3191 as_bad (_("expected register list"));
3192 ignore_rest_of_line ();
3196 demand_empty_rest_of_line ();
3198 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3199 into .unwind_save {..., sp...}. We aren't bothered about the value of
3200 ip because it is clobbered by calls. */
3201 if (unwind.sp_restored && unwind.fp_reg == 12
3202 && (range & 0x3000) == 0x1000)
3204 unwind.opcode_count--;
3205 unwind.sp_restored = 0;
3206 range = (range | 0x2000) & ~0x1000;
3207 unwind.pending_offset = 0;
3213 /* See if we can use the short opcodes. These pop a block of up to 8
3214 registers starting with r4, plus maybe r14. */
3215 for (n = 0; n < 8; n++)
3217 /* Break at the first non-saved register. */
3218 if ((range & (1 << (n + 4))) == 0)
3221 /* See if there are any other bits set. */
3222 if (n == 0 || (range & (0xfff0 << n) & 0xbff0) != 0)
3224 /* Use the long form. */
3225 op = 0x8000 | ((range >> 4) & 0xfff);
3226 add_unwind_opcode (op, 2);
3230 /* Use the short form. */
3232 op = 0xa8; /* Pop r14. */
3234 op = 0xa0; /* Do not pop r14. */
3236 add_unwind_opcode (op, 1);
3243 op = 0xb100 | (range & 0xf);
3244 add_unwind_opcode (op, 2);
3247 /* Record the number of bytes pushed. */
3248 for (n = 0; n < 16; n++)
3250 if (range & (1 << n))
3251 unwind.frame_size += 4;
3256 /* Parse a directive saving FPA registers. */
3259 s_arm_unwind_save_fpa (int reg)
3265 /* Get Number of registers to transfer. */
3266 if (skip_past_comma (&input_line_pointer) != FAIL)
3269 exp.X_op = O_illegal;
3271 if (exp.X_op != O_constant)
3273 as_bad (_("expected , <constant>"));
3274 ignore_rest_of_line ();
3278 num_regs = exp.X_add_number;
3280 if (num_regs < 1 || num_regs > 4)
3282 as_bad (_("number of registers must be in the range [1:4]"));
3283 ignore_rest_of_line ();
3287 demand_empty_rest_of_line ();
3292 op = 0xb4 | (num_regs - 1);
3293 add_unwind_opcode (op, 1);
3298 op = 0xc800 | (reg << 4) | (num_regs - 1);
3299 add_unwind_opcode (op, 2);
3301 unwind.frame_size += num_regs * 12;
3305 /* Parse a directive saving VFP registers for ARMv6 and above. */
3308 s_arm_unwind_save_vfp_armv6 (void)
3313 int num_vfpv3_regs = 0;
3314 int num_regs_below_16;
3316 count = parse_vfp_reg_list (&input_line_pointer, &start, REGLIST_VFP_D);
3319 as_bad (_("expected register list"));
3320 ignore_rest_of_line ();
3324 demand_empty_rest_of_line ();
3326 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
3327 than FSTMX/FLDMX-style ones). */
3329 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
3331 num_vfpv3_regs = count;
3332 else if (start + count > 16)
3333 num_vfpv3_regs = start + count - 16;
3335 if (num_vfpv3_regs > 0)
3337 int start_offset = start > 16 ? start - 16 : 0;
3338 op = 0xc800 | (start_offset << 4) | (num_vfpv3_regs - 1);
3339 add_unwind_opcode (op, 2);
3342 /* Generate opcode for registers numbered in the range 0 .. 15. */
3343 num_regs_below_16 = num_vfpv3_regs > 0 ? 16 - (int) start : count;
3344 assert (num_regs_below_16 + num_vfpv3_regs == count);
3345 if (num_regs_below_16 > 0)
3347 op = 0xc900 | (start << 4) | (num_regs_below_16 - 1);
3348 add_unwind_opcode (op, 2);
3351 unwind.frame_size += count * 8;
3355 /* Parse a directive saving VFP registers for pre-ARMv6. */
3358 s_arm_unwind_save_vfp (void)
3364 count = parse_vfp_reg_list (&input_line_pointer, ®, REGLIST_VFP_D);
3367 as_bad (_("expected register list"));
3368 ignore_rest_of_line ();
3372 demand_empty_rest_of_line ();
3377 op = 0xb8 | (count - 1);
3378 add_unwind_opcode (op, 1);
3383 op = 0xb300 | (reg << 4) | (count - 1);
3384 add_unwind_opcode (op, 2);
3386 unwind.frame_size += count * 8 + 4;
3390 /* Parse a directive saving iWMMXt data registers. */
3393 s_arm_unwind_save_mmxwr (void)
3401 if (*input_line_pointer == '{')
3402 input_line_pointer++;
3406 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
3410 as_bad (_(reg_expected_msgs[REG_TYPE_MMXWR]));
3415 as_tsktsk (_("register list not in ascending order"));
3418 if (*input_line_pointer == '-')
3420 input_line_pointer++;
3421 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
3424 as_bad (_(reg_expected_msgs[REG_TYPE_MMXWR]));
3427 else if (reg >= hi_reg)
3429 as_bad (_("bad register range"));
3432 for (; reg < hi_reg; reg++)
3436 while (skip_past_comma (&input_line_pointer) != FAIL);
3438 if (*input_line_pointer == '}')
3439 input_line_pointer++;
3441 demand_empty_rest_of_line ();
3443 /* Generate any deferred opcodes because we're going to be looking at
3445 flush_pending_unwind ();
3447 for (i = 0; i < 16; i++)
3449 if (mask & (1 << i))
3450 unwind.frame_size += 8;
3453 /* Attempt to combine with a previous opcode. We do this because gcc
3454 likes to output separate unwind directives for a single block of
3456 if (unwind.opcode_count > 0)
3458 i = unwind.opcodes[unwind.opcode_count - 1];
3459 if ((i & 0xf8) == 0xc0)
3462 /* Only merge if the blocks are contiguous. */
3465 if ((mask & 0xfe00) == (1 << 9))
3467 mask |= ((1 << (i + 11)) - 1) & 0xfc00;
3468 unwind.opcode_count--;
3471 else if (i == 6 && unwind.opcode_count >= 2)
3473 i = unwind.opcodes[unwind.opcode_count - 2];
3477 op = 0xffff << (reg - 1);
3479 && ((mask & op) == (1u << (reg - 1))))
3481 op = (1 << (reg + i + 1)) - 1;
3482 op &= ~((1 << reg) - 1);
3484 unwind.opcode_count -= 2;
3491 /* We want to generate opcodes in the order the registers have been
3492 saved, ie. descending order. */
3493 for (reg = 15; reg >= -1; reg--)
3495 /* Save registers in blocks. */
3497 || !(mask & (1 << reg)))
3499 /* We found an unsaved reg. Generate opcodes to save the
3500 preceeding block. */
3506 op = 0xc0 | (hi_reg - 10);
3507 add_unwind_opcode (op, 1);
3512 op = 0xc600 | ((reg + 1) << 4) | ((hi_reg - reg) - 1);
3513 add_unwind_opcode (op, 2);
3522 ignore_rest_of_line ();
3526 s_arm_unwind_save_mmxwcg (void)
3533 if (*input_line_pointer == '{')
3534 input_line_pointer++;
3538 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
3542 as_bad (_(reg_expected_msgs[REG_TYPE_MMXWCG]));
3548 as_tsktsk (_("register list not in ascending order"));
3551 if (*input_line_pointer == '-')
3553 input_line_pointer++;
3554 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
3557 as_bad (_(reg_expected_msgs[REG_TYPE_MMXWCG]));
3560 else if (reg >= hi_reg)
3562 as_bad (_("bad register range"));
3565 for (; reg < hi_reg; reg++)
3569 while (skip_past_comma (&input_line_pointer) != FAIL);
3571 if (*input_line_pointer == '}')
3572 input_line_pointer++;
3574 demand_empty_rest_of_line ();
3576 /* Generate any deferred opcodes because we're going to be looking at
3578 flush_pending_unwind ();
3580 for (reg = 0; reg < 16; reg++)
3582 if (mask & (1 << reg))
3583 unwind.frame_size += 4;
3586 add_unwind_opcode (op, 2);
3589 ignore_rest_of_line ();
3593 /* Parse an unwind_save directive.
3594 If the argument is non-zero, this is a .vsave directive. */
3597 s_arm_unwind_save (int arch_v6)
3600 struct reg_entry *reg;
3601 bfd_boolean had_brace = FALSE;
3603 /* Figure out what sort of save we have. */
3604 peek = input_line_pointer;
3612 reg = arm_reg_parse_multi (&peek);
3616 as_bad (_("register expected"));
3617 ignore_rest_of_line ();
3626 as_bad (_("FPA .unwind_save does not take a register list"));
3627 ignore_rest_of_line ();
3630 s_arm_unwind_save_fpa (reg->number);
3633 case REG_TYPE_RN: s_arm_unwind_save_core (); return;
3636 s_arm_unwind_save_vfp_armv6 ();
3638 s_arm_unwind_save_vfp ();
3640 case REG_TYPE_MMXWR: s_arm_unwind_save_mmxwr (); return;
3641 case REG_TYPE_MMXWCG: s_arm_unwind_save_mmxwcg (); return;
3644 as_bad (_(".unwind_save does not support this kind of register"));
3645 ignore_rest_of_line ();
3650 /* Parse an unwind_movsp directive. */
3653 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED)
3659 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
3662 as_bad (_(reg_expected_msgs[REG_TYPE_RN]));
3663 ignore_rest_of_line ();
3667 /* Optional constant. */
3668 if (skip_past_comma (&input_line_pointer) != FAIL)
3670 if (immediate_for_directive (&offset) == FAIL)
3676 demand_empty_rest_of_line ();
3678 if (reg == REG_SP || reg == REG_PC)
3680 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
3684 if (unwind.fp_reg != REG_SP)
3685 as_bad (_("unexpected .unwind_movsp directive"));
3687 /* Generate opcode to restore the value. */
3689 add_unwind_opcode (op, 1);
3691 /* Record the information for later. */
3692 unwind.fp_reg = reg;
3693 unwind.fp_offset = unwind.frame_size - offset;
3694 unwind.sp_restored = 1;
3697 /* Parse an unwind_pad directive. */
3700 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED)
3704 if (immediate_for_directive (&offset) == FAIL)
3709 as_bad (_("stack increment must be multiple of 4"));
3710 ignore_rest_of_line ();
3714 /* Don't generate any opcodes, just record the details for later. */
3715 unwind.frame_size += offset;
3716 unwind.pending_offset += offset;
3718 demand_empty_rest_of_line ();
3721 /* Parse an unwind_setfp directive. */
3724 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED)
3730 fp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
3731 if (skip_past_comma (&input_line_pointer) == FAIL)
3734 sp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
3736 if (fp_reg == FAIL || sp_reg == FAIL)
3738 as_bad (_("expected <reg>, <reg>"));
3739 ignore_rest_of_line ();
3743 /* Optional constant. */
3744 if (skip_past_comma (&input_line_pointer) != FAIL)
3746 if (immediate_for_directive (&offset) == FAIL)
3752 demand_empty_rest_of_line ();
3754 if (sp_reg != 13 && sp_reg != unwind.fp_reg)
3756 as_bad (_("register must be either sp or set by a previous"
3757 "unwind_movsp directive"));
3761 /* Don't generate any opcodes, just record the information for later. */
3762 unwind.fp_reg = fp_reg;
3765 unwind.fp_offset = unwind.frame_size - offset;
3767 unwind.fp_offset -= offset;
3770 /* Parse an unwind_raw directive. */
3773 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED)
3776 /* This is an arbitrary limit. */
3777 unsigned char op[16];
3781 if (exp.X_op == O_constant
3782 && skip_past_comma (&input_line_pointer) != FAIL)
3784 unwind.frame_size += exp.X_add_number;
3788 exp.X_op = O_illegal;
3790 if (exp.X_op != O_constant)
3792 as_bad (_("expected <offset>, <opcode>"));
3793 ignore_rest_of_line ();
3799 /* Parse the opcode. */
3804 as_bad (_("unwind opcode too long"));
3805 ignore_rest_of_line ();
3807 if (exp.X_op != O_constant || exp.X_add_number & ~0xff)
3809 as_bad (_("invalid unwind opcode"));
3810 ignore_rest_of_line ();
3813 op[count++] = exp.X_add_number;
3815 /* Parse the next byte. */
3816 if (skip_past_comma (&input_line_pointer) == FAIL)
3822 /* Add the opcode bytes in reverse order. */
3824 add_unwind_opcode (op[count], 1);
3826 demand_empty_rest_of_line ();
3830 /* Parse a .eabi_attribute directive. */
3833 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED)
3835 s_vendor_attribute (OBJ_ATTR_PROC);
3837 #endif /* OBJ_ELF */
3839 static void s_arm_arch (int);
3840 static void s_arm_object_arch (int);
3841 static void s_arm_cpu (int);
3842 static void s_arm_fpu (int);
3847 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
3854 if (exp.X_op == O_symbol)
3855 exp.X_op = O_secrel;
3857 emit_expr (&exp, 4);
3859 while (*input_line_pointer++ == ',');
3861 input_line_pointer--;
3862 demand_empty_rest_of_line ();
3866 /* This table describes all the machine specific pseudo-ops the assembler
3867 has to support. The fields are:
3868 pseudo-op name without dot
3869 function to call to execute this pseudo-op
3870 Integer arg to pass to the function. */
3872 const pseudo_typeS md_pseudo_table[] =
3874 /* Never called because '.req' does not start a line. */
3875 { "req", s_req, 0 },
3876 /* Following two are likewise never called. */
3879 { "unreq", s_unreq, 0 },
3880 { "bss", s_bss, 0 },
3881 { "align", s_align, 0 },
3882 { "arm", s_arm, 0 },
3883 { "thumb", s_thumb, 0 },
3884 { "code", s_code, 0 },
3885 { "force_thumb", s_force_thumb, 0 },
3886 { "thumb_func", s_thumb_func, 0 },
3887 { "thumb_set", s_thumb_set, 0 },
3888 { "even", s_even, 0 },
3889 { "ltorg", s_ltorg, 0 },
3890 { "pool", s_ltorg, 0 },
3891 { "syntax", s_syntax, 0 },
3892 { "cpu", s_arm_cpu, 0 },
3893 { "arch", s_arm_arch, 0 },
3894 { "object_arch", s_arm_object_arch, 0 },
3895 { "fpu", s_arm_fpu, 0 },
3897 { "word", s_arm_elf_cons, 4 },
3898 { "long", s_arm_elf_cons, 4 },
3899 { "rel31", s_arm_rel31, 0 },
3900 { "fnstart", s_arm_unwind_fnstart, 0 },
3901 { "fnend", s_arm_unwind_fnend, 0 },
3902 { "cantunwind", s_arm_unwind_cantunwind, 0 },
3903 { "personality", s_arm_unwind_personality, 0 },
3904 { "personalityindex", s_arm_unwind_personalityindex, 0 },
3905 { "handlerdata", s_arm_unwind_handlerdata, 0 },
3906 { "save", s_arm_unwind_save, 0 },
3907 { "vsave", s_arm_unwind_save, 1 },
3908 { "movsp", s_arm_unwind_movsp, 0 },
3909 { "pad", s_arm_unwind_pad, 0 },
3910 { "setfp", s_arm_unwind_setfp, 0 },
3911 { "unwind_raw", s_arm_unwind_raw, 0 },
3912 { "eabi_attribute", s_arm_eabi_attribute, 0 },
3916 /* These are used for dwarf. */
3920 /* These are used for dwarf2. */
3921 { "file", (void (*) (int)) dwarf2_directive_file, 0 },
3922 { "loc", dwarf2_directive_loc, 0 },
3923 { "loc_mark_labels", dwarf2_directive_loc_mark_labels, 0 },
3925 { "extend", float_cons, 'x' },
3926 { "ldouble", float_cons, 'x' },
3927 { "packed", float_cons, 'p' },
3929 {"secrel32", pe_directive_secrel, 0},
3934 /* Parser functions used exclusively in instruction operands. */
3936 /* Generic immediate-value read function for use in insn parsing.
3937 STR points to the beginning of the immediate (the leading #);
3938 VAL receives the value; if the value is outside [MIN, MAX]
3939 issue an error. PREFIX_OPT is true if the immediate prefix is
3943 parse_immediate (char **str, int *val, int min, int max,
3944 bfd_boolean prefix_opt)
3947 my_get_expression (&exp, str, prefix_opt ? GE_OPT_PREFIX : GE_IMM_PREFIX);
3948 if (exp.X_op != O_constant)
3950 inst.error = _("constant expression required");
3954 if (exp.X_add_number < min || exp.X_add_number > max)
3956 inst.error = _("immediate value out of range");
3960 *val = exp.X_add_number;
3964 /* Less-generic immediate-value read function with the possibility of loading a
3965 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
3966 instructions. Puts the result directly in inst.operands[i]. */
3969 parse_big_immediate (char **str, int i)
3974 my_get_expression (&exp, &ptr, GE_OPT_PREFIX_BIG);
3976 if (exp.X_op == O_constant)
3978 inst.operands[i].imm = exp.X_add_number & 0xffffffff;
3979 /* If we're on a 64-bit host, then a 64-bit number can be returned using
3980 O_constant. We have to be careful not to break compilation for
3981 32-bit X_add_number, though. */
3982 if ((exp.X_add_number & ~0xffffffffl) != 0)
3984 /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4. */
3985 inst.operands[i].reg = ((exp.X_add_number >> 16) >> 16) & 0xffffffff;
3986 inst.operands[i].regisimm = 1;
3989 else if (exp.X_op == O_big
3990 && LITTLENUM_NUMBER_OF_BITS * exp.X_add_number > 32
3991 && LITTLENUM_NUMBER_OF_BITS * exp.X_add_number <= 64)
3993 unsigned parts = 32 / LITTLENUM_NUMBER_OF_BITS, j, idx = 0;
3994 /* Bignums have their least significant bits in
3995 generic_bignum[0]. Make sure we put 32 bits in imm and
3996 32 bits in reg, in a (hopefully) portable way. */
3997 assert (parts != 0);
3998 inst.operands[i].imm = 0;
3999 for (j = 0; j < parts; j++, idx++)
4000 inst.operands[i].imm |= generic_bignum[idx]
4001 << (LITTLENUM_NUMBER_OF_BITS * j);
4002 inst.operands[i].reg = 0;
4003 for (j = 0; j < parts; j++, idx++)
4004 inst.operands[i].reg |= generic_bignum[idx]
4005 << (LITTLENUM_NUMBER_OF_BITS * j);
4006 inst.operands[i].regisimm = 1;
4016 /* Returns the pseudo-register number of an FPA immediate constant,
4017 or FAIL if there isn't a valid constant here. */
4020 parse_fpa_immediate (char ** str)
4022 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4028 /* First try and match exact strings, this is to guarantee
4029 that some formats will work even for cross assembly. */
4031 for (i = 0; fp_const[i]; i++)
4033 if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0)
4037 *str += strlen (fp_const[i]);
4038 if (is_end_of_line[(unsigned char) **str])
4044 /* Just because we didn't get a match doesn't mean that the constant
4045 isn't valid, just that it is in a format that we don't
4046 automatically recognize. Try parsing it with the standard
4047 expression routines. */
4049 memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE));
4051 /* Look for a raw floating point number. */
4052 if ((save_in = atof_ieee (*str, 'x', words)) != NULL
4053 && is_end_of_line[(unsigned char) *save_in])
4055 for (i = 0; i < NUM_FLOAT_VALS; i++)
4057 for (j = 0; j < MAX_LITTLENUMS; j++)
4059 if (words[j] != fp_values[i][j])
4063 if (j == MAX_LITTLENUMS)
4071 /* Try and parse a more complex expression, this will probably fail
4072 unless the code uses a floating point prefix (eg "0f"). */
4073 save_in = input_line_pointer;
4074 input_line_pointer = *str;
4075 if (expression (&exp) == absolute_section
4076 && exp.X_op == O_big
4077 && exp.X_add_number < 0)
4079 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4081 if (gen_to_words (words, 5, (long) 15) == 0)
4083 for (i = 0; i < NUM_FLOAT_VALS; i++)
4085 for (j = 0; j < MAX_LITTLENUMS; j++)
4087 if (words[j] != fp_values[i][j])
4091 if (j == MAX_LITTLENUMS)
4093 *str = input_line_pointer;
4094 input_line_pointer = save_in;
4101 *str = input_line_pointer;
4102 input_line_pointer = save_in;
4103 inst.error = _("invalid FPA immediate expression");
4107 /* Returns 1 if a number has "quarter-precision" float format
4108 0baBbbbbbc defgh000 00000000 00000000. */
4111 is_quarter_float (unsigned imm)
4113 int bs = (imm & 0x20000000) ? 0x3e000000 : 0x40000000;
4114 return (imm & 0x7ffff) == 0 && ((imm & 0x7e000000) ^ bs) == 0;
4117 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4118 0baBbbbbbc defgh000 00000000 00000000.
4119 The zero and minus-zero cases need special handling, since they can't be
4120 encoded in the "quarter-precision" float format, but can nonetheless be
4121 loaded as integer constants. */
4124 parse_qfloat_immediate (char **ccp, int *immed)
4128 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4129 int found_fpchar = 0;
4131 skip_past_char (&str, '#');
4133 /* We must not accidentally parse an integer as a floating-point number. Make
4134 sure that the value we parse is not an integer by checking for special
4135 characters '.' or 'e'.
4136 FIXME: This is a horrible hack, but doing better is tricky because type
4137 information isn't in a very usable state at parse time. */
4139 skip_whitespace (fpnum);
4141 if (strncmp (fpnum, "0x", 2) == 0)
4145 for (; *fpnum != '\0' && *fpnum != ' ' && *fpnum != '\n'; fpnum++)
4146 if (*fpnum == '.' || *fpnum == 'e' || *fpnum == 'E')
4156 if ((str = atof_ieee (str, 's', words)) != NULL)
4158 unsigned fpword = 0;
4161 /* Our FP word must be 32 bits (single-precision FP). */
4162 for (i = 0; i < 32 / LITTLENUM_NUMBER_OF_BITS; i++)
4164 fpword <<= LITTLENUM_NUMBER_OF_BITS;
4168 if (is_quarter_float (fpword) || (fpword & 0x7fffffff) == 0)
4181 /* Shift operands. */
4184 SHIFT_LSL, SHIFT_LSR, SHIFT_ASR, SHIFT_ROR, SHIFT_RRX
4187 struct asm_shift_name
4190 enum shift_kind kind;
4193 /* Third argument to parse_shift. */
4194 enum parse_shift_mode
4196 NO_SHIFT_RESTRICT, /* Any kind of shift is accepted. */
4197 SHIFT_IMMEDIATE, /* Shift operand must be an immediate. */
4198 SHIFT_LSL_OR_ASR_IMMEDIATE, /* Shift must be LSL or ASR immediate. */
4199 SHIFT_ASR_IMMEDIATE, /* Shift must be ASR immediate. */
4200 SHIFT_LSL_IMMEDIATE, /* Shift must be LSL immediate. */
4203 /* Parse a <shift> specifier on an ARM data processing instruction.
4204 This has three forms:
4206 (LSL|LSR|ASL|ASR|ROR) Rs
4207 (LSL|LSR|ASL|ASR|ROR) #imm
4210 Note that ASL is assimilated to LSL in the instruction encoding, and
4211 RRX to ROR #0 (which cannot be written as such). */
4214 parse_shift (char **str, int i, enum parse_shift_mode mode)
4216 const struct asm_shift_name *shift_name;
4217 enum shift_kind shift;
4222 for (p = *str; ISALPHA (*p); p++)
4227 inst.error = _("shift expression expected");
4231 shift_name = hash_find_n (arm_shift_hsh, *str, p - *str);
4233 if (shift_name == NULL)
4235 inst.error = _("shift expression expected");
4239 shift = shift_name->kind;
4243 case NO_SHIFT_RESTRICT:
4244 case SHIFT_IMMEDIATE: break;
4246 case SHIFT_LSL_OR_ASR_IMMEDIATE:
4247 if (shift != SHIFT_LSL && shift != SHIFT_ASR)
4249 inst.error = _("'LSL' or 'ASR' required");
4254 case SHIFT_LSL_IMMEDIATE:
4255 if (shift != SHIFT_LSL)
4257 inst.error = _("'LSL' required");
4262 case SHIFT_ASR_IMMEDIATE:
4263 if (shift != SHIFT_ASR)
4265 inst.error = _("'ASR' required");
4273 if (shift != SHIFT_RRX)
4275 /* Whitespace can appear here if the next thing is a bare digit. */
4276 skip_whitespace (p);
4278 if (mode == NO_SHIFT_RESTRICT
4279 && (reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
4281 inst.operands[i].imm = reg;
4282 inst.operands[i].immisreg = 1;
4284 else if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
4287 inst.operands[i].shift_kind = shift;
4288 inst.operands[i].shifted = 1;
4293 /* Parse a <shifter_operand> for an ARM data processing instruction:
4296 #<immediate>, <rotate>
4300 where <shift> is defined by parse_shift above, and <rotate> is a
4301 multiple of 2 between 0 and 30. Validation of immediate operands
4302 is deferred to md_apply_fix. */
4305 parse_shifter_operand (char **str, int i)
4310 if ((value = arm_reg_parse (str, REG_TYPE_RN)) != FAIL)
4312 inst.operands[i].reg = value;
4313 inst.operands[i].isreg = 1;
4315 /* parse_shift will override this if appropriate */
4316 inst.reloc.exp.X_op = O_constant;
4317 inst.reloc.exp.X_add_number = 0;
4319 if (skip_past_comma (str) == FAIL)
4322 /* Shift operation on register. */
4323 return parse_shift (str, i, NO_SHIFT_RESTRICT);
4326 if (my_get_expression (&inst.reloc.exp, str, GE_IMM_PREFIX))
4329 if (skip_past_comma (str) == SUCCESS)
4331 /* #x, y -- ie explicit rotation by Y. */
4332 if (my_get_expression (&expr, str, GE_NO_PREFIX))
4335 if (expr.X_op != O_constant || inst.reloc.exp.X_op != O_constant)
4337 inst.error = _("constant expression expected");
4341 value = expr.X_add_number;
4342 if (value < 0 || value > 30 || value % 2 != 0)
4344 inst.error = _("invalid rotation");
4347 if (inst.reloc.exp.X_add_number < 0 || inst.reloc.exp.X_add_number > 255)
4349 inst.error = _("invalid constant");
4353 /* Convert to decoded value. md_apply_fix will put it back. */
4354 inst.reloc.exp.X_add_number
4355 = (((inst.reloc.exp.X_add_number << (32 - value))
4356 | (inst.reloc.exp.X_add_number >> value)) & 0xffffffff);
4359 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
4360 inst.reloc.pc_rel = 0;
4364 /* Group relocation information. Each entry in the table contains the
4365 textual name of the relocation as may appear in assembler source
4366 and must end with a colon.
4367 Along with this textual name are the relocation codes to be used if
4368 the corresponding instruction is an ALU instruction (ADD or SUB only),
4369 an LDR, an LDRS, or an LDC. */
4371 struct group_reloc_table_entry
4382 /* Varieties of non-ALU group relocation. */
4389 static struct group_reloc_table_entry group_reloc_table[] =
4390 { /* Program counter relative: */
4392 BFD_RELOC_ARM_ALU_PC_G0_NC, /* ALU */
4397 BFD_RELOC_ARM_ALU_PC_G0, /* ALU */
4398 BFD_RELOC_ARM_LDR_PC_G0, /* LDR */
4399 BFD_RELOC_ARM_LDRS_PC_G0, /* LDRS */
4400 BFD_RELOC_ARM_LDC_PC_G0 }, /* LDC */
4402 BFD_RELOC_ARM_ALU_PC_G1_NC, /* ALU */
4407 BFD_RELOC_ARM_ALU_PC_G1, /* ALU */
4408 BFD_RELOC_ARM_LDR_PC_G1, /* LDR */
4409 BFD_RELOC_ARM_LDRS_PC_G1, /* LDRS */
4410 BFD_RELOC_ARM_LDC_PC_G1 }, /* LDC */
4412 BFD_RELOC_ARM_ALU_PC_G2, /* ALU */
4413 BFD_RELOC_ARM_LDR_PC_G2, /* LDR */
4414 BFD_RELOC_ARM_LDRS_PC_G2, /* LDRS */
4415 BFD_RELOC_ARM_LDC_PC_G2 }, /* LDC */
4416 /* Section base relative */
4418 BFD_RELOC_ARM_ALU_SB_G0_NC, /* ALU */
4423 BFD_RELOC_ARM_ALU_SB_G0, /* ALU */
4424 BFD_RELOC_ARM_LDR_SB_G0, /* LDR */
4425 BFD_RELOC_ARM_LDRS_SB_G0, /* LDRS */
4426 BFD_RELOC_ARM_LDC_SB_G0 }, /* LDC */
4428 BFD_RELOC_ARM_ALU_SB_G1_NC, /* ALU */
4433 BFD_RELOC_ARM_ALU_SB_G1, /* ALU */
4434 BFD_RELOC_ARM_LDR_SB_G1, /* LDR */
4435 BFD_RELOC_ARM_LDRS_SB_G1, /* LDRS */
4436 BFD_RELOC_ARM_LDC_SB_G1 }, /* LDC */
4438 BFD_RELOC_ARM_ALU_SB_G2, /* ALU */
4439 BFD_RELOC_ARM_LDR_SB_G2, /* LDR */
4440 BFD_RELOC_ARM_LDRS_SB_G2, /* LDRS */
4441 BFD_RELOC_ARM_LDC_SB_G2 } }; /* LDC */
4443 /* Given the address of a pointer pointing to the textual name of a group
4444 relocation as may appear in assembler source, attempt to find its details
4445 in group_reloc_table. The pointer will be updated to the character after
4446 the trailing colon. On failure, FAIL will be returned; SUCCESS
4447 otherwise. On success, *entry will be updated to point at the relevant
4448 group_reloc_table entry. */
4451 find_group_reloc_table_entry (char **str, struct group_reloc_table_entry **out)
4454 for (i = 0; i < ARRAY_SIZE (group_reloc_table); i++)
4456 int length = strlen (group_reloc_table[i].name);
4458 if (strncasecmp (group_reloc_table[i].name, *str, length) == 0 &&
4459 (*str)[length] == ':')
4461 *out = &group_reloc_table[i];
4462 *str += (length + 1);
4470 /* Parse a <shifter_operand> for an ARM data processing instruction
4471 (as for parse_shifter_operand) where group relocations are allowed:
4474 #<immediate>, <rotate>
4475 #:<group_reloc>:<expression>
4479 where <group_reloc> is one of the strings defined in group_reloc_table.
4480 The hashes are optional.
4482 Everything else is as for parse_shifter_operand. */
4484 static parse_operand_result
4485 parse_shifter_operand_group_reloc (char **str, int i)
4487 /* Determine if we have the sequence of characters #: or just :
4488 coming next. If we do, then we check for a group relocation.
4489 If we don't, punt the whole lot to parse_shifter_operand. */
4491 if (((*str)[0] == '#' && (*str)[1] == ':')
4492 || (*str)[0] == ':')
4494 struct group_reloc_table_entry *entry;
4496 if ((*str)[0] == '#')
4501 /* Try to parse a group relocation. Anything else is an error. */
4502 if (find_group_reloc_table_entry (str, &entry) == FAIL)
4504 inst.error = _("unknown group relocation");
4505 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
4508 /* We now have the group relocation table entry corresponding to
4509 the name in the assembler source. Next, we parse the expression. */
4510 if (my_get_expression (&inst.reloc.exp, str, GE_NO_PREFIX))
4511 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
4513 /* Record the relocation type (always the ALU variant here). */
4514 inst.reloc.type = entry->alu_code;
4515 assert (inst.reloc.type != 0);
4517 return PARSE_OPERAND_SUCCESS;
4520 return parse_shifter_operand (str, i) == SUCCESS
4521 ? PARSE_OPERAND_SUCCESS : PARSE_OPERAND_FAIL;
4523 /* Never reached. */
4526 /* Parse all forms of an ARM address expression. Information is written
4527 to inst.operands[i] and/or inst.reloc.
4529 Preindexed addressing (.preind=1):
4531 [Rn, #offset] .reg=Rn .reloc.exp=offset
4532 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4533 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4534 .shift_kind=shift .reloc.exp=shift_imm
4536 These three may have a trailing ! which causes .writeback to be set also.
4538 Postindexed addressing (.postind=1, .writeback=1):
4540 [Rn], #offset .reg=Rn .reloc.exp=offset
4541 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4542 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4543 .shift_kind=shift .reloc.exp=shift_imm
4545 Unindexed addressing (.preind=0, .postind=0):
4547 [Rn], {option} .reg=Rn .imm=option .immisreg=0
4551 [Rn]{!} shorthand for [Rn,#0]{!}
4552 =immediate .isreg=0 .reloc.exp=immediate
4553 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
4555 It is the caller's responsibility to check for addressing modes not
4556 supported by the instruction, and to set inst.reloc.type. */
4558 static parse_operand_result
4559 parse_address_main (char **str, int i, int group_relocations,
4560 group_reloc_type group_type)
4565 if (skip_past_char (&p, '[') == FAIL)
4567 if (skip_past_char (&p, '=') == FAIL)
4569 /* bare address - translate to PC-relative offset */
4570 inst.reloc.pc_rel = 1;
4571 inst.operands[i].reg = REG_PC;
4572 inst.operands[i].isreg = 1;
4573 inst.operands[i].preind = 1;
4575 /* else a load-constant pseudo op, no special treatment needed here */
4577 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
4578 return PARSE_OPERAND_FAIL;
4581 return PARSE_OPERAND_SUCCESS;
4584 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
4586 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
4587 return PARSE_OPERAND_FAIL;
4589 inst.operands[i].reg = reg;
4590 inst.operands[i].isreg = 1;
4592 if (skip_past_comma (&p) == SUCCESS)
4594 inst.operands[i].preind = 1;
4597 else if (*p == '-') p++, inst.operands[i].negative = 1;
4599 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
4601 inst.operands[i].imm = reg;
4602 inst.operands[i].immisreg = 1;
4604 if (skip_past_comma (&p) == SUCCESS)
4605 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
4606 return PARSE_OPERAND_FAIL;
4608 else if (skip_past_char (&p, ':') == SUCCESS)
4610 /* FIXME: '@' should be used here, but it's filtered out by generic
4611 code before we get to see it here. This may be subject to
4614 my_get_expression (&exp, &p, GE_NO_PREFIX);
4615 if (exp.X_op != O_constant)
4617 inst.error = _("alignment must be constant");
4618 return PARSE_OPERAND_FAIL;
4620 inst.operands[i].imm = exp.X_add_number << 8;
4621 inst.operands[i].immisalign = 1;
4622 /* Alignments are not pre-indexes. */
4623 inst.operands[i].preind = 0;
4627 if (inst.operands[i].negative)
4629 inst.operands[i].negative = 0;
4633 if (group_relocations &&
4634 ((*p == '#' && *(p + 1) == ':') || *p == ':'))
4637 struct group_reloc_table_entry *entry;
4639 /* Skip over the #: or : sequence. */
4645 /* Try to parse a group relocation. Anything else is an
4647 if (find_group_reloc_table_entry (&p, &entry) == FAIL)
4649 inst.error = _("unknown group relocation");
4650 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
4653 /* We now have the group relocation table entry corresponding to
4654 the name in the assembler source. Next, we parse the
4656 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
4657 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
4659 /* Record the relocation type. */
4663 inst.reloc.type = entry->ldr_code;
4667 inst.reloc.type = entry->ldrs_code;
4671 inst.reloc.type = entry->ldc_code;
4678 if (inst.reloc.type == 0)
4680 inst.error = _("this group relocation is not allowed on this instruction");
4681 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
4685 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
4686 return PARSE_OPERAND_FAIL;
4690 if (skip_past_char (&p, ']') == FAIL)
4692 inst.error = _("']' expected");
4693 return PARSE_OPERAND_FAIL;
4696 if (skip_past_char (&p, '!') == SUCCESS)
4697 inst.operands[i].writeback = 1;
4699 else if (skip_past_comma (&p) == SUCCESS)
4701 if (skip_past_char (&p, '{') == SUCCESS)
4703 /* [Rn], {expr} - unindexed, with option */
4704 if (parse_immediate (&p, &inst.operands[i].imm,
4705 0, 255, TRUE) == FAIL)
4706 return PARSE_OPERAND_FAIL;
4708 if (skip_past_char (&p, '}') == FAIL)
4710 inst.error = _("'}' expected at end of 'option' field");
4711 return PARSE_OPERAND_FAIL;
4713 if (inst.operands[i].preind)
4715 inst.error = _("cannot combine index with option");
4716 return PARSE_OPERAND_FAIL;
4719 return PARSE_OPERAND_SUCCESS;
4723 inst.operands[i].postind = 1;
4724 inst.operands[i].writeback = 1;
4726 if (inst.operands[i].preind)
4728 inst.error = _("cannot combine pre- and post-indexing");
4729 return PARSE_OPERAND_FAIL;
4733 else if (*p == '-') p++, inst.operands[i].negative = 1;
4735 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
4737 /* We might be using the immediate for alignment already. If we
4738 are, OR the register number into the low-order bits. */
4739 if (inst.operands[i].immisalign)
4740 inst.operands[i].imm |= reg;
4742 inst.operands[i].imm = reg;
4743 inst.operands[i].immisreg = 1;
4745 if (skip_past_comma (&p) == SUCCESS)
4746 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
4747 return PARSE_OPERAND_FAIL;
4751 if (inst.operands[i].negative)
4753 inst.operands[i].negative = 0;
4756 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
4757 return PARSE_OPERAND_FAIL;
4762 /* If at this point neither .preind nor .postind is set, we have a
4763 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
4764 if (inst.operands[i].preind == 0 && inst.operands[i].postind == 0)
4766 inst.operands[i].preind = 1;
4767 inst.reloc.exp.X_op = O_constant;
4768 inst.reloc.exp.X_add_number = 0;
4771 return PARSE_OPERAND_SUCCESS;
4775 parse_address (char **str, int i)
4777 return parse_address_main (str, i, 0, 0) == PARSE_OPERAND_SUCCESS
4781 static parse_operand_result
4782 parse_address_group_reloc (char **str, int i, group_reloc_type type)
4784 return parse_address_main (str, i, 1, type);
4787 /* Parse an operand for a MOVW or MOVT instruction. */
4789 parse_half (char **str)
4794 skip_past_char (&p, '#');
4795 if (strncasecmp (p, ":lower16:", 9) == 0)
4796 inst.reloc.type = BFD_RELOC_ARM_MOVW;
4797 else if (strncasecmp (p, ":upper16:", 9) == 0)
4798 inst.reloc.type = BFD_RELOC_ARM_MOVT;
4800 if (inst.reloc.type != BFD_RELOC_UNUSED)
4806 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
4809 if (inst.reloc.type == BFD_RELOC_UNUSED)
4811 if (inst.reloc.exp.X_op != O_constant)
4813 inst.error = _("constant expression expected");
4816 if (inst.reloc.exp.X_add_number < 0
4817 || inst.reloc.exp.X_add_number > 0xffff)
4819 inst.error = _("immediate value out of range");
4827 /* Miscellaneous. */
4829 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
4830 or a bitmask suitable to be or-ed into the ARM msr instruction. */
4832 parse_psr (char **str)
4835 unsigned long psr_field;
4836 const struct asm_psr *psr;
4839 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
4840 feature for ease of use and backwards compatibility. */
4842 if (strncasecmp (p, "SPSR", 4) == 0)
4843 psr_field = SPSR_BIT;
4844 else if (strncasecmp (p, "CPSR", 4) == 0)
4851 while (ISALNUM (*p) || *p == '_');
4853 psr = hash_find_n (arm_v7m_psr_hsh, start, p - start);
4864 /* A suffix follows. */
4870 while (ISALNUM (*p) || *p == '_');
4872 psr = hash_find_n (arm_psr_hsh, start, p - start);
4876 psr_field |= psr->field;
4881 goto error; /* Garbage after "[CS]PSR". */
4883 psr_field |= (PSR_c | PSR_f);
4889 inst.error = _("flag for {c}psr instruction expected");
4893 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
4894 value suitable for splatting into the AIF field of the instruction. */
4897 parse_cps_flags (char **str)
4906 case '\0': case ',':
4909 case 'a': case 'A': saw_a_flag = 1; val |= 0x4; break;
4910 case 'i': case 'I': saw_a_flag = 1; val |= 0x2; break;
4911 case 'f': case 'F': saw_a_flag = 1; val |= 0x1; break;
4914 inst.error = _("unrecognized CPS flag");
4919 if (saw_a_flag == 0)
4921 inst.error = _("missing CPS flags");
4929 /* Parse an endian specifier ("BE" or "LE", case insensitive);
4930 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
4933 parse_endian_specifier (char **str)
4938 if (strncasecmp (s, "BE", 2))
4940 else if (strncasecmp (s, "LE", 2))
4944 inst.error = _("valid endian specifiers are be or le");
4948 if (ISALNUM (s[2]) || s[2] == '_')
4950 inst.error = _("valid endian specifiers are be or le");
4955 return little_endian;
4958 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
4959 value suitable for poking into the rotate field of an sxt or sxta
4960 instruction, or FAIL on error. */
4963 parse_ror (char **str)
4968 if (strncasecmp (s, "ROR", 3) == 0)
4972 inst.error = _("missing rotation field after comma");
4976 if (parse_immediate (&s, &rot, 0, 24, FALSE) == FAIL)
4981 case 0: *str = s; return 0x0;
4982 case 8: *str = s; return 0x1;
4983 case 16: *str = s; return 0x2;
4984 case 24: *str = s; return 0x3;
4987 inst.error = _("rotation can only be 0, 8, 16, or 24");
4992 /* Parse a conditional code (from conds[] below). The value returned is in the
4993 range 0 .. 14, or FAIL. */
4995 parse_cond (char **str)
4998 const struct asm_cond *c;
5001 while (ISALPHA (*q))
5004 c = hash_find_n (arm_cond_hsh, p, q - p);
5007 inst.error = _("condition required");
5015 /* Parse an option for a barrier instruction. Returns the encoding for the
5018 parse_barrier (char **str)
5021 const struct asm_barrier_opt *o;
5024 while (ISALPHA (*q))
5027 o = hash_find_n (arm_barrier_opt_hsh, p, q - p);
5035 /* Parse the operands of a table branch instruction. Similar to a memory
5038 parse_tb (char **str)
5043 if (skip_past_char (&p, '[') == FAIL)
5045 inst.error = _("'[' expected");
5049 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
5051 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
5054 inst.operands[0].reg = reg;
5056 if (skip_past_comma (&p) == FAIL)
5058 inst.error = _("',' expected");
5062 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
5064 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
5067 inst.operands[0].imm = reg;
5069 if (skip_past_comma (&p) == SUCCESS)
5071 if (parse_shift (&p, 0, SHIFT_LSL_IMMEDIATE) == FAIL)
5073 if (inst.reloc.exp.X_add_number != 1)
5075 inst.error = _("invalid shift");
5078 inst.operands[0].shifted = 1;
5081 if (skip_past_char (&p, ']') == FAIL)
5083 inst.error = _("']' expected");
5090 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
5091 information on the types the operands can take and how they are encoded.
5092 Up to four operands may be read; this function handles setting the
5093 ".present" field for each read operand itself.
5094 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
5095 else returns FAIL. */
5098 parse_neon_mov (char **str, int *which_operand)
5100 int i = *which_operand, val;
5101 enum arm_reg_type rtype;
5103 struct neon_type_el optype;
5105 if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL)
5107 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
5108 inst.operands[i].reg = val;
5109 inst.operands[i].isscalar = 1;
5110 inst.operands[i].vectype = optype;
5111 inst.operands[i++].present = 1;
5113 if (skip_past_comma (&ptr) == FAIL)
5116 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5119 inst.operands[i].reg = val;
5120 inst.operands[i].isreg = 1;
5121 inst.operands[i].present = 1;
5123 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, &optype))
5126 /* Cases 0, 1, 2, 3, 5 (D only). */
5127 if (skip_past_comma (&ptr) == FAIL)
5130 inst.operands[i].reg = val;
5131 inst.operands[i].isreg = 1;
5132 inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
5133 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
5134 inst.operands[i].isvec = 1;
5135 inst.operands[i].vectype = optype;
5136 inst.operands[i++].present = 1;
5138 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
5140 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
5141 Case 13: VMOV <Sd>, <Rm> */
5142 inst.operands[i].reg = val;
5143 inst.operands[i].isreg = 1;
5144 inst.operands[i].present = 1;
5146 if (rtype == REG_TYPE_NQ)
5148 first_error (_("can't use Neon quad register here"));
5151 else if (rtype != REG_TYPE_VFS)
5154 if (skip_past_comma (&ptr) == FAIL)
5156 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5158 inst.operands[i].reg = val;
5159 inst.operands[i].isreg = 1;
5160 inst.operands[i].present = 1;
5163 else if (parse_qfloat_immediate (&ptr, &inst.operands[i].imm) == SUCCESS)
5164 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
5165 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
5166 Case 10: VMOV.F32 <Sd>, #<imm>
5167 Case 11: VMOV.F64 <Dd>, #<imm> */
5168 inst.operands[i].immisfloat = 1;
5169 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype,
5172 /* Case 0: VMOV<c><q> <Qd>, <Qm>
5173 Case 1: VMOV<c><q> <Dd>, <Dm>
5174 Case 8: VMOV.F32 <Sd>, <Sm>
5175 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
5177 inst.operands[i].reg = val;
5178 inst.operands[i].isreg = 1;
5179 inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
5180 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
5181 inst.operands[i].isvec = 1;
5182 inst.operands[i].vectype = optype;
5183 inst.operands[i].present = 1;
5185 if (skip_past_comma (&ptr) == SUCCESS)
5190 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5193 inst.operands[i].reg = val;
5194 inst.operands[i].isreg = 1;
5195 inst.operands[i++].present = 1;
5197 if (skip_past_comma (&ptr) == FAIL)
5200 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5203 inst.operands[i].reg = val;
5204 inst.operands[i].isreg = 1;
5205 inst.operands[i++].present = 1;
5208 else if (parse_big_immediate (&ptr, i) == SUCCESS)
5209 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
5210 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
5214 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
5218 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
5221 inst.operands[i].reg = val;
5222 inst.operands[i].isreg = 1;
5223 inst.operands[i++].present = 1;
5225 if (skip_past_comma (&ptr) == FAIL)
5228 if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL)
5230 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
5231 inst.operands[i].reg = val;
5232 inst.operands[i].isscalar = 1;
5233 inst.operands[i].present = 1;
5234 inst.operands[i].vectype = optype;
5236 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
5238 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
5239 inst.operands[i].reg = val;
5240 inst.operands[i].isreg = 1;
5241 inst.operands[i++].present = 1;
5243 if (skip_past_comma (&ptr) == FAIL)
5246 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFSD, &rtype, &optype))
5249 first_error (_(reg_expected_msgs[REG_TYPE_VFSD]));
5253 inst.operands[i].reg = val;
5254 inst.operands[i].isreg = 1;
5255 inst.operands[i].isvec = 1;
5256 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
5257 inst.operands[i].vectype = optype;
5258 inst.operands[i].present = 1;
5260 if (rtype == REG_TYPE_VFS)
5264 if (skip_past_comma (&ptr) == FAIL)
5266 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL,
5269 first_error (_(reg_expected_msgs[REG_TYPE_VFS]));
5272 inst.operands[i].reg = val;
5273 inst.operands[i].isreg = 1;
5274 inst.operands[i].isvec = 1;
5275 inst.operands[i].issingle = 1;
5276 inst.operands[i].vectype = optype;
5277 inst.operands[i].present = 1;
5280 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, &optype))
5284 inst.operands[i].reg = val;
5285 inst.operands[i].isreg = 1;
5286 inst.operands[i].isvec = 1;
5287 inst.operands[i].issingle = 1;
5288 inst.operands[i].vectype = optype;
5289 inst.operands[i++].present = 1;
5294 first_error (_("parse error"));
5298 /* Successfully parsed the operands. Update args. */
5304 first_error (_("expected comma"));
5308 first_error (_(reg_expected_msgs[REG_TYPE_RN]));
5312 /* Matcher codes for parse_operands. */
5313 enum operand_parse_code
5315 OP_stop, /* end of line */
5317 OP_RR, /* ARM register */
5318 OP_RRnpc, /* ARM register, not r15 */
5319 OP_RRnpcb, /* ARM register, not r15, in square brackets */
5320 OP_RRw, /* ARM register, not r15, optional trailing ! */
5321 OP_RCP, /* Coprocessor number */
5322 OP_RCN, /* Coprocessor register */
5323 OP_RF, /* FPA register */
5324 OP_RVS, /* VFP single precision register */
5325 OP_RVD, /* VFP double precision register (0..15) */
5326 OP_RND, /* Neon double precision register (0..31) */
5327 OP_RNQ, /* Neon quad precision register */
5328 OP_RVSD, /* VFP single or double precision register */
5329 OP_RNDQ, /* Neon double or quad precision register */
5330 OP_RNSDQ, /* Neon single, double or quad precision register */
5331 OP_RNSC, /* Neon scalar D[X] */
5332 OP_RVC, /* VFP control register */
5333 OP_RMF, /* Maverick F register */
5334 OP_RMD, /* Maverick D register */
5335 OP_RMFX, /* Maverick FX register */
5336 OP_RMDX, /* Maverick DX register */
5337 OP_RMAX, /* Maverick AX register */
5338 OP_RMDS, /* Maverick DSPSC register */
5339 OP_RIWR, /* iWMMXt wR register */
5340 OP_RIWC, /* iWMMXt wC register */
5341 OP_RIWG, /* iWMMXt wCG register */
5342 OP_RXA, /* XScale accumulator register */
5344 OP_REGLST, /* ARM register list */
5345 OP_VRSLST, /* VFP single-precision register list */
5346 OP_VRDLST, /* VFP double-precision register list */
5347 OP_VRSDLST, /* VFP single or double-precision register list (& quad) */
5348 OP_NRDLST, /* Neon double-precision register list (d0-d31, qN aliases) */
5349 OP_NSTRLST, /* Neon element/structure list */
5351 OP_NILO, /* Neon immediate/logic operands 2 or 2+3. (VBIC, VORR...) */
5352 OP_RNDQ_I0, /* Neon D or Q reg, or immediate zero. */
5353 OP_RVSD_I0, /* VFP S or D reg, or immediate zero. */
5354 OP_RR_RNSC, /* ARM reg or Neon scalar. */
5355 OP_RNSDQ_RNSC, /* Vector S, D or Q reg, or Neon scalar. */
5356 OP_RNDQ_RNSC, /* Neon D or Q reg, or Neon scalar. */
5357 OP_RND_RNSC, /* Neon D reg, or Neon scalar. */
5358 OP_VMOV, /* Neon VMOV operands. */
5359 OP_RNDQ_IMVNb,/* Neon D or Q reg, or immediate good for VMVN. */
5360 OP_RNDQ_I63b, /* Neon D or Q reg, or immediate for shift. */
5361 OP_RIWR_I32z, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
5363 OP_I0, /* immediate zero */
5364 OP_I7, /* immediate value 0 .. 7 */
5365 OP_I15, /* 0 .. 15 */
5366 OP_I16, /* 1 .. 16 */
5367 OP_I16z, /* 0 .. 16 */
5368 OP_I31, /* 0 .. 31 */
5369 OP_I31w, /* 0 .. 31, optional trailing ! */
5370 OP_I32, /* 1 .. 32 */
5371 OP_I32z, /* 0 .. 32 */
5372 OP_I63, /* 0 .. 63 */
5373 OP_I63s, /* -64 .. 63 */
5374 OP_I64, /* 1 .. 64 */
5375 OP_I64z, /* 0 .. 64 */
5376 OP_I255, /* 0 .. 255 */
5378 OP_I4b, /* immediate, prefix optional, 1 .. 4 */
5379 OP_I7b, /* 0 .. 7 */
5380 OP_I15b, /* 0 .. 15 */
5381 OP_I31b, /* 0 .. 31 */
5383 OP_SH, /* shifter operand */
5384 OP_SHG, /* shifter operand with possible group relocation */
5385 OP_ADDR, /* Memory address expression (any mode) */
5386 OP_ADDRGLDR, /* Mem addr expr (any mode) with possible LDR group reloc */
5387 OP_ADDRGLDRS, /* Mem addr expr (any mode) with possible LDRS group reloc */
5388 OP_ADDRGLDC, /* Mem addr expr (any mode) with possible LDC group reloc */
5389 OP_EXP, /* arbitrary expression */
5390 OP_EXPi, /* same, with optional immediate prefix */
5391 OP_EXPr, /* same, with optional relocation suffix */
5392 OP_HALF, /* 0 .. 65535 or low/high reloc. */
5394 OP_CPSF, /* CPS flags */
5395 OP_ENDI, /* Endianness specifier */
5396 OP_PSR, /* CPSR/SPSR mask for msr */
5397 OP_COND, /* conditional code */
5398 OP_TB, /* Table branch. */
5400 OP_RVC_PSR, /* CPSR/SPSR mask for msr, or VFP control register. */
5401 OP_APSR_RR, /* ARM register or "APSR_nzcv". */
5403 OP_RRnpc_I0, /* ARM register or literal 0 */
5404 OP_RR_EXr, /* ARM register or expression with opt. reloc suff. */
5405 OP_RR_EXi, /* ARM register or expression with imm prefix */
5406 OP_RF_IF, /* FPA register or immediate */
5407 OP_RIWR_RIWC, /* iWMMXt R or C reg */
5408 OP_RIWC_RIWG, /* iWMMXt wC or wCG reg */
5410 /* Optional operands. */
5411 OP_oI7b, /* immediate, prefix optional, 0 .. 7 */
5412 OP_oI31b, /* 0 .. 31 */
5413 OP_oI32b, /* 1 .. 32 */
5414 OP_oIffffb, /* 0 .. 65535 */
5415 OP_oI255c, /* curly-brace enclosed, 0 .. 255 */
5417 OP_oRR, /* ARM register */
5418 OP_oRRnpc, /* ARM register, not the PC */
5419 OP_oRRw, /* ARM register, not r15, optional trailing ! */
5420 OP_oRND, /* Optional Neon double precision register */
5421 OP_oRNQ, /* Optional Neon quad precision register */
5422 OP_oRNDQ, /* Optional Neon double or quad precision register */
5423 OP_oRNSDQ, /* Optional single, double or quad precision vector register */
5424 OP_oSHll, /* LSL immediate */
5425 OP_oSHar, /* ASR immediate */
5426 OP_oSHllar, /* LSL or ASR immediate */
5427 OP_oROR, /* ROR 0/8/16/24 */
5428 OP_oBARRIER, /* Option argument for a barrier instruction. */
5430 OP_FIRST_OPTIONAL = OP_oI7b
5433 /* Generic instruction operand parser. This does no encoding and no
5434 semantic validation; it merely squirrels values away in the inst
5435 structure. Returns SUCCESS or FAIL depending on whether the
5436 specified grammar matched. */
5438 parse_operands (char *str, const unsigned char *pattern)
5440 unsigned const char *upat = pattern;
5441 char *backtrack_pos = 0;
5442 const char *backtrack_error = 0;
5443 int i, val, backtrack_index = 0;
5444 enum arm_reg_type rtype;
5445 parse_operand_result result;
5447 #define po_char_or_fail(chr) do { \
5448 if (skip_past_char (&str, chr) == FAIL) \
5452 #define po_reg_or_fail(regtype) do { \
5453 val = arm_typed_reg_parse (&str, regtype, &rtype, \
5454 &inst.operands[i].vectype); \
5457 first_error (_(reg_expected_msgs[regtype])); \
5460 inst.operands[i].reg = val; \
5461 inst.operands[i].isreg = 1; \
5462 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
5463 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
5464 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
5465 || rtype == REG_TYPE_VFD \
5466 || rtype == REG_TYPE_NQ); \
5469 #define po_reg_or_goto(regtype, label) do { \
5470 val = arm_typed_reg_parse (&str, regtype, &rtype, \
5471 &inst.operands[i].vectype); \
5475 inst.operands[i].reg = val; \
5476 inst.operands[i].isreg = 1; \
5477 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
5478 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
5479 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
5480 || rtype == REG_TYPE_VFD \
5481 || rtype == REG_TYPE_NQ); \
5484 #define po_imm_or_fail(min, max, popt) do { \
5485 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
5487 inst.operands[i].imm = val; \
5490 #define po_scalar_or_goto(elsz, label) do { \
5491 val = parse_scalar (&str, elsz, &inst.operands[i].vectype); \
5494 inst.operands[i].reg = val; \
5495 inst.operands[i].isscalar = 1; \
5498 #define po_misc_or_fail(expr) do { \
5503 #define po_misc_or_fail_no_backtrack(expr) do { \
5505 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK)\
5506 backtrack_pos = 0; \
5507 if (result != PARSE_OPERAND_SUCCESS) \
5511 skip_whitespace (str);
5513 for (i = 0; upat[i] != OP_stop; i++)
5515 if (upat[i] >= OP_FIRST_OPTIONAL)
5517 /* Remember where we are in case we need to backtrack. */
5518 assert (!backtrack_pos);
5519 backtrack_pos = str;
5520 backtrack_error = inst.error;
5521 backtrack_index = i;
5524 if (i > 0 && (i > 1 || inst.operands[0].present))
5525 po_char_or_fail (',');
5533 case OP_RR: po_reg_or_fail (REG_TYPE_RN); break;
5534 case OP_RCP: po_reg_or_fail (REG_TYPE_CP); break;
5535 case OP_RCN: po_reg_or_fail (REG_TYPE_CN); break;
5536 case OP_RF: po_reg_or_fail (REG_TYPE_FN); break;
5537 case OP_RVS: po_reg_or_fail (REG_TYPE_VFS); break;
5538 case OP_RVD: po_reg_or_fail (REG_TYPE_VFD); break;
5540 case OP_RND: po_reg_or_fail (REG_TYPE_VFD); break;
5542 po_reg_or_goto (REG_TYPE_VFC, coproc_reg);
5544 /* Also accept generic coprocessor regs for unknown registers. */
5546 po_reg_or_fail (REG_TYPE_CN);
5548 case OP_RMF: po_reg_or_fail (REG_TYPE_MVF); break;
5549 case OP_RMD: po_reg_or_fail (REG_TYPE_MVD); break;
5550 case OP_RMFX: po_reg_or_fail (REG_TYPE_MVFX); break;
5551 case OP_RMDX: po_reg_or_fail (REG_TYPE_MVDX); break;
5552 case OP_RMAX: po_reg_or_fail (REG_TYPE_MVAX); break;
5553 case OP_RMDS: po_reg_or_fail (REG_TYPE_DSPSC); break;
5554 case OP_RIWR: po_reg_or_fail (REG_TYPE_MMXWR); break;
5555 case OP_RIWC: po_reg_or_fail (REG_TYPE_MMXWC); break;
5556 case OP_RIWG: po_reg_or_fail (REG_TYPE_MMXWCG); break;
5557 case OP_RXA: po_reg_or_fail (REG_TYPE_XSCALE); break;
5559 case OP_RNQ: po_reg_or_fail (REG_TYPE_NQ); break;
5561 case OP_RNDQ: po_reg_or_fail (REG_TYPE_NDQ); break;
5562 case OP_RVSD: po_reg_or_fail (REG_TYPE_VFSD); break;
5564 case OP_RNSDQ: po_reg_or_fail (REG_TYPE_NSDQ); break;
5566 /* Neon scalar. Using an element size of 8 means that some invalid
5567 scalars are accepted here, so deal with those in later code. */
5568 case OP_RNSC: po_scalar_or_goto (8, failure); break;
5570 /* WARNING: We can expand to two operands here. This has the potential
5571 to totally confuse the backtracking mechanism! It will be OK at
5572 least as long as we don't try to use optional args as well,
5576 po_reg_or_goto (REG_TYPE_NDQ, try_imm);
5577 inst.operands[i].present = 1;
5579 skip_past_comma (&str);
5580 po_reg_or_goto (REG_TYPE_NDQ, one_reg_only);
5583 /* Optional register operand was omitted. Unfortunately, it's in
5584 operands[i-1] and we need it to be in inst.operands[i]. Fix that
5585 here (this is a bit grotty). */
5586 inst.operands[i] = inst.operands[i-1];
5587 inst.operands[i-1].present = 0;
5590 /* There's a possibility of getting a 64-bit immediate here, so
5591 we need special handling. */
5592 if (parse_big_immediate (&str, i) == FAIL)
5594 inst.error = _("immediate value is out of range");
5602 po_reg_or_goto (REG_TYPE_NDQ, try_imm0);
5605 po_imm_or_fail (0, 0, TRUE);
5610 po_reg_or_goto (REG_TYPE_VFSD, try_imm0);
5615 po_scalar_or_goto (8, try_rr);
5618 po_reg_or_fail (REG_TYPE_RN);
5624 po_scalar_or_goto (8, try_nsdq);
5627 po_reg_or_fail (REG_TYPE_NSDQ);
5633 po_scalar_or_goto (8, try_ndq);
5636 po_reg_or_fail (REG_TYPE_NDQ);
5642 po_scalar_or_goto (8, try_vfd);
5645 po_reg_or_fail (REG_TYPE_VFD);
5650 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
5651 not careful then bad things might happen. */
5652 po_misc_or_fail (parse_neon_mov (&str, &i) == FAIL);
5657 po_reg_or_goto (REG_TYPE_NDQ, try_mvnimm);
5660 /* There's a possibility of getting a 64-bit immediate here, so
5661 we need special handling. */
5662 if (parse_big_immediate (&str, i) == FAIL)
5664 inst.error = _("immediate value is out of range");
5672 po_reg_or_goto (REG_TYPE_NDQ, try_shimm);
5675 po_imm_or_fail (0, 63, TRUE);
5680 po_char_or_fail ('[');
5681 po_reg_or_fail (REG_TYPE_RN);
5682 po_char_or_fail (']');
5687 po_reg_or_fail (REG_TYPE_RN);
5688 if (skip_past_char (&str, '!') == SUCCESS)
5689 inst.operands[i].writeback = 1;
5693 case OP_I7: po_imm_or_fail ( 0, 7, FALSE); break;
5694 case OP_I15: po_imm_or_fail ( 0, 15, FALSE); break;
5695 case OP_I16: po_imm_or_fail ( 1, 16, FALSE); break;
5696 case OP_I16z: po_imm_or_fail ( 0, 16, FALSE); break;
5697 case OP_I31: po_imm_or_fail ( 0, 31, FALSE); break;
5698 case OP_I32: po_imm_or_fail ( 1, 32, FALSE); break;
5699 case OP_I32z: po_imm_or_fail ( 0, 32, FALSE); break;
5700 case OP_I63s: po_imm_or_fail (-64, 63, FALSE); break;
5701 case OP_I63: po_imm_or_fail ( 0, 63, FALSE); break;
5702 case OP_I64: po_imm_or_fail ( 1, 64, FALSE); break;
5703 case OP_I64z: po_imm_or_fail ( 0, 64, FALSE); break;
5704 case OP_I255: po_imm_or_fail ( 0, 255, FALSE); break;
5706 case OP_I4b: po_imm_or_fail ( 1, 4, TRUE); break;
5708 case OP_I7b: po_imm_or_fail ( 0, 7, TRUE); break;
5709 case OP_I15b: po_imm_or_fail ( 0, 15, TRUE); break;
5711 case OP_I31b: po_imm_or_fail ( 0, 31, TRUE); break;
5712 case OP_oI32b: po_imm_or_fail ( 1, 32, TRUE); break;
5713 case OP_oIffffb: po_imm_or_fail ( 0, 0xffff, TRUE); break;
5715 /* Immediate variants */
5717 po_char_or_fail ('{');
5718 po_imm_or_fail (0, 255, TRUE);
5719 po_char_or_fail ('}');
5723 /* The expression parser chokes on a trailing !, so we have
5724 to find it first and zap it. */
5727 while (*s && *s != ',')
5732 inst.operands[i].writeback = 1;
5734 po_imm_or_fail (0, 31, TRUE);
5742 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
5747 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
5752 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
5754 if (inst.reloc.exp.X_op == O_symbol)
5756 val = parse_reloc (&str);
5759 inst.error = _("unrecognized relocation suffix");
5762 else if (val != BFD_RELOC_UNUSED)
5764 inst.operands[i].imm = val;
5765 inst.operands[i].hasreloc = 1;
5770 /* Operand for MOVW or MOVT. */
5772 po_misc_or_fail (parse_half (&str));
5775 /* Register or expression */
5776 case OP_RR_EXr: po_reg_or_goto (REG_TYPE_RN, EXPr); break;
5777 case OP_RR_EXi: po_reg_or_goto (REG_TYPE_RN, EXPi); break;
5779 /* Register or immediate */
5780 case OP_RRnpc_I0: po_reg_or_goto (REG_TYPE_RN, I0); break;
5781 I0: po_imm_or_fail (0, 0, FALSE); break;
5783 case OP_RF_IF: po_reg_or_goto (REG_TYPE_FN, IF); break;
5785 if (!is_immediate_prefix (*str))
5788 val = parse_fpa_immediate (&str);
5791 /* FPA immediates are encoded as registers 8-15.
5792 parse_fpa_immediate has already applied the offset. */
5793 inst.operands[i].reg = val;
5794 inst.operands[i].isreg = 1;
5797 case OP_RIWR_I32z: po_reg_or_goto (REG_TYPE_MMXWR, I32z); break;
5798 I32z: po_imm_or_fail (0, 32, FALSE); break;
5800 /* Two kinds of register */
5803 struct reg_entry *rege = arm_reg_parse_multi (&str);
5805 || (rege->type != REG_TYPE_MMXWR
5806 && rege->type != REG_TYPE_MMXWC
5807 && rege->type != REG_TYPE_MMXWCG))
5809 inst.error = _("iWMMXt data or control register expected");
5812 inst.operands[i].reg = rege->number;
5813 inst.operands[i].isreg = (rege->type == REG_TYPE_MMXWR);
5819 struct reg_entry *rege = arm_reg_parse_multi (&str);
5821 || (rege->type != REG_TYPE_MMXWC
5822 && rege->type != REG_TYPE_MMXWCG))
5824 inst.error = _("iWMMXt control register expected");
5827 inst.operands[i].reg = rege->number;
5828 inst.operands[i].isreg = 1;
5833 case OP_CPSF: val = parse_cps_flags (&str); break;
5834 case OP_ENDI: val = parse_endian_specifier (&str); break;
5835 case OP_oROR: val = parse_ror (&str); break;
5836 case OP_PSR: val = parse_psr (&str); break;
5837 case OP_COND: val = parse_cond (&str); break;
5838 case OP_oBARRIER:val = parse_barrier (&str); break;
5841 po_reg_or_goto (REG_TYPE_VFC, try_psr);
5842 inst.operands[i].isvec = 1; /* Mark VFP control reg as vector. */
5845 val = parse_psr (&str);
5849 po_reg_or_goto (REG_TYPE_RN, try_apsr);
5852 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
5854 if (strncasecmp (str, "APSR_", 5) == 0)
5861 case 'c': found = (found & 1) ? 16 : found | 1; break;
5862 case 'n': found = (found & 2) ? 16 : found | 2; break;
5863 case 'z': found = (found & 4) ? 16 : found | 4; break;
5864 case 'v': found = (found & 8) ? 16 : found | 8; break;
5865 default: found = 16;
5869 inst.operands[i].isvec = 1;
5876 po_misc_or_fail (parse_tb (&str));
5879 /* Register lists */
5881 val = parse_reg_list (&str);
5884 inst.operands[1].writeback = 1;
5890 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_S);
5894 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_D);
5898 /* Allow Q registers too. */
5899 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
5904 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
5906 inst.operands[i].issingle = 1;
5911 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
5916 val = parse_neon_el_struct_list (&str, &inst.operands[i].reg,
5917 &inst.operands[i].vectype);
5920 /* Addressing modes */
5922 po_misc_or_fail (parse_address (&str, i));
5926 po_misc_or_fail_no_backtrack (
5927 parse_address_group_reloc (&str, i, GROUP_LDR));
5931 po_misc_or_fail_no_backtrack (
5932 parse_address_group_reloc (&str, i, GROUP_LDRS));
5936 po_misc_or_fail_no_backtrack (
5937 parse_address_group_reloc (&str, i, GROUP_LDC));
5941 po_misc_or_fail (parse_shifter_operand (&str, i));
5945 po_misc_or_fail_no_backtrack (
5946 parse_shifter_operand_group_reloc (&str, i));
5950 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_IMMEDIATE));
5954 po_misc_or_fail (parse_shift (&str, i, SHIFT_ASR_IMMEDIATE));
5958 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_OR_ASR_IMMEDIATE));
5962 as_fatal ("unhandled operand code %d", upat[i]);
5965 /* Various value-based sanity checks and shared operations. We
5966 do not signal immediate failures for the register constraints;
5967 this allows a syntax error to take precedence. */
5976 if (inst.operands[i].isreg && inst.operands[i].reg == REG_PC)
5977 inst.error = BAD_PC;
5995 inst.operands[i].imm = val;
6002 /* If we get here, this operand was successfully parsed. */
6003 inst.operands[i].present = 1;
6007 inst.error = BAD_ARGS;
6012 /* The parse routine should already have set inst.error, but set a
6013 defaut here just in case. */
6015 inst.error = _("syntax error");
6019 /* Do not backtrack over a trailing optional argument that
6020 absorbed some text. We will only fail again, with the
6021 'garbage following instruction' error message, which is
6022 probably less helpful than the current one. */
6023 if (backtrack_index == i && backtrack_pos != str
6024 && upat[i+1] == OP_stop)
6027 inst.error = _("syntax error");
6031 /* Try again, skipping the optional argument at backtrack_pos. */
6032 str = backtrack_pos;
6033 inst.error = backtrack_error;
6034 inst.operands[backtrack_index].present = 0;
6035 i = backtrack_index;
6039 /* Check that we have parsed all the arguments. */
6040 if (*str != '\0' && !inst.error)
6041 inst.error = _("garbage following instruction");
6043 return inst.error ? FAIL : SUCCESS;
6046 #undef po_char_or_fail
6047 #undef po_reg_or_fail
6048 #undef po_reg_or_goto
6049 #undef po_imm_or_fail
6050 #undef po_scalar_or_fail
6052 /* Shorthand macro for instruction encoding functions issuing errors. */
6053 #define constraint(expr, err) do { \
6061 /* Functions for operand encoding. ARM, then Thumb. */
6063 #define rotate_left(v, n) (v << n | v >> (32 - n))
6065 /* If VAL can be encoded in the immediate field of an ARM instruction,
6066 return the encoded form. Otherwise, return FAIL. */
6069 encode_arm_immediate (unsigned int val)
6073 for (i = 0; i < 32; i += 2)
6074 if ((a = rotate_left (val, i)) <= 0xff)
6075 return a | (i << 7); /* 12-bit pack: [shift-cnt,const]. */
6080 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
6081 return the encoded form. Otherwise, return FAIL. */
6083 encode_thumb32_immediate (unsigned int val)
6090 for (i = 1; i <= 24; i++)
6093 if ((val & ~(0xff << i)) == 0)
6094 return ((val >> i) & 0x7f) | ((32 - i) << 7);
6098 if (val == ((a << 16) | a))
6100 if (val == ((a << 24) | (a << 16) | (a << 8) | a))
6104 if (val == ((a << 16) | a))
6105 return 0x200 | (a >> 8);
6109 /* Encode a VFP SP or DP register number into inst.instruction. */
6112 encode_arm_vfp_reg (int reg, enum vfp_reg_pos pos)
6114 if ((pos == VFP_REG_Dd || pos == VFP_REG_Dn || pos == VFP_REG_Dm)
6117 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v3))
6120 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
6123 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
6128 first_error (_("D register out of range for selected VFP version"));
6136 inst.instruction |= ((reg >> 1) << 12) | ((reg & 1) << 22);
6140 inst.instruction |= ((reg >> 1) << 16) | ((reg & 1) << 7);
6144 inst.instruction |= ((reg >> 1) << 0) | ((reg & 1) << 5);
6148 inst.instruction |= ((reg & 15) << 12) | ((reg >> 4) << 22);
6152 inst.instruction |= ((reg & 15) << 16) | ((reg >> 4) << 7);
6156 inst.instruction |= (reg & 15) | ((reg >> 4) << 5);
6164 /* Encode a <shift> in an ARM-format instruction. The immediate,
6165 if any, is handled by md_apply_fix. */
6167 encode_arm_shift (int i)
6169 if (inst.operands[i].shift_kind == SHIFT_RRX)
6170 inst.instruction |= SHIFT_ROR << 5;
6173 inst.instruction |= inst.operands[i].shift_kind << 5;
6174 if (inst.operands[i].immisreg)
6176 inst.instruction |= SHIFT_BY_REG;
6177 inst.instruction |= inst.operands[i].imm << 8;
6180 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
6185 encode_arm_shifter_operand (int i)
6187 if (inst.operands[i].isreg)
6189 inst.instruction |= inst.operands[i].reg;
6190 encode_arm_shift (i);
6193 inst.instruction |= INST_IMMEDIATE;
6196 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
6198 encode_arm_addr_mode_common (int i, bfd_boolean is_t)
6200 assert (inst.operands[i].isreg);
6201 inst.instruction |= inst.operands[i].reg << 16;
6203 if (inst.operands[i].preind)
6207 inst.error = _("instruction does not accept preindexed addressing");
6210 inst.instruction |= PRE_INDEX;
6211 if (inst.operands[i].writeback)
6212 inst.instruction |= WRITE_BACK;
6215 else if (inst.operands[i].postind)
6217 assert (inst.operands[i].writeback);
6219 inst.instruction |= WRITE_BACK;
6221 else /* unindexed - only for coprocessor */
6223 inst.error = _("instruction does not accept unindexed addressing");
6227 if (((inst.instruction & WRITE_BACK) || !(inst.instruction & PRE_INDEX))
6228 && (((inst.instruction & 0x000f0000) >> 16)
6229 == ((inst.instruction & 0x0000f000) >> 12)))
6230 as_warn ((inst.instruction & LOAD_BIT)
6231 ? _("destination register same as write-back base")
6232 : _("source register same as write-back base"));
6235 /* inst.operands[i] was set up by parse_address. Encode it into an
6236 ARM-format mode 2 load or store instruction. If is_t is true,
6237 reject forms that cannot be used with a T instruction (i.e. not
6240 encode_arm_addr_mode_2 (int i, bfd_boolean is_t)
6242 encode_arm_addr_mode_common (i, is_t);
6244 if (inst.operands[i].immisreg)
6246 inst.instruction |= INST_IMMEDIATE; /* yes, this is backwards */
6247 inst.instruction |= inst.operands[i].imm;
6248 if (!inst.operands[i].negative)
6249 inst.instruction |= INDEX_UP;
6250 if (inst.operands[i].shifted)
6252 if (inst.operands[i].shift_kind == SHIFT_RRX)
6253 inst.instruction |= SHIFT_ROR << 5;
6256 inst.instruction |= inst.operands[i].shift_kind << 5;
6257 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
6261 else /* immediate offset in inst.reloc */
6263 if (inst.reloc.type == BFD_RELOC_UNUSED)
6264 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM;
6268 /* inst.operands[i] was set up by parse_address. Encode it into an
6269 ARM-format mode 3 load or store instruction. Reject forms that
6270 cannot be used with such instructions. If is_t is true, reject
6271 forms that cannot be used with a T instruction (i.e. not
6274 encode_arm_addr_mode_3 (int i, bfd_boolean is_t)
6276 if (inst.operands[i].immisreg && inst.operands[i].shifted)
6278 inst.error = _("instruction does not accept scaled register index");
6282 encode_arm_addr_mode_common (i, is_t);
6284 if (inst.operands[i].immisreg)
6286 inst.instruction |= inst.operands[i].imm;
6287 if (!inst.operands[i].negative)
6288 inst.instruction |= INDEX_UP;
6290 else /* immediate offset in inst.reloc */
6292 inst.instruction |= HWOFFSET_IMM;
6293 if (inst.reloc.type == BFD_RELOC_UNUSED)
6294 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
6298 /* inst.operands[i] was set up by parse_address. Encode it into an
6299 ARM-format instruction. Reject all forms which cannot be encoded
6300 into a coprocessor load/store instruction. If wb_ok is false,
6301 reject use of writeback; if unind_ok is false, reject use of
6302 unindexed addressing. If reloc_override is not 0, use it instead
6303 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
6304 (in which case it is preserved). */
6307 encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override)
6309 inst.instruction |= inst.operands[i].reg << 16;
6311 assert (!(inst.operands[i].preind && inst.operands[i].postind));
6313 if (!inst.operands[i].preind && !inst.operands[i].postind) /* unindexed */
6315 assert (!inst.operands[i].writeback);
6318 inst.error = _("instruction does not support unindexed addressing");
6321 inst.instruction |= inst.operands[i].imm;
6322 inst.instruction |= INDEX_UP;
6326 if (inst.operands[i].preind)
6327 inst.instruction |= PRE_INDEX;
6329 if (inst.operands[i].writeback)
6331 if (inst.operands[i].reg == REG_PC)
6333 inst.error = _("pc may not be used with write-back");
6338 inst.error = _("instruction does not support writeback");
6341 inst.instruction |= WRITE_BACK;
6345 inst.reloc.type = reloc_override;
6346 else if ((inst.reloc.type < BFD_RELOC_ARM_ALU_PC_G0_NC
6347 || inst.reloc.type > BFD_RELOC_ARM_LDC_SB_G2)
6348 && inst.reloc.type != BFD_RELOC_ARM_LDR_PC_G0)
6351 inst.reloc.type = BFD_RELOC_ARM_T32_CP_OFF_IMM;
6353 inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM;
6359 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
6360 Determine whether it can be performed with a move instruction; if
6361 it can, convert inst.instruction to that move instruction and
6362 return 1; if it can't, convert inst.instruction to a literal-pool
6363 load and return 0. If this is not a valid thing to do in the
6364 current context, set inst.error and return 1.
6366 inst.operands[i] describes the destination register. */
6369 move_or_literal_pool (int i, bfd_boolean thumb_p, bfd_boolean mode_3)
6374 tbit = (inst.instruction > 0xffff) ? THUMB2_LOAD_BIT : THUMB_LOAD_BIT;
6378 if ((inst.instruction & tbit) == 0)
6380 inst.error = _("invalid pseudo operation");
6383 if (inst.reloc.exp.X_op != O_constant && inst.reloc.exp.X_op != O_symbol)
6385 inst.error = _("constant expression expected");
6388 if (inst.reloc.exp.X_op == O_constant)
6392 if (!unified_syntax && (inst.reloc.exp.X_add_number & ~0xFF) == 0)
6394 /* This can be done with a mov(1) instruction. */
6395 inst.instruction = T_OPCODE_MOV_I8 | (inst.operands[i].reg << 8);
6396 inst.instruction |= inst.reloc.exp.X_add_number;
6402 int value = encode_arm_immediate (inst.reloc.exp.X_add_number);
6405 /* This can be done with a mov instruction. */
6406 inst.instruction &= LITERAL_MASK;
6407 inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT);
6408 inst.instruction |= value & 0xfff;
6412 value = encode_arm_immediate (~inst.reloc.exp.X_add_number);
6415 /* This can be done with a mvn instruction. */
6416 inst.instruction &= LITERAL_MASK;
6417 inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT);
6418 inst.instruction |= value & 0xfff;
6424 if (add_to_lit_pool () == FAIL)
6426 inst.error = _("literal pool insertion failed");
6429 inst.operands[1].reg = REG_PC;
6430 inst.operands[1].isreg = 1;
6431 inst.operands[1].preind = 1;
6432 inst.reloc.pc_rel = 1;
6433 inst.reloc.type = (thumb_p
6434 ? BFD_RELOC_ARM_THUMB_OFFSET
6436 ? BFD_RELOC_ARM_HWLITERAL
6437 : BFD_RELOC_ARM_LITERAL));
6441 /* Functions for instruction encoding, sorted by subarchitecture.
6442 First some generics; their names are taken from the conventional
6443 bit positions for register arguments in ARM format instructions. */
6453 inst.instruction |= inst.operands[0].reg << 12;
6459 inst.instruction |= inst.operands[0].reg << 12;
6460 inst.instruction |= inst.operands[1].reg;
6466 inst.instruction |= inst.operands[0].reg << 12;
6467 inst.instruction |= inst.operands[1].reg << 16;
6473 inst.instruction |= inst.operands[0].reg << 16;
6474 inst.instruction |= inst.operands[1].reg << 12;
6480 unsigned Rn = inst.operands[2].reg;
6481 /* Enforce restrictions on SWP instruction. */
6482 if ((inst.instruction & 0x0fbfffff) == 0x01000090)
6483 constraint (Rn == inst.operands[0].reg || Rn == inst.operands[1].reg,
6484 _("Rn must not overlap other operands"));
6485 inst.instruction |= inst.operands[0].reg << 12;
6486 inst.instruction |= inst.operands[1].reg;
6487 inst.instruction |= Rn << 16;
6493 inst.instruction |= inst.operands[0].reg << 12;
6494 inst.instruction |= inst.operands[1].reg << 16;
6495 inst.instruction |= inst.operands[2].reg;
6501 inst.instruction |= inst.operands[0].reg;
6502 inst.instruction |= inst.operands[1].reg << 12;
6503 inst.instruction |= inst.operands[2].reg << 16;
6509 inst.instruction |= inst.operands[0].imm;
6515 inst.instruction |= inst.operands[0].reg << 12;
6516 encode_arm_cp_address (1, TRUE, TRUE, 0);
6519 /* ARM instructions, in alphabetical order by function name (except
6520 that wrapper functions appear immediately after the function they
6523 /* This is a pseudo-op of the form "adr rd, label" to be converted
6524 into a relative address of the form "add rd, pc, #label-.-8". */
6529 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
6531 /* Frag hacking will turn this into a sub instruction if the offset turns
6532 out to be negative. */
6533 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
6534 inst.reloc.pc_rel = 1;
6535 inst.reloc.exp.X_add_number -= 8;
6538 /* This is a pseudo-op of the form "adrl rd, label" to be converted
6539 into a relative address of the form:
6540 add rd, pc, #low(label-.-8)"
6541 add rd, rd, #high(label-.-8)" */
6546 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
6548 /* Frag hacking will turn this into a sub instruction if the offset turns
6549 out to be negative. */
6550 inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE;
6551 inst.reloc.pc_rel = 1;
6552 inst.size = INSN_SIZE * 2;
6553 inst.reloc.exp.X_add_number -= 8;
6559 if (!inst.operands[1].present)
6560 inst.operands[1].reg = inst.operands[0].reg;
6561 inst.instruction |= inst.operands[0].reg << 12;
6562 inst.instruction |= inst.operands[1].reg << 16;
6563 encode_arm_shifter_operand (2);
6569 if (inst.operands[0].present)
6571 constraint ((inst.instruction & 0xf0) != 0x40
6572 && inst.operands[0].imm != 0xf,
6573 "bad barrier type");
6574 inst.instruction |= inst.operands[0].imm;
6577 inst.instruction |= 0xf;
6583 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
6584 constraint (msb > 32, _("bit-field extends past end of register"));
6585 /* The instruction encoding stores the LSB and MSB,
6586 not the LSB and width. */
6587 inst.instruction |= inst.operands[0].reg << 12;
6588 inst.instruction |= inst.operands[1].imm << 7;
6589 inst.instruction |= (msb - 1) << 16;
6597 /* #0 in second position is alternative syntax for bfc, which is
6598 the same instruction but with REG_PC in the Rm field. */
6599 if (!inst.operands[1].isreg)
6600 inst.operands[1].reg = REG_PC;
6602 msb = inst.operands[2].imm + inst.operands[3].imm;
6603 constraint (msb > 32, _("bit-field extends past end of register"));
6604 /* The instruction encoding stores the LSB and MSB,
6605 not the LSB and width. */
6606 inst.instruction |= inst.operands[0].reg << 12;
6607 inst.instruction |= inst.operands[1].reg;
6608 inst.instruction |= inst.operands[2].imm << 7;
6609 inst.instruction |= (msb - 1) << 16;
6615 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
6616 _("bit-field extends past end of register"));
6617 inst.instruction |= inst.operands[0].reg << 12;
6618 inst.instruction |= inst.operands[1].reg;
6619 inst.instruction |= inst.operands[2].imm << 7;
6620 inst.instruction |= (inst.operands[3].imm - 1) << 16;
6623 /* ARM V5 breakpoint instruction (argument parse)
6624 BKPT <16 bit unsigned immediate>
6625 Instruction is not conditional.
6626 The bit pattern given in insns[] has the COND_ALWAYS condition,
6627 and it is an error if the caller tried to override that. */
6632 /* Top 12 of 16 bits to bits 19:8. */
6633 inst.instruction |= (inst.operands[0].imm & 0xfff0) << 4;
6635 /* Bottom 4 of 16 bits to bits 3:0. */
6636 inst.instruction |= inst.operands[0].imm & 0xf;
6640 encode_branch (int default_reloc)
6642 if (inst.operands[0].hasreloc)
6644 constraint (inst.operands[0].imm != BFD_RELOC_ARM_PLT32,
6645 _("the only suffix valid here is '(plt)'"));
6646 inst.reloc.type = BFD_RELOC_ARM_PLT32;
6650 inst.reloc.type = default_reloc;
6652 inst.reloc.pc_rel = 1;
6659 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
6660 encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
6663 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
6670 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
6672 if (inst.cond == COND_ALWAYS)
6673 encode_branch (BFD_RELOC_ARM_PCREL_CALL);
6675 encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
6679 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
6682 /* ARM V5 branch-link-exchange instruction (argument parse)
6683 BLX <target_addr> ie BLX(1)
6684 BLX{<condition>} <Rm> ie BLX(2)
6685 Unfortunately, there are two different opcodes for this mnemonic.
6686 So, the insns[].value is not used, and the code here zaps values
6687 into inst.instruction.
6688 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
6693 if (inst.operands[0].isreg)
6695 /* Arg is a register; the opcode provided by insns[] is correct.
6696 It is not illegal to do "blx pc", just useless. */
6697 if (inst.operands[0].reg == REG_PC)
6698 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
6700 inst.instruction |= inst.operands[0].reg;
6704 /* Arg is an address; this instruction cannot be executed
6705 conditionally, and the opcode must be adjusted. */
6706 constraint (inst.cond != COND_ALWAYS, BAD_COND);
6707 inst.instruction = 0xfa000000;
6709 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
6710 encode_branch (BFD_RELOC_ARM_PCREL_CALL);
6713 encode_branch (BFD_RELOC_ARM_PCREL_BLX);
6720 if (inst.operands[0].reg == REG_PC)
6721 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
6723 inst.instruction |= inst.operands[0].reg;
6727 /* ARM v5TEJ. Jump to Jazelle code. */
6732 if (inst.operands[0].reg == REG_PC)
6733 as_tsktsk (_("use of r15 in bxj is not really useful"));
6735 inst.instruction |= inst.operands[0].reg;
6738 /* Co-processor data operation:
6739 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
6740 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
6744 inst.instruction |= inst.operands[0].reg << 8;
6745 inst.instruction |= inst.operands[1].imm << 20;
6746 inst.instruction |= inst.operands[2].reg << 12;
6747 inst.instruction |= inst.operands[3].reg << 16;
6748 inst.instruction |= inst.operands[4].reg;
6749 inst.instruction |= inst.operands[5].imm << 5;
6755 inst.instruction |= inst.operands[0].reg << 16;
6756 encode_arm_shifter_operand (1);
6759 /* Transfer between coprocessor and ARM registers.
6760 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
6765 No special properties. */
6770 inst.instruction |= inst.operands[0].reg << 8;
6771 inst.instruction |= inst.operands[1].imm << 21;
6772 inst.instruction |= inst.operands[2].reg << 12;
6773 inst.instruction |= inst.operands[3].reg << 16;
6774 inst.instruction |= inst.operands[4].reg;
6775 inst.instruction |= inst.operands[5].imm << 5;
6778 /* Transfer between coprocessor register and pair of ARM registers.
6779 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
6784 Two XScale instructions are special cases of these:
6786 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
6787 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
6789 Result unpredicatable if Rd or Rn is R15. */
6794 inst.instruction |= inst.operands[0].reg << 8;
6795 inst.instruction |= inst.operands[1].imm << 4;
6796 inst.instruction |= inst.operands[2].reg << 12;
6797 inst.instruction |= inst.operands[3].reg << 16;
6798 inst.instruction |= inst.operands[4].reg;
6804 inst.instruction |= inst.operands[0].imm << 6;
6805 if (inst.operands[1].present)
6807 inst.instruction |= CPSI_MMOD;
6808 inst.instruction |= inst.operands[1].imm;
6815 inst.instruction |= inst.operands[0].imm;
6821 /* There is no IT instruction in ARM mode. We
6822 process it but do not generate code for it. */
6829 int base_reg = inst.operands[0].reg;
6830 int range = inst.operands[1].imm;
6832 inst.instruction |= base_reg << 16;
6833 inst.instruction |= range;
6835 if (inst.operands[1].writeback)
6836 inst.instruction |= LDM_TYPE_2_OR_3;
6838 if (inst.operands[0].writeback)
6840 inst.instruction |= WRITE_BACK;
6841 /* Check for unpredictable uses of writeback. */
6842 if (inst.instruction & LOAD_BIT)
6844 /* Not allowed in LDM type 2. */
6845 if ((inst.instruction & LDM_TYPE_2_OR_3)
6846 && ((range & (1 << REG_PC)) == 0))
6847 as_warn (_("writeback of base register is UNPREDICTABLE"));
6848 /* Only allowed if base reg not in list for other types. */
6849 else if (range & (1 << base_reg))
6850 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
6854 /* Not allowed for type 2. */
6855 if (inst.instruction & LDM_TYPE_2_OR_3)
6856 as_warn (_("writeback of base register is UNPREDICTABLE"));
6857 /* Only allowed if base reg not in list, or first in list. */
6858 else if ((range & (1 << base_reg))
6859 && (range & ((1 << base_reg) - 1)))
6860 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
6865 /* ARMv5TE load-consecutive (argument parse)
6874 constraint (inst.operands[0].reg % 2 != 0,
6875 _("first destination register must be even"));
6876 constraint (inst.operands[1].present
6877 && inst.operands[1].reg != inst.operands[0].reg + 1,
6878 _("can only load two consecutive registers"));
6879 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
6880 constraint (!inst.operands[2].isreg, _("'[' expected"));
6882 if (!inst.operands[1].present)
6883 inst.operands[1].reg = inst.operands[0].reg + 1;
6885 if (inst.instruction & LOAD_BIT)
6887 /* encode_arm_addr_mode_3 will diagnose overlap between the base
6888 register and the first register written; we have to diagnose
6889 overlap between the base and the second register written here. */
6891 if (inst.operands[2].reg == inst.operands[1].reg
6892 && (inst.operands[2].writeback || inst.operands[2].postind))
6893 as_warn (_("base register written back, and overlaps "
6894 "second destination register"));
6896 /* For an index-register load, the index register must not overlap the
6897 destination (even if not write-back). */
6898 else if (inst.operands[2].immisreg
6899 && ((unsigned) inst.operands[2].imm == inst.operands[0].reg
6900 || (unsigned) inst.operands[2].imm == inst.operands[1].reg))
6901 as_warn (_("index register overlaps destination register"));
6904 inst.instruction |= inst.operands[0].reg << 12;
6905 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE);
6911 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
6912 || inst.operands[1].postind || inst.operands[1].writeback
6913 || inst.operands[1].immisreg || inst.operands[1].shifted
6914 || inst.operands[1].negative
6915 /* This can arise if the programmer has written
6917 or if they have mistakenly used a register name as the last
6920 It is very difficult to distinguish between these two cases
6921 because "rX" might actually be a label. ie the register
6922 name has been occluded by a symbol of the same name. So we
6923 just generate a general 'bad addressing mode' type error
6924 message and leave it up to the programmer to discover the
6925 true cause and fix their mistake. */
6926 || (inst.operands[1].reg == REG_PC),
6929 constraint (inst.reloc.exp.X_op != O_constant
6930 || inst.reloc.exp.X_add_number != 0,
6931 _("offset must be zero in ARM encoding"));
6933 inst.instruction |= inst.operands[0].reg << 12;
6934 inst.instruction |= inst.operands[1].reg << 16;
6935 inst.reloc.type = BFD_RELOC_UNUSED;
6941 constraint (inst.operands[0].reg % 2 != 0,
6942 _("even register required"));
6943 constraint (inst.operands[1].present
6944 && inst.operands[1].reg != inst.operands[0].reg + 1,
6945 _("can only load two consecutive registers"));
6946 /* If op 1 were present and equal to PC, this function wouldn't
6947 have been called in the first place. */
6948 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
6950 inst.instruction |= inst.operands[0].reg << 12;
6951 inst.instruction |= inst.operands[2].reg << 16;
6957 inst.instruction |= inst.operands[0].reg << 12;
6958 if (!inst.operands[1].isreg)
6959 if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/FALSE))
6961 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE);
6967 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
6969 if (inst.operands[1].preind)
6971 constraint (inst.reloc.exp.X_op != O_constant ||
6972 inst.reloc.exp.X_add_number != 0,
6973 _("this instruction requires a post-indexed address"));
6975 inst.operands[1].preind = 0;
6976 inst.operands[1].postind = 1;
6977 inst.operands[1].writeback = 1;
6979 inst.instruction |= inst.operands[0].reg << 12;
6980 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE);
6983 /* Halfword and signed-byte load/store operations. */
6988 inst.instruction |= inst.operands[0].reg << 12;
6989 if (!inst.operands[1].isreg)
6990 if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/TRUE))
6992 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE);
6998 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7000 if (inst.operands[1].preind)
7002 constraint (inst.reloc.exp.X_op != O_constant ||
7003 inst.reloc.exp.X_add_number != 0,
7004 _("this instruction requires a post-indexed address"));
7006 inst.operands[1].preind = 0;
7007 inst.operands[1].postind = 1;
7008 inst.operands[1].writeback = 1;
7010 inst.instruction |= inst.operands[0].reg << 12;
7011 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE);
7014 /* Co-processor register load/store.
7015 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
7019 inst.instruction |= inst.operands[0].reg << 8;
7020 inst.instruction |= inst.operands[1].reg << 12;
7021 encode_arm_cp_address (2, TRUE, TRUE, 0);
7027 /* This restriction does not apply to mls (nor to mla in v6 or later). */
7028 if (inst.operands[0].reg == inst.operands[1].reg
7029 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)
7030 && !(inst.instruction & 0x00400000))
7031 as_tsktsk (_("Rd and Rm should be different in mla"));
7033 inst.instruction |= inst.operands[0].reg << 16;
7034 inst.instruction |= inst.operands[1].reg;
7035 inst.instruction |= inst.operands[2].reg << 8;
7036 inst.instruction |= inst.operands[3].reg << 12;
7042 inst.instruction |= inst.operands[0].reg << 12;
7043 encode_arm_shifter_operand (1);
7046 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
7053 top = (inst.instruction & 0x00400000) != 0;
7054 constraint (top && inst.reloc.type == BFD_RELOC_ARM_MOVW,
7055 _(":lower16: not allowed this instruction"));
7056 constraint (!top && inst.reloc.type == BFD_RELOC_ARM_MOVT,
7057 _(":upper16: not allowed instruction"));
7058 inst.instruction |= inst.operands[0].reg << 12;
7059 if (inst.reloc.type == BFD_RELOC_UNUSED)
7061 imm = inst.reloc.exp.X_add_number;
7062 /* The value is in two pieces: 0:11, 16:19. */
7063 inst.instruction |= (imm & 0x00000fff);
7064 inst.instruction |= (imm & 0x0000f000) << 4;
7068 static void do_vfp_nsyn_opcode (const char *);
7071 do_vfp_nsyn_mrs (void)
7073 if (inst.operands[0].isvec)
7075 if (inst.operands[1].reg != 1)
7076 first_error (_("operand 1 must be FPSCR"));
7077 memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
7078 memset (&inst.operands[1], '\0', sizeof (inst.operands[1]));
7079 do_vfp_nsyn_opcode ("fmstat");
7081 else if (inst.operands[1].isvec)
7082 do_vfp_nsyn_opcode ("fmrx");
7090 do_vfp_nsyn_msr (void)
7092 if (inst.operands[0].isvec)
7093 do_vfp_nsyn_opcode ("fmxr");
7105 /* The destination register can be r0-r14 or APSR_nzcv */
7106 if (inst.operands[0].reg > 14)
7108 inst.error = BAD_PC;
7112 /* If the destination is r13 and not in ARM mode then unprefictable */
7113 if (thumb_mode && inst.operands[0].reg == REG_SP)
7115 inst.error = BAD_SP;
7119 /* If the destination is APSR_nzcv */
7120 if (inst.operands[0].isvec && inst.operands[1].reg != 1)
7122 inst.error = BAD_VMRS;
7126 if (inst.operands[0].isvec)
7129 rt = inst.operands[0].reg;
7131 /* Or in the registers to use */
7132 inst.instruction |= rt << 12;
7133 inst.instruction |= inst.operands[1].reg << 16;
7139 /* The destination register can be r0-r14 or APSR_nzcv */
7140 if (inst.operands[1].reg > 14)
7142 inst.error = BAD_PC;
7146 /* If the destination is r13 and not in ARM mode then unprefictable */
7147 if (thumb_mode && inst.operands[0].reg == REG_SP)
7149 inst.error = BAD_SP;
7153 /* Or in the registers to use */
7154 inst.instruction |= inst.operands[1].reg << 12;
7155 inst.instruction |= inst.operands[0].reg << 16;
7161 if (do_vfp_nsyn_mrs () == SUCCESS)
7164 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
7165 constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f))
7167 _("'CPSR' or 'SPSR' expected"));
7168 inst.instruction |= inst.operands[0].reg << 12;
7169 inst.instruction |= (inst.operands[1].imm & SPSR_BIT);
7172 /* Two possible forms:
7173 "{C|S}PSR_<field>, Rm",
7174 "{C|S}PSR_f, #expression". */
7179 if (do_vfp_nsyn_msr () == SUCCESS)
7182 inst.instruction |= inst.operands[0].imm;
7183 if (inst.operands[1].isreg)
7184 inst.instruction |= inst.operands[1].reg;
7187 inst.instruction |= INST_IMMEDIATE;
7188 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
7189 inst.reloc.pc_rel = 0;
7196 if (!inst.operands[2].present)
7197 inst.operands[2].reg = inst.operands[0].reg;
7198 inst.instruction |= inst.operands[0].reg << 16;
7199 inst.instruction |= inst.operands[1].reg;
7200 inst.instruction |= inst.operands[2].reg << 8;
7202 if (inst.operands[0].reg == inst.operands[1].reg
7203 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
7204 as_tsktsk (_("Rd and Rm should be different in mul"));
7207 /* Long Multiply Parser
7208 UMULL RdLo, RdHi, Rm, Rs
7209 SMULL RdLo, RdHi, Rm, Rs
7210 UMLAL RdLo, RdHi, Rm, Rs
7211 SMLAL RdLo, RdHi, Rm, Rs. */
7216 inst.instruction |= inst.operands[0].reg << 12;
7217 inst.instruction |= inst.operands[1].reg << 16;
7218 inst.instruction |= inst.operands[2].reg;
7219 inst.instruction |= inst.operands[3].reg << 8;
7221 /* rdhi, rdlo and rm must all be different prior to ARMv6. */
7222 if (inst.operands[0].reg == inst.operands[1].reg
7223 || ((inst.operands[0].reg == inst.operands[2].reg
7224 || inst.operands[1].reg == inst.operands[2].reg)
7225 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)))
7226 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
7232 if (inst.operands[0].present)
7234 /* Architectural NOP hints are CPSR sets with no bits selected. */
7235 inst.instruction &= 0xf0000000;
7236 inst.instruction |= 0x0320f000 + inst.operands[0].imm;
7240 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
7241 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
7242 Condition defaults to COND_ALWAYS.
7243 Error if Rd, Rn or Rm are R15. */
7248 inst.instruction |= inst.operands[0].reg << 12;
7249 inst.instruction |= inst.operands[1].reg << 16;
7250 inst.instruction |= inst.operands[2].reg;
7251 if (inst.operands[3].present)
7252 encode_arm_shift (3);
7255 /* ARM V6 PKHTB (Argument Parse). */
7260 if (!inst.operands[3].present)
7262 /* If the shift specifier is omitted, turn the instruction
7263 into pkhbt rd, rm, rn. */
7264 inst.instruction &= 0xfff00010;
7265 inst.instruction |= inst.operands[0].reg << 12;
7266 inst.instruction |= inst.operands[1].reg;
7267 inst.instruction |= inst.operands[2].reg << 16;
7271 inst.instruction |= inst.operands[0].reg << 12;
7272 inst.instruction |= inst.operands[1].reg << 16;
7273 inst.instruction |= inst.operands[2].reg;
7274 encode_arm_shift (3);
7278 /* ARMv5TE: Preload-Cache
7282 Syntactically, like LDR with B=1, W=0, L=1. */
7287 constraint (!inst.operands[0].isreg,
7288 _("'[' expected after PLD mnemonic"));
7289 constraint (inst.operands[0].postind,
7290 _("post-indexed expression used in preload instruction"));
7291 constraint (inst.operands[0].writeback,
7292 _("writeback used in preload instruction"));
7293 constraint (!inst.operands[0].preind,
7294 _("unindexed addressing used in preload instruction"));
7295 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
7298 /* ARMv7: PLI <addr_mode> */
7302 constraint (!inst.operands[0].isreg,
7303 _("'[' expected after PLI mnemonic"));
7304 constraint (inst.operands[0].postind,
7305 _("post-indexed expression used in preload instruction"));
7306 constraint (inst.operands[0].writeback,
7307 _("writeback used in preload instruction"));
7308 constraint (!inst.operands[0].preind,
7309 _("unindexed addressing used in preload instruction"));
7310 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
7311 inst.instruction &= ~PRE_INDEX;
7317 inst.operands[1] = inst.operands[0];
7318 memset (&inst.operands[0], 0, sizeof inst.operands[0]);
7319 inst.operands[0].isreg = 1;
7320 inst.operands[0].writeback = 1;
7321 inst.operands[0].reg = REG_SP;
7325 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
7326 word at the specified address and the following word
7328 Unconditionally executed.
7329 Error if Rn is R15. */
7334 inst.instruction |= inst.operands[0].reg << 16;
7335 if (inst.operands[0].writeback)
7336 inst.instruction |= WRITE_BACK;
7339 /* ARM V6 ssat (argument parse). */
7344 inst.instruction |= inst.operands[0].reg << 12;
7345 inst.instruction |= (inst.operands[1].imm - 1) << 16;
7346 inst.instruction |= inst.operands[2].reg;
7348 if (inst.operands[3].present)
7349 encode_arm_shift (3);
7352 /* ARM V6 usat (argument parse). */
7357 inst.instruction |= inst.operands[0].reg << 12;
7358 inst.instruction |= inst.operands[1].imm << 16;
7359 inst.instruction |= inst.operands[2].reg;
7361 if (inst.operands[3].present)
7362 encode_arm_shift (3);
7365 /* ARM V6 ssat16 (argument parse). */
7370 inst.instruction |= inst.operands[0].reg << 12;
7371 inst.instruction |= ((inst.operands[1].imm - 1) << 16);
7372 inst.instruction |= inst.operands[2].reg;
7378 inst.instruction |= inst.operands[0].reg << 12;
7379 inst.instruction |= inst.operands[1].imm << 16;
7380 inst.instruction |= inst.operands[2].reg;
7383 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
7384 preserving the other bits.
7386 setend <endian_specifier>, where <endian_specifier> is either
7392 if (inst.operands[0].imm)
7393 inst.instruction |= 0x200;
7399 unsigned int Rm = (inst.operands[1].present
7400 ? inst.operands[1].reg
7401 : inst.operands[0].reg);
7403 inst.instruction |= inst.operands[0].reg << 12;
7404 inst.instruction |= Rm;
7405 if (inst.operands[2].isreg) /* Rd, {Rm,} Rs */
7407 inst.instruction |= inst.operands[2].reg << 8;
7408 inst.instruction |= SHIFT_BY_REG;
7411 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
7417 inst.reloc.type = BFD_RELOC_ARM_SMC;
7418 inst.reloc.pc_rel = 0;
7424 inst.reloc.type = BFD_RELOC_ARM_SWI;
7425 inst.reloc.pc_rel = 0;
7428 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
7429 SMLAxy{cond} Rd,Rm,Rs,Rn
7430 SMLAWy{cond} Rd,Rm,Rs,Rn
7431 Error if any register is R15. */
7436 inst.instruction |= inst.operands[0].reg << 16;
7437 inst.instruction |= inst.operands[1].reg;
7438 inst.instruction |= inst.operands[2].reg << 8;
7439 inst.instruction |= inst.operands[3].reg << 12;
7442 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
7443 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
7444 Error if any register is R15.
7445 Warning if Rdlo == Rdhi. */
7450 inst.instruction |= inst.operands[0].reg << 12;
7451 inst.instruction |= inst.operands[1].reg << 16;
7452 inst.instruction |= inst.operands[2].reg;
7453 inst.instruction |= inst.operands[3].reg << 8;
7455 if (inst.operands[0].reg == inst.operands[1].reg)
7456 as_tsktsk (_("rdhi and rdlo must be different"));
7459 /* ARM V5E (El Segundo) signed-multiply (argument parse)
7460 SMULxy{cond} Rd,Rm,Rs
7461 Error if any register is R15. */
7466 inst.instruction |= inst.operands[0].reg << 16;
7467 inst.instruction |= inst.operands[1].reg;
7468 inst.instruction |= inst.operands[2].reg << 8;
7471 /* ARM V6 srs (argument parse). The variable fields in the encoding are
7472 the same for both ARM and Thumb-2. */
7479 if (inst.operands[0].present)
7481 reg = inst.operands[0].reg;
7482 constraint (reg != 13, _("SRS base register must be r13"));
7487 inst.instruction |= reg << 16;
7488 inst.instruction |= inst.operands[1].imm;
7489 if (inst.operands[0].writeback || inst.operands[1].writeback)
7490 inst.instruction |= WRITE_BACK;
7493 /* ARM V6 strex (argument parse). */
7498 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
7499 || inst.operands[2].postind || inst.operands[2].writeback
7500 || inst.operands[2].immisreg || inst.operands[2].shifted
7501 || inst.operands[2].negative
7502 /* See comment in do_ldrex(). */
7503 || (inst.operands[2].reg == REG_PC),
7506 constraint (inst.operands[0].reg == inst.operands[1].reg
7507 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
7509 constraint (inst.reloc.exp.X_op != O_constant
7510 || inst.reloc.exp.X_add_number != 0,
7511 _("offset must be zero in ARM encoding"));
7513 inst.instruction |= inst.operands[0].reg << 12;
7514 inst.instruction |= inst.operands[1].reg;
7515 inst.instruction |= inst.operands[2].reg << 16;
7516 inst.reloc.type = BFD_RELOC_UNUSED;
7522 constraint (inst.operands[1].reg % 2 != 0,
7523 _("even register required"));
7524 constraint (inst.operands[2].present
7525 && inst.operands[2].reg != inst.operands[1].reg + 1,
7526 _("can only store two consecutive registers"));
7527 /* If op 2 were present and equal to PC, this function wouldn't
7528 have been called in the first place. */
7529 constraint (inst.operands[1].reg == REG_LR, _("r14 not allowed here"));
7531 constraint (inst.operands[0].reg == inst.operands[1].reg
7532 || inst.operands[0].reg == inst.operands[1].reg + 1
7533 || inst.operands[0].reg == inst.operands[3].reg,
7536 inst.instruction |= inst.operands[0].reg << 12;
7537 inst.instruction |= inst.operands[1].reg;
7538 inst.instruction |= inst.operands[3].reg << 16;
7541 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
7542 extends it to 32-bits, and adds the result to a value in another
7543 register. You can specify a rotation by 0, 8, 16, or 24 bits
7544 before extracting the 16-bit value.
7545 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
7546 Condition defaults to COND_ALWAYS.
7547 Error if any register uses R15. */
7552 inst.instruction |= inst.operands[0].reg << 12;
7553 inst.instruction |= inst.operands[1].reg << 16;
7554 inst.instruction |= inst.operands[2].reg;
7555 inst.instruction |= inst.operands[3].imm << 10;
7560 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
7561 Condition defaults to COND_ALWAYS.
7562 Error if any register uses R15. */
7567 inst.instruction |= inst.operands[0].reg << 12;
7568 inst.instruction |= inst.operands[1].reg;
7569 inst.instruction |= inst.operands[2].imm << 10;
7572 /* VFP instructions. In a logical order: SP variant first, monad
7573 before dyad, arithmetic then move then load/store. */
7576 do_vfp_sp_monadic (void)
7578 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
7579 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
7583 do_vfp_sp_dyadic (void)
7585 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
7586 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
7587 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
7591 do_vfp_sp_compare_z (void)
7593 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
7597 do_vfp_dp_sp_cvt (void)
7599 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
7600 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
7604 do_vfp_sp_dp_cvt (void)
7606 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
7607 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
7611 do_vfp_reg_from_sp (void)
7613 inst.instruction |= inst.operands[0].reg << 12;
7614 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
7618 do_vfp_reg2_from_sp2 (void)
7620 constraint (inst.operands[2].imm != 2,
7621 _("only two consecutive VFP SP registers allowed here"));
7622 inst.instruction |= inst.operands[0].reg << 12;
7623 inst.instruction |= inst.operands[1].reg << 16;
7624 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
7628 do_vfp_sp_from_reg (void)
7630 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sn);
7631 inst.instruction |= inst.operands[1].reg << 12;
7635 do_vfp_sp2_from_reg2 (void)
7637 constraint (inst.operands[0].imm != 2,
7638 _("only two consecutive VFP SP registers allowed here"));
7639 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sm);
7640 inst.instruction |= inst.operands[1].reg << 12;
7641 inst.instruction |= inst.operands[2].reg << 16;
7645 do_vfp_sp_ldst (void)
7647 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
7648 encode_arm_cp_address (1, FALSE, TRUE, 0);
7652 do_vfp_dp_ldst (void)
7654 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
7655 encode_arm_cp_address (1, FALSE, TRUE, 0);
7660 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type)
7662 if (inst.operands[0].writeback)
7663 inst.instruction |= WRITE_BACK;
7665 constraint (ldstm_type != VFP_LDSTMIA,
7666 _("this addressing mode requires base-register writeback"));
7667 inst.instruction |= inst.operands[0].reg << 16;
7668 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sd);
7669 inst.instruction |= inst.operands[1].imm;
7673 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type)
7677 if (inst.operands[0].writeback)
7678 inst.instruction |= WRITE_BACK;
7680 constraint (ldstm_type != VFP_LDSTMIA && ldstm_type != VFP_LDSTMIAX,
7681 _("this addressing mode requires base-register writeback"));
7683 inst.instruction |= inst.operands[0].reg << 16;
7684 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
7686 count = inst.operands[1].imm << 1;
7687 if (ldstm_type == VFP_LDSTMIAX || ldstm_type == VFP_LDSTMDBX)
7690 inst.instruction |= count;
7694 do_vfp_sp_ldstmia (void)
7696 vfp_sp_ldstm (VFP_LDSTMIA);
7700 do_vfp_sp_ldstmdb (void)
7702 vfp_sp_ldstm (VFP_LDSTMDB);
7706 do_vfp_dp_ldstmia (void)
7708 vfp_dp_ldstm (VFP_LDSTMIA);
7712 do_vfp_dp_ldstmdb (void)
7714 vfp_dp_ldstm (VFP_LDSTMDB);
7718 do_vfp_xp_ldstmia (void)
7720 vfp_dp_ldstm (VFP_LDSTMIAX);
7724 do_vfp_xp_ldstmdb (void)
7726 vfp_dp_ldstm (VFP_LDSTMDBX);
7730 do_vfp_dp_rd_rm (void)
7732 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
7733 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
7737 do_vfp_dp_rn_rd (void)
7739 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dn);
7740 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
7744 do_vfp_dp_rd_rn (void)
7746 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
7747 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
7751 do_vfp_dp_rd_rn_rm (void)
7753 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
7754 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
7755 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dm);
7761 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
7765 do_vfp_dp_rm_rd_rn (void)
7767 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dm);
7768 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
7769 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dn);
7772 /* VFPv3 instructions. */
7774 do_vfp_sp_const (void)
7776 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
7777 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
7778 inst.instruction |= (inst.operands[1].imm & 0x0f);
7782 do_vfp_dp_const (void)
7784 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
7785 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
7786 inst.instruction |= (inst.operands[1].imm & 0x0f);
7790 vfp_conv (int srcsize)
7792 unsigned immbits = srcsize - inst.operands[1].imm;
7793 inst.instruction |= (immbits & 1) << 5;
7794 inst.instruction |= (immbits >> 1);
7798 do_vfp_sp_conv_16 (void)
7800 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
7805 do_vfp_dp_conv_16 (void)
7807 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
7812 do_vfp_sp_conv_32 (void)
7814 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
7819 do_vfp_dp_conv_32 (void)
7821 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
7826 /* FPA instructions. Also in a logical order. */
7831 inst.instruction |= inst.operands[0].reg << 16;
7832 inst.instruction |= inst.operands[1].reg;
7836 do_fpa_ldmstm (void)
7838 inst.instruction |= inst.operands[0].reg << 12;
7839 switch (inst.operands[1].imm)
7841 case 1: inst.instruction |= CP_T_X; break;
7842 case 2: inst.instruction |= CP_T_Y; break;
7843 case 3: inst.instruction |= CP_T_Y | CP_T_X; break;
7848 if (inst.instruction & (PRE_INDEX | INDEX_UP))
7850 /* The instruction specified "ea" or "fd", so we can only accept
7851 [Rn]{!}. The instruction does not really support stacking or
7852 unstacking, so we have to emulate these by setting appropriate
7853 bits and offsets. */
7854 constraint (inst.reloc.exp.X_op != O_constant
7855 || inst.reloc.exp.X_add_number != 0,
7856 _("this instruction does not support indexing"));
7858 if ((inst.instruction & PRE_INDEX) || inst.operands[2].writeback)
7859 inst.reloc.exp.X_add_number = 12 * inst.operands[1].imm;
7861 if (!(inst.instruction & INDEX_UP))
7862 inst.reloc.exp.X_add_number = -inst.reloc.exp.X_add_number;
7864 if (!(inst.instruction & PRE_INDEX) && inst.operands[2].writeback)
7866 inst.operands[2].preind = 0;
7867 inst.operands[2].postind = 1;
7871 encode_arm_cp_address (2, TRUE, TRUE, 0);
7875 /* iWMMXt instructions: strictly in alphabetical order. */
7878 do_iwmmxt_tandorc (void)
7880 constraint (inst.operands[0].reg != REG_PC, _("only r15 allowed here"));
7884 do_iwmmxt_textrc (void)
7886 inst.instruction |= inst.operands[0].reg << 12;
7887 inst.instruction |= inst.operands[1].imm;
7891 do_iwmmxt_textrm (void)
7893 inst.instruction |= inst.operands[0].reg << 12;
7894 inst.instruction |= inst.operands[1].reg << 16;
7895 inst.instruction |= inst.operands[2].imm;
7899 do_iwmmxt_tinsr (void)
7901 inst.instruction |= inst.operands[0].reg << 16;
7902 inst.instruction |= inst.operands[1].reg << 12;
7903 inst.instruction |= inst.operands[2].imm;
7907 do_iwmmxt_tmia (void)
7909 inst.instruction |= inst.operands[0].reg << 5;
7910 inst.instruction |= inst.operands[1].reg;
7911 inst.instruction |= inst.operands[2].reg << 12;
7915 do_iwmmxt_waligni (void)
7917 inst.instruction |= inst.operands[0].reg << 12;
7918 inst.instruction |= inst.operands[1].reg << 16;
7919 inst.instruction |= inst.operands[2].reg;
7920 inst.instruction |= inst.operands[3].imm << 20;
7924 do_iwmmxt_wmerge (void)
7926 inst.instruction |= inst.operands[0].reg << 12;
7927 inst.instruction |= inst.operands[1].reg << 16;
7928 inst.instruction |= inst.operands[2].reg;
7929 inst.instruction |= inst.operands[3].imm << 21;
7933 do_iwmmxt_wmov (void)
7935 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
7936 inst.instruction |= inst.operands[0].reg << 12;
7937 inst.instruction |= inst.operands[1].reg << 16;
7938 inst.instruction |= inst.operands[1].reg;
7942 do_iwmmxt_wldstbh (void)
7945 inst.instruction |= inst.operands[0].reg << 12;
7947 reloc = BFD_RELOC_ARM_T32_CP_OFF_IMM_S2;
7949 reloc = BFD_RELOC_ARM_CP_OFF_IMM_S2;
7950 encode_arm_cp_address (1, TRUE, FALSE, reloc);
7954 do_iwmmxt_wldstw (void)
7956 /* RIWR_RIWC clears .isreg for a control register. */
7957 if (!inst.operands[0].isreg)
7959 constraint (inst.cond != COND_ALWAYS, BAD_COND);
7960 inst.instruction |= 0xf0000000;
7963 inst.instruction |= inst.operands[0].reg << 12;
7964 encode_arm_cp_address (1, TRUE, TRUE, 0);
7968 do_iwmmxt_wldstd (void)
7970 inst.instruction |= inst.operands[0].reg << 12;
7971 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2)
7972 && inst.operands[1].immisreg)
7974 inst.instruction &= ~0x1a000ff;
7975 inst.instruction |= (0xf << 28);
7976 if (inst.operands[1].preind)
7977 inst.instruction |= PRE_INDEX;
7978 if (!inst.operands[1].negative)
7979 inst.instruction |= INDEX_UP;
7980 if (inst.operands[1].writeback)
7981 inst.instruction |= WRITE_BACK;
7982 inst.instruction |= inst.operands[1].reg << 16;
7983 inst.instruction |= inst.reloc.exp.X_add_number << 4;
7984 inst.instruction |= inst.operands[1].imm;
7987 encode_arm_cp_address (1, TRUE, FALSE, 0);
7991 do_iwmmxt_wshufh (void)
7993 inst.instruction |= inst.operands[0].reg << 12;
7994 inst.instruction |= inst.operands[1].reg << 16;
7995 inst.instruction |= ((inst.operands[2].imm & 0xf0) << 16);
7996 inst.instruction |= (inst.operands[2].imm & 0x0f);
8000 do_iwmmxt_wzero (void)
8002 /* WZERO reg is an alias for WANDN reg, reg, reg. */
8003 inst.instruction |= inst.operands[0].reg;
8004 inst.instruction |= inst.operands[0].reg << 12;
8005 inst.instruction |= inst.operands[0].reg << 16;
8009 do_iwmmxt_wrwrwr_or_imm5 (void)
8011 if (inst.operands[2].isreg)
8014 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2),
8015 _("immediate operand requires iWMMXt2"));
8017 if (inst.operands[2].imm == 0)
8019 switch ((inst.instruction >> 20) & 0xf)
8025 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
8026 inst.operands[2].imm = 16;
8027 inst.instruction = (inst.instruction & 0xff0fffff) | (0x7 << 20);
8033 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
8034 inst.operands[2].imm = 32;
8035 inst.instruction = (inst.instruction & 0xff0fffff) | (0xb << 20);
8042 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
8044 wrn = (inst.instruction >> 16) & 0xf;
8045 inst.instruction &= 0xff0fff0f;
8046 inst.instruction |= wrn;
8047 /* Bail out here; the instruction is now assembled. */
8052 /* Map 32 -> 0, etc. */
8053 inst.operands[2].imm &= 0x1f;
8054 inst.instruction |= (0xf << 28) | ((inst.operands[2].imm & 0x10) << 4) | (inst.operands[2].imm & 0xf);
8058 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
8059 operations first, then control, shift, and load/store. */
8061 /* Insns like "foo X,Y,Z". */
8064 do_mav_triple (void)
8066 inst.instruction |= inst.operands[0].reg << 16;
8067 inst.instruction |= inst.operands[1].reg;
8068 inst.instruction |= inst.operands[2].reg << 12;
8071 /* Insns like "foo W,X,Y,Z".
8072 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
8077 inst.instruction |= inst.operands[0].reg << 5;
8078 inst.instruction |= inst.operands[1].reg << 12;
8079 inst.instruction |= inst.operands[2].reg << 16;
8080 inst.instruction |= inst.operands[3].reg;
8083 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
8087 inst.instruction |= inst.operands[1].reg << 12;
8090 /* Maverick shift immediate instructions.
8091 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
8092 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
8097 int imm = inst.operands[2].imm;
8099 inst.instruction |= inst.operands[0].reg << 12;
8100 inst.instruction |= inst.operands[1].reg << 16;
8102 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
8103 Bits 5-7 of the insn should have bits 4-6 of the immediate.
8104 Bit 4 should be 0. */
8105 imm = (imm & 0xf) | ((imm & 0x70) << 1);
8107 inst.instruction |= imm;
8110 /* XScale instructions. Also sorted arithmetic before move. */
8112 /* Xscale multiply-accumulate (argument parse)
8115 MIAxycc acc0,Rm,Rs. */
8120 inst.instruction |= inst.operands[1].reg;
8121 inst.instruction |= inst.operands[2].reg << 12;
8124 /* Xscale move-accumulator-register (argument parse)
8126 MARcc acc0,RdLo,RdHi. */
8131 inst.instruction |= inst.operands[1].reg << 12;
8132 inst.instruction |= inst.operands[2].reg << 16;
8135 /* Xscale move-register-accumulator (argument parse)
8137 MRAcc RdLo,RdHi,acc0. */
8142 constraint (inst.operands[0].reg == inst.operands[1].reg, BAD_OVERLAP);
8143 inst.instruction |= inst.operands[0].reg << 12;
8144 inst.instruction |= inst.operands[1].reg << 16;
8147 /* Encoding functions relevant only to Thumb. */
8149 /* inst.operands[i] is a shifted-register operand; encode
8150 it into inst.instruction in the format used by Thumb32. */
8153 encode_thumb32_shifted_operand (int i)
8155 unsigned int value = inst.reloc.exp.X_add_number;
8156 unsigned int shift = inst.operands[i].shift_kind;
8158 constraint (inst.operands[i].immisreg,
8159 _("shift by register not allowed in thumb mode"));
8160 inst.instruction |= inst.operands[i].reg;
8161 if (shift == SHIFT_RRX)
8162 inst.instruction |= SHIFT_ROR << 4;
8165 constraint (inst.reloc.exp.X_op != O_constant,
8166 _("expression too complex"));
8168 constraint (value > 32
8169 || (value == 32 && (shift == SHIFT_LSL
8170 || shift == SHIFT_ROR)),
8171 _("shift expression is too large"));
8175 else if (value == 32)
8178 inst.instruction |= shift << 4;
8179 inst.instruction |= (value & 0x1c) << 10;
8180 inst.instruction |= (value & 0x03) << 6;
8185 /* inst.operands[i] was set up by parse_address. Encode it into a
8186 Thumb32 format load or store instruction. Reject forms that cannot
8187 be used with such instructions. If is_t is true, reject forms that
8188 cannot be used with a T instruction; if is_d is true, reject forms
8189 that cannot be used with a D instruction. */
8192 encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d)
8194 bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);
8196 constraint (!inst.operands[i].isreg,
8197 _("Instruction does not support =N addresses"));
8199 inst.instruction |= inst.operands[i].reg << 16;
8200 if (inst.operands[i].immisreg)
8202 constraint (is_pc, _("cannot use register index with PC-relative addressing"));
8203 constraint (is_t || is_d, _("cannot use register index with this instruction"));
8204 constraint (inst.operands[i].negative,
8205 _("Thumb does not support negative register indexing"));
8206 constraint (inst.operands[i].postind,
8207 _("Thumb does not support register post-indexing"));
8208 constraint (inst.operands[i].writeback,
8209 _("Thumb does not support register indexing with writeback"));
8210 constraint (inst.operands[i].shifted && inst.operands[i].shift_kind != SHIFT_LSL,
8211 _("Thumb supports only LSL in shifted register indexing"));
8213 inst.instruction |= inst.operands[i].imm;
8214 if (inst.operands[i].shifted)
8216 constraint (inst.reloc.exp.X_op != O_constant,
8217 _("expression too complex"));
8218 constraint (inst.reloc.exp.X_add_number < 0
8219 || inst.reloc.exp.X_add_number > 3,
8220 _("shift out of range"));
8221 inst.instruction |= inst.reloc.exp.X_add_number << 4;
8223 inst.reloc.type = BFD_RELOC_UNUSED;
8225 else if (inst.operands[i].preind)
8227 constraint (is_pc && inst.operands[i].writeback,
8228 _("cannot use writeback with PC-relative addressing"));
8229 constraint (is_t && inst.operands[i].writeback,
8230 _("cannot use writeback with this instruction"));
8234 inst.instruction |= 0x01000000;
8235 if (inst.operands[i].writeback)
8236 inst.instruction |= 0x00200000;
8240 inst.instruction |= 0x00000c00;
8241 if (inst.operands[i].writeback)
8242 inst.instruction |= 0x00000100;
8244 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
8246 else if (inst.operands[i].postind)
8248 assert (inst.operands[i].writeback);
8249 constraint (is_pc, _("cannot use post-indexing with PC-relative addressing"));
8250 constraint (is_t, _("cannot use post-indexing with this instruction"));
8253 inst.instruction |= 0x00200000;
8255 inst.instruction |= 0x00000900;
8256 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
8258 else /* unindexed - only for coprocessor */
8259 inst.error = _("instruction does not accept unindexed addressing");
8262 /* Table of Thumb instructions which exist in both 16- and 32-bit
8263 encodings (the latter only in post-V6T2 cores). The index is the
8264 value used in the insns table below. When there is more than one
8265 possible 16-bit encoding for the instruction, this table always
8267 Also contains several pseudo-instructions used during relaxation. */
8268 #define T16_32_TAB \
8269 X(adc, 4140, eb400000), \
8270 X(adcs, 4140, eb500000), \
8271 X(add, 1c00, eb000000), \
8272 X(adds, 1c00, eb100000), \
8273 X(addi, 0000, f1000000), \
8274 X(addis, 0000, f1100000), \
8275 X(add_pc,000f, f20f0000), \
8276 X(add_sp,000d, f10d0000), \
8277 X(adr, 000f, f20f0000), \
8278 X(and, 4000, ea000000), \
8279 X(ands, 4000, ea100000), \
8280 X(asr, 1000, fa40f000), \
8281 X(asrs, 1000, fa50f000), \
8282 X(b, e000, f000b000), \
8283 X(bcond, d000, f0008000), \
8284 X(bic, 4380, ea200000), \
8285 X(bics, 4380, ea300000), \
8286 X(cmn, 42c0, eb100f00), \
8287 X(cmp, 2800, ebb00f00), \
8288 X(cpsie, b660, f3af8400), \
8289 X(cpsid, b670, f3af8600), \
8290 X(cpy, 4600, ea4f0000), \
8291 X(dec_sp,80dd, f1ad0d00), \
8292 X(eor, 4040, ea800000), \
8293 X(eors, 4040, ea900000), \
8294 X(inc_sp,00dd, f10d0d00), \
8295 X(ldmia, c800, e8900000), \
8296 X(ldr, 6800, f8500000), \
8297 X(ldrb, 7800, f8100000), \
8298 X(ldrh, 8800, f8300000), \
8299 X(ldrsb, 5600, f9100000), \
8300 X(ldrsh, 5e00, f9300000), \
8301 X(ldr_pc,4800, f85f0000), \
8302 X(ldr_pc2,4800, f85f0000), \
8303 X(ldr_sp,9800, f85d0000), \
8304 X(lsl, 0000, fa00f000), \
8305 X(lsls, 0000, fa10f000), \
8306 X(lsr, 0800, fa20f000), \
8307 X(lsrs, 0800, fa30f000), \
8308 X(mov, 2000, ea4f0000), \
8309 X(movs, 2000, ea5f0000), \
8310 X(mul, 4340, fb00f000), \
8311 X(muls, 4340, ffffffff), /* no 32b muls */ \
8312 X(mvn, 43c0, ea6f0000), \
8313 X(mvns, 43c0, ea7f0000), \
8314 X(neg, 4240, f1c00000), /* rsb #0 */ \
8315 X(negs, 4240, f1d00000), /* rsbs #0 */ \
8316 X(orr, 4300, ea400000), \
8317 X(orrs, 4300, ea500000), \
8318 X(pop, bc00, e8bd0000), /* ldmia sp!,... */ \
8319 X(push, b400, e92d0000), /* stmdb sp!,... */ \
8320 X(rev, ba00, fa90f080), \
8321 X(rev16, ba40, fa90f090), \
8322 X(revsh, bac0, fa90f0b0), \
8323 X(ror, 41c0, fa60f000), \
8324 X(rors, 41c0, fa70f000), \
8325 X(sbc, 4180, eb600000), \
8326 X(sbcs, 4180, eb700000), \
8327 X(stmia, c000, e8800000), \
8328 X(str, 6000, f8400000), \
8329 X(strb, 7000, f8000000), \
8330 X(strh, 8000, f8200000), \
8331 X(str_sp,9000, f84d0000), \
8332 X(sub, 1e00, eba00000), \
8333 X(subs, 1e00, ebb00000), \
8334 X(subi, 8000, f1a00000), \
8335 X(subis, 8000, f1b00000), \
8336 X(sxtb, b240, fa4ff080), \
8337 X(sxth, b200, fa0ff080), \
8338 X(tst, 4200, ea100f00), \
8339 X(uxtb, b2c0, fa5ff080), \
8340 X(uxth, b280, fa1ff080), \
8341 X(nop, bf00, f3af8000), \
8342 X(yield, bf10, f3af8001), \
8343 X(wfe, bf20, f3af8002), \
8344 X(wfi, bf30, f3af8003), \
8345 X(sev, bf40, f3af9004), /* typo, 8004? */
8347 /* To catch errors in encoding functions, the codes are all offset by
8348 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
8349 as 16-bit instructions. */
8350 #define X(a,b,c) T_MNEM_##a
8351 enum t16_32_codes { T16_32_OFFSET = 0xF7FF, T16_32_TAB };
8354 #define X(a,b,c) 0x##b
8355 static const unsigned short thumb_op16[] = { T16_32_TAB };
8356 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
8359 #define X(a,b,c) 0x##c
8360 static const unsigned int thumb_op32[] = { T16_32_TAB };
8361 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
8362 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
8366 /* Thumb instruction encoders, in alphabetical order. */
8370 do_t_add_sub_w (void)
8374 Rd = inst.operands[0].reg;
8375 Rn = inst.operands[1].reg;
8377 constraint (Rd == 15, _("PC not allowed as destination"));
8378 inst.instruction |= (Rn << 16) | (Rd << 8);
8379 inst.reloc.type = BFD_RELOC_ARM_T32_IMM12;
8382 /* Parse an add or subtract instruction. We get here with inst.instruction
8383 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
8390 Rd = inst.operands[0].reg;
8391 Rs = (inst.operands[1].present
8392 ? inst.operands[1].reg /* Rd, Rs, foo */
8393 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
8401 flags = (inst.instruction == T_MNEM_adds
8402 || inst.instruction == T_MNEM_subs);
8404 narrow = (current_it_mask == 0);
8406 narrow = (current_it_mask != 0);
8407 if (!inst.operands[2].isreg)
8411 add = (inst.instruction == T_MNEM_add
8412 || inst.instruction == T_MNEM_adds);
8414 if (inst.size_req != 4)
8416 /* Attempt to use a narrow opcode, with relaxation if
8418 if (Rd == REG_SP && Rs == REG_SP && !flags)
8419 opcode = add ? T_MNEM_inc_sp : T_MNEM_dec_sp;
8420 else if (Rd <= 7 && Rs == REG_SP && add && !flags)
8421 opcode = T_MNEM_add_sp;
8422 else if (Rd <= 7 && Rs == REG_PC && add && !flags)
8423 opcode = T_MNEM_add_pc;
8424 else if (Rd <= 7 && Rs <= 7 && narrow)
8427 opcode = add ? T_MNEM_addis : T_MNEM_subis;
8429 opcode = add ? T_MNEM_addi : T_MNEM_subi;
8433 inst.instruction = THUMB_OP16(opcode);
8434 inst.instruction |= (Rd << 4) | Rs;
8435 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
8436 if (inst.size_req != 2)
8437 inst.relax = opcode;
8440 constraint (inst.size_req == 2, BAD_HIREG);
8442 if (inst.size_req == 4
8443 || (inst.size_req != 2 && !opcode))
8447 constraint (Rs != REG_LR || inst.instruction != T_MNEM_subs,
8448 _("only SUBS PC, LR, #const allowed"));
8449 constraint (inst.reloc.exp.X_op != O_constant,
8450 _("expression too complex"));
8451 constraint (inst.reloc.exp.X_add_number < 0
8452 || inst.reloc.exp.X_add_number > 0xff,
8453 _("immediate value out of range"));
8454 inst.instruction = T2_SUBS_PC_LR
8455 | inst.reloc.exp.X_add_number;
8456 inst.reloc.type = BFD_RELOC_UNUSED;
8459 else if (Rs == REG_PC)
8461 /* Always use addw/subw. */
8462 inst.instruction = add ? 0xf20f0000 : 0xf2af0000;
8463 inst.reloc.type = BFD_RELOC_ARM_T32_IMM12;
8467 inst.instruction = THUMB_OP32 (inst.instruction);
8468 inst.instruction = (inst.instruction & 0xe1ffffff)
8471 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
8473 inst.reloc.type = BFD_RELOC_ARM_T32_ADD_IMM;
8475 inst.instruction |= Rd << 8;
8476 inst.instruction |= Rs << 16;
8481 Rn = inst.operands[2].reg;
8482 /* See if we can do this with a 16-bit instruction. */
8483 if (!inst.operands[2].shifted && inst.size_req != 4)
8485 if (Rd > 7 || Rs > 7 || Rn > 7)
8490 inst.instruction = ((inst.instruction == T_MNEM_adds
8491 || inst.instruction == T_MNEM_add)
8494 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
8498 if (inst.instruction == T_MNEM_add)
8502 inst.instruction = T_OPCODE_ADD_HI;
8503 inst.instruction |= (Rd & 8) << 4;
8504 inst.instruction |= (Rd & 7);
8505 inst.instruction |= Rn << 3;
8508 /* ... because addition is commutative! */
8511 inst.instruction = T_OPCODE_ADD_HI;
8512 inst.instruction |= (Rd & 8) << 4;
8513 inst.instruction |= (Rd & 7);
8514 inst.instruction |= Rs << 3;
8519 /* If we get here, it can't be done in 16 bits. */
8520 constraint (inst.operands[2].shifted && inst.operands[2].immisreg,
8521 _("shift must be constant"));
8522 inst.instruction = THUMB_OP32 (inst.instruction);
8523 inst.instruction |= Rd << 8;
8524 inst.instruction |= Rs << 16;
8525 encode_thumb32_shifted_operand (2);
8530 constraint (inst.instruction == T_MNEM_adds
8531 || inst.instruction == T_MNEM_subs,
8534 if (!inst.operands[2].isreg) /* Rd, Rs, #imm */
8536 constraint ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP))
8537 || (Rs > 7 && Rs != REG_SP && Rs != REG_PC),
8540 inst.instruction = (inst.instruction == T_MNEM_add
8542 inst.instruction |= (Rd << 4) | Rs;
8543 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
8547 Rn = inst.operands[2].reg;
8548 constraint (inst.operands[2].shifted, _("unshifted register required"));
8550 /* We now have Rd, Rs, and Rn set to registers. */
8551 if (Rd > 7 || Rs > 7 || Rn > 7)
8553 /* Can't do this for SUB. */
8554 constraint (inst.instruction == T_MNEM_sub, BAD_HIREG);
8555 inst.instruction = T_OPCODE_ADD_HI;
8556 inst.instruction |= (Rd & 8) << 4;
8557 inst.instruction |= (Rd & 7);
8559 inst.instruction |= Rn << 3;
8561 inst.instruction |= Rs << 3;
8563 constraint (1, _("dest must overlap one source register"));
8567 inst.instruction = (inst.instruction == T_MNEM_add
8568 ? T_OPCODE_ADD_R3 : T_OPCODE_SUB_R3);
8569 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
8577 if (unified_syntax && inst.size_req == 0 && inst.operands[0].reg <= 7)
8579 /* Defer to section relaxation. */
8580 inst.relax = inst.instruction;
8581 inst.instruction = THUMB_OP16 (inst.instruction);
8582 inst.instruction |= inst.operands[0].reg << 4;
8584 else if (unified_syntax && inst.size_req != 2)
8586 /* Generate a 32-bit opcode. */
8587 inst.instruction = THUMB_OP32 (inst.instruction);
8588 inst.instruction |= inst.operands[0].reg << 8;
8589 inst.reloc.type = BFD_RELOC_ARM_T32_ADD_PC12;
8590 inst.reloc.pc_rel = 1;
8594 /* Generate a 16-bit opcode. */
8595 inst.instruction = THUMB_OP16 (inst.instruction);
8596 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
8597 inst.reloc.exp.X_add_number -= 4; /* PC relative adjust. */
8598 inst.reloc.pc_rel = 1;
8600 inst.instruction |= inst.operands[0].reg << 4;
8604 /* Arithmetic instructions for which there is just one 16-bit
8605 instruction encoding, and it allows only two low registers.
8606 For maximal compatibility with ARM syntax, we allow three register
8607 operands even when Thumb-32 instructions are not available, as long
8608 as the first two are identical. For instance, both "sbc r0,r1" and
8609 "sbc r0,r0,r1" are allowed. */
8615 Rd = inst.operands[0].reg;
8616 Rs = (inst.operands[1].present
8617 ? inst.operands[1].reg /* Rd, Rs, foo */
8618 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
8619 Rn = inst.operands[2].reg;
8623 if (!inst.operands[2].isreg)
8625 /* For an immediate, we always generate a 32-bit opcode;
8626 section relaxation will shrink it later if possible. */
8627 inst.instruction = THUMB_OP32 (inst.instruction);
8628 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
8629 inst.instruction |= Rd << 8;
8630 inst.instruction |= Rs << 16;
8631 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
8637 /* See if we can do this with a 16-bit instruction. */
8638 if (THUMB_SETS_FLAGS (inst.instruction))
8639 narrow = current_it_mask == 0;
8641 narrow = current_it_mask != 0;
8643 if (Rd > 7 || Rn > 7 || Rs > 7)
8645 if (inst.operands[2].shifted)
8647 if (inst.size_req == 4)
8653 inst.instruction = THUMB_OP16 (inst.instruction);
8654 inst.instruction |= Rd;
8655 inst.instruction |= Rn << 3;
8659 /* If we get here, it can't be done in 16 bits. */
8660 constraint (inst.operands[2].shifted
8661 && inst.operands[2].immisreg,
8662 _("shift must be constant"));
8663 inst.instruction = THUMB_OP32 (inst.instruction);
8664 inst.instruction |= Rd << 8;
8665 inst.instruction |= Rs << 16;
8666 encode_thumb32_shifted_operand (2);
8671 /* On its face this is a lie - the instruction does set the
8672 flags. However, the only supported mnemonic in this mode
8674 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
8676 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
8677 _("unshifted register required"));
8678 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
8679 constraint (Rd != Rs,
8680 _("dest and source1 must be the same register"));
8682 inst.instruction = THUMB_OP16 (inst.instruction);
8683 inst.instruction |= Rd;
8684 inst.instruction |= Rn << 3;
8688 /* Similarly, but for instructions where the arithmetic operation is
8689 commutative, so we can allow either of them to be different from
8690 the destination operand in a 16-bit instruction. For instance, all
8691 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
8698 Rd = inst.operands[0].reg;
8699 Rs = (inst.operands[1].present
8700 ? inst.operands[1].reg /* Rd, Rs, foo */
8701 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
8702 Rn = inst.operands[2].reg;
8706 if (!inst.operands[2].isreg)
8708 /* For an immediate, we always generate a 32-bit opcode;
8709 section relaxation will shrink it later if possible. */
8710 inst.instruction = THUMB_OP32 (inst.instruction);
8711 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
8712 inst.instruction |= Rd << 8;
8713 inst.instruction |= Rs << 16;
8714 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
8720 /* See if we can do this with a 16-bit instruction. */
8721 if (THUMB_SETS_FLAGS (inst.instruction))
8722 narrow = current_it_mask == 0;
8724 narrow = current_it_mask != 0;
8726 if (Rd > 7 || Rn > 7 || Rs > 7)
8728 if (inst.operands[2].shifted)
8730 if (inst.size_req == 4)
8737 inst.instruction = THUMB_OP16 (inst.instruction);
8738 inst.instruction |= Rd;
8739 inst.instruction |= Rn << 3;
8744 inst.instruction = THUMB_OP16 (inst.instruction);
8745 inst.instruction |= Rd;
8746 inst.instruction |= Rs << 3;
8751 /* If we get here, it can't be done in 16 bits. */
8752 constraint (inst.operands[2].shifted
8753 && inst.operands[2].immisreg,
8754 _("shift must be constant"));
8755 inst.instruction = THUMB_OP32 (inst.instruction);
8756 inst.instruction |= Rd << 8;
8757 inst.instruction |= Rs << 16;
8758 encode_thumb32_shifted_operand (2);
8763 /* On its face this is a lie - the instruction does set the
8764 flags. However, the only supported mnemonic in this mode
8766 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
8768 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
8769 _("unshifted register required"));
8770 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
8772 inst.instruction = THUMB_OP16 (inst.instruction);
8773 inst.instruction |= Rd;
8776 inst.instruction |= Rn << 3;
8778 inst.instruction |= Rs << 3;
8780 constraint (1, _("dest must overlap one source register"));
8787 if (inst.operands[0].present)
8789 constraint ((inst.instruction & 0xf0) != 0x40
8790 && inst.operands[0].imm != 0xf,
8791 "bad barrier type");
8792 inst.instruction |= inst.operands[0].imm;
8795 inst.instruction |= 0xf;
8801 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
8802 constraint (msb > 32, _("bit-field extends past end of register"));
8803 /* The instruction encoding stores the LSB and MSB,
8804 not the LSB and width. */
8805 inst.instruction |= inst.operands[0].reg << 8;
8806 inst.instruction |= (inst.operands[1].imm & 0x1c) << 10;
8807 inst.instruction |= (inst.operands[1].imm & 0x03) << 6;
8808 inst.instruction |= msb - 1;
8816 /* #0 in second position is alternative syntax for bfc, which is
8817 the same instruction but with REG_PC in the Rm field. */
8818 if (!inst.operands[1].isreg)
8819 inst.operands[1].reg = REG_PC;
8821 msb = inst.operands[2].imm + inst.operands[3].imm;
8822 constraint (msb > 32, _("bit-field extends past end of register"));
8823 /* The instruction encoding stores the LSB and MSB,
8824 not the LSB and width. */
8825 inst.instruction |= inst.operands[0].reg << 8;
8826 inst.instruction |= inst.operands[1].reg << 16;
8827 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
8828 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
8829 inst.instruction |= msb - 1;
8835 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
8836 _("bit-field extends past end of register"));
8837 inst.instruction |= inst.operands[0].reg << 8;
8838 inst.instruction |= inst.operands[1].reg << 16;
8839 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
8840 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
8841 inst.instruction |= inst.operands[3].imm - 1;
8844 /* ARM V5 Thumb BLX (argument parse)
8845 BLX <target_addr> which is BLX(1)
8846 BLX <Rm> which is BLX(2)
8847 Unfortunately, there are two different opcodes for this mnemonic.
8848 So, the insns[].value is not used, and the code here zaps values
8849 into inst.instruction.
8851 ??? How to take advantage of the additional two bits of displacement
8852 available in Thumb32 mode? Need new relocation? */
8857 constraint (current_it_mask && current_it_mask != 0x10, BAD_BRANCH);
8858 if (inst.operands[0].isreg)
8859 /* We have a register, so this is BLX(2). */
8860 inst.instruction |= inst.operands[0].reg << 3;
8863 /* No register. This must be BLX(1). */
8864 inst.instruction = 0xf000e800;
8866 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
8867 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23;
8870 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BLX;
8871 inst.reloc.pc_rel = 1;
8881 if (current_it_mask)
8883 /* Conditional branches inside IT blocks are encoded as unconditional
8886 /* A branch must be the last instruction in an IT block. */
8887 constraint (current_it_mask != 0x10, BAD_BRANCH);
8892 if (cond != COND_ALWAYS)
8893 opcode = T_MNEM_bcond;
8895 opcode = inst.instruction;
8897 if (unified_syntax && inst.size_req == 4)
8899 inst.instruction = THUMB_OP32(opcode);
8900 if (cond == COND_ALWAYS)
8901 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH25;
8904 assert (cond != 0xF);
8905 inst.instruction |= cond << 22;
8906 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH20;
8911 inst.instruction = THUMB_OP16(opcode);
8912 if (cond == COND_ALWAYS)
8913 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH12;
8916 inst.instruction |= cond << 8;
8917 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH9;
8919 /* Allow section relaxation. */
8920 if (unified_syntax && inst.size_req != 2)
8921 inst.relax = opcode;
8924 inst.reloc.pc_rel = 1;
8930 constraint (inst.cond != COND_ALWAYS,
8931 _("instruction is always unconditional"));
8932 if (inst.operands[0].present)
8934 constraint (inst.operands[0].imm > 255,
8935 _("immediate value out of range"));
8936 inst.instruction |= inst.operands[0].imm;
8941 do_t_branch23 (void)
8943 constraint (current_it_mask && current_it_mask != 0x10, BAD_BRANCH);
8944 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23;
8945 inst.reloc.pc_rel = 1;
8947 /* If the destination of the branch is a defined symbol which does not have
8948 the THUMB_FUNC attribute, then we must be calling a function which has
8949 the (interfacearm) attribute. We look for the Thumb entry point to that
8950 function and change the branch to refer to that function instead. */
8951 if ( inst.reloc.exp.X_op == O_symbol
8952 && inst.reloc.exp.X_add_symbol != NULL
8953 && S_IS_DEFINED (inst.reloc.exp.X_add_symbol)
8954 && ! THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol))
8955 inst.reloc.exp.X_add_symbol =
8956 find_real_start (inst.reloc.exp.X_add_symbol);
8962 constraint (current_it_mask && current_it_mask != 0x10, BAD_BRANCH);
8963 inst.instruction |= inst.operands[0].reg << 3;
8964 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
8965 should cause the alignment to be checked once it is known. This is
8966 because BX PC only works if the instruction is word aligned. */
8972 constraint (current_it_mask && current_it_mask != 0x10, BAD_BRANCH);
8973 if (inst.operands[0].reg == REG_PC)
8974 as_tsktsk (_("use of r15 in bxj is not really useful"));
8976 inst.instruction |= inst.operands[0].reg << 16;
8982 inst.instruction |= inst.operands[0].reg << 8;
8983 inst.instruction |= inst.operands[1].reg << 16;
8984 inst.instruction |= inst.operands[1].reg;
8990 constraint (current_it_mask, BAD_NOT_IT);
8991 inst.instruction |= inst.operands[0].imm;
8997 constraint (current_it_mask, BAD_NOT_IT);
8999 && (inst.operands[1].present || inst.size_req == 4)
9000 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6_notm))
9002 unsigned int imod = (inst.instruction & 0x0030) >> 4;
9003 inst.instruction = 0xf3af8000;
9004 inst.instruction |= imod << 9;
9005 inst.instruction |= inst.operands[0].imm << 5;
9006 if (inst.operands[1].present)
9007 inst.instruction |= 0x100 | inst.operands[1].imm;
9011 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)
9012 && (inst.operands[0].imm & 4),
9013 _("selected processor does not support 'A' form "
9014 "of this instruction"));
9015 constraint (inst.operands[1].present || inst.size_req == 4,
9016 _("Thumb does not support the 2-argument "
9017 "form of this instruction"));
9018 inst.instruction |= inst.operands[0].imm;
9022 /* THUMB CPY instruction (argument parse). */
9027 if (inst.size_req == 4)
9029 inst.instruction = THUMB_OP32 (T_MNEM_mov);
9030 inst.instruction |= inst.operands[0].reg << 8;
9031 inst.instruction |= inst.operands[1].reg;
9035 inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
9036 inst.instruction |= (inst.operands[0].reg & 0x7);
9037 inst.instruction |= inst.operands[1].reg << 3;
9044 constraint (current_it_mask, BAD_NOT_IT);
9045 constraint (inst.operands[0].reg > 7, BAD_HIREG);
9046 inst.instruction |= inst.operands[0].reg;
9047 inst.reloc.pc_rel = 1;
9048 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH7;
9054 inst.instruction |= inst.operands[0].imm;
9060 if (!inst.operands[1].present)
9061 inst.operands[1].reg = inst.operands[0].reg;
9062 inst.instruction |= inst.operands[0].reg << 8;
9063 inst.instruction |= inst.operands[1].reg << 16;
9064 inst.instruction |= inst.operands[2].reg;
9070 if (unified_syntax && inst.size_req == 4)
9071 inst.instruction = THUMB_OP32 (inst.instruction);
9073 inst.instruction = THUMB_OP16 (inst.instruction);
9079 unsigned int cond = inst.operands[0].imm;
9081 constraint (current_it_mask, BAD_NOT_IT);
9082 current_it_mask = (inst.instruction & 0xf) | 0x10;
9085 /* If the condition is a negative condition, invert the mask. */
9086 if ((cond & 0x1) == 0x0)
9088 unsigned int mask = inst.instruction & 0x000f;
9090 if ((mask & 0x7) == 0)
9091 /* no conversion needed */;
9092 else if ((mask & 0x3) == 0)
9094 else if ((mask & 0x1) == 0)
9099 inst.instruction &= 0xfff0;
9100 inst.instruction |= mask;
9103 inst.instruction |= cond << 4;
9106 /* Helper function used for both push/pop and ldm/stm. */
9108 encode_thumb2_ldmstm (int base, unsigned mask, bfd_boolean writeback)
9112 load = (inst.instruction & (1 << 20)) != 0;
9114 if (mask & (1 << 13))
9115 inst.error = _("SP not allowed in register list");
9118 if (mask & (1 << 14)
9119 && mask & (1 << 15))
9120 inst.error = _("LR and PC should not both be in register list");
9122 if ((mask & (1 << base)) != 0
9124 as_warn (_("base register should not be in register list "
9125 "when written back"));
9129 if (mask & (1 << 15))
9130 inst.error = _("PC not allowed in register list");
9132 if (mask & (1 << base))
9133 as_warn (_("value stored for r%d is UNPREDICTABLE"), base);
9136 if ((mask & (mask - 1)) == 0)
9138 /* Single register transfers implemented as str/ldr. */
9141 if (inst.instruction & (1 << 23))
9142 inst.instruction = 0x00000b04; /* ia! -> [base], #4 */
9144 inst.instruction = 0x00000d04; /* db! -> [base, #-4]! */
9148 if (inst.instruction & (1 << 23))
9149 inst.instruction = 0x00800000; /* ia -> [base] */
9151 inst.instruction = 0x00000c04; /* db -> [base, #-4] */
9154 inst.instruction |= 0xf8400000;
9156 inst.instruction |= 0x00100000;
9158 mask = ffs(mask) - 1;
9162 inst.instruction |= WRITE_BACK;
9164 inst.instruction |= mask;
9165 inst.instruction |= base << 16;
9171 /* This really doesn't seem worth it. */
9172 constraint (inst.reloc.type != BFD_RELOC_UNUSED,
9173 _("expression too complex"));
9174 constraint (inst.operands[1].writeback,
9175 _("Thumb load/store multiple does not support {reglist}^"));
9183 /* See if we can use a 16-bit instruction. */
9184 if (inst.instruction < 0xffff /* not ldmdb/stmdb */
9185 && inst.size_req != 4
9186 && !(inst.operands[1].imm & ~0xff))
9188 mask = 1 << inst.operands[0].reg;
9190 if (inst.operands[0].reg <= 7
9191 && (inst.instruction == T_MNEM_stmia
9192 ? inst.operands[0].writeback
9193 : (inst.operands[0].writeback
9194 == !(inst.operands[1].imm & mask))))
9196 if (inst.instruction == T_MNEM_stmia
9197 && (inst.operands[1].imm & mask)
9198 && (inst.operands[1].imm & (mask - 1)))
9199 as_warn (_("value stored for r%d is UNPREDICTABLE"),
9200 inst.operands[0].reg);
9202 inst.instruction = THUMB_OP16 (inst.instruction);
9203 inst.instruction |= inst.operands[0].reg << 8;
9204 inst.instruction |= inst.operands[1].imm;
9207 else if (inst.operands[0] .reg == REG_SP
9208 && inst.operands[0].writeback)
9210 inst.instruction = THUMB_OP16 (inst.instruction == T_MNEM_stmia
9211 ? T_MNEM_push : T_MNEM_pop);
9212 inst.instruction |= inst.operands[1].imm;
9219 if (inst.instruction < 0xffff)
9220 inst.instruction = THUMB_OP32 (inst.instruction);
9222 encode_thumb2_ldmstm(inst.operands[0].reg, inst.operands[1].imm,
9223 inst.operands[0].writeback);
9228 constraint (inst.operands[0].reg > 7
9229 || (inst.operands[1].imm & ~0xff), BAD_HIREG);
9230 constraint (inst.instruction != T_MNEM_ldmia
9231 && inst.instruction != T_MNEM_stmia,
9232 _("Thumb-2 instruction only valid in unified syntax"));
9233 if (inst.instruction == T_MNEM_stmia)
9235 if (!inst.operands[0].writeback)
9236 as_warn (_("this instruction will write back the base register"));
9237 if ((inst.operands[1].imm & (1 << inst.operands[0].reg))
9238 && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1)))
9239 as_warn (_("value stored for r%d is UNPREDICTABLE"),
9240 inst.operands[0].reg);
9244 if (!inst.operands[0].writeback
9245 && !(inst.operands[1].imm & (1 << inst.operands[0].reg)))
9246 as_warn (_("this instruction will write back the base register"));
9247 else if (inst.operands[0].writeback
9248 && (inst.operands[1].imm & (1 << inst.operands[0].reg)))
9249 as_warn (_("this instruction will not write back the base register"));
9252 inst.instruction = THUMB_OP16 (inst.instruction);
9253 inst.instruction |= inst.operands[0].reg << 8;
9254 inst.instruction |= inst.operands[1].imm;
9261 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
9262 || inst.operands[1].postind || inst.operands[1].writeback
9263 || inst.operands[1].immisreg || inst.operands[1].shifted
9264 || inst.operands[1].negative,
9267 inst.instruction |= inst.operands[0].reg << 12;
9268 inst.instruction |= inst.operands[1].reg << 16;
9269 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8;
9275 if (!inst.operands[1].present)
9277 constraint (inst.operands[0].reg == REG_LR,
9278 _("r14 not allowed as first register "
9279 "when second register is omitted"));
9280 inst.operands[1].reg = inst.operands[0].reg + 1;
9282 constraint (inst.operands[0].reg == inst.operands[1].reg,
9285 inst.instruction |= inst.operands[0].reg << 12;
9286 inst.instruction |= inst.operands[1].reg << 8;
9287 inst.instruction |= inst.operands[2].reg << 16;
9293 unsigned long opcode;
9296 opcode = inst.instruction;
9299 if (!inst.operands[1].isreg)
9301 if (opcode <= 0xffff)
9302 inst.instruction = THUMB_OP32 (opcode);
9303 if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE))
9306 if (inst.operands[1].isreg
9307 && !inst.operands[1].writeback
9308 && !inst.operands[1].shifted && !inst.operands[1].postind
9309 && !inst.operands[1].negative && inst.operands[0].reg <= 7
9311 && inst.size_req != 4)
9313 /* Insn may have a 16-bit form. */
9314 Rn = inst.operands[1].reg;
9315 if (inst.operands[1].immisreg)
9317 inst.instruction = THUMB_OP16 (opcode);
9319 if (Rn <= 7 && inst.operands[1].imm <= 7)
9322 else if ((Rn <= 7 && opcode != T_MNEM_ldrsh
9323 && opcode != T_MNEM_ldrsb)
9324 || ((Rn == REG_PC || Rn == REG_SP) && opcode == T_MNEM_ldr)
9325 || (Rn == REG_SP && opcode == T_MNEM_str))
9332 if (inst.reloc.pc_rel)
9333 opcode = T_MNEM_ldr_pc2;
9335 opcode = T_MNEM_ldr_pc;
9339 if (opcode == T_MNEM_ldr)
9340 opcode = T_MNEM_ldr_sp;
9342 opcode = T_MNEM_str_sp;
9344 inst.instruction = inst.operands[0].reg << 8;
9348 inst.instruction = inst.operands[0].reg;
9349 inst.instruction |= inst.operands[1].reg << 3;
9351 inst.instruction |= THUMB_OP16 (opcode);
9352 if (inst.size_req == 2)
9353 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
9355 inst.relax = opcode;
9359 /* Definitely a 32-bit variant. */
9360 inst.instruction = THUMB_OP32 (opcode);
9361 inst.instruction |= inst.operands[0].reg << 12;
9362 encode_thumb32_addr_mode (1, /*is_t=*/FALSE, /*is_d=*/FALSE);
9366 constraint (inst.operands[0].reg > 7, BAD_HIREG);
9368 if (inst.instruction == T_MNEM_ldrsh || inst.instruction == T_MNEM_ldrsb)
9370 /* Only [Rn,Rm] is acceptable. */
9371 constraint (inst.operands[1].reg > 7 || inst.operands[1].imm > 7, BAD_HIREG);
9372 constraint (!inst.operands[1].isreg || !inst.operands[1].immisreg
9373 || inst.operands[1].postind || inst.operands[1].shifted
9374 || inst.operands[1].negative,
9375 _("Thumb does not support this addressing mode"));
9376 inst.instruction = THUMB_OP16 (inst.instruction);
9380 inst.instruction = THUMB_OP16 (inst.instruction);
9381 if (!inst.operands[1].isreg)
9382 if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE))
9385 constraint (!inst.operands[1].preind
9386 || inst.operands[1].shifted
9387 || inst.operands[1].writeback,
9388 _("Thumb does not support this addressing mode"));
9389 if (inst.operands[1].reg == REG_PC || inst.operands[1].reg == REG_SP)
9391 constraint (inst.instruction & 0x0600,
9392 _("byte or halfword not valid for base register"));
9393 constraint (inst.operands[1].reg == REG_PC
9394 && !(inst.instruction & THUMB_LOAD_BIT),
9395 _("r15 based store not allowed"));
9396 constraint (inst.operands[1].immisreg,
9397 _("invalid base register for register offset"));
9399 if (inst.operands[1].reg == REG_PC)
9400 inst.instruction = T_OPCODE_LDR_PC;
9401 else if (inst.instruction & THUMB_LOAD_BIT)
9402 inst.instruction = T_OPCODE_LDR_SP;
9404 inst.instruction = T_OPCODE_STR_SP;
9406 inst.instruction |= inst.operands[0].reg << 8;
9407 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
9411 constraint (inst.operands[1].reg > 7, BAD_HIREG);
9412 if (!inst.operands[1].immisreg)
9414 /* Immediate offset. */
9415 inst.instruction |= inst.operands[0].reg;
9416 inst.instruction |= inst.operands[1].reg << 3;
9417 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
9421 /* Register offset. */
9422 constraint (inst.operands[1].imm > 7, BAD_HIREG);
9423 constraint (inst.operands[1].negative,
9424 _("Thumb does not support this addressing mode"));
9427 switch (inst.instruction)
9429 case T_OPCODE_STR_IW: inst.instruction = T_OPCODE_STR_RW; break;
9430 case T_OPCODE_STR_IH: inst.instruction = T_OPCODE_STR_RH; break;
9431 case T_OPCODE_STR_IB: inst.instruction = T_OPCODE_STR_RB; break;
9432 case T_OPCODE_LDR_IW: inst.instruction = T_OPCODE_LDR_RW; break;
9433 case T_OPCODE_LDR_IH: inst.instruction = T_OPCODE_LDR_RH; break;
9434 case T_OPCODE_LDR_IB: inst.instruction = T_OPCODE_LDR_RB; break;
9435 case 0x5600 /* ldrsb */:
9436 case 0x5e00 /* ldrsh */: break;
9440 inst.instruction |= inst.operands[0].reg;
9441 inst.instruction |= inst.operands[1].reg << 3;
9442 inst.instruction |= inst.operands[1].imm << 6;
9448 if (!inst.operands[1].present)
9450 inst.operands[1].reg = inst.operands[0].reg + 1;
9451 constraint (inst.operands[0].reg == REG_LR,
9452 _("r14 not allowed here"));
9454 inst.instruction |= inst.operands[0].reg << 12;
9455 inst.instruction |= inst.operands[1].reg << 8;
9456 encode_thumb32_addr_mode (2, /*is_t=*/FALSE, /*is_d=*/TRUE);
9463 inst.instruction |= inst.operands[0].reg << 12;
9464 encode_thumb32_addr_mode (1, /*is_t=*/TRUE, /*is_d=*/FALSE);
9470 inst.instruction |= inst.operands[0].reg << 8;
9471 inst.instruction |= inst.operands[1].reg << 16;
9472 inst.instruction |= inst.operands[2].reg;
9473 inst.instruction |= inst.operands[3].reg << 12;
9479 inst.instruction |= inst.operands[0].reg << 12;
9480 inst.instruction |= inst.operands[1].reg << 8;
9481 inst.instruction |= inst.operands[2].reg << 16;
9482 inst.instruction |= inst.operands[3].reg;
9490 int r0off = (inst.instruction == T_MNEM_mov
9491 || inst.instruction == T_MNEM_movs) ? 8 : 16;
9492 unsigned long opcode;
9494 bfd_boolean low_regs;
9496 low_regs = (inst.operands[0].reg <= 7 && inst.operands[1].reg <= 7);
9497 opcode = inst.instruction;
9498 if (current_it_mask)
9499 narrow = opcode != T_MNEM_movs;
9501 narrow = opcode != T_MNEM_movs || low_regs;
9502 if (inst.size_req == 4
9503 || inst.operands[1].shifted)
9506 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
9507 if (opcode == T_MNEM_movs && inst.operands[1].isreg
9508 && !inst.operands[1].shifted
9509 && inst.operands[0].reg == REG_PC
9510 && inst.operands[1].reg == REG_LR)
9512 inst.instruction = T2_SUBS_PC_LR;
9516 if (!inst.operands[1].isreg)
9518 /* Immediate operand. */
9519 if (current_it_mask == 0 && opcode == T_MNEM_mov)
9521 if (low_regs && narrow)
9523 inst.instruction = THUMB_OP16 (opcode);
9524 inst.instruction |= inst.operands[0].reg << 8;
9525 if (inst.size_req == 2)
9526 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
9528 inst.relax = opcode;
9532 inst.instruction = THUMB_OP32 (inst.instruction);
9533 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
9534 inst.instruction |= inst.operands[0].reg << r0off;
9535 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
9538 else if (inst.operands[1].shifted && inst.operands[1].immisreg
9539 && (inst.instruction == T_MNEM_mov
9540 || inst.instruction == T_MNEM_movs))
9542 /* Register shifts are encoded as separate shift instructions. */
9543 bfd_boolean flags = (inst.instruction == T_MNEM_movs);
9545 if (current_it_mask)
9550 if (inst.size_req == 4)
9553 if (!low_regs || inst.operands[1].imm > 7)
9556 if (inst.operands[0].reg != inst.operands[1].reg)
9559 switch (inst.operands[1].shift_kind)
9562 opcode = narrow ? T_OPCODE_LSL_R : THUMB_OP32 (T_MNEM_lsl);
9565 opcode = narrow ? T_OPCODE_ASR_R : THUMB_OP32 (T_MNEM_asr);
9568 opcode = narrow ? T_OPCODE_LSR_R : THUMB_OP32 (T_MNEM_lsr);
9571 opcode = narrow ? T_OPCODE_ROR_R : THUMB_OP32 (T_MNEM_ror);
9577 inst.instruction = opcode;
9580 inst.instruction |= inst.operands[0].reg;
9581 inst.instruction |= inst.operands[1].imm << 3;
9586 inst.instruction |= CONDS_BIT;
9588 inst.instruction |= inst.operands[0].reg << 8;
9589 inst.instruction |= inst.operands[1].reg << 16;
9590 inst.instruction |= inst.operands[1].imm;
9595 /* Some mov with immediate shift have narrow variants.
9596 Register shifts are handled above. */
9597 if (low_regs && inst.operands[1].shifted
9598 && (inst.instruction == T_MNEM_mov
9599 || inst.instruction == T_MNEM_movs))
9601 if (current_it_mask)
9602 narrow = (inst.instruction == T_MNEM_mov);
9604 narrow = (inst.instruction == T_MNEM_movs);
9609 switch (inst.operands[1].shift_kind)
9611 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
9612 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
9613 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
9614 default: narrow = FALSE; break;
9620 inst.instruction |= inst.operands[0].reg;
9621 inst.instruction |= inst.operands[1].reg << 3;
9622 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
9626 inst.instruction = THUMB_OP32 (inst.instruction);
9627 inst.instruction |= inst.operands[0].reg << r0off;
9628 encode_thumb32_shifted_operand (1);
9632 switch (inst.instruction)
9635 inst.instruction = T_OPCODE_MOV_HR;
9636 inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
9637 inst.instruction |= (inst.operands[0].reg & 0x7);
9638 inst.instruction |= inst.operands[1].reg << 3;
9642 /* We know we have low registers at this point.
9643 Generate ADD Rd, Rs, #0. */
9644 inst.instruction = T_OPCODE_ADD_I3;
9645 inst.instruction |= inst.operands[0].reg;
9646 inst.instruction |= inst.operands[1].reg << 3;
9652 inst.instruction = T_OPCODE_CMP_LR;
9653 inst.instruction |= inst.operands[0].reg;
9654 inst.instruction |= inst.operands[1].reg << 3;
9658 inst.instruction = T_OPCODE_CMP_HR;
9659 inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
9660 inst.instruction |= (inst.operands[0].reg & 0x7);
9661 inst.instruction |= inst.operands[1].reg << 3;
9668 inst.instruction = THUMB_OP16 (inst.instruction);
9669 if (inst.operands[1].isreg)
9671 if (inst.operands[0].reg < 8 && inst.operands[1].reg < 8)
9673 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
9674 since a MOV instruction produces unpredictable results. */
9675 if (inst.instruction == T_OPCODE_MOV_I8)
9676 inst.instruction = T_OPCODE_ADD_I3;
9678 inst.instruction = T_OPCODE_CMP_LR;
9680 inst.instruction |= inst.operands[0].reg;
9681 inst.instruction |= inst.operands[1].reg << 3;
9685 if (inst.instruction == T_OPCODE_MOV_I8)
9686 inst.instruction = T_OPCODE_MOV_HR;
9688 inst.instruction = T_OPCODE_CMP_HR;
9694 constraint (inst.operands[0].reg > 7,
9695 _("only lo regs allowed with immediate"));
9696 inst.instruction |= inst.operands[0].reg << 8;
9697 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
9707 top = (inst.instruction & 0x00800000) != 0;
9708 if (inst.reloc.type == BFD_RELOC_ARM_MOVW)
9710 constraint (top, _(":lower16: not allowed this instruction"));
9711 inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVW;
9713 else if (inst.reloc.type == BFD_RELOC_ARM_MOVT)
9715 constraint (!top, _(":upper16: not allowed this instruction"));
9716 inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVT;
9719 inst.instruction |= inst.operands[0].reg << 8;
9720 if (inst.reloc.type == BFD_RELOC_UNUSED)
9722 imm = inst.reloc.exp.X_add_number;
9723 inst.instruction |= (imm & 0xf000) << 4;
9724 inst.instruction |= (imm & 0x0800) << 15;
9725 inst.instruction |= (imm & 0x0700) << 4;
9726 inst.instruction |= (imm & 0x00ff);
9735 int r0off = (inst.instruction == T_MNEM_mvn
9736 || inst.instruction == T_MNEM_mvns) ? 8 : 16;
9739 if (inst.size_req == 4
9740 || inst.instruction > 0xffff
9741 || inst.operands[1].shifted
9742 || inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
9744 else if (inst.instruction == T_MNEM_cmn)
9746 else if (THUMB_SETS_FLAGS (inst.instruction))
9747 narrow = (current_it_mask == 0);
9749 narrow = (current_it_mask != 0);
9751 if (!inst.operands[1].isreg)
9753 /* For an immediate, we always generate a 32-bit opcode;
9754 section relaxation will shrink it later if possible. */
9755 if (inst.instruction < 0xffff)
9756 inst.instruction = THUMB_OP32 (inst.instruction);
9757 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
9758 inst.instruction |= inst.operands[0].reg << r0off;
9759 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
9763 /* See if we can do this with a 16-bit instruction. */
9766 inst.instruction = THUMB_OP16 (inst.instruction);
9767 inst.instruction |= inst.operands[0].reg;
9768 inst.instruction |= inst.operands[1].reg << 3;
9772 constraint (inst.operands[1].shifted
9773 && inst.operands[1].immisreg,
9774 _("shift must be constant"));
9775 if (inst.instruction < 0xffff)
9776 inst.instruction = THUMB_OP32 (inst.instruction);
9777 inst.instruction |= inst.operands[0].reg << r0off;
9778 encode_thumb32_shifted_operand (1);
9784 constraint (inst.instruction > 0xffff
9785 || inst.instruction == T_MNEM_mvns, BAD_THUMB32);
9786 constraint (!inst.operands[1].isreg || inst.operands[1].shifted,
9787 _("unshifted register required"));
9788 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7,
9791 inst.instruction = THUMB_OP16 (inst.instruction);
9792 inst.instruction |= inst.operands[0].reg;
9793 inst.instruction |= inst.operands[1].reg << 3;
9802 if (do_vfp_nsyn_mrs () == SUCCESS)
9805 flags = inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
9808 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7m),
9809 _("selected processor does not support "
9810 "requested special purpose register"));
9814 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1),
9815 _("selected processor does not support "
9816 "requested special purpose register %x"));
9817 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
9818 constraint ((flags & ~SPSR_BIT) != (PSR_c|PSR_f),
9819 _("'CPSR' or 'SPSR' expected"));
9822 inst.instruction |= inst.operands[0].reg << 8;
9823 inst.instruction |= (flags & SPSR_BIT) >> 2;
9824 inst.instruction |= inst.operands[1].imm & 0xff;
9832 if (do_vfp_nsyn_msr () == SUCCESS)
9835 constraint (!inst.operands[1].isreg,
9836 _("Thumb encoding does not support an immediate here"));
9837 flags = inst.operands[0].imm;
9840 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1),
9841 _("selected processor does not support "
9842 "requested special purpose register"));
9846 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7m),
9847 _("selected processor does not support "
9848 "requested special purpose register"));
9851 inst.instruction |= (flags & SPSR_BIT) >> 2;
9852 inst.instruction |= (flags & ~SPSR_BIT) >> 8;
9853 inst.instruction |= (flags & 0xff);
9854 inst.instruction |= inst.operands[1].reg << 16;
9860 if (!inst.operands[2].present)
9861 inst.operands[2].reg = inst.operands[0].reg;
9863 /* There is no 32-bit MULS and no 16-bit MUL. */
9864 if (unified_syntax && inst.instruction == T_MNEM_mul)
9866 inst.instruction = THUMB_OP32 (inst.instruction);
9867 inst.instruction |= inst.operands[0].reg << 8;
9868 inst.instruction |= inst.operands[1].reg << 16;
9869 inst.instruction |= inst.operands[2].reg << 0;
9873 constraint (!unified_syntax
9874 && inst.instruction == T_MNEM_muls, BAD_THUMB32);
9875 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7,
9878 inst.instruction = THUMB_OP16 (inst.instruction);
9879 inst.instruction |= inst.operands[0].reg;
9881 if (inst.operands[0].reg == inst.operands[1].reg)
9882 inst.instruction |= inst.operands[2].reg << 3;
9883 else if (inst.operands[0].reg == inst.operands[2].reg)
9884 inst.instruction |= inst.operands[1].reg << 3;
9886 constraint (1, _("dest must overlap one source register"));
9893 inst.instruction |= inst.operands[0].reg << 12;
9894 inst.instruction |= inst.operands[1].reg << 8;
9895 inst.instruction |= inst.operands[2].reg << 16;
9896 inst.instruction |= inst.operands[3].reg;
9898 if (inst.operands[0].reg == inst.operands[1].reg)
9899 as_tsktsk (_("rdhi and rdlo must be different"));
9907 if (inst.size_req == 4 || inst.operands[0].imm > 15)
9909 inst.instruction = THUMB_OP32 (inst.instruction);
9910 inst.instruction |= inst.operands[0].imm;
9914 inst.instruction = THUMB_OP16 (inst.instruction);
9915 inst.instruction |= inst.operands[0].imm << 4;
9920 constraint (inst.operands[0].present,
9921 _("Thumb does not support NOP with hints"));
9922 inst.instruction = 0x46c0;
9933 if (THUMB_SETS_FLAGS (inst.instruction))
9934 narrow = (current_it_mask == 0);
9936 narrow = (current_it_mask != 0);
9937 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
9939 if (inst.size_req == 4)
9944 inst.instruction = THUMB_OP32 (inst.instruction);
9945 inst.instruction |= inst.operands[0].reg << 8;
9946 inst.instruction |= inst.operands[1].reg << 16;
9950 inst.instruction = THUMB_OP16 (inst.instruction);
9951 inst.instruction |= inst.operands[0].reg;
9952 inst.instruction |= inst.operands[1].reg << 3;
9957 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7,
9959 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
9961 inst.instruction = THUMB_OP16 (inst.instruction);
9962 inst.instruction |= inst.operands[0].reg;
9963 inst.instruction |= inst.operands[1].reg << 3;
9970 inst.instruction |= inst.operands[0].reg << 8;
9971 inst.instruction |= inst.operands[1].reg << 16;
9972 inst.instruction |= inst.operands[2].reg;
9973 if (inst.operands[3].present)
9975 unsigned int val = inst.reloc.exp.X_add_number;
9976 constraint (inst.reloc.exp.X_op != O_constant,
9977 _("expression too complex"));
9978 inst.instruction |= (val & 0x1c) << 10;
9979 inst.instruction |= (val & 0x03) << 6;
9986 if (!inst.operands[3].present)
9987 inst.instruction &= ~0x00000020;
9994 encode_thumb32_addr_mode (0, /*is_t=*/FALSE, /*is_d=*/FALSE);
9998 do_t_push_pop (void)
10002 constraint (inst.operands[0].writeback,
10003 _("push/pop do not support {reglist}^"));
10004 constraint (inst.reloc.type != BFD_RELOC_UNUSED,
10005 _("expression too complex"));
10007 mask = inst.operands[0].imm;
10008 if ((mask & ~0xff) == 0)
10009 inst.instruction = THUMB_OP16 (inst.instruction) | mask;
10010 else if ((inst.instruction == T_MNEM_push
10011 && (mask & ~0xff) == 1 << REG_LR)
10012 || (inst.instruction == T_MNEM_pop
10013 && (mask & ~0xff) == 1 << REG_PC))
10015 inst.instruction = THUMB_OP16 (inst.instruction);
10016 inst.instruction |= THUMB_PP_PC_LR;
10017 inst.instruction |= mask & 0xff;
10019 else if (unified_syntax)
10021 inst.instruction = THUMB_OP32 (inst.instruction);
10022 encode_thumb2_ldmstm(13, mask, TRUE);
10026 inst.error = _("invalid register list to push/pop instruction");
10034 inst.instruction |= inst.operands[0].reg << 8;
10035 inst.instruction |= inst.operands[1].reg << 16;
10041 inst.instruction |= inst.operands[0].reg << 8;
10042 inst.instruction |= inst.operands[1].reg;
10048 if (inst.operands[0].reg <= 7 && inst.operands[1].reg <= 7
10049 && inst.size_req != 4)
10051 inst.instruction = THUMB_OP16 (inst.instruction);
10052 inst.instruction |= inst.operands[0].reg;
10053 inst.instruction |= inst.operands[1].reg << 3;
10055 else if (unified_syntax)
10057 inst.instruction = THUMB_OP32 (inst.instruction);
10058 inst.instruction |= inst.operands[0].reg << 8;
10059 inst.instruction |= inst.operands[1].reg << 16;
10060 inst.instruction |= inst.operands[1].reg;
10063 inst.error = BAD_HIREG;
10071 Rd = inst.operands[0].reg;
10072 Rs = (inst.operands[1].present
10073 ? inst.operands[1].reg /* Rd, Rs, foo */
10074 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
10076 inst.instruction |= Rd << 8;
10077 inst.instruction |= Rs << 16;
10078 if (!inst.operands[2].isreg)
10080 bfd_boolean narrow;
10082 if ((inst.instruction & 0x00100000) != 0)
10083 narrow = (current_it_mask == 0);
10085 narrow = (current_it_mask != 0);
10087 if (Rd > 7 || Rs > 7)
10090 if (inst.size_req == 4 || !unified_syntax)
10093 if (inst.reloc.exp.X_op != O_constant
10094 || inst.reloc.exp.X_add_number != 0)
10097 /* Turn rsb #0 into 16-bit neg. We should probably do this via
10098 relaxation, but it doesn't seem worth the hassle. */
10101 inst.reloc.type = BFD_RELOC_UNUSED;
10102 inst.instruction = THUMB_OP16 (T_MNEM_negs);
10103 inst.instruction |= Rs << 3;
10104 inst.instruction |= Rd;
10108 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
10109 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
10113 encode_thumb32_shifted_operand (2);
10119 constraint (current_it_mask, BAD_NOT_IT);
10120 if (inst.operands[0].imm)
10121 inst.instruction |= 0x8;
10127 if (!inst.operands[1].present)
10128 inst.operands[1].reg = inst.operands[0].reg;
10130 if (unified_syntax)
10132 bfd_boolean narrow;
10135 switch (inst.instruction)
10138 case T_MNEM_asrs: shift_kind = SHIFT_ASR; break;
10140 case T_MNEM_lsls: shift_kind = SHIFT_LSL; break;
10142 case T_MNEM_lsrs: shift_kind = SHIFT_LSR; break;
10144 case T_MNEM_rors: shift_kind = SHIFT_ROR; break;
10148 if (THUMB_SETS_FLAGS (inst.instruction))
10149 narrow = (current_it_mask == 0);
10151 narrow = (current_it_mask != 0);
10152 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
10154 if (!inst.operands[2].isreg && shift_kind == SHIFT_ROR)
10156 if (inst.operands[2].isreg
10157 && (inst.operands[1].reg != inst.operands[0].reg
10158 || inst.operands[2].reg > 7))
10160 if (inst.size_req == 4)
10165 if (inst.operands[2].isreg)
10167 inst.instruction = THUMB_OP32 (inst.instruction);
10168 inst.instruction |= inst.operands[0].reg << 8;
10169 inst.instruction |= inst.operands[1].reg << 16;
10170 inst.instruction |= inst.operands[2].reg;
10174 inst.operands[1].shifted = 1;
10175 inst.operands[1].shift_kind = shift_kind;
10176 inst.instruction = THUMB_OP32 (THUMB_SETS_FLAGS (inst.instruction)
10177 ? T_MNEM_movs : T_MNEM_mov);
10178 inst.instruction |= inst.operands[0].reg << 8;
10179 encode_thumb32_shifted_operand (1);
10180 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
10181 inst.reloc.type = BFD_RELOC_UNUSED;
10186 if (inst.operands[2].isreg)
10188 switch (shift_kind)
10190 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_R; break;
10191 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_R; break;
10192 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_R; break;
10193 case SHIFT_ROR: inst.instruction = T_OPCODE_ROR_R; break;
10197 inst.instruction |= inst.operands[0].reg;
10198 inst.instruction |= inst.operands[2].reg << 3;
10202 switch (shift_kind)
10204 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
10205 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
10206 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
10209 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
10210 inst.instruction |= inst.operands[0].reg;
10211 inst.instruction |= inst.operands[1].reg << 3;
10217 constraint (inst.operands[0].reg > 7
10218 || inst.operands[1].reg > 7, BAD_HIREG);
10219 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
10221 if (inst.operands[2].isreg) /* Rd, {Rs,} Rn */
10223 constraint (inst.operands[2].reg > 7, BAD_HIREG);
10224 constraint (inst.operands[0].reg != inst.operands[1].reg,
10225 _("source1 and dest must be same register"));
10227 switch (inst.instruction)
10229 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_R; break;
10230 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_R; break;
10231 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_R; break;
10232 case T_MNEM_ror: inst.instruction = T_OPCODE_ROR_R; break;
10236 inst.instruction |= inst.operands[0].reg;
10237 inst.instruction |= inst.operands[2].reg << 3;
10241 switch (inst.instruction)
10243 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_I; break;
10244 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_I; break;
10245 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_I; break;
10246 case T_MNEM_ror: inst.error = _("ror #imm not supported"); return;
10249 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
10250 inst.instruction |= inst.operands[0].reg;
10251 inst.instruction |= inst.operands[1].reg << 3;
10259 inst.instruction |= inst.operands[0].reg << 8;
10260 inst.instruction |= inst.operands[1].reg << 16;
10261 inst.instruction |= inst.operands[2].reg;
10267 unsigned int value = inst.reloc.exp.X_add_number;
10268 constraint (inst.reloc.exp.X_op != O_constant,
10269 _("expression too complex"));
10270 inst.reloc.type = BFD_RELOC_UNUSED;
10271 inst.instruction |= (value & 0xf000) >> 12;
10272 inst.instruction |= (value & 0x0ff0);
10273 inst.instruction |= (value & 0x000f) << 16;
10279 inst.instruction |= inst.operands[0].reg << 8;
10280 inst.instruction |= inst.operands[1].imm - 1;
10281 inst.instruction |= inst.operands[2].reg << 16;
10283 if (inst.operands[3].present)
10285 constraint (inst.reloc.exp.X_op != O_constant,
10286 _("expression too complex"));
10288 if (inst.reloc.exp.X_add_number != 0)
10290 if (inst.operands[3].shift_kind == SHIFT_ASR)
10291 inst.instruction |= 0x00200000; /* sh bit */
10292 inst.instruction |= (inst.reloc.exp.X_add_number & 0x1c) << 10;
10293 inst.instruction |= (inst.reloc.exp.X_add_number & 0x03) << 6;
10295 inst.reloc.type = BFD_RELOC_UNUSED;
10302 inst.instruction |= inst.operands[0].reg << 8;
10303 inst.instruction |= inst.operands[1].imm - 1;
10304 inst.instruction |= inst.operands[2].reg << 16;
10310 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
10311 || inst.operands[2].postind || inst.operands[2].writeback
10312 || inst.operands[2].immisreg || inst.operands[2].shifted
10313 || inst.operands[2].negative,
10316 inst.instruction |= inst.operands[0].reg << 8;
10317 inst.instruction |= inst.operands[1].reg << 12;
10318 inst.instruction |= inst.operands[2].reg << 16;
10319 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8;
10325 if (!inst.operands[2].present)
10326 inst.operands[2].reg = inst.operands[1].reg + 1;
10328 constraint (inst.operands[0].reg == inst.operands[1].reg
10329 || inst.operands[0].reg == inst.operands[2].reg
10330 || inst.operands[0].reg == inst.operands[3].reg
10331 || inst.operands[1].reg == inst.operands[2].reg,
10334 inst.instruction |= inst.operands[0].reg;
10335 inst.instruction |= inst.operands[1].reg << 12;
10336 inst.instruction |= inst.operands[2].reg << 8;
10337 inst.instruction |= inst.operands[3].reg << 16;
10343 inst.instruction |= inst.operands[0].reg << 8;
10344 inst.instruction |= inst.operands[1].reg << 16;
10345 inst.instruction |= inst.operands[2].reg;
10346 inst.instruction |= inst.operands[3].imm << 4;
10352 if (inst.instruction <= 0xffff && inst.size_req != 4
10353 && inst.operands[0].reg <= 7 && inst.operands[1].reg <= 7
10354 && (!inst.operands[2].present || inst.operands[2].imm == 0))
10356 inst.instruction = THUMB_OP16 (inst.instruction);
10357 inst.instruction |= inst.operands[0].reg;
10358 inst.instruction |= inst.operands[1].reg << 3;
10360 else if (unified_syntax)
10362 if (inst.instruction <= 0xffff)
10363 inst.instruction = THUMB_OP32 (inst.instruction);
10364 inst.instruction |= inst.operands[0].reg << 8;
10365 inst.instruction |= inst.operands[1].reg;
10366 inst.instruction |= inst.operands[2].imm << 4;
10370 constraint (inst.operands[2].present && inst.operands[2].imm != 0,
10371 _("Thumb encoding does not support rotation"));
10372 constraint (1, BAD_HIREG);
10379 inst.reloc.type = BFD_RELOC_ARM_SWI;
10387 half = (inst.instruction & 0x10) != 0;
10388 constraint (current_it_mask && current_it_mask != 0x10, BAD_BRANCH);
10389 constraint (inst.operands[0].immisreg,
10390 _("instruction requires register index"));
10391 constraint (inst.operands[0].imm == 15,
10392 _("PC is not a valid index register"));
10393 constraint (!half && inst.operands[0].shifted,
10394 _("instruction does not allow shifted index"));
10395 inst.instruction |= (inst.operands[0].reg << 16) | inst.operands[0].imm;
10401 inst.instruction |= inst.operands[0].reg << 8;
10402 inst.instruction |= inst.operands[1].imm;
10403 inst.instruction |= inst.operands[2].reg << 16;
10405 if (inst.operands[3].present)
10407 constraint (inst.reloc.exp.X_op != O_constant,
10408 _("expression too complex"));
10409 if (inst.reloc.exp.X_add_number != 0)
10411 if (inst.operands[3].shift_kind == SHIFT_ASR)
10412 inst.instruction |= 0x00200000; /* sh bit */
10414 inst.instruction |= (inst.reloc.exp.X_add_number & 0x1c) << 10;
10415 inst.instruction |= (inst.reloc.exp.X_add_number & 0x03) << 6;
10417 inst.reloc.type = BFD_RELOC_UNUSED;
10424 inst.instruction |= inst.operands[0].reg << 8;
10425 inst.instruction |= inst.operands[1].imm;
10426 inst.instruction |= inst.operands[2].reg << 16;
10429 /* Neon instruction encoder helpers. */
10431 /* Encodings for the different types for various Neon opcodes. */
10433 /* An "invalid" code for the following tables. */
10436 struct neon_tab_entry
10439 unsigned float_or_poly;
10440 unsigned scalar_or_imm;
10443 /* Map overloaded Neon opcodes to their respective encodings. */
10444 #define NEON_ENC_TAB \
10445 X(vabd, 0x0000700, 0x1200d00, N_INV), \
10446 X(vmax, 0x0000600, 0x0000f00, N_INV), \
10447 X(vmin, 0x0000610, 0x0200f00, N_INV), \
10448 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
10449 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
10450 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
10451 X(vadd, 0x0000800, 0x0000d00, N_INV), \
10452 X(vsub, 0x1000800, 0x0200d00, N_INV), \
10453 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
10454 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
10455 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
10456 /* Register variants of the following two instructions are encoded as
10457 vcge / vcgt with the operands reversed. */ \
10458 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
10459 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
10460 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
10461 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
10462 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
10463 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
10464 X(vmlal, 0x0800800, N_INV, 0x0800240), \
10465 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
10466 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
10467 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
10468 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
10469 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
10470 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
10471 X(vshl, 0x0000400, N_INV, 0x0800510), \
10472 X(vqshl, 0x0000410, N_INV, 0x0800710), \
10473 X(vand, 0x0000110, N_INV, 0x0800030), \
10474 X(vbic, 0x0100110, N_INV, 0x0800030), \
10475 X(veor, 0x1000110, N_INV, N_INV), \
10476 X(vorn, 0x0300110, N_INV, 0x0800010), \
10477 X(vorr, 0x0200110, N_INV, 0x0800010), \
10478 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
10479 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
10480 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
10481 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
10482 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
10483 X(vst1, 0x0000000, 0x0800000, N_INV), \
10484 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
10485 X(vst2, 0x0000100, 0x0800100, N_INV), \
10486 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
10487 X(vst3, 0x0000200, 0x0800200, N_INV), \
10488 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
10489 X(vst4, 0x0000300, 0x0800300, N_INV), \
10490 X(vmovn, 0x1b20200, N_INV, N_INV), \
10491 X(vtrn, 0x1b20080, N_INV, N_INV), \
10492 X(vqmovn, 0x1b20200, N_INV, N_INV), \
10493 X(vqmovun, 0x1b20240, N_INV, N_INV), \
10494 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
10495 X(vnmla, 0xe000a40, 0xe000b40, N_INV), \
10496 X(vnmls, 0xe100a40, 0xe100b40, N_INV), \
10497 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
10498 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
10499 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
10500 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV)
10504 #define X(OPC,I,F,S) N_MNEM_##OPC
10509 static const struct neon_tab_entry neon_enc_tab[] =
10511 #define X(OPC,I,F,S) { (I), (F), (S) }
10516 #define NEON_ENC_INTEGER(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
10517 #define NEON_ENC_ARMREG(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
10518 #define NEON_ENC_POLY(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
10519 #define NEON_ENC_FLOAT(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
10520 #define NEON_ENC_SCALAR(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
10521 #define NEON_ENC_IMMED(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
10522 #define NEON_ENC_INTERLV(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
10523 #define NEON_ENC_LANE(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
10524 #define NEON_ENC_DUP(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
10525 #define NEON_ENC_SINGLE(X) \
10526 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
10527 #define NEON_ENC_DOUBLE(X) \
10528 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
10530 /* Define shapes for instruction operands. The following mnemonic characters
10531 are used in this table:
10533 F - VFP S<n> register
10534 D - Neon D<n> register
10535 Q - Neon Q<n> register
10539 L - D<n> register list
10541 This table is used to generate various data:
10542 - enumerations of the form NS_DDR to be used as arguments to
10544 - a table classifying shapes into single, double, quad, mixed.
10545 - a table used to drive neon_select_shape.
10548 #define NEON_SHAPE_DEF \
10549 X(3, (D, D, D), DOUBLE), \
10550 X(3, (Q, Q, Q), QUAD), \
10551 X(3, (D, D, I), DOUBLE), \
10552 X(3, (Q, Q, I), QUAD), \
10553 X(3, (D, D, S), DOUBLE), \
10554 X(3, (Q, Q, S), QUAD), \
10555 X(2, (D, D), DOUBLE), \
10556 X(2, (Q, Q), QUAD), \
10557 X(2, (D, S), DOUBLE), \
10558 X(2, (Q, S), QUAD), \
10559 X(2, (D, R), DOUBLE), \
10560 X(2, (Q, R), QUAD), \
10561 X(2, (D, I), DOUBLE), \
10562 X(2, (Q, I), QUAD), \
10563 X(3, (D, L, D), DOUBLE), \
10564 X(2, (D, Q), MIXED), \
10565 X(2, (Q, D), MIXED), \
10566 X(3, (D, Q, I), MIXED), \
10567 X(3, (Q, D, I), MIXED), \
10568 X(3, (Q, D, D), MIXED), \
10569 X(3, (D, Q, Q), MIXED), \
10570 X(3, (Q, Q, D), MIXED), \
10571 X(3, (Q, D, S), MIXED), \
10572 X(3, (D, Q, S), MIXED), \
10573 X(4, (D, D, D, I), DOUBLE), \
10574 X(4, (Q, Q, Q, I), QUAD), \
10575 X(2, (F, F), SINGLE), \
10576 X(3, (F, F, F), SINGLE), \
10577 X(2, (F, I), SINGLE), \
10578 X(2, (F, D), MIXED), \
10579 X(2, (D, F), MIXED), \
10580 X(3, (F, F, I), MIXED), \
10581 X(4, (R, R, F, F), SINGLE), \
10582 X(4, (F, F, R, R), SINGLE), \
10583 X(3, (D, R, R), DOUBLE), \
10584 X(3, (R, R, D), DOUBLE), \
10585 X(2, (S, R), SINGLE), \
10586 X(2, (R, S), SINGLE), \
10587 X(2, (F, R), SINGLE), \
10588 X(2, (R, F), SINGLE)
10590 #define S2(A,B) NS_##A##B
10591 #define S3(A,B,C) NS_##A##B##C
10592 #define S4(A,B,C,D) NS_##A##B##C##D
10594 #define X(N, L, C) S##N L
10607 enum neon_shape_class
10615 #define X(N, L, C) SC_##C
10617 static enum neon_shape_class neon_shape_class[] =
10635 /* Register widths of above. */
10636 static unsigned neon_shape_el_size[] =
10647 struct neon_shape_info
10650 enum neon_shape_el el[NEON_MAX_TYPE_ELS];
10653 #define S2(A,B) { SE_##A, SE_##B }
10654 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
10655 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
10657 #define X(N, L, C) { N, S##N L }
10659 static struct neon_shape_info neon_shape_tab[] =
10669 /* Bit masks used in type checking given instructions.
10670 'N_EQK' means the type must be the same as (or based on in some way) the key
10671 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
10672 set, various other bits can be set as well in order to modify the meaning of
10673 the type constraint. */
10675 enum neon_type_mask
10697 N_KEY = 0x100000, /* key element (main type specifier). */
10698 N_EQK = 0x200000, /* given operand has the same type & size as the key. */
10699 N_VFP = 0x400000, /* VFP mode: operand size must match register width. */
10700 N_DBL = 0x000001, /* if N_EQK, this operand is twice the size. */
10701 N_HLF = 0x000002, /* if N_EQK, this operand is half the size. */
10702 N_SGN = 0x000004, /* if N_EQK, this operand is forced to be signed. */
10703 N_UNS = 0x000008, /* if N_EQK, this operand is forced to be unsigned. */
10704 N_INT = 0x000010, /* if N_EQK, this operand is forced to be integer. */
10705 N_FLT = 0x000020, /* if N_EQK, this operand is forced to be float. */
10706 N_SIZ = 0x000040, /* if N_EQK, this operand is forced to be size-only. */
10708 N_MAX_NONSPECIAL = N_F64
10711 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
10713 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
10714 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
10715 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
10716 #define N_SUF_32 (N_SU_32 | N_F32)
10717 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
10718 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
10720 /* Pass this as the first type argument to neon_check_type to ignore types
10722 #define N_IGNORE_TYPE (N_KEY | N_EQK)
10724 /* Select a "shape" for the current instruction (describing register types or
10725 sizes) from a list of alternatives. Return NS_NULL if the current instruction
10726 doesn't fit. For non-polymorphic shapes, checking is usually done as a
10727 function of operand parsing, so this function doesn't need to be called.
10728 Shapes should be listed in order of decreasing length. */
10730 static enum neon_shape
10731 neon_select_shape (enum neon_shape shape, ...)
10734 enum neon_shape first_shape = shape;
10736 /* Fix missing optional operands. FIXME: we don't know at this point how
10737 many arguments we should have, so this makes the assumption that we have
10738 > 1. This is true of all current Neon opcodes, I think, but may not be
10739 true in the future. */
10740 if (!inst.operands[1].present)
10741 inst.operands[1] = inst.operands[0];
10743 va_start (ap, shape);
10745 for (; shape != NS_NULL; shape = va_arg (ap, int))
10750 for (j = 0; j < neon_shape_tab[shape].els; j++)
10752 if (!inst.operands[j].present)
10758 switch (neon_shape_tab[shape].el[j])
10761 if (!(inst.operands[j].isreg
10762 && inst.operands[j].isvec
10763 && inst.operands[j].issingle
10764 && !inst.operands[j].isquad))
10769 if (!(inst.operands[j].isreg
10770 && inst.operands[j].isvec
10771 && !inst.operands[j].isquad
10772 && !inst.operands[j].issingle))
10777 if (!(inst.operands[j].isreg
10778 && !inst.operands[j].isvec))
10783 if (!(inst.operands[j].isreg
10784 && inst.operands[j].isvec
10785 && inst.operands[j].isquad
10786 && !inst.operands[j].issingle))
10791 if (!(!inst.operands[j].isreg
10792 && !inst.operands[j].isscalar))
10797 if (!(!inst.operands[j].isreg
10798 && inst.operands[j].isscalar))
10812 if (shape == NS_NULL && first_shape != NS_NULL)
10813 first_error (_("invalid instruction shape"));
10818 /* True if SHAPE is predominantly a quadword operation (most of the time, this
10819 means the Q bit should be set). */
10822 neon_quad (enum neon_shape shape)
10824 return neon_shape_class[shape] == SC_QUAD;
10828 neon_modify_type_size (unsigned typebits, enum neon_el_type *g_type,
10831 /* Allow modification to be made to types which are constrained to be
10832 based on the key element, based on bits set alongside N_EQK. */
10833 if ((typebits & N_EQK) != 0)
10835 if ((typebits & N_HLF) != 0)
10837 else if ((typebits & N_DBL) != 0)
10839 if ((typebits & N_SGN) != 0)
10840 *g_type = NT_signed;
10841 else if ((typebits & N_UNS) != 0)
10842 *g_type = NT_unsigned;
10843 else if ((typebits & N_INT) != 0)
10844 *g_type = NT_integer;
10845 else if ((typebits & N_FLT) != 0)
10846 *g_type = NT_float;
10847 else if ((typebits & N_SIZ) != 0)
10848 *g_type = NT_untyped;
10852 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
10853 operand type, i.e. the single type specified in a Neon instruction when it
10854 is the only one given. */
10856 static struct neon_type_el
10857 neon_type_promote (struct neon_type_el *key, unsigned thisarg)
10859 struct neon_type_el dest = *key;
10861 assert ((thisarg & N_EQK) != 0);
10863 neon_modify_type_size (thisarg, &dest.type, &dest.size);
10868 /* Convert Neon type and size into compact bitmask representation. */
10870 static enum neon_type_mask
10871 type_chk_of_el_type (enum neon_el_type type, unsigned size)
10878 case 8: return N_8;
10879 case 16: return N_16;
10880 case 32: return N_32;
10881 case 64: return N_64;
10889 case 8: return N_I8;
10890 case 16: return N_I16;
10891 case 32: return N_I32;
10892 case 64: return N_I64;
10900 case 32: return N_F32;
10901 case 64: return N_F64;
10909 case 8: return N_P8;
10910 case 16: return N_P16;
10918 case 8: return N_S8;
10919 case 16: return N_S16;
10920 case 32: return N_S32;
10921 case 64: return N_S64;
10929 case 8: return N_U8;
10930 case 16: return N_U16;
10931 case 32: return N_U32;
10932 case 64: return N_U64;
10943 /* Convert compact Neon bitmask type representation to a type and size. Only
10944 handles the case where a single bit is set in the mask. */
10947 el_type_of_type_chk (enum neon_el_type *type, unsigned *size,
10948 enum neon_type_mask mask)
10950 if ((mask & N_EQK) != 0)
10953 if ((mask & (N_S8 | N_U8 | N_I8 | N_8 | N_P8)) != 0)
10955 else if ((mask & (N_S16 | N_U16 | N_I16 | N_16 | N_P16)) != 0)
10957 else if ((mask & (N_S32 | N_U32 | N_I32 | N_32 | N_F32)) != 0)
10959 else if ((mask & (N_S64 | N_U64 | N_I64 | N_64 | N_F64)) != 0)
10964 if ((mask & (N_S8 | N_S16 | N_S32 | N_S64)) != 0)
10966 else if ((mask & (N_U8 | N_U16 | N_U32 | N_U64)) != 0)
10967 *type = NT_unsigned;
10968 else if ((mask & (N_I8 | N_I16 | N_I32 | N_I64)) != 0)
10969 *type = NT_integer;
10970 else if ((mask & (N_8 | N_16 | N_32 | N_64)) != 0)
10971 *type = NT_untyped;
10972 else if ((mask & (N_P8 | N_P16)) != 0)
10974 else if ((mask & (N_F32 | N_F64)) != 0)
10982 /* Modify a bitmask of allowed types. This is only needed for type
10986 modify_types_allowed (unsigned allowed, unsigned mods)
10989 enum neon_el_type type;
10995 for (i = 1; i <= N_MAX_NONSPECIAL; i <<= 1)
10997 if (el_type_of_type_chk (&type, &size, allowed & i) == SUCCESS)
10999 neon_modify_type_size (mods, &type, &size);
11000 destmask |= type_chk_of_el_type (type, size);
11007 /* Check type and return type classification.
11008 The manual states (paraphrase): If one datatype is given, it indicates the
11010 - the second operand, if there is one
11011 - the operand, if there is no second operand
11012 - the result, if there are no operands.
11013 This isn't quite good enough though, so we use a concept of a "key" datatype
11014 which is set on a per-instruction basis, which is the one which matters when
11015 only one data type is written.
11016 Note: this function has side-effects (e.g. filling in missing operands). All
11017 Neon instructions should call it before performing bit encoding. */
11019 static struct neon_type_el
11020 neon_check_type (unsigned els, enum neon_shape ns, ...)
11023 unsigned i, pass, key_el = 0;
11024 unsigned types[NEON_MAX_TYPE_ELS];
11025 enum neon_el_type k_type = NT_invtype;
11026 unsigned k_size = -1u;
11027 struct neon_type_el badtype = {NT_invtype, -1};
11028 unsigned key_allowed = 0;
11030 /* Optional registers in Neon instructions are always (not) in operand 1.
11031 Fill in the missing operand here, if it was omitted. */
11032 if (els > 1 && !inst.operands[1].present)
11033 inst.operands[1] = inst.operands[0];
11035 /* Suck up all the varargs. */
11037 for (i = 0; i < els; i++)
11039 unsigned thisarg = va_arg (ap, unsigned);
11040 if (thisarg == N_IGNORE_TYPE)
11045 types[i] = thisarg;
11046 if ((thisarg & N_KEY) != 0)
11051 if (inst.vectype.elems > 0)
11052 for (i = 0; i < els; i++)
11053 if (inst.operands[i].vectype.type != NT_invtype)
11055 first_error (_("types specified in both the mnemonic and operands"));
11059 /* Duplicate inst.vectype elements here as necessary.
11060 FIXME: No idea if this is exactly the same as the ARM assembler,
11061 particularly when an insn takes one register and one non-register
11063 if (inst.vectype.elems == 1 && els > 1)
11066 inst.vectype.elems = els;
11067 inst.vectype.el[key_el] = inst.vectype.el[0];
11068 for (j = 0; j < els; j++)
11070 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
11073 else if (inst.vectype.elems == 0 && els > 0)
11076 /* No types were given after the mnemonic, so look for types specified
11077 after each operand. We allow some flexibility here; as long as the
11078 "key" operand has a type, we can infer the others. */
11079 for (j = 0; j < els; j++)
11080 if (inst.operands[j].vectype.type != NT_invtype)
11081 inst.vectype.el[j] = inst.operands[j].vectype;
11083 if (inst.operands[key_el].vectype.type != NT_invtype)
11085 for (j = 0; j < els; j++)
11086 if (inst.operands[j].vectype.type == NT_invtype)
11087 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
11092 first_error (_("operand types can't be inferred"));
11096 else if (inst.vectype.elems != els)
11098 first_error (_("type specifier has the wrong number of parts"));
11102 for (pass = 0; pass < 2; pass++)
11104 for (i = 0; i < els; i++)
11106 unsigned thisarg = types[i];
11107 unsigned types_allowed = ((thisarg & N_EQK) != 0 && pass != 0)
11108 ? modify_types_allowed (key_allowed, thisarg) : thisarg;
11109 enum neon_el_type g_type = inst.vectype.el[i].type;
11110 unsigned g_size = inst.vectype.el[i].size;
11112 /* Decay more-specific signed & unsigned types to sign-insensitive
11113 integer types if sign-specific variants are unavailable. */
11114 if ((g_type == NT_signed || g_type == NT_unsigned)
11115 && (types_allowed & N_SU_ALL) == 0)
11116 g_type = NT_integer;
11118 /* If only untyped args are allowed, decay any more specific types to
11119 them. Some instructions only care about signs for some element
11120 sizes, so handle that properly. */
11121 if ((g_size == 8 && (types_allowed & N_8) != 0)
11122 || (g_size == 16 && (types_allowed & N_16) != 0)
11123 || (g_size == 32 && (types_allowed & N_32) != 0)
11124 || (g_size == 64 && (types_allowed & N_64) != 0))
11125 g_type = NT_untyped;
11129 if ((thisarg & N_KEY) != 0)
11133 key_allowed = thisarg & ~N_KEY;
11138 if ((thisarg & N_VFP) != 0)
11140 enum neon_shape_el regshape = neon_shape_tab[ns].el[i];
11141 unsigned regwidth = neon_shape_el_size[regshape], match;
11143 /* In VFP mode, operands must match register widths. If we
11144 have a key operand, use its width, else use the width of
11145 the current operand. */
11151 if (regwidth != match)
11153 first_error (_("operand size must match register width"));
11158 if ((thisarg & N_EQK) == 0)
11160 unsigned given_type = type_chk_of_el_type (g_type, g_size);
11162 if ((given_type & types_allowed) == 0)
11164 first_error (_("bad type in Neon instruction"));
11170 enum neon_el_type mod_k_type = k_type;
11171 unsigned mod_k_size = k_size;
11172 neon_modify_type_size (thisarg, &mod_k_type, &mod_k_size);
11173 if (g_type != mod_k_type || g_size != mod_k_size)
11175 first_error (_("inconsistent types in Neon instruction"));
11183 return inst.vectype.el[key_el];
11186 /* Neon-style VFP instruction forwarding. */
11188 /* Thumb VFP instructions have 0xE in the condition field. */
11191 do_vfp_cond_or_thumb (void)
11194 inst.instruction |= 0xe0000000;
11196 inst.instruction |= inst.cond << 28;
11199 /* Look up and encode a simple mnemonic, for use as a helper function for the
11200 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
11201 etc. It is assumed that operand parsing has already been done, and that the
11202 operands are in the form expected by the given opcode (this isn't necessarily
11203 the same as the form in which they were parsed, hence some massaging must
11204 take place before this function is called).
11205 Checks current arch version against that in the looked-up opcode. */
11208 do_vfp_nsyn_opcode (const char *opname)
11210 const struct asm_opcode *opcode;
11212 opcode = hash_find (arm_ops_hsh, opname);
11217 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant,
11218 thumb_mode ? *opcode->tvariant : *opcode->avariant),
11223 inst.instruction = opcode->tvalue;
11224 opcode->tencode ();
11228 inst.instruction = (inst.cond << 28) | opcode->avalue;
11229 opcode->aencode ();
11234 do_vfp_nsyn_add_sub (enum neon_shape rs)
11236 int is_add = (inst.instruction & 0x0fffffff) == N_MNEM_vadd;
11241 do_vfp_nsyn_opcode ("fadds");
11243 do_vfp_nsyn_opcode ("fsubs");
11248 do_vfp_nsyn_opcode ("faddd");
11250 do_vfp_nsyn_opcode ("fsubd");
11254 /* Check operand types to see if this is a VFP instruction, and if so call
11258 try_vfp_nsyn (int args, void (*pfn) (enum neon_shape))
11260 enum neon_shape rs;
11261 struct neon_type_el et;
11266 rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
11267 et = neon_check_type (2, rs,
11268 N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
11272 rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
11273 et = neon_check_type (3, rs,
11274 N_EQK | N_VFP, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
11281 if (et.type != NT_invtype)
11293 do_vfp_nsyn_mla_mls (enum neon_shape rs)
11295 int is_mla = (inst.instruction & 0x0fffffff) == N_MNEM_vmla;
11300 do_vfp_nsyn_opcode ("fmacs");
11302 do_vfp_nsyn_opcode ("fmscs");
11307 do_vfp_nsyn_opcode ("fmacd");
11309 do_vfp_nsyn_opcode ("fmscd");
11314 do_vfp_nsyn_mul (enum neon_shape rs)
11317 do_vfp_nsyn_opcode ("fmuls");
11319 do_vfp_nsyn_opcode ("fmuld");
11323 do_vfp_nsyn_abs_neg (enum neon_shape rs)
11325 int is_neg = (inst.instruction & 0x80) != 0;
11326 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_VFP | N_KEY);
11331 do_vfp_nsyn_opcode ("fnegs");
11333 do_vfp_nsyn_opcode ("fabss");
11338 do_vfp_nsyn_opcode ("fnegd");
11340 do_vfp_nsyn_opcode ("fabsd");
11344 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
11345 insns belong to Neon, and are handled elsewhere. */
11348 do_vfp_nsyn_ldm_stm (int is_dbmode)
11350 int is_ldm = (inst.instruction & (1 << 20)) != 0;
11354 do_vfp_nsyn_opcode ("fldmdbs");
11356 do_vfp_nsyn_opcode ("fldmias");
11361 do_vfp_nsyn_opcode ("fstmdbs");
11363 do_vfp_nsyn_opcode ("fstmias");
11368 do_vfp_nsyn_sqrt (void)
11370 enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
11371 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
11374 do_vfp_nsyn_opcode ("fsqrts");
11376 do_vfp_nsyn_opcode ("fsqrtd");
11380 do_vfp_nsyn_div (void)
11382 enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
11383 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
11384 N_F32 | N_F64 | N_KEY | N_VFP);
11387 do_vfp_nsyn_opcode ("fdivs");
11389 do_vfp_nsyn_opcode ("fdivd");
11393 do_vfp_nsyn_nmul (void)
11395 enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
11396 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
11397 N_F32 | N_F64 | N_KEY | N_VFP);
11401 inst.instruction = NEON_ENC_SINGLE (inst.instruction);
11402 do_vfp_sp_dyadic ();
11406 inst.instruction = NEON_ENC_DOUBLE (inst.instruction);
11407 do_vfp_dp_rd_rn_rm ();
11409 do_vfp_cond_or_thumb ();
11413 do_vfp_nsyn_cmp (void)
11415 if (inst.operands[1].isreg)
11417 enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
11418 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
11422 inst.instruction = NEON_ENC_SINGLE (inst.instruction);
11423 do_vfp_sp_monadic ();
11427 inst.instruction = NEON_ENC_DOUBLE (inst.instruction);
11428 do_vfp_dp_rd_rm ();
11433 enum neon_shape rs = neon_select_shape (NS_FI, NS_DI, NS_NULL);
11434 neon_check_type (2, rs, N_F32 | N_F64 | N_KEY | N_VFP, N_EQK);
11436 switch (inst.instruction & 0x0fffffff)
11439 inst.instruction += N_MNEM_vcmpz - N_MNEM_vcmp;
11442 inst.instruction += N_MNEM_vcmpez - N_MNEM_vcmpe;
11450 inst.instruction = NEON_ENC_SINGLE (inst.instruction);
11451 do_vfp_sp_compare_z ();
11455 inst.instruction = NEON_ENC_DOUBLE (inst.instruction);
11459 do_vfp_cond_or_thumb ();
11463 nsyn_insert_sp (void)
11465 inst.operands[1] = inst.operands[0];
11466 memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
11467 inst.operands[0].reg = 13;
11468 inst.operands[0].isreg = 1;
11469 inst.operands[0].writeback = 1;
11470 inst.operands[0].present = 1;
11474 do_vfp_nsyn_push (void)
11477 if (inst.operands[1].issingle)
11478 do_vfp_nsyn_opcode ("fstmdbs");
11480 do_vfp_nsyn_opcode ("fstmdbd");
11484 do_vfp_nsyn_pop (void)
11487 if (inst.operands[1].issingle)
11488 do_vfp_nsyn_opcode ("fldmias");
11490 do_vfp_nsyn_opcode ("fldmiad");
11493 /* Fix up Neon data-processing instructions, ORing in the correct bits for
11494 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
11497 neon_dp_fixup (unsigned i)
11501 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
11515 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
11519 neon_logbits (unsigned x)
11521 return ffs (x) - 4;
11524 #define LOW4(R) ((R) & 0xf)
11525 #define HI1(R) (((R) >> 4) & 1)
11527 /* Encode insns with bit pattern:
11529 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
11530 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
11532 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
11533 different meaning for some instruction. */
11536 neon_three_same (int isquad, int ubit, int size)
11538 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
11539 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
11540 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
11541 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
11542 inst.instruction |= LOW4 (inst.operands[2].reg);
11543 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
11544 inst.instruction |= (isquad != 0) << 6;
11545 inst.instruction |= (ubit != 0) << 24;
11547 inst.instruction |= neon_logbits (size) << 20;
11549 inst.instruction = neon_dp_fixup (inst.instruction);
11552 /* Encode instructions of the form:
11554 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
11555 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
11557 Don't write size if SIZE == -1. */
11560 neon_two_same (int qbit, int ubit, int size)
11562 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
11563 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
11564 inst.instruction |= LOW4 (inst.operands[1].reg);
11565 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
11566 inst.instruction |= (qbit != 0) << 6;
11567 inst.instruction |= (ubit != 0) << 24;
11570 inst.instruction |= neon_logbits (size) << 18;
11572 inst.instruction = neon_dp_fixup (inst.instruction);
11575 /* Neon instruction encoders, in approximate order of appearance. */
11578 do_neon_dyadic_i_su (void)
11580 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
11581 struct neon_type_el et = neon_check_type (3, rs,
11582 N_EQK, N_EQK, N_SU_32 | N_KEY);
11583 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
11587 do_neon_dyadic_i64_su (void)
11589 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
11590 struct neon_type_el et = neon_check_type (3, rs,
11591 N_EQK, N_EQK, N_SU_ALL | N_KEY);
11592 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
11596 neon_imm_shift (int write_ubit, int uval, int isquad, struct neon_type_el et,
11599 unsigned size = et.size >> 3;
11600 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
11601 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
11602 inst.instruction |= LOW4 (inst.operands[1].reg);
11603 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
11604 inst.instruction |= (isquad != 0) << 6;
11605 inst.instruction |= immbits << 16;
11606 inst.instruction |= (size >> 3) << 7;
11607 inst.instruction |= (size & 0x7) << 19;
11609 inst.instruction |= (uval != 0) << 24;
11611 inst.instruction = neon_dp_fixup (inst.instruction);
11615 do_neon_shl_imm (void)
11617 if (!inst.operands[2].isreg)
11619 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
11620 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_KEY | N_I_ALL);
11621 inst.instruction = NEON_ENC_IMMED (inst.instruction);
11622 neon_imm_shift (FALSE, 0, neon_quad (rs), et, inst.operands[2].imm);
11626 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
11627 struct neon_type_el et = neon_check_type (3, rs,
11628 N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN);
11631 /* VSHL/VQSHL 3-register variants have syntax such as:
11633 whereas other 3-register operations encoded by neon_three_same have
11636 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
11638 tmp = inst.operands[2].reg;
11639 inst.operands[2].reg = inst.operands[1].reg;
11640 inst.operands[1].reg = tmp;
11641 inst.instruction = NEON_ENC_INTEGER (inst.instruction);
11642 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
11647 do_neon_qshl_imm (void)
11649 if (!inst.operands[2].isreg)
11651 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
11652 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
11654 inst.instruction = NEON_ENC_IMMED (inst.instruction);
11655 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et,
11656 inst.operands[2].imm);
11660 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
11661 struct neon_type_el et = neon_check_type (3, rs,
11662 N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN);
11665 /* See note in do_neon_shl_imm. */
11666 tmp = inst.operands[2].reg;
11667 inst.operands[2].reg = inst.operands[1].reg;
11668 inst.operands[1].reg = tmp;
11669 inst.instruction = NEON_ENC_INTEGER (inst.instruction);
11670 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
11675 do_neon_rshl (void)
11677 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
11678 struct neon_type_el et = neon_check_type (3, rs,
11679 N_EQK, N_EQK, N_SU_ALL | N_KEY);
11682 tmp = inst.operands[2].reg;
11683 inst.operands[2].reg = inst.operands[1].reg;
11684 inst.operands[1].reg = tmp;
11685 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
11689 neon_cmode_for_logic_imm (unsigned immediate, unsigned *immbits, int size)
11691 /* Handle .I8 pseudo-instructions. */
11694 /* Unfortunately, this will make everything apart from zero out-of-range.
11695 FIXME is this the intended semantics? There doesn't seem much point in
11696 accepting .I8 if so. */
11697 immediate |= immediate << 8;
11703 if (immediate == (immediate & 0x000000ff))
11705 *immbits = immediate;
11708 else if (immediate == (immediate & 0x0000ff00))
11710 *immbits = immediate >> 8;
11713 else if (immediate == (immediate & 0x00ff0000))
11715 *immbits = immediate >> 16;
11718 else if (immediate == (immediate & 0xff000000))
11720 *immbits = immediate >> 24;
11723 if ((immediate & 0xffff) != (immediate >> 16))
11724 goto bad_immediate;
11725 immediate &= 0xffff;
11728 if (immediate == (immediate & 0x000000ff))
11730 *immbits = immediate;
11733 else if (immediate == (immediate & 0x0000ff00))
11735 *immbits = immediate >> 8;
11740 first_error (_("immediate value out of range"));
11744 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
11748 neon_bits_same_in_bytes (unsigned imm)
11750 return ((imm & 0x000000ff) == 0 || (imm & 0x000000ff) == 0x000000ff)
11751 && ((imm & 0x0000ff00) == 0 || (imm & 0x0000ff00) == 0x0000ff00)
11752 && ((imm & 0x00ff0000) == 0 || (imm & 0x00ff0000) == 0x00ff0000)
11753 && ((imm & 0xff000000) == 0 || (imm & 0xff000000) == 0xff000000);
11756 /* For immediate of above form, return 0bABCD. */
11759 neon_squash_bits (unsigned imm)
11761 return (imm & 0x01) | ((imm & 0x0100) >> 7) | ((imm & 0x010000) >> 14)
11762 | ((imm & 0x01000000) >> 21);
11765 /* Compress quarter-float representation to 0b...000 abcdefgh. */
11768 neon_qfloat_bits (unsigned imm)
11770 return ((imm >> 19) & 0x7f) | ((imm >> 24) & 0x80);
11773 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
11774 the instruction. *OP is passed as the initial value of the op field, and
11775 may be set to a different value depending on the constant (i.e.
11776 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
11777 MVN). If the immediate looks like a repeated parttern then also
11778 try smaller element sizes. */
11781 neon_cmode_for_move_imm (unsigned immlo, unsigned immhi, int float_p,
11782 unsigned *immbits, int *op, int size,
11783 enum neon_el_type type)
11785 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
11787 if (type == NT_float && !float_p)
11790 if (type == NT_float && is_quarter_float (immlo) && immhi == 0)
11792 if (size != 32 || *op == 1)
11794 *immbits = neon_qfloat_bits (immlo);
11800 if (neon_bits_same_in_bytes (immhi)
11801 && neon_bits_same_in_bytes (immlo))
11805 *immbits = (neon_squash_bits (immhi) << 4)
11806 | neon_squash_bits (immlo);
11811 if (immhi != immlo)
11817 if (immlo == (immlo & 0x000000ff))
11822 else if (immlo == (immlo & 0x0000ff00))
11824 *immbits = immlo >> 8;
11827 else if (immlo == (immlo & 0x00ff0000))
11829 *immbits = immlo >> 16;
11832 else if (immlo == (immlo & 0xff000000))
11834 *immbits = immlo >> 24;
11837 else if (immlo == ((immlo & 0x0000ff00) | 0x000000ff))
11839 *immbits = (immlo >> 8) & 0xff;
11842 else if (immlo == ((immlo & 0x00ff0000) | 0x0000ffff))
11844 *immbits = (immlo >> 16) & 0xff;
11848 if ((immlo & 0xffff) != (immlo >> 16))
11855 if (immlo == (immlo & 0x000000ff))
11860 else if (immlo == (immlo & 0x0000ff00))
11862 *immbits = immlo >> 8;
11866 if ((immlo & 0xff) != (immlo >> 8))
11871 if (immlo == (immlo & 0x000000ff))
11873 /* Don't allow MVN with 8-bit immediate. */
11883 /* Write immediate bits [7:0] to the following locations:
11885 |28/24|23 19|18 16|15 4|3 0|
11886 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
11888 This function is used by VMOV/VMVN/VORR/VBIC. */
11891 neon_write_immbits (unsigned immbits)
11893 inst.instruction |= immbits & 0xf;
11894 inst.instruction |= ((immbits >> 4) & 0x7) << 16;
11895 inst.instruction |= ((immbits >> 7) & 0x1) << 24;
11898 /* Invert low-order SIZE bits of XHI:XLO. */
11901 neon_invert_size (unsigned *xlo, unsigned *xhi, int size)
11903 unsigned immlo = xlo ? *xlo : 0;
11904 unsigned immhi = xhi ? *xhi : 0;
11909 immlo = (~immlo) & 0xff;
11913 immlo = (~immlo) & 0xffff;
11917 immhi = (~immhi) & 0xffffffff;
11918 /* fall through. */
11921 immlo = (~immlo) & 0xffffffff;
11936 do_neon_logic (void)
11938 if (inst.operands[2].present && inst.operands[2].isreg)
11940 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
11941 neon_check_type (3, rs, N_IGNORE_TYPE);
11942 /* U bit and size field were set as part of the bitmask. */
11943 inst.instruction = NEON_ENC_INTEGER (inst.instruction);
11944 neon_three_same (neon_quad (rs), 0, -1);
11948 enum neon_shape rs = neon_select_shape (NS_DI, NS_QI, NS_NULL);
11949 struct neon_type_el et = neon_check_type (2, rs,
11950 N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK);
11951 enum neon_opc opcode = inst.instruction & 0x0fffffff;
11955 if (et.type == NT_invtype)
11958 inst.instruction = NEON_ENC_IMMED (inst.instruction);
11960 immbits = inst.operands[1].imm;
11963 /* .i64 is a pseudo-op, so the immediate must be a repeating
11965 if (immbits != (inst.operands[1].regisimm ?
11966 inst.operands[1].reg : 0))
11968 /* Set immbits to an invalid constant. */
11969 immbits = 0xdeadbeef;
11976 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
11980 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
11984 /* Pseudo-instruction for VBIC. */
11985 neon_invert_size (&immbits, 0, et.size);
11986 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
11990 /* Pseudo-instruction for VORR. */
11991 neon_invert_size (&immbits, 0, et.size);
11992 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
12002 inst.instruction |= neon_quad (rs) << 6;
12003 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
12004 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
12005 inst.instruction |= cmode << 8;
12006 neon_write_immbits (immbits);
12008 inst.instruction = neon_dp_fixup (inst.instruction);
12013 do_neon_bitfield (void)
12015 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
12016 neon_check_type (3, rs, N_IGNORE_TYPE);
12017 neon_three_same (neon_quad (rs), 0, -1);
12021 neon_dyadic_misc (enum neon_el_type ubit_meaning, unsigned types,
12024 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
12025 struct neon_type_el et = neon_check_type (3, rs, N_EQK | destbits, N_EQK,
12027 if (et.type == NT_float)
12029 inst.instruction = NEON_ENC_FLOAT (inst.instruction);
12030 neon_three_same (neon_quad (rs), 0, -1);
12034 inst.instruction = NEON_ENC_INTEGER (inst.instruction);
12035 neon_three_same (neon_quad (rs), et.type == ubit_meaning, et.size);
12040 do_neon_dyadic_if_su (void)
12042 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0);
12046 do_neon_dyadic_if_su_d (void)
12048 /* This version only allow D registers, but that constraint is enforced during
12049 operand parsing so we don't need to do anything extra here. */
12050 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0);
12054 do_neon_dyadic_if_i_d (void)
12056 /* The "untyped" case can't happen. Do this to stop the "U" bit being
12057 affected if we specify unsigned args. */
12058 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
12061 enum vfp_or_neon_is_neon_bits
12064 NEON_CHECK_ARCH = 2
12067 /* Call this function if an instruction which may have belonged to the VFP or
12068 Neon instruction sets, but turned out to be a Neon instruction (due to the
12069 operand types involved, etc.). We have to check and/or fix-up a couple of
12072 - Make sure the user hasn't attempted to make a Neon instruction
12074 - Alter the value in the condition code field if necessary.
12075 - Make sure that the arch supports Neon instructions.
12077 Which of these operations take place depends on bits from enum
12078 vfp_or_neon_is_neon_bits.
12080 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
12081 current instruction's condition is COND_ALWAYS, the condition field is
12082 changed to inst.uncond_value. This is necessary because instructions shared
12083 between VFP and Neon may be conditional for the VFP variants only, and the
12084 unconditional Neon version must have, e.g., 0xF in the condition field. */
12087 vfp_or_neon_is_neon (unsigned check)
12089 /* Conditions are always legal in Thumb mode (IT blocks). */
12090 if (!thumb_mode && (check & NEON_CHECK_CC))
12092 if (inst.cond != COND_ALWAYS)
12094 first_error (_(BAD_COND));
12097 if (inst.uncond_value != -1)
12098 inst.instruction |= inst.uncond_value << 28;
12101 if ((check & NEON_CHECK_ARCH)
12102 && !ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1))
12104 first_error (_(BAD_FPU));
12112 do_neon_addsub_if_i (void)
12114 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub) == SUCCESS)
12117 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
12120 /* The "untyped" case can't happen. Do this to stop the "U" bit being
12121 affected if we specify unsigned args. */
12122 neon_dyadic_misc (NT_untyped, N_IF_32 | N_I64, 0);
12125 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
12127 V<op> A,B (A is operand 0, B is operand 2)
12132 so handle that case specially. */
12135 neon_exchange_operands (void)
12137 void *scratch = alloca (sizeof (inst.operands[0]));
12138 if (inst.operands[1].present)
12140 /* Swap operands[1] and operands[2]. */
12141 memcpy (scratch, &inst.operands[1], sizeof (inst.operands[0]));
12142 inst.operands[1] = inst.operands[2];
12143 memcpy (&inst.operands[2], scratch, sizeof (inst.operands[0]));
12147 inst.operands[1] = inst.operands[2];
12148 inst.operands[2] = inst.operands[0];
12153 neon_compare (unsigned regtypes, unsigned immtypes, int invert)
12155 if (inst.operands[2].isreg)
12158 neon_exchange_operands ();
12159 neon_dyadic_misc (NT_unsigned, regtypes, N_SIZ);
12163 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
12164 struct neon_type_el et = neon_check_type (2, rs,
12165 N_EQK | N_SIZ, immtypes | N_KEY);
12167 inst.instruction = NEON_ENC_IMMED (inst.instruction);
12168 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
12169 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
12170 inst.instruction |= LOW4 (inst.operands[1].reg);
12171 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
12172 inst.instruction |= neon_quad (rs) << 6;
12173 inst.instruction |= (et.type == NT_float) << 10;
12174 inst.instruction |= neon_logbits (et.size) << 18;
12176 inst.instruction = neon_dp_fixup (inst.instruction);
12183 neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, FALSE);
12187 do_neon_cmp_inv (void)
12189 neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, TRUE);
12195 neon_compare (N_IF_32, N_IF_32, FALSE);
12198 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
12199 scalars, which are encoded in 5 bits, M : Rm.
12200 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
12201 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
12205 neon_scalar_for_mul (unsigned scalar, unsigned elsize)
12207 unsigned regno = NEON_SCALAR_REG (scalar);
12208 unsigned elno = NEON_SCALAR_INDEX (scalar);
12213 if (regno > 7 || elno > 3)
12215 return regno | (elno << 3);
12218 if (regno > 15 || elno > 1)
12220 return regno | (elno << 4);
12224 first_error (_("scalar out of range for multiply instruction"));
12230 /* Encode multiply / multiply-accumulate scalar instructions. */
12233 neon_mul_mac (struct neon_type_el et, int ubit)
12237 /* Give a more helpful error message if we have an invalid type. */
12238 if (et.type == NT_invtype)
12241 scalar = neon_scalar_for_mul (inst.operands[2].reg, et.size);
12242 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
12243 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
12244 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
12245 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
12246 inst.instruction |= LOW4 (scalar);
12247 inst.instruction |= HI1 (scalar) << 5;
12248 inst.instruction |= (et.type == NT_float) << 8;
12249 inst.instruction |= neon_logbits (et.size) << 20;
12250 inst.instruction |= (ubit != 0) << 24;
12252 inst.instruction = neon_dp_fixup (inst.instruction);
12256 do_neon_mac_maybe_scalar (void)
12258 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls) == SUCCESS)
12261 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
12264 if (inst.operands[2].isscalar)
12266 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
12267 struct neon_type_el et = neon_check_type (3, rs,
12268 N_EQK, N_EQK, N_I16 | N_I32 | N_F32 | N_KEY);
12269 inst.instruction = NEON_ENC_SCALAR (inst.instruction);
12270 neon_mul_mac (et, neon_quad (rs));
12274 /* The "untyped" case can't happen. Do this to stop the "U" bit being
12275 affected if we specify unsigned args. */
12276 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
12283 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
12284 struct neon_type_el et = neon_check_type (3, rs,
12285 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_KEY);
12286 neon_three_same (neon_quad (rs), 0, et.size);
12289 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
12290 same types as the MAC equivalents. The polynomial type for this instruction
12291 is encoded the same as the integer type. */
12296 if (try_vfp_nsyn (3, do_vfp_nsyn_mul) == SUCCESS)
12299 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
12302 if (inst.operands[2].isscalar)
12303 do_neon_mac_maybe_scalar ();
12305 neon_dyadic_misc (NT_poly, N_I8 | N_I16 | N_I32 | N_F32 | N_P8, 0);
12309 do_neon_qdmulh (void)
12311 if (inst.operands[2].isscalar)
12313 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
12314 struct neon_type_el et = neon_check_type (3, rs,
12315 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
12316 inst.instruction = NEON_ENC_SCALAR (inst.instruction);
12317 neon_mul_mac (et, neon_quad (rs));
12321 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
12322 struct neon_type_el et = neon_check_type (3, rs,
12323 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
12324 inst.instruction = NEON_ENC_INTEGER (inst.instruction);
12325 /* The U bit (rounding) comes from bit mask. */
12326 neon_three_same (neon_quad (rs), 0, et.size);
12331 do_neon_fcmp_absolute (void)
12333 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
12334 neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY);
12335 /* Size field comes from bit mask. */
12336 neon_three_same (neon_quad (rs), 1, -1);
12340 do_neon_fcmp_absolute_inv (void)
12342 neon_exchange_operands ();
12343 do_neon_fcmp_absolute ();
12347 do_neon_step (void)
12349 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
12350 neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY);
12351 neon_three_same (neon_quad (rs), 0, -1);
12355 do_neon_abs_neg (void)
12357 enum neon_shape rs;
12358 struct neon_type_el et;
12360 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg) == SUCCESS)
12363 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
12366 rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
12367 et = neon_check_type (2, rs, N_EQK, N_S8 | N_S16 | N_S32 | N_F32 | N_KEY);
12369 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
12370 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
12371 inst.instruction |= LOW4 (inst.operands[1].reg);
12372 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
12373 inst.instruction |= neon_quad (rs) << 6;
12374 inst.instruction |= (et.type == NT_float) << 10;
12375 inst.instruction |= neon_logbits (et.size) << 18;
12377 inst.instruction = neon_dp_fixup (inst.instruction);
12383 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
12384 struct neon_type_el et = neon_check_type (2, rs,
12385 N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
12386 int imm = inst.operands[2].imm;
12387 constraint (imm < 0 || (unsigned)imm >= et.size,
12388 _("immediate out of range for insert"));
12389 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
12395 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
12396 struct neon_type_el et = neon_check_type (2, rs,
12397 N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
12398 int imm = inst.operands[2].imm;
12399 constraint (imm < 1 || (unsigned)imm > et.size,
12400 _("immediate out of range for insert"));
12401 neon_imm_shift (FALSE, 0, neon_quad (rs), et, et.size - imm);
12405 do_neon_qshlu_imm (void)
12407 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
12408 struct neon_type_el et = neon_check_type (2, rs,
12409 N_EQK | N_UNS, N_S8 | N_S16 | N_S32 | N_S64 | N_KEY);
12410 int imm = inst.operands[2].imm;
12411 constraint (imm < 0 || (unsigned)imm >= et.size,
12412 _("immediate out of range for shift"));
12413 /* Only encodes the 'U present' variant of the instruction.
12414 In this case, signed types have OP (bit 8) set to 0.
12415 Unsigned types have OP set to 1. */
12416 inst.instruction |= (et.type == NT_unsigned) << 8;
12417 /* The rest of the bits are the same as other immediate shifts. */
12418 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
12422 do_neon_qmovn (void)
12424 struct neon_type_el et = neon_check_type (2, NS_DQ,
12425 N_EQK | N_HLF, N_SU_16_64 | N_KEY);
12426 /* Saturating move where operands can be signed or unsigned, and the
12427 destination has the same signedness. */
12428 inst.instruction = NEON_ENC_INTEGER (inst.instruction);
12429 if (et.type == NT_unsigned)
12430 inst.instruction |= 0xc0;
12432 inst.instruction |= 0x80;
12433 neon_two_same (0, 1, et.size / 2);
12437 do_neon_qmovun (void)
12439 struct neon_type_el et = neon_check_type (2, NS_DQ,
12440 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY);
12441 /* Saturating move with unsigned results. Operands must be signed. */
12442 inst.instruction = NEON_ENC_INTEGER (inst.instruction);
12443 neon_two_same (0, 1, et.size / 2);
12447 do_neon_rshift_sat_narrow (void)
12449 /* FIXME: Types for narrowing. If operands are signed, results can be signed
12450 or unsigned. If operands are unsigned, results must also be unsigned. */
12451 struct neon_type_el et = neon_check_type (2, NS_DQI,
12452 N_EQK | N_HLF, N_SU_16_64 | N_KEY);
12453 int imm = inst.operands[2].imm;
12454 /* This gets the bounds check, size encoding and immediate bits calculation
12458 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
12459 VQMOVN.I<size> <Dd>, <Qm>. */
12462 inst.operands[2].present = 0;
12463 inst.instruction = N_MNEM_vqmovn;
12468 constraint (imm < 1 || (unsigned)imm > et.size,
12469 _("immediate out of range"));
12470 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, et.size - imm);
12474 do_neon_rshift_sat_narrow_u (void)
12476 /* FIXME: Types for narrowing. If operands are signed, results can be signed
12477 or unsigned. If operands are unsigned, results must also be unsigned. */
12478 struct neon_type_el et = neon_check_type (2, NS_DQI,
12479 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY);
12480 int imm = inst.operands[2].imm;
12481 /* This gets the bounds check, size encoding and immediate bits calculation
12485 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
12486 VQMOVUN.I<size> <Dd>, <Qm>. */
12489 inst.operands[2].present = 0;
12490 inst.instruction = N_MNEM_vqmovun;
12495 constraint (imm < 1 || (unsigned)imm > et.size,
12496 _("immediate out of range"));
12497 /* FIXME: The manual is kind of unclear about what value U should have in
12498 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
12500 neon_imm_shift (TRUE, 1, 0, et, et.size - imm);
12504 do_neon_movn (void)
12506 struct neon_type_el et = neon_check_type (2, NS_DQ,
12507 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY);
12508 inst.instruction = NEON_ENC_INTEGER (inst.instruction);
12509 neon_two_same (0, 1, et.size / 2);
12513 do_neon_rshift_narrow (void)
12515 struct neon_type_el et = neon_check_type (2, NS_DQI,
12516 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY);
12517 int imm = inst.operands[2].imm;
12518 /* This gets the bounds check, size encoding and immediate bits calculation
12522 /* If immediate is zero then we are a pseudo-instruction for
12523 VMOVN.I<size> <Dd>, <Qm> */
12526 inst.operands[2].present = 0;
12527 inst.instruction = N_MNEM_vmovn;
12532 constraint (imm < 1 || (unsigned)imm > et.size,
12533 _("immediate out of range for narrowing operation"));
12534 neon_imm_shift (FALSE, 0, 0, et, et.size - imm);
12538 do_neon_shll (void)
12540 /* FIXME: Type checking when lengthening. */
12541 struct neon_type_el et = neon_check_type (2, NS_QDI,
12542 N_EQK | N_DBL, N_I8 | N_I16 | N_I32 | N_KEY);
12543 unsigned imm = inst.operands[2].imm;
12545 if (imm == et.size)
12547 /* Maximum shift variant. */
12548 inst.instruction = NEON_ENC_INTEGER (inst.instruction);
12549 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
12550 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
12551 inst.instruction |= LOW4 (inst.operands[1].reg);
12552 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
12553 inst.instruction |= neon_logbits (et.size) << 18;
12555 inst.instruction = neon_dp_fixup (inst.instruction);
12559 /* A more-specific type check for non-max versions. */
12560 et = neon_check_type (2, NS_QDI,
12561 N_EQK | N_DBL, N_SU_32 | N_KEY);
12562 inst.instruction = NEON_ENC_IMMED (inst.instruction);
12563 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, imm);
12567 /* Check the various types for the VCVT instruction, and return which version
12568 the current instruction is. */
12571 neon_cvt_flavour (enum neon_shape rs)
12573 #define CVT_VAR(C,X,Y) \
12574 et = neon_check_type (2, rs, whole_reg | (X), whole_reg | (Y)); \
12575 if (et.type != NT_invtype) \
12577 inst.error = NULL; \
12580 struct neon_type_el et;
12581 unsigned whole_reg = (rs == NS_FFI || rs == NS_FD || rs == NS_DF
12582 || rs == NS_FF) ? N_VFP : 0;
12583 /* The instruction versions which take an immediate take one register
12584 argument, which is extended to the width of the full register. Thus the
12585 "source" and "destination" registers must have the same width. Hack that
12586 here by making the size equal to the key (wider, in this case) operand. */
12587 unsigned key = (rs == NS_QQI || rs == NS_DDI || rs == NS_FFI) ? N_KEY : 0;
12589 CVT_VAR (0, N_S32, N_F32);
12590 CVT_VAR (1, N_U32, N_F32);
12591 CVT_VAR (2, N_F32, N_S32);
12592 CVT_VAR (3, N_F32, N_U32);
12596 /* VFP instructions. */
12597 CVT_VAR (4, N_F32, N_F64);
12598 CVT_VAR (5, N_F64, N_F32);
12599 CVT_VAR (6, N_S32, N_F64 | key);
12600 CVT_VAR (7, N_U32, N_F64 | key);
12601 CVT_VAR (8, N_F64 | key, N_S32);
12602 CVT_VAR (9, N_F64 | key, N_U32);
12603 /* VFP instructions with bitshift. */
12604 CVT_VAR (10, N_F32 | key, N_S16);
12605 CVT_VAR (11, N_F32 | key, N_U16);
12606 CVT_VAR (12, N_F64 | key, N_S16);
12607 CVT_VAR (13, N_F64 | key, N_U16);
12608 CVT_VAR (14, N_S16, N_F32 | key);
12609 CVT_VAR (15, N_U16, N_F32 | key);
12610 CVT_VAR (16, N_S16, N_F64 | key);
12611 CVT_VAR (17, N_U16, N_F64 | key);
12617 /* Neon-syntax VFP conversions. */
12620 do_vfp_nsyn_cvt (enum neon_shape rs, int flavour)
12622 const char *opname = 0;
12624 if (rs == NS_DDI || rs == NS_QQI || rs == NS_FFI)
12626 /* Conversions with immediate bitshift. */
12627 const char *enc[] =
12649 if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc))
12651 opname = enc[flavour];
12652 constraint (inst.operands[0].reg != inst.operands[1].reg,
12653 _("operands 0 and 1 must be the same register"));
12654 inst.operands[1] = inst.operands[2];
12655 memset (&inst.operands[2], '\0', sizeof (inst.operands[2]));
12660 /* Conversions without bitshift. */
12661 const char *enc[] =
12675 if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc))
12676 opname = enc[flavour];
12680 do_vfp_nsyn_opcode (opname);
12684 do_vfp_nsyn_cvtz (void)
12686 enum neon_shape rs = neon_select_shape (NS_FF, NS_FD, NS_NULL);
12687 int flavour = neon_cvt_flavour (rs);
12688 const char *enc[] =
12700 if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc) && enc[flavour])
12701 do_vfp_nsyn_opcode (enc[flavour]);
12707 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_FFI, NS_DD, NS_QQ,
12708 NS_FD, NS_DF, NS_FF, NS_NULL);
12709 int flavour = neon_cvt_flavour (rs);
12711 /* VFP rather than Neon conversions. */
12714 do_vfp_nsyn_cvt (rs, flavour);
12723 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
12726 /* Fixed-point conversion with #0 immediate is encoded as an
12727 integer conversion. */
12728 if (inst.operands[2].present && inst.operands[2].imm == 0)
12730 unsigned immbits = 32 - inst.operands[2].imm;
12731 unsigned enctab[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
12732 inst.instruction = NEON_ENC_IMMED (inst.instruction);
12734 inst.instruction |= enctab[flavour];
12735 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
12736 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
12737 inst.instruction |= LOW4 (inst.operands[1].reg);
12738 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
12739 inst.instruction |= neon_quad (rs) << 6;
12740 inst.instruction |= 1 << 21;
12741 inst.instruction |= immbits << 16;
12743 inst.instruction = neon_dp_fixup (inst.instruction);
12751 unsigned enctab[] = { 0x100, 0x180, 0x0, 0x080 };
12753 inst.instruction = NEON_ENC_INTEGER (inst.instruction);
12755 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
12759 inst.instruction |= enctab[flavour];
12761 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
12762 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
12763 inst.instruction |= LOW4 (inst.operands[1].reg);
12764 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
12765 inst.instruction |= neon_quad (rs) << 6;
12766 inst.instruction |= 2 << 18;
12768 inst.instruction = neon_dp_fixup (inst.instruction);
12773 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
12774 do_vfp_nsyn_cvt (rs, flavour);
12779 neon_move_immediate (void)
12781 enum neon_shape rs = neon_select_shape (NS_DI, NS_QI, NS_NULL);
12782 struct neon_type_el et = neon_check_type (2, rs,
12783 N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK);
12784 unsigned immlo, immhi = 0, immbits;
12785 int op, cmode, float_p;
12787 constraint (et.type == NT_invtype,
12788 _("operand size must be specified for immediate VMOV"));
12790 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
12791 op = (inst.instruction & (1 << 5)) != 0;
12793 immlo = inst.operands[1].imm;
12794 if (inst.operands[1].regisimm)
12795 immhi = inst.operands[1].reg;
12797 constraint (et.size < 32 && (immlo & ~((1 << et.size) - 1)) != 0,
12798 _("immediate has bits set outside the operand size"));
12800 float_p = inst.operands[1].immisfloat;
12802 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, &op,
12803 et.size, et.type)) == FAIL)
12805 /* Invert relevant bits only. */
12806 neon_invert_size (&immlo, &immhi, et.size);
12807 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
12808 with one or the other; those cases are caught by
12809 neon_cmode_for_move_imm. */
12811 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits,
12812 &op, et.size, et.type)) == FAIL)
12814 first_error (_("immediate out of range"));
12819 inst.instruction &= ~(1 << 5);
12820 inst.instruction |= op << 5;
12822 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
12823 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
12824 inst.instruction |= neon_quad (rs) << 6;
12825 inst.instruction |= cmode << 8;
12827 neon_write_immbits (immbits);
12833 if (inst.operands[1].isreg)
12835 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
12837 inst.instruction = NEON_ENC_INTEGER (inst.instruction);
12838 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
12839 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
12840 inst.instruction |= LOW4 (inst.operands[1].reg);
12841 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
12842 inst.instruction |= neon_quad (rs) << 6;
12846 inst.instruction = NEON_ENC_IMMED (inst.instruction);
12847 neon_move_immediate ();
12850 inst.instruction = neon_dp_fixup (inst.instruction);
12853 /* Encode instructions of form:
12855 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
12856 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm |
12861 neon_mixed_length (struct neon_type_el et, unsigned size)
12863 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
12864 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
12865 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
12866 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
12867 inst.instruction |= LOW4 (inst.operands[2].reg);
12868 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
12869 inst.instruction |= (et.type == NT_unsigned) << 24;
12870 inst.instruction |= neon_logbits (size) << 20;
12872 inst.instruction = neon_dp_fixup (inst.instruction);
12876 do_neon_dyadic_long (void)
12878 /* FIXME: Type checking for lengthening op. */
12879 struct neon_type_el et = neon_check_type (3, NS_QDD,
12880 N_EQK | N_DBL, N_EQK, N_SU_32 | N_KEY);
12881 neon_mixed_length (et, et.size);
12885 do_neon_abal (void)
12887 struct neon_type_el et = neon_check_type (3, NS_QDD,
12888 N_EQK | N_INT | N_DBL, N_EQK, N_SU_32 | N_KEY);
12889 neon_mixed_length (et, et.size);
12893 neon_mac_reg_scalar_long (unsigned regtypes, unsigned scalartypes)
12895 if (inst.operands[2].isscalar)
12897 struct neon_type_el et = neon_check_type (3, NS_QDS,
12898 N_EQK | N_DBL, N_EQK, regtypes | N_KEY);
12899 inst.instruction = NEON_ENC_SCALAR (inst.instruction);
12900 neon_mul_mac (et, et.type == NT_unsigned);
12904 struct neon_type_el et = neon_check_type (3, NS_QDD,
12905 N_EQK | N_DBL, N_EQK, scalartypes | N_KEY);
12906 inst.instruction = NEON_ENC_INTEGER (inst.instruction);
12907 neon_mixed_length (et, et.size);
12912 do_neon_mac_maybe_scalar_long (void)
12914 neon_mac_reg_scalar_long (N_S16 | N_S32 | N_U16 | N_U32, N_SU_32);
12918 do_neon_dyadic_wide (void)
12920 struct neon_type_el et = neon_check_type (3, NS_QQD,
12921 N_EQK | N_DBL, N_EQK | N_DBL, N_SU_32 | N_KEY);
12922 neon_mixed_length (et, et.size);
12926 do_neon_dyadic_narrow (void)
12928 struct neon_type_el et = neon_check_type (3, NS_QDD,
12929 N_EQK | N_DBL, N_EQK, N_I16 | N_I32 | N_I64 | N_KEY);
12930 /* Operand sign is unimportant, and the U bit is part of the opcode,
12931 so force the operand type to integer. */
12932 et.type = NT_integer;
12933 neon_mixed_length (et, et.size / 2);
12937 do_neon_mul_sat_scalar_long (void)
12939 neon_mac_reg_scalar_long (N_S16 | N_S32, N_S16 | N_S32);
12943 do_neon_vmull (void)
12945 if (inst.operands[2].isscalar)
12946 do_neon_mac_maybe_scalar_long ();
12949 struct neon_type_el et = neon_check_type (3, NS_QDD,
12950 N_EQK | N_DBL, N_EQK, N_SU_32 | N_P8 | N_KEY);
12951 if (et.type == NT_poly)
12952 inst.instruction = NEON_ENC_POLY (inst.instruction);
12954 inst.instruction = NEON_ENC_INTEGER (inst.instruction);
12955 /* For polynomial encoding, size field must be 0b00 and the U bit must be
12956 zero. Should be OK as-is. */
12957 neon_mixed_length (et, et.size);
12964 enum neon_shape rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL);
12965 struct neon_type_el et = neon_check_type (3, rs,
12966 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
12967 unsigned imm = (inst.operands[3].imm * et.size) / 8;
12968 constraint (imm >= (neon_quad (rs) ? 16 : 8), _("shift out of range"));
12969 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
12970 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
12971 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
12972 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
12973 inst.instruction |= LOW4 (inst.operands[2].reg);
12974 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
12975 inst.instruction |= neon_quad (rs) << 6;
12976 inst.instruction |= imm << 8;
12978 inst.instruction = neon_dp_fixup (inst.instruction);
12984 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
12985 struct neon_type_el et = neon_check_type (2, rs,
12986 N_EQK, N_8 | N_16 | N_32 | N_KEY);
12987 unsigned op = (inst.instruction >> 7) & 3;
12988 /* N (width of reversed regions) is encoded as part of the bitmask. We
12989 extract it here to check the elements to be reversed are smaller.
12990 Otherwise we'd get a reserved instruction. */
12991 unsigned elsize = (op == 2) ? 16 : (op == 1) ? 32 : (op == 0) ? 64 : 0;
12992 assert (elsize != 0);
12993 constraint (et.size >= elsize,
12994 _("elements must be smaller than reversal region"));
12995 neon_two_same (neon_quad (rs), 1, et.size);
13001 if (inst.operands[1].isscalar)
13003 enum neon_shape rs = neon_select_shape (NS_DS, NS_QS, NS_NULL);
13004 struct neon_type_el et = neon_check_type (2, rs,
13005 N_EQK, N_8 | N_16 | N_32 | N_KEY);
13006 unsigned sizebits = et.size >> 3;
13007 unsigned dm = NEON_SCALAR_REG (inst.operands[1].reg);
13008 int logsize = neon_logbits (et.size);
13009 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg) << logsize;
13011 if (vfp_or_neon_is_neon (NEON_CHECK_CC) == FAIL)
13014 inst.instruction = NEON_ENC_SCALAR (inst.instruction);
13015 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13016 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13017 inst.instruction |= LOW4 (dm);
13018 inst.instruction |= HI1 (dm) << 5;
13019 inst.instruction |= neon_quad (rs) << 6;
13020 inst.instruction |= x << 17;
13021 inst.instruction |= sizebits << 16;
13023 inst.instruction = neon_dp_fixup (inst.instruction);
13027 enum neon_shape rs = neon_select_shape (NS_DR, NS_QR, NS_NULL);
13028 struct neon_type_el et = neon_check_type (2, rs,
13029 N_8 | N_16 | N_32 | N_KEY, N_EQK);
13030 /* Duplicate ARM register to lanes of vector. */
13031 inst.instruction = NEON_ENC_ARMREG (inst.instruction);
13034 case 8: inst.instruction |= 0x400000; break;
13035 case 16: inst.instruction |= 0x000020; break;
13036 case 32: inst.instruction |= 0x000000; break;
13039 inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
13040 inst.instruction |= LOW4 (inst.operands[0].reg) << 16;
13041 inst.instruction |= HI1 (inst.operands[0].reg) << 7;
13042 inst.instruction |= neon_quad (rs) << 21;
13043 /* The encoding for this instruction is identical for the ARM and Thumb
13044 variants, except for the condition field. */
13045 do_vfp_cond_or_thumb ();
13049 /* VMOV has particularly many variations. It can be one of:
13050 0. VMOV<c><q> <Qd>, <Qm>
13051 1. VMOV<c><q> <Dd>, <Dm>
13052 (Register operations, which are VORR with Rm = Rn.)
13053 2. VMOV<c><q>.<dt> <Qd>, #<imm>
13054 3. VMOV<c><q>.<dt> <Dd>, #<imm>
13056 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
13057 (ARM register to scalar.)
13058 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
13059 (Two ARM registers to vector.)
13060 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
13061 (Scalar to ARM register.)
13062 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
13063 (Vector to two ARM registers.)
13064 8. VMOV.F32 <Sd>, <Sm>
13065 9. VMOV.F64 <Dd>, <Dm>
13066 (VFP register moves.)
13067 10. VMOV.F32 <Sd>, #imm
13068 11. VMOV.F64 <Dd>, #imm
13069 (VFP float immediate load.)
13070 12. VMOV <Rd>, <Sm>
13071 (VFP single to ARM reg.)
13072 13. VMOV <Sd>, <Rm>
13073 (ARM reg to VFP single.)
13074 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
13075 (Two ARM regs to two VFP singles.)
13076 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
13077 (Two VFP singles to two ARM regs.)
13079 These cases can be disambiguated using neon_select_shape, except cases 1/9
13080 and 3/11 which depend on the operand type too.
13082 All the encoded bits are hardcoded by this function.
13084 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
13085 Cases 5, 7 may be used with VFPv2 and above.
13087 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
13088 can specify a type where it doesn't make sense to, and is ignored).
13094 enum neon_shape rs = neon_select_shape (NS_RRFF, NS_FFRR, NS_DRR, NS_RRD,
13095 NS_QQ, NS_DD, NS_QI, NS_DI, NS_SR, NS_RS, NS_FF, NS_FI, NS_RF, NS_FR,
13097 struct neon_type_el et;
13098 const char *ldconst = 0;
13102 case NS_DD: /* case 1/9. */
13103 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY);
13104 /* It is not an error here if no type is given. */
13106 if (et.type == NT_float && et.size == 64)
13108 do_vfp_nsyn_opcode ("fcpyd");
13111 /* fall through. */
13113 case NS_QQ: /* case 0/1. */
13115 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
13117 /* The architecture manual I have doesn't explicitly state which
13118 value the U bit should have for register->register moves, but
13119 the equivalent VORR instruction has U = 0, so do that. */
13120 inst.instruction = 0x0200110;
13121 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13122 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13123 inst.instruction |= LOW4 (inst.operands[1].reg);
13124 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
13125 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
13126 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
13127 inst.instruction |= neon_quad (rs) << 6;
13129 inst.instruction = neon_dp_fixup (inst.instruction);
13133 case NS_DI: /* case 3/11. */
13134 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY);
13136 if (et.type == NT_float && et.size == 64)
13138 /* case 11 (fconstd). */
13139 ldconst = "fconstd";
13140 goto encode_fconstd;
13142 /* fall through. */
13144 case NS_QI: /* case 2/3. */
13145 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
13147 inst.instruction = 0x0800010;
13148 neon_move_immediate ();
13149 inst.instruction = neon_dp_fixup (inst.instruction);
13152 case NS_SR: /* case 4. */
13154 unsigned bcdebits = 0;
13155 struct neon_type_el et = neon_check_type (2, NS_NULL,
13156 N_8 | N_16 | N_32 | N_KEY, N_EQK);
13157 int logsize = neon_logbits (et.size);
13158 unsigned dn = NEON_SCALAR_REG (inst.operands[0].reg);
13159 unsigned x = NEON_SCALAR_INDEX (inst.operands[0].reg);
13161 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1),
13163 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)
13164 && et.size != 32, _(BAD_FPU));
13165 constraint (et.type == NT_invtype, _("bad type for scalar"));
13166 constraint (x >= 64 / et.size, _("scalar index out of range"));
13170 case 8: bcdebits = 0x8; break;
13171 case 16: bcdebits = 0x1; break;
13172 case 32: bcdebits = 0x0; break;
13176 bcdebits |= x << logsize;
13178 inst.instruction = 0xe000b10;
13179 do_vfp_cond_or_thumb ();
13180 inst.instruction |= LOW4 (dn) << 16;
13181 inst.instruction |= HI1 (dn) << 7;
13182 inst.instruction |= inst.operands[1].reg << 12;
13183 inst.instruction |= (bcdebits & 3) << 5;
13184 inst.instruction |= (bcdebits >> 2) << 21;
13188 case NS_DRR: /* case 5 (fmdrr). */
13189 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2),
13192 inst.instruction = 0xc400b10;
13193 do_vfp_cond_or_thumb ();
13194 inst.instruction |= LOW4 (inst.operands[0].reg);
13195 inst.instruction |= HI1 (inst.operands[0].reg) << 5;
13196 inst.instruction |= inst.operands[1].reg << 12;
13197 inst.instruction |= inst.operands[2].reg << 16;
13200 case NS_RS: /* case 6. */
13202 struct neon_type_el et = neon_check_type (2, NS_NULL,
13203 N_EQK, N_S8 | N_S16 | N_U8 | N_U16 | N_32 | N_KEY);
13204 unsigned logsize = neon_logbits (et.size);
13205 unsigned dn = NEON_SCALAR_REG (inst.operands[1].reg);
13206 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg);
13207 unsigned abcdebits = 0;
13209 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1),
13211 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)
13212 && et.size != 32, _(BAD_FPU));
13213 constraint (et.type == NT_invtype, _("bad type for scalar"));
13214 constraint (x >= 64 / et.size, _("scalar index out of range"));
13218 case 8: abcdebits = (et.type == NT_signed) ? 0x08 : 0x18; break;
13219 case 16: abcdebits = (et.type == NT_signed) ? 0x01 : 0x11; break;
13220 case 32: abcdebits = 0x00; break;
13224 abcdebits |= x << logsize;
13225 inst.instruction = 0xe100b10;
13226 do_vfp_cond_or_thumb ();
13227 inst.instruction |= LOW4 (dn) << 16;
13228 inst.instruction |= HI1 (dn) << 7;
13229 inst.instruction |= inst.operands[0].reg << 12;
13230 inst.instruction |= (abcdebits & 3) << 5;
13231 inst.instruction |= (abcdebits >> 2) << 21;
13235 case NS_RRD: /* case 7 (fmrrd). */
13236 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2),
13239 inst.instruction = 0xc500b10;
13240 do_vfp_cond_or_thumb ();
13241 inst.instruction |= inst.operands[0].reg << 12;
13242 inst.instruction |= inst.operands[1].reg << 16;
13243 inst.instruction |= LOW4 (inst.operands[2].reg);
13244 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
13247 case NS_FF: /* case 8 (fcpys). */
13248 do_vfp_nsyn_opcode ("fcpys");
13251 case NS_FI: /* case 10 (fconsts). */
13252 ldconst = "fconsts";
13254 if (is_quarter_float (inst.operands[1].imm))
13256 inst.operands[1].imm = neon_qfloat_bits (inst.operands[1].imm);
13257 do_vfp_nsyn_opcode (ldconst);
13260 first_error (_("immediate out of range"));
13263 case NS_RF: /* case 12 (fmrs). */
13264 do_vfp_nsyn_opcode ("fmrs");
13267 case NS_FR: /* case 13 (fmsr). */
13268 do_vfp_nsyn_opcode ("fmsr");
13271 /* The encoders for the fmrrs and fmsrr instructions expect three operands
13272 (one of which is a list), but we have parsed four. Do some fiddling to
13273 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
13275 case NS_RRFF: /* case 14 (fmrrs). */
13276 constraint (inst.operands[3].reg != inst.operands[2].reg + 1,
13277 _("VFP registers must be adjacent"));
13278 inst.operands[2].imm = 2;
13279 memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
13280 do_vfp_nsyn_opcode ("fmrrs");
13283 case NS_FFRR: /* case 15 (fmsrr). */
13284 constraint (inst.operands[1].reg != inst.operands[0].reg + 1,
13285 _("VFP registers must be adjacent"));
13286 inst.operands[1] = inst.operands[2];
13287 inst.operands[2] = inst.operands[3];
13288 inst.operands[0].imm = 2;
13289 memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
13290 do_vfp_nsyn_opcode ("fmsrr");
13299 do_neon_rshift_round_imm (void)
13301 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
13302 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
13303 int imm = inst.operands[2].imm;
13305 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
13308 inst.operands[2].present = 0;
13313 constraint (imm < 1 || (unsigned)imm > et.size,
13314 _("immediate out of range for shift"));
13315 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et,
13320 do_neon_movl (void)
13322 struct neon_type_el et = neon_check_type (2, NS_QD,
13323 N_EQK | N_DBL, N_SU_32 | N_KEY);
13324 unsigned sizebits = et.size >> 3;
13325 inst.instruction |= sizebits << 19;
13326 neon_two_same (0, et.type == NT_unsigned, -1);
13332 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
13333 struct neon_type_el et = neon_check_type (2, rs,
13334 N_EQK, N_8 | N_16 | N_32 | N_KEY);
13335 inst.instruction = NEON_ENC_INTEGER (inst.instruction);
13336 neon_two_same (neon_quad (rs), 1, et.size);
13340 do_neon_zip_uzp (void)
13342 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
13343 struct neon_type_el et = neon_check_type (2, rs,
13344 N_EQK, N_8 | N_16 | N_32 | N_KEY);
13345 if (rs == NS_DD && et.size == 32)
13347 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
13348 inst.instruction = N_MNEM_vtrn;
13352 neon_two_same (neon_quad (rs), 1, et.size);
13356 do_neon_sat_abs_neg (void)
13358 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
13359 struct neon_type_el et = neon_check_type (2, rs,
13360 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
13361 neon_two_same (neon_quad (rs), 1, et.size);
13365 do_neon_pair_long (void)
13367 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
13368 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_32 | N_KEY);
13369 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
13370 inst.instruction |= (et.type == NT_unsigned) << 7;
13371 neon_two_same (neon_quad (rs), 1, et.size);
13375 do_neon_recip_est (void)
13377 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
13378 struct neon_type_el et = neon_check_type (2, rs,
13379 N_EQK | N_FLT, N_F32 | N_U32 | N_KEY);
13380 inst.instruction |= (et.type == NT_float) << 8;
13381 neon_two_same (neon_quad (rs), 1, et.size);
13387 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
13388 struct neon_type_el et = neon_check_type (2, rs,
13389 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
13390 neon_two_same (neon_quad (rs), 1, et.size);
13396 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
13397 struct neon_type_el et = neon_check_type (2, rs,
13398 N_EQK, N_I8 | N_I16 | N_I32 | N_KEY);
13399 neon_two_same (neon_quad (rs), 1, et.size);
13405 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
13406 struct neon_type_el et = neon_check_type (2, rs,
13407 N_EQK | N_INT, N_8 | N_KEY);
13408 neon_two_same (neon_quad (rs), 1, et.size);
13414 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
13415 neon_two_same (neon_quad (rs), 1, -1);
13419 do_neon_tbl_tbx (void)
13421 unsigned listlenbits;
13422 neon_check_type (3, NS_DLD, N_EQK, N_EQK, N_8 | N_KEY);
13424 if (inst.operands[1].imm < 1 || inst.operands[1].imm > 4)
13426 first_error (_("bad list length for table lookup"));
13430 listlenbits = inst.operands[1].imm - 1;
13431 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13432 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13433 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
13434 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
13435 inst.instruction |= LOW4 (inst.operands[2].reg);
13436 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
13437 inst.instruction |= listlenbits << 8;
13439 inst.instruction = neon_dp_fixup (inst.instruction);
13443 do_neon_ldm_stm (void)
13445 /* P, U and L bits are part of bitmask. */
13446 int is_dbmode = (inst.instruction & (1 << 24)) != 0;
13447 unsigned offsetbits = inst.operands[1].imm * 2;
13449 if (inst.operands[1].issingle)
13451 do_vfp_nsyn_ldm_stm (is_dbmode);
13455 constraint (is_dbmode && !inst.operands[0].writeback,
13456 _("writeback (!) must be used for VLDMDB and VSTMDB"));
13458 constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16,
13459 _("register list must contain at least 1 and at most 16 "
13462 inst.instruction |= inst.operands[0].reg << 16;
13463 inst.instruction |= inst.operands[0].writeback << 21;
13464 inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
13465 inst.instruction |= HI1 (inst.operands[1].reg) << 22;
13467 inst.instruction |= offsetbits;
13469 do_vfp_cond_or_thumb ();
13473 do_neon_ldr_str (void)
13475 int is_ldr = (inst.instruction & (1 << 20)) != 0;
13477 if (inst.operands[0].issingle)
13480 do_vfp_nsyn_opcode ("flds");
13482 do_vfp_nsyn_opcode ("fsts");
13487 do_vfp_nsyn_opcode ("fldd");
13489 do_vfp_nsyn_opcode ("fstd");
13493 /* "interleave" version also handles non-interleaving register VLD1/VST1
13497 do_neon_ld_st_interleave (void)
13499 struct neon_type_el et = neon_check_type (1, NS_NULL,
13500 N_8 | N_16 | N_32 | N_64);
13501 unsigned alignbits = 0;
13503 /* The bits in this table go:
13504 0: register stride of one (0) or two (1)
13505 1,2: register list length, minus one (1, 2, 3, 4).
13506 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
13507 We use -1 for invalid entries. */
13508 const int typetable[] =
13510 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
13511 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
13512 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
13513 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
13517 if (et.type == NT_invtype)
13520 if (inst.operands[1].immisalign)
13521 switch (inst.operands[1].imm >> 8)
13523 case 64: alignbits = 1; break;
13525 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) == 3)
13526 goto bad_alignment;
13530 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) == 3)
13531 goto bad_alignment;
13536 first_error (_("bad alignment"));
13540 inst.instruction |= alignbits << 4;
13541 inst.instruction |= neon_logbits (et.size) << 6;
13543 /* Bits [4:6] of the immediate in a list specifier encode register stride
13544 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
13545 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
13546 up the right value for "type" in a table based on this value and the given
13547 list style, then stick it back. */
13548 idx = ((inst.operands[0].imm >> 4) & 7)
13549 | (((inst.instruction >> 8) & 3) << 3);
13551 typebits = typetable[idx];
13553 constraint (typebits == -1, _("bad list type for instruction"));
13555 inst.instruction &= ~0xf00;
13556 inst.instruction |= typebits << 8;
13559 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
13560 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
13561 otherwise. The variable arguments are a list of pairs of legal (size, align)
13562 values, terminated with -1. */
13565 neon_alignment_bit (int size, int align, int *do_align, ...)
13568 int result = FAIL, thissize, thisalign;
13570 if (!inst.operands[1].immisalign)
13576 va_start (ap, do_align);
13580 thissize = va_arg (ap, int);
13581 if (thissize == -1)
13583 thisalign = va_arg (ap, int);
13585 if (size == thissize && align == thisalign)
13588 while (result != SUCCESS);
13592 if (result == SUCCESS)
13595 first_error (_("unsupported alignment for instruction"));
13601 do_neon_ld_st_lane (void)
13603 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32);
13604 int align_good, do_align = 0;
13605 int logsize = neon_logbits (et.size);
13606 int align = inst.operands[1].imm >> 8;
13607 int n = (inst.instruction >> 8) & 3;
13608 int max_el = 64 / et.size;
13610 if (et.type == NT_invtype)
13613 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != n + 1,
13614 _("bad list length"));
13615 constraint (NEON_LANE (inst.operands[0].imm) >= max_el,
13616 _("scalar index out of range"));
13617 constraint (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2
13619 _("stride of 2 unavailable when element size is 8"));
13623 case 0: /* VLD1 / VST1. */
13624 align_good = neon_alignment_bit (et.size, align, &do_align, 16, 16,
13626 if (align_good == FAIL)
13630 unsigned alignbits = 0;
13633 case 16: alignbits = 0x1; break;
13634 case 32: alignbits = 0x3; break;
13637 inst.instruction |= alignbits << 4;
13641 case 1: /* VLD2 / VST2. */
13642 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 16, 16, 32,
13644 if (align_good == FAIL)
13647 inst.instruction |= 1 << 4;
13650 case 2: /* VLD3 / VST3. */
13651 constraint (inst.operands[1].immisalign,
13652 _("can't use alignment with this instruction"));
13655 case 3: /* VLD4 / VST4. */
13656 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32,
13657 16, 64, 32, 64, 32, 128, -1);
13658 if (align_good == FAIL)
13662 unsigned alignbits = 0;
13665 case 8: alignbits = 0x1; break;
13666 case 16: alignbits = 0x1; break;
13667 case 32: alignbits = (align == 64) ? 0x1 : 0x2; break;
13670 inst.instruction |= alignbits << 4;
13677 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
13678 if (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2)
13679 inst.instruction |= 1 << (4 + logsize);
13681 inst.instruction |= NEON_LANE (inst.operands[0].imm) << (logsize + 5);
13682 inst.instruction |= logsize << 10;
13685 /* Encode single n-element structure to all lanes VLD<n> instructions. */
13688 do_neon_ld_dup (void)
13690 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32);
13691 int align_good, do_align = 0;
13693 if (et.type == NT_invtype)
13696 switch ((inst.instruction >> 8) & 3)
13698 case 0: /* VLD1. */
13699 assert (NEON_REG_STRIDE (inst.operands[0].imm) != 2);
13700 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
13701 &do_align, 16, 16, 32, 32, -1);
13702 if (align_good == FAIL)
13704 switch (NEON_REGLIST_LENGTH (inst.operands[0].imm))
13707 case 2: inst.instruction |= 1 << 5; break;
13708 default: first_error (_("bad list length")); return;
13710 inst.instruction |= neon_logbits (et.size) << 6;
13713 case 1: /* VLD2. */
13714 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
13715 &do_align, 8, 16, 16, 32, 32, 64, -1);
13716 if (align_good == FAIL)
13718 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2,
13719 _("bad list length"));
13720 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
13721 inst.instruction |= 1 << 5;
13722 inst.instruction |= neon_logbits (et.size) << 6;
13725 case 2: /* VLD3. */
13726 constraint (inst.operands[1].immisalign,
13727 _("can't use alignment with this instruction"));
13728 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 3,
13729 _("bad list length"));
13730 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
13731 inst.instruction |= 1 << 5;
13732 inst.instruction |= neon_logbits (et.size) << 6;
13735 case 3: /* VLD4. */
13737 int align = inst.operands[1].imm >> 8;
13738 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32,
13739 16, 64, 32, 64, 32, 128, -1);
13740 if (align_good == FAIL)
13742 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4,
13743 _("bad list length"));
13744 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
13745 inst.instruction |= 1 << 5;
13746 if (et.size == 32 && align == 128)
13747 inst.instruction |= 0x3 << 6;
13749 inst.instruction |= neon_logbits (et.size) << 6;
13756 inst.instruction |= do_align << 4;
13759 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
13760 apart from bits [11:4]. */
13763 do_neon_ldx_stx (void)
13765 switch (NEON_LANE (inst.operands[0].imm))
13767 case NEON_INTERLEAVE_LANES:
13768 inst.instruction = NEON_ENC_INTERLV (inst.instruction);
13769 do_neon_ld_st_interleave ();
13772 case NEON_ALL_LANES:
13773 inst.instruction = NEON_ENC_DUP (inst.instruction);
13778 inst.instruction = NEON_ENC_LANE (inst.instruction);
13779 do_neon_ld_st_lane ();
13782 /* L bit comes from bit mask. */
13783 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13784 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13785 inst.instruction |= inst.operands[1].reg << 16;
13787 if (inst.operands[1].postind)
13789 int postreg = inst.operands[1].imm & 0xf;
13790 constraint (!inst.operands[1].immisreg,
13791 _("post-index must be a register"));
13792 constraint (postreg == 0xd || postreg == 0xf,
13793 _("bad register for post-index"));
13794 inst.instruction |= postreg;
13796 else if (inst.operands[1].writeback)
13798 inst.instruction |= 0xd;
13801 inst.instruction |= 0xf;
13804 inst.instruction |= 0xf9000000;
13806 inst.instruction |= 0xf4000000;
13810 /* Overall per-instruction processing. */
13812 /* We need to be able to fix up arbitrary expressions in some statements.
13813 This is so that we can handle symbols that are an arbitrary distance from
13814 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
13815 which returns part of an address in a form which will be valid for
13816 a data instruction. We do this by pushing the expression into a symbol
13817 in the expr_section, and creating a fix for that. */
13820 fix_new_arm (fragS * frag,
13835 new_fix = fix_new_exp (frag, where, size, exp, pc_rel, reloc);
13839 new_fix = fix_new (frag, where, size, make_expr_symbol (exp), 0,
13844 /* Mark whether the fix is to a THUMB instruction, or an ARM
13846 new_fix->tc_fix_data = thumb_mode;
13849 /* Create a frg for an instruction requiring relaxation. */
13851 output_relax_insn (void)
13857 /* The size of the instruction is unknown, so tie the debug info to the
13858 start of the instruction. */
13859 dwarf2_emit_insn (0);
13861 switch (inst.reloc.exp.X_op)
13864 sym = inst.reloc.exp.X_add_symbol;
13865 offset = inst.reloc.exp.X_add_number;
13869 offset = inst.reloc.exp.X_add_number;
13872 sym = make_expr_symbol (&inst.reloc.exp);
13876 to = frag_var (rs_machine_dependent, INSN_SIZE, THUMB_SIZE,
13877 inst.relax, sym, offset, NULL/*offset, opcode*/);
13878 md_number_to_chars (to, inst.instruction, THUMB_SIZE);
13881 /* Write a 32-bit thumb instruction to buf. */
13883 put_thumb32_insn (char * buf, unsigned long insn)
13885 md_number_to_chars (buf, insn >> 16, THUMB_SIZE);
13886 md_number_to_chars (buf + THUMB_SIZE, insn, THUMB_SIZE);
13890 output_inst (const char * str)
13896 as_bad ("%s -- `%s'", inst.error, str);
13900 output_relax_insn();
13903 if (inst.size == 0)
13906 to = frag_more (inst.size);
13908 if (thumb_mode && (inst.size > THUMB_SIZE))
13910 assert (inst.size == (2 * THUMB_SIZE));
13911 put_thumb32_insn (to, inst.instruction);
13913 else if (inst.size > INSN_SIZE)
13915 assert (inst.size == (2 * INSN_SIZE));
13916 md_number_to_chars (to, inst.instruction, INSN_SIZE);
13917 md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE);
13920 md_number_to_chars (to, inst.instruction, inst.size);
13922 if (inst.reloc.type != BFD_RELOC_UNUSED)
13923 fix_new_arm (frag_now, to - frag_now->fr_literal,
13924 inst.size, & inst.reloc.exp, inst.reloc.pc_rel,
13927 dwarf2_emit_insn (inst.size);
13930 /* Tag values used in struct asm_opcode's tag field. */
13933 OT_unconditional, /* Instruction cannot be conditionalized.
13934 The ARM condition field is still 0xE. */
13935 OT_unconditionalF, /* Instruction cannot be conditionalized
13936 and carries 0xF in its ARM condition field. */
13937 OT_csuffix, /* Instruction takes a conditional suffix. */
13938 OT_csuffixF, /* Some forms of the instruction take a conditional
13939 suffix, others place 0xF where the condition field
13941 OT_cinfix3, /* Instruction takes a conditional infix,
13942 beginning at character index 3. (In
13943 unified mode, it becomes a suffix.) */
13944 OT_cinfix3_deprecated, /* The same as OT_cinfix3. This is used for
13945 tsts, cmps, cmns, and teqs. */
13946 OT_cinfix3_legacy, /* Legacy instruction takes a conditional infix at
13947 character index 3, even in unified mode. Used for
13948 legacy instructions where suffix and infix forms
13949 may be ambiguous. */
13950 OT_csuf_or_in3, /* Instruction takes either a conditional
13951 suffix or an infix at character index 3. */
13952 OT_odd_infix_unc, /* This is the unconditional variant of an
13953 instruction that takes a conditional infix
13954 at an unusual position. In unified mode,
13955 this variant will accept a suffix. */
13956 OT_odd_infix_0 /* Values greater than or equal to OT_odd_infix_0
13957 are the conditional variants of instructions that
13958 take conditional infixes in unusual positions.
13959 The infix appears at character index
13960 (tag - OT_odd_infix_0). These are not accepted
13961 in unified mode. */
13964 /* Subroutine of md_assemble, responsible for looking up the primary
13965 opcode from the mnemonic the user wrote. STR points to the
13966 beginning of the mnemonic.
13968 This is not simply a hash table lookup, because of conditional
13969 variants. Most instructions have conditional variants, which are
13970 expressed with a _conditional affix_ to the mnemonic. If we were
13971 to encode each conditional variant as a literal string in the opcode
13972 table, it would have approximately 20,000 entries.
13974 Most mnemonics take this affix as a suffix, and in unified syntax,
13975 'most' is upgraded to 'all'. However, in the divided syntax, some
13976 instructions take the affix as an infix, notably the s-variants of
13977 the arithmetic instructions. Of those instructions, all but six
13978 have the infix appear after the third character of the mnemonic.
13980 Accordingly, the algorithm for looking up primary opcodes given
13983 1. Look up the identifier in the opcode table.
13984 If we find a match, go to step U.
13986 2. Look up the last two characters of the identifier in the
13987 conditions table. If we find a match, look up the first N-2
13988 characters of the identifier in the opcode table. If we
13989 find a match, go to step CE.
13991 3. Look up the fourth and fifth characters of the identifier in
13992 the conditions table. If we find a match, extract those
13993 characters from the identifier, and look up the remaining
13994 characters in the opcode table. If we find a match, go
13999 U. Examine the tag field of the opcode structure, in case this is
14000 one of the six instructions with its conditional infix in an
14001 unusual place. If it is, the tag tells us where to find the
14002 infix; look it up in the conditions table and set inst.cond
14003 accordingly. Otherwise, this is an unconditional instruction.
14004 Again set inst.cond accordingly. Return the opcode structure.
14006 CE. Examine the tag field to make sure this is an instruction that
14007 should receive a conditional suffix. If it is not, fail.
14008 Otherwise, set inst.cond from the suffix we already looked up,
14009 and return the opcode structure.
14011 CM. Examine the tag field to make sure this is an instruction that
14012 should receive a conditional infix after the third character.
14013 If it is not, fail. Otherwise, undo the edits to the current
14014 line of input and proceed as for case CE. */
14016 static const struct asm_opcode *
14017 opcode_lookup (char **str)
14021 const struct asm_opcode *opcode;
14022 const struct asm_cond *cond;
14024 bfd_boolean neon_supported;
14026 neon_supported = ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1);
14028 /* Scan up to the end of the mnemonic, which must end in white space,
14029 '.' (in unified mode, or for Neon instructions), or end of string. */
14030 for (base = end = *str; *end != '\0'; end++)
14031 if (*end == ' ' || ((unified_syntax || neon_supported) && *end == '.'))
14037 /* Handle a possible width suffix and/or Neon type suffix. */
14042 /* The .w and .n suffixes are only valid if the unified syntax is in
14044 if (unified_syntax && end[1] == 'w')
14046 else if (unified_syntax && end[1] == 'n')
14051 inst.vectype.elems = 0;
14053 *str = end + offset;
14055 if (end[offset] == '.')
14057 /* See if we have a Neon type suffix (possible in either unified or
14058 non-unified ARM syntax mode). */
14059 if (parse_neon_type (&inst.vectype, str) == FAIL)
14062 else if (end[offset] != '\0' && end[offset] != ' ')
14068 /* Look for unaffixed or special-case affixed mnemonic. */
14069 opcode = hash_find_n (arm_ops_hsh, base, end - base);
14073 if (opcode->tag < OT_odd_infix_0)
14075 inst.cond = COND_ALWAYS;
14079 if (unified_syntax)
14080 as_warn (_("conditional infixes are deprecated in unified syntax"));
14081 affix = base + (opcode->tag - OT_odd_infix_0);
14082 cond = hash_find_n (arm_cond_hsh, affix, 2);
14085 inst.cond = cond->value;
14089 /* Cannot have a conditional suffix on a mnemonic of less than two
14091 if (end - base < 3)
14094 /* Look for suffixed mnemonic. */
14096 cond = hash_find_n (arm_cond_hsh, affix, 2);
14097 opcode = hash_find_n (arm_ops_hsh, base, affix - base);
14098 if (opcode && cond)
14101 switch (opcode->tag)
14103 case OT_cinfix3_legacy:
14104 /* Ignore conditional suffixes matched on infix only mnemonics. */
14108 case OT_cinfix3_deprecated:
14109 case OT_odd_infix_unc:
14110 if (!unified_syntax)
14112 /* else fall through */
14116 case OT_csuf_or_in3:
14117 inst.cond = cond->value;
14120 case OT_unconditional:
14121 case OT_unconditionalF:
14124 inst.cond = cond->value;
14128 /* delayed diagnostic */
14129 inst.error = BAD_COND;
14130 inst.cond = COND_ALWAYS;
14139 /* Cannot have a usual-position infix on a mnemonic of less than
14140 six characters (five would be a suffix). */
14141 if (end - base < 6)
14144 /* Look for infixed mnemonic in the usual position. */
14146 cond = hash_find_n (arm_cond_hsh, affix, 2);
14150 memcpy (save, affix, 2);
14151 memmove (affix, affix + 2, (end - affix) - 2);
14152 opcode = hash_find_n (arm_ops_hsh, base, (end - base) - 2);
14153 memmove (affix + 2, affix, (end - affix) - 2);
14154 memcpy (affix, save, 2);
14157 && (opcode->tag == OT_cinfix3
14158 || opcode->tag == OT_cinfix3_deprecated
14159 || opcode->tag == OT_csuf_or_in3
14160 || opcode->tag == OT_cinfix3_legacy))
14164 && (opcode->tag == OT_cinfix3
14165 || opcode->tag == OT_cinfix3_deprecated))
14166 as_warn (_("conditional infixes are deprecated in unified syntax"));
14168 inst.cond = cond->value;
14176 md_assemble (char *str)
14179 const struct asm_opcode * opcode;
14181 /* Align the previous label if needed. */
14182 if (last_label_seen != NULL)
14184 symbol_set_frag (last_label_seen, frag_now);
14185 S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ());
14186 S_SET_SEGMENT (last_label_seen, now_seg);
14189 memset (&inst, '\0', sizeof (inst));
14190 inst.reloc.type = BFD_RELOC_UNUSED;
14192 opcode = opcode_lookup (&p);
14195 /* It wasn't an instruction, but it might be a register alias of
14196 the form alias .req reg, or a Neon .dn/.qn directive. */
14197 if (!create_register_alias (str, p)
14198 && !create_neon_reg_alias (str, p))
14199 as_bad (_("bad instruction `%s'"), str);
14204 if (opcode->tag == OT_cinfix3_deprecated)
14205 as_warn (_("s suffix on comparison instruction is deprecated"));
14207 /* The value which unconditional instructions should have in place of the
14208 condition field. */
14209 inst.uncond_value = (opcode->tag == OT_csuffixF) ? 0xf : -1;
14213 arm_feature_set variant;
14215 variant = cpu_variant;
14216 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
14217 if (!ARM_CPU_HAS_FEATURE (variant, arm_arch_t2))
14218 ARM_CLEAR_FEATURE (variant, variant, fpu_any_hard);
14219 /* Check that this instruction is supported for this CPU. */
14220 if (!opcode->tvariant
14221 || (thumb_mode == 1
14222 && !ARM_CPU_HAS_FEATURE (variant, *opcode->tvariant)))
14224 as_bad (_("selected processor does not support `%s'"), str);
14227 if (inst.cond != COND_ALWAYS && !unified_syntax
14228 && opcode->tencode != do_t_branch)
14230 as_bad (_("Thumb does not support conditional execution"));
14234 if (!ARM_CPU_HAS_FEATURE (variant, arm_ext_v6t2) && !inst.size_req)
14236 /* Implicit require narrow instructions on Thumb-1. This avoids
14237 relaxation accidentally introducing Thumb-2 instructions. */
14238 if (opcode->tencode != do_t_blx && opcode->tencode != do_t_branch23)
14242 /* Check conditional suffixes. */
14243 if (current_it_mask)
14246 cond = current_cc ^ ((current_it_mask >> 4) & 1) ^ 1;
14247 current_it_mask <<= 1;
14248 current_it_mask &= 0x1f;
14249 /* The BKPT instruction is unconditional even in an IT block. */
14251 && cond != inst.cond && opcode->tencode != do_t_bkpt)
14253 as_bad (_("incorrect condition in IT block"));
14257 else if (inst.cond != COND_ALWAYS && opcode->tencode != do_t_branch)
14259 as_bad (_("thumb conditional instrunction not in IT block"));
14263 mapping_state (MAP_THUMB);
14264 inst.instruction = opcode->tvalue;
14266 if (!parse_operands (p, opcode->operands))
14267 opcode->tencode ();
14269 /* Clear current_it_mask at the end of an IT block. */
14270 if (current_it_mask == 0x10)
14271 current_it_mask = 0;
14273 if (!(inst.error || inst.relax))
14275 assert (inst.instruction < 0xe800 || inst.instruction > 0xffff);
14276 inst.size = (inst.instruction > 0xffff ? 4 : 2);
14277 if (inst.size_req && inst.size_req != inst.size)
14279 as_bad (_("cannot honor width suffix -- `%s'"), str);
14284 /* Something has gone badly wrong if we try to relax a fixed size
14286 assert (inst.size_req == 0 || !inst.relax);
14288 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
14289 *opcode->tvariant);
14290 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
14291 set those bits when Thumb-2 32-bit instructions are seen. ie.
14292 anything other than bl/blx.
14293 This is overly pessimistic for relaxable instructions. */
14294 if ((inst.size == 4 && (inst.instruction & 0xf800e800) != 0xf000e800)
14296 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
14299 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
14301 /* Check that this instruction is supported for this CPU. */
14302 if (!opcode->avariant ||
14303 !ARM_CPU_HAS_FEATURE (cpu_variant, *opcode->avariant))
14305 as_bad (_("selected processor does not support `%s'"), str);
14310 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str);
14314 mapping_state (MAP_ARM);
14315 inst.instruction = opcode->avalue;
14316 if (opcode->tag == OT_unconditionalF)
14317 inst.instruction |= 0xF << 28;
14319 inst.instruction |= inst.cond << 28;
14320 inst.size = INSN_SIZE;
14321 if (!parse_operands (p, opcode->operands))
14322 opcode->aencode ();
14323 /* Arm mode bx is marked as both v4T and v5 because it's still required
14324 on a hypothetical non-thumb v5 core. */
14325 if (ARM_CPU_HAS_FEATURE (*opcode->avariant, arm_ext_v4t)
14326 || ARM_CPU_HAS_FEATURE (*opcode->avariant, arm_ext_v5))
14327 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, arm_ext_v4t);
14329 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
14330 *opcode->avariant);
14334 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
14341 /* Various frobbings of labels and their addresses. */
14344 arm_start_line_hook (void)
14346 last_label_seen = NULL;
14350 arm_frob_label (symbolS * sym)
14352 last_label_seen = sym;
14354 ARM_SET_THUMB (sym, thumb_mode);
14356 #if defined OBJ_COFF || defined OBJ_ELF
14357 ARM_SET_INTERWORK (sym, support_interwork);
14360 /* Note - do not allow local symbols (.Lxxx) to be labeled
14361 as Thumb functions. This is because these labels, whilst
14362 they exist inside Thumb code, are not the entry points for
14363 possible ARM->Thumb calls. Also, these labels can be used
14364 as part of a computed goto or switch statement. eg gcc
14365 can generate code that looks like this:
14367 ldr r2, [pc, .Laaa]
14377 The first instruction loads the address of the jump table.
14378 The second instruction converts a table index into a byte offset.
14379 The third instruction gets the jump address out of the table.
14380 The fourth instruction performs the jump.
14382 If the address stored at .Laaa is that of a symbol which has the
14383 Thumb_Func bit set, then the linker will arrange for this address
14384 to have the bottom bit set, which in turn would mean that the
14385 address computation performed by the third instruction would end
14386 up with the bottom bit set. Since the ARM is capable of unaligned
14387 word loads, the instruction would then load the incorrect address
14388 out of the jump table, and chaos would ensue. */
14389 if (label_is_thumb_function_name
14390 && (S_GET_NAME (sym)[0] != '.' || S_GET_NAME (sym)[1] != 'L')
14391 && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
14393 /* When the address of a Thumb function is taken the bottom
14394 bit of that address should be set. This will allow
14395 interworking between Arm and Thumb functions to work
14398 THUMB_SET_FUNC (sym, 1);
14400 label_is_thumb_function_name = FALSE;
14403 dwarf2_emit_label (sym);
14407 arm_data_in_code (void)
14409 if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5))
14411 *input_line_pointer = '/';
14412 input_line_pointer += 5;
14413 *input_line_pointer = 0;
14421 arm_canonicalize_symbol_name (char * name)
14425 if (thumb_mode && (len = strlen (name)) > 5
14426 && streq (name + len - 5, "/data"))
14427 *(name + len - 5) = 0;
14432 /* Table of all register names defined by default. The user can
14433 define additional names with .req. Note that all register names
14434 should appear in both upper and lowercase variants. Some registers
14435 also have mixed-case names. */
14437 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
14438 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
14439 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
14440 #define REGSET(p,t) \
14441 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
14442 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
14443 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
14444 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
14445 #define REGSETH(p,t) \
14446 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
14447 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
14448 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
14449 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
14450 #define REGSET2(p,t) \
14451 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
14452 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
14453 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
14454 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
14456 static const struct reg_entry reg_names[] =
14458 /* ARM integer registers. */
14459 REGSET(r, RN), REGSET(R, RN),
14461 /* ATPCS synonyms. */
14462 REGDEF(a1,0,RN), REGDEF(a2,1,RN), REGDEF(a3, 2,RN), REGDEF(a4, 3,RN),
14463 REGDEF(v1,4,RN), REGDEF(v2,5,RN), REGDEF(v3, 6,RN), REGDEF(v4, 7,RN),
14464 REGDEF(v5,8,RN), REGDEF(v6,9,RN), REGDEF(v7,10,RN), REGDEF(v8,11,RN),
14466 REGDEF(A1,0,RN), REGDEF(A2,1,RN), REGDEF(A3, 2,RN), REGDEF(A4, 3,RN),
14467 REGDEF(V1,4,RN), REGDEF(V2,5,RN), REGDEF(V3, 6,RN), REGDEF(V4, 7,RN),
14468 REGDEF(V5,8,RN), REGDEF(V6,9,RN), REGDEF(V7,10,RN), REGDEF(V8,11,RN),
14470 /* Well-known aliases. */
14471 REGDEF(wr, 7,RN), REGDEF(sb, 9,RN), REGDEF(sl,10,RN), REGDEF(fp,11,RN),
14472 REGDEF(ip,12,RN), REGDEF(sp,13,RN), REGDEF(lr,14,RN), REGDEF(pc,15,RN),
14474 REGDEF(WR, 7,RN), REGDEF(SB, 9,RN), REGDEF(SL,10,RN), REGDEF(FP,11,RN),
14475 REGDEF(IP,12,RN), REGDEF(SP,13,RN), REGDEF(LR,14,RN), REGDEF(PC,15,RN),
14477 /* Coprocessor numbers. */
14478 REGSET(p, CP), REGSET(P, CP),
14480 /* Coprocessor register numbers. The "cr" variants are for backward
14482 REGSET(c, CN), REGSET(C, CN),
14483 REGSET(cr, CN), REGSET(CR, CN),
14485 /* FPA registers. */
14486 REGNUM(f,0,FN), REGNUM(f,1,FN), REGNUM(f,2,FN), REGNUM(f,3,FN),
14487 REGNUM(f,4,FN), REGNUM(f,5,FN), REGNUM(f,6,FN), REGNUM(f,7, FN),
14489 REGNUM(F,0,FN), REGNUM(F,1,FN), REGNUM(F,2,FN), REGNUM(F,3,FN),
14490 REGNUM(F,4,FN), REGNUM(F,5,FN), REGNUM(F,6,FN), REGNUM(F,7, FN),
14492 /* VFP SP registers. */
14493 REGSET(s,VFS), REGSET(S,VFS),
14494 REGSETH(s,VFS), REGSETH(S,VFS),
14496 /* VFP DP Registers. */
14497 REGSET(d,VFD), REGSET(D,VFD),
14498 /* Extra Neon DP registers. */
14499 REGSETH(d,VFD), REGSETH(D,VFD),
14501 /* Neon QP registers. */
14502 REGSET2(q,NQ), REGSET2(Q,NQ),
14504 /* VFP control registers. */
14505 REGDEF(fpsid,0,VFC), REGDEF(fpscr,1,VFC), REGDEF(fpexc,8,VFC),
14506 REGDEF(FPSID,0,VFC), REGDEF(FPSCR,1,VFC), REGDEF(FPEXC,8,VFC),
14507 REGDEF(fpinst,9,VFC), REGDEF(fpinst2,10,VFC),
14508 REGDEF(FPINST,9,VFC), REGDEF(FPINST2,10,VFC),
14509 REGDEF(mvfr0,7,VFC), REGDEF(mvfr1,6,VFC),
14510 REGDEF(MVFR0,7,VFC), REGDEF(MVFR1,6,VFC),
14512 /* Maverick DSP coprocessor registers. */
14513 REGSET(mvf,MVF), REGSET(mvd,MVD), REGSET(mvfx,MVFX), REGSET(mvdx,MVDX),
14514 REGSET(MVF,MVF), REGSET(MVD,MVD), REGSET(MVFX,MVFX), REGSET(MVDX,MVDX),
14516 REGNUM(mvax,0,MVAX), REGNUM(mvax,1,MVAX),
14517 REGNUM(mvax,2,MVAX), REGNUM(mvax,3,MVAX),
14518 REGDEF(dspsc,0,DSPSC),
14520 REGNUM(MVAX,0,MVAX), REGNUM(MVAX,1,MVAX),
14521 REGNUM(MVAX,2,MVAX), REGNUM(MVAX,3,MVAX),
14522 REGDEF(DSPSC,0,DSPSC),
14524 /* iWMMXt data registers - p0, c0-15. */
14525 REGSET(wr,MMXWR), REGSET(wR,MMXWR), REGSET(WR, MMXWR),
14527 /* iWMMXt control registers - p1, c0-3. */
14528 REGDEF(wcid, 0,MMXWC), REGDEF(wCID, 0,MMXWC), REGDEF(WCID, 0,MMXWC),
14529 REGDEF(wcon, 1,MMXWC), REGDEF(wCon, 1,MMXWC), REGDEF(WCON, 1,MMXWC),
14530 REGDEF(wcssf, 2,MMXWC), REGDEF(wCSSF, 2,MMXWC), REGDEF(WCSSF, 2,MMXWC),
14531 REGDEF(wcasf, 3,MMXWC), REGDEF(wCASF, 3,MMXWC), REGDEF(WCASF, 3,MMXWC),
14533 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
14534 REGDEF(wcgr0, 8,MMXWCG), REGDEF(wCGR0, 8,MMXWCG), REGDEF(WCGR0, 8,MMXWCG),
14535 REGDEF(wcgr1, 9,MMXWCG), REGDEF(wCGR1, 9,MMXWCG), REGDEF(WCGR1, 9,MMXWCG),
14536 REGDEF(wcgr2,10,MMXWCG), REGDEF(wCGR2,10,MMXWCG), REGDEF(WCGR2,10,MMXWCG),
14537 REGDEF(wcgr3,11,MMXWCG), REGDEF(wCGR3,11,MMXWCG), REGDEF(WCGR3,11,MMXWCG),
14539 /* XScale accumulator registers. */
14540 REGNUM(acc,0,XSCALE), REGNUM(ACC,0,XSCALE),
14546 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
14547 within psr_required_here. */
14548 static const struct asm_psr psrs[] =
14550 /* Backward compatibility notation. Note that "all" is no longer
14551 truly all possible PSR bits. */
14552 {"all", PSR_c | PSR_f},
14556 /* Individual flags. */
14561 /* Combinations of flags. */
14562 {"fs", PSR_f | PSR_s},
14563 {"fx", PSR_f | PSR_x},
14564 {"fc", PSR_f | PSR_c},
14565 {"sf", PSR_s | PSR_f},
14566 {"sx", PSR_s | PSR_x},
14567 {"sc", PSR_s | PSR_c},
14568 {"xf", PSR_x | PSR_f},
14569 {"xs", PSR_x | PSR_s},
14570 {"xc", PSR_x | PSR_c},
14571 {"cf", PSR_c | PSR_f},
14572 {"cs", PSR_c | PSR_s},
14573 {"cx", PSR_c | PSR_x},
14574 {"fsx", PSR_f | PSR_s | PSR_x},
14575 {"fsc", PSR_f | PSR_s | PSR_c},
14576 {"fxs", PSR_f | PSR_x | PSR_s},
14577 {"fxc", PSR_f | PSR_x | PSR_c},
14578 {"fcs", PSR_f | PSR_c | PSR_s},
14579 {"fcx", PSR_f | PSR_c | PSR_x},
14580 {"sfx", PSR_s | PSR_f | PSR_x},
14581 {"sfc", PSR_s | PSR_f | PSR_c},
14582 {"sxf", PSR_s | PSR_x | PSR_f},
14583 {"sxc", PSR_s | PSR_x | PSR_c},
14584 {"scf", PSR_s | PSR_c | PSR_f},
14585 {"scx", PSR_s | PSR_c | PSR_x},
14586 {"xfs", PSR_x | PSR_f | PSR_s},
14587 {"xfc", PSR_x | PSR_f | PSR_c},
14588 {"xsf", PSR_x | PSR_s | PSR_f},
14589 {"xsc", PSR_x | PSR_s | PSR_c},
14590 {"xcf", PSR_x | PSR_c | PSR_f},
14591 {"xcs", PSR_x | PSR_c | PSR_s},
14592 {"cfs", PSR_c | PSR_f | PSR_s},
14593 {"cfx", PSR_c | PSR_f | PSR_x},
14594 {"csf", PSR_c | PSR_s | PSR_f},
14595 {"csx", PSR_c | PSR_s | PSR_x},
14596 {"cxf", PSR_c | PSR_x | PSR_f},
14597 {"cxs", PSR_c | PSR_x | PSR_s},
14598 {"fsxc", PSR_f | PSR_s | PSR_x | PSR_c},
14599 {"fscx", PSR_f | PSR_s | PSR_c | PSR_x},
14600 {"fxsc", PSR_f | PSR_x | PSR_s | PSR_c},
14601 {"fxcs", PSR_f | PSR_x | PSR_c | PSR_s},
14602 {"fcsx", PSR_f | PSR_c | PSR_s | PSR_x},
14603 {"fcxs", PSR_f | PSR_c | PSR_x | PSR_s},
14604 {"sfxc", PSR_s | PSR_f | PSR_x | PSR_c},
14605 {"sfcx", PSR_s | PSR_f | PSR_c | PSR_x},
14606 {"sxfc", PSR_s | PSR_x | PSR_f | PSR_c},
14607 {"sxcf", PSR_s | PSR_x | PSR_c | PSR_f},
14608 {"scfx", PSR_s | PSR_c | PSR_f | PSR_x},
14609 {"scxf", PSR_s | PSR_c | PSR_x | PSR_f},
14610 {"xfsc", PSR_x | PSR_f | PSR_s | PSR_c},
14611 {"xfcs", PSR_x | PSR_f | PSR_c | PSR_s},
14612 {"xsfc", PSR_x | PSR_s | PSR_f | PSR_c},
14613 {"xscf", PSR_x | PSR_s | PSR_c | PSR_f},
14614 {"xcfs", PSR_x | PSR_c | PSR_f | PSR_s},
14615 {"xcsf", PSR_x | PSR_c | PSR_s | PSR_f},
14616 {"cfsx", PSR_c | PSR_f | PSR_s | PSR_x},
14617 {"cfxs", PSR_c | PSR_f | PSR_x | PSR_s},
14618 {"csfx", PSR_c | PSR_s | PSR_f | PSR_x},
14619 {"csxf", PSR_c | PSR_s | PSR_x | PSR_f},
14620 {"cxfs", PSR_c | PSR_x | PSR_f | PSR_s},
14621 {"cxsf", PSR_c | PSR_x | PSR_s | PSR_f},
14624 /* Table of V7M psr names. */
14625 static const struct asm_psr v7m_psrs[] =
14627 {"apsr", 0 }, {"APSR", 0 },
14628 {"iapsr", 1 }, {"IAPSR", 1 },
14629 {"eapsr", 2 }, {"EAPSR", 2 },
14630 {"psr", 3 }, {"PSR", 3 },
14631 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
14632 {"ipsr", 5 }, {"IPSR", 5 },
14633 {"epsr", 6 }, {"EPSR", 6 },
14634 {"iepsr", 7 }, {"IEPSR", 7 },
14635 {"msp", 8 }, {"MSP", 8 },
14636 {"psp", 9 }, {"PSP", 9 },
14637 {"primask", 16}, {"PRIMASK", 16},
14638 {"basepri", 17}, {"BASEPRI", 17},
14639 {"basepri_max", 18}, {"BASEPRI_MAX", 18},
14640 {"faultmask", 19}, {"FAULTMASK", 19},
14641 {"control", 20}, {"CONTROL", 20}
14644 /* Table of all shift-in-operand names. */
14645 static const struct asm_shift_name shift_names [] =
14647 { "asl", SHIFT_LSL }, { "ASL", SHIFT_LSL },
14648 { "lsl", SHIFT_LSL }, { "LSL", SHIFT_LSL },
14649 { "lsr", SHIFT_LSR }, { "LSR", SHIFT_LSR },
14650 { "asr", SHIFT_ASR }, { "ASR", SHIFT_ASR },
14651 { "ror", SHIFT_ROR }, { "ROR", SHIFT_ROR },
14652 { "rrx", SHIFT_RRX }, { "RRX", SHIFT_RRX }
14655 /* Table of all explicit relocation names. */
14657 static struct reloc_entry reloc_names[] =
14659 { "got", BFD_RELOC_ARM_GOT32 }, { "GOT", BFD_RELOC_ARM_GOT32 },
14660 { "gotoff", BFD_RELOC_ARM_GOTOFF }, { "GOTOFF", BFD_RELOC_ARM_GOTOFF },
14661 { "plt", BFD_RELOC_ARM_PLT32 }, { "PLT", BFD_RELOC_ARM_PLT32 },
14662 { "target1", BFD_RELOC_ARM_TARGET1 }, { "TARGET1", BFD_RELOC_ARM_TARGET1 },
14663 { "target2", BFD_RELOC_ARM_TARGET2 }, { "TARGET2", BFD_RELOC_ARM_TARGET2 },
14664 { "sbrel", BFD_RELOC_ARM_SBREL32 }, { "SBREL", BFD_RELOC_ARM_SBREL32 },
14665 { "tlsgd", BFD_RELOC_ARM_TLS_GD32}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32},
14666 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32},
14667 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32},
14668 { "gottpoff",BFD_RELOC_ARM_TLS_IE32}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32},
14669 { "tpoff", BFD_RELOC_ARM_TLS_LE32}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32}
14673 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
14674 static const struct asm_cond conds[] =
14678 {"cs", 0x2}, {"hs", 0x2},
14679 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
14693 static struct asm_barrier_opt barrier_opt_names[] =
14701 /* Table of ARM-format instructions. */
14703 /* Macros for gluing together operand strings. N.B. In all cases
14704 other than OPS0, the trailing OP_stop comes from default
14705 zero-initialization of the unspecified elements of the array. */
14706 #define OPS0() { OP_stop, }
14707 #define OPS1(a) { OP_##a, }
14708 #define OPS2(a,b) { OP_##a,OP_##b, }
14709 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
14710 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
14711 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
14712 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
14714 /* These macros abstract out the exact format of the mnemonic table and
14715 save some repeated characters. */
14717 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
14718 #define TxCE(mnem, op, top, nops, ops, ae, te) \
14719 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
14720 THUMB_VARIANT, do_##ae, do_##te }
14722 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
14723 a T_MNEM_xyz enumerator. */
14724 #define TCE(mnem, aop, top, nops, ops, ae, te) \
14725 TxCE(mnem, aop, 0x##top, nops, ops, ae, te)
14726 #define tCE(mnem, aop, top, nops, ops, ae, te) \
14727 TxCE(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
14729 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
14730 infix after the third character. */
14731 #define TxC3(mnem, op, top, nops, ops, ae, te) \
14732 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
14733 THUMB_VARIANT, do_##ae, do_##te }
14734 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
14735 { #mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
14736 THUMB_VARIANT, do_##ae, do_##te }
14737 #define TC3(mnem, aop, top, nops, ops, ae, te) \
14738 TxC3(mnem, aop, 0x##top, nops, ops, ae, te)
14739 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
14740 TxC3w(mnem, aop, 0x##top, nops, ops, ae, te)
14741 #define tC3(mnem, aop, top, nops, ops, ae, te) \
14742 TxC3(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
14743 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
14744 TxC3w(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
14746 /* Mnemonic with a conditional infix in an unusual place. Each and every variant has to
14747 appear in the condition table. */
14748 #define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \
14749 { #m1 #m2 #m3, OPS##nops ops, sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \
14750 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te }
14752 #define TxCM(m1, m2, op, top, nops, ops, ae, te) \
14753 TxCM_(m1, , m2, op, top, nops, ops, ae, te), \
14754 TxCM_(m1, eq, m2, op, top, nops, ops, ae, te), \
14755 TxCM_(m1, ne, m2, op, top, nops, ops, ae, te), \
14756 TxCM_(m1, cs, m2, op, top, nops, ops, ae, te), \
14757 TxCM_(m1, hs, m2, op, top, nops, ops, ae, te), \
14758 TxCM_(m1, cc, m2, op, top, nops, ops, ae, te), \
14759 TxCM_(m1, ul, m2, op, top, nops, ops, ae, te), \
14760 TxCM_(m1, lo, m2, op, top, nops, ops, ae, te), \
14761 TxCM_(m1, mi, m2, op, top, nops, ops, ae, te), \
14762 TxCM_(m1, pl, m2, op, top, nops, ops, ae, te), \
14763 TxCM_(m1, vs, m2, op, top, nops, ops, ae, te), \
14764 TxCM_(m1, vc, m2, op, top, nops, ops, ae, te), \
14765 TxCM_(m1, hi, m2, op, top, nops, ops, ae, te), \
14766 TxCM_(m1, ls, m2, op, top, nops, ops, ae, te), \
14767 TxCM_(m1, ge, m2, op, top, nops, ops, ae, te), \
14768 TxCM_(m1, lt, m2, op, top, nops, ops, ae, te), \
14769 TxCM_(m1, gt, m2, op, top, nops, ops, ae, te), \
14770 TxCM_(m1, le, m2, op, top, nops, ops, ae, te), \
14771 TxCM_(m1, al, m2, op, top, nops, ops, ae, te)
14773 #define TCM(m1,m2, aop, top, nops, ops, ae, te) \
14774 TxCM(m1,m2, aop, 0x##top, nops, ops, ae, te)
14775 #define tCM(m1,m2, aop, top, nops, ops, ae, te) \
14776 TxCM(m1,m2, aop, T_MNEM_##top, nops, ops, ae, te)
14778 /* Mnemonic that cannot be conditionalized. The ARM condition-code
14779 field is still 0xE. Many of the Thumb variants can be executed
14780 conditionally, so this is checked separately. */
14781 #define TUE(mnem, op, top, nops, ops, ae, te) \
14782 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
14783 THUMB_VARIANT, do_##ae, do_##te }
14785 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
14786 condition code field. */
14787 #define TUF(mnem, op, top, nops, ops, ae, te) \
14788 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
14789 THUMB_VARIANT, do_##ae, do_##te }
14791 /* ARM-only variants of all the above. */
14792 #define CE(mnem, op, nops, ops, ae) \
14793 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14795 #define C3(mnem, op, nops, ops, ae) \
14796 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14798 /* Legacy mnemonics that always have conditional infix after the third
14800 #define CL(mnem, op, nops, ops, ae) \
14801 { #mnem, OPS##nops ops, OT_cinfix3_legacy, \
14802 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14804 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
14805 #define cCE(mnem, op, nops, ops, ae) \
14806 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
14808 /* Legacy coprocessor instructions where conditional infix and conditional
14809 suffix are ambiguous. For consistency this includes all FPA instructions,
14810 not just the potentially ambiguous ones. */
14811 #define cCL(mnem, op, nops, ops, ae) \
14812 { #mnem, OPS##nops ops, OT_cinfix3_legacy, \
14813 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
14815 /* Coprocessor, takes either a suffix or a position-3 infix
14816 (for an FPA corner case). */
14817 #define C3E(mnem, op, nops, ops, ae) \
14818 { #mnem, OPS##nops ops, OT_csuf_or_in3, \
14819 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
14821 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
14822 { #m1 #m2 #m3, OPS##nops ops, \
14823 sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \
14824 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14826 #define CM(m1, m2, op, nops, ops, ae) \
14827 xCM_(m1, , m2, op, nops, ops, ae), \
14828 xCM_(m1, eq, m2, op, nops, ops, ae), \
14829 xCM_(m1, ne, m2, op, nops, ops, ae), \
14830 xCM_(m1, cs, m2, op, nops, ops, ae), \
14831 xCM_(m1, hs, m2, op, nops, ops, ae), \
14832 xCM_(m1, cc, m2, op, nops, ops, ae), \
14833 xCM_(m1, ul, m2, op, nops, ops, ae), \
14834 xCM_(m1, lo, m2, op, nops, ops, ae), \
14835 xCM_(m1, mi, m2, op, nops, ops, ae), \
14836 xCM_(m1, pl, m2, op, nops, ops, ae), \
14837 xCM_(m1, vs, m2, op, nops, ops, ae), \
14838 xCM_(m1, vc, m2, op, nops, ops, ae), \
14839 xCM_(m1, hi, m2, op, nops, ops, ae), \
14840 xCM_(m1, ls, m2, op, nops, ops, ae), \
14841 xCM_(m1, ge, m2, op, nops, ops, ae), \
14842 xCM_(m1, lt, m2, op, nops, ops, ae), \
14843 xCM_(m1, gt, m2, op, nops, ops, ae), \
14844 xCM_(m1, le, m2, op, nops, ops, ae), \
14845 xCM_(m1, al, m2, op, nops, ops, ae)
14847 #define UE(mnem, op, nops, ops, ae) \
14848 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
14850 #define UF(mnem, op, nops, ops, ae) \
14851 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
14853 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
14854 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
14855 use the same encoding function for each. */
14856 #define NUF(mnem, op, nops, ops, enc) \
14857 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
14858 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
14860 /* Neon data processing, version which indirects through neon_enc_tab for
14861 the various overloaded versions of opcodes. */
14862 #define nUF(mnem, op, nops, ops, enc) \
14863 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM_##op, N_MNEM_##op, \
14864 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
14866 /* Neon insn with conditional suffix for the ARM version, non-overloaded
14868 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
14869 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
14870 THUMB_VARIANT, do_##enc, do_##enc }
14872 #define NCE(mnem, op, nops, ops, enc) \
14873 NCE_tag(mnem, op, nops, ops, enc, OT_csuffix)
14875 #define NCEF(mnem, op, nops, ops, enc) \
14876 NCE_tag(mnem, op, nops, ops, enc, OT_csuffixF)
14878 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
14879 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
14880 { #mnem, OPS##nops ops, tag, N_MNEM_##op, N_MNEM_##op, \
14881 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
14883 #define nCE(mnem, op, nops, ops, enc) \
14884 nCE_tag(mnem, op, nops, ops, enc, OT_csuffix)
14886 #define nCEF(mnem, op, nops, ops, enc) \
14887 nCE_tag(mnem, op, nops, ops, enc, OT_csuffixF)
14891 /* Thumb-only, unconditional. */
14892 #define UT(mnem, op, nops, ops, te) TUE(mnem, 0, op, nops, ops, 0, te)
14894 static const struct asm_opcode insns[] =
14896 #define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */
14897 #define THUMB_VARIANT &arm_ext_v4t
14898 tCE(and, 0000000, and, 3, (RR, oRR, SH), arit, t_arit3c),
14899 tC3(ands, 0100000, ands, 3, (RR, oRR, SH), arit, t_arit3c),
14900 tCE(eor, 0200000, eor, 3, (RR, oRR, SH), arit, t_arit3c),
14901 tC3(eors, 0300000, eors, 3, (RR, oRR, SH), arit, t_arit3c),
14902 tCE(sub, 0400000, sub, 3, (RR, oRR, SH), arit, t_add_sub),
14903 tC3(subs, 0500000, subs, 3, (RR, oRR, SH), arit, t_add_sub),
14904 tCE(add, 0800000, add, 3, (RR, oRR, SHG), arit, t_add_sub),
14905 tC3(adds, 0900000, adds, 3, (RR, oRR, SHG), arit, t_add_sub),
14906 tCE(adc, 0a00000, adc, 3, (RR, oRR, SH), arit, t_arit3c),
14907 tC3(adcs, 0b00000, adcs, 3, (RR, oRR, SH), arit, t_arit3c),
14908 tCE(sbc, 0c00000, sbc, 3, (RR, oRR, SH), arit, t_arit3),
14909 tC3(sbcs, 0d00000, sbcs, 3, (RR, oRR, SH), arit, t_arit3),
14910 tCE(orr, 1800000, orr, 3, (RR, oRR, SH), arit, t_arit3c),
14911 tC3(orrs, 1900000, orrs, 3, (RR, oRR, SH), arit, t_arit3c),
14912 tCE(bic, 1c00000, bic, 3, (RR, oRR, SH), arit, t_arit3),
14913 tC3(bics, 1d00000, bics, 3, (RR, oRR, SH), arit, t_arit3),
14915 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
14916 for setting PSR flag bits. They are obsolete in V6 and do not
14917 have Thumb equivalents. */
14918 tCE(tst, 1100000, tst, 2, (RR, SH), cmp, t_mvn_tst),
14919 tC3w(tsts, 1100000, tst, 2, (RR, SH), cmp, t_mvn_tst),
14920 CL(tstp, 110f000, 2, (RR, SH), cmp),
14921 tCE(cmp, 1500000, cmp, 2, (RR, SH), cmp, t_mov_cmp),
14922 tC3w(cmps, 1500000, cmp, 2, (RR, SH), cmp, t_mov_cmp),
14923 CL(cmpp, 150f000, 2, (RR, SH), cmp),
14924 tCE(cmn, 1700000, cmn, 2, (RR, SH), cmp, t_mvn_tst),
14925 tC3w(cmns, 1700000, cmn, 2, (RR, SH), cmp, t_mvn_tst),
14926 CL(cmnp, 170f000, 2, (RR, SH), cmp),
14928 tCE(mov, 1a00000, mov, 2, (RR, SH), mov, t_mov_cmp),
14929 tC3(movs, 1b00000, movs, 2, (RR, SH), mov, t_mov_cmp),
14930 tCE(mvn, 1e00000, mvn, 2, (RR, SH), mov, t_mvn_tst),
14931 tC3(mvns, 1f00000, mvns, 2, (RR, SH), mov, t_mvn_tst),
14933 tCE(ldr, 4100000, ldr, 2, (RR, ADDRGLDR),ldst, t_ldst),
14934 tC3(ldrb, 4500000, ldrb, 2, (RR, ADDRGLDR),ldst, t_ldst),
14935 tCE(str, 4000000, str, 2, (RR, ADDRGLDR),ldst, t_ldst),
14936 tC3(strb, 4400000, strb, 2, (RR, ADDRGLDR),ldst, t_ldst),
14938 tCE(stm, 8800000, stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
14939 tC3(stmia, 8800000, stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
14940 tC3(stmea, 8800000, stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
14941 tCE(ldm, 8900000, ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
14942 tC3(ldmia, 8900000, ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
14943 tC3(ldmfd, 8900000, ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
14945 TCE(swi, f000000, df00, 1, (EXPi), swi, t_swi),
14946 TCE(svc, f000000, df00, 1, (EXPi), swi, t_swi),
14947 tCE(b, a000000, b, 1, (EXPr), branch, t_branch),
14948 TCE(bl, b000000, f000f800, 1, (EXPr), bl, t_branch23),
14951 tCE(adr, 28f0000, adr, 2, (RR, EXP), adr, t_adr),
14952 C3(adrl, 28f0000, 2, (RR, EXP), adrl),
14953 tCE(nop, 1a00000, nop, 1, (oI255c), nop, t_nop),
14955 /* Thumb-compatibility pseudo ops. */
14956 tCE(lsl, 1a00000, lsl, 3, (RR, oRR, SH), shift, t_shift),
14957 tC3(lsls, 1b00000, lsls, 3, (RR, oRR, SH), shift, t_shift),
14958 tCE(lsr, 1a00020, lsr, 3, (RR, oRR, SH), shift, t_shift),
14959 tC3(lsrs, 1b00020, lsrs, 3, (RR, oRR, SH), shift, t_shift),
14960 tCE(asr, 1a00040, asr, 3, (RR, oRR, SH), shift, t_shift),
14961 tC3(asrs, 1b00040, asrs, 3, (RR, oRR, SH), shift, t_shift),
14962 tCE(ror, 1a00060, ror, 3, (RR, oRR, SH), shift, t_shift),
14963 tC3(rors, 1b00060, rors, 3, (RR, oRR, SH), shift, t_shift),
14964 tCE(neg, 2600000, neg, 2, (RR, RR), rd_rn, t_neg),
14965 tC3(negs, 2700000, negs, 2, (RR, RR), rd_rn, t_neg),
14966 tCE(push, 92d0000, push, 1, (REGLST), push_pop, t_push_pop),
14967 tCE(pop, 8bd0000, pop, 1, (REGLST), push_pop, t_push_pop),
14969 /* These may simplify to neg. */
14970 TCE(rsb, 0600000, ebc00000, 3, (RR, oRR, SH), arit, t_rsb),
14971 TC3(rsbs, 0700000, ebd00000, 3, (RR, oRR, SH), arit, t_rsb),
14973 TCE(rrx, 1a00060, ea4f0030, 2, (RR, RR), rd_rm, t_rd_rm),
14974 TCE(rrxs, 1b00060, ea5f0030, 2, (RR, RR), rd_rm, t_rd_rm),
14976 #undef THUMB_VARIANT
14977 #define THUMB_VARIANT &arm_ext_v6
14978 TCE(cpy, 1a00000, 4600, 2, (RR, RR), rd_rm, t_cpy),
14980 /* V1 instructions with no Thumb analogue prior to V6T2. */
14981 #undef THUMB_VARIANT
14982 #define THUMB_VARIANT &arm_ext_v6t2
14983 TCE(teq, 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
14984 TC3w(teqs, 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
14985 CL(teqp, 130f000, 2, (RR, SH), cmp),
14987 TC3(ldrt, 4300000, f8500e00, 2, (RR, ADDR), ldstt, t_ldstt),
14988 TC3(ldrbt, 4700000, f8100e00, 2, (RR, ADDR), ldstt, t_ldstt),
14989 TC3(strt, 4200000, f8400e00, 2, (RR, ADDR), ldstt, t_ldstt),
14990 TC3(strbt, 4600000, f8000e00, 2, (RR, ADDR), ldstt, t_ldstt),
14992 TC3(stmdb, 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
14993 TC3(stmfd, 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
14995 TC3(ldmdb, 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
14996 TC3(ldmea, 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
14998 /* V1 instructions with no Thumb analogue at all. */
14999 CE(rsc, 0e00000, 3, (RR, oRR, SH), arit),
15000 C3(rscs, 0f00000, 3, (RR, oRR, SH), arit),
15002 C3(stmib, 9800000, 2, (RRw, REGLST), ldmstm),
15003 C3(stmfa, 9800000, 2, (RRw, REGLST), ldmstm),
15004 C3(stmda, 8000000, 2, (RRw, REGLST), ldmstm),
15005 C3(stmed, 8000000, 2, (RRw, REGLST), ldmstm),
15006 C3(ldmib, 9900000, 2, (RRw, REGLST), ldmstm),
15007 C3(ldmed, 9900000, 2, (RRw, REGLST), ldmstm),
15008 C3(ldmda, 8100000, 2, (RRw, REGLST), ldmstm),
15009 C3(ldmfa, 8100000, 2, (RRw, REGLST), ldmstm),
15012 #define ARM_VARIANT &arm_ext_v2 /* ARM 2 - multiplies. */
15013 #undef THUMB_VARIANT
15014 #define THUMB_VARIANT &arm_ext_v4t
15015 tCE(mul, 0000090, mul, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
15016 tC3(muls, 0100090, muls, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
15018 #undef THUMB_VARIANT
15019 #define THUMB_VARIANT &arm_ext_v6t2
15020 TCE(mla, 0200090, fb000000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
15021 C3(mlas, 0300090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas),
15023 /* Generic coprocessor instructions. */
15024 TCE(cdp, e000000, ee000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
15025 TCE(ldc, c100000, ec100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
15026 TC3(ldcl, c500000, ec500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
15027 TCE(stc, c000000, ec000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
15028 TC3(stcl, c400000, ec400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
15029 TCE(mcr, e000010, ee000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
15030 TCE(mrc, e100010, ee100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
15033 #define ARM_VARIANT &arm_ext_v2s /* ARM 3 - swp instructions. */
15034 CE(swp, 1000090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
15035 C3(swpb, 1400090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
15038 #define ARM_VARIANT &arm_ext_v3 /* ARM 6 Status register instructions. */
15039 TCE(mrs, 10f0000, f3ef8000, 2, (APSR_RR, RVC_PSR), mrs, t_mrs),
15040 TCE(msr, 120f000, f3808000, 2, (RVC_PSR, RR_EXi), msr, t_msr),
15043 #define ARM_VARIANT &arm_ext_v3m /* ARM 7M long multiplies. */
15044 TCE(smull, 0c00090, fb800000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
15045 CM(smull,s, 0d00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
15046 TCE(umull, 0800090, fba00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
15047 CM(umull,s, 0900090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
15048 TCE(smlal, 0e00090, fbc00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
15049 CM(smlal,s, 0f00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
15050 TCE(umlal, 0a00090, fbe00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
15051 CM(umlal,s, 0b00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
15054 #define ARM_VARIANT &arm_ext_v4 /* ARM Architecture 4. */
15055 #undef THUMB_VARIANT
15056 #define THUMB_VARIANT &arm_ext_v4t
15057 tC3(ldrh, 01000b0, ldrh, 2, (RR, ADDRGLDRS), ldstv4, t_ldst),
15058 tC3(strh, 00000b0, strh, 2, (RR, ADDRGLDRS), ldstv4, t_ldst),
15059 tC3(ldrsh, 01000f0, ldrsh, 2, (RR, ADDRGLDRS), ldstv4, t_ldst),
15060 tC3(ldrsb, 01000d0, ldrsb, 2, (RR, ADDRGLDRS), ldstv4, t_ldst),
15061 tCM(ld,sh, 01000f0, ldrsh, 2, (RR, ADDRGLDRS), ldstv4, t_ldst),
15062 tCM(ld,sb, 01000d0, ldrsb, 2, (RR, ADDRGLDRS), ldstv4, t_ldst),
15065 #define ARM_VARIANT &arm_ext_v4t_5
15066 /* ARM Architecture 4T. */
15067 /* Note: bx (and blx) are required on V5, even if the processor does
15068 not support Thumb. */
15069 TCE(bx, 12fff10, 4700, 1, (RR), bx, t_bx),
15072 #define ARM_VARIANT &arm_ext_v5 /* ARM Architecture 5T. */
15073 #undef THUMB_VARIANT
15074 #define THUMB_VARIANT &arm_ext_v5t
15075 /* Note: blx has 2 variants; the .value coded here is for
15076 BLX(2). Only this variant has conditional execution. */
15077 TCE(blx, 12fff30, 4780, 1, (RR_EXr), blx, t_blx),
15078 TUE(bkpt, 1200070, be00, 1, (oIffffb), bkpt, t_bkpt),
15080 #undef THUMB_VARIANT
15081 #define THUMB_VARIANT &arm_ext_v6t2
15082 TCE(clz, 16f0f10, fab0f080, 2, (RRnpc, RRnpc), rd_rm, t_clz),
15083 TUF(ldc2, c100000, fc100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
15084 TUF(ldc2l, c500000, fc500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
15085 TUF(stc2, c000000, fc000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
15086 TUF(stc2l, c400000, fc400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
15087 TUF(cdp2, e000000, fe000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
15088 TUF(mcr2, e000010, fe000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
15089 TUF(mrc2, e100010, fe100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
15092 #define ARM_VARIANT &arm_ext_v5exp /* ARM Architecture 5TExP. */
15093 TCE(smlabb, 1000080, fb100000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
15094 TCE(smlatb, 10000a0, fb100020, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
15095 TCE(smlabt, 10000c0, fb100010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
15096 TCE(smlatt, 10000e0, fb100030, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
15098 TCE(smlawb, 1200080, fb300000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
15099 TCE(smlawt, 12000c0, fb300010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
15101 TCE(smlalbb, 1400080, fbc00080, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
15102 TCE(smlaltb, 14000a0, fbc000a0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
15103 TCE(smlalbt, 14000c0, fbc00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
15104 TCE(smlaltt, 14000e0, fbc000b0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
15106 TCE(smulbb, 1600080, fb10f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
15107 TCE(smultb, 16000a0, fb10f020, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
15108 TCE(smulbt, 16000c0, fb10f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
15109 TCE(smultt, 16000e0, fb10f030, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
15111 TCE(smulwb, 12000a0, fb30f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
15112 TCE(smulwt, 12000e0, fb30f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
15114 TCE(qadd, 1000050, fa80f080, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn),
15115 TCE(qdadd, 1400050, fa80f090, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn),
15116 TCE(qsub, 1200050, fa80f0a0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn),
15117 TCE(qdsub, 1600050, fa80f0b0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn),
15120 #define ARM_VARIANT &arm_ext_v5e /* ARM Architecture 5TE. */
15121 TUF(pld, 450f000, f810f000, 1, (ADDR), pld, t_pld),
15122 TC3(ldrd, 00000d0, e8500000, 3, (RRnpc, oRRnpc, ADDRGLDRS), ldrd, t_ldstd),
15123 TC3(strd, 00000f0, e8400000, 3, (RRnpc, oRRnpc, ADDRGLDRS), ldrd, t_ldstd),
15125 TCE(mcrr, c400000, ec400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
15126 TCE(mrrc, c500000, ec500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
15129 #define ARM_VARIANT &arm_ext_v5j /* ARM Architecture 5TEJ. */
15130 TCE(bxj, 12fff20, f3c08f00, 1, (RR), bxj, t_bxj),
15133 #define ARM_VARIANT &arm_ext_v6 /* ARM V6. */
15134 #undef THUMB_VARIANT
15135 #define THUMB_VARIANT &arm_ext_v6
15136 TUF(cpsie, 1080000, b660, 2, (CPSF, oI31b), cpsi, t_cpsi),
15137 TUF(cpsid, 10c0000, b670, 2, (CPSF, oI31b), cpsi, t_cpsi),
15138 tCE(rev, 6bf0f30, rev, 2, (RRnpc, RRnpc), rd_rm, t_rev),
15139 tCE(rev16, 6bf0fb0, rev16, 2, (RRnpc, RRnpc), rd_rm, t_rev),
15140 tCE(revsh, 6ff0fb0, revsh, 2, (RRnpc, RRnpc), rd_rm, t_rev),
15141 tCE(sxth, 6bf0070, sxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
15142 tCE(uxth, 6ff0070, uxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
15143 tCE(sxtb, 6af0070, sxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
15144 tCE(uxtb, 6ef0070, uxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
15145 TUF(setend, 1010000, b650, 1, (ENDI), setend, t_setend),
15147 #undef THUMB_VARIANT
15148 #define THUMB_VARIANT &arm_ext_v6t2
15149 TCE(ldrex, 1900f9f, e8500f00, 2, (RRnpc, ADDR), ldrex, t_ldrex),
15150 TCE(strex, 1800f90, e8400000, 3, (RRnpc, RRnpc, ADDR), strex, t_strex),
15151 TUF(mcrr2, c400000, fc400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
15152 TUF(mrrc2, c500000, fc500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
15154 TCE(ssat, 6a00010, f3000000, 4, (RRnpc, I32, RRnpc, oSHllar),ssat, t_ssat),
15155 TCE(usat, 6e00010, f3800000, 4, (RRnpc, I31, RRnpc, oSHllar),usat, t_usat),
15157 /* ARM V6 not included in V7M (eg. integer SIMD). */
15158 #undef THUMB_VARIANT
15159 #define THUMB_VARIANT &arm_ext_v6_notm
15160 TUF(cps, 1020000, f3af8100, 1, (I31b), imm0, t_cps),
15161 TCE(pkhbt, 6800010, eac00000, 4, (RRnpc, RRnpc, RRnpc, oSHll), pkhbt, t_pkhbt),
15162 TCE(pkhtb, 6800050, eac00020, 4, (RRnpc, RRnpc, RRnpc, oSHar), pkhtb, t_pkhtb),
15163 TCE(qadd16, 6200f10, fa90f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15164 TCE(qadd8, 6200f90, fa80f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15165 TCE(qaddsubx, 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15166 TCE(qsub16, 6200f70, fad0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15167 TCE(qsub8, 6200ff0, fac0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15168 TCE(qsubaddx, 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15169 TCE(sadd16, 6100f10, fa90f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15170 TCE(sadd8, 6100f90, fa80f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15171 TCE(saddsubx, 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15172 TCE(shadd16, 6300f10, fa90f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15173 TCE(shadd8, 6300f90, fa80f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15174 TCE(shaddsubx, 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15175 TCE(shsub16, 6300f70, fad0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15176 TCE(shsub8, 6300ff0, fac0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15177 TCE(shsubaddx, 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15178 TCE(ssub16, 6100f70, fad0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15179 TCE(ssub8, 6100ff0, fac0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15180 TCE(ssubaddx, 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15181 TCE(uadd16, 6500f10, fa90f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15182 TCE(uadd8, 6500f90, fa80f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15183 TCE(uaddsubx, 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15184 TCE(uhadd16, 6700f10, fa90f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15185 TCE(uhadd8, 6700f90, fa80f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15186 TCE(uhaddsubx, 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15187 TCE(uhsub16, 6700f70, fad0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15188 TCE(uhsub8, 6700ff0, fac0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15189 TCE(uhsubaddx, 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15190 TCE(uqadd16, 6600f10, fa90f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15191 TCE(uqadd8, 6600f90, fa80f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15192 TCE(uqaddsubx, 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15193 TCE(uqsub16, 6600f70, fad0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15194 TCE(uqsub8, 6600ff0, fac0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15195 TCE(uqsubaddx, 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15196 TCE(usub16, 6500f70, fad0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15197 TCE(usub8, 6500ff0, fac0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15198 TCE(usubaddx, 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15199 TUF(rfeia, 8900a00, e990c000, 1, (RRw), rfe, rfe),
15200 UF(rfeib, 9900a00, 1, (RRw), rfe),
15201 UF(rfeda, 8100a00, 1, (RRw), rfe),
15202 TUF(rfedb, 9100a00, e810c000, 1, (RRw), rfe, rfe),
15203 TUF(rfefd, 8900a00, e990c000, 1, (RRw), rfe, rfe),
15204 UF(rfefa, 9900a00, 1, (RRw), rfe),
15205 UF(rfeea, 8100a00, 1, (RRw), rfe),
15206 TUF(rfeed, 9100a00, e810c000, 1, (RRw), rfe, rfe),
15207 TCE(sxtah, 6b00070, fa00f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
15208 TCE(sxtab16, 6800070, fa20f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
15209 TCE(sxtab, 6a00070, fa40f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
15210 TCE(sxtb16, 68f0070, fa2ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
15211 TCE(uxtah, 6f00070, fa10f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
15212 TCE(uxtab16, 6c00070, fa30f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
15213 TCE(uxtab, 6e00070, fa50f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
15214 TCE(uxtb16, 6cf0070, fa3ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
15215 TCE(sel, 6800fb0, faa0f080, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
15216 TCE(smlad, 7000010, fb200000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
15217 TCE(smladx, 7000030, fb200010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
15218 TCE(smlald, 7400010, fbc000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
15219 TCE(smlaldx, 7400030, fbc000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
15220 TCE(smlsd, 7000050, fb400000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
15221 TCE(smlsdx, 7000070, fb400010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
15222 TCE(smlsld, 7400050, fbd000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
15223 TCE(smlsldx, 7400070, fbd000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
15224 TCE(smmla, 7500010, fb500000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
15225 TCE(smmlar, 7500030, fb500010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
15226 TCE(smmls, 75000d0, fb600000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
15227 TCE(smmlsr, 75000f0, fb600010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
15228 TCE(smmul, 750f010, fb50f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
15229 TCE(smmulr, 750f030, fb50f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
15230 TCE(smuad, 700f010, fb20f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
15231 TCE(smuadx, 700f030, fb20f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
15232 TCE(smusd, 700f050, fb40f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
15233 TCE(smusdx, 700f070, fb40f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
15234 TUF(srsia, 8c00500, e980c000, 2, (oRRw, I31w), srs, srs),
15235 UF(srsib, 9c00500, 2, (oRRw, I31w), srs),
15236 UF(srsda, 8400500, 2, (oRRw, I31w), srs),
15237 TUF(srsdb, 9400500, e800c000, 2, (oRRw, I31w), srs, srs),
15238 TCE(ssat16, 6a00f30, f3200000, 3, (RRnpc, I16, RRnpc), ssat16, t_ssat16),
15239 TCE(umaal, 0400090, fbe00060, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal, t_mlal),
15240 TCE(usad8, 780f010, fb70f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
15241 TCE(usada8, 7800010, fb700000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
15242 TCE(usat16, 6e00f30, f3a00000, 3, (RRnpc, I15, RRnpc), usat16, t_usat16),
15245 #define ARM_VARIANT &arm_ext_v6k
15246 #undef THUMB_VARIANT
15247 #define THUMB_VARIANT &arm_ext_v6k
15248 tCE(yield, 320f001, yield, 0, (), noargs, t_hint),
15249 tCE(wfe, 320f002, wfe, 0, (), noargs, t_hint),
15250 tCE(wfi, 320f003, wfi, 0, (), noargs, t_hint),
15251 tCE(sev, 320f004, sev, 0, (), noargs, t_hint),
15253 #undef THUMB_VARIANT
15254 #define THUMB_VARIANT &arm_ext_v6_notm
15255 TCE(ldrexd, 1b00f9f, e8d0007f, 3, (RRnpc, oRRnpc, RRnpcb), ldrexd, t_ldrexd),
15256 TCE(strexd, 1a00f90, e8c00070, 4, (RRnpc, RRnpc, oRRnpc, RRnpcb), strexd, t_strexd),
15258 #undef THUMB_VARIANT
15259 #define THUMB_VARIANT &arm_ext_v6t2
15260 TCE(ldrexb, 1d00f9f, e8d00f4f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
15261 TCE(ldrexh, 1f00f9f, e8d00f5f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
15262 TCE(strexb, 1c00f90, e8c00f40, 3, (RRnpc, RRnpc, ADDR), strex, rm_rd_rn),
15263 TCE(strexh, 1e00f90, e8c00f50, 3, (RRnpc, RRnpc, ADDR), strex, rm_rd_rn),
15264 TUF(clrex, 57ff01f, f3bf8f2f, 0, (), noargs, noargs),
15267 #define ARM_VARIANT &arm_ext_v6z
15268 TCE(smc, 1600070, f7f08000, 1, (EXPi), smc, t_smc),
15271 #define ARM_VARIANT &arm_ext_v6t2
15272 TCE(bfc, 7c0001f, f36f0000, 3, (RRnpc, I31, I32), bfc, t_bfc),
15273 TCE(bfi, 7c00010, f3600000, 4, (RRnpc, RRnpc_I0, I31, I32), bfi, t_bfi),
15274 TCE(sbfx, 7a00050, f3400000, 4, (RR, RR, I31, I32), bfx, t_bfx),
15275 TCE(ubfx, 7e00050, f3c00000, 4, (RR, RR, I31, I32), bfx, t_bfx),
15277 TCE(mls, 0600090, fb000010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
15278 TCE(movw, 3000000, f2400000, 2, (RRnpc, HALF), mov16, t_mov16),
15279 TCE(movt, 3400000, f2c00000, 2, (RRnpc, HALF), mov16, t_mov16),
15280 TCE(rbit, 6ff0f30, fa90f0a0, 2, (RR, RR), rd_rm, t_rbit),
15282 TC3(ldrht, 03000b0, f8300e00, 2, (RR, ADDR), ldsttv4, t_ldstt),
15283 TC3(ldrsht, 03000f0, f9300e00, 2, (RR, ADDR), ldsttv4, t_ldstt),
15284 TC3(ldrsbt, 03000d0, f9100e00, 2, (RR, ADDR), ldsttv4, t_ldstt),
15285 TC3(strht, 02000b0, f8200e00, 2, (RR, ADDR), ldsttv4, t_ldstt),
15287 UT(cbnz, b900, 2, (RR, EXP), t_cbz),
15288 UT(cbz, b100, 2, (RR, EXP), t_cbz),
15289 /* ARM does not really have an IT instruction, so always allow it. */
15291 #define ARM_VARIANT &arm_ext_v1
15292 TUE(it, 0, bf08, 1, (COND), it, t_it),
15293 TUE(itt, 0, bf0c, 1, (COND), it, t_it),
15294 TUE(ite, 0, bf04, 1, (COND), it, t_it),
15295 TUE(ittt, 0, bf0e, 1, (COND), it, t_it),
15296 TUE(itet, 0, bf06, 1, (COND), it, t_it),
15297 TUE(itte, 0, bf0a, 1, (COND), it, t_it),
15298 TUE(itee, 0, bf02, 1, (COND), it, t_it),
15299 TUE(itttt, 0, bf0f, 1, (COND), it, t_it),
15300 TUE(itett, 0, bf07, 1, (COND), it, t_it),
15301 TUE(ittet, 0, bf0b, 1, (COND), it, t_it),
15302 TUE(iteet, 0, bf03, 1, (COND), it, t_it),
15303 TUE(ittte, 0, bf0d, 1, (COND), it, t_it),
15304 TUE(itete, 0, bf05, 1, (COND), it, t_it),
15305 TUE(ittee, 0, bf09, 1, (COND), it, t_it),
15306 TUE(iteee, 0, bf01, 1, (COND), it, t_it),
15308 /* Thumb2 only instructions. */
15310 #define ARM_VARIANT NULL
15312 TCE(addw, 0, f2000000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
15313 TCE(subw, 0, f2a00000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
15314 TCE(tbb, 0, e8d0f000, 1, (TB), 0, t_tb),
15315 TCE(tbh, 0, e8d0f010, 1, (TB), 0, t_tb),
15317 /* Thumb-2 hardware division instructions (R and M profiles only). */
15318 #undef THUMB_VARIANT
15319 #define THUMB_VARIANT &arm_ext_div
15320 TCE(sdiv, 0, fb90f0f0, 3, (RR, oRR, RR), 0, t_div),
15321 TCE(udiv, 0, fbb0f0f0, 3, (RR, oRR, RR), 0, t_div),
15323 /* ARM V7 instructions. */
15325 #define ARM_VARIANT &arm_ext_v7
15326 #undef THUMB_VARIANT
15327 #define THUMB_VARIANT &arm_ext_v7
15328 TUF(pli, 450f000, f910f000, 1, (ADDR), pli, t_pld),
15329 TCE(dbg, 320f0f0, f3af80f0, 1, (I15), dbg, t_dbg),
15330 TUF(dmb, 57ff050, f3bf8f50, 1, (oBARRIER), barrier, t_barrier),
15331 TUF(dsb, 57ff040, f3bf8f40, 1, (oBARRIER), barrier, t_barrier),
15332 TUF(isb, 57ff060, f3bf8f60, 1, (oBARRIER), barrier, t_barrier),
15335 #define ARM_VARIANT &fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
15336 cCE(wfs, e200110, 1, (RR), rd),
15337 cCE(rfs, e300110, 1, (RR), rd),
15338 cCE(wfc, e400110, 1, (RR), rd),
15339 cCE(rfc, e500110, 1, (RR), rd),
15341 cCL(ldfs, c100100, 2, (RF, ADDRGLDC), rd_cpaddr),
15342 cCL(ldfd, c108100, 2, (RF, ADDRGLDC), rd_cpaddr),
15343 cCL(ldfe, c500100, 2, (RF, ADDRGLDC), rd_cpaddr),
15344 cCL(ldfp, c508100, 2, (RF, ADDRGLDC), rd_cpaddr),
15346 cCL(stfs, c000100, 2, (RF, ADDRGLDC), rd_cpaddr),
15347 cCL(stfd, c008100, 2, (RF, ADDRGLDC), rd_cpaddr),
15348 cCL(stfe, c400100, 2, (RF, ADDRGLDC), rd_cpaddr),
15349 cCL(stfp, c408100, 2, (RF, ADDRGLDC), rd_cpaddr),
15351 cCL(mvfs, e008100, 2, (RF, RF_IF), rd_rm),
15352 cCL(mvfsp, e008120, 2, (RF, RF_IF), rd_rm),
15353 cCL(mvfsm, e008140, 2, (RF, RF_IF), rd_rm),
15354 cCL(mvfsz, e008160, 2, (RF, RF_IF), rd_rm),
15355 cCL(mvfd, e008180, 2, (RF, RF_IF), rd_rm),
15356 cCL(mvfdp, e0081a0, 2, (RF, RF_IF), rd_rm),
15357 cCL(mvfdm, e0081c0, 2, (RF, RF_IF), rd_rm),
15358 cCL(mvfdz, e0081e0, 2, (RF, RF_IF), rd_rm),
15359 cCL(mvfe, e088100, 2, (RF, RF_IF), rd_rm),
15360 cCL(mvfep, e088120, 2, (RF, RF_IF), rd_rm),
15361 cCL(mvfem, e088140, 2, (RF, RF_IF), rd_rm),
15362 cCL(mvfez, e088160, 2, (RF, RF_IF), rd_rm),
15364 cCL(mnfs, e108100, 2, (RF, RF_IF), rd_rm),
15365 cCL(mnfsp, e108120, 2, (RF, RF_IF), rd_rm),
15366 cCL(mnfsm, e108140, 2, (RF, RF_IF), rd_rm),
15367 cCL(mnfsz, e108160, 2, (RF, RF_IF), rd_rm),
15368 cCL(mnfd, e108180, 2, (RF, RF_IF), rd_rm),
15369 cCL(mnfdp, e1081a0, 2, (RF, RF_IF), rd_rm),
15370 cCL(mnfdm, e1081c0, 2, (RF, RF_IF), rd_rm),
15371 cCL(mnfdz, e1081e0, 2, (RF, RF_IF), rd_rm),
15372 cCL(mnfe, e188100, 2, (RF, RF_IF), rd_rm),
15373 cCL(mnfep, e188120, 2, (RF, RF_IF), rd_rm),
15374 cCL(mnfem, e188140, 2, (RF, RF_IF), rd_rm),
15375 cCL(mnfez, e188160, 2, (RF, RF_IF), rd_rm),
15377 cCL(abss, e208100, 2, (RF, RF_IF), rd_rm),
15378 cCL(abssp, e208120, 2, (RF, RF_IF), rd_rm),
15379 cCL(abssm, e208140, 2, (RF, RF_IF), rd_rm),
15380 cCL(abssz, e208160, 2, (RF, RF_IF), rd_rm),
15381 cCL(absd, e208180, 2, (RF, RF_IF), rd_rm),
15382 cCL(absdp, e2081a0, 2, (RF, RF_IF), rd_rm),
15383 cCL(absdm, e2081c0, 2, (RF, RF_IF), rd_rm),
15384 cCL(absdz, e2081e0, 2, (RF, RF_IF), rd_rm),
15385 cCL(abse, e288100, 2, (RF, RF_IF), rd_rm),
15386 cCL(absep, e288120, 2, (RF, RF_IF), rd_rm),
15387 cCL(absem, e288140, 2, (RF, RF_IF), rd_rm),
15388 cCL(absez, e288160, 2, (RF, RF_IF), rd_rm),
15390 cCL(rnds, e308100, 2, (RF, RF_IF), rd_rm),
15391 cCL(rndsp, e308120, 2, (RF, RF_IF), rd_rm),
15392 cCL(rndsm, e308140, 2, (RF, RF_IF), rd_rm),
15393 cCL(rndsz, e308160, 2, (RF, RF_IF), rd_rm),
15394 cCL(rndd, e308180, 2, (RF, RF_IF), rd_rm),
15395 cCL(rnddp, e3081a0, 2, (RF, RF_IF), rd_rm),
15396 cCL(rnddm, e3081c0, 2, (RF, RF_IF), rd_rm),
15397 cCL(rnddz, e3081e0, 2, (RF, RF_IF), rd_rm),
15398 cCL(rnde, e388100, 2, (RF, RF_IF), rd_rm),
15399 cCL(rndep, e388120, 2, (RF, RF_IF), rd_rm),
15400 cCL(rndem, e388140, 2, (RF, RF_IF), rd_rm),
15401 cCL(rndez, e388160, 2, (RF, RF_IF), rd_rm),
15403 cCL(sqts, e408100, 2, (RF, RF_IF), rd_rm),
15404 cCL(sqtsp, e408120, 2, (RF, RF_IF), rd_rm),
15405 cCL(sqtsm, e408140, 2, (RF, RF_IF), rd_rm),
15406 cCL(sqtsz, e408160, 2, (RF, RF_IF), rd_rm),
15407 cCL(sqtd, e408180, 2, (RF, RF_IF), rd_rm),
15408 cCL(sqtdp, e4081a0, 2, (RF, RF_IF), rd_rm),
15409 cCL(sqtdm, e4081c0, 2, (RF, RF_IF), rd_rm),
15410 cCL(sqtdz, e4081e0, 2, (RF, RF_IF), rd_rm),
15411 cCL(sqte, e488100, 2, (RF, RF_IF), rd_rm),
15412 cCL(sqtep, e488120, 2, (RF, RF_IF), rd_rm),
15413 cCL(sqtem, e488140, 2, (RF, RF_IF), rd_rm),
15414 cCL(sqtez, e488160, 2, (RF, RF_IF), rd_rm),
15416 cCL(logs, e508100, 2, (RF, RF_IF), rd_rm),
15417 cCL(logsp, e508120, 2, (RF, RF_IF), rd_rm),
15418 cCL(logsm, e508140, 2, (RF, RF_IF), rd_rm),
15419 cCL(logsz, e508160, 2, (RF, RF_IF), rd_rm),
15420 cCL(logd, e508180, 2, (RF, RF_IF), rd_rm),
15421 cCL(logdp, e5081a0, 2, (RF, RF_IF), rd_rm),
15422 cCL(logdm, e5081c0, 2, (RF, RF_IF), rd_rm),
15423 cCL(logdz, e5081e0, 2, (RF, RF_IF), rd_rm),
15424 cCL(loge, e588100, 2, (RF, RF_IF), rd_rm),
15425 cCL(logep, e588120, 2, (RF, RF_IF), rd_rm),
15426 cCL(logem, e588140, 2, (RF, RF_IF), rd_rm),
15427 cCL(logez, e588160, 2, (RF, RF_IF), rd_rm),
15429 cCL(lgns, e608100, 2, (RF, RF_IF), rd_rm),
15430 cCL(lgnsp, e608120, 2, (RF, RF_IF), rd_rm),
15431 cCL(lgnsm, e608140, 2, (RF, RF_IF), rd_rm),
15432 cCL(lgnsz, e608160, 2, (RF, RF_IF), rd_rm),
15433 cCL(lgnd, e608180, 2, (RF, RF_IF), rd_rm),
15434 cCL(lgndp, e6081a0, 2, (RF, RF_IF), rd_rm),
15435 cCL(lgndm, e6081c0, 2, (RF, RF_IF), rd_rm),
15436 cCL(lgndz, e6081e0, 2, (RF, RF_IF), rd_rm),
15437 cCL(lgne, e688100, 2, (RF, RF_IF), rd_rm),
15438 cCL(lgnep, e688120, 2, (RF, RF_IF), rd_rm),
15439 cCL(lgnem, e688140, 2, (RF, RF_IF), rd_rm),
15440 cCL(lgnez, e688160, 2, (RF, RF_IF), rd_rm),
15442 cCL(exps, e708100, 2, (RF, RF_IF), rd_rm),
15443 cCL(expsp, e708120, 2, (RF, RF_IF), rd_rm),
15444 cCL(expsm, e708140, 2, (RF, RF_IF), rd_rm),
15445 cCL(expsz, e708160, 2, (RF, RF_IF), rd_rm),
15446 cCL(expd, e708180, 2, (RF, RF_IF), rd_rm),
15447 cCL(expdp, e7081a0, 2, (RF, RF_IF), rd_rm),
15448 cCL(expdm, e7081c0, 2, (RF, RF_IF), rd_rm),
15449 cCL(expdz, e7081e0, 2, (RF, RF_IF), rd_rm),
15450 cCL(expe, e788100, 2, (RF, RF_IF), rd_rm),
15451 cCL(expep, e788120, 2, (RF, RF_IF), rd_rm),
15452 cCL(expem, e788140, 2, (RF, RF_IF), rd_rm),
15453 cCL(expdz, e788160, 2, (RF, RF_IF), rd_rm),
15455 cCL(sins, e808100, 2, (RF, RF_IF), rd_rm),
15456 cCL(sinsp, e808120, 2, (RF, RF_IF), rd_rm),
15457 cCL(sinsm, e808140, 2, (RF, RF_IF), rd_rm),
15458 cCL(sinsz, e808160, 2, (RF, RF_IF), rd_rm),
15459 cCL(sind, e808180, 2, (RF, RF_IF), rd_rm),
15460 cCL(sindp, e8081a0, 2, (RF, RF_IF), rd_rm),
15461 cCL(sindm, e8081c0, 2, (RF, RF_IF), rd_rm),
15462 cCL(sindz, e8081e0, 2, (RF, RF_IF), rd_rm),
15463 cCL(sine, e888100, 2, (RF, RF_IF), rd_rm),
15464 cCL(sinep, e888120, 2, (RF, RF_IF), rd_rm),
15465 cCL(sinem, e888140, 2, (RF, RF_IF), rd_rm),
15466 cCL(sinez, e888160, 2, (RF, RF_IF), rd_rm),
15468 cCL(coss, e908100, 2, (RF, RF_IF), rd_rm),
15469 cCL(cossp, e908120, 2, (RF, RF_IF), rd_rm),
15470 cCL(cossm, e908140, 2, (RF, RF_IF), rd_rm),
15471 cCL(cossz, e908160, 2, (RF, RF_IF), rd_rm),
15472 cCL(cosd, e908180, 2, (RF, RF_IF), rd_rm),
15473 cCL(cosdp, e9081a0, 2, (RF, RF_IF), rd_rm),
15474 cCL(cosdm, e9081c0, 2, (RF, RF_IF), rd_rm),
15475 cCL(cosdz, e9081e0, 2, (RF, RF_IF), rd_rm),
15476 cCL(cose, e988100, 2, (RF, RF_IF), rd_rm),
15477 cCL(cosep, e988120, 2, (RF, RF_IF), rd_rm),
15478 cCL(cosem, e988140, 2, (RF, RF_IF), rd_rm),
15479 cCL(cosez, e988160, 2, (RF, RF_IF), rd_rm),
15481 cCL(tans, ea08100, 2, (RF, RF_IF), rd_rm),
15482 cCL(tansp, ea08120, 2, (RF, RF_IF), rd_rm),
15483 cCL(tansm, ea08140, 2, (RF, RF_IF), rd_rm),
15484 cCL(tansz, ea08160, 2, (RF, RF_IF), rd_rm),
15485 cCL(tand, ea08180, 2, (RF, RF_IF), rd_rm),
15486 cCL(tandp, ea081a0, 2, (RF, RF_IF), rd_rm),
15487 cCL(tandm, ea081c0, 2, (RF, RF_IF), rd_rm),
15488 cCL(tandz, ea081e0, 2, (RF, RF_IF), rd_rm),
15489 cCL(tane, ea88100, 2, (RF, RF_IF), rd_rm),
15490 cCL(tanep, ea88120, 2, (RF, RF_IF), rd_rm),
15491 cCL(tanem, ea88140, 2, (RF, RF_IF), rd_rm),
15492 cCL(tanez, ea88160, 2, (RF, RF_IF), rd_rm),
15494 cCL(asns, eb08100, 2, (RF, RF_IF), rd_rm),
15495 cCL(asnsp, eb08120, 2, (RF, RF_IF), rd_rm),
15496 cCL(asnsm, eb08140, 2, (RF, RF_IF), rd_rm),
15497 cCL(asnsz, eb08160, 2, (RF, RF_IF), rd_rm),
15498 cCL(asnd, eb08180, 2, (RF, RF_IF), rd_rm),
15499 cCL(asndp, eb081a0, 2, (RF, RF_IF), rd_rm),
15500 cCL(asndm, eb081c0, 2, (RF, RF_IF), rd_rm),
15501 cCL(asndz, eb081e0, 2, (RF, RF_IF), rd_rm),
15502 cCL(asne, eb88100, 2, (RF, RF_IF), rd_rm),
15503 cCL(asnep, eb88120, 2, (RF, RF_IF), rd_rm),
15504 cCL(asnem, eb88140, 2, (RF, RF_IF), rd_rm),
15505 cCL(asnez, eb88160, 2, (RF, RF_IF), rd_rm),
15507 cCL(acss, ec08100, 2, (RF, RF_IF), rd_rm),
15508 cCL(acssp, ec08120, 2, (RF, RF_IF), rd_rm),
15509 cCL(acssm, ec08140, 2, (RF, RF_IF), rd_rm),
15510 cCL(acssz, ec08160, 2, (RF, RF_IF), rd_rm),
15511 cCL(acsd, ec08180, 2, (RF, RF_IF), rd_rm),
15512 cCL(acsdp, ec081a0, 2, (RF, RF_IF), rd_rm),
15513 cCL(acsdm, ec081c0, 2, (RF, RF_IF), rd_rm),
15514 cCL(acsdz, ec081e0, 2, (RF, RF_IF), rd_rm),
15515 cCL(acse, ec88100, 2, (RF, RF_IF), rd_rm),
15516 cCL(acsep, ec88120, 2, (RF, RF_IF), rd_rm),
15517 cCL(acsem, ec88140, 2, (RF, RF_IF), rd_rm),
15518 cCL(acsez, ec88160, 2, (RF, RF_IF), rd_rm),
15520 cCL(atns, ed08100, 2, (RF, RF_IF), rd_rm),
15521 cCL(atnsp, ed08120, 2, (RF, RF_IF), rd_rm),
15522 cCL(atnsm, ed08140, 2, (RF, RF_IF), rd_rm),
15523 cCL(atnsz, ed08160, 2, (RF, RF_IF), rd_rm),
15524 cCL(atnd, ed08180, 2, (RF, RF_IF), rd_rm),
15525 cCL(atndp, ed081a0, 2, (RF, RF_IF), rd_rm),
15526 cCL(atndm, ed081c0, 2, (RF, RF_IF), rd_rm),
15527 cCL(atndz, ed081e0, 2, (RF, RF_IF), rd_rm),
15528 cCL(atne, ed88100, 2, (RF, RF_IF), rd_rm),
15529 cCL(atnep, ed88120, 2, (RF, RF_IF), rd_rm),
15530 cCL(atnem, ed88140, 2, (RF, RF_IF), rd_rm),
15531 cCL(atnez, ed88160, 2, (RF, RF_IF), rd_rm),
15533 cCL(urds, ee08100, 2, (RF, RF_IF), rd_rm),
15534 cCL(urdsp, ee08120, 2, (RF, RF_IF), rd_rm),
15535 cCL(urdsm, ee08140, 2, (RF, RF_IF), rd_rm),
15536 cCL(urdsz, ee08160, 2, (RF, RF_IF), rd_rm),
15537 cCL(urdd, ee08180, 2, (RF, RF_IF), rd_rm),
15538 cCL(urddp, ee081a0, 2, (RF, RF_IF), rd_rm),
15539 cCL(urddm, ee081c0, 2, (RF, RF_IF), rd_rm),
15540 cCL(urddz, ee081e0, 2, (RF, RF_IF), rd_rm),
15541 cCL(urde, ee88100, 2, (RF, RF_IF), rd_rm),
15542 cCL(urdep, ee88120, 2, (RF, RF_IF), rd_rm),
15543 cCL(urdem, ee88140, 2, (RF, RF_IF), rd_rm),
15544 cCL(urdez, ee88160, 2, (RF, RF_IF), rd_rm),
15546 cCL(nrms, ef08100, 2, (RF, RF_IF), rd_rm),
15547 cCL(nrmsp, ef08120, 2, (RF, RF_IF), rd_rm),
15548 cCL(nrmsm, ef08140, 2, (RF, RF_IF), rd_rm),
15549 cCL(nrmsz, ef08160, 2, (RF, RF_IF), rd_rm),
15550 cCL(nrmd, ef08180, 2, (RF, RF_IF), rd_rm),
15551 cCL(nrmdp, ef081a0, 2, (RF, RF_IF), rd_rm),
15552 cCL(nrmdm, ef081c0, 2, (RF, RF_IF), rd_rm),
15553 cCL(nrmdz, ef081e0, 2, (RF, RF_IF), rd_rm),
15554 cCL(nrme, ef88100, 2, (RF, RF_IF), rd_rm),
15555 cCL(nrmep, ef88120, 2, (RF, RF_IF), rd_rm),
15556 cCL(nrmem, ef88140, 2, (RF, RF_IF), rd_rm),
15557 cCL(nrmez, ef88160, 2, (RF, RF_IF), rd_rm),
15559 cCL(adfs, e000100, 3, (RF, RF, RF_IF), rd_rn_rm),
15560 cCL(adfsp, e000120, 3, (RF, RF, RF_IF), rd_rn_rm),
15561 cCL(adfsm, e000140, 3, (RF, RF, RF_IF), rd_rn_rm),
15562 cCL(adfsz, e000160, 3, (RF, RF, RF_IF), rd_rn_rm),
15563 cCL(adfd, e000180, 3, (RF, RF, RF_IF), rd_rn_rm),
15564 cCL(adfdp, e0001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
15565 cCL(adfdm, e0001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
15566 cCL(adfdz, e0001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
15567 cCL(adfe, e080100, 3, (RF, RF, RF_IF), rd_rn_rm),
15568 cCL(adfep, e080120, 3, (RF, RF, RF_IF), rd_rn_rm),
15569 cCL(adfem, e080140, 3, (RF, RF, RF_IF), rd_rn_rm),
15570 cCL(adfez, e080160, 3, (RF, RF, RF_IF), rd_rn_rm),
15572 cCL(sufs, e200100, 3, (RF, RF, RF_IF), rd_rn_rm),
15573 cCL(sufsp, e200120, 3, (RF, RF, RF_IF), rd_rn_rm),
15574 cCL(sufsm, e200140, 3, (RF, RF, RF_IF), rd_rn_rm),
15575 cCL(sufsz, e200160, 3, (RF, RF, RF_IF), rd_rn_rm),
15576 cCL(sufd, e200180, 3, (RF, RF, RF_IF), rd_rn_rm),
15577 cCL(sufdp, e2001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
15578 cCL(sufdm, e2001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
15579 cCL(sufdz, e2001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
15580 cCL(sufe, e280100, 3, (RF, RF, RF_IF), rd_rn_rm),
15581 cCL(sufep, e280120, 3, (RF, RF, RF_IF), rd_rn_rm),
15582 cCL(sufem, e280140, 3, (RF, RF, RF_IF), rd_rn_rm),
15583 cCL(sufez, e280160, 3, (RF, RF, RF_IF), rd_rn_rm),
15585 cCL(rsfs, e300100, 3, (RF, RF, RF_IF), rd_rn_rm),
15586 cCL(rsfsp, e300120, 3, (RF, RF, RF_IF), rd_rn_rm),
15587 cCL(rsfsm, e300140, 3, (RF, RF, RF_IF), rd_rn_rm),
15588 cCL(rsfsz, e300160, 3, (RF, RF, RF_IF), rd_rn_rm),
15589 cCL(rsfd, e300180, 3, (RF, RF, RF_IF), rd_rn_rm),
15590 cCL(rsfdp, e3001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
15591 cCL(rsfdm, e3001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
15592 cCL(rsfdz, e3001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
15593 cCL(rsfe, e380100, 3, (RF, RF, RF_IF), rd_rn_rm),
15594 cCL(rsfep, e380120, 3, (RF, RF, RF_IF), rd_rn_rm),
15595 cCL(rsfem, e380140, 3, (RF, RF, RF_IF), rd_rn_rm),
15596 cCL(rsfez, e380160, 3, (RF, RF, RF_IF), rd_rn_rm),
15598 cCL(mufs, e100100, 3, (RF, RF, RF_IF), rd_rn_rm),
15599 cCL(mufsp, e100120, 3, (RF, RF, RF_IF), rd_rn_rm),
15600 cCL(mufsm, e100140, 3, (RF, RF, RF_IF), rd_rn_rm),
15601 cCL(mufsz, e100160, 3, (RF, RF, RF_IF), rd_rn_rm),
15602 cCL(mufd, e100180, 3, (RF, RF, RF_IF), rd_rn_rm),
15603 cCL(mufdp, e1001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
15604 cCL(mufdm, e1001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
15605 cCL(mufdz, e1001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
15606 cCL(mufe, e180100, 3, (RF, RF, RF_IF), rd_rn_rm),
15607 cCL(mufep, e180120, 3, (RF, RF, RF_IF), rd_rn_rm),
15608 cCL(mufem, e180140, 3, (RF, RF, RF_IF), rd_rn_rm),
15609 cCL(mufez, e180160, 3, (RF, RF, RF_IF), rd_rn_rm),
15611 cCL(dvfs, e400100, 3, (RF, RF, RF_IF), rd_rn_rm),
15612 cCL(dvfsp, e400120, 3, (RF, RF, RF_IF), rd_rn_rm),
15613 cCL(dvfsm, e400140, 3, (RF, RF, RF_IF), rd_rn_rm),
15614 cCL(dvfsz, e400160, 3, (RF, RF, RF_IF), rd_rn_rm),
15615 cCL(dvfd, e400180, 3, (RF, RF, RF_IF), rd_rn_rm),
15616 cCL(dvfdp, e4001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
15617 cCL(dvfdm, e4001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
15618 cCL(dvfdz, e4001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
15619 cCL(dvfe, e480100, 3, (RF, RF, RF_IF), rd_rn_rm),
15620 cCL(dvfep, e480120, 3, (RF, RF, RF_IF), rd_rn_rm),
15621 cCL(dvfem, e480140, 3, (RF, RF, RF_IF), rd_rn_rm),
15622 cCL(dvfez, e480160, 3, (RF, RF, RF_IF), rd_rn_rm),
15624 cCL(rdfs, e500100, 3, (RF, RF, RF_IF), rd_rn_rm),
15625 cCL(rdfsp, e500120, 3, (RF, RF, RF_IF), rd_rn_rm),
15626 cCL(rdfsm, e500140, 3, (RF, RF, RF_IF), rd_rn_rm),
15627 cCL(rdfsz, e500160, 3, (RF, RF, RF_IF), rd_rn_rm),
15628 cCL(rdfd, e500180, 3, (RF, RF, RF_IF), rd_rn_rm),
15629 cCL(rdfdp, e5001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
15630 cCL(rdfdm, e5001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
15631 cCL(rdfdz, e5001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
15632 cCL(rdfe, e580100, 3, (RF, RF, RF_IF), rd_rn_rm),
15633 cCL(rdfep, e580120, 3, (RF, RF, RF_IF), rd_rn_rm),
15634 cCL(rdfem, e580140, 3, (RF, RF, RF_IF), rd_rn_rm),
15635 cCL(rdfez, e580160, 3, (RF, RF, RF_IF), rd_rn_rm),
15637 cCL(pows, e600100, 3, (RF, RF, RF_IF), rd_rn_rm),
15638 cCL(powsp, e600120, 3, (RF, RF, RF_IF), rd_rn_rm),
15639 cCL(powsm, e600140, 3, (RF, RF, RF_IF), rd_rn_rm),
15640 cCL(powsz, e600160, 3, (RF, RF, RF_IF), rd_rn_rm),
15641 cCL(powd, e600180, 3, (RF, RF, RF_IF), rd_rn_rm),
15642 cCL(powdp, e6001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
15643 cCL(powdm, e6001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
15644 cCL(powdz, e6001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
15645 cCL(powe, e680100, 3, (RF, RF, RF_IF), rd_rn_rm),
15646 cCL(powep, e680120, 3, (RF, RF, RF_IF), rd_rn_rm),
15647 cCL(powem, e680140, 3, (RF, RF, RF_IF), rd_rn_rm),
15648 cCL(powez, e680160, 3, (RF, RF, RF_IF), rd_rn_rm),
15650 cCL(rpws, e700100, 3, (RF, RF, RF_IF), rd_rn_rm),
15651 cCL(rpwsp, e700120, 3, (RF, RF, RF_IF), rd_rn_rm),
15652 cCL(rpwsm, e700140, 3, (RF, RF, RF_IF), rd_rn_rm),
15653 cCL(rpwsz, e700160, 3, (RF, RF, RF_IF), rd_rn_rm),
15654 cCL(rpwd, e700180, 3, (RF, RF, RF_IF), rd_rn_rm),
15655 cCL(rpwdp, e7001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
15656 cCL(rpwdm, e7001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
15657 cCL(rpwdz, e7001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
15658 cCL(rpwe, e780100, 3, (RF, RF, RF_IF), rd_rn_rm),
15659 cCL(rpwep, e780120, 3, (RF, RF, RF_IF), rd_rn_rm),
15660 cCL(rpwem, e780140, 3, (RF, RF, RF_IF), rd_rn_rm),
15661 cCL(rpwez, e780160, 3, (RF, RF, RF_IF), rd_rn_rm),
15663 cCL(rmfs, e800100, 3, (RF, RF, RF_IF), rd_rn_rm),
15664 cCL(rmfsp, e800120, 3, (RF, RF, RF_IF), rd_rn_rm),
15665 cCL(rmfsm, e800140, 3, (RF, RF, RF_IF), rd_rn_rm),
15666 cCL(rmfsz, e800160, 3, (RF, RF, RF_IF), rd_rn_rm),
15667 cCL(rmfd, e800180, 3, (RF, RF, RF_IF), rd_rn_rm),
15668 cCL(rmfdp, e8001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
15669 cCL(rmfdm, e8001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
15670 cCL(rmfdz, e8001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
15671 cCL(rmfe, e880100, 3, (RF, RF, RF_IF), rd_rn_rm),
15672 cCL(rmfep, e880120, 3, (RF, RF, RF_IF), rd_rn_rm),
15673 cCL(rmfem, e880140, 3, (RF, RF, RF_IF), rd_rn_rm),
15674 cCL(rmfez, e880160, 3, (RF, RF, RF_IF), rd_rn_rm),
15676 cCL(fmls, e900100, 3, (RF, RF, RF_IF), rd_rn_rm),
15677 cCL(fmlsp, e900120, 3, (RF, RF, RF_IF), rd_rn_rm),
15678 cCL(fmlsm, e900140, 3, (RF, RF, RF_IF), rd_rn_rm),
15679 cCL(fmlsz, e900160, 3, (RF, RF, RF_IF), rd_rn_rm),
15680 cCL(fmld, e900180, 3, (RF, RF, RF_IF), rd_rn_rm),
15681 cCL(fmldp, e9001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
15682 cCL(fmldm, e9001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
15683 cCL(fmldz, e9001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
15684 cCL(fmle, e980100, 3, (RF, RF, RF_IF), rd_rn_rm),
15685 cCL(fmlep, e980120, 3, (RF, RF, RF_IF), rd_rn_rm),
15686 cCL(fmlem, e980140, 3, (RF, RF, RF_IF), rd_rn_rm),
15687 cCL(fmlez, e980160, 3, (RF, RF, RF_IF), rd_rn_rm),
15689 cCL(fdvs, ea00100, 3, (RF, RF, RF_IF), rd_rn_rm),
15690 cCL(fdvsp, ea00120, 3, (RF, RF, RF_IF), rd_rn_rm),
15691 cCL(fdvsm, ea00140, 3, (RF, RF, RF_IF), rd_rn_rm),
15692 cCL(fdvsz, ea00160, 3, (RF, RF, RF_IF), rd_rn_rm),
15693 cCL(fdvd, ea00180, 3, (RF, RF, RF_IF), rd_rn_rm),
15694 cCL(fdvdp, ea001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
15695 cCL(fdvdm, ea001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
15696 cCL(fdvdz, ea001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
15697 cCL(fdve, ea80100, 3, (RF, RF, RF_IF), rd_rn_rm),
15698 cCL(fdvep, ea80120, 3, (RF, RF, RF_IF), rd_rn_rm),
15699 cCL(fdvem, ea80140, 3, (RF, RF, RF_IF), rd_rn_rm),
15700 cCL(fdvez, ea80160, 3, (RF, RF, RF_IF), rd_rn_rm),
15702 cCL(frds, eb00100, 3, (RF, RF, RF_IF), rd_rn_rm),
15703 cCL(frdsp, eb00120, 3, (RF, RF, RF_IF), rd_rn_rm),
15704 cCL(frdsm, eb00140, 3, (RF, RF, RF_IF), rd_rn_rm),
15705 cCL(frdsz, eb00160, 3, (RF, RF, RF_IF), rd_rn_rm),
15706 cCL(frdd, eb00180, 3, (RF, RF, RF_IF), rd_rn_rm),
15707 cCL(frddp, eb001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
15708 cCL(frddm, eb001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
15709 cCL(frddz, eb001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
15710 cCL(frde, eb80100, 3, (RF, RF, RF_IF), rd_rn_rm),
15711 cCL(frdep, eb80120, 3, (RF, RF, RF_IF), rd_rn_rm),
15712 cCL(frdem, eb80140, 3, (RF, RF, RF_IF), rd_rn_rm),
15713 cCL(frdez, eb80160, 3, (RF, RF, RF_IF), rd_rn_rm),
15715 cCL(pols, ec00100, 3, (RF, RF, RF_IF), rd_rn_rm),
15716 cCL(polsp, ec00120, 3, (RF, RF, RF_IF), rd_rn_rm),
15717 cCL(polsm, ec00140, 3, (RF, RF, RF_IF), rd_rn_rm),
15718 cCL(polsz, ec00160, 3, (RF, RF, RF_IF), rd_rn_rm),
15719 cCL(pold, ec00180, 3, (RF, RF, RF_IF), rd_rn_rm),
15720 cCL(poldp, ec001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
15721 cCL(poldm, ec001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
15722 cCL(poldz, ec001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
15723 cCL(pole, ec80100, 3, (RF, RF, RF_IF), rd_rn_rm),
15724 cCL(polep, ec80120, 3, (RF, RF, RF_IF), rd_rn_rm),
15725 cCL(polem, ec80140, 3, (RF, RF, RF_IF), rd_rn_rm),
15726 cCL(polez, ec80160, 3, (RF, RF, RF_IF), rd_rn_rm),
15728 cCE(cmf, e90f110, 2, (RF, RF_IF), fpa_cmp),
15729 C3E(cmfe, ed0f110, 2, (RF, RF_IF), fpa_cmp),
15730 cCE(cnf, eb0f110, 2, (RF, RF_IF), fpa_cmp),
15731 C3E(cnfe, ef0f110, 2, (RF, RF_IF), fpa_cmp),
15733 cCL(flts, e000110, 2, (RF, RR), rn_rd),
15734 cCL(fltsp, e000130, 2, (RF, RR), rn_rd),
15735 cCL(fltsm, e000150, 2, (RF, RR), rn_rd),
15736 cCL(fltsz, e000170, 2, (RF, RR), rn_rd),
15737 cCL(fltd, e000190, 2, (RF, RR), rn_rd),
15738 cCL(fltdp, e0001b0, 2, (RF, RR), rn_rd),
15739 cCL(fltdm, e0001d0, 2, (RF, RR), rn_rd),
15740 cCL(fltdz, e0001f0, 2, (RF, RR), rn_rd),
15741 cCL(flte, e080110, 2, (RF, RR), rn_rd),
15742 cCL(fltep, e080130, 2, (RF, RR), rn_rd),
15743 cCL(fltem, e080150, 2, (RF, RR), rn_rd),
15744 cCL(fltez, e080170, 2, (RF, RR), rn_rd),
15746 /* The implementation of the FIX instruction is broken on some
15747 assemblers, in that it accepts a precision specifier as well as a
15748 rounding specifier, despite the fact that this is meaningless.
15749 To be more compatible, we accept it as well, though of course it
15750 does not set any bits. */
15751 cCE(fix, e100110, 2, (RR, RF), rd_rm),
15752 cCL(fixp, e100130, 2, (RR, RF), rd_rm),
15753 cCL(fixm, e100150, 2, (RR, RF), rd_rm),
15754 cCL(fixz, e100170, 2, (RR, RF), rd_rm),
15755 cCL(fixsp, e100130, 2, (RR, RF), rd_rm),
15756 cCL(fixsm, e100150, 2, (RR, RF), rd_rm),
15757 cCL(fixsz, e100170, 2, (RR, RF), rd_rm),
15758 cCL(fixdp, e100130, 2, (RR, RF), rd_rm),
15759 cCL(fixdm, e100150, 2, (RR, RF), rd_rm),
15760 cCL(fixdz, e100170, 2, (RR, RF), rd_rm),
15761 cCL(fixep, e100130, 2, (RR, RF), rd_rm),
15762 cCL(fixem, e100150, 2, (RR, RF), rd_rm),
15763 cCL(fixez, e100170, 2, (RR, RF), rd_rm),
15765 /* Instructions that were new with the real FPA, call them V2. */
15767 #define ARM_VARIANT &fpu_fpa_ext_v2
15768 cCE(lfm, c100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
15769 cCL(lfmfd, c900200, 3, (RF, I4b, ADDR), fpa_ldmstm),
15770 cCL(lfmea, d100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
15771 cCE(sfm, c000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
15772 cCL(sfmfd, d000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
15773 cCL(sfmea, c800200, 3, (RF, I4b, ADDR), fpa_ldmstm),
15776 #define ARM_VARIANT &fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
15777 /* Moves and type conversions. */
15778 cCE(fcpys, eb00a40, 2, (RVS, RVS), vfp_sp_monadic),
15779 cCE(fmrs, e100a10, 2, (RR, RVS), vfp_reg_from_sp),
15780 cCE(fmsr, e000a10, 2, (RVS, RR), vfp_sp_from_reg),
15781 cCE(fmstat, ef1fa10, 0, (), noargs),
15782 cCE(fsitos, eb80ac0, 2, (RVS, RVS), vfp_sp_monadic),
15783 cCE(fuitos, eb80a40, 2, (RVS, RVS), vfp_sp_monadic),
15784 cCE(ftosis, ebd0a40, 2, (RVS, RVS), vfp_sp_monadic),
15785 cCE(ftosizs, ebd0ac0, 2, (RVS, RVS), vfp_sp_monadic),
15786 cCE(ftouis, ebc0a40, 2, (RVS, RVS), vfp_sp_monadic),
15787 cCE(ftouizs, ebc0ac0, 2, (RVS, RVS), vfp_sp_monadic),
15788 cCE(fmrx, ef00a10, 2, (RR, RVC), rd_rn),
15789 cCE(fmxr, ee00a10, 2, (RVC, RR), rn_rd),
15790 cCE(vmrs, ef00a10, 2, (APSR_RR, RVC), vfp_vmrs),
15791 cCE(vmsr, ee00a10, 2, (RVC, RR), vfp_vmsr),
15793 /* Memory operations. */
15794 cCE(flds, d100a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst),
15795 cCE(fsts, d000a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst),
15796 cCE(fldmias, c900a00, 2, (RRw, VRSLST), vfp_sp_ldstmia),
15797 cCE(fldmfds, c900a00, 2, (RRw, VRSLST), vfp_sp_ldstmia),
15798 cCE(fldmdbs, d300a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb),
15799 cCE(fldmeas, d300a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb),
15800 cCE(fldmiax, c900b00, 2, (RRw, VRDLST), vfp_xp_ldstmia),
15801 cCE(fldmfdx, c900b00, 2, (RRw, VRDLST), vfp_xp_ldstmia),
15802 cCE(fldmdbx, d300b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb),
15803 cCE(fldmeax, d300b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb),
15804 cCE(fstmias, c800a00, 2, (RRw, VRSLST), vfp_sp_ldstmia),
15805 cCE(fstmeas, c800a00, 2, (RRw, VRSLST), vfp_sp_ldstmia),
15806 cCE(fstmdbs, d200a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb),
15807 cCE(fstmfds, d200a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb),
15808 cCE(fstmiax, c800b00, 2, (RRw, VRDLST), vfp_xp_ldstmia),
15809 cCE(fstmeax, c800b00, 2, (RRw, VRDLST), vfp_xp_ldstmia),
15810 cCE(fstmdbx, d200b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb),
15811 cCE(fstmfdx, d200b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb),
15813 /* Monadic operations. */
15814 cCE(fabss, eb00ac0, 2, (RVS, RVS), vfp_sp_monadic),
15815 cCE(fnegs, eb10a40, 2, (RVS, RVS), vfp_sp_monadic),
15816 cCE(fsqrts, eb10ac0, 2, (RVS, RVS), vfp_sp_monadic),
15818 /* Dyadic operations. */
15819 cCE(fadds, e300a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
15820 cCE(fsubs, e300a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
15821 cCE(fmuls, e200a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
15822 cCE(fdivs, e800a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
15823 cCE(fmacs, e000a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
15824 cCE(fmscs, e100a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
15825 cCE(fnmuls, e200a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
15826 cCE(fnmacs, e000a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
15827 cCE(fnmscs, e100a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
15830 cCE(fcmps, eb40a40, 2, (RVS, RVS), vfp_sp_monadic),
15831 cCE(fcmpzs, eb50a40, 1, (RVS), vfp_sp_compare_z),
15832 cCE(fcmpes, eb40ac0, 2, (RVS, RVS), vfp_sp_monadic),
15833 cCE(fcmpezs, eb50ac0, 1, (RVS), vfp_sp_compare_z),
15836 #define ARM_VARIANT &fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
15837 /* Moves and type conversions. */
15838 cCE(fcpyd, eb00b40, 2, (RVD, RVD), vfp_dp_rd_rm),
15839 cCE(fcvtds, eb70ac0, 2, (RVD, RVS), vfp_dp_sp_cvt),
15840 cCE(fcvtsd, eb70bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
15841 cCE(fmdhr, e200b10, 2, (RVD, RR), vfp_dp_rn_rd),
15842 cCE(fmdlr, e000b10, 2, (RVD, RR), vfp_dp_rn_rd),
15843 cCE(fmrdh, e300b10, 2, (RR, RVD), vfp_dp_rd_rn),
15844 cCE(fmrdl, e100b10, 2, (RR, RVD), vfp_dp_rd_rn),
15845 cCE(fsitod, eb80bc0, 2, (RVD, RVS), vfp_dp_sp_cvt),
15846 cCE(fuitod, eb80b40, 2, (RVD, RVS), vfp_dp_sp_cvt),
15847 cCE(ftosid, ebd0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
15848 cCE(ftosizd, ebd0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
15849 cCE(ftouid, ebc0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
15850 cCE(ftouizd, ebc0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
15852 /* Memory operations. */
15853 cCE(fldd, d100b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst),
15854 cCE(fstd, d000b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst),
15855 cCE(fldmiad, c900b00, 2, (RRw, VRDLST), vfp_dp_ldstmia),
15856 cCE(fldmfdd, c900b00, 2, (RRw, VRDLST), vfp_dp_ldstmia),
15857 cCE(fldmdbd, d300b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb),
15858 cCE(fldmead, d300b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb),
15859 cCE(fstmiad, c800b00, 2, (RRw, VRDLST), vfp_dp_ldstmia),
15860 cCE(fstmead, c800b00, 2, (RRw, VRDLST), vfp_dp_ldstmia),
15861 cCE(fstmdbd, d200b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb),
15862 cCE(fstmfdd, d200b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb),
15864 /* Monadic operations. */
15865 cCE(fabsd, eb00bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
15866 cCE(fnegd, eb10b40, 2, (RVD, RVD), vfp_dp_rd_rm),
15867 cCE(fsqrtd, eb10bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
15869 /* Dyadic operations. */
15870 cCE(faddd, e300b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
15871 cCE(fsubd, e300b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
15872 cCE(fmuld, e200b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
15873 cCE(fdivd, e800b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
15874 cCE(fmacd, e000b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
15875 cCE(fmscd, e100b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
15876 cCE(fnmuld, e200b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
15877 cCE(fnmacd, e000b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
15878 cCE(fnmscd, e100b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
15881 cCE(fcmpd, eb40b40, 2, (RVD, RVD), vfp_dp_rd_rm),
15882 cCE(fcmpzd, eb50b40, 1, (RVD), vfp_dp_rd),
15883 cCE(fcmped, eb40bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
15884 cCE(fcmpezd, eb50bc0, 1, (RVD), vfp_dp_rd),
15887 #define ARM_VARIANT &fpu_vfp_ext_v2
15888 cCE(fmsrr, c400a10, 3, (VRSLST, RR, RR), vfp_sp2_from_reg2),
15889 cCE(fmrrs, c500a10, 3, (RR, RR, VRSLST), vfp_reg2_from_sp2),
15890 cCE(fmdrr, c400b10, 3, (RVD, RR, RR), vfp_dp_rm_rd_rn),
15891 cCE(fmrrd, c500b10, 3, (RR, RR, RVD), vfp_dp_rd_rn_rm),
15893 /* Instructions which may belong to either the Neon or VFP instruction sets.
15894 Individual encoder functions perform additional architecture checks. */
15896 #define ARM_VARIANT &fpu_vfp_ext_v1xd
15897 #undef THUMB_VARIANT
15898 #define THUMB_VARIANT &fpu_vfp_ext_v1xd
15899 /* These mnemonics are unique to VFP. */
15900 NCE(vsqrt, 0, 2, (RVSD, RVSD), vfp_nsyn_sqrt),
15901 NCE(vdiv, 0, 3, (RVSD, RVSD, RVSD), vfp_nsyn_div),
15902 nCE(vnmul, vnmul, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
15903 nCE(vnmla, vnmla, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
15904 nCE(vnmls, vnmls, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
15905 nCE(vcmp, vcmp, 2, (RVSD, RVSD_I0), vfp_nsyn_cmp),
15906 nCE(vcmpe, vcmpe, 2, (RVSD, RVSD_I0), vfp_nsyn_cmp),
15907 NCE(vpush, 0, 1, (VRSDLST), vfp_nsyn_push),
15908 NCE(vpop, 0, 1, (VRSDLST), vfp_nsyn_pop),
15909 NCE(vcvtz, 0, 2, (RVSD, RVSD), vfp_nsyn_cvtz),
15911 /* Mnemonics shared by Neon and VFP. */
15912 nCEF(vmul, vmul, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mul),
15913 nCEF(vmla, vmla, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar),
15914 nCEF(vmls, vmls, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar),
15916 nCEF(vadd, vadd, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i),
15917 nCEF(vsub, vsub, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i),
15919 NCEF(vabs, 1b10300, 2, (RNSDQ, RNSDQ), neon_abs_neg),
15920 NCEF(vneg, 1b10380, 2, (RNSDQ, RNSDQ), neon_abs_neg),
15922 NCE(vldm, c900b00, 2, (RRw, VRSDLST), neon_ldm_stm),
15923 NCE(vldmia, c900b00, 2, (RRw, VRSDLST), neon_ldm_stm),
15924 NCE(vldmdb, d100b00, 2, (RRw, VRSDLST), neon_ldm_stm),
15925 NCE(vstm, c800b00, 2, (RRw, VRSDLST), neon_ldm_stm),
15926 NCE(vstmia, c800b00, 2, (RRw, VRSDLST), neon_ldm_stm),
15927 NCE(vstmdb, d000b00, 2, (RRw, VRSDLST), neon_ldm_stm),
15928 NCE(vldr, d100b00, 2, (RVSD, ADDRGLDC), neon_ldr_str),
15929 NCE(vstr, d000b00, 2, (RVSD, ADDRGLDC), neon_ldr_str),
15931 nCEF(vcvt, vcvt, 3, (RNSDQ, RNSDQ, oI32b), neon_cvt),
15933 /* NOTE: All VMOV encoding is special-cased! */
15934 NCE(vmov, 0, 1, (VMOV), neon_mov),
15935 NCE(vmovq, 0, 1, (VMOV), neon_mov),
15937 #undef THUMB_VARIANT
15938 #define THUMB_VARIANT &fpu_neon_ext_v1
15940 #define ARM_VARIANT &fpu_neon_ext_v1
15941 /* Data processing with three registers of the same length. */
15942 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
15943 NUF(vaba, 0000710, 3, (RNDQ, RNDQ, RNDQ), neon_dyadic_i_su),
15944 NUF(vabaq, 0000710, 3, (RNQ, RNQ, RNQ), neon_dyadic_i_su),
15945 NUF(vhadd, 0000000, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
15946 NUF(vhaddq, 0000000, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
15947 NUF(vrhadd, 0000100, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
15948 NUF(vrhaddq, 0000100, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
15949 NUF(vhsub, 0000200, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
15950 NUF(vhsubq, 0000200, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
15951 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
15952 NUF(vqadd, 0000010, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su),
15953 NUF(vqaddq, 0000010, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su),
15954 NUF(vqsub, 0000210, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su),
15955 NUF(vqsubq, 0000210, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su),
15956 NUF(vrshl, 0000500, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl),
15957 NUF(vrshlq, 0000500, 3, (RNQ, oRNQ, RNQ), neon_rshl),
15958 NUF(vqrshl, 0000510, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl),
15959 NUF(vqrshlq, 0000510, 3, (RNQ, oRNQ, RNQ), neon_rshl),
15960 /* If not immediate, fall back to neon_dyadic_i64_su.
15961 shl_imm should accept I8 I16 I32 I64,
15962 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
15963 nUF(vshl, vshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_shl_imm),
15964 nUF(vshlq, vshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_shl_imm),
15965 nUF(vqshl, vqshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_qshl_imm),
15966 nUF(vqshlq, vqshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_qshl_imm),
15967 /* Logic ops, types optional & ignored. */
15968 nUF(vand, vand, 2, (RNDQ, NILO), neon_logic),
15969 nUF(vandq, vand, 2, (RNQ, NILO), neon_logic),
15970 nUF(vbic, vbic, 2, (RNDQ, NILO), neon_logic),
15971 nUF(vbicq, vbic, 2, (RNQ, NILO), neon_logic),
15972 nUF(vorr, vorr, 2, (RNDQ, NILO), neon_logic),
15973 nUF(vorrq, vorr, 2, (RNQ, NILO), neon_logic),
15974 nUF(vorn, vorn, 2, (RNDQ, NILO), neon_logic),
15975 nUF(vornq, vorn, 2, (RNQ, NILO), neon_logic),
15976 nUF(veor, veor, 3, (RNDQ, oRNDQ, RNDQ), neon_logic),
15977 nUF(veorq, veor, 3, (RNQ, oRNQ, RNQ), neon_logic),
15978 /* Bitfield ops, untyped. */
15979 NUF(vbsl, 1100110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
15980 NUF(vbslq, 1100110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
15981 NUF(vbit, 1200110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
15982 NUF(vbitq, 1200110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
15983 NUF(vbif, 1300110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
15984 NUF(vbifq, 1300110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
15985 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
15986 nUF(vabd, vabd, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
15987 nUF(vabdq, vabd, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
15988 nUF(vmax, vmax, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
15989 nUF(vmaxq, vmax, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
15990 nUF(vmin, vmin, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
15991 nUF(vminq, vmin, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
15992 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
15993 back to neon_dyadic_if_su. */
15994 nUF(vcge, vcge, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp),
15995 nUF(vcgeq, vcge, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp),
15996 nUF(vcgt, vcgt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp),
15997 nUF(vcgtq, vcgt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp),
15998 nUF(vclt, vclt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv),
15999 nUF(vcltq, vclt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv),
16000 nUF(vcle, vcle, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv),
16001 nUF(vcleq, vcle, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv),
16002 /* Comparison. Type I8 I16 I32 F32. */
16003 nUF(vceq, vceq, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_ceq),
16004 nUF(vceqq, vceq, 3, (RNQ, oRNQ, RNDQ_I0), neon_ceq),
16005 /* As above, D registers only. */
16006 nUF(vpmax, vpmax, 3, (RND, oRND, RND), neon_dyadic_if_su_d),
16007 nUF(vpmin, vpmin, 3, (RND, oRND, RND), neon_dyadic_if_su_d),
16008 /* Int and float variants, signedness unimportant. */
16009 nUF(vmlaq, vmla, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar),
16010 nUF(vmlsq, vmls, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar),
16011 nUF(vpadd, vpadd, 3, (RND, oRND, RND), neon_dyadic_if_i_d),
16012 /* Add/sub take types I8 I16 I32 I64 F32. */
16013 nUF(vaddq, vadd, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i),
16014 nUF(vsubq, vsub, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i),
16015 /* vtst takes sizes 8, 16, 32. */
16016 NUF(vtst, 0000810, 3, (RNDQ, oRNDQ, RNDQ), neon_tst),
16017 NUF(vtstq, 0000810, 3, (RNQ, oRNQ, RNQ), neon_tst),
16018 /* VMUL takes I8 I16 I32 F32 P8. */
16019 nUF(vmulq, vmul, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mul),
16020 /* VQD{R}MULH takes S16 S32. */
16021 nUF(vqdmulh, vqdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh),
16022 nUF(vqdmulhq, vqdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh),
16023 nUF(vqrdmulh, vqrdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh),
16024 nUF(vqrdmulhq, vqrdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh),
16025 NUF(vacge, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute),
16026 NUF(vacgeq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute),
16027 NUF(vacgt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute),
16028 NUF(vacgtq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute),
16029 NUF(vaclt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
16030 NUF(vacltq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv),
16031 NUF(vacle, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
16032 NUF(vacleq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv),
16033 NUF(vrecps, 0000f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step),
16034 NUF(vrecpsq, 0000f10, 3, (RNQ, oRNQ, RNQ), neon_step),
16035 NUF(vrsqrts, 0200f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step),
16036 NUF(vrsqrtsq, 0200f10, 3, (RNQ, oRNQ, RNQ), neon_step),
16038 /* Two address, int/float. Types S8 S16 S32 F32. */
16039 NUF(vabsq, 1b10300, 2, (RNQ, RNQ), neon_abs_neg),
16040 NUF(vnegq, 1b10380, 2, (RNQ, RNQ), neon_abs_neg),
16042 /* Data processing with two registers and a shift amount. */
16043 /* Right shifts, and variants with rounding.
16044 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
16045 NUF(vshr, 0800010, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm),
16046 NUF(vshrq, 0800010, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm),
16047 NUF(vrshr, 0800210, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm),
16048 NUF(vrshrq, 0800210, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm),
16049 NUF(vsra, 0800110, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm),
16050 NUF(vsraq, 0800110, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm),
16051 NUF(vrsra, 0800310, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm),
16052 NUF(vrsraq, 0800310, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm),
16053 /* Shift and insert. Sizes accepted 8 16 32 64. */
16054 NUF(vsli, 1800510, 3, (RNDQ, oRNDQ, I63), neon_sli),
16055 NUF(vsliq, 1800510, 3, (RNQ, oRNQ, I63), neon_sli),
16056 NUF(vsri, 1800410, 3, (RNDQ, oRNDQ, I64), neon_sri),
16057 NUF(vsriq, 1800410, 3, (RNQ, oRNQ, I64), neon_sri),
16058 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
16059 NUF(vqshlu, 1800610, 3, (RNDQ, oRNDQ, I63), neon_qshlu_imm),
16060 NUF(vqshluq, 1800610, 3, (RNQ, oRNQ, I63), neon_qshlu_imm),
16061 /* Right shift immediate, saturating & narrowing, with rounding variants.
16062 Types accepted S16 S32 S64 U16 U32 U64. */
16063 NUF(vqshrn, 0800910, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow),
16064 NUF(vqrshrn, 0800950, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow),
16065 /* As above, unsigned. Types accepted S16 S32 S64. */
16066 NUF(vqshrun, 0800810, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u),
16067 NUF(vqrshrun, 0800850, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u),
16068 /* Right shift narrowing. Types accepted I16 I32 I64. */
16069 NUF(vshrn, 0800810, 3, (RND, RNQ, I32z), neon_rshift_narrow),
16070 NUF(vrshrn, 0800850, 3, (RND, RNQ, I32z), neon_rshift_narrow),
16071 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
16072 nUF(vshll, vshll, 3, (RNQ, RND, I32), neon_shll),
16073 /* CVT with optional immediate for fixed-point variant. */
16074 nUF(vcvtq, vcvt, 3, (RNQ, RNQ, oI32b), neon_cvt),
16076 nUF(vmvn, vmvn, 2, (RNDQ, RNDQ_IMVNb), neon_mvn),
16077 nUF(vmvnq, vmvn, 2, (RNQ, RNDQ_IMVNb), neon_mvn),
16079 /* Data processing, three registers of different lengths. */
16080 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
16081 NUF(vabal, 0800500, 3, (RNQ, RND, RND), neon_abal),
16082 NUF(vabdl, 0800700, 3, (RNQ, RND, RND), neon_dyadic_long),
16083 NUF(vaddl, 0800000, 3, (RNQ, RND, RND), neon_dyadic_long),
16084 NUF(vsubl, 0800200, 3, (RNQ, RND, RND), neon_dyadic_long),
16085 /* If not scalar, fall back to neon_dyadic_long.
16086 Vector types as above, scalar types S16 S32 U16 U32. */
16087 nUF(vmlal, vmlal, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long),
16088 nUF(vmlsl, vmlsl, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long),
16089 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
16090 NUF(vaddw, 0800100, 3, (RNQ, oRNQ, RND), neon_dyadic_wide),
16091 NUF(vsubw, 0800300, 3, (RNQ, oRNQ, RND), neon_dyadic_wide),
16092 /* Dyadic, narrowing insns. Types I16 I32 I64. */
16093 NUF(vaddhn, 0800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
16094 NUF(vraddhn, 1800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
16095 NUF(vsubhn, 0800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
16096 NUF(vrsubhn, 1800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
16097 /* Saturating doubling multiplies. Types S16 S32. */
16098 nUF(vqdmlal, vqdmlal, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
16099 nUF(vqdmlsl, vqdmlsl, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
16100 nUF(vqdmull, vqdmull, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
16101 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
16102 S16 S32 U16 U32. */
16103 nUF(vmull, vmull, 3, (RNQ, RND, RND_RNSC), neon_vmull),
16105 /* Extract. Size 8. */
16106 NUF(vext, 0b00000, 4, (RNDQ, oRNDQ, RNDQ, I15), neon_ext),
16107 NUF(vextq, 0b00000, 4, (RNQ, oRNQ, RNQ, I15), neon_ext),
16109 /* Two registers, miscellaneous. */
16110 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
16111 NUF(vrev64, 1b00000, 2, (RNDQ, RNDQ), neon_rev),
16112 NUF(vrev64q, 1b00000, 2, (RNQ, RNQ), neon_rev),
16113 NUF(vrev32, 1b00080, 2, (RNDQ, RNDQ), neon_rev),
16114 NUF(vrev32q, 1b00080, 2, (RNQ, RNQ), neon_rev),
16115 NUF(vrev16, 1b00100, 2, (RNDQ, RNDQ), neon_rev),
16116 NUF(vrev16q, 1b00100, 2, (RNQ, RNQ), neon_rev),
16117 /* Vector replicate. Sizes 8 16 32. */
16118 nCE(vdup, vdup, 2, (RNDQ, RR_RNSC), neon_dup),
16119 nCE(vdupq, vdup, 2, (RNQ, RR_RNSC), neon_dup),
16120 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
16121 NUF(vmovl, 0800a10, 2, (RNQ, RND), neon_movl),
16122 /* VMOVN. Types I16 I32 I64. */
16123 nUF(vmovn, vmovn, 2, (RND, RNQ), neon_movn),
16124 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
16125 nUF(vqmovn, vqmovn, 2, (RND, RNQ), neon_qmovn),
16126 /* VQMOVUN. Types S16 S32 S64. */
16127 nUF(vqmovun, vqmovun, 2, (RND, RNQ), neon_qmovun),
16128 /* VZIP / VUZP. Sizes 8 16 32. */
16129 NUF(vzip, 1b20180, 2, (RNDQ, RNDQ), neon_zip_uzp),
16130 NUF(vzipq, 1b20180, 2, (RNQ, RNQ), neon_zip_uzp),
16131 NUF(vuzp, 1b20100, 2, (RNDQ, RNDQ), neon_zip_uzp),
16132 NUF(vuzpq, 1b20100, 2, (RNQ, RNQ), neon_zip_uzp),
16133 /* VQABS / VQNEG. Types S8 S16 S32. */
16134 NUF(vqabs, 1b00700, 2, (RNDQ, RNDQ), neon_sat_abs_neg),
16135 NUF(vqabsq, 1b00700, 2, (RNQ, RNQ), neon_sat_abs_neg),
16136 NUF(vqneg, 1b00780, 2, (RNDQ, RNDQ), neon_sat_abs_neg),
16137 NUF(vqnegq, 1b00780, 2, (RNQ, RNQ), neon_sat_abs_neg),
16138 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
16139 NUF(vpadal, 1b00600, 2, (RNDQ, RNDQ), neon_pair_long),
16140 NUF(vpadalq, 1b00600, 2, (RNQ, RNQ), neon_pair_long),
16141 NUF(vpaddl, 1b00200, 2, (RNDQ, RNDQ), neon_pair_long),
16142 NUF(vpaddlq, 1b00200, 2, (RNQ, RNQ), neon_pair_long),
16143 /* Reciprocal estimates. Types U32 F32. */
16144 NUF(vrecpe, 1b30400, 2, (RNDQ, RNDQ), neon_recip_est),
16145 NUF(vrecpeq, 1b30400, 2, (RNQ, RNQ), neon_recip_est),
16146 NUF(vrsqrte, 1b30480, 2, (RNDQ, RNDQ), neon_recip_est),
16147 NUF(vrsqrteq, 1b30480, 2, (RNQ, RNQ), neon_recip_est),
16148 /* VCLS. Types S8 S16 S32. */
16149 NUF(vcls, 1b00400, 2, (RNDQ, RNDQ), neon_cls),
16150 NUF(vclsq, 1b00400, 2, (RNQ, RNQ), neon_cls),
16151 /* VCLZ. Types I8 I16 I32. */
16152 NUF(vclz, 1b00480, 2, (RNDQ, RNDQ), neon_clz),
16153 NUF(vclzq, 1b00480, 2, (RNQ, RNQ), neon_clz),
16154 /* VCNT. Size 8. */
16155 NUF(vcnt, 1b00500, 2, (RNDQ, RNDQ), neon_cnt),
16156 NUF(vcntq, 1b00500, 2, (RNQ, RNQ), neon_cnt),
16157 /* Two address, untyped. */
16158 NUF(vswp, 1b20000, 2, (RNDQ, RNDQ), neon_swp),
16159 NUF(vswpq, 1b20000, 2, (RNQ, RNQ), neon_swp),
16160 /* VTRN. Sizes 8 16 32. */
16161 nUF(vtrn, vtrn, 2, (RNDQ, RNDQ), neon_trn),
16162 nUF(vtrnq, vtrn, 2, (RNQ, RNQ), neon_trn),
16164 /* Table lookup. Size 8. */
16165 NUF(vtbl, 1b00800, 3, (RND, NRDLST, RND), neon_tbl_tbx),
16166 NUF(vtbx, 1b00840, 3, (RND, NRDLST, RND), neon_tbl_tbx),
16168 #undef THUMB_VARIANT
16169 #define THUMB_VARIANT &fpu_vfp_v3_or_neon_ext
16171 #define ARM_VARIANT &fpu_vfp_v3_or_neon_ext
16172 /* Neon element/structure load/store. */
16173 nUF(vld1, vld1, 2, (NSTRLST, ADDR), neon_ldx_stx),
16174 nUF(vst1, vst1, 2, (NSTRLST, ADDR), neon_ldx_stx),
16175 nUF(vld2, vld2, 2, (NSTRLST, ADDR), neon_ldx_stx),
16176 nUF(vst2, vst2, 2, (NSTRLST, ADDR), neon_ldx_stx),
16177 nUF(vld3, vld3, 2, (NSTRLST, ADDR), neon_ldx_stx),
16178 nUF(vst3, vst3, 2, (NSTRLST, ADDR), neon_ldx_stx),
16179 nUF(vld4, vld4, 2, (NSTRLST, ADDR), neon_ldx_stx),
16180 nUF(vst4, vst4, 2, (NSTRLST, ADDR), neon_ldx_stx),
16182 #undef THUMB_VARIANT
16183 #define THUMB_VARIANT &fpu_vfp_ext_v3
16185 #define ARM_VARIANT &fpu_vfp_ext_v3
16186 cCE(fconsts, eb00a00, 2, (RVS, I255), vfp_sp_const),
16187 cCE(fconstd, eb00b00, 2, (RVD, I255), vfp_dp_const),
16188 cCE(fshtos, eba0a40, 2, (RVS, I16z), vfp_sp_conv_16),
16189 cCE(fshtod, eba0b40, 2, (RVD, I16z), vfp_dp_conv_16),
16190 cCE(fsltos, eba0ac0, 2, (RVS, I32), vfp_sp_conv_32),
16191 cCE(fsltod, eba0bc0, 2, (RVD, I32), vfp_dp_conv_32),
16192 cCE(fuhtos, ebb0a40, 2, (RVS, I16z), vfp_sp_conv_16),
16193 cCE(fuhtod, ebb0b40, 2, (RVD, I16z), vfp_dp_conv_16),
16194 cCE(fultos, ebb0ac0, 2, (RVS, I32), vfp_sp_conv_32),
16195 cCE(fultod, ebb0bc0, 2, (RVD, I32), vfp_dp_conv_32),
16196 cCE(ftoshs, ebe0a40, 2, (RVS, I16z), vfp_sp_conv_16),
16197 cCE(ftoshd, ebe0b40, 2, (RVD, I16z), vfp_dp_conv_16),
16198 cCE(ftosls, ebe0ac0, 2, (RVS, I32), vfp_sp_conv_32),
16199 cCE(ftosld, ebe0bc0, 2, (RVD, I32), vfp_dp_conv_32),
16200 cCE(ftouhs, ebf0a40, 2, (RVS, I16z), vfp_sp_conv_16),
16201 cCE(ftouhd, ebf0b40, 2, (RVD, I16z), vfp_dp_conv_16),
16202 cCE(ftouls, ebf0ac0, 2, (RVS, I32), vfp_sp_conv_32),
16203 cCE(ftould, ebf0bc0, 2, (RVD, I32), vfp_dp_conv_32),
16205 #undef THUMB_VARIANT
16207 #define ARM_VARIANT &arm_cext_xscale /* Intel XScale extensions. */
16208 cCE(mia, e200010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
16209 cCE(miaph, e280010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
16210 cCE(miabb, e2c0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
16211 cCE(miabt, e2d0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
16212 cCE(miatb, e2e0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
16213 cCE(miatt, e2f0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
16214 cCE(mar, c400000, 3, (RXA, RRnpc, RRnpc), xsc_mar),
16215 cCE(mra, c500000, 3, (RRnpc, RRnpc, RXA), xsc_mra),
16218 #define ARM_VARIANT &arm_cext_iwmmxt /* Intel Wireless MMX technology. */
16219 cCE(tandcb, e13f130, 1, (RR), iwmmxt_tandorc),
16220 cCE(tandch, e53f130, 1, (RR), iwmmxt_tandorc),
16221 cCE(tandcw, e93f130, 1, (RR), iwmmxt_tandorc),
16222 cCE(tbcstb, e400010, 2, (RIWR, RR), rn_rd),
16223 cCE(tbcsth, e400050, 2, (RIWR, RR), rn_rd),
16224 cCE(tbcstw, e400090, 2, (RIWR, RR), rn_rd),
16225 cCE(textrcb, e130170, 2, (RR, I7), iwmmxt_textrc),
16226 cCE(textrch, e530170, 2, (RR, I7), iwmmxt_textrc),
16227 cCE(textrcw, e930170, 2, (RR, I7), iwmmxt_textrc),
16228 cCE(textrmub, e100070, 3, (RR, RIWR, I7), iwmmxt_textrm),
16229 cCE(textrmuh, e500070, 3, (RR, RIWR, I7), iwmmxt_textrm),
16230 cCE(textrmuw, e900070, 3, (RR, RIWR, I7), iwmmxt_textrm),
16231 cCE(textrmsb, e100078, 3, (RR, RIWR, I7), iwmmxt_textrm),
16232 cCE(textrmsh, e500078, 3, (RR, RIWR, I7), iwmmxt_textrm),
16233 cCE(textrmsw, e900078, 3, (RR, RIWR, I7), iwmmxt_textrm),
16234 cCE(tinsrb, e600010, 3, (RIWR, RR, I7), iwmmxt_tinsr),
16235 cCE(tinsrh, e600050, 3, (RIWR, RR, I7), iwmmxt_tinsr),
16236 cCE(tinsrw, e600090, 3, (RIWR, RR, I7), iwmmxt_tinsr),
16237 cCE(tmcr, e000110, 2, (RIWC_RIWG, RR), rn_rd),
16238 cCE(tmcrr, c400000, 3, (RIWR, RR, RR), rm_rd_rn),
16239 cCE(tmia, e200010, 3, (RIWR, RR, RR), iwmmxt_tmia),
16240 cCE(tmiaph, e280010, 3, (RIWR, RR, RR), iwmmxt_tmia),
16241 cCE(tmiabb, e2c0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
16242 cCE(tmiabt, e2d0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
16243 cCE(tmiatb, e2e0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
16244 cCE(tmiatt, e2f0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
16245 cCE(tmovmskb, e100030, 2, (RR, RIWR), rd_rn),
16246 cCE(tmovmskh, e500030, 2, (RR, RIWR), rd_rn),
16247 cCE(tmovmskw, e900030, 2, (RR, RIWR), rd_rn),
16248 cCE(tmrc, e100110, 2, (RR, RIWC_RIWG), rd_rn),
16249 cCE(tmrrc, c500000, 3, (RR, RR, RIWR), rd_rn_rm),
16250 cCE(torcb, e13f150, 1, (RR), iwmmxt_tandorc),
16251 cCE(torch, e53f150, 1, (RR), iwmmxt_tandorc),
16252 cCE(torcw, e93f150, 1, (RR), iwmmxt_tandorc),
16253 cCE(waccb, e0001c0, 2, (RIWR, RIWR), rd_rn),
16254 cCE(wacch, e4001c0, 2, (RIWR, RIWR), rd_rn),
16255 cCE(waccw, e8001c0, 2, (RIWR, RIWR), rd_rn),
16256 cCE(waddbss, e300180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16257 cCE(waddb, e000180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16258 cCE(waddbus, e100180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16259 cCE(waddhss, e700180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16260 cCE(waddh, e400180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16261 cCE(waddhus, e500180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16262 cCE(waddwss, eb00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16263 cCE(waddw, e800180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16264 cCE(waddwus, e900180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16265 cCE(waligni, e000020, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_waligni),
16266 cCE(walignr0, e800020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16267 cCE(walignr1, e900020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16268 cCE(walignr2, ea00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16269 cCE(walignr3, eb00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16270 cCE(wand, e200000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16271 cCE(wandn, e300000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16272 cCE(wavg2b, e800000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16273 cCE(wavg2br, e900000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16274 cCE(wavg2h, ec00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16275 cCE(wavg2hr, ed00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16276 cCE(wcmpeqb, e000060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16277 cCE(wcmpeqh, e400060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16278 cCE(wcmpeqw, e800060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16279 cCE(wcmpgtub, e100060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16280 cCE(wcmpgtuh, e500060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16281 cCE(wcmpgtuw, e900060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16282 cCE(wcmpgtsb, e300060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16283 cCE(wcmpgtsh, e700060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16284 cCE(wcmpgtsw, eb00060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16285 cCE(wldrb, c100000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
16286 cCE(wldrh, c500000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
16287 cCE(wldrw, c100100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
16288 cCE(wldrd, c500100, 2, (RIWR, ADDR), iwmmxt_wldstd),
16289 cCE(wmacs, e600100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16290 cCE(wmacsz, e700100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16291 cCE(wmacu, e400100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16292 cCE(wmacuz, e500100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16293 cCE(wmadds, ea00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16294 cCE(wmaddu, e800100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16295 cCE(wmaxsb, e200160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16296 cCE(wmaxsh, e600160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16297 cCE(wmaxsw, ea00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16298 cCE(wmaxub, e000160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16299 cCE(wmaxuh, e400160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16300 cCE(wmaxuw, e800160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16301 cCE(wminsb, e300160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16302 cCE(wminsh, e700160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16303 cCE(wminsw, eb00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16304 cCE(wminub, e100160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16305 cCE(wminuh, e500160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16306 cCE(wminuw, e900160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16307 cCE(wmov, e000000, 2, (RIWR, RIWR), iwmmxt_wmov),
16308 cCE(wmulsm, e300100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16309 cCE(wmulsl, e200100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16310 cCE(wmulum, e100100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16311 cCE(wmulul, e000100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16312 cCE(wor, e000000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16313 cCE(wpackhss, e700080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16314 cCE(wpackhus, e500080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16315 cCE(wpackwss, eb00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16316 cCE(wpackwus, e900080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16317 cCE(wpackdss, ef00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16318 cCE(wpackdus, ed00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16319 cCE(wrorh, e700040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
16320 cCE(wrorhg, e700148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
16321 cCE(wrorw, eb00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
16322 cCE(wrorwg, eb00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
16323 cCE(wrord, ef00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
16324 cCE(wrordg, ef00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
16325 cCE(wsadb, e000120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16326 cCE(wsadbz, e100120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16327 cCE(wsadh, e400120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16328 cCE(wsadhz, e500120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16329 cCE(wshufh, e0001e0, 3, (RIWR, RIWR, I255), iwmmxt_wshufh),
16330 cCE(wsllh, e500040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
16331 cCE(wsllhg, e500148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
16332 cCE(wsllw, e900040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
16333 cCE(wsllwg, e900148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
16334 cCE(wslld, ed00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
16335 cCE(wslldg, ed00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
16336 cCE(wsrah, e400040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
16337 cCE(wsrahg, e400148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
16338 cCE(wsraw, e800040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
16339 cCE(wsrawg, e800148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
16340 cCE(wsrad, ec00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
16341 cCE(wsradg, ec00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
16342 cCE(wsrlh, e600040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
16343 cCE(wsrlhg, e600148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
16344 cCE(wsrlw, ea00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
16345 cCE(wsrlwg, ea00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
16346 cCE(wsrld, ee00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
16347 cCE(wsrldg, ee00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
16348 cCE(wstrb, c000000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
16349 cCE(wstrh, c400000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
16350 cCE(wstrw, c000100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
16351 cCE(wstrd, c400100, 2, (RIWR, ADDR), iwmmxt_wldstd),
16352 cCE(wsubbss, e3001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16353 cCE(wsubb, e0001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16354 cCE(wsubbus, e1001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16355 cCE(wsubhss, e7001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16356 cCE(wsubh, e4001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16357 cCE(wsubhus, e5001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16358 cCE(wsubwss, eb001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16359 cCE(wsubw, e8001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16360 cCE(wsubwus, e9001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16361 cCE(wunpckehub,e0000c0, 2, (RIWR, RIWR), rd_rn),
16362 cCE(wunpckehuh,e4000c0, 2, (RIWR, RIWR), rd_rn),
16363 cCE(wunpckehuw,e8000c0, 2, (RIWR, RIWR), rd_rn),
16364 cCE(wunpckehsb,e2000c0, 2, (RIWR, RIWR), rd_rn),
16365 cCE(wunpckehsh,e6000c0, 2, (RIWR, RIWR), rd_rn),
16366 cCE(wunpckehsw,ea000c0, 2, (RIWR, RIWR), rd_rn),
16367 cCE(wunpckihb, e1000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16368 cCE(wunpckihh, e5000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16369 cCE(wunpckihw, e9000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16370 cCE(wunpckelub,e0000e0, 2, (RIWR, RIWR), rd_rn),
16371 cCE(wunpckeluh,e4000e0, 2, (RIWR, RIWR), rd_rn),
16372 cCE(wunpckeluw,e8000e0, 2, (RIWR, RIWR), rd_rn),
16373 cCE(wunpckelsb,e2000e0, 2, (RIWR, RIWR), rd_rn),
16374 cCE(wunpckelsh,e6000e0, 2, (RIWR, RIWR), rd_rn),
16375 cCE(wunpckelsw,ea000e0, 2, (RIWR, RIWR), rd_rn),
16376 cCE(wunpckilb, e1000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16377 cCE(wunpckilh, e5000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16378 cCE(wunpckilw, e9000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16379 cCE(wxor, e100000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16380 cCE(wzero, e300000, 1, (RIWR), iwmmxt_wzero),
16383 #define ARM_VARIANT &arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
16384 cCE(torvscb, e13f190, 1, (RR), iwmmxt_tandorc),
16385 cCE(torvsch, e53f190, 1, (RR), iwmmxt_tandorc),
16386 cCE(torvscw, e93f190, 1, (RR), iwmmxt_tandorc),
16387 cCE(wabsb, e2001c0, 2, (RIWR, RIWR), rd_rn),
16388 cCE(wabsh, e6001c0, 2, (RIWR, RIWR), rd_rn),
16389 cCE(wabsw, ea001c0, 2, (RIWR, RIWR), rd_rn),
16390 cCE(wabsdiffb, e1001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16391 cCE(wabsdiffh, e5001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16392 cCE(wabsdiffw, e9001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16393 cCE(waddbhusl, e2001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16394 cCE(waddbhusm, e6001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16395 cCE(waddhc, e600180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16396 cCE(waddwc, ea00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16397 cCE(waddsubhx, ea001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16398 cCE(wavg4, e400000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16399 cCE(wavg4r, e500000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16400 cCE(wmaddsn, ee00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16401 cCE(wmaddsx, eb00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16402 cCE(wmaddun, ec00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16403 cCE(wmaddux, e900100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16404 cCE(wmerge, e000080, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_wmerge),
16405 cCE(wmiabb, e0000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16406 cCE(wmiabt, e1000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16407 cCE(wmiatb, e2000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16408 cCE(wmiatt, e3000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16409 cCE(wmiabbn, e4000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16410 cCE(wmiabtn, e5000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16411 cCE(wmiatbn, e6000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16412 cCE(wmiattn, e7000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16413 cCE(wmiawbb, e800120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16414 cCE(wmiawbt, e900120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16415 cCE(wmiawtb, ea00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16416 cCE(wmiawtt, eb00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16417 cCE(wmiawbbn, ec00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16418 cCE(wmiawbtn, ed00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16419 cCE(wmiawtbn, ee00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16420 cCE(wmiawttn, ef00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16421 cCE(wmulsmr, ef00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16422 cCE(wmulumr, ed00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16423 cCE(wmulwumr, ec000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16424 cCE(wmulwsmr, ee000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16425 cCE(wmulwum, ed000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16426 cCE(wmulwsm, ef000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16427 cCE(wmulwl, eb000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16428 cCE(wqmiabb, e8000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16429 cCE(wqmiabt, e9000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16430 cCE(wqmiatb, ea000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16431 cCE(wqmiatt, eb000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16432 cCE(wqmiabbn, ec000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16433 cCE(wqmiabtn, ed000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16434 cCE(wqmiatbn, ee000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16435 cCE(wqmiattn, ef000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16436 cCE(wqmulm, e100080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16437 cCE(wqmulmr, e300080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16438 cCE(wqmulwm, ec000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16439 cCE(wqmulwmr, ee000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16440 cCE(wsubaddhx, ed001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
16443 #define ARM_VARIANT &arm_cext_maverick /* Cirrus Maverick instructions. */
16444 cCE(cfldrs, c100400, 2, (RMF, ADDRGLDC), rd_cpaddr),
16445 cCE(cfldrd, c500400, 2, (RMD, ADDRGLDC), rd_cpaddr),
16446 cCE(cfldr32, c100500, 2, (RMFX, ADDRGLDC), rd_cpaddr),
16447 cCE(cfldr64, c500500, 2, (RMDX, ADDRGLDC), rd_cpaddr),
16448 cCE(cfstrs, c000400, 2, (RMF, ADDRGLDC), rd_cpaddr),
16449 cCE(cfstrd, c400400, 2, (RMD, ADDRGLDC), rd_cpaddr),
16450 cCE(cfstr32, c000500, 2, (RMFX, ADDRGLDC), rd_cpaddr),
16451 cCE(cfstr64, c400500, 2, (RMDX, ADDRGLDC), rd_cpaddr),
16452 cCE(cfmvsr, e000450, 2, (RMF, RR), rn_rd),
16453 cCE(cfmvrs, e100450, 2, (RR, RMF), rd_rn),
16454 cCE(cfmvdlr, e000410, 2, (RMD, RR), rn_rd),
16455 cCE(cfmvrdl, e100410, 2, (RR, RMD), rd_rn),
16456 cCE(cfmvdhr, e000430, 2, (RMD, RR), rn_rd),
16457 cCE(cfmvrdh, e100430, 2, (RR, RMD), rd_rn),
16458 cCE(cfmv64lr, e000510, 2, (RMDX, RR), rn_rd),
16459 cCE(cfmvr64l, e100510, 2, (RR, RMDX), rd_rn),
16460 cCE(cfmv64hr, e000530, 2, (RMDX, RR), rn_rd),
16461 cCE(cfmvr64h, e100530, 2, (RR, RMDX), rd_rn),
16462 cCE(cfmval32, e200440, 2, (RMAX, RMFX), rd_rn),
16463 cCE(cfmv32al, e100440, 2, (RMFX, RMAX), rd_rn),
16464 cCE(cfmvam32, e200460, 2, (RMAX, RMFX), rd_rn),
16465 cCE(cfmv32am, e100460, 2, (RMFX, RMAX), rd_rn),
16466 cCE(cfmvah32, e200480, 2, (RMAX, RMFX), rd_rn),
16467 cCE(cfmv32ah, e100480, 2, (RMFX, RMAX), rd_rn),
16468 cCE(cfmva32, e2004a0, 2, (RMAX, RMFX), rd_rn),
16469 cCE(cfmv32a, e1004a0, 2, (RMFX, RMAX), rd_rn),
16470 cCE(cfmva64, e2004c0, 2, (RMAX, RMDX), rd_rn),
16471 cCE(cfmv64a, e1004c0, 2, (RMDX, RMAX), rd_rn),
16472 cCE(cfmvsc32, e2004e0, 2, (RMDS, RMDX), mav_dspsc),
16473 cCE(cfmv32sc, e1004e0, 2, (RMDX, RMDS), rd),
16474 cCE(cfcpys, e000400, 2, (RMF, RMF), rd_rn),
16475 cCE(cfcpyd, e000420, 2, (RMD, RMD), rd_rn),
16476 cCE(cfcvtsd, e000460, 2, (RMD, RMF), rd_rn),
16477 cCE(cfcvtds, e000440, 2, (RMF, RMD), rd_rn),
16478 cCE(cfcvt32s, e000480, 2, (RMF, RMFX), rd_rn),
16479 cCE(cfcvt32d, e0004a0, 2, (RMD, RMFX), rd_rn),
16480 cCE(cfcvt64s, e0004c0, 2, (RMF, RMDX), rd_rn),
16481 cCE(cfcvt64d, e0004e0, 2, (RMD, RMDX), rd_rn),
16482 cCE(cfcvts32, e100580, 2, (RMFX, RMF), rd_rn),
16483 cCE(cfcvtd32, e1005a0, 2, (RMFX, RMD), rd_rn),
16484 cCE(cftruncs32,e1005c0, 2, (RMFX, RMF), rd_rn),
16485 cCE(cftruncd32,e1005e0, 2, (RMFX, RMD), rd_rn),
16486 cCE(cfrshl32, e000550, 3, (RMFX, RMFX, RR), mav_triple),
16487 cCE(cfrshl64, e000570, 3, (RMDX, RMDX, RR), mav_triple),
16488 cCE(cfsh32, e000500, 3, (RMFX, RMFX, I63s), mav_shift),
16489 cCE(cfsh64, e200500, 3, (RMDX, RMDX, I63s), mav_shift),
16490 cCE(cfcmps, e100490, 3, (RR, RMF, RMF), rd_rn_rm),
16491 cCE(cfcmpd, e1004b0, 3, (RR, RMD, RMD), rd_rn_rm),
16492 cCE(cfcmp32, e100590, 3, (RR, RMFX, RMFX), rd_rn_rm),
16493 cCE(cfcmp64, e1005b0, 3, (RR, RMDX, RMDX), rd_rn_rm),
16494 cCE(cfabss, e300400, 2, (RMF, RMF), rd_rn),
16495 cCE(cfabsd, e300420, 2, (RMD, RMD), rd_rn),
16496 cCE(cfnegs, e300440, 2, (RMF, RMF), rd_rn),
16497 cCE(cfnegd, e300460, 2, (RMD, RMD), rd_rn),
16498 cCE(cfadds, e300480, 3, (RMF, RMF, RMF), rd_rn_rm),
16499 cCE(cfaddd, e3004a0, 3, (RMD, RMD, RMD), rd_rn_rm),
16500 cCE(cfsubs, e3004c0, 3, (RMF, RMF, RMF), rd_rn_rm),
16501 cCE(cfsubd, e3004e0, 3, (RMD, RMD, RMD), rd_rn_rm),
16502 cCE(cfmuls, e100400, 3, (RMF, RMF, RMF), rd_rn_rm),
16503 cCE(cfmuld, e100420, 3, (RMD, RMD, RMD), rd_rn_rm),
16504 cCE(cfabs32, e300500, 2, (RMFX, RMFX), rd_rn),
16505 cCE(cfabs64, e300520, 2, (RMDX, RMDX), rd_rn),
16506 cCE(cfneg32, e300540, 2, (RMFX, RMFX), rd_rn),
16507 cCE(cfneg64, e300560, 2, (RMDX, RMDX), rd_rn),
16508 cCE(cfadd32, e300580, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
16509 cCE(cfadd64, e3005a0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
16510 cCE(cfsub32, e3005c0, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
16511 cCE(cfsub64, e3005e0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
16512 cCE(cfmul32, e100500, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
16513 cCE(cfmul64, e100520, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
16514 cCE(cfmac32, e100540, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
16515 cCE(cfmsc32, e100560, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
16516 cCE(cfmadd32, e000600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
16517 cCE(cfmsub32, e100600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
16518 cCE(cfmadda32, e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
16519 cCE(cfmsuba32, e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
16522 #undef THUMB_VARIANT
16549 /* MD interface: bits in the object file. */
16551 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
16552 for use in the a.out file, and stores them in the array pointed to by buf.
16553 This knows about the endian-ness of the target machine and does
16554 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
16555 2 (short) and 4 (long) Floating numbers are put out as a series of
16556 LITTLENUMS (shorts, here at least). */
16559 md_number_to_chars (char * buf, valueT val, int n)
16561 if (target_big_endian)
16562 number_to_chars_bigendian (buf, val, n);
16564 number_to_chars_littleendian (buf, val, n);
16568 md_chars_to_number (char * buf, int n)
16571 unsigned char * where = (unsigned char *) buf;
16573 if (target_big_endian)
16578 result |= (*where++ & 255);
16586 result |= (where[n] & 255);
16593 /* MD interface: Sections. */
16595 /* Estimate the size of a frag before relaxing. Assume everything fits in
16599 md_estimate_size_before_relax (fragS * fragp,
16600 segT segtype ATTRIBUTE_UNUSED)
16606 /* Convert a machine dependent frag. */
16609 md_convert_frag (bfd *abfd, segT asec ATTRIBUTE_UNUSED, fragS *fragp)
16611 unsigned long insn;
16612 unsigned long old_op;
16620 buf = fragp->fr_literal + fragp->fr_fix;
16622 old_op = bfd_get_16(abfd, buf);
16623 if (fragp->fr_symbol) {
16624 exp.X_op = O_symbol;
16625 exp.X_add_symbol = fragp->fr_symbol;
16627 exp.X_op = O_constant;
16629 exp.X_add_number = fragp->fr_offset;
16630 opcode = fragp->fr_subtype;
16633 case T_MNEM_ldr_pc:
16634 case T_MNEM_ldr_pc2:
16635 case T_MNEM_ldr_sp:
16636 case T_MNEM_str_sp:
16643 if (fragp->fr_var == 4)
16645 insn = THUMB_OP32(opcode);
16646 if ((old_op >> 12) == 4 || (old_op >> 12) == 9)
16648 insn |= (old_op & 0x700) << 4;
16652 insn |= (old_op & 7) << 12;
16653 insn |= (old_op & 0x38) << 13;
16655 insn |= 0x00000c00;
16656 put_thumb32_insn (buf, insn);
16657 reloc_type = BFD_RELOC_ARM_T32_OFFSET_IMM;
16661 reloc_type = BFD_RELOC_ARM_THUMB_OFFSET;
16663 pc_rel = (opcode == T_MNEM_ldr_pc2);
16666 if (fragp->fr_var == 4)
16668 insn = THUMB_OP32 (opcode);
16669 insn |= (old_op & 0xf0) << 4;
16670 put_thumb32_insn (buf, insn);
16671 reloc_type = BFD_RELOC_ARM_T32_ADD_PC12;
16675 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
16676 exp.X_add_number -= 4;
16684 if (fragp->fr_var == 4)
16686 int r0off = (opcode == T_MNEM_mov
16687 || opcode == T_MNEM_movs) ? 0 : 8;
16688 insn = THUMB_OP32 (opcode);
16689 insn = (insn & 0xe1ffffff) | 0x10000000;
16690 insn |= (old_op & 0x700) << r0off;
16691 put_thumb32_insn (buf, insn);
16692 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
16696 reloc_type = BFD_RELOC_ARM_THUMB_IMM;
16701 if (fragp->fr_var == 4)
16703 insn = THUMB_OP32(opcode);
16704 put_thumb32_insn (buf, insn);
16705 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH25;
16708 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH12;
16712 if (fragp->fr_var == 4)
16714 insn = THUMB_OP32(opcode);
16715 insn |= (old_op & 0xf00) << 14;
16716 put_thumb32_insn (buf, insn);
16717 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH20;
16720 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH9;
16723 case T_MNEM_add_sp:
16724 case T_MNEM_add_pc:
16725 case T_MNEM_inc_sp:
16726 case T_MNEM_dec_sp:
16727 if (fragp->fr_var == 4)
16729 /* ??? Choose between add and addw. */
16730 insn = THUMB_OP32 (opcode);
16731 insn |= (old_op & 0xf0) << 4;
16732 put_thumb32_insn (buf, insn);
16733 if (opcode == T_MNEM_add_pc)
16734 reloc_type = BFD_RELOC_ARM_T32_IMM12;
16736 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM;
16739 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
16747 if (fragp->fr_var == 4)
16749 insn = THUMB_OP32 (opcode);
16750 insn |= (old_op & 0xf0) << 4;
16751 insn |= (old_op & 0xf) << 16;
16752 put_thumb32_insn (buf, insn);
16753 if (insn & (1 << 20))
16754 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM;
16756 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
16759 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
16765 fixp = fix_new_exp (fragp, fragp->fr_fix, fragp->fr_var, &exp, pc_rel,
16767 fixp->fx_file = fragp->fr_file;
16768 fixp->fx_line = fragp->fr_line;
16769 fragp->fr_fix += fragp->fr_var;
16772 /* Return the size of a relaxable immediate operand instruction.
16773 SHIFT and SIZE specify the form of the allowable immediate. */
16775 relax_immediate (fragS *fragp, int size, int shift)
16781 /* ??? Should be able to do better than this. */
16782 if (fragp->fr_symbol)
16785 low = (1 << shift) - 1;
16786 mask = (1 << (shift + size)) - (1 << shift);
16787 offset = fragp->fr_offset;
16788 /* Force misaligned offsets to 32-bit variant. */
16791 if (offset & ~mask)
16796 /* Get the address of a symbol during relaxation. */
16798 relaxed_symbol_addr(fragS *fragp, long stretch)
16804 sym = fragp->fr_symbol;
16805 sym_frag = symbol_get_frag (sym);
16806 know (S_GET_SEGMENT (sym) != absolute_section
16807 || sym_frag == &zero_address_frag);
16808 addr = S_GET_VALUE (sym) + fragp->fr_offset;
16810 /* If frag has yet to be reached on this pass, assume it will
16811 move by STRETCH just as we did. If this is not so, it will
16812 be because some frag between grows, and that will force
16816 && sym_frag->relax_marker != fragp->relax_marker)
16822 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
16825 relax_adr (fragS *fragp, asection *sec, long stretch)
16830 /* Assume worst case for symbols not known to be in the same section. */
16831 if (!S_IS_DEFINED(fragp->fr_symbol)
16832 || sec != S_GET_SEGMENT (fragp->fr_symbol))
16835 val = relaxed_symbol_addr(fragp, stretch);
16836 addr = fragp->fr_address + fragp->fr_fix;
16837 addr = (addr + 4) & ~3;
16838 /* Force misaligned targets to 32-bit variant. */
16842 if (val < 0 || val > 1020)
16847 /* Return the size of a relaxable add/sub immediate instruction. */
16849 relax_addsub (fragS *fragp, asection *sec)
16854 buf = fragp->fr_literal + fragp->fr_fix;
16855 op = bfd_get_16(sec->owner, buf);
16856 if ((op & 0xf) == ((op >> 4) & 0xf))
16857 return relax_immediate (fragp, 8, 0);
16859 return relax_immediate (fragp, 3, 0);
16863 /* Return the size of a relaxable branch instruction. BITS is the
16864 size of the offset field in the narrow instruction. */
16867 relax_branch (fragS *fragp, asection *sec, int bits, long stretch)
16873 /* Assume worst case for symbols not known to be in the same section. */
16874 if (!S_IS_DEFINED(fragp->fr_symbol)
16875 || sec != S_GET_SEGMENT (fragp->fr_symbol))
16878 val = relaxed_symbol_addr(fragp, stretch);
16879 addr = fragp->fr_address + fragp->fr_fix + 4;
16882 /* Offset is a signed value *2 */
16884 if (val >= limit || val < -limit)
16890 /* Relax a machine dependent frag. This returns the amount by which
16891 the current size of the frag should change. */
16894 arm_relax_frag (asection *sec, fragS *fragp, long stretch)
16899 oldsize = fragp->fr_var;
16900 switch (fragp->fr_subtype)
16902 case T_MNEM_ldr_pc2:
16903 newsize = relax_adr(fragp, sec, stretch);
16905 case T_MNEM_ldr_pc:
16906 case T_MNEM_ldr_sp:
16907 case T_MNEM_str_sp:
16908 newsize = relax_immediate(fragp, 8, 2);
16912 newsize = relax_immediate(fragp, 5, 2);
16916 newsize = relax_immediate(fragp, 5, 1);
16920 newsize = relax_immediate(fragp, 5, 0);
16923 newsize = relax_adr(fragp, sec, stretch);
16929 newsize = relax_immediate(fragp, 8, 0);
16932 newsize = relax_branch(fragp, sec, 11, stretch);
16935 newsize = relax_branch(fragp, sec, 8, stretch);
16937 case T_MNEM_add_sp:
16938 case T_MNEM_add_pc:
16939 newsize = relax_immediate (fragp, 8, 2);
16941 case T_MNEM_inc_sp:
16942 case T_MNEM_dec_sp:
16943 newsize = relax_immediate (fragp, 7, 2);
16949 newsize = relax_addsub (fragp, sec);
16955 fragp->fr_var = newsize;
16956 /* Freeze wide instructions that are at or before the same location as
16957 in the previous pass. This avoids infinite loops.
16958 Don't freeze them unconditionally because targets may be artificialy
16959 misaligned by the expansion of preceeding frags. */
16960 if (stretch <= 0 && newsize > 2)
16962 md_convert_frag (sec->owner, sec, fragp);
16966 return newsize - oldsize;
16969 /* Round up a section size to the appropriate boundary. */
16972 md_section_align (segT segment ATTRIBUTE_UNUSED,
16975 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
16976 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
16978 /* For a.out, force the section size to be aligned. If we don't do
16979 this, BFD will align it for us, but it will not write out the
16980 final bytes of the section. This may be a bug in BFD, but it is
16981 easier to fix it here since that is how the other a.out targets
16985 align = bfd_get_section_alignment (stdoutput, segment);
16986 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
16993 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
16994 of an rs_align_code fragment. */
16997 arm_handle_align (fragS * fragP)
16999 static char const arm_noop[4] = { 0x00, 0x00, 0xa0, 0xe1 };
17000 static char const thumb_noop[2] = { 0xc0, 0x46 };
17001 static char const arm_bigend_noop[4] = { 0xe1, 0xa0, 0x00, 0x00 };
17002 static char const thumb_bigend_noop[2] = { 0x46, 0xc0 };
17004 int bytes, fix, noop_size;
17008 if (fragP->fr_type != rs_align_code)
17011 bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix;
17012 p = fragP->fr_literal + fragP->fr_fix;
17015 if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE)
17016 bytes &= MAX_MEM_FOR_RS_ALIGN_CODE;
17018 if (fragP->tc_frag_data)
17020 if (target_big_endian)
17021 noop = thumb_bigend_noop;
17024 noop_size = sizeof (thumb_noop);
17028 if (target_big_endian)
17029 noop = arm_bigend_noop;
17032 noop_size = sizeof (arm_noop);
17035 if (bytes & (noop_size - 1))
17037 fix = bytes & (noop_size - 1);
17038 memset (p, 0, fix);
17043 while (bytes >= noop_size)
17045 memcpy (p, noop, noop_size);
17047 bytes -= noop_size;
17051 fragP->fr_fix += fix;
17052 fragP->fr_var = noop_size;
17055 /* Called from md_do_align. Used to create an alignment
17056 frag in a code section. */
17059 arm_frag_align_code (int n, int max)
17063 /* We assume that there will never be a requirement
17064 to support alignments greater than 32 bytes. */
17065 if (max > MAX_MEM_FOR_RS_ALIGN_CODE)
17066 as_fatal (_("alignments greater than 32 bytes not supported in .text sections."));
17068 p = frag_var (rs_align_code,
17069 MAX_MEM_FOR_RS_ALIGN_CODE,
17071 (relax_substateT) max,
17078 /* Perform target specific initialisation of a frag. */
17081 arm_init_frag (fragS * fragP)
17083 /* Record whether this frag is in an ARM or a THUMB area. */
17084 fragP->tc_frag_data = thumb_mode;
17088 /* When we change sections we need to issue a new mapping symbol. */
17091 arm_elf_change_section (void)
17094 segment_info_type *seginfo;
17096 /* Link an unlinked unwind index table section to the .text section. */
17097 if (elf_section_type (now_seg) == SHT_ARM_EXIDX
17098 && elf_linked_to_section (now_seg) == NULL)
17099 elf_linked_to_section (now_seg) = text_section;
17101 if (!SEG_NORMAL (now_seg))
17104 flags = bfd_get_section_flags (stdoutput, now_seg);
17106 /* We can ignore sections that only contain debug info. */
17107 if ((flags & SEC_ALLOC) == 0)
17110 seginfo = seg_info (now_seg);
17111 mapstate = seginfo->tc_segment_info_data.mapstate;
17112 marked_pr_dependency = seginfo->tc_segment_info_data.marked_pr_dependency;
17116 arm_elf_section_type (const char * str, size_t len)
17118 if (len == 5 && strncmp (str, "exidx", 5) == 0)
17119 return SHT_ARM_EXIDX;
17124 /* Code to deal with unwinding tables. */
17126 static void add_unwind_adjustsp (offsetT);
17128 /* Cenerate and deferred unwind frame offset. */
17131 flush_pending_unwind (void)
17135 offset = unwind.pending_offset;
17136 unwind.pending_offset = 0;
17138 add_unwind_adjustsp (offset);
17141 /* Add an opcode to this list for this function. Two-byte opcodes should
17142 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
17146 add_unwind_opcode (valueT op, int length)
17148 /* Add any deferred stack adjustment. */
17149 if (unwind.pending_offset)
17150 flush_pending_unwind ();
17152 unwind.sp_restored = 0;
17154 if (unwind.opcode_count + length > unwind.opcode_alloc)
17156 unwind.opcode_alloc += ARM_OPCODE_CHUNK_SIZE;
17157 if (unwind.opcodes)
17158 unwind.opcodes = xrealloc (unwind.opcodes,
17159 unwind.opcode_alloc);
17161 unwind.opcodes = xmalloc (unwind.opcode_alloc);
17166 unwind.opcodes[unwind.opcode_count] = op & 0xff;
17168 unwind.opcode_count++;
17172 /* Add unwind opcodes to adjust the stack pointer. */
17175 add_unwind_adjustsp (offsetT offset)
17179 if (offset > 0x200)
17181 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
17186 /* Long form: 0xb2, uleb128. */
17187 /* This might not fit in a word so add the individual bytes,
17188 remembering the list is built in reverse order. */
17189 o = (valueT) ((offset - 0x204) >> 2);
17191 add_unwind_opcode (0, 1);
17193 /* Calculate the uleb128 encoding of the offset. */
17197 bytes[n] = o & 0x7f;
17203 /* Add the insn. */
17205 add_unwind_opcode (bytes[n - 1], 1);
17206 add_unwind_opcode (0xb2, 1);
17208 else if (offset > 0x100)
17210 /* Two short opcodes. */
17211 add_unwind_opcode (0x3f, 1);
17212 op = (offset - 0x104) >> 2;
17213 add_unwind_opcode (op, 1);
17215 else if (offset > 0)
17217 /* Short opcode. */
17218 op = (offset - 4) >> 2;
17219 add_unwind_opcode (op, 1);
17221 else if (offset < 0)
17224 while (offset > 0x100)
17226 add_unwind_opcode (0x7f, 1);
17229 op = ((offset - 4) >> 2) | 0x40;
17230 add_unwind_opcode (op, 1);
17234 /* Finish the list of unwind opcodes for this function. */
17236 finish_unwind_opcodes (void)
17240 if (unwind.fp_used)
17242 /* Adjust sp as necessary. */
17243 unwind.pending_offset += unwind.fp_offset - unwind.frame_size;
17244 flush_pending_unwind ();
17246 /* After restoring sp from the frame pointer. */
17247 op = 0x90 | unwind.fp_reg;
17248 add_unwind_opcode (op, 1);
17251 flush_pending_unwind ();
17255 /* Start an exception table entry. If idx is nonzero this is an index table
17259 start_unwind_section (const segT text_seg, int idx)
17261 const char * text_name;
17262 const char * prefix;
17263 const char * prefix_once;
17264 const char * group_name;
17268 size_t sec_name_len;
17275 prefix = ELF_STRING_ARM_unwind;
17276 prefix_once = ELF_STRING_ARM_unwind_once;
17277 type = SHT_ARM_EXIDX;
17281 prefix = ELF_STRING_ARM_unwind_info;
17282 prefix_once = ELF_STRING_ARM_unwind_info_once;
17283 type = SHT_PROGBITS;
17286 text_name = segment_name (text_seg);
17287 if (streq (text_name, ".text"))
17290 if (strncmp (text_name, ".gnu.linkonce.t.",
17291 strlen (".gnu.linkonce.t.")) == 0)
17293 prefix = prefix_once;
17294 text_name += strlen (".gnu.linkonce.t.");
17297 prefix_len = strlen (prefix);
17298 text_len = strlen (text_name);
17299 sec_name_len = prefix_len + text_len;
17300 sec_name = xmalloc (sec_name_len + 1);
17301 memcpy (sec_name, prefix, prefix_len);
17302 memcpy (sec_name + prefix_len, text_name, text_len);
17303 sec_name[prefix_len + text_len] = '\0';
17309 /* Handle COMDAT group. */
17310 if (prefix != prefix_once && (text_seg->flags & SEC_LINK_ONCE) != 0)
17312 group_name = elf_group_name (text_seg);
17313 if (group_name == NULL)
17315 as_bad ("Group section `%s' has no group signature",
17316 segment_name (text_seg));
17317 ignore_rest_of_line ();
17320 flags |= SHF_GROUP;
17324 obj_elf_change_section (sec_name, type, flags, 0, group_name, linkonce, 0);
17326 /* Set the setion link for index tables. */
17328 elf_linked_to_section (now_seg) = text_seg;
17332 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
17333 personality routine data. Returns zero, or the index table value for
17334 and inline entry. */
17337 create_unwind_entry (int have_data)
17342 /* The current word of data. */
17344 /* The number of bytes left in this word. */
17347 finish_unwind_opcodes ();
17349 /* Remember the current text section. */
17350 unwind.saved_seg = now_seg;
17351 unwind.saved_subseg = now_subseg;
17353 start_unwind_section (now_seg, 0);
17355 if (unwind.personality_routine == NULL)
17357 if (unwind.personality_index == -2)
17360 as_bad (_("handerdata in cantunwind frame"));
17361 return 1; /* EXIDX_CANTUNWIND. */
17364 /* Use a default personality routine if none is specified. */
17365 if (unwind.personality_index == -1)
17367 if (unwind.opcode_count > 3)
17368 unwind.personality_index = 1;
17370 unwind.personality_index = 0;
17373 /* Space for the personality routine entry. */
17374 if (unwind.personality_index == 0)
17376 if (unwind.opcode_count > 3)
17377 as_bad (_("too many unwind opcodes for personality routine 0"));
17381 /* All the data is inline in the index table. */
17384 while (unwind.opcode_count > 0)
17386 unwind.opcode_count--;
17387 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
17391 /* Pad with "finish" opcodes. */
17393 data = (data << 8) | 0xb0;
17400 /* We get two opcodes "free" in the first word. */
17401 size = unwind.opcode_count - 2;
17404 /* An extra byte is required for the opcode count. */
17405 size = unwind.opcode_count + 1;
17407 size = (size + 3) >> 2;
17409 as_bad (_("too many unwind opcodes"));
17411 frag_align (2, 0, 0);
17412 record_alignment (now_seg, 2);
17413 unwind.table_entry = expr_build_dot ();
17415 /* Allocate the table entry. */
17416 ptr = frag_more ((size << 2) + 4);
17417 memset(ptr, 0, (size << 2) + 4);
17418 where = frag_now_fix () - ((size << 2) + 4);
17420 switch (unwind.personality_index)
17423 /* ??? Should this be a PLT generating relocation? */
17424 /* Custom personality routine. */
17425 fix_new (frag_now, where, 4, unwind.personality_routine, 0, 1,
17426 BFD_RELOC_ARM_PREL31);
17431 /* Set the first byte to the number of additional words. */
17436 /* ABI defined personality routines. */
17438 /* Three opcodes bytes are packed into the first word. */
17445 /* The size and first two opcode bytes go in the first word. */
17446 data = ((0x80 + unwind.personality_index) << 8) | size;
17451 /* Should never happen. */
17455 /* Pack the opcodes into words (MSB first), reversing the list at the same
17457 while (unwind.opcode_count > 0)
17461 md_number_to_chars (ptr, data, 4);
17466 unwind.opcode_count--;
17468 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
17471 /* Finish off the last word. */
17474 /* Pad with "finish" opcodes. */
17476 data = (data << 8) | 0xb0;
17478 md_number_to_chars (ptr, data, 4);
17483 /* Add an empty descriptor if there is no user-specified data. */
17484 ptr = frag_more (4);
17485 md_number_to_chars (ptr, 0, 4);
17492 /* Initialize the DWARF-2 unwind information for this procedure. */
17495 tc_arm_frame_initial_instructions (void)
17497 cfi_add_CFA_def_cfa (REG_SP, 0);
17499 #endif /* OBJ_ELF */
17501 /* Convert REGNAME to a DWARF-2 register number. */
17504 tc_arm_regname_to_dw2regnum (char *regname)
17506 int reg = arm_reg_parse (®name, REG_TYPE_RN);
17516 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
17520 expr.X_op = O_secrel;
17521 expr.X_add_symbol = symbol;
17522 expr.X_add_number = 0;
17523 emit_expr (&expr, size);
17527 /* MD interface: Symbol and relocation handling. */
17529 /* Return the address within the segment that a PC-relative fixup is
17530 relative to. For ARM, PC-relative fixups applied to instructions
17531 are generally relative to the location of the fixup plus 8 bytes.
17532 Thumb branches are offset by 4, and Thumb loads relative to PC
17533 require special handling. */
17536 md_pcrel_from_section (fixS * fixP, segT seg)
17538 offsetT base = fixP->fx_where + fixP->fx_frag->fr_address;
17540 /* If this is pc-relative and we are going to emit a relocation
17541 then we just want to put out any pipeline compensation that the linker
17542 will need. Otherwise we want to use the calculated base.
17543 For WinCE we skip the bias for externals as well, since this
17544 is how the MS ARM-CE assembler behaves and we want to be compatible. */
17546 && ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg)
17547 || (arm_force_relocation (fixP)
17549 && !S_IS_EXTERNAL (fixP->fx_addsy)
17554 switch (fixP->fx_r_type)
17556 /* PC relative addressing on the Thumb is slightly odd as the
17557 bottom two bits of the PC are forced to zero for the
17558 calculation. This happens *after* application of the
17559 pipeline offset. However, Thumb adrl already adjusts for
17560 this, so we need not do it again. */
17561 case BFD_RELOC_ARM_THUMB_ADD:
17564 case BFD_RELOC_ARM_THUMB_OFFSET:
17565 case BFD_RELOC_ARM_T32_OFFSET_IMM:
17566 case BFD_RELOC_ARM_T32_ADD_PC12:
17567 case BFD_RELOC_ARM_T32_CP_OFF_IMM:
17568 return (base + 4) & ~3;
17570 /* Thumb branches are simply offset by +4. */
17571 case BFD_RELOC_THUMB_PCREL_BRANCH7:
17572 case BFD_RELOC_THUMB_PCREL_BRANCH9:
17573 case BFD_RELOC_THUMB_PCREL_BRANCH12:
17574 case BFD_RELOC_THUMB_PCREL_BRANCH20:
17575 case BFD_RELOC_THUMB_PCREL_BRANCH23:
17576 case BFD_RELOC_THUMB_PCREL_BRANCH25:
17577 case BFD_RELOC_THUMB_PCREL_BLX:
17580 /* ARM mode branches are offset by +8. However, the Windows CE
17581 loader expects the relocation not to take this into account. */
17582 case BFD_RELOC_ARM_PCREL_BRANCH:
17583 case BFD_RELOC_ARM_PCREL_CALL:
17584 case BFD_RELOC_ARM_PCREL_JUMP:
17585 case BFD_RELOC_ARM_PCREL_BLX:
17586 case BFD_RELOC_ARM_PLT32:
17588 /* When handling fixups immediately, because we have already
17589 discovered the value of a symbol, or the address of the frag involved
17590 we must account for the offset by +8, as the OS loader will never see the reloc.
17591 see fixup_segment() in write.c
17592 The S_IS_EXTERNAL test handles the case of global symbols.
17593 Those need the calculated base, not just the pipe compensation the linker will need. */
17595 && fixP->fx_addsy != NULL
17596 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
17597 && (S_IS_EXTERNAL (fixP->fx_addsy) || !arm_force_relocation (fixP)))
17604 /* ARM mode loads relative to PC are also offset by +8. Unlike
17605 branches, the Windows CE loader *does* expect the relocation
17606 to take this into account. */
17607 case BFD_RELOC_ARM_OFFSET_IMM:
17608 case BFD_RELOC_ARM_OFFSET_IMM8:
17609 case BFD_RELOC_ARM_HWLITERAL:
17610 case BFD_RELOC_ARM_LITERAL:
17611 case BFD_RELOC_ARM_CP_OFF_IMM:
17615 /* Other PC-relative relocations are un-offset. */
17621 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
17622 Otherwise we have no need to default values of symbols. */
17625 md_undefined_symbol (char * name ATTRIBUTE_UNUSED)
17628 if (name[0] == '_' && name[1] == 'G'
17629 && streq (name, GLOBAL_OFFSET_TABLE_NAME))
17633 if (symbol_find (name))
17634 as_bad ("GOT already in the symbol table");
17636 GOT_symbol = symbol_new (name, undefined_section,
17637 (valueT) 0, & zero_address_frag);
17647 /* Subroutine of md_apply_fix. Check to see if an immediate can be
17648 computed as two separate immediate values, added together. We
17649 already know that this value cannot be computed by just one ARM
17652 static unsigned int
17653 validate_immediate_twopart (unsigned int val,
17654 unsigned int * highpart)
17659 for (i = 0; i < 32; i += 2)
17660 if (((a = rotate_left (val, i)) & 0xff) != 0)
17666 * highpart = (a >> 8) | ((i + 24) << 7);
17668 else if (a & 0xff0000)
17670 if (a & 0xff000000)
17672 * highpart = (a >> 16) | ((i + 16) << 7);
17676 assert (a & 0xff000000);
17677 * highpart = (a >> 24) | ((i + 8) << 7);
17680 return (a & 0xff) | (i << 7);
17687 validate_offset_imm (unsigned int val, int hwse)
17689 if ((hwse && val > 255) || val > 4095)
17694 /* Subroutine of md_apply_fix. Do those data_ops which can take a
17695 negative immediate constant by altering the instruction. A bit of
17700 by inverting the second operand, and
17703 by negating the second operand. */
17706 negate_data_op (unsigned long * instruction,
17707 unsigned long value)
17710 unsigned long negated, inverted;
17712 negated = encode_arm_immediate (-value);
17713 inverted = encode_arm_immediate (~value);
17715 op = (*instruction >> DATA_OP_SHIFT) & 0xf;
17718 /* First negates. */
17719 case OPCODE_SUB: /* ADD <-> SUB */
17720 new_inst = OPCODE_ADD;
17725 new_inst = OPCODE_SUB;
17729 case OPCODE_CMP: /* CMP <-> CMN */
17730 new_inst = OPCODE_CMN;
17735 new_inst = OPCODE_CMP;
17739 /* Now Inverted ops. */
17740 case OPCODE_MOV: /* MOV <-> MVN */
17741 new_inst = OPCODE_MVN;
17746 new_inst = OPCODE_MOV;
17750 case OPCODE_AND: /* AND <-> BIC */
17751 new_inst = OPCODE_BIC;
17756 new_inst = OPCODE_AND;
17760 case OPCODE_ADC: /* ADC <-> SBC */
17761 new_inst = OPCODE_SBC;
17766 new_inst = OPCODE_ADC;
17770 /* We cannot do anything. */
17775 if (value == (unsigned) FAIL)
17778 *instruction &= OPCODE_MASK;
17779 *instruction |= new_inst << DATA_OP_SHIFT;
17783 /* Like negate_data_op, but for Thumb-2. */
17785 static unsigned int
17786 thumb32_negate_data_op (offsetT *instruction, unsigned int value)
17790 unsigned int negated, inverted;
17792 negated = encode_thumb32_immediate (-value);
17793 inverted = encode_thumb32_immediate (~value);
17795 rd = (*instruction >> 8) & 0xf;
17796 op = (*instruction >> T2_DATA_OP_SHIFT) & 0xf;
17799 /* ADD <-> SUB. Includes CMP <-> CMN. */
17800 case T2_OPCODE_SUB:
17801 new_inst = T2_OPCODE_ADD;
17805 case T2_OPCODE_ADD:
17806 new_inst = T2_OPCODE_SUB;
17810 /* ORR <-> ORN. Includes MOV <-> MVN. */
17811 case T2_OPCODE_ORR:
17812 new_inst = T2_OPCODE_ORN;
17816 case T2_OPCODE_ORN:
17817 new_inst = T2_OPCODE_ORR;
17821 /* AND <-> BIC. TST has no inverted equivalent. */
17822 case T2_OPCODE_AND:
17823 new_inst = T2_OPCODE_BIC;
17830 case T2_OPCODE_BIC:
17831 new_inst = T2_OPCODE_AND;
17836 case T2_OPCODE_ADC:
17837 new_inst = T2_OPCODE_SBC;
17841 case T2_OPCODE_SBC:
17842 new_inst = T2_OPCODE_ADC;
17846 /* We cannot do anything. */
17851 if (value == (unsigned int)FAIL)
17854 *instruction &= T2_OPCODE_MASK;
17855 *instruction |= new_inst << T2_DATA_OP_SHIFT;
17859 /* Read a 32-bit thumb instruction from buf. */
17860 static unsigned long
17861 get_thumb32_insn (char * buf)
17863 unsigned long insn;
17864 insn = md_chars_to_number (buf, THUMB_SIZE) << 16;
17865 insn |= md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
17871 /* We usually want to set the low bit on the address of thumb function
17872 symbols. In particular .word foo - . should have the low bit set.
17873 Generic code tries to fold the difference of two symbols to
17874 a constant. Prevent this and force a relocation when the first symbols
17875 is a thumb function. */
17877 arm_optimize_expr (expressionS *l, operatorT op, expressionS *r)
17879 if (op == O_subtract
17880 && l->X_op == O_symbol
17881 && r->X_op == O_symbol
17882 && THUMB_IS_FUNC (l->X_add_symbol))
17884 l->X_op = O_subtract;
17885 l->X_op_symbol = r->X_add_symbol;
17886 l->X_add_number -= r->X_add_number;
17889 /* Process as normal. */
17894 md_apply_fix (fixS * fixP,
17898 offsetT value = * valP;
17900 unsigned int newimm;
17901 unsigned long temp;
17903 char * buf = fixP->fx_where + fixP->fx_frag->fr_literal;
17905 assert (fixP->fx_r_type <= BFD_RELOC_UNUSED);
17907 /* Note whether this will delete the relocation. */
17909 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
17912 /* On a 64-bit host, silently truncate 'value' to 32 bits for
17913 consistency with the behavior on 32-bit hosts. Remember value
17915 value &= 0xffffffff;
17916 value ^= 0x80000000;
17917 value -= 0x80000000;
17920 fixP->fx_addnumber = value;
17922 /* Same treatment for fixP->fx_offset. */
17923 fixP->fx_offset &= 0xffffffff;
17924 fixP->fx_offset ^= 0x80000000;
17925 fixP->fx_offset -= 0x80000000;
17927 switch (fixP->fx_r_type)
17929 case BFD_RELOC_NONE:
17930 /* This will need to go in the object file. */
17934 case BFD_RELOC_ARM_IMMEDIATE:
17935 /* We claim that this fixup has been processed here,
17936 even if in fact we generate an error because we do
17937 not have a reloc for it, so tc_gen_reloc will reject it. */
17941 && ! S_IS_DEFINED (fixP->fx_addsy))
17943 as_bad_where (fixP->fx_file, fixP->fx_line,
17944 _("undefined symbol %s used as an immediate value"),
17945 S_GET_NAME (fixP->fx_addsy));
17949 newimm = encode_arm_immediate (value);
17950 temp = md_chars_to_number (buf, INSN_SIZE);
17952 /* If the instruction will fail, see if we can fix things up by
17953 changing the opcode. */
17954 if (newimm == (unsigned int) FAIL
17955 && (newimm = negate_data_op (&temp, value)) == (unsigned int) FAIL)
17957 as_bad_where (fixP->fx_file, fixP->fx_line,
17958 _("invalid constant (%lx) after fixup"),
17959 (unsigned long) value);
17963 newimm |= (temp & 0xfffff000);
17964 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
17967 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
17969 unsigned int highpart = 0;
17970 unsigned int newinsn = 0xe1a00000; /* nop. */
17972 newimm = encode_arm_immediate (value);
17973 temp = md_chars_to_number (buf, INSN_SIZE);
17975 /* If the instruction will fail, see if we can fix things up by
17976 changing the opcode. */
17977 if (newimm == (unsigned int) FAIL
17978 && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL)
17980 /* No ? OK - try using two ADD instructions to generate
17982 newimm = validate_immediate_twopart (value, & highpart);
17984 /* Yes - then make sure that the second instruction is
17986 if (newimm != (unsigned int) FAIL)
17988 /* Still No ? Try using a negated value. */
17989 else if ((newimm = validate_immediate_twopart (- value, & highpart)) != (unsigned int) FAIL)
17990 temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT;
17991 /* Otherwise - give up. */
17994 as_bad_where (fixP->fx_file, fixP->fx_line,
17995 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
18000 /* Replace the first operand in the 2nd instruction (which
18001 is the PC) with the destination register. We have
18002 already added in the PC in the first instruction and we
18003 do not want to do it again. */
18004 newinsn &= ~ 0xf0000;
18005 newinsn |= ((newinsn & 0x0f000) << 4);
18008 newimm |= (temp & 0xfffff000);
18009 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
18011 highpart |= (newinsn & 0xfffff000);
18012 md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE);
18016 case BFD_RELOC_ARM_OFFSET_IMM:
18017 if (!fixP->fx_done && seg->use_rela_p)
18020 case BFD_RELOC_ARM_LITERAL:
18026 if (validate_offset_imm (value, 0) == FAIL)
18028 if (fixP->fx_r_type == BFD_RELOC_ARM_LITERAL)
18029 as_bad_where (fixP->fx_file, fixP->fx_line,
18030 _("invalid literal constant: pool needs to be closer"));
18032 as_bad_where (fixP->fx_file, fixP->fx_line,
18033 _("bad immediate value for offset (%ld)"),
18038 newval = md_chars_to_number (buf, INSN_SIZE);
18039 newval &= 0xff7ff000;
18040 newval |= value | (sign ? INDEX_UP : 0);
18041 md_number_to_chars (buf, newval, INSN_SIZE);
18044 case BFD_RELOC_ARM_OFFSET_IMM8:
18045 case BFD_RELOC_ARM_HWLITERAL:
18051 if (validate_offset_imm (value, 1) == FAIL)
18053 if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL)
18054 as_bad_where (fixP->fx_file, fixP->fx_line,
18055 _("invalid literal constant: pool needs to be closer"));
18057 as_bad (_("bad immediate value for 8-bit offset (%ld)"),
18062 newval = md_chars_to_number (buf, INSN_SIZE);
18063 newval &= 0xff7ff0f0;
18064 newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0);
18065 md_number_to_chars (buf, newval, INSN_SIZE);
18068 case BFD_RELOC_ARM_T32_OFFSET_U8:
18069 if (value < 0 || value > 1020 || value % 4 != 0)
18070 as_bad_where (fixP->fx_file, fixP->fx_line,
18071 _("bad immediate value for offset (%ld)"), (long) value);
18074 newval = md_chars_to_number (buf+2, THUMB_SIZE);
18076 md_number_to_chars (buf+2, newval, THUMB_SIZE);
18079 case BFD_RELOC_ARM_T32_OFFSET_IMM:
18080 /* This is a complicated relocation used for all varieties of Thumb32
18081 load/store instruction with immediate offset:
18083 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
18084 *4, optional writeback(W)
18085 (doubleword load/store)
18087 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
18088 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
18089 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
18090 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
18091 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
18093 Uppercase letters indicate bits that are already encoded at
18094 this point. Lowercase letters are our problem. For the
18095 second block of instructions, the secondary opcode nybble
18096 (bits 8..11) is present, and bit 23 is zero, even if this is
18097 a PC-relative operation. */
18098 newval = md_chars_to_number (buf, THUMB_SIZE);
18100 newval |= md_chars_to_number (buf+THUMB_SIZE, THUMB_SIZE);
18102 if ((newval & 0xf0000000) == 0xe0000000)
18104 /* Doubleword load/store: 8-bit offset, scaled by 4. */
18106 newval |= (1 << 23);
18109 if (value % 4 != 0)
18111 as_bad_where (fixP->fx_file, fixP->fx_line,
18112 _("offset not a multiple of 4"));
18118 as_bad_where (fixP->fx_file, fixP->fx_line,
18119 _("offset out of range"));
18124 else if ((newval & 0x000f0000) == 0x000f0000)
18126 /* PC-relative, 12-bit offset. */
18128 newval |= (1 << 23);
18133 as_bad_where (fixP->fx_file, fixP->fx_line,
18134 _("offset out of range"));
18139 else if ((newval & 0x00000100) == 0x00000100)
18141 /* Writeback: 8-bit, +/- offset. */
18143 newval |= (1 << 9);
18148 as_bad_where (fixP->fx_file, fixP->fx_line,
18149 _("offset out of range"));
18154 else if ((newval & 0x00000f00) == 0x00000e00)
18156 /* T-instruction: positive 8-bit offset. */
18157 if (value < 0 || value > 0xff)
18159 as_bad_where (fixP->fx_file, fixP->fx_line,
18160 _("offset out of range"));
18168 /* Positive 12-bit or negative 8-bit offset. */
18172 newval |= (1 << 23);
18182 as_bad_where (fixP->fx_file, fixP->fx_line,
18183 _("offset out of range"));
18190 md_number_to_chars (buf, (newval >> 16) & 0xffff, THUMB_SIZE);
18191 md_number_to_chars (buf + THUMB_SIZE, newval & 0xffff, THUMB_SIZE);
18194 case BFD_RELOC_ARM_SHIFT_IMM:
18195 newval = md_chars_to_number (buf, INSN_SIZE);
18196 if (((unsigned long) value) > 32
18198 && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60)))
18200 as_bad_where (fixP->fx_file, fixP->fx_line,
18201 _("shift expression is too large"));
18206 /* Shifts of zero must be done as lsl. */
18208 else if (value == 32)
18210 newval &= 0xfffff07f;
18211 newval |= (value & 0x1f) << 7;
18212 md_number_to_chars (buf, newval, INSN_SIZE);
18215 case BFD_RELOC_ARM_T32_IMMEDIATE:
18216 case BFD_RELOC_ARM_T32_ADD_IMM:
18217 case BFD_RELOC_ARM_T32_IMM12:
18218 case BFD_RELOC_ARM_T32_ADD_PC12:
18219 /* We claim that this fixup has been processed here,
18220 even if in fact we generate an error because we do
18221 not have a reloc for it, so tc_gen_reloc will reject it. */
18225 && ! S_IS_DEFINED (fixP->fx_addsy))
18227 as_bad_where (fixP->fx_file, fixP->fx_line,
18228 _("undefined symbol %s used as an immediate value"),
18229 S_GET_NAME (fixP->fx_addsy));
18233 newval = md_chars_to_number (buf, THUMB_SIZE);
18235 newval |= md_chars_to_number (buf+2, THUMB_SIZE);
18238 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
18239 || fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM)
18241 newimm = encode_thumb32_immediate (value);
18242 if (newimm == (unsigned int) FAIL)
18243 newimm = thumb32_negate_data_op (&newval, value);
18245 if (fixP->fx_r_type != BFD_RELOC_ARM_T32_IMMEDIATE
18246 && newimm == (unsigned int) FAIL)
18248 /* Turn add/sum into addw/subw. */
18249 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM)
18250 newval = (newval & 0xfeffffff) | 0x02000000;
18252 /* 12 bit immediate for addw/subw. */
18256 newval ^= 0x00a00000;
18259 newimm = (unsigned int) FAIL;
18264 if (newimm == (unsigned int)FAIL)
18266 as_bad_where (fixP->fx_file, fixP->fx_line,
18267 _("invalid constant (%lx) after fixup"),
18268 (unsigned long) value);
18272 newval |= (newimm & 0x800) << 15;
18273 newval |= (newimm & 0x700) << 4;
18274 newval |= (newimm & 0x0ff);
18276 md_number_to_chars (buf, (valueT) ((newval >> 16) & 0xffff), THUMB_SIZE);
18277 md_number_to_chars (buf+2, (valueT) (newval & 0xffff), THUMB_SIZE);
18280 case BFD_RELOC_ARM_SMC:
18281 if (((unsigned long) value) > 0xffff)
18282 as_bad_where (fixP->fx_file, fixP->fx_line,
18283 _("invalid smc expression"));
18284 newval = md_chars_to_number (buf, INSN_SIZE);
18285 newval |= (value & 0xf) | ((value & 0xfff0) << 4);
18286 md_number_to_chars (buf, newval, INSN_SIZE);
18289 case BFD_RELOC_ARM_SWI:
18290 if (fixP->tc_fix_data != 0)
18292 if (((unsigned long) value) > 0xff)
18293 as_bad_where (fixP->fx_file, fixP->fx_line,
18294 _("invalid swi expression"));
18295 newval = md_chars_to_number (buf, THUMB_SIZE);
18297 md_number_to_chars (buf, newval, THUMB_SIZE);
18301 if (((unsigned long) value) > 0x00ffffff)
18302 as_bad_where (fixP->fx_file, fixP->fx_line,
18303 _("invalid swi expression"));
18304 newval = md_chars_to_number (buf, INSN_SIZE);
18306 md_number_to_chars (buf, newval, INSN_SIZE);
18310 case BFD_RELOC_ARM_MULTI:
18311 if (((unsigned long) value) > 0xffff)
18312 as_bad_where (fixP->fx_file, fixP->fx_line,
18313 _("invalid expression in load/store multiple"));
18314 newval = value | md_chars_to_number (buf, INSN_SIZE);
18315 md_number_to_chars (buf, newval, INSN_SIZE);
18319 case BFD_RELOC_ARM_PCREL_CALL:
18320 newval = md_chars_to_number (buf, INSN_SIZE);
18321 if ((newval & 0xf0000000) == 0xf0000000)
18325 goto arm_branch_common;
18327 case BFD_RELOC_ARM_PCREL_JUMP:
18328 case BFD_RELOC_ARM_PLT32:
18330 case BFD_RELOC_ARM_PCREL_BRANCH:
18332 goto arm_branch_common;
18334 case BFD_RELOC_ARM_PCREL_BLX:
18337 /* We are going to store value (shifted right by two) in the
18338 instruction, in a 24 bit, signed field. Bits 26 through 32 either
18339 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
18340 also be be clear. */
18342 as_bad_where (fixP->fx_file, fixP->fx_line,
18343 _("misaligned branch destination"));
18344 if ((value & (offsetT)0xfe000000) != (offsetT)0
18345 && (value & (offsetT)0xfe000000) != (offsetT)0xfe000000)
18346 as_bad_where (fixP->fx_file, fixP->fx_line,
18347 _("branch out of range"));
18349 if (fixP->fx_done || !seg->use_rela_p)
18351 newval = md_chars_to_number (buf, INSN_SIZE);
18352 newval |= (value >> 2) & 0x00ffffff;
18353 /* Set the H bit on BLX instructions. */
18357 newval |= 0x01000000;
18359 newval &= ~0x01000000;
18361 md_number_to_chars (buf, newval, INSN_SIZE);
18365 case BFD_RELOC_THUMB_PCREL_BRANCH7: /* CBZ */
18366 /* CBZ can only branch forward. */
18368 /* Attempts to use CBZ to branch to the next instruction
18369 (which, strictly speaking, are prohibited) will be turned into
18372 FIXME: It may be better to remove the instruction completely and
18373 perform relaxation. */
18376 newval = md_chars_to_number (buf, THUMB_SIZE);
18377 newval = 0xbf00; /* NOP encoding T1 */
18378 md_number_to_chars (buf, newval, THUMB_SIZE);
18383 as_bad_where (fixP->fx_file, fixP->fx_line,
18384 _("branch out of range"));
18386 if (fixP->fx_done || !seg->use_rela_p)
18388 newval = md_chars_to_number (buf, THUMB_SIZE);
18389 newval |= ((value & 0x3e) << 2) | ((value & 0x40) << 3);
18390 md_number_to_chars (buf, newval, THUMB_SIZE);
18395 case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */
18396 if ((value & ~0xff) && ((value & ~0xff) != ~0xff))
18397 as_bad_where (fixP->fx_file, fixP->fx_line,
18398 _("branch out of range"));
18400 if (fixP->fx_done || !seg->use_rela_p)
18402 newval = md_chars_to_number (buf, THUMB_SIZE);
18403 newval |= (value & 0x1ff) >> 1;
18404 md_number_to_chars (buf, newval, THUMB_SIZE);
18408 case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch. */
18409 if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff))
18410 as_bad_where (fixP->fx_file, fixP->fx_line,
18411 _("branch out of range"));
18413 if (fixP->fx_done || !seg->use_rela_p)
18415 newval = md_chars_to_number (buf, THUMB_SIZE);
18416 newval |= (value & 0xfff) >> 1;
18417 md_number_to_chars (buf, newval, THUMB_SIZE);
18421 case BFD_RELOC_THUMB_PCREL_BRANCH20:
18422 if ((value & ~0x1fffff) && ((value & ~0x1fffff) != ~0x1fffff))
18423 as_bad_where (fixP->fx_file, fixP->fx_line,
18424 _("conditional branch out of range"));
18426 if (fixP->fx_done || !seg->use_rela_p)
18429 addressT S, J1, J2, lo, hi;
18431 S = (value & 0x00100000) >> 20;
18432 J2 = (value & 0x00080000) >> 19;
18433 J1 = (value & 0x00040000) >> 18;
18434 hi = (value & 0x0003f000) >> 12;
18435 lo = (value & 0x00000ffe) >> 1;
18437 newval = md_chars_to_number (buf, THUMB_SIZE);
18438 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
18439 newval |= (S << 10) | hi;
18440 newval2 |= (J1 << 13) | (J2 << 11) | lo;
18441 md_number_to_chars (buf, newval, THUMB_SIZE);
18442 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
18446 case BFD_RELOC_THUMB_PCREL_BLX:
18447 case BFD_RELOC_THUMB_PCREL_BRANCH23:
18448 if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff))
18449 as_bad_where (fixP->fx_file, fixP->fx_line,
18450 _("branch out of range"));
18452 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
18453 /* For a BLX instruction, make sure that the relocation is rounded up
18454 to a word boundary. This follows the semantics of the instruction
18455 which specifies that bit 1 of the target address will come from bit
18456 1 of the base address. */
18457 value = (value + 1) & ~ 1;
18459 if (fixP->fx_done || !seg->use_rela_p)
18463 newval = md_chars_to_number (buf, THUMB_SIZE);
18464 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
18465 newval |= (value & 0x7fffff) >> 12;
18466 newval2 |= (value & 0xfff) >> 1;
18467 md_number_to_chars (buf, newval, THUMB_SIZE);
18468 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
18472 case BFD_RELOC_THUMB_PCREL_BRANCH25:
18473 if ((value & ~0x1ffffff) && ((value & ~0x1ffffff) != ~0x1ffffff))
18474 as_bad_where (fixP->fx_file, fixP->fx_line,
18475 _("branch out of range"));
18477 if (fixP->fx_done || !seg->use_rela_p)
18480 addressT S, I1, I2, lo, hi;
18482 S = (value & 0x01000000) >> 24;
18483 I1 = (value & 0x00800000) >> 23;
18484 I2 = (value & 0x00400000) >> 22;
18485 hi = (value & 0x003ff000) >> 12;
18486 lo = (value & 0x00000ffe) >> 1;
18491 newval = md_chars_to_number (buf, THUMB_SIZE);
18492 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
18493 newval |= (S << 10) | hi;
18494 newval2 |= (I1 << 13) | (I2 << 11) | lo;
18495 md_number_to_chars (buf, newval, THUMB_SIZE);
18496 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
18501 if (fixP->fx_done || !seg->use_rela_p)
18502 md_number_to_chars (buf, value, 1);
18506 if (fixP->fx_done || !seg->use_rela_p)
18507 md_number_to_chars (buf, value, 2);
18511 case BFD_RELOC_ARM_TLS_GD32:
18512 case BFD_RELOC_ARM_TLS_LE32:
18513 case BFD_RELOC_ARM_TLS_IE32:
18514 case BFD_RELOC_ARM_TLS_LDM32:
18515 case BFD_RELOC_ARM_TLS_LDO32:
18516 S_SET_THREAD_LOCAL (fixP->fx_addsy);
18519 case BFD_RELOC_ARM_GOT32:
18520 case BFD_RELOC_ARM_GOTOFF:
18521 case BFD_RELOC_ARM_TARGET2:
18522 if (fixP->fx_done || !seg->use_rela_p)
18523 md_number_to_chars (buf, 0, 4);
18527 case BFD_RELOC_RVA:
18529 case BFD_RELOC_ARM_TARGET1:
18530 case BFD_RELOC_ARM_ROSEGREL32:
18531 case BFD_RELOC_ARM_SBREL32:
18532 case BFD_RELOC_32_PCREL:
18534 case BFD_RELOC_32_SECREL:
18536 if (fixP->fx_done || !seg->use_rela_p)
18538 /* For WinCE we only do this for pcrel fixups. */
18539 if (fixP->fx_done || fixP->fx_pcrel)
18541 md_number_to_chars (buf, value, 4);
18545 case BFD_RELOC_ARM_PREL31:
18546 if (fixP->fx_done || !seg->use_rela_p)
18548 newval = md_chars_to_number (buf, 4) & 0x80000000;
18549 if ((value ^ (value >> 1)) & 0x40000000)
18551 as_bad_where (fixP->fx_file, fixP->fx_line,
18552 _("rel31 relocation overflow"));
18554 newval |= value & 0x7fffffff;
18555 md_number_to_chars (buf, newval, 4);
18560 case BFD_RELOC_ARM_CP_OFF_IMM:
18561 case BFD_RELOC_ARM_T32_CP_OFF_IMM:
18562 if (value < -1023 || value > 1023 || (value & 3))
18563 as_bad_where (fixP->fx_file, fixP->fx_line,
18564 _("co-processor offset out of range"));
18569 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
18570 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
18571 newval = md_chars_to_number (buf, INSN_SIZE);
18573 newval = get_thumb32_insn (buf);
18574 newval &= 0xff7fff00;
18575 newval |= (value >> 2) | (sign ? INDEX_UP : 0);
18576 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
18577 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
18578 md_number_to_chars (buf, newval, INSN_SIZE);
18580 put_thumb32_insn (buf, newval);
18583 case BFD_RELOC_ARM_CP_OFF_IMM_S2:
18584 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2:
18585 if (value < -255 || value > 255)
18586 as_bad_where (fixP->fx_file, fixP->fx_line,
18587 _("co-processor offset out of range"));
18589 goto cp_off_common;
18591 case BFD_RELOC_ARM_THUMB_OFFSET:
18592 newval = md_chars_to_number (buf, THUMB_SIZE);
18593 /* Exactly what ranges, and where the offset is inserted depends
18594 on the type of instruction, we can establish this from the
18596 switch (newval >> 12)
18598 case 4: /* PC load. */
18599 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
18600 forced to zero for these loads; md_pcrel_from has already
18601 compensated for this. */
18603 as_bad_where (fixP->fx_file, fixP->fx_line,
18604 _("invalid offset, target not word aligned (0x%08lX)"),
18605 (((unsigned long) fixP->fx_frag->fr_address
18606 + (unsigned long) fixP->fx_where) & ~3)
18607 + (unsigned long) value);
18609 if (value & ~0x3fc)
18610 as_bad_where (fixP->fx_file, fixP->fx_line,
18611 _("invalid offset, value too big (0x%08lX)"),
18614 newval |= value >> 2;
18617 case 9: /* SP load/store. */
18618 if (value & ~0x3fc)
18619 as_bad_where (fixP->fx_file, fixP->fx_line,
18620 _("invalid offset, value too big (0x%08lX)"),
18622 newval |= value >> 2;
18625 case 6: /* Word load/store. */
18627 as_bad_where (fixP->fx_file, fixP->fx_line,
18628 _("invalid offset, value too big (0x%08lX)"),
18630 newval |= value << 4; /* 6 - 2. */
18633 case 7: /* Byte load/store. */
18635 as_bad_where (fixP->fx_file, fixP->fx_line,
18636 _("invalid offset, value too big (0x%08lX)"),
18638 newval |= value << 6;
18641 case 8: /* Halfword load/store. */
18643 as_bad_where (fixP->fx_file, fixP->fx_line,
18644 _("invalid offset, value too big (0x%08lX)"),
18646 newval |= value << 5; /* 6 - 1. */
18650 as_bad_where (fixP->fx_file, fixP->fx_line,
18651 "Unable to process relocation for thumb opcode: %lx",
18652 (unsigned long) newval);
18655 md_number_to_chars (buf, newval, THUMB_SIZE);
18658 case BFD_RELOC_ARM_THUMB_ADD:
18659 /* This is a complicated relocation, since we use it for all of
18660 the following immediate relocations:
18664 9bit ADD/SUB SP word-aligned
18665 10bit ADD PC/SP word-aligned
18667 The type of instruction being processed is encoded in the
18674 newval = md_chars_to_number (buf, THUMB_SIZE);
18676 int rd = (newval >> 4) & 0xf;
18677 int rs = newval & 0xf;
18678 int subtract = !!(newval & 0x8000);
18680 /* Check for HI regs, only very restricted cases allowed:
18681 Adjusting SP, and using PC or SP to get an address. */
18682 if ((rd > 7 && (rd != REG_SP || rs != REG_SP))
18683 || (rs > 7 && rs != REG_SP && rs != REG_PC))
18684 as_bad_where (fixP->fx_file, fixP->fx_line,
18685 _("invalid Hi register with immediate"));
18687 /* If value is negative, choose the opposite instruction. */
18691 subtract = !subtract;
18693 as_bad_where (fixP->fx_file, fixP->fx_line,
18694 _("immediate value out of range"));
18699 if (value & ~0x1fc)
18700 as_bad_where (fixP->fx_file, fixP->fx_line,
18701 _("invalid immediate for stack address calculation"));
18702 newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST;
18703 newval |= value >> 2;
18705 else if (rs == REG_PC || rs == REG_SP)
18707 if (subtract || value & ~0x3fc)
18708 as_bad_where (fixP->fx_file, fixP->fx_line,
18709 _("invalid immediate for address calculation (value = 0x%08lX)"),
18710 (unsigned long) value);
18711 newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP);
18713 newval |= value >> 2;
18718 as_bad_where (fixP->fx_file, fixP->fx_line,
18719 _("immediate value out of range"));
18720 newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8;
18721 newval |= (rd << 8) | value;
18726 as_bad_where (fixP->fx_file, fixP->fx_line,
18727 _("immediate value out of range"));
18728 newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3;
18729 newval |= rd | (rs << 3) | (value << 6);
18732 md_number_to_chars (buf, newval, THUMB_SIZE);
18735 case BFD_RELOC_ARM_THUMB_IMM:
18736 newval = md_chars_to_number (buf, THUMB_SIZE);
18737 if (value < 0 || value > 255)
18738 as_bad_where (fixP->fx_file, fixP->fx_line,
18739 _("invalid immediate: %ld is too large"),
18742 md_number_to_chars (buf, newval, THUMB_SIZE);
18745 case BFD_RELOC_ARM_THUMB_SHIFT:
18746 /* 5bit shift value (0..32). LSL cannot take 32. */
18747 newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf83f;
18748 temp = newval & 0xf800;
18749 if (value < 0 || value > 32 || (value == 32 && temp == T_OPCODE_LSL_I))
18750 as_bad_where (fixP->fx_file, fixP->fx_line,
18751 _("invalid shift value: %ld"), (long) value);
18752 /* Shifts of zero must be encoded as LSL. */
18754 newval = (newval & 0x003f) | T_OPCODE_LSL_I;
18755 /* Shifts of 32 are encoded as zero. */
18756 else if (value == 32)
18758 newval |= value << 6;
18759 md_number_to_chars (buf, newval, THUMB_SIZE);
18762 case BFD_RELOC_VTABLE_INHERIT:
18763 case BFD_RELOC_VTABLE_ENTRY:
18767 case BFD_RELOC_ARM_MOVW:
18768 case BFD_RELOC_ARM_MOVT:
18769 case BFD_RELOC_ARM_THUMB_MOVW:
18770 case BFD_RELOC_ARM_THUMB_MOVT:
18771 if (fixP->fx_done || !seg->use_rela_p)
18773 /* REL format relocations are limited to a 16-bit addend. */
18774 if (!fixP->fx_done)
18776 if (value < -0x1000 || value > 0xffff)
18777 as_bad_where (fixP->fx_file, fixP->fx_line,
18778 _("offset too big"));
18780 else if (fixP->fx_r_type == BFD_RELOC_ARM_MOVT
18781 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT)
18786 if (fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW
18787 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT)
18789 newval = get_thumb32_insn (buf);
18790 newval &= 0xfbf08f00;
18791 newval |= (value & 0xf000) << 4;
18792 newval |= (value & 0x0800) << 15;
18793 newval |= (value & 0x0700) << 4;
18794 newval |= (value & 0x00ff);
18795 put_thumb32_insn (buf, newval);
18799 newval = md_chars_to_number (buf, 4);
18800 newval &= 0xfff0f000;
18801 newval |= value & 0x0fff;
18802 newval |= (value & 0xf000) << 4;
18803 md_number_to_chars (buf, newval, 4);
18808 case BFD_RELOC_ARM_ALU_PC_G0_NC:
18809 case BFD_RELOC_ARM_ALU_PC_G0:
18810 case BFD_RELOC_ARM_ALU_PC_G1_NC:
18811 case BFD_RELOC_ARM_ALU_PC_G1:
18812 case BFD_RELOC_ARM_ALU_PC_G2:
18813 case BFD_RELOC_ARM_ALU_SB_G0_NC:
18814 case BFD_RELOC_ARM_ALU_SB_G0:
18815 case BFD_RELOC_ARM_ALU_SB_G1_NC:
18816 case BFD_RELOC_ARM_ALU_SB_G1:
18817 case BFD_RELOC_ARM_ALU_SB_G2:
18818 assert (!fixP->fx_done);
18819 if (!seg->use_rela_p)
18822 bfd_vma encoded_addend;
18823 bfd_vma addend_abs = abs (value);
18825 /* Check that the absolute value of the addend can be
18826 expressed as an 8-bit constant plus a rotation. */
18827 encoded_addend = encode_arm_immediate (addend_abs);
18828 if (encoded_addend == (unsigned int) FAIL)
18829 as_bad_where (fixP->fx_file, fixP->fx_line,
18830 _("the offset 0x%08lX is not representable"),
18831 (unsigned long) addend_abs);
18833 /* Extract the instruction. */
18834 insn = md_chars_to_number (buf, INSN_SIZE);
18836 /* If the addend is positive, use an ADD instruction.
18837 Otherwise use a SUB. Take care not to destroy the S bit. */
18838 insn &= 0xff1fffff;
18844 /* Place the encoded addend into the first 12 bits of the
18846 insn &= 0xfffff000;
18847 insn |= encoded_addend;
18849 /* Update the instruction. */
18850 md_number_to_chars (buf, insn, INSN_SIZE);
18854 case BFD_RELOC_ARM_LDR_PC_G0:
18855 case BFD_RELOC_ARM_LDR_PC_G1:
18856 case BFD_RELOC_ARM_LDR_PC_G2:
18857 case BFD_RELOC_ARM_LDR_SB_G0:
18858 case BFD_RELOC_ARM_LDR_SB_G1:
18859 case BFD_RELOC_ARM_LDR_SB_G2:
18860 assert (!fixP->fx_done);
18861 if (!seg->use_rela_p)
18864 bfd_vma addend_abs = abs (value);
18866 /* Check that the absolute value of the addend can be
18867 encoded in 12 bits. */
18868 if (addend_abs >= 0x1000)
18869 as_bad_where (fixP->fx_file, fixP->fx_line,
18870 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
18871 (unsigned long) addend_abs);
18873 /* Extract the instruction. */
18874 insn = md_chars_to_number (buf, INSN_SIZE);
18876 /* If the addend is negative, clear bit 23 of the instruction.
18877 Otherwise set it. */
18879 insn &= ~(1 << 23);
18883 /* Place the absolute value of the addend into the first 12 bits
18884 of the instruction. */
18885 insn &= 0xfffff000;
18886 insn |= addend_abs;
18888 /* Update the instruction. */
18889 md_number_to_chars (buf, insn, INSN_SIZE);
18893 case BFD_RELOC_ARM_LDRS_PC_G0:
18894 case BFD_RELOC_ARM_LDRS_PC_G1:
18895 case BFD_RELOC_ARM_LDRS_PC_G2:
18896 case BFD_RELOC_ARM_LDRS_SB_G0:
18897 case BFD_RELOC_ARM_LDRS_SB_G1:
18898 case BFD_RELOC_ARM_LDRS_SB_G2:
18899 assert (!fixP->fx_done);
18900 if (!seg->use_rela_p)
18903 bfd_vma addend_abs = abs (value);
18905 /* Check that the absolute value of the addend can be
18906 encoded in 8 bits. */
18907 if (addend_abs >= 0x100)
18908 as_bad_where (fixP->fx_file, fixP->fx_line,
18909 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
18910 (unsigned long) addend_abs);
18912 /* Extract the instruction. */
18913 insn = md_chars_to_number (buf, INSN_SIZE);
18915 /* If the addend is negative, clear bit 23 of the instruction.
18916 Otherwise set it. */
18918 insn &= ~(1 << 23);
18922 /* Place the first four bits of the absolute value of the addend
18923 into the first 4 bits of the instruction, and the remaining
18924 four into bits 8 .. 11. */
18925 insn &= 0xfffff0f0;
18926 insn |= (addend_abs & 0xf) | ((addend_abs & 0xf0) << 4);
18928 /* Update the instruction. */
18929 md_number_to_chars (buf, insn, INSN_SIZE);
18933 case BFD_RELOC_ARM_LDC_PC_G0:
18934 case BFD_RELOC_ARM_LDC_PC_G1:
18935 case BFD_RELOC_ARM_LDC_PC_G2:
18936 case BFD_RELOC_ARM_LDC_SB_G0:
18937 case BFD_RELOC_ARM_LDC_SB_G1:
18938 case BFD_RELOC_ARM_LDC_SB_G2:
18939 assert (!fixP->fx_done);
18940 if (!seg->use_rela_p)
18943 bfd_vma addend_abs = abs (value);
18945 /* Check that the absolute value of the addend is a multiple of
18946 four and, when divided by four, fits in 8 bits. */
18947 if (addend_abs & 0x3)
18948 as_bad_where (fixP->fx_file, fixP->fx_line,
18949 _("bad offset 0x%08lX (must be word-aligned)"),
18950 (unsigned long) addend_abs);
18952 if ((addend_abs >> 2) > 0xff)
18953 as_bad_where (fixP->fx_file, fixP->fx_line,
18954 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
18955 (unsigned long) addend_abs);
18957 /* Extract the instruction. */
18958 insn = md_chars_to_number (buf, INSN_SIZE);
18960 /* If the addend is negative, clear bit 23 of the instruction.
18961 Otherwise set it. */
18963 insn &= ~(1 << 23);
18967 /* Place the addend (divided by four) into the first eight
18968 bits of the instruction. */
18969 insn &= 0xfffffff0;
18970 insn |= addend_abs >> 2;
18972 /* Update the instruction. */
18973 md_number_to_chars (buf, insn, INSN_SIZE);
18977 case BFD_RELOC_UNUSED:
18979 as_bad_where (fixP->fx_file, fixP->fx_line,
18980 _("bad relocation fixup type (%d)"), fixP->fx_r_type);
18984 /* Translate internal representation of relocation info to BFD target
18988 tc_gen_reloc (asection *section, fixS *fixp)
18991 bfd_reloc_code_real_type code;
18993 reloc = xmalloc (sizeof (arelent));
18995 reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
18996 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
18997 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
18999 if (fixp->fx_pcrel)
19001 if (section->use_rela_p)
19002 fixp->fx_offset -= md_pcrel_from_section (fixp, section);
19004 fixp->fx_offset = reloc->address;
19006 reloc->addend = fixp->fx_offset;
19008 switch (fixp->fx_r_type)
19011 if (fixp->fx_pcrel)
19013 code = BFD_RELOC_8_PCREL;
19018 if (fixp->fx_pcrel)
19020 code = BFD_RELOC_16_PCREL;
19025 if (fixp->fx_pcrel)
19027 code = BFD_RELOC_32_PCREL;
19031 case BFD_RELOC_ARM_MOVW:
19032 if (fixp->fx_pcrel)
19034 code = BFD_RELOC_ARM_MOVW_PCREL;
19038 case BFD_RELOC_ARM_MOVT:
19039 if (fixp->fx_pcrel)
19041 code = BFD_RELOC_ARM_MOVT_PCREL;
19045 case BFD_RELOC_ARM_THUMB_MOVW:
19046 if (fixp->fx_pcrel)
19048 code = BFD_RELOC_ARM_THUMB_MOVW_PCREL;
19052 case BFD_RELOC_ARM_THUMB_MOVT:
19053 if (fixp->fx_pcrel)
19055 code = BFD_RELOC_ARM_THUMB_MOVT_PCREL;
19059 case BFD_RELOC_NONE:
19060 case BFD_RELOC_ARM_PCREL_BRANCH:
19061 case BFD_RELOC_ARM_PCREL_BLX:
19062 case BFD_RELOC_RVA:
19063 case BFD_RELOC_THUMB_PCREL_BRANCH7:
19064 case BFD_RELOC_THUMB_PCREL_BRANCH9:
19065 case BFD_RELOC_THUMB_PCREL_BRANCH12:
19066 case BFD_RELOC_THUMB_PCREL_BRANCH20:
19067 case BFD_RELOC_THUMB_PCREL_BRANCH23:
19068 case BFD_RELOC_THUMB_PCREL_BRANCH25:
19069 case BFD_RELOC_THUMB_PCREL_BLX:
19070 case BFD_RELOC_VTABLE_ENTRY:
19071 case BFD_RELOC_VTABLE_INHERIT:
19073 case BFD_RELOC_32_SECREL:
19075 code = fixp->fx_r_type;
19078 case BFD_RELOC_ARM_LITERAL:
19079 case BFD_RELOC_ARM_HWLITERAL:
19080 /* If this is called then the a literal has
19081 been referenced across a section boundary. */
19082 as_bad_where (fixp->fx_file, fixp->fx_line,
19083 _("literal referenced across section boundary"));
19087 case BFD_RELOC_ARM_GOT32:
19088 case BFD_RELOC_ARM_GOTOFF:
19089 case BFD_RELOC_ARM_PLT32:
19090 case BFD_RELOC_ARM_TARGET1:
19091 case BFD_RELOC_ARM_ROSEGREL32:
19092 case BFD_RELOC_ARM_SBREL32:
19093 case BFD_RELOC_ARM_PREL31:
19094 case BFD_RELOC_ARM_TARGET2:
19095 case BFD_RELOC_ARM_TLS_LE32:
19096 case BFD_RELOC_ARM_TLS_LDO32:
19097 case BFD_RELOC_ARM_PCREL_CALL:
19098 case BFD_RELOC_ARM_PCREL_JUMP:
19099 case BFD_RELOC_ARM_ALU_PC_G0_NC:
19100 case BFD_RELOC_ARM_ALU_PC_G0:
19101 case BFD_RELOC_ARM_ALU_PC_G1_NC:
19102 case BFD_RELOC_ARM_ALU_PC_G1:
19103 case BFD_RELOC_ARM_ALU_PC_G2:
19104 case BFD_RELOC_ARM_LDR_PC_G0:
19105 case BFD_RELOC_ARM_LDR_PC_G1:
19106 case BFD_RELOC_ARM_LDR_PC_G2:
19107 case BFD_RELOC_ARM_LDRS_PC_G0:
19108 case BFD_RELOC_ARM_LDRS_PC_G1:
19109 case BFD_RELOC_ARM_LDRS_PC_G2:
19110 case BFD_RELOC_ARM_LDC_PC_G0:
19111 case BFD_RELOC_ARM_LDC_PC_G1:
19112 case BFD_RELOC_ARM_LDC_PC_G2:
19113 case BFD_RELOC_ARM_ALU_SB_G0_NC:
19114 case BFD_RELOC_ARM_ALU_SB_G0:
19115 case BFD_RELOC_ARM_ALU_SB_G1_NC:
19116 case BFD_RELOC_ARM_ALU_SB_G1:
19117 case BFD_RELOC_ARM_ALU_SB_G2:
19118 case BFD_RELOC_ARM_LDR_SB_G0:
19119 case BFD_RELOC_ARM_LDR_SB_G1:
19120 case BFD_RELOC_ARM_LDR_SB_G2:
19121 case BFD_RELOC_ARM_LDRS_SB_G0:
19122 case BFD_RELOC_ARM_LDRS_SB_G1:
19123 case BFD_RELOC_ARM_LDRS_SB_G2:
19124 case BFD_RELOC_ARM_LDC_SB_G0:
19125 case BFD_RELOC_ARM_LDC_SB_G1:
19126 case BFD_RELOC_ARM_LDC_SB_G2:
19127 code = fixp->fx_r_type;
19130 case BFD_RELOC_ARM_TLS_GD32:
19131 case BFD_RELOC_ARM_TLS_IE32:
19132 case BFD_RELOC_ARM_TLS_LDM32:
19133 /* BFD will include the symbol's address in the addend.
19134 But we don't want that, so subtract it out again here. */
19135 if (!S_IS_COMMON (fixp->fx_addsy))
19136 reloc->addend -= (*reloc->sym_ptr_ptr)->value;
19137 code = fixp->fx_r_type;
19141 case BFD_RELOC_ARM_IMMEDIATE:
19142 as_bad_where (fixp->fx_file, fixp->fx_line,
19143 _("internal relocation (type: IMMEDIATE) not fixed up"));
19146 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
19147 as_bad_where (fixp->fx_file, fixp->fx_line,
19148 _("ADRL used for a symbol not defined in the same file"));
19151 case BFD_RELOC_ARM_OFFSET_IMM:
19152 if (section->use_rela_p)
19154 code = fixp->fx_r_type;
19158 if (fixp->fx_addsy != NULL
19159 && !S_IS_DEFINED (fixp->fx_addsy)
19160 && S_IS_LOCAL (fixp->fx_addsy))
19162 as_bad_where (fixp->fx_file, fixp->fx_line,
19163 _("undefined local label `%s'"),
19164 S_GET_NAME (fixp->fx_addsy));
19168 as_bad_where (fixp->fx_file, fixp->fx_line,
19169 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
19176 switch (fixp->fx_r_type)
19178 case BFD_RELOC_NONE: type = "NONE"; break;
19179 case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break;
19180 case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break;
19181 case BFD_RELOC_ARM_SMC: type = "SMC"; break;
19182 case BFD_RELOC_ARM_SWI: type = "SWI"; break;
19183 case BFD_RELOC_ARM_MULTI: type = "MULTI"; break;
19184 case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break;
19185 case BFD_RELOC_ARM_T32_CP_OFF_IMM: type = "T32_CP_OFF_IMM"; break;
19186 case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break;
19187 case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break;
19188 case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break;
19189 case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break;
19190 default: type = _("<unknown>"); break;
19192 as_bad_where (fixp->fx_file, fixp->fx_line,
19193 _("cannot represent %s relocation in this object file format"),
19200 if ((code == BFD_RELOC_32_PCREL || code == BFD_RELOC_32)
19202 && fixp->fx_addsy == GOT_symbol)
19204 code = BFD_RELOC_ARM_GOTPC;
19205 reloc->addend = fixp->fx_offset = reloc->address;
19209 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
19211 if (reloc->howto == NULL)
19213 as_bad_where (fixp->fx_file, fixp->fx_line,
19214 _("cannot represent %s relocation in this object file format"),
19215 bfd_get_reloc_code_name (code));
19219 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
19220 vtable entry to be used in the relocation's section offset. */
19221 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
19222 reloc->address = fixp->fx_offset;
19227 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
19230 cons_fix_new_arm (fragS * frag,
19235 bfd_reloc_code_real_type type;
19239 FIXME: @@ Should look at CPU word size. */
19243 type = BFD_RELOC_8;
19246 type = BFD_RELOC_16;
19250 type = BFD_RELOC_32;
19253 type = BFD_RELOC_64;
19258 if (exp->X_op == O_secrel)
19260 exp->X_op = O_symbol;
19261 type = BFD_RELOC_32_SECREL;
19265 fix_new_exp (frag, where, (int) size, exp, pcrel, type);
19268 #if defined OBJ_COFF || defined OBJ_ELF
19270 arm_validate_fix (fixS * fixP)
19272 /* If the destination of the branch is a defined symbol which does not have
19273 the THUMB_FUNC attribute, then we must be calling a function which has
19274 the (interfacearm) attribute. We look for the Thumb entry point to that
19275 function and change the branch to refer to that function instead. */
19276 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23
19277 && fixP->fx_addsy != NULL
19278 && S_IS_DEFINED (fixP->fx_addsy)
19279 && ! THUMB_IS_FUNC (fixP->fx_addsy))
19281 fixP->fx_addsy = find_real_start (fixP->fx_addsy);
19287 arm_force_relocation (struct fix * fixp)
19289 #if defined (OBJ_COFF) && defined (TE_PE)
19290 if (fixp->fx_r_type == BFD_RELOC_RVA)
19294 /* Resolve these relocations even if the symbol is extern or weak. */
19295 if (fixp->fx_r_type == BFD_RELOC_ARM_IMMEDIATE
19296 || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM
19297 || fixp->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE
19298 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM
19299 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
19300 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMM12
19301 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_PC12)
19304 /* Always leave these relocations for the linker. */
19305 if ((fixp->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC
19306 && fixp->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2)
19307 || fixp->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0)
19310 /* Always generate relocations against function symbols. */
19311 if (fixp->fx_r_type == BFD_RELOC_32
19313 && (symbol_get_bfdsym (fixp->fx_addsy)->flags & BSF_FUNCTION))
19316 return generic_force_reloc (fixp);
19319 #if defined (OBJ_ELF) || defined (OBJ_COFF)
19320 /* Relocations against function names must be left unadjusted,
19321 so that the linker can use this information to generate interworking
19322 stubs. The MIPS version of this function
19323 also prevents relocations that are mips-16 specific, but I do not
19324 know why it does this.
19327 There is one other problem that ought to be addressed here, but
19328 which currently is not: Taking the address of a label (rather
19329 than a function) and then later jumping to that address. Such
19330 addresses also ought to have their bottom bit set (assuming that
19331 they reside in Thumb code), but at the moment they will not. */
19334 arm_fix_adjustable (fixS * fixP)
19336 if (fixP->fx_addsy == NULL)
19339 /* Preserve relocations against symbols with function type. */
19340 if (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_FUNCTION)
19343 if (THUMB_IS_FUNC (fixP->fx_addsy)
19344 && fixP->fx_subsy == NULL)
19347 /* We need the symbol name for the VTABLE entries. */
19348 if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
19349 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
19352 /* Don't allow symbols to be discarded on GOT related relocs. */
19353 if (fixP->fx_r_type == BFD_RELOC_ARM_PLT32
19354 || fixP->fx_r_type == BFD_RELOC_ARM_GOT32
19355 || fixP->fx_r_type == BFD_RELOC_ARM_GOTOFF
19356 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32
19357 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LE32
19358 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32
19359 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32
19360 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDO32
19361 || fixP->fx_r_type == BFD_RELOC_ARM_TARGET2)
19364 /* Similarly for group relocations. */
19365 if ((fixP->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC
19366 && fixP->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2)
19367 || fixP->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0)
19372 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
19377 elf32_arm_target_format (void)
19380 return (target_big_endian
19381 ? "elf32-bigarm-symbian"
19382 : "elf32-littlearm-symbian");
19383 #elif defined (TE_VXWORKS)
19384 return (target_big_endian
19385 ? "elf32-bigarm-vxworks"
19386 : "elf32-littlearm-vxworks");
19388 if (target_big_endian)
19389 return "elf32-bigarm";
19391 return "elf32-littlearm";
19396 armelf_frob_symbol (symbolS * symp,
19399 elf_frob_symbol (symp, puntp);
19403 /* MD interface: Finalization. */
19405 /* A good place to do this, although this was probably not intended
19406 for this kind of use. We need to dump the literal pool before
19407 references are made to a null symbol pointer. */
19412 literal_pool * pool;
19414 for (pool = list_of_pools; pool; pool = pool->next)
19416 /* Put it at the end of the relevent section. */
19417 subseg_set (pool->section, pool->sub_section);
19419 arm_elf_change_section ();
19425 /* Adjust the symbol table. This marks Thumb symbols as distinct from
19429 arm_adjust_symtab (void)
19434 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
19436 if (ARM_IS_THUMB (sym))
19438 if (THUMB_IS_FUNC (sym))
19440 /* Mark the symbol as a Thumb function. */
19441 if ( S_GET_STORAGE_CLASS (sym) == C_STAT
19442 || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */
19443 S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC);
19445 else if (S_GET_STORAGE_CLASS (sym) == C_EXT)
19446 S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC);
19448 as_bad (_("%s: unexpected function type: %d"),
19449 S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym));
19451 else switch (S_GET_STORAGE_CLASS (sym))
19454 S_SET_STORAGE_CLASS (sym, C_THUMBEXT);
19457 S_SET_STORAGE_CLASS (sym, C_THUMBSTAT);
19460 S_SET_STORAGE_CLASS (sym, C_THUMBLABEL);
19468 if (ARM_IS_INTERWORK (sym))
19469 coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF;
19476 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
19478 if (ARM_IS_THUMB (sym))
19480 elf_symbol_type * elf_sym;
19482 elf_sym = elf_symbol (symbol_get_bfdsym (sym));
19483 bind = ELF_ST_BIND (elf_sym->internal_elf_sym.st_info);
19485 if (! bfd_is_arm_special_symbol_name (elf_sym->symbol.name,
19486 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
19488 /* If it's a .thumb_func, declare it as so,
19489 otherwise tag label as .code 16. */
19490 if (THUMB_IS_FUNC (sym))
19491 elf_sym->internal_elf_sym.st_info =
19492 ELF_ST_INFO (bind, STT_ARM_TFUNC);
19493 else if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
19494 elf_sym->internal_elf_sym.st_info =
19495 ELF_ST_INFO (bind, STT_ARM_16BIT);
19502 /* MD interface: Initialization. */
19505 set_constant_flonums (void)
19509 for (i = 0; i < NUM_FLOAT_VALS; i++)
19510 if (atof_ieee ((char *) fp_const[i], 'x', fp_values[i]) == NULL)
19514 /* Auto-select Thumb mode if it's the only available instruction set for the
19515 given architecture. */
19518 autoselect_thumb_from_cpu_variant (void)
19520 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
19521 opcode_select (16);
19530 if ( (arm_ops_hsh = hash_new ()) == NULL
19531 || (arm_cond_hsh = hash_new ()) == NULL
19532 || (arm_shift_hsh = hash_new ()) == NULL
19533 || (arm_psr_hsh = hash_new ()) == NULL
19534 || (arm_v7m_psr_hsh = hash_new ()) == NULL
19535 || (arm_reg_hsh = hash_new ()) == NULL
19536 || (arm_reloc_hsh = hash_new ()) == NULL
19537 || (arm_barrier_opt_hsh = hash_new ()) == NULL)
19538 as_fatal (_("virtual memory exhausted"));
19540 for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++)
19541 hash_insert (arm_ops_hsh, insns[i].template, (PTR) (insns + i));
19542 for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++)
19543 hash_insert (arm_cond_hsh, conds[i].template, (PTR) (conds + i));
19544 for (i = 0; i < sizeof (shift_names) / sizeof (struct asm_shift_name); i++)
19545 hash_insert (arm_shift_hsh, shift_names[i].name, (PTR) (shift_names + i));
19546 for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++)
19547 hash_insert (arm_psr_hsh, psrs[i].template, (PTR) (psrs + i));
19548 for (i = 0; i < sizeof (v7m_psrs) / sizeof (struct asm_psr); i++)
19549 hash_insert (arm_v7m_psr_hsh, v7m_psrs[i].template, (PTR) (v7m_psrs + i));
19550 for (i = 0; i < sizeof (reg_names) / sizeof (struct reg_entry); i++)
19551 hash_insert (arm_reg_hsh, reg_names[i].name, (PTR) (reg_names + i));
19553 i < sizeof (barrier_opt_names) / sizeof (struct asm_barrier_opt);
19555 hash_insert (arm_barrier_opt_hsh, barrier_opt_names[i].template,
19556 (PTR) (barrier_opt_names + i));
19558 for (i = 0; i < sizeof (reloc_names) / sizeof (struct reloc_entry); i++)
19559 hash_insert (arm_reloc_hsh, reloc_names[i].name, (PTR) (reloc_names + i));
19562 set_constant_flonums ();
19564 /* Set the cpu variant based on the command-line options. We prefer
19565 -mcpu= over -march= if both are set (as for GCC); and we prefer
19566 -mfpu= over any other way of setting the floating point unit.
19567 Use of legacy options with new options are faulted. */
19570 if (mcpu_cpu_opt || march_cpu_opt)
19571 as_bad (_("use of old and new-style options to set CPU type"));
19573 mcpu_cpu_opt = legacy_cpu;
19575 else if (!mcpu_cpu_opt)
19576 mcpu_cpu_opt = march_cpu_opt;
19581 as_bad (_("use of old and new-style options to set FPU type"));
19583 mfpu_opt = legacy_fpu;
19585 else if (!mfpu_opt)
19587 #if !(defined (TE_LINUX) || defined (TE_NetBSD) || defined (TE_VXWORKS))
19588 /* Some environments specify a default FPU. If they don't, infer it
19589 from the processor. */
19591 mfpu_opt = mcpu_fpu_opt;
19593 mfpu_opt = march_fpu_opt;
19595 mfpu_opt = &fpu_default;
19601 if (mcpu_cpu_opt != NULL)
19602 mfpu_opt = &fpu_default;
19603 else if (mcpu_fpu_opt != NULL && ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt, arm_ext_v5))
19604 mfpu_opt = &fpu_arch_vfp_v2;
19606 mfpu_opt = &fpu_arch_fpa;
19612 mcpu_cpu_opt = &cpu_default;
19613 selected_cpu = cpu_default;
19617 selected_cpu = *mcpu_cpu_opt;
19619 mcpu_cpu_opt = &arm_arch_any;
19622 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
19624 autoselect_thumb_from_cpu_variant ();
19626 arm_arch_used = thumb_arch_used = arm_arch_none;
19628 #if defined OBJ_COFF || defined OBJ_ELF
19630 unsigned int flags = 0;
19632 #if defined OBJ_ELF
19633 flags = meabi_flags;
19635 switch (meabi_flags)
19637 case EF_ARM_EABI_UNKNOWN:
19639 /* Set the flags in the private structure. */
19640 if (uses_apcs_26) flags |= F_APCS26;
19641 if (support_interwork) flags |= F_INTERWORK;
19642 if (uses_apcs_float) flags |= F_APCS_FLOAT;
19643 if (pic_code) flags |= F_PIC;
19644 if (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_any_hard))
19645 flags |= F_SOFT_FLOAT;
19647 switch (mfloat_abi_opt)
19649 case ARM_FLOAT_ABI_SOFT:
19650 case ARM_FLOAT_ABI_SOFTFP:
19651 flags |= F_SOFT_FLOAT;
19654 case ARM_FLOAT_ABI_HARD:
19655 if (flags & F_SOFT_FLOAT)
19656 as_bad (_("hard-float conflicts with specified fpu"));
19660 /* Using pure-endian doubles (even if soft-float). */
19661 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
19662 flags |= F_VFP_FLOAT;
19664 #if defined OBJ_ELF
19665 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_maverick))
19666 flags |= EF_ARM_MAVERICK_FLOAT;
19669 case EF_ARM_EABI_VER4:
19670 case EF_ARM_EABI_VER5:
19671 /* No additional flags to set. */
19678 bfd_set_private_flags (stdoutput, flags);
19680 /* We have run out flags in the COFF header to encode the
19681 status of ATPCS support, so instead we create a dummy,
19682 empty, debug section called .arm.atpcs. */
19687 sec = bfd_make_section (stdoutput, ".arm.atpcs");
19691 bfd_set_section_flags
19692 (stdoutput, sec, SEC_READONLY | SEC_DEBUGGING /* | SEC_HAS_CONTENTS */);
19693 bfd_set_section_size (stdoutput, sec, 0);
19694 bfd_set_section_contents (stdoutput, sec, NULL, 0, 0);
19700 /* Record the CPU type as well. */
19701 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2))
19702 mach = bfd_mach_arm_iWMMXt2;
19703 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt))
19704 mach = bfd_mach_arm_iWMMXt;
19705 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_xscale))
19706 mach = bfd_mach_arm_XScale;
19707 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_maverick))
19708 mach = bfd_mach_arm_ep9312;
19709 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5e))
19710 mach = bfd_mach_arm_5TE;
19711 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5))
19713 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
19714 mach = bfd_mach_arm_5T;
19716 mach = bfd_mach_arm_5;
19718 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4))
19720 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
19721 mach = bfd_mach_arm_4T;
19723 mach = bfd_mach_arm_4;
19725 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3m))
19726 mach = bfd_mach_arm_3M;
19727 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3))
19728 mach = bfd_mach_arm_3;
19729 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2s))
19730 mach = bfd_mach_arm_2a;
19731 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2))
19732 mach = bfd_mach_arm_2;
19734 mach = bfd_mach_arm_unknown;
19736 bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach);
19739 /* Command line processing. */
19742 Invocation line includes a switch not recognized by the base assembler.
19743 See if it's a processor-specific option.
19745 This routine is somewhat complicated by the need for backwards
19746 compatibility (since older releases of gcc can't be changed).
19747 The new options try to make the interface as compatible as
19750 New options (supported) are:
19752 -mcpu=<cpu name> Assemble for selected processor
19753 -march=<architecture name> Assemble for selected architecture
19754 -mfpu=<fpu architecture> Assemble for selected FPU.
19755 -EB/-mbig-endian Big-endian
19756 -EL/-mlittle-endian Little-endian
19757 -k Generate PIC code
19758 -mthumb Start in Thumb mode
19759 -mthumb-interwork Code supports ARM/Thumb interworking
19761 For now we will also provide support for:
19763 -mapcs-32 32-bit Program counter
19764 -mapcs-26 26-bit Program counter
19765 -macps-float Floats passed in FP registers
19766 -mapcs-reentrant Reentrant code
19768 (sometime these will probably be replaced with -mapcs=<list of options>
19769 and -matpcs=<list of options>)
19771 The remaining options are only supported for back-wards compatibility.
19772 Cpu variants, the arm part is optional:
19773 -m[arm]1 Currently not supported.
19774 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
19775 -m[arm]3 Arm 3 processor
19776 -m[arm]6[xx], Arm 6 processors
19777 -m[arm]7[xx][t][[d]m] Arm 7 processors
19778 -m[arm]8[10] Arm 8 processors
19779 -m[arm]9[20][tdmi] Arm 9 processors
19780 -mstrongarm[110[0]] StrongARM processors
19781 -mxscale XScale processors
19782 -m[arm]v[2345[t[e]]] Arm architectures
19783 -mall All (except the ARM1)
19785 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
19786 -mfpe-old (No float load/store multiples)
19787 -mvfpxd VFP Single precision
19789 -mno-fpu Disable all floating point instructions
19791 The following CPU names are recognized:
19792 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
19793 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
19794 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
19795 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
19796 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
19797 arm10t arm10e, arm1020t, arm1020e, arm10200e,
19798 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
19802 const char * md_shortopts = "m:k";
19804 #ifdef ARM_BI_ENDIAN
19805 #define OPTION_EB (OPTION_MD_BASE + 0)
19806 #define OPTION_EL (OPTION_MD_BASE + 1)
19808 #if TARGET_BYTES_BIG_ENDIAN
19809 #define OPTION_EB (OPTION_MD_BASE + 0)
19811 #define OPTION_EL (OPTION_MD_BASE + 1)
19815 struct option md_longopts[] =
19818 {"EB", no_argument, NULL, OPTION_EB},
19821 {"EL", no_argument, NULL, OPTION_EL},
19823 {NULL, no_argument, NULL, 0}
19826 size_t md_longopts_size = sizeof (md_longopts);
19828 struct arm_option_table
19830 char *option; /* Option name to match. */
19831 char *help; /* Help information. */
19832 int *var; /* Variable to change. */
19833 int value; /* What to change it to. */
19834 char *deprecated; /* If non-null, print this message. */
19837 struct arm_option_table arm_opts[] =
19839 {"k", N_("generate PIC code"), &pic_code, 1, NULL},
19840 {"mthumb", N_("assemble Thumb code"), &thumb_mode, 1, NULL},
19841 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
19842 &support_interwork, 1, NULL},
19843 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26, 0, NULL},
19844 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26, 1, NULL},
19845 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float,
19847 {"mapcs-reentrant", N_("re-entrant code"), &pic_code, 1, NULL},
19848 {"matpcs", N_("code is ATPCS conformant"), &atpcs, 1, NULL},
19849 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL},
19850 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 0,
19853 /* These are recognized by the assembler, but have no affect on code. */
19854 {"mapcs-frame", N_("use frame pointer"), NULL, 0, NULL},
19855 {"mapcs-stack-check", N_("use stack size checking"), NULL, 0, NULL},
19856 {NULL, NULL, NULL, 0, NULL}
19859 struct arm_legacy_option_table
19861 char *option; /* Option name to match. */
19862 const arm_feature_set **var; /* Variable to change. */
19863 const arm_feature_set value; /* What to change it to. */
19864 char *deprecated; /* If non-null, print this message. */
19867 const struct arm_legacy_option_table arm_legacy_opts[] =
19869 /* DON'T add any new processors to this list -- we want the whole list
19870 to go away... Add them to the processors table instead. */
19871 {"marm1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
19872 {"m1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
19873 {"marm2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
19874 {"m2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
19875 {"marm250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
19876 {"m250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
19877 {"marm3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
19878 {"m3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
19879 {"marm6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
19880 {"m6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
19881 {"marm600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
19882 {"m600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
19883 {"marm610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
19884 {"m610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
19885 {"marm620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
19886 {"m620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
19887 {"marm7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
19888 {"m7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
19889 {"marm70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
19890 {"m70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
19891 {"marm700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
19892 {"m700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
19893 {"marm700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
19894 {"m700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
19895 {"marm710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
19896 {"m710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
19897 {"marm710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
19898 {"m710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
19899 {"marm720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
19900 {"m720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
19901 {"marm7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
19902 {"m7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
19903 {"marm7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
19904 {"m7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
19905 {"marm7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
19906 {"m7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
19907 {"marm7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
19908 {"m7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
19909 {"marm7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
19910 {"m7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
19911 {"marm7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
19912 {"m7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
19913 {"marm7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
19914 {"m7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
19915 {"marm7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
19916 {"m7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
19917 {"marm7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
19918 {"m7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
19919 {"marm7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
19920 {"m7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
19921 {"marm710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
19922 {"m710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
19923 {"marm720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
19924 {"m720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
19925 {"marm740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
19926 {"m740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
19927 {"marm8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
19928 {"m8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
19929 {"marm810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
19930 {"m810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
19931 {"marm9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
19932 {"m9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
19933 {"marm9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
19934 {"m9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
19935 {"marm920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
19936 {"m920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
19937 {"marm940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
19938 {"m940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
19939 {"mstrongarm", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=strongarm")},
19940 {"mstrongarm110", &legacy_cpu, ARM_ARCH_V4,
19941 N_("use -mcpu=strongarm110")},
19942 {"mstrongarm1100", &legacy_cpu, ARM_ARCH_V4,
19943 N_("use -mcpu=strongarm1100")},
19944 {"mstrongarm1110", &legacy_cpu, ARM_ARCH_V4,
19945 N_("use -mcpu=strongarm1110")},
19946 {"mxscale", &legacy_cpu, ARM_ARCH_XSCALE, N_("use -mcpu=xscale")},
19947 {"miwmmxt", &legacy_cpu, ARM_ARCH_IWMMXT, N_("use -mcpu=iwmmxt")},
19948 {"mall", &legacy_cpu, ARM_ANY, N_("use -mcpu=all")},
19950 /* Architecture variants -- don't add any more to this list either. */
19951 {"mv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
19952 {"marmv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
19953 {"mv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
19954 {"marmv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
19955 {"mv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
19956 {"marmv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
19957 {"mv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
19958 {"marmv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
19959 {"mv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
19960 {"marmv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
19961 {"mv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
19962 {"marmv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
19963 {"mv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
19964 {"marmv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
19965 {"mv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
19966 {"marmv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
19967 {"mv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
19968 {"marmv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
19970 /* Floating point variants -- don't add any more to this list either. */
19971 {"mfpe-old", &legacy_fpu, FPU_ARCH_FPE, N_("use -mfpu=fpe")},
19972 {"mfpa10", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa10")},
19973 {"mfpa11", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa11")},
19974 {"mno-fpu", &legacy_fpu, ARM_ARCH_NONE,
19975 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
19977 {NULL, NULL, ARM_ARCH_NONE, NULL}
19980 struct arm_cpu_option_table
19983 const arm_feature_set value;
19984 /* For some CPUs we assume an FPU unless the user explicitly sets
19986 const arm_feature_set default_fpu;
19987 /* The canonical name of the CPU, or NULL to use NAME converted to upper
19989 const char *canonical_name;
19992 /* This list should, at a minimum, contain all the cpu names
19993 recognized by GCC. */
19994 static const struct arm_cpu_option_table arm_cpus[] =
19996 {"all", ARM_ANY, FPU_ARCH_FPA, NULL},
19997 {"arm1", ARM_ARCH_V1, FPU_ARCH_FPA, NULL},
19998 {"arm2", ARM_ARCH_V2, FPU_ARCH_FPA, NULL},
19999 {"arm250", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL},
20000 {"arm3", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL},
20001 {"arm6", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
20002 {"arm60", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
20003 {"arm600", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
20004 {"arm610", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
20005 {"arm620", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
20006 {"arm7", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
20007 {"arm7m", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL},
20008 {"arm7d", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
20009 {"arm7dm", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL},
20010 {"arm7di", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
20011 {"arm7dmi", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL},
20012 {"arm70", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
20013 {"arm700", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
20014 {"arm700i", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
20015 {"arm710", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
20016 {"arm710t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
20017 {"arm720", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
20018 {"arm720t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
20019 {"arm740t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
20020 {"arm710c", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
20021 {"arm7100", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
20022 {"arm7500", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
20023 {"arm7500fe", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
20024 {"arm7t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
20025 {"arm7tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
20026 {"arm7tdmi-s", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
20027 {"arm8", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
20028 {"arm810", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
20029 {"strongarm", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
20030 {"strongarm1", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
20031 {"strongarm110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
20032 {"strongarm1100", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
20033 {"strongarm1110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
20034 {"arm9", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
20035 {"arm920", ARM_ARCH_V4T, FPU_ARCH_FPA, "ARM920T"},
20036 {"arm920t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
20037 {"arm922t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
20038 {"arm940t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
20039 {"arm9tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
20040 /* For V5 or later processors we default to using VFP; but the user
20041 should really set the FPU type explicitly. */
20042 {"arm9e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL},
20043 {"arm9e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
20044 {"arm926ej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"},
20045 {"arm926ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"},
20046 {"arm926ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL},
20047 {"arm946e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL},
20048 {"arm946e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM946E-S"},
20049 {"arm946e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
20050 {"arm966e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL},
20051 {"arm966e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM966E-S"},
20052 {"arm966e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
20053 {"arm968e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
20054 {"arm10t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL},
20055 {"arm10tdmi", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL},
20056 {"arm10e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
20057 {"arm1020", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM1020E"},
20058 {"arm1020t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL},
20059 {"arm1020e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
20060 {"arm1022e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
20061 {"arm1026ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM1026EJ-S"},
20062 {"arm1026ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL},
20063 {"arm1136js", ARM_ARCH_V6, FPU_NONE, "ARM1136J-S"},
20064 {"arm1136j-s", ARM_ARCH_V6, FPU_NONE, NULL},
20065 {"arm1136jfs", ARM_ARCH_V6, FPU_ARCH_VFP_V2, "ARM1136JF-S"},
20066 {"arm1136jf-s", ARM_ARCH_V6, FPU_ARCH_VFP_V2, NULL},
20067 {"mpcore", ARM_ARCH_V6K, FPU_ARCH_VFP_V2, NULL},
20068 {"mpcorenovfp", ARM_ARCH_V6K, FPU_NONE, NULL},
20069 {"arm1156t2-s", ARM_ARCH_V6T2, FPU_NONE, NULL},
20070 {"arm1156t2f-s", ARM_ARCH_V6T2, FPU_ARCH_VFP_V2, NULL},
20071 {"arm1176jz-s", ARM_ARCH_V6ZK, FPU_NONE, NULL},
20072 {"arm1176jzf-s", ARM_ARCH_V6ZK, FPU_ARCH_VFP_V2, NULL},
20073 {"cortex-a8", ARM_ARCH_V7A, ARM_FEATURE(0, FPU_VFP_V3
20074 | FPU_NEON_EXT_V1),
20076 {"cortex-a9", ARM_ARCH_V7A, ARM_FEATURE(0, FPU_VFP_V3
20077 | FPU_NEON_EXT_V1),
20079 {"cortex-r4", ARM_ARCH_V7R, FPU_NONE, NULL},
20080 {"cortex-m3", ARM_ARCH_V7M, FPU_NONE, NULL},
20081 /* ??? XSCALE is really an architecture. */
20082 {"xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL},
20083 /* ??? iwmmxt is not a processor. */
20084 {"iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP_V2, NULL},
20085 {"iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP_V2, NULL},
20086 {"i80200", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL},
20088 {"ep9312", ARM_FEATURE(ARM_AEXT_V4T, ARM_CEXT_MAVERICK), FPU_ARCH_MAVERICK, "ARM920T"},
20089 {NULL, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL}
20092 struct arm_arch_option_table
20095 const arm_feature_set value;
20096 const arm_feature_set default_fpu;
20099 /* This list should, at a minimum, contain all the architecture names
20100 recognized by GCC. */
20101 static const struct arm_arch_option_table arm_archs[] =
20103 {"all", ARM_ANY, FPU_ARCH_FPA},
20104 {"armv1", ARM_ARCH_V1, FPU_ARCH_FPA},
20105 {"armv2", ARM_ARCH_V2, FPU_ARCH_FPA},
20106 {"armv2a", ARM_ARCH_V2S, FPU_ARCH_FPA},
20107 {"armv2s", ARM_ARCH_V2S, FPU_ARCH_FPA},
20108 {"armv3", ARM_ARCH_V3, FPU_ARCH_FPA},
20109 {"armv3m", ARM_ARCH_V3M, FPU_ARCH_FPA},
20110 {"armv4", ARM_ARCH_V4, FPU_ARCH_FPA},
20111 {"armv4xm", ARM_ARCH_V4xM, FPU_ARCH_FPA},
20112 {"armv4t", ARM_ARCH_V4T, FPU_ARCH_FPA},
20113 {"armv4txm", ARM_ARCH_V4TxM, FPU_ARCH_FPA},
20114 {"armv5", ARM_ARCH_V5, FPU_ARCH_VFP},
20115 {"armv5t", ARM_ARCH_V5T, FPU_ARCH_VFP},
20116 {"armv5txm", ARM_ARCH_V5TxM, FPU_ARCH_VFP},
20117 {"armv5te", ARM_ARCH_V5TE, FPU_ARCH_VFP},
20118 {"armv5texp", ARM_ARCH_V5TExP, FPU_ARCH_VFP},
20119 {"armv5tej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP},
20120 {"armv6", ARM_ARCH_V6, FPU_ARCH_VFP},
20121 {"armv6j", ARM_ARCH_V6, FPU_ARCH_VFP},
20122 {"armv6k", ARM_ARCH_V6K, FPU_ARCH_VFP},
20123 {"armv6z", ARM_ARCH_V6Z, FPU_ARCH_VFP},
20124 {"armv6zk", ARM_ARCH_V6ZK, FPU_ARCH_VFP},
20125 {"armv6t2", ARM_ARCH_V6T2, FPU_ARCH_VFP},
20126 {"armv6kt2", ARM_ARCH_V6KT2, FPU_ARCH_VFP},
20127 {"armv6zt2", ARM_ARCH_V6ZT2, FPU_ARCH_VFP},
20128 {"armv6zkt2", ARM_ARCH_V6ZKT2, FPU_ARCH_VFP},
20129 {"armv7", ARM_ARCH_V7, FPU_ARCH_VFP},
20130 /* The official spelling of the ARMv7 profile variants is the dashed form.
20131 Accept the non-dashed form for compatibility with old toolchains. */
20132 {"armv7a", ARM_ARCH_V7A, FPU_ARCH_VFP},
20133 {"armv7r", ARM_ARCH_V7R, FPU_ARCH_VFP},
20134 {"armv7m", ARM_ARCH_V7M, FPU_ARCH_VFP},
20135 {"armv7-a", ARM_ARCH_V7A, FPU_ARCH_VFP},
20136 {"armv7-r", ARM_ARCH_V7R, FPU_ARCH_VFP},
20137 {"armv7-m", ARM_ARCH_V7M, FPU_ARCH_VFP},
20138 {"xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP},
20139 {"iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP},
20140 {"iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP},
20141 {NULL, ARM_ARCH_NONE, ARM_ARCH_NONE}
20144 /* ISA extensions in the co-processor space. */
20145 struct arm_option_cpu_value_table
20148 const arm_feature_set value;
20151 static const struct arm_option_cpu_value_table arm_extensions[] =
20153 {"maverick", ARM_FEATURE (0, ARM_CEXT_MAVERICK)},
20154 {"xscale", ARM_FEATURE (0, ARM_CEXT_XSCALE)},
20155 {"iwmmxt", ARM_FEATURE (0, ARM_CEXT_IWMMXT)},
20156 {"iwmmxt2", ARM_FEATURE (0, ARM_CEXT_IWMMXT2)},
20157 {NULL, ARM_ARCH_NONE}
20160 /* This list should, at a minimum, contain all the fpu names
20161 recognized by GCC. */
20162 static const struct arm_option_cpu_value_table arm_fpus[] =
20164 {"softfpa", FPU_NONE},
20165 {"fpe", FPU_ARCH_FPE},
20166 {"fpe2", FPU_ARCH_FPE},
20167 {"fpe3", FPU_ARCH_FPA}, /* Third release supports LFM/SFM. */
20168 {"fpa", FPU_ARCH_FPA},
20169 {"fpa10", FPU_ARCH_FPA},
20170 {"fpa11", FPU_ARCH_FPA},
20171 {"arm7500fe", FPU_ARCH_FPA},
20172 {"softvfp", FPU_ARCH_VFP},
20173 {"softvfp+vfp", FPU_ARCH_VFP_V2},
20174 {"vfp", FPU_ARCH_VFP_V2},
20175 {"vfpv2", FPU_ARCH_VFP_V2},
20176 {"vfp9", FPU_ARCH_VFP_V2},
20177 {"vfp3", FPU_ARCH_VFP_V3},
20178 {"vfpv3", FPU_ARCH_VFP_V3},
20179 {"vfp10", FPU_ARCH_VFP_V2},
20180 {"vfp10-r0", FPU_ARCH_VFP_V1},
20181 {"vfpxd", FPU_ARCH_VFP_V1xD},
20182 {"arm1020t", FPU_ARCH_VFP_V1},
20183 {"arm1020e", FPU_ARCH_VFP_V2},
20184 {"arm1136jfs", FPU_ARCH_VFP_V2},
20185 {"arm1136jf-s", FPU_ARCH_VFP_V2},
20186 {"maverick", FPU_ARCH_MAVERICK},
20187 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1},
20188 {NULL, ARM_ARCH_NONE}
20191 struct arm_option_value_table
20197 static const struct arm_option_value_table arm_float_abis[] =
20199 {"hard", ARM_FLOAT_ABI_HARD},
20200 {"softfp", ARM_FLOAT_ABI_SOFTFP},
20201 {"soft", ARM_FLOAT_ABI_SOFT},
20206 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
20207 static const struct arm_option_value_table arm_eabis[] =
20209 {"gnu", EF_ARM_EABI_UNKNOWN},
20210 {"4", EF_ARM_EABI_VER4},
20211 {"5", EF_ARM_EABI_VER5},
20216 struct arm_long_option_table
20218 char * option; /* Substring to match. */
20219 char * help; /* Help information. */
20220 int (* func) (char * subopt); /* Function to decode sub-option. */
20221 char * deprecated; /* If non-null, print this message. */
20225 arm_parse_extension (char * str, const arm_feature_set **opt_p)
20227 arm_feature_set *ext_set = xmalloc (sizeof (arm_feature_set));
20229 /* Copy the feature set, so that we can modify it. */
20230 *ext_set = **opt_p;
20233 while (str != NULL && *str != 0)
20235 const struct arm_option_cpu_value_table * opt;
20241 as_bad (_("invalid architectural extension"));
20246 ext = strchr (str, '+');
20249 optlen = ext - str;
20251 optlen = strlen (str);
20255 as_bad (_("missing architectural extension"));
20259 for (opt = arm_extensions; opt->name != NULL; opt++)
20260 if (strncmp (opt->name, str, optlen) == 0)
20262 ARM_MERGE_FEATURE_SETS (*ext_set, *ext_set, opt->value);
20266 if (opt->name == NULL)
20268 as_bad (_("unknown architectural extnsion `%s'"), str);
20279 arm_parse_cpu (char * str)
20281 const struct arm_cpu_option_table * opt;
20282 char * ext = strchr (str, '+');
20286 optlen = ext - str;
20288 optlen = strlen (str);
20292 as_bad (_("missing cpu name `%s'"), str);
20296 for (opt = arm_cpus; opt->name != NULL; opt++)
20297 if (strncmp (opt->name, str, optlen) == 0)
20299 mcpu_cpu_opt = &opt->value;
20300 mcpu_fpu_opt = &opt->default_fpu;
20301 if (opt->canonical_name)
20302 strcpy(selected_cpu_name, opt->canonical_name);
20306 for (i = 0; i < optlen; i++)
20307 selected_cpu_name[i] = TOUPPER (opt->name[i]);
20308 selected_cpu_name[i] = 0;
20312 return arm_parse_extension (ext, &mcpu_cpu_opt);
20317 as_bad (_("unknown cpu `%s'"), str);
20322 arm_parse_arch (char * str)
20324 const struct arm_arch_option_table *opt;
20325 char *ext = strchr (str, '+');
20329 optlen = ext - str;
20331 optlen = strlen (str);
20335 as_bad (_("missing architecture name `%s'"), str);
20339 for (opt = arm_archs; opt->name != NULL; opt++)
20340 if (streq (opt->name, str))
20342 march_cpu_opt = &opt->value;
20343 march_fpu_opt = &opt->default_fpu;
20344 strcpy(selected_cpu_name, opt->name);
20347 return arm_parse_extension (ext, &march_cpu_opt);
20352 as_bad (_("unknown architecture `%s'\n"), str);
20357 arm_parse_fpu (char * str)
20359 const struct arm_option_cpu_value_table * opt;
20361 for (opt = arm_fpus; opt->name != NULL; opt++)
20362 if (streq (opt->name, str))
20364 mfpu_opt = &opt->value;
20368 as_bad (_("unknown floating point format `%s'\n"), str);
20373 arm_parse_float_abi (char * str)
20375 const struct arm_option_value_table * opt;
20377 for (opt = arm_float_abis; opt->name != NULL; opt++)
20378 if (streq (opt->name, str))
20380 mfloat_abi_opt = opt->value;
20384 as_bad (_("unknown floating point abi `%s'\n"), str);
20390 arm_parse_eabi (char * str)
20392 const struct arm_option_value_table *opt;
20394 for (opt = arm_eabis; opt->name != NULL; opt++)
20395 if (streq (opt->name, str))
20397 meabi_flags = opt->value;
20400 as_bad (_("unknown EABI `%s'\n"), str);
20405 struct arm_long_option_table arm_long_opts[] =
20407 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
20408 arm_parse_cpu, NULL},
20409 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
20410 arm_parse_arch, NULL},
20411 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
20412 arm_parse_fpu, NULL},
20413 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
20414 arm_parse_float_abi, NULL},
20416 {"meabi=", N_("<ver>\t assemble for eabi version <ver>"),
20417 arm_parse_eabi, NULL},
20419 {NULL, NULL, 0, NULL}
20423 md_parse_option (int c, char * arg)
20425 struct arm_option_table *opt;
20426 const struct arm_legacy_option_table *fopt;
20427 struct arm_long_option_table *lopt;
20433 target_big_endian = 1;
20439 target_big_endian = 0;
20444 /* Listing option. Just ignore these, we don't support additional
20449 for (opt = arm_opts; opt->option != NULL; opt++)
20451 if (c == opt->option[0]
20452 && ((arg == NULL && opt->option[1] == 0)
20453 || streq (arg, opt->option + 1)))
20455 #if WARN_DEPRECATED
20456 /* If the option is deprecated, tell the user. */
20457 if (opt->deprecated != NULL)
20458 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
20459 arg ? arg : "", _(opt->deprecated));
20462 if (opt->var != NULL)
20463 *opt->var = opt->value;
20469 for (fopt = arm_legacy_opts; fopt->option != NULL; fopt++)
20471 if (c == fopt->option[0]
20472 && ((arg == NULL && fopt->option[1] == 0)
20473 || streq (arg, fopt->option + 1)))
20475 #if WARN_DEPRECATED
20476 /* If the option is deprecated, tell the user. */
20477 if (fopt->deprecated != NULL)
20478 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
20479 arg ? arg : "", _(fopt->deprecated));
20482 if (fopt->var != NULL)
20483 *fopt->var = &fopt->value;
20489 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
20491 /* These options are expected to have an argument. */
20492 if (c == lopt->option[0]
20494 && strncmp (arg, lopt->option + 1,
20495 strlen (lopt->option + 1)) == 0)
20497 #if WARN_DEPRECATED
20498 /* If the option is deprecated, tell the user. */
20499 if (lopt->deprecated != NULL)
20500 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, arg,
20501 _(lopt->deprecated));
20504 /* Call the sup-option parser. */
20505 return lopt->func (arg + strlen (lopt->option) - 1);
20516 md_show_usage (FILE * fp)
20518 struct arm_option_table *opt;
20519 struct arm_long_option_table *lopt;
20521 fprintf (fp, _(" ARM-specific assembler options:\n"));
20523 for (opt = arm_opts; opt->option != NULL; opt++)
20524 if (opt->help != NULL)
20525 fprintf (fp, " -%-23s%s\n", opt->option, _(opt->help));
20527 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
20528 if (lopt->help != NULL)
20529 fprintf (fp, " -%s%s\n", lopt->option, _(lopt->help));
20533 -EB assemble code for a big-endian cpu\n"));
20538 -EL assemble code for a little-endian cpu\n"));
20547 arm_feature_set flags;
20548 } cpu_arch_ver_table;
20550 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
20551 least features first. */
20552 static const cpu_arch_ver_table cpu_arch_ver[] =
20557 {4, ARM_ARCH_V5TE},
20558 {5, ARM_ARCH_V5TEJ},
20562 {9, ARM_ARCH_V6T2},
20563 {10, ARM_ARCH_V7A},
20564 {10, ARM_ARCH_V7R},
20565 {10, ARM_ARCH_V7M},
20569 /* Set the public EABI object attributes. */
20571 aeabi_set_public_attributes (void)
20574 arm_feature_set flags;
20575 arm_feature_set tmp;
20576 const cpu_arch_ver_table *p;
20578 /* Choose the architecture based on the capabilities of the requested cpu
20579 (if any) and/or the instructions actually used. */
20580 ARM_MERGE_FEATURE_SETS (flags, arm_arch_used, thumb_arch_used);
20581 ARM_MERGE_FEATURE_SETS (flags, flags, *mfpu_opt);
20582 ARM_MERGE_FEATURE_SETS (flags, flags, selected_cpu);
20583 /*Allow the user to override the reported architecture. */
20586 ARM_CLEAR_FEATURE (flags, flags, arm_arch_any);
20587 ARM_MERGE_FEATURE_SETS (flags, flags, *object_arch);
20592 for (p = cpu_arch_ver; p->val; p++)
20594 if (ARM_CPU_HAS_FEATURE (tmp, p->flags))
20597 ARM_CLEAR_FEATURE (tmp, tmp, p->flags);
20601 /* Tag_CPU_name. */
20602 if (selected_cpu_name[0])
20606 p = selected_cpu_name;
20607 if (strncmp(p, "armv", 4) == 0)
20612 for (i = 0; p[i]; i++)
20613 p[i] = TOUPPER (p[i]);
20615 bfd_elf_add_proc_attr_string (stdoutput, 5, p);
20617 /* Tag_CPU_arch. */
20618 bfd_elf_add_proc_attr_int (stdoutput, 6, arch);
20619 /* Tag_CPU_arch_profile. */
20620 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a))
20621 bfd_elf_add_proc_attr_int (stdoutput, 7, 'A');
20622 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7r))
20623 bfd_elf_add_proc_attr_int (stdoutput, 7, 'R');
20624 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7m))
20625 bfd_elf_add_proc_attr_int (stdoutput, 7, 'M');
20626 /* Tag_ARM_ISA_use. */
20627 if (ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_full))
20628 bfd_elf_add_proc_attr_int (stdoutput, 8, 1);
20629 /* Tag_THUMB_ISA_use. */
20630 if (ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_full))
20631 bfd_elf_add_proc_attr_int (stdoutput, 9,
20632 ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_t2) ? 2 : 1);
20633 /* Tag_VFP_arch. */
20634 if (ARM_CPU_HAS_FEATURE (thumb_arch_used, fpu_vfp_ext_v3)
20635 || ARM_CPU_HAS_FEATURE (arm_arch_used, fpu_vfp_ext_v3))
20636 bfd_elf_add_proc_attr_int (stdoutput, 10, 3);
20637 else if (ARM_CPU_HAS_FEATURE (thumb_arch_used, fpu_vfp_ext_v2)
20638 || ARM_CPU_HAS_FEATURE (arm_arch_used, fpu_vfp_ext_v2))
20639 bfd_elf_add_proc_attr_int (stdoutput, 10, 2);
20640 else if (ARM_CPU_HAS_FEATURE (thumb_arch_used, fpu_vfp_ext_v1)
20641 || ARM_CPU_HAS_FEATURE (arm_arch_used, fpu_vfp_ext_v1)
20642 || ARM_CPU_HAS_FEATURE (thumb_arch_used, fpu_vfp_ext_v1xd)
20643 || ARM_CPU_HAS_FEATURE (arm_arch_used, fpu_vfp_ext_v1xd))
20644 bfd_elf_add_proc_attr_int (stdoutput, 10, 1);
20645 /* Tag_WMMX_arch. */
20646 if (ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_cext_iwmmxt)
20647 || ARM_CPU_HAS_FEATURE (arm_arch_used, arm_cext_iwmmxt))
20648 bfd_elf_add_proc_attr_int (stdoutput, 11, 1);
20649 /* Tag_NEON_arch. */
20650 if (ARM_CPU_HAS_FEATURE (thumb_arch_used, fpu_neon_ext_v1)
20651 || ARM_CPU_HAS_FEATURE (arm_arch_used, fpu_neon_ext_v1))
20652 bfd_elf_add_proc_attr_int (stdoutput, 12, 1);
20655 /* Add the default contents for the .ARM.attributes section. */
20659 if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
20662 aeabi_set_public_attributes ();
20664 #endif /* OBJ_ELF */
20667 /* Parse a .cpu directive. */
20670 s_arm_cpu (int ignored ATTRIBUTE_UNUSED)
20672 const struct arm_cpu_option_table *opt;
20676 name = input_line_pointer;
20677 while (*input_line_pointer && !ISSPACE(*input_line_pointer))
20678 input_line_pointer++;
20679 saved_char = *input_line_pointer;
20680 *input_line_pointer = 0;
20682 /* Skip the first "all" entry. */
20683 for (opt = arm_cpus + 1; opt->name != NULL; opt++)
20684 if (streq (opt->name, name))
20686 mcpu_cpu_opt = &opt->value;
20687 selected_cpu = opt->value;
20688 if (opt->canonical_name)
20689 strcpy(selected_cpu_name, opt->canonical_name);
20693 for (i = 0; opt->name[i]; i++)
20694 selected_cpu_name[i] = TOUPPER (opt->name[i]);
20695 selected_cpu_name[i] = 0;
20697 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
20698 *input_line_pointer = saved_char;
20699 demand_empty_rest_of_line ();
20702 as_bad (_("unknown cpu `%s'"), name);
20703 *input_line_pointer = saved_char;
20704 ignore_rest_of_line ();
20708 /* Parse a .arch directive. */
20711 s_arm_arch (int ignored ATTRIBUTE_UNUSED)
20713 const struct arm_arch_option_table *opt;
20717 name = input_line_pointer;
20718 while (*input_line_pointer && !ISSPACE(*input_line_pointer))
20719 input_line_pointer++;
20720 saved_char = *input_line_pointer;
20721 *input_line_pointer = 0;
20723 /* Skip the first "all" entry. */
20724 for (opt = arm_archs + 1; opt->name != NULL; opt++)
20725 if (streq (opt->name, name))
20727 mcpu_cpu_opt = &opt->value;
20728 selected_cpu = opt->value;
20729 strcpy(selected_cpu_name, opt->name);
20730 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
20731 *input_line_pointer = saved_char;
20732 demand_empty_rest_of_line ();
20736 as_bad (_("unknown architecture `%s'\n"), name);
20737 *input_line_pointer = saved_char;
20738 ignore_rest_of_line ();
20742 /* Parse a .object_arch directive. */
20745 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED)
20747 const struct arm_arch_option_table *opt;
20751 name = input_line_pointer;
20752 while (*input_line_pointer && !ISSPACE(*input_line_pointer))
20753 input_line_pointer++;
20754 saved_char = *input_line_pointer;
20755 *input_line_pointer = 0;
20757 /* Skip the first "all" entry. */
20758 for (opt = arm_archs + 1; opt->name != NULL; opt++)
20759 if (streq (opt->name, name))
20761 object_arch = &opt->value;
20762 *input_line_pointer = saved_char;
20763 demand_empty_rest_of_line ();
20767 as_bad (_("unknown architecture `%s'\n"), name);
20768 *input_line_pointer = saved_char;
20769 ignore_rest_of_line ();
20773 /* Parse a .fpu directive. */
20776 s_arm_fpu (int ignored ATTRIBUTE_UNUSED)
20778 const struct arm_option_cpu_value_table *opt;
20782 name = input_line_pointer;
20783 while (*input_line_pointer && !ISSPACE(*input_line_pointer))
20784 input_line_pointer++;
20785 saved_char = *input_line_pointer;
20786 *input_line_pointer = 0;
20788 for (opt = arm_fpus; opt->name != NULL; opt++)
20789 if (streq (opt->name, name))
20791 mfpu_opt = &opt->value;
20792 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
20793 *input_line_pointer = saved_char;
20794 demand_empty_rest_of_line ();
20798 as_bad (_("unknown floating point format `%s'\n"), name);
20799 *input_line_pointer = saved_char;
20800 ignore_rest_of_line ();
20803 /* Copy symbol information. */
20805 arm_copy_symbol_attributes (symbolS *dest, symbolS *src)
20807 ARM_GET_FLAG (dest) = ARM_GET_FLAG (src);