1 /* Output routines for GCC for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
5 and Martin Simmons (@harleqn.co.uk).
6 More major hacks by Richard Earnshaw (rearnsha@arm.com).
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify it
11 under the terms of the GNU General Public License as published
12 by the Free Software Foundation; either version 2, or (at your
13 option) any later version.
15 GCC is distributed in the hope that it will be useful, but WITHOUT
16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
18 License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING. If not, write to
22 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
23 Boston, MA 02110-1301, USA. */
27 #include "coretypes.h"
33 #include "hard-reg-set.h"
35 #include "insn-config.h"
36 #include "conditions.h"
38 #include "insn-attr.h"
49 #include "integrate.h"
52 #include "target-def.h"
54 #include "langhooks.h"
56 /* Forward definitions of types. */
57 typedef struct minipool_node Mnode;
58 typedef struct minipool_fixup Mfix;
60 const struct attribute_spec arm_attribute_table[];
62 /* Forward function declarations. */
63 static arm_stack_offsets *arm_get_frame_offsets (void);
64 static void arm_add_gc_roots (void);
65 static int arm_gen_constant (enum rtx_code, enum machine_mode, rtx,
66 HOST_WIDE_INT, rtx, rtx, int, int);
67 static unsigned bit_count (unsigned long);
68 static int arm_address_register_rtx_p (rtx, int);
69 static int arm_legitimate_index_p (enum machine_mode, rtx, RTX_CODE, int);
70 static int thumb_base_register_rtx_p (rtx, enum machine_mode, int);
71 inline static int thumb_index_register_rtx_p (rtx, int);
72 static int thumb_far_jump_used_p (void);
73 static bool thumb_force_lr_save (void);
74 static int const_ok_for_op (HOST_WIDE_INT, enum rtx_code);
75 static rtx emit_sfm (int, int);
76 static int arm_size_return_regs (void);
78 static bool arm_assemble_integer (rtx, unsigned int, int);
80 static const char *fp_const_from_val (REAL_VALUE_TYPE *);
81 static arm_cc get_arm_condition_code (rtx);
82 static HOST_WIDE_INT int_log2 (HOST_WIDE_INT);
83 static rtx is_jump_table (rtx);
84 static const char *output_multi_immediate (rtx *, const char *, const char *,
86 static const char *shift_op (rtx, HOST_WIDE_INT *);
87 static struct machine_function *arm_init_machine_status (void);
88 static void thumb_exit (FILE *, int);
89 static rtx is_jump_table (rtx);
90 static HOST_WIDE_INT get_jump_table_size (rtx);
91 static Mnode *move_minipool_fix_forward_ref (Mnode *, Mnode *, HOST_WIDE_INT);
92 static Mnode *add_minipool_forward_ref (Mfix *);
93 static Mnode *move_minipool_fix_backward_ref (Mnode *, Mnode *, HOST_WIDE_INT);
94 static Mnode *add_minipool_backward_ref (Mfix *);
95 static void assign_minipool_offsets (Mfix *);
96 static void arm_print_value (FILE *, rtx);
97 static void dump_minipool (rtx);
98 static int arm_barrier_cost (rtx);
99 static Mfix *create_fix_barrier (Mfix *, HOST_WIDE_INT);
100 static void push_minipool_barrier (rtx, HOST_WIDE_INT);
101 static void push_minipool_fix (rtx, HOST_WIDE_INT, rtx *, enum machine_mode,
103 static void arm_reorg (void);
104 static bool note_invalid_constants (rtx, HOST_WIDE_INT, int);
105 static int current_file_function_operand (rtx);
106 static unsigned long arm_compute_save_reg0_reg12_mask (void);
107 static unsigned long arm_compute_save_reg_mask (void);
108 static unsigned long arm_isr_value (tree);
109 static unsigned long arm_compute_func_type (void);
110 static tree arm_handle_fndecl_attribute (tree *, tree, tree, int, bool *);
111 static tree arm_handle_isr_attribute (tree *, tree, tree, int, bool *);
112 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
113 static tree arm_handle_notshared_attribute (tree *, tree, tree, int, bool *);
115 static void arm_output_function_epilogue (FILE *, HOST_WIDE_INT);
116 static void arm_output_function_prologue (FILE *, HOST_WIDE_INT);
117 static void thumb_output_function_prologue (FILE *, HOST_WIDE_INT);
118 static int arm_comp_type_attributes (tree, tree);
119 static void arm_set_default_type_attributes (tree);
120 static int arm_adjust_cost (rtx, rtx, rtx, int);
121 static int count_insns_for_constant (HOST_WIDE_INT, int);
122 static int arm_get_strip_length (int);
123 static bool arm_function_ok_for_sibcall (tree, tree);
124 static void arm_internal_label (FILE *, const char *, unsigned long);
125 static void arm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,
127 static int arm_rtx_costs_1 (rtx, enum rtx_code, enum rtx_code);
128 static bool arm_size_rtx_costs (rtx, int, int, int *);
129 static bool arm_slowmul_rtx_costs (rtx, int, int, int *);
130 static bool arm_fastmul_rtx_costs (rtx, int, int, int *);
131 static bool arm_xscale_rtx_costs (rtx, int, int, int *);
132 static bool arm_9e_rtx_costs (rtx, int, int, int *);
133 static int arm_address_cost (rtx);
134 static bool arm_memory_load_p (rtx);
135 static bool arm_cirrus_insn_p (rtx);
136 static void cirrus_reorg (rtx);
137 static void arm_init_builtins (void);
138 static rtx arm_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
139 static void arm_init_iwmmxt_builtins (void);
140 static rtx safe_vector_operand (rtx, enum machine_mode);
141 static rtx arm_expand_binop_builtin (enum insn_code, tree, rtx);
142 static rtx arm_expand_unop_builtin (enum insn_code, tree, rtx, int);
143 static rtx arm_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
144 static void emit_constant_insn (rtx cond, rtx pattern);
145 static rtx emit_set_insn (rtx, rtx);
146 static int arm_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
149 #ifdef OBJECT_FORMAT_ELF
150 static void arm_elf_asm_constructor (rtx, int);
153 static void arm_encode_section_info (tree, rtx, int);
156 static void arm_file_end (void);
159 static void aof_globalize_label (FILE *, const char *);
160 static void aof_dump_imports (FILE *);
161 static void aof_dump_pic_table (FILE *);
162 static void aof_file_start (void);
163 static void aof_file_end (void);
164 static void aof_asm_init_sections (void);
166 static void arm_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode,
168 static bool arm_pass_by_reference (CUMULATIVE_ARGS *,
169 enum machine_mode, tree, bool);
170 static bool arm_promote_prototypes (tree);
171 static bool arm_default_short_enums (void);
172 static bool arm_align_anon_bitfield (void);
173 static bool arm_return_in_msb (tree);
174 static bool arm_must_pass_in_stack (enum machine_mode, tree);
175 #ifdef TARGET_UNWIND_INFO
176 static void arm_unwind_emit (FILE *, rtx);
177 static bool arm_output_ttype (rtx);
180 static tree arm_cxx_guard_type (void);
181 static bool arm_cxx_guard_mask_bit (void);
182 static tree arm_get_cookie_size (tree);
183 static bool arm_cookie_has_size (void);
184 static bool arm_cxx_cdtor_returns_this (void);
185 static bool arm_cxx_key_method_may_be_inline (void);
186 static void arm_cxx_determine_class_data_visibility (tree);
187 static bool arm_cxx_class_data_always_comdat (void);
188 static bool arm_cxx_use_aeabi_atexit (void);
189 static void arm_init_libfuncs (void);
190 static bool arm_handle_option (size_t, const char *, int);
191 static unsigned HOST_WIDE_INT arm_shift_truncation_mask (enum machine_mode);
192 static bool arm_cannot_copy_insn_p (rtx);
193 static bool arm_tls_symbol_p (rtx x);
196 /* Initialize the GCC target structure. */
197 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
198 #undef TARGET_MERGE_DECL_ATTRIBUTES
199 #define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
202 #undef TARGET_ATTRIBUTE_TABLE
203 #define TARGET_ATTRIBUTE_TABLE arm_attribute_table
205 #undef TARGET_ASM_FILE_END
206 #define TARGET_ASM_FILE_END arm_file_end
209 #undef TARGET_ASM_BYTE_OP
210 #define TARGET_ASM_BYTE_OP "\tDCB\t"
211 #undef TARGET_ASM_ALIGNED_HI_OP
212 #define TARGET_ASM_ALIGNED_HI_OP "\tDCW\t"
213 #undef TARGET_ASM_ALIGNED_SI_OP
214 #define TARGET_ASM_ALIGNED_SI_OP "\tDCD\t"
215 #undef TARGET_ASM_GLOBALIZE_LABEL
216 #define TARGET_ASM_GLOBALIZE_LABEL aof_globalize_label
217 #undef TARGET_ASM_FILE_START
218 #define TARGET_ASM_FILE_START aof_file_start
219 #undef TARGET_ASM_FILE_END
220 #define TARGET_ASM_FILE_END aof_file_end
222 #undef TARGET_ASM_ALIGNED_SI_OP
223 #define TARGET_ASM_ALIGNED_SI_OP NULL
224 #undef TARGET_ASM_INTEGER
225 #define TARGET_ASM_INTEGER arm_assemble_integer
228 #undef TARGET_ASM_FUNCTION_PROLOGUE
229 #define TARGET_ASM_FUNCTION_PROLOGUE arm_output_function_prologue
231 #undef TARGET_ASM_FUNCTION_EPILOGUE
232 #define TARGET_ASM_FUNCTION_EPILOGUE arm_output_function_epilogue
234 #undef TARGET_DEFAULT_TARGET_FLAGS
235 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | MASK_SCHED_PROLOG)
236 #undef TARGET_HANDLE_OPTION
237 #define TARGET_HANDLE_OPTION arm_handle_option
239 #undef TARGET_COMP_TYPE_ATTRIBUTES
240 #define TARGET_COMP_TYPE_ATTRIBUTES arm_comp_type_attributes
242 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
243 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES arm_set_default_type_attributes
245 #undef TARGET_SCHED_ADJUST_COST
246 #define TARGET_SCHED_ADJUST_COST arm_adjust_cost
248 #undef TARGET_ENCODE_SECTION_INFO
250 #define TARGET_ENCODE_SECTION_INFO arm_pe_encode_section_info
252 #define TARGET_ENCODE_SECTION_INFO arm_encode_section_info
255 #undef TARGET_STRIP_NAME_ENCODING
256 #define TARGET_STRIP_NAME_ENCODING arm_strip_name_encoding
258 #undef TARGET_ASM_INTERNAL_LABEL
259 #define TARGET_ASM_INTERNAL_LABEL arm_internal_label
261 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
262 #define TARGET_FUNCTION_OK_FOR_SIBCALL arm_function_ok_for_sibcall
264 #undef TARGET_ASM_OUTPUT_MI_THUNK
265 #define TARGET_ASM_OUTPUT_MI_THUNK arm_output_mi_thunk
266 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
267 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
269 /* This will be overridden in arm_override_options. */
270 #undef TARGET_RTX_COSTS
271 #define TARGET_RTX_COSTS arm_slowmul_rtx_costs
272 #undef TARGET_ADDRESS_COST
273 #define TARGET_ADDRESS_COST arm_address_cost
275 #undef TARGET_SHIFT_TRUNCATION_MASK
276 #define TARGET_SHIFT_TRUNCATION_MASK arm_shift_truncation_mask
277 #undef TARGET_VECTOR_MODE_SUPPORTED_P
278 #define TARGET_VECTOR_MODE_SUPPORTED_P arm_vector_mode_supported_p
280 #undef TARGET_MACHINE_DEPENDENT_REORG
281 #define TARGET_MACHINE_DEPENDENT_REORG arm_reorg
283 #undef TARGET_INIT_BUILTINS
284 #define TARGET_INIT_BUILTINS arm_init_builtins
285 #undef TARGET_EXPAND_BUILTIN
286 #define TARGET_EXPAND_BUILTIN arm_expand_builtin
288 #undef TARGET_INIT_LIBFUNCS
289 #define TARGET_INIT_LIBFUNCS arm_init_libfuncs
291 #undef TARGET_PROMOTE_FUNCTION_ARGS
292 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
293 #undef TARGET_PROMOTE_FUNCTION_RETURN
294 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
295 #undef TARGET_PROMOTE_PROTOTYPES
296 #define TARGET_PROMOTE_PROTOTYPES arm_promote_prototypes
297 #undef TARGET_PASS_BY_REFERENCE
298 #define TARGET_PASS_BY_REFERENCE arm_pass_by_reference
299 #undef TARGET_ARG_PARTIAL_BYTES
300 #define TARGET_ARG_PARTIAL_BYTES arm_arg_partial_bytes
302 #undef TARGET_SETUP_INCOMING_VARARGS
303 #define TARGET_SETUP_INCOMING_VARARGS arm_setup_incoming_varargs
305 #undef TARGET_DEFAULT_SHORT_ENUMS
306 #define TARGET_DEFAULT_SHORT_ENUMS arm_default_short_enums
308 #undef TARGET_ALIGN_ANON_BITFIELD
309 #define TARGET_ALIGN_ANON_BITFIELD arm_align_anon_bitfield
311 #undef TARGET_NARROW_VOLATILE_BITFIELD
312 #define TARGET_NARROW_VOLATILE_BITFIELD hook_bool_void_false
314 #undef TARGET_CXX_GUARD_TYPE
315 #define TARGET_CXX_GUARD_TYPE arm_cxx_guard_type
317 #undef TARGET_CXX_GUARD_MASK_BIT
318 #define TARGET_CXX_GUARD_MASK_BIT arm_cxx_guard_mask_bit
320 #undef TARGET_CXX_GET_COOKIE_SIZE
321 #define TARGET_CXX_GET_COOKIE_SIZE arm_get_cookie_size
323 #undef TARGET_CXX_COOKIE_HAS_SIZE
324 #define TARGET_CXX_COOKIE_HAS_SIZE arm_cookie_has_size
326 #undef TARGET_CXX_CDTOR_RETURNS_THIS
327 #define TARGET_CXX_CDTOR_RETURNS_THIS arm_cxx_cdtor_returns_this
329 #undef TARGET_CXX_KEY_METHOD_MAY_BE_INLINE
330 #define TARGET_CXX_KEY_METHOD_MAY_BE_INLINE arm_cxx_key_method_may_be_inline
332 #undef TARGET_CXX_USE_AEABI_ATEXIT
333 #define TARGET_CXX_USE_AEABI_ATEXIT arm_cxx_use_aeabi_atexit
335 #undef TARGET_CXX_DETERMINE_CLASS_DATA_VISIBILITY
336 #define TARGET_CXX_DETERMINE_CLASS_DATA_VISIBILITY \
337 arm_cxx_determine_class_data_visibility
339 #undef TARGET_CXX_CLASS_DATA_ALWAYS_COMDAT
340 #define TARGET_CXX_CLASS_DATA_ALWAYS_COMDAT arm_cxx_class_data_always_comdat
342 #undef TARGET_RETURN_IN_MSB
343 #define TARGET_RETURN_IN_MSB arm_return_in_msb
345 #undef TARGET_MUST_PASS_IN_STACK
346 #define TARGET_MUST_PASS_IN_STACK arm_must_pass_in_stack
348 #ifdef TARGET_UNWIND_INFO
349 #undef TARGET_UNWIND_EMIT
350 #define TARGET_UNWIND_EMIT arm_unwind_emit
352 /* EABI unwinding tables use a different format for the typeinfo tables. */
353 #undef TARGET_ASM_TTYPE
354 #define TARGET_ASM_TTYPE arm_output_ttype
356 #undef TARGET_ARM_EABI_UNWINDER
357 #define TARGET_ARM_EABI_UNWINDER true
358 #endif /* TARGET_UNWIND_INFO */
360 #undef TARGET_CANNOT_COPY_INSN_P
361 #define TARGET_CANNOT_COPY_INSN_P arm_cannot_copy_insn_p
364 #undef TARGET_HAVE_TLS
365 #define TARGET_HAVE_TLS true
368 #undef TARGET_CANNOT_FORCE_CONST_MEM
369 #define TARGET_CANNOT_FORCE_CONST_MEM arm_tls_referenced_p
371 struct gcc_target targetm = TARGET_INITIALIZER;
373 /* Obstack for minipool constant handling. */
374 static struct obstack minipool_obstack;
375 static char * minipool_startobj;
377 /* The maximum number of insns skipped which
378 will be conditionalised if possible. */
379 static int max_insns_skipped = 5;
381 extern FILE * asm_out_file;
383 /* True if we are currently building a constant table. */
384 int making_const_table;
386 /* Define the information needed to generate branch insns. This is
387 stored from the compare operation. */
388 rtx arm_compare_op0, arm_compare_op1;
390 /* The processor for which instructions should be scheduled. */
391 enum processor_type arm_tune = arm_none;
393 /* Which floating point model to use. */
394 enum arm_fp_model arm_fp_model;
396 /* Which floating point hardware is available. */
397 enum fputype arm_fpu_arch;
399 /* Which floating point hardware to schedule for. */
400 enum fputype arm_fpu_tune;
402 /* Whether to use floating point hardware. */
403 enum float_abi_type arm_float_abi;
405 /* Which ABI to use. */
406 enum arm_abi_type arm_abi;
408 /* Which thread pointer model to use. */
409 enum arm_tp_type target_thread_pointer = TP_AUTO;
411 /* Used to parse -mstructure_size_boundary command line option. */
412 int arm_structure_size_boundary = DEFAULT_STRUCTURE_SIZE_BOUNDARY;
414 /* Used for Thumb call_via trampolines. */
415 rtx thumb_call_via_label[14];
416 static int thumb_call_reg_needed;
418 /* Bit values used to identify processor capabilities. */
419 #define FL_CO_PROC (1 << 0) /* Has external co-processor bus */
420 #define FL_ARCH3M (1 << 1) /* Extended multiply */
421 #define FL_MODE26 (1 << 2) /* 26-bit mode support */
422 #define FL_MODE32 (1 << 3) /* 32-bit mode support */
423 #define FL_ARCH4 (1 << 4) /* Architecture rel 4 */
424 #define FL_ARCH5 (1 << 5) /* Architecture rel 5 */
425 #define FL_THUMB (1 << 6) /* Thumb aware */
426 #define FL_LDSCHED (1 << 7) /* Load scheduling necessary */
427 #define FL_STRONG (1 << 8) /* StrongARM */
428 #define FL_ARCH5E (1 << 9) /* DSP extensions to v5 */
429 #define FL_XSCALE (1 << 10) /* XScale */
430 #define FL_CIRRUS (1 << 11) /* Cirrus/DSP. */
431 #define FL_ARCH6 (1 << 12) /* Architecture rel 6. Adds
432 media instructions. */
433 #define FL_VFPV2 (1 << 13) /* Vector Floating Point V2. */
434 #define FL_WBUF (1 << 14) /* Schedule for write buffer ops.
435 Note: ARM6 & 7 derivatives only. */
436 #define FL_ARCH6K (1 << 15) /* Architecture rel 6 K extensions. */
438 #define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */
440 #define FL_FOR_ARCH2 0
441 #define FL_FOR_ARCH3 FL_MODE32
442 #define FL_FOR_ARCH3M (FL_FOR_ARCH3 | FL_ARCH3M)
443 #define FL_FOR_ARCH4 (FL_FOR_ARCH3M | FL_ARCH4)
444 #define FL_FOR_ARCH4T (FL_FOR_ARCH4 | FL_THUMB)
445 #define FL_FOR_ARCH5 (FL_FOR_ARCH4 | FL_ARCH5)
446 #define FL_FOR_ARCH5T (FL_FOR_ARCH5 | FL_THUMB)
447 #define FL_FOR_ARCH5E (FL_FOR_ARCH5 | FL_ARCH5E)
448 #define FL_FOR_ARCH5TE (FL_FOR_ARCH5E | FL_THUMB)
449 #define FL_FOR_ARCH5TEJ FL_FOR_ARCH5TE
450 #define FL_FOR_ARCH6 (FL_FOR_ARCH5TE | FL_ARCH6)
451 #define FL_FOR_ARCH6J FL_FOR_ARCH6
452 #define FL_FOR_ARCH6K (FL_FOR_ARCH6 | FL_ARCH6K)
453 #define FL_FOR_ARCH6Z FL_FOR_ARCH6
454 #define FL_FOR_ARCH6ZK FL_FOR_ARCH6K
456 /* The bits in this mask specify which
457 instructions we are allowed to generate. */
458 static unsigned long insn_flags = 0;
460 /* The bits in this mask specify which instruction scheduling options should
462 static unsigned long tune_flags = 0;
464 /* The following are used in the arm.md file as equivalents to bits
465 in the above two flag variables. */
467 /* Nonzero if this chip supports the ARM Architecture 3M extensions. */
470 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
473 /* Nonzero if this chip supports the ARM Architecture 4t extensions. */
476 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
479 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
482 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */
485 /* Nonzero if this chip supports the ARM 6K extensions. */
488 /* Nonzero if this chip can benefit from load scheduling. */
489 int arm_ld_sched = 0;
491 /* Nonzero if this chip is a StrongARM. */
492 int arm_tune_strongarm = 0;
494 /* Nonzero if this chip is a Cirrus variant. */
495 int arm_arch_cirrus = 0;
497 /* Nonzero if this chip supports Intel Wireless MMX technology. */
498 int arm_arch_iwmmxt = 0;
500 /* Nonzero if this chip is an XScale. */
501 int arm_arch_xscale = 0;
503 /* Nonzero if tuning for XScale */
504 int arm_tune_xscale = 0;
506 /* Nonzero if we want to tune for stores that access the write-buffer.
507 This typically means an ARM6 or ARM7 with MMU or MPU. */
508 int arm_tune_wbuf = 0;
510 /* Nonzero if generating Thumb instructions. */
513 /* Nonzero if we should define __THUMB_INTERWORK__ in the
515 XXX This is a bit of a hack, it's intended to help work around
516 problems in GLD which doesn't understand that armv5t code is
517 interworking clean. */
518 int arm_cpp_interwork = 0;
520 /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we
521 must report the mode of the memory reference from PRINT_OPERAND to
522 PRINT_OPERAND_ADDRESS. */
523 enum machine_mode output_memory_reference_mode;
525 /* The register number to be used for the PIC offset register. */
526 unsigned arm_pic_register = INVALID_REGNUM;
528 /* Set to 1 when a return insn is output, this means that the epilogue
530 int return_used_this_function;
532 /* Set to 1 after arm_reorg has started. Reset to start at the start of
533 the next function. */
534 static int after_arm_reorg = 0;
536 /* The maximum number of insns to be used when loading a constant. */
537 static int arm_constant_limit = 3;
539 /* For an explanation of these variables, see final_prescan_insn below. */
541 enum arm_cond_code arm_current_cc;
543 int arm_target_label;
545 /* The condition codes of the ARM, and the inverse function. */
546 static const char * const arm_condition_codes[] =
548 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
549 "hi", "ls", "ge", "lt", "gt", "le", "al", "nv"
552 #define streq(string1, string2) (strcmp (string1, string2) == 0)
554 /* Initialization code. */
558 const char *const name;
559 enum processor_type core;
561 const unsigned long flags;
562 bool (* rtx_costs) (rtx, int, int, int *);
565 /* Not all of these give usefully different compilation alternatives,
566 but there is no simple way of generalizing them. */
567 static const struct processors all_cores[] =
570 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
571 {NAME, arm_none, #ARCH, FLAGS | FL_FOR_ARCH##ARCH, arm_##COSTS##_rtx_costs},
572 #include "arm-cores.def"
574 {NULL, arm_none, NULL, 0, NULL}
577 static const struct processors all_architectures[] =
579 /* ARM Architectures */
580 /* We don't specify rtx_costs here as it will be figured out
583 {"armv2", arm2, "2", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2, NULL},
584 {"armv2a", arm2, "2", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2, NULL},
585 {"armv3", arm6, "3", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3, NULL},
586 {"armv3m", arm7m, "3M", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3M, NULL},
587 {"armv4", arm7tdmi, "4", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH4, NULL},
588 /* Strictly, FL_MODE26 is a permitted option for v4t, but there are no
589 implementations that support it, so we will leave it out for now. */
590 {"armv4t", arm7tdmi, "4T", FL_CO_PROC | FL_FOR_ARCH4T, NULL},
591 {"armv5", arm10tdmi, "5", FL_CO_PROC | FL_FOR_ARCH5, NULL},
592 {"armv5t", arm10tdmi, "5T", FL_CO_PROC | FL_FOR_ARCH5T, NULL},
593 {"armv5e", arm1026ejs, "5E", FL_CO_PROC | FL_FOR_ARCH5E, NULL},
594 {"armv5te", arm1026ejs, "5TE", FL_CO_PROC | FL_FOR_ARCH5TE, NULL},
595 {"armv6", arm1136js, "6", FL_CO_PROC | FL_FOR_ARCH6, NULL},
596 {"armv6j", arm1136js, "6J", FL_CO_PROC | FL_FOR_ARCH6J, NULL},
597 {"armv6k", mpcore, "6K", FL_CO_PROC | FL_FOR_ARCH6K, NULL},
598 {"armv6z", arm1176jzs, "6Z", FL_CO_PROC | FL_FOR_ARCH6Z, NULL},
599 {"armv6zk", arm1176jzs, "6ZK", FL_CO_PROC | FL_FOR_ARCH6ZK, NULL},
600 {"ep9312", ep9312, "4T", FL_LDSCHED | FL_CIRRUS | FL_FOR_ARCH4, NULL},
601 {"iwmmxt", iwmmxt, "5TE", FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT , NULL},
602 {NULL, arm_none, NULL, 0 , NULL}
605 struct arm_cpu_select
609 const struct processors * processors;
612 /* This is a magic structure. The 'string' field is magically filled in
613 with a pointer to the value specified by the user on the command line
614 assuming that the user has specified such a value. */
616 static struct arm_cpu_select arm_select[] =
618 /* string name processors */
619 { NULL, "-mcpu=", all_cores },
620 { NULL, "-march=", all_architectures },
621 { NULL, "-mtune=", all_cores }
624 /* Defines representing the indexes into the above table. */
625 #define ARM_OPT_SET_CPU 0
626 #define ARM_OPT_SET_ARCH 1
627 #define ARM_OPT_SET_TUNE 2
629 /* The name of the preprocessor macro to define for this architecture. */
631 char arm_arch_name[] = "__ARM_ARCH_0UNK__";
640 /* Available values for -mfpu=. */
642 static const struct fpu_desc all_fpus[] =
644 {"fpa", FPUTYPE_FPA},
645 {"fpe2", FPUTYPE_FPA_EMU2},
646 {"fpe3", FPUTYPE_FPA_EMU2},
647 {"maverick", FPUTYPE_MAVERICK},
652 /* Floating point models used by the different hardware.
653 See fputype in arm.h. */
655 static const enum fputype fp_model_for_fpu[] =
657 /* No FP hardware. */
658 ARM_FP_MODEL_UNKNOWN, /* FPUTYPE_NONE */
659 ARM_FP_MODEL_FPA, /* FPUTYPE_FPA */
660 ARM_FP_MODEL_FPA, /* FPUTYPE_FPA_EMU2 */
661 ARM_FP_MODEL_FPA, /* FPUTYPE_FPA_EMU3 */
662 ARM_FP_MODEL_MAVERICK, /* FPUTYPE_MAVERICK */
663 ARM_FP_MODEL_VFP /* FPUTYPE_VFP */
670 enum float_abi_type abi_type;
674 /* Available values for -mfloat-abi=. */
676 static const struct float_abi all_float_abis[] =
678 {"soft", ARM_FLOAT_ABI_SOFT},
679 {"softfp", ARM_FLOAT_ABI_SOFTFP},
680 {"hard", ARM_FLOAT_ABI_HARD}
687 enum arm_abi_type abi_type;
691 /* Available values for -mabi=. */
693 static const struct abi_name arm_all_abis[] =
695 {"apcs-gnu", ARM_ABI_APCS},
696 {"atpcs", ARM_ABI_ATPCS},
697 {"aapcs", ARM_ABI_AAPCS},
698 {"iwmmxt", ARM_ABI_IWMMXT},
699 {"aapcs-linux", ARM_ABI_AAPCS_LINUX}
702 /* Supported TLS relocations. */
712 /* Emit an insn that's a simple single-set. Both the operands must be known
715 emit_set_insn (rtx x, rtx y)
717 return emit_insn (gen_rtx_SET (VOIDmode, x, y));
720 /* Return the number of bits set in VALUE. */
722 bit_count (unsigned long value)
724 unsigned long count = 0;
729 value &= value - 1; /* Clear the least-significant set bit. */
735 /* Set up library functions unique to ARM. */
738 arm_init_libfuncs (void)
740 /* There are no special library functions unless we are using the
745 /* The functions below are described in Section 4 of the "Run-Time
746 ABI for the ARM architecture", Version 1.0. */
748 /* Double-precision floating-point arithmetic. Table 2. */
749 set_optab_libfunc (add_optab, DFmode, "__aeabi_dadd");
750 set_optab_libfunc (sdiv_optab, DFmode, "__aeabi_ddiv");
751 set_optab_libfunc (smul_optab, DFmode, "__aeabi_dmul");
752 set_optab_libfunc (neg_optab, DFmode, "__aeabi_dneg");
753 set_optab_libfunc (sub_optab, DFmode, "__aeabi_dsub");
755 /* Double-precision comparisons. Table 3. */
756 set_optab_libfunc (eq_optab, DFmode, "__aeabi_dcmpeq");
757 set_optab_libfunc (ne_optab, DFmode, NULL);
758 set_optab_libfunc (lt_optab, DFmode, "__aeabi_dcmplt");
759 set_optab_libfunc (le_optab, DFmode, "__aeabi_dcmple");
760 set_optab_libfunc (ge_optab, DFmode, "__aeabi_dcmpge");
761 set_optab_libfunc (gt_optab, DFmode, "__aeabi_dcmpgt");
762 set_optab_libfunc (unord_optab, DFmode, "__aeabi_dcmpun");
764 /* Single-precision floating-point arithmetic. Table 4. */
765 set_optab_libfunc (add_optab, SFmode, "__aeabi_fadd");
766 set_optab_libfunc (sdiv_optab, SFmode, "__aeabi_fdiv");
767 set_optab_libfunc (smul_optab, SFmode, "__aeabi_fmul");
768 set_optab_libfunc (neg_optab, SFmode, "__aeabi_fneg");
769 set_optab_libfunc (sub_optab, SFmode, "__aeabi_fsub");
771 /* Single-precision comparisons. Table 5. */
772 set_optab_libfunc (eq_optab, SFmode, "__aeabi_fcmpeq");
773 set_optab_libfunc (ne_optab, SFmode, NULL);
774 set_optab_libfunc (lt_optab, SFmode, "__aeabi_fcmplt");
775 set_optab_libfunc (le_optab, SFmode, "__aeabi_fcmple");
776 set_optab_libfunc (ge_optab, SFmode, "__aeabi_fcmpge");
777 set_optab_libfunc (gt_optab, SFmode, "__aeabi_fcmpgt");
778 set_optab_libfunc (unord_optab, SFmode, "__aeabi_fcmpun");
780 /* Floating-point to integer conversions. Table 6. */
781 set_conv_libfunc (sfix_optab, SImode, DFmode, "__aeabi_d2iz");
782 set_conv_libfunc (ufix_optab, SImode, DFmode, "__aeabi_d2uiz");
783 set_conv_libfunc (sfix_optab, DImode, DFmode, "__aeabi_d2lz");
784 set_conv_libfunc (ufix_optab, DImode, DFmode, "__aeabi_d2ulz");
785 set_conv_libfunc (sfix_optab, SImode, SFmode, "__aeabi_f2iz");
786 set_conv_libfunc (ufix_optab, SImode, SFmode, "__aeabi_f2uiz");
787 set_conv_libfunc (sfix_optab, DImode, SFmode, "__aeabi_f2lz");
788 set_conv_libfunc (ufix_optab, DImode, SFmode, "__aeabi_f2ulz");
790 /* Conversions between floating types. Table 7. */
791 set_conv_libfunc (trunc_optab, SFmode, DFmode, "__aeabi_d2f");
792 set_conv_libfunc (sext_optab, DFmode, SFmode, "__aeabi_f2d");
794 /* Integer to floating-point conversions. Table 8. */
795 set_conv_libfunc (sfloat_optab, DFmode, SImode, "__aeabi_i2d");
796 set_conv_libfunc (ufloat_optab, DFmode, SImode, "__aeabi_ui2d");
797 set_conv_libfunc (sfloat_optab, DFmode, DImode, "__aeabi_l2d");
798 set_conv_libfunc (ufloat_optab, DFmode, DImode, "__aeabi_ul2d");
799 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__aeabi_i2f");
800 set_conv_libfunc (ufloat_optab, SFmode, SImode, "__aeabi_ui2f");
801 set_conv_libfunc (sfloat_optab, SFmode, DImode, "__aeabi_l2f");
802 set_conv_libfunc (ufloat_optab, SFmode, DImode, "__aeabi_ul2f");
804 /* Long long. Table 9. */
805 set_optab_libfunc (smul_optab, DImode, "__aeabi_lmul");
806 set_optab_libfunc (sdivmod_optab, DImode, "__aeabi_ldivmod");
807 set_optab_libfunc (udivmod_optab, DImode, "__aeabi_uldivmod");
808 set_optab_libfunc (ashl_optab, DImode, "__aeabi_llsl");
809 set_optab_libfunc (lshr_optab, DImode, "__aeabi_llsr");
810 set_optab_libfunc (ashr_optab, DImode, "__aeabi_lasr");
811 set_optab_libfunc (cmp_optab, DImode, "__aeabi_lcmp");
812 set_optab_libfunc (ucmp_optab, DImode, "__aeabi_ulcmp");
814 /* Integer (32/32->32) division. \S 4.3.1. */
815 set_optab_libfunc (sdivmod_optab, SImode, "__aeabi_idivmod");
816 set_optab_libfunc (udivmod_optab, SImode, "__aeabi_uidivmod");
818 /* The divmod functions are designed so that they can be used for
819 plain division, even though they return both the quotient and the
820 remainder. The quotient is returned in the usual location (i.e.,
821 r0 for SImode, {r0, r1} for DImode), just as would be expected
822 for an ordinary division routine. Because the AAPCS calling
823 conventions specify that all of { r0, r1, r2, r3 } are
824 callee-saved registers, there is no need to tell the compiler
825 explicitly that those registers are clobbered by these
827 set_optab_libfunc (sdiv_optab, DImode, "__aeabi_ldivmod");
828 set_optab_libfunc (udiv_optab, DImode, "__aeabi_uldivmod");
830 /* For SImode division the ABI provides div-without-mod routines,
832 set_optab_libfunc (sdiv_optab, SImode, "__aeabi_idiv");
833 set_optab_libfunc (udiv_optab, SImode, "__aeabi_uidiv");
835 /* We don't have mod libcalls. Fortunately gcc knows how to use the
836 divmod libcalls instead. */
837 set_optab_libfunc (smod_optab, DImode, NULL);
838 set_optab_libfunc (umod_optab, DImode, NULL);
839 set_optab_libfunc (smod_optab, SImode, NULL);
840 set_optab_libfunc (umod_optab, SImode, NULL);
843 /* Implement TARGET_HANDLE_OPTION. */
846 arm_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
851 arm_select[1].string = arg;
855 arm_select[0].string = arg;
858 case OPT_mhard_float:
859 target_float_abi_name = "hard";
862 case OPT_msoft_float:
863 target_float_abi_name = "soft";
867 arm_select[2].string = arg;
875 /* Fix up any incompatible options that the user has specified.
876 This has now turned into a maze. */
878 arm_override_options (void)
881 enum processor_type target_arch_cpu = arm_none;
883 /* Set up the flags based on the cpu/architecture selected by the user. */
884 for (i = ARRAY_SIZE (arm_select); i--;)
886 struct arm_cpu_select * ptr = arm_select + i;
888 if (ptr->string != NULL && ptr->string[0] != '\0')
890 const struct processors * sel;
892 for (sel = ptr->processors; sel->name != NULL; sel++)
893 if (streq (ptr->string, sel->name))
895 /* Set the architecture define. */
896 if (i != ARM_OPT_SET_TUNE)
897 sprintf (arm_arch_name, "__ARM_ARCH_%s__", sel->arch);
899 /* Determine the processor core for which we should
900 tune code-generation. */
901 if (/* -mcpu= is a sensible default. */
903 /* -mtune= overrides -mcpu= and -march=. */
904 || i == ARM_OPT_SET_TUNE)
905 arm_tune = (enum processor_type) (sel - ptr->processors);
907 /* Remember the CPU associated with this architecture.
908 If no other option is used to set the CPU type,
909 we'll use this to guess the most suitable tuning
911 if (i == ARM_OPT_SET_ARCH)
912 target_arch_cpu = sel->core;
914 if (i != ARM_OPT_SET_TUNE)
916 /* If we have been given an architecture and a processor
917 make sure that they are compatible. We only generate
918 a warning though, and we prefer the CPU over the
920 if (insn_flags != 0 && (insn_flags ^ sel->flags))
921 warning (0, "switch -mcpu=%s conflicts with -march= switch",
924 insn_flags = sel->flags;
930 if (sel->name == NULL)
931 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
935 /* Guess the tuning options from the architecture if necessary. */
936 if (arm_tune == arm_none)
937 arm_tune = target_arch_cpu;
939 /* If the user did not specify a processor, choose one for them. */
942 const struct processors * sel;
944 enum processor_type cpu;
946 cpu = TARGET_CPU_DEFAULT;
949 #ifdef SUBTARGET_CPU_DEFAULT
950 /* Use the subtarget default CPU if none was specified by
952 cpu = SUBTARGET_CPU_DEFAULT;
954 /* Default to ARM6. */
958 sel = &all_cores[cpu];
960 insn_flags = sel->flags;
962 /* Now check to see if the user has specified some command line
963 switch that require certain abilities from the cpu. */
966 if (TARGET_INTERWORK || TARGET_THUMB)
968 sought |= (FL_THUMB | FL_MODE32);
970 /* There are no ARM processors that support both APCS-26 and
971 interworking. Therefore we force FL_MODE26 to be removed
972 from insn_flags here (if it was set), so that the search
973 below will always be able to find a compatible processor. */
974 insn_flags &= ~FL_MODE26;
977 if (sought != 0 && ((sought & insn_flags) != sought))
979 /* Try to locate a CPU type that supports all of the abilities
980 of the default CPU, plus the extra abilities requested by
982 for (sel = all_cores; sel->name != NULL; sel++)
983 if ((sel->flags & sought) == (sought | insn_flags))
986 if (sel->name == NULL)
988 unsigned current_bit_count = 0;
989 const struct processors * best_fit = NULL;
991 /* Ideally we would like to issue an error message here
992 saying that it was not possible to find a CPU compatible
993 with the default CPU, but which also supports the command
994 line options specified by the programmer, and so they
995 ought to use the -mcpu=<name> command line option to
996 override the default CPU type.
998 If we cannot find a cpu that has both the
999 characteristics of the default cpu and the given
1000 command line options we scan the array again looking
1001 for a best match. */
1002 for (sel = all_cores; sel->name != NULL; sel++)
1003 if ((sel->flags & sought) == sought)
1007 count = bit_count (sel->flags & insn_flags);
1009 if (count >= current_bit_count)
1012 current_bit_count = count;
1016 gcc_assert (best_fit);
1020 insn_flags = sel->flags;
1022 sprintf (arm_arch_name, "__ARM_ARCH_%s__", sel->arch);
1023 if (arm_tune == arm_none)
1024 arm_tune = (enum processor_type) (sel - all_cores);
1027 /* The processor for which we should tune should now have been
1029 gcc_assert (arm_tune != arm_none);
1031 tune_flags = all_cores[(int)arm_tune].flags;
1033 targetm.rtx_costs = arm_size_rtx_costs;
1035 targetm.rtx_costs = all_cores[(int)arm_tune].rtx_costs;
1037 /* Make sure that the processor choice does not conflict with any of the
1038 other command line choices. */
1039 if (TARGET_INTERWORK && !(insn_flags & FL_THUMB))
1041 warning (0, "target CPU does not support interworking" );
1042 target_flags &= ~MASK_INTERWORK;
1045 if (TARGET_THUMB && !(insn_flags & FL_THUMB))
1047 warning (0, "target CPU does not support THUMB instructions");
1048 target_flags &= ~MASK_THUMB;
1051 if (TARGET_APCS_FRAME && TARGET_THUMB)
1053 /* warning (0, "ignoring -mapcs-frame because -mthumb was used"); */
1054 target_flags &= ~MASK_APCS_FRAME;
1057 /* Callee super interworking implies thumb interworking. Adding
1058 this to the flags here simplifies the logic elsewhere. */
1059 if (TARGET_THUMB && TARGET_CALLEE_INTERWORKING)
1060 target_flags |= MASK_INTERWORK;
1062 /* TARGET_BACKTRACE calls leaf_function_p, which causes a crash if done
1063 from here where no function is being compiled currently. */
1064 if ((TARGET_TPCS_FRAME || TARGET_TPCS_LEAF_FRAME) && TARGET_ARM)
1065 warning (0, "enabling backtrace support is only meaningful when compiling for the Thumb");
1067 if (TARGET_ARM && TARGET_CALLEE_INTERWORKING)
1068 warning (0, "enabling callee interworking support is only meaningful when compiling for the Thumb");
1070 if (TARGET_ARM && TARGET_CALLER_INTERWORKING)
1071 warning (0, "enabling caller interworking support is only meaningful when compiling for the Thumb");
1073 if (TARGET_APCS_STACK && !TARGET_APCS_FRAME)
1075 warning (0, "-mapcs-stack-check incompatible with -mno-apcs-frame");
1076 target_flags |= MASK_APCS_FRAME;
1079 if (TARGET_POKE_FUNCTION_NAME)
1080 target_flags |= MASK_APCS_FRAME;
1082 if (TARGET_APCS_REENT && flag_pic)
1083 error ("-fpic and -mapcs-reent are incompatible");
1085 if (TARGET_APCS_REENT)
1086 warning (0, "APCS reentrant code not supported. Ignored");
1088 /* If this target is normally configured to use APCS frames, warn if they
1089 are turned off and debugging is turned on. */
1091 && write_symbols != NO_DEBUG
1092 && !TARGET_APCS_FRAME
1093 && (TARGET_DEFAULT & MASK_APCS_FRAME))
1094 warning (0, "-g with -mno-apcs-frame may not give sensible debugging");
1096 /* If stack checking is disabled, we can use r10 as the PIC register,
1097 which keeps r9 available. */
1098 if (flag_pic && TARGET_SINGLE_PIC_BASE)
1099 arm_pic_register = TARGET_APCS_STACK ? 9 : 10;
1101 if (TARGET_APCS_FLOAT)
1102 warning (0, "passing floating point arguments in fp regs not yet supported");
1104 /* Initialize boolean versions of the flags, for use in the arm.md file. */
1105 arm_arch3m = (insn_flags & FL_ARCH3M) != 0;
1106 arm_arch4 = (insn_flags & FL_ARCH4) != 0;
1107 arm_arch4t = arm_arch4 & ((insn_flags & FL_THUMB) != 0);
1108 arm_arch5 = (insn_flags & FL_ARCH5) != 0;
1109 arm_arch5e = (insn_flags & FL_ARCH5E) != 0;
1110 arm_arch6 = (insn_flags & FL_ARCH6) != 0;
1111 arm_arch6k = (insn_flags & FL_ARCH6K) != 0;
1112 arm_arch_xscale = (insn_flags & FL_XSCALE) != 0;
1113 arm_arch_cirrus = (insn_flags & FL_CIRRUS) != 0;
1115 arm_ld_sched = (tune_flags & FL_LDSCHED) != 0;
1116 arm_tune_strongarm = (tune_flags & FL_STRONG) != 0;
1117 thumb_code = (TARGET_ARM == 0);
1118 arm_tune_wbuf = (tune_flags & FL_WBUF) != 0;
1119 arm_tune_xscale = (tune_flags & FL_XSCALE) != 0;
1120 arm_arch_iwmmxt = (insn_flags & FL_IWMMXT) != 0;
1122 /* V5 code we generate is completely interworking capable, so we turn off
1123 TARGET_INTERWORK here to avoid many tests later on. */
1125 /* XXX However, we must pass the right pre-processor defines to CPP
1126 or GLD can get confused. This is a hack. */
1127 if (TARGET_INTERWORK)
1128 arm_cpp_interwork = 1;
1131 target_flags &= ~MASK_INTERWORK;
1133 if (target_abi_name)
1135 for (i = 0; i < ARRAY_SIZE (arm_all_abis); i++)
1137 if (streq (arm_all_abis[i].name, target_abi_name))
1139 arm_abi = arm_all_abis[i].abi_type;
1143 if (i == ARRAY_SIZE (arm_all_abis))
1144 error ("invalid ABI option: -mabi=%s", target_abi_name);
1147 arm_abi = ARM_DEFAULT_ABI;
1149 if (TARGET_IWMMXT && !ARM_DOUBLEWORD_ALIGN)
1150 error ("iwmmxt requires an AAPCS compatible ABI for proper operation");
1152 if (TARGET_IWMMXT_ABI && !TARGET_IWMMXT)
1153 error ("iwmmxt abi requires an iwmmxt capable cpu");
1155 arm_fp_model = ARM_FP_MODEL_UNKNOWN;
1156 if (target_fpu_name == NULL && target_fpe_name != NULL)
1158 if (streq (target_fpe_name, "2"))
1159 target_fpu_name = "fpe2";
1160 else if (streq (target_fpe_name, "3"))
1161 target_fpu_name = "fpe3";
1163 error ("invalid floating point emulation option: -mfpe=%s",
1166 if (target_fpu_name != NULL)
1168 /* The user specified a FPU. */
1169 for (i = 0; i < ARRAY_SIZE (all_fpus); i++)
1171 if (streq (all_fpus[i].name, target_fpu_name))
1173 arm_fpu_arch = all_fpus[i].fpu;
1174 arm_fpu_tune = arm_fpu_arch;
1175 arm_fp_model = fp_model_for_fpu[arm_fpu_arch];
1179 if (arm_fp_model == ARM_FP_MODEL_UNKNOWN)
1180 error ("invalid floating point option: -mfpu=%s", target_fpu_name);
1184 #ifdef FPUTYPE_DEFAULT
1185 /* Use the default if it is specified for this platform. */
1186 arm_fpu_arch = FPUTYPE_DEFAULT;
1187 arm_fpu_tune = FPUTYPE_DEFAULT;
1189 /* Pick one based on CPU type. */
1190 /* ??? Some targets assume FPA is the default.
1191 if ((insn_flags & FL_VFP) != 0)
1192 arm_fpu_arch = FPUTYPE_VFP;
1195 if (arm_arch_cirrus)
1196 arm_fpu_arch = FPUTYPE_MAVERICK;
1198 arm_fpu_arch = FPUTYPE_FPA_EMU2;
1200 if (tune_flags & FL_CO_PROC && arm_fpu_arch == FPUTYPE_FPA_EMU2)
1201 arm_fpu_tune = FPUTYPE_FPA;
1203 arm_fpu_tune = arm_fpu_arch;
1204 arm_fp_model = fp_model_for_fpu[arm_fpu_arch];
1205 gcc_assert (arm_fp_model != ARM_FP_MODEL_UNKNOWN);
1208 if (target_float_abi_name != NULL)
1210 /* The user specified a FP ABI. */
1211 for (i = 0; i < ARRAY_SIZE (all_float_abis); i++)
1213 if (streq (all_float_abis[i].name, target_float_abi_name))
1215 arm_float_abi = all_float_abis[i].abi_type;
1219 if (i == ARRAY_SIZE (all_float_abis))
1220 error ("invalid floating point abi: -mfloat-abi=%s",
1221 target_float_abi_name);
1224 arm_float_abi = TARGET_DEFAULT_FLOAT_ABI;
1226 if (arm_float_abi == ARM_FLOAT_ABI_HARD && TARGET_VFP)
1227 sorry ("-mfloat-abi=hard and VFP");
1229 /* FPA and iWMMXt are incompatible because the insn encodings overlap.
1230 VFP and iWMMXt can theoretically coexist, but it's unlikely such silicon
1231 will ever exist. GCC makes no attempt to support this combination. */
1232 if (TARGET_IWMMXT && !TARGET_SOFT_FLOAT)
1233 sorry ("iWMMXt and hardware floating point");
1235 /* If soft-float is specified then don't use FPU. */
1236 if (TARGET_SOFT_FLOAT)
1237 arm_fpu_arch = FPUTYPE_NONE;
1239 /* For arm2/3 there is no need to do any scheduling if there is only
1240 a floating point emulator, or we are doing software floating-point. */
1241 if ((TARGET_SOFT_FLOAT
1242 || arm_fpu_tune == FPUTYPE_FPA_EMU2
1243 || arm_fpu_tune == FPUTYPE_FPA_EMU3)
1244 && (tune_flags & FL_MODE32) == 0)
1245 flag_schedule_insns = flag_schedule_insns_after_reload = 0;
1247 if (target_thread_switch)
1249 if (strcmp (target_thread_switch, "soft") == 0)
1250 target_thread_pointer = TP_SOFT;
1251 else if (strcmp (target_thread_switch, "auto") == 0)
1252 target_thread_pointer = TP_AUTO;
1253 else if (strcmp (target_thread_switch, "cp15") == 0)
1254 target_thread_pointer = TP_CP15;
1256 error ("invalid thread pointer option: -mtp=%s", target_thread_switch);
1259 /* Use the cp15 method if it is available. */
1260 if (target_thread_pointer == TP_AUTO)
1262 if (arm_arch6k && !TARGET_THUMB)
1263 target_thread_pointer = TP_CP15;
1265 target_thread_pointer = TP_SOFT;
1268 if (TARGET_HARD_TP && TARGET_THUMB)
1269 error ("can not use -mtp=cp15 with -mthumb");
1271 /* Override the default structure alignment for AAPCS ABI. */
1272 if (TARGET_AAPCS_BASED)
1273 arm_structure_size_boundary = 8;
1275 if (structure_size_string != NULL)
1277 int size = strtol (structure_size_string, NULL, 0);
1279 if (size == 8 || size == 32
1280 || (ARM_DOUBLEWORD_ALIGN && size == 64))
1281 arm_structure_size_boundary = size;
1283 warning (0, "structure size boundary can only be set to %s",
1284 ARM_DOUBLEWORD_ALIGN ? "8, 32 or 64": "8 or 32");
1287 if (arm_pic_register_string != NULL)
1289 int pic_register = decode_reg_name (arm_pic_register_string);
1292 warning (0, "-mpic-register= is useless without -fpic");
1294 /* Prevent the user from choosing an obviously stupid PIC register. */
1295 else if (pic_register < 0 || call_used_regs[pic_register]
1296 || pic_register == HARD_FRAME_POINTER_REGNUM
1297 || pic_register == STACK_POINTER_REGNUM
1298 || pic_register >= PC_REGNUM)
1299 error ("unable to use '%s' for PIC register", arm_pic_register_string);
1301 arm_pic_register = pic_register;
1304 if (TARGET_THUMB && flag_schedule_insns)
1306 /* Don't warn since it's on by default in -O2. */
1307 flag_schedule_insns = 0;
1312 arm_constant_limit = 1;
1314 /* If optimizing for size, bump the number of instructions that we
1315 are prepared to conditionally execute (even on a StrongARM). */
1316 max_insns_skipped = 6;
1320 /* For processors with load scheduling, it never costs more than
1321 2 cycles to load a constant, and the load scheduler may well
1322 reduce that to 1. */
1324 arm_constant_limit = 1;
1326 /* On XScale the longer latency of a load makes it more difficult
1327 to achieve a good schedule, so it's faster to synthesize
1328 constants that can be done in two insns. */
1329 if (arm_tune_xscale)
1330 arm_constant_limit = 2;
1332 /* StrongARM has early execution of branches, so a sequence
1333 that is worth skipping is shorter. */
1334 if (arm_tune_strongarm)
1335 max_insns_skipped = 3;
1338 /* Register global variables with the garbage collector. */
1339 arm_add_gc_roots ();
1343 arm_add_gc_roots (void)
1345 gcc_obstack_init(&minipool_obstack);
1346 minipool_startobj = (char *) obstack_alloc (&minipool_obstack, 0);
1349 /* A table of known ARM exception types.
1350 For use with the interrupt function attribute. */
1354 const char *const arg;
1355 const unsigned long return_value;
1359 static const isr_attribute_arg isr_attribute_args [] =
1361 { "IRQ", ARM_FT_ISR },
1362 { "irq", ARM_FT_ISR },
1363 { "FIQ", ARM_FT_FIQ },
1364 { "fiq", ARM_FT_FIQ },
1365 { "ABORT", ARM_FT_ISR },
1366 { "abort", ARM_FT_ISR },
1367 { "ABORT", ARM_FT_ISR },
1368 { "abort", ARM_FT_ISR },
1369 { "UNDEF", ARM_FT_EXCEPTION },
1370 { "undef", ARM_FT_EXCEPTION },
1371 { "SWI", ARM_FT_EXCEPTION },
1372 { "swi", ARM_FT_EXCEPTION },
1373 { NULL, ARM_FT_NORMAL }
1376 /* Returns the (interrupt) function type of the current
1377 function, or ARM_FT_UNKNOWN if the type cannot be determined. */
1379 static unsigned long
1380 arm_isr_value (tree argument)
1382 const isr_attribute_arg * ptr;
1385 /* No argument - default to IRQ. */
1386 if (argument == NULL_TREE)
1389 /* Get the value of the argument. */
1390 if (TREE_VALUE (argument) == NULL_TREE
1391 || TREE_CODE (TREE_VALUE (argument)) != STRING_CST)
1392 return ARM_FT_UNKNOWN;
1394 arg = TREE_STRING_POINTER (TREE_VALUE (argument));
1396 /* Check it against the list of known arguments. */
1397 for (ptr = isr_attribute_args; ptr->arg != NULL; ptr++)
1398 if (streq (arg, ptr->arg))
1399 return ptr->return_value;
1401 /* An unrecognized interrupt type. */
1402 return ARM_FT_UNKNOWN;
1405 /* Computes the type of the current function. */
1407 static unsigned long
1408 arm_compute_func_type (void)
1410 unsigned long type = ARM_FT_UNKNOWN;
1414 gcc_assert (TREE_CODE (current_function_decl) == FUNCTION_DECL);
1416 /* Decide if the current function is volatile. Such functions
1417 never return, and many memory cycles can be saved by not storing
1418 register values that will never be needed again. This optimization
1419 was added to speed up context switching in a kernel application. */
1421 && (TREE_NOTHROW (current_function_decl)
1422 || !(flag_unwind_tables
1423 || (flag_exceptions && !USING_SJLJ_EXCEPTIONS)))
1424 && TREE_THIS_VOLATILE (current_function_decl))
1425 type |= ARM_FT_VOLATILE;
1427 if (cfun->static_chain_decl != NULL)
1428 type |= ARM_FT_NESTED;
1430 attr = DECL_ATTRIBUTES (current_function_decl);
1432 a = lookup_attribute ("naked", attr);
1434 type |= ARM_FT_NAKED;
1436 a = lookup_attribute ("isr", attr);
1438 a = lookup_attribute ("interrupt", attr);
1441 type |= TARGET_INTERWORK ? ARM_FT_INTERWORKED : ARM_FT_NORMAL;
1443 type |= arm_isr_value (TREE_VALUE (a));
1448 /* Returns the type of the current function. */
1451 arm_current_func_type (void)
1453 if (ARM_FUNC_TYPE (cfun->machine->func_type) == ARM_FT_UNKNOWN)
1454 cfun->machine->func_type = arm_compute_func_type ();
1456 return cfun->machine->func_type;
1459 /* Return 1 if it is possible to return using a single instruction.
1460 If SIBLING is non-null, this is a test for a return before a sibling
1461 call. SIBLING is the call insn, so we can examine its register usage. */
1464 use_return_insn (int iscond, rtx sibling)
1467 unsigned int func_type;
1468 unsigned long saved_int_regs;
1469 unsigned HOST_WIDE_INT stack_adjust;
1470 arm_stack_offsets *offsets;
1472 /* Never use a return instruction before reload has run. */
1473 if (!reload_completed)
1476 func_type = arm_current_func_type ();
1478 /* Naked functions and volatile functions need special
1480 if (func_type & (ARM_FT_VOLATILE | ARM_FT_NAKED))
1483 /* So do interrupt functions that use the frame pointer. */
1484 if (IS_INTERRUPT (func_type) && frame_pointer_needed)
1487 offsets = arm_get_frame_offsets ();
1488 stack_adjust = offsets->outgoing_args - offsets->saved_regs;
1490 /* As do variadic functions. */
1491 if (current_function_pretend_args_size
1492 || cfun->machine->uses_anonymous_args
1493 /* Or if the function calls __builtin_eh_return () */
1494 || current_function_calls_eh_return
1495 /* Or if the function calls alloca */
1496 || current_function_calls_alloca
1497 /* Or if there is a stack adjustment. However, if the stack pointer
1498 is saved on the stack, we can use a pre-incrementing stack load. */
1499 || !(stack_adjust == 0 || (frame_pointer_needed && stack_adjust == 4)))
1502 saved_int_regs = arm_compute_save_reg_mask ();
1504 /* Unfortunately, the insn
1506 ldmib sp, {..., sp, ...}
1508 triggers a bug on most SA-110 based devices, such that the stack
1509 pointer won't be correctly restored if the instruction takes a
1510 page fault. We work around this problem by popping r3 along with
1511 the other registers, since that is never slower than executing
1512 another instruction.
1514 We test for !arm_arch5 here, because code for any architecture
1515 less than this could potentially be run on one of the buggy
1517 if (stack_adjust == 4 && !arm_arch5)
1519 /* Validate that r3 is a call-clobbered register (always true in
1520 the default abi) ... */
1521 if (!call_used_regs[3])
1524 /* ... that it isn't being used for a return value ... */
1525 if (arm_size_return_regs () >= (4 * UNITS_PER_WORD))
1528 /* ... or for a tail-call argument ... */
1531 gcc_assert (GET_CODE (sibling) == CALL_INSN);
1533 if (find_regno_fusage (sibling, USE, 3))
1537 /* ... and that there are no call-saved registers in r0-r2
1538 (always true in the default ABI). */
1539 if (saved_int_regs & 0x7)
1543 /* Can't be done if interworking with Thumb, and any registers have been
1545 if (TARGET_INTERWORK && saved_int_regs != 0)
1548 /* On StrongARM, conditional returns are expensive if they aren't
1549 taken and multiple registers have been stacked. */
1550 if (iscond && arm_tune_strongarm)
1552 /* Conditional return when just the LR is stored is a simple
1553 conditional-load instruction, that's not expensive. */
1554 if (saved_int_regs != 0 && saved_int_regs != (1 << LR_REGNUM))
1558 && arm_pic_register != INVALID_REGNUM
1559 && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
1563 /* If there are saved registers but the LR isn't saved, then we need
1564 two instructions for the return. */
1565 if (saved_int_regs && !(saved_int_regs & (1 << LR_REGNUM)))
1568 /* Can't be done if any of the FPA regs are pushed,
1569 since this also requires an insn. */
1570 if (TARGET_HARD_FLOAT && TARGET_FPA)
1571 for (regno = FIRST_FPA_REGNUM; regno <= LAST_FPA_REGNUM; regno++)
1572 if (regs_ever_live[regno] && !call_used_regs[regno])
1575 /* Likewise VFP regs. */
1576 if (TARGET_HARD_FLOAT && TARGET_VFP)
1577 for (regno = FIRST_VFP_REGNUM; regno <= LAST_VFP_REGNUM; regno++)
1578 if (regs_ever_live[regno] && !call_used_regs[regno])
1581 if (TARGET_REALLY_IWMMXT)
1582 for (regno = FIRST_IWMMXT_REGNUM; regno <= LAST_IWMMXT_REGNUM; regno++)
1583 if (regs_ever_live[regno] && ! call_used_regs [regno])
1589 /* Return TRUE if int I is a valid immediate ARM constant. */
1592 const_ok_for_arm (HOST_WIDE_INT i)
1596 /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must
1597 be all zero, or all one. */
1598 if ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff) != 0
1599 && ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff)
1600 != ((~(unsigned HOST_WIDE_INT) 0)
1601 & ~(unsigned HOST_WIDE_INT) 0xffffffff)))
1604 i &= (unsigned HOST_WIDE_INT) 0xffffffff;
1606 /* Fast return for 0 and small values. We must do this for zero, since
1607 the code below can't handle that one case. */
1608 if ((i & ~(unsigned HOST_WIDE_INT) 0xff) == 0)
1611 /* Get the number of trailing zeros, rounded down to the nearest even
1613 lowbit = (ffs ((int) i) - 1) & ~1;
1615 if ((i & ~(((unsigned HOST_WIDE_INT) 0xff) << lowbit)) == 0)
1617 else if (lowbit <= 4
1618 && ((i & ~0xc000003f) == 0
1619 || (i & ~0xf000000f) == 0
1620 || (i & ~0xfc000003) == 0))
1626 /* Return true if I is a valid constant for the operation CODE. */
1628 const_ok_for_op (HOST_WIDE_INT i, enum rtx_code code)
1630 if (const_ok_for_arm (i))
1636 return const_ok_for_arm (ARM_SIGN_EXTEND (-i));
1638 case MINUS: /* Should only occur with (MINUS I reg) => rsb */
1644 return const_ok_for_arm (ARM_SIGN_EXTEND (~i));
1651 /* Emit a sequence of insns to handle a large constant.
1652 CODE is the code of the operation required, it can be any of SET, PLUS,
1653 IOR, AND, XOR, MINUS;
1654 MODE is the mode in which the operation is being performed;
1655 VAL is the integer to operate on;
1656 SOURCE is the other operand (a register, or a null-pointer for SET);
1657 SUBTARGETS means it is safe to create scratch registers if that will
1658 either produce a simpler sequence, or we will want to cse the values.
1659 Return value is the number of insns emitted. */
1662 arm_split_constant (enum rtx_code code, enum machine_mode mode, rtx insn,
1663 HOST_WIDE_INT val, rtx target, rtx source, int subtargets)
1667 if (insn && GET_CODE (PATTERN (insn)) == COND_EXEC)
1668 cond = COND_EXEC_TEST (PATTERN (insn));
1672 if (subtargets || code == SET
1673 || (GET_CODE (target) == REG && GET_CODE (source) == REG
1674 && REGNO (target) != REGNO (source)))
1676 /* After arm_reorg has been called, we can't fix up expensive
1677 constants by pushing them into memory so we must synthesize
1678 them in-line, regardless of the cost. This is only likely to
1679 be more costly on chips that have load delay slots and we are
1680 compiling without running the scheduler (so no splitting
1681 occurred before the final instruction emission).
1683 Ref: gcc -O1 -mcpu=strongarm gcc.c-torture/compile/980506-2.c
1685 if (!after_arm_reorg
1687 && (arm_gen_constant (code, mode, NULL_RTX, val, target, source,
1689 > arm_constant_limit + (code != SET)))
1693 /* Currently SET is the only monadic value for CODE, all
1694 the rest are diadic. */
1695 emit_set_insn (target, GEN_INT (val));
1700 rtx temp = subtargets ? gen_reg_rtx (mode) : target;
1702 emit_set_insn (temp, GEN_INT (val));
1703 /* For MINUS, the value is subtracted from, since we never
1704 have subtraction of a constant. */
1706 emit_set_insn (target, gen_rtx_MINUS (mode, temp, source));
1708 emit_set_insn (target,
1709 gen_rtx_fmt_ee (code, mode, source, temp));
1715 return arm_gen_constant (code, mode, cond, val, target, source, subtargets,
1720 count_insns_for_constant (HOST_WIDE_INT remainder, int i)
1722 HOST_WIDE_INT temp1;
1730 if (remainder & (3 << (i - 2)))
1735 temp1 = remainder & ((0x0ff << end)
1736 | ((i < end) ? (0xff >> (32 - end)) : 0));
1737 remainder &= ~temp1;
1742 } while (remainder);
1746 /* Emit an instruction with the indicated PATTERN. If COND is
1747 non-NULL, conditionalize the execution of the instruction on COND
1751 emit_constant_insn (rtx cond, rtx pattern)
1754 pattern = gen_rtx_COND_EXEC (VOIDmode, copy_rtx (cond), pattern);
1755 emit_insn (pattern);
1758 /* As above, but extra parameter GENERATE which, if clear, suppresses
1762 arm_gen_constant (enum rtx_code code, enum machine_mode mode, rtx cond,
1763 HOST_WIDE_INT val, rtx target, rtx source, int subtargets,
1768 int can_negate_initial = 0;
1771 int num_bits_set = 0;
1772 int set_sign_bit_copies = 0;
1773 int clear_sign_bit_copies = 0;
1774 int clear_zero_bit_copies = 0;
1775 int set_zero_bit_copies = 0;
1777 unsigned HOST_WIDE_INT temp1, temp2;
1778 unsigned HOST_WIDE_INT remainder = val & 0xffffffff;
1780 /* Find out which operations are safe for a given CODE. Also do a quick
1781 check for degenerate cases; these can occur when DImode operations
1793 can_negate_initial = 1;
1797 if (remainder == 0xffffffff)
1800 emit_constant_insn (cond,
1801 gen_rtx_SET (VOIDmode, target,
1802 GEN_INT (ARM_SIGN_EXTEND (val))));
1807 if (reload_completed && rtx_equal_p (target, source))
1810 emit_constant_insn (cond,
1811 gen_rtx_SET (VOIDmode, target, source));
1820 emit_constant_insn (cond,
1821 gen_rtx_SET (VOIDmode, target, const0_rtx));
1824 if (remainder == 0xffffffff)
1826 if (reload_completed && rtx_equal_p (target, source))
1829 emit_constant_insn (cond,
1830 gen_rtx_SET (VOIDmode, target, source));
1839 if (reload_completed && rtx_equal_p (target, source))
1842 emit_constant_insn (cond,
1843 gen_rtx_SET (VOIDmode, target, source));
1847 /* We don't know how to handle other cases yet. */
1848 gcc_assert (remainder == 0xffffffff);
1851 emit_constant_insn (cond,
1852 gen_rtx_SET (VOIDmode, target,
1853 gen_rtx_NOT (mode, source)));
1857 /* We treat MINUS as (val - source), since (source - val) is always
1858 passed as (source + (-val)). */
1862 emit_constant_insn (cond,
1863 gen_rtx_SET (VOIDmode, target,
1864 gen_rtx_NEG (mode, source)));
1867 if (const_ok_for_arm (val))
1870 emit_constant_insn (cond,
1871 gen_rtx_SET (VOIDmode, target,
1872 gen_rtx_MINUS (mode, GEN_INT (val),
1884 /* If we can do it in one insn get out quickly. */
1885 if (const_ok_for_arm (val)
1886 || (can_negate_initial && const_ok_for_arm (-val))
1887 || (can_invert && const_ok_for_arm (~val)))
1890 emit_constant_insn (cond,
1891 gen_rtx_SET (VOIDmode, target,
1893 ? gen_rtx_fmt_ee (code, mode, source,
1899 /* Calculate a few attributes that may be useful for specific
1901 for (i = 31; i >= 0; i--)
1903 if ((remainder & (1 << i)) == 0)
1904 clear_sign_bit_copies++;
1909 for (i = 31; i >= 0; i--)
1911 if ((remainder & (1 << i)) != 0)
1912 set_sign_bit_copies++;
1917 for (i = 0; i <= 31; i++)
1919 if ((remainder & (1 << i)) == 0)
1920 clear_zero_bit_copies++;
1925 for (i = 0; i <= 31; i++)
1927 if ((remainder & (1 << i)) != 0)
1928 set_zero_bit_copies++;
1936 /* See if we can do this by sign_extending a constant that is known
1937 to be negative. This is a good, way of doing it, since the shift
1938 may well merge into a subsequent insn. */
1939 if (set_sign_bit_copies > 1)
1941 if (const_ok_for_arm
1942 (temp1 = ARM_SIGN_EXTEND (remainder
1943 << (set_sign_bit_copies - 1))))
1947 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1948 emit_constant_insn (cond,
1949 gen_rtx_SET (VOIDmode, new_src,
1951 emit_constant_insn (cond,
1952 gen_ashrsi3 (target, new_src,
1953 GEN_INT (set_sign_bit_copies - 1)));
1957 /* For an inverted constant, we will need to set the low bits,
1958 these will be shifted out of harm's way. */
1959 temp1 |= (1 << (set_sign_bit_copies - 1)) - 1;
1960 if (const_ok_for_arm (~temp1))
1964 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1965 emit_constant_insn (cond,
1966 gen_rtx_SET (VOIDmode, new_src,
1968 emit_constant_insn (cond,
1969 gen_ashrsi3 (target, new_src,
1970 GEN_INT (set_sign_bit_copies - 1)));
1976 /* See if we can calculate the value as the difference between two
1977 valid immediates. */
1978 if (clear_sign_bit_copies + clear_zero_bit_copies <= 16)
1980 int topshift = clear_sign_bit_copies & ~1;
1982 temp1 = ARM_SIGN_EXTEND ((remainder + (0x00800000 >> topshift))
1983 & (0xff000000 >> topshift));
1985 /* If temp1 is zero, then that means the 9 most significant
1986 bits of remainder were 1 and we've caused it to overflow.
1987 When topshift is 0 we don't need to do anything since we
1988 can borrow from 'bit 32'. */
1989 if (temp1 == 0 && topshift != 0)
1990 temp1 = 0x80000000 >> (topshift - 1);
1992 temp2 = ARM_SIGN_EXTEND (temp1 - remainder);
1994 if (const_ok_for_arm (temp2))
1998 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1999 emit_constant_insn (cond,
2000 gen_rtx_SET (VOIDmode, new_src,
2002 emit_constant_insn (cond,
2003 gen_addsi3 (target, new_src,
2011 /* See if we can generate this by setting the bottom (or the top)
2012 16 bits, and then shifting these into the other half of the
2013 word. We only look for the simplest cases, to do more would cost
2014 too much. Be careful, however, not to generate this when the
2015 alternative would take fewer insns. */
2016 if (val & 0xffff0000)
2018 temp1 = remainder & 0xffff0000;
2019 temp2 = remainder & 0x0000ffff;
2021 /* Overlaps outside this range are best done using other methods. */
2022 for (i = 9; i < 24; i++)
2024 if ((((temp2 | (temp2 << i)) & 0xffffffff) == remainder)
2025 && !const_ok_for_arm (temp2))
2027 rtx new_src = (subtargets
2028 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
2030 insns = arm_gen_constant (code, mode, cond, temp2, new_src,
2031 source, subtargets, generate);
2039 gen_rtx_ASHIFT (mode, source,
2046 /* Don't duplicate cases already considered. */
2047 for (i = 17; i < 24; i++)
2049 if (((temp1 | (temp1 >> i)) == remainder)
2050 && !const_ok_for_arm (temp1))
2052 rtx new_src = (subtargets
2053 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
2055 insns = arm_gen_constant (code, mode, cond, temp1, new_src,
2056 source, subtargets, generate);
2061 gen_rtx_SET (VOIDmode, target,
2064 gen_rtx_LSHIFTRT (mode, source,
2075 /* If we have IOR or XOR, and the constant can be loaded in a
2076 single instruction, and we can find a temporary to put it in,
2077 then this can be done in two instructions instead of 3-4. */
2079 /* TARGET can't be NULL if SUBTARGETS is 0 */
2080 || (reload_completed && !reg_mentioned_p (target, source)))
2082 if (const_ok_for_arm (ARM_SIGN_EXTEND (~val)))
2086 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
2088 emit_constant_insn (cond,
2089 gen_rtx_SET (VOIDmode, sub,
2091 emit_constant_insn (cond,
2092 gen_rtx_SET (VOIDmode, target,
2093 gen_rtx_fmt_ee (code, mode,
2103 if (set_sign_bit_copies > 8
2104 && (val & (-1 << (32 - set_sign_bit_copies))) == val)
2108 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
2109 rtx shift = GEN_INT (set_sign_bit_copies);
2113 gen_rtx_SET (VOIDmode, sub,
2115 gen_rtx_ASHIFT (mode,
2120 gen_rtx_SET (VOIDmode, target,
2122 gen_rtx_LSHIFTRT (mode, sub,
2128 if (set_zero_bit_copies > 8
2129 && (remainder & ((1 << set_zero_bit_copies) - 1)) == remainder)
2133 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
2134 rtx shift = GEN_INT (set_zero_bit_copies);
2138 gen_rtx_SET (VOIDmode, sub,
2140 gen_rtx_LSHIFTRT (mode,
2145 gen_rtx_SET (VOIDmode, target,
2147 gen_rtx_ASHIFT (mode, sub,
2153 if (const_ok_for_arm (temp1 = ARM_SIGN_EXTEND (~val)))
2157 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
2158 emit_constant_insn (cond,
2159 gen_rtx_SET (VOIDmode, sub,
2160 gen_rtx_NOT (mode, source)));
2163 sub = gen_reg_rtx (mode);
2164 emit_constant_insn (cond,
2165 gen_rtx_SET (VOIDmode, sub,
2166 gen_rtx_AND (mode, source,
2168 emit_constant_insn (cond,
2169 gen_rtx_SET (VOIDmode, target,
2170 gen_rtx_NOT (mode, sub)));
2177 /* See if two shifts will do 2 or more insn's worth of work. */
2178 if (clear_sign_bit_copies >= 16 && clear_sign_bit_copies < 24)
2180 HOST_WIDE_INT shift_mask = ((0xffffffff
2181 << (32 - clear_sign_bit_copies))
2184 if ((remainder | shift_mask) != 0xffffffff)
2188 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
2189 insns = arm_gen_constant (AND, mode, cond,
2190 remainder | shift_mask,
2191 new_src, source, subtargets, 1);
2196 rtx targ = subtargets ? NULL_RTX : target;
2197 insns = arm_gen_constant (AND, mode, cond,
2198 remainder | shift_mask,
2199 targ, source, subtargets, 0);
2205 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
2206 rtx shift = GEN_INT (clear_sign_bit_copies);
2208 emit_insn (gen_ashlsi3 (new_src, source, shift));
2209 emit_insn (gen_lshrsi3 (target, new_src, shift));
2215 if (clear_zero_bit_copies >= 16 && clear_zero_bit_copies < 24)
2217 HOST_WIDE_INT shift_mask = (1 << clear_zero_bit_copies) - 1;
2219 if ((remainder | shift_mask) != 0xffffffff)
2223 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
2225 insns = arm_gen_constant (AND, mode, cond,
2226 remainder | shift_mask,
2227 new_src, source, subtargets, 1);
2232 rtx targ = subtargets ? NULL_RTX : target;
2234 insns = arm_gen_constant (AND, mode, cond,
2235 remainder | shift_mask,
2236 targ, source, subtargets, 0);
2242 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
2243 rtx shift = GEN_INT (clear_zero_bit_copies);
2245 emit_insn (gen_lshrsi3 (new_src, source, shift));
2246 emit_insn (gen_ashlsi3 (target, new_src, shift));
2258 for (i = 0; i < 32; i++)
2259 if (remainder & (1 << i))
2262 if (code == AND || (can_invert && num_bits_set > 16))
2263 remainder = (~remainder) & 0xffffffff;
2264 else if (code == PLUS && num_bits_set > 16)
2265 remainder = (-remainder) & 0xffffffff;
2272 /* Now try and find a way of doing the job in either two or three
2274 We start by looking for the largest block of zeros that are aligned on
2275 a 2-bit boundary, we then fill up the temps, wrapping around to the
2276 top of the word when we drop off the bottom.
2277 In the worst case this code should produce no more than four insns. */
2280 int best_consecutive_zeros = 0;
2282 for (i = 0; i < 32; i += 2)
2284 int consecutive_zeros = 0;
2286 if (!(remainder & (3 << i)))
2288 while ((i < 32) && !(remainder & (3 << i)))
2290 consecutive_zeros += 2;
2293 if (consecutive_zeros > best_consecutive_zeros)
2295 best_consecutive_zeros = consecutive_zeros;
2296 best_start = i - consecutive_zeros;
2302 /* So long as it won't require any more insns to do so, it's
2303 desirable to emit a small constant (in bits 0...9) in the last
2304 insn. This way there is more chance that it can be combined with
2305 a later addressing insn to form a pre-indexed load or store
2306 operation. Consider:
2308 *((volatile int *)0xe0000100) = 1;
2309 *((volatile int *)0xe0000110) = 2;
2311 We want this to wind up as:
2315 str rB, [rA, #0x100]
2317 str rB, [rA, #0x110]
2319 rather than having to synthesize both large constants from scratch.
2321 Therefore, we calculate how many insns would be required to emit
2322 the constant starting from `best_start', and also starting from
2323 zero (i.e. with bit 31 first to be output). If `best_start' doesn't
2324 yield a shorter sequence, we may as well use zero. */
2326 && ((((unsigned HOST_WIDE_INT) 1) << best_start) < remainder)
2327 && (count_insns_for_constant (remainder, 0) <=
2328 count_insns_for_constant (remainder, best_start)))
2331 /* Now start emitting the insns. */
2339 if (remainder & (3 << (i - 2)))
2344 temp1 = remainder & ((0x0ff << end)
2345 | ((i < end) ? (0xff >> (32 - end)) : 0));
2346 remainder &= ~temp1;
2350 rtx new_src, temp1_rtx;
2352 if (code == SET || code == MINUS)
2354 new_src = (subtargets ? gen_reg_rtx (mode) : target);
2355 if (can_invert && code != MINUS)
2360 if (remainder && subtargets)
2361 new_src = gen_reg_rtx (mode);
2366 else if (can_negate)
2370 temp1 = trunc_int_for_mode (temp1, mode);
2371 temp1_rtx = GEN_INT (temp1);
2375 else if (code == MINUS)
2376 temp1_rtx = gen_rtx_MINUS (mode, temp1_rtx, source);
2378 temp1_rtx = gen_rtx_fmt_ee (code, mode, source, temp1_rtx);
2380 emit_constant_insn (cond,
2381 gen_rtx_SET (VOIDmode, new_src,
2391 else if (code == MINUS)
2405 /* Canonicalize a comparison so that we are more likely to recognize it.
2406 This can be done for a few constant compares, where we can make the
2407 immediate value easier to load. */
2410 arm_canonicalize_comparison (enum rtx_code code, enum machine_mode mode,
2413 unsigned HOST_WIDE_INT i = INTVAL (*op1);
2414 unsigned HOST_WIDE_INT maxval;
2415 maxval = (((unsigned HOST_WIDE_INT) 1) << (GET_MODE_BITSIZE(mode) - 1)) - 1;
2426 && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1))))
2428 *op1 = GEN_INT (i + 1);
2429 return code == GT ? GE : LT;
2436 && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1))))
2438 *op1 = GEN_INT (i - 1);
2439 return code == GE ? GT : LE;
2445 if (i != ~((unsigned HOST_WIDE_INT) 0)
2446 && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1))))
2448 *op1 = GEN_INT (i + 1);
2449 return code == GTU ? GEU : LTU;
2456 && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1))))
2458 *op1 = GEN_INT (i - 1);
2459 return code == GEU ? GTU : LEU;
2471 /* Define how to find the value returned by a function. */
2474 arm_function_value(tree type, tree func ATTRIBUTE_UNUSED)
2476 enum machine_mode mode;
2477 int unsignedp ATTRIBUTE_UNUSED;
2478 rtx r ATTRIBUTE_UNUSED;
2480 mode = TYPE_MODE (type);
2481 /* Promote integer types. */
2482 if (INTEGRAL_TYPE_P (type))
2483 PROMOTE_FUNCTION_MODE (mode, unsignedp, type);
2485 /* Promotes small structs returned in a register to full-word size
2486 for big-endian AAPCS. */
2487 if (arm_return_in_msb (type))
2489 HOST_WIDE_INT size = int_size_in_bytes (type);
2490 if (size % UNITS_PER_WORD != 0)
2492 size += UNITS_PER_WORD - size % UNITS_PER_WORD;
2493 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
2497 return LIBCALL_VALUE(mode);
2500 /* Determine the amount of memory needed to store the possible return
2501 registers of an untyped call. */
2503 arm_apply_result_size (void)
2509 if (TARGET_HARD_FLOAT_ABI)
2513 if (TARGET_MAVERICK)
2516 if (TARGET_IWMMXT_ABI)
2523 /* Decide whether a type should be returned in memory (true)
2524 or in a register (false). This is called by the macro
2525 RETURN_IN_MEMORY. */
2527 arm_return_in_memory (tree type)
2531 if (!AGGREGATE_TYPE_P (type) &&
2532 (TREE_CODE (type) != VECTOR_TYPE) &&
2533 !(TARGET_AAPCS_BASED && TREE_CODE (type) == COMPLEX_TYPE))
2534 /* All simple types are returned in registers.
2535 For AAPCS, complex types are treated the same as aggregates. */
2538 size = int_size_in_bytes (type);
2540 if (arm_abi != ARM_ABI_APCS)
2542 /* ATPCS and later return aggregate types in memory only if they are
2543 larger than a word (or are variable size). */
2544 return (size < 0 || size > UNITS_PER_WORD);
2547 /* To maximize backwards compatibility with previous versions of gcc,
2548 return vectors up to 4 words in registers. */
2549 if (TREE_CODE (type) == VECTOR_TYPE)
2550 return (size < 0 || size > (4 * UNITS_PER_WORD));
2552 /* For the arm-wince targets we choose to be compatible with Microsoft's
2553 ARM and Thumb compilers, which always return aggregates in memory. */
2555 /* All structures/unions bigger than one word are returned in memory.
2556 Also catch the case where int_size_in_bytes returns -1. In this case
2557 the aggregate is either huge or of variable size, and in either case
2558 we will want to return it via memory and not in a register. */
2559 if (size < 0 || size > UNITS_PER_WORD)
2562 if (TREE_CODE (type) == RECORD_TYPE)
2566 /* For a struct the APCS says that we only return in a register
2567 if the type is 'integer like' and every addressable element
2568 has an offset of zero. For practical purposes this means
2569 that the structure can have at most one non bit-field element
2570 and that this element must be the first one in the structure. */
2572 /* Find the first field, ignoring non FIELD_DECL things which will
2573 have been created by C++. */
2574 for (field = TYPE_FIELDS (type);
2575 field && TREE_CODE (field) != FIELD_DECL;
2576 field = TREE_CHAIN (field))
2580 return 0; /* An empty structure. Allowed by an extension to ANSI C. */
2582 /* Check that the first field is valid for returning in a register. */
2584 /* ... Floats are not allowed */
2585 if (FLOAT_TYPE_P (TREE_TYPE (field)))
2588 /* ... Aggregates that are not themselves valid for returning in
2589 a register are not allowed. */
2590 if (RETURN_IN_MEMORY (TREE_TYPE (field)))
2593 /* Now check the remaining fields, if any. Only bitfields are allowed,
2594 since they are not addressable. */
2595 for (field = TREE_CHAIN (field);
2597 field = TREE_CHAIN (field))
2599 if (TREE_CODE (field) != FIELD_DECL)
2602 if (!DECL_BIT_FIELD_TYPE (field))
2609 if (TREE_CODE (type) == UNION_TYPE)
2613 /* Unions can be returned in registers if every element is
2614 integral, or can be returned in an integer register. */
2615 for (field = TYPE_FIELDS (type);
2617 field = TREE_CHAIN (field))
2619 if (TREE_CODE (field) != FIELD_DECL)
2622 if (FLOAT_TYPE_P (TREE_TYPE (field)))
2625 if (RETURN_IN_MEMORY (TREE_TYPE (field)))
2631 #endif /* not ARM_WINCE */
2633 /* Return all other types in memory. */
2637 /* Indicate whether or not words of a double are in big-endian order. */
2640 arm_float_words_big_endian (void)
2642 if (TARGET_MAVERICK)
2645 /* For FPA, float words are always big-endian. For VFP, floats words
2646 follow the memory system mode. */
2654 return (TARGET_BIG_END ? 1 : 0);
2659 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2660 for a call to a function whose data type is FNTYPE.
2661 For a library call, FNTYPE is NULL. */
2663 arm_init_cumulative_args (CUMULATIVE_ARGS *pcum, tree fntype,
2664 rtx libname ATTRIBUTE_UNUSED,
2665 tree fndecl ATTRIBUTE_UNUSED)
2667 /* On the ARM, the offset starts at 0. */
2669 pcum->iwmmxt_nregs = 0;
2670 pcum->can_split = true;
2672 pcum->call_cookie = CALL_NORMAL;
2674 if (TARGET_LONG_CALLS)
2675 pcum->call_cookie = CALL_LONG;
2677 /* Check for long call/short call attributes. The attributes
2678 override any command line option. */
2681 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (fntype)))
2682 pcum->call_cookie = CALL_SHORT;
2683 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (fntype)))
2684 pcum->call_cookie = CALL_LONG;
2687 /* Varargs vectors are treated the same as long long.
2688 named_count avoids having to change the way arm handles 'named' */
2689 pcum->named_count = 0;
2692 if (TARGET_REALLY_IWMMXT && fntype)
2696 for (fn_arg = TYPE_ARG_TYPES (fntype);
2698 fn_arg = TREE_CHAIN (fn_arg))
2699 pcum->named_count += 1;
2701 if (! pcum->named_count)
2702 pcum->named_count = INT_MAX;
2707 /* Return true if mode/type need doubleword alignment. */
2709 arm_needs_doubleword_align (enum machine_mode mode, tree type)
2711 return (GET_MODE_ALIGNMENT (mode) > PARM_BOUNDARY
2712 || (type && TYPE_ALIGN (type) > PARM_BOUNDARY));
2716 /* Determine where to put an argument to a function.
2717 Value is zero to push the argument on the stack,
2718 or a hard register in which to store the argument.
2720 MODE is the argument's machine mode.
2721 TYPE is the data type of the argument (as a tree).
2722 This is null for libcalls where that information may
2724 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2725 the preceding args and about the function being called.
2726 NAMED is nonzero if this argument is a named parameter
2727 (otherwise it is an extra parameter matching an ellipsis). */
2730 arm_function_arg (CUMULATIVE_ARGS *pcum, enum machine_mode mode,
2731 tree type, int named)
2735 /* Varargs vectors are treated the same as long long.
2736 named_count avoids having to change the way arm handles 'named' */
2737 if (TARGET_IWMMXT_ABI
2738 && arm_vector_mode_supported_p (mode)
2739 && pcum->named_count > pcum->nargs + 1)
2741 if (pcum->iwmmxt_nregs <= 9)
2742 return gen_rtx_REG (mode, pcum->iwmmxt_nregs + FIRST_IWMMXT_REGNUM);
2745 pcum->can_split = false;
2750 /* Put doubleword aligned quantities in even register pairs. */
2752 && ARM_DOUBLEWORD_ALIGN
2753 && arm_needs_doubleword_align (mode, type))
2756 if (mode == VOIDmode)
2757 /* Compute operand 2 of the call insn. */
2758 return GEN_INT (pcum->call_cookie);
2760 /* Only allow splitting an arg between regs and memory if all preceding
2761 args were allocated to regs. For args passed by reference we only count
2762 the reference pointer. */
2763 if (pcum->can_split)
2766 nregs = ARM_NUM_REGS2 (mode, type);
2768 if (!named || pcum->nregs + nregs > NUM_ARG_REGS)
2771 return gen_rtx_REG (mode, pcum->nregs);
2775 arm_arg_partial_bytes (CUMULATIVE_ARGS *pcum, enum machine_mode mode,
2776 tree type, bool named ATTRIBUTE_UNUSED)
2778 int nregs = pcum->nregs;
2780 if (arm_vector_mode_supported_p (mode))
2783 if (NUM_ARG_REGS > nregs
2784 && (NUM_ARG_REGS < nregs + ARM_NUM_REGS2 (mode, type))
2786 return (NUM_ARG_REGS - nregs) * UNITS_PER_WORD;
2791 /* Variable sized types are passed by reference. This is a GCC
2792 extension to the ARM ABI. */
2795 arm_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
2796 enum machine_mode mode ATTRIBUTE_UNUSED,
2797 tree type, bool named ATTRIBUTE_UNUSED)
2799 return type && TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST;
2802 /* Encode the current state of the #pragma [no_]long_calls. */
2805 OFF, /* No #pragma [no_]long_calls is in effect. */
2806 LONG, /* #pragma long_calls is in effect. */
2807 SHORT /* #pragma no_long_calls is in effect. */
2810 static arm_pragma_enum arm_pragma_long_calls = OFF;
2813 arm_pr_long_calls (struct cpp_reader * pfile ATTRIBUTE_UNUSED)
2815 arm_pragma_long_calls = LONG;
2819 arm_pr_no_long_calls (struct cpp_reader * pfile ATTRIBUTE_UNUSED)
2821 arm_pragma_long_calls = SHORT;
2825 arm_pr_long_calls_off (struct cpp_reader * pfile ATTRIBUTE_UNUSED)
2827 arm_pragma_long_calls = OFF;
2830 /* Table of machine attributes. */
2831 const struct attribute_spec arm_attribute_table[] =
2833 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
2834 /* Function calls made to this symbol must be done indirectly, because
2835 it may lie outside of the 26 bit addressing range of a normal function
2837 { "long_call", 0, 0, false, true, true, NULL },
2838 /* Whereas these functions are always known to reside within the 26 bit
2839 addressing range. */
2840 { "short_call", 0, 0, false, true, true, NULL },
2841 /* Interrupt Service Routines have special prologue and epilogue requirements. */
2842 { "isr", 0, 1, false, false, false, arm_handle_isr_attribute },
2843 { "interrupt", 0, 1, false, false, false, arm_handle_isr_attribute },
2844 { "naked", 0, 0, true, false, false, arm_handle_fndecl_attribute },
2846 /* ARM/PE has three new attributes:
2848 dllexport - for exporting a function/variable that will live in a dll
2849 dllimport - for importing a function/variable from a dll
2851 Microsoft allows multiple declspecs in one __declspec, separating
2852 them with spaces. We do NOT support this. Instead, use __declspec
2855 { "dllimport", 0, 0, true, false, false, NULL },
2856 { "dllexport", 0, 0, true, false, false, NULL },
2857 { "interfacearm", 0, 0, true, false, false, arm_handle_fndecl_attribute },
2858 #elif TARGET_DLLIMPORT_DECL_ATTRIBUTES
2859 { "dllimport", 0, 0, false, false, false, handle_dll_attribute },
2860 { "dllexport", 0, 0, false, false, false, handle_dll_attribute },
2861 { "notshared", 0, 0, false, true, false, arm_handle_notshared_attribute },
2863 { NULL, 0, 0, false, false, false, NULL }
2866 /* Handle an attribute requiring a FUNCTION_DECL;
2867 arguments as in struct attribute_spec.handler. */
2869 arm_handle_fndecl_attribute (tree *node, tree name, tree args ATTRIBUTE_UNUSED,
2870 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
2872 if (TREE_CODE (*node) != FUNCTION_DECL)
2874 warning (OPT_Wattributes, "%qs attribute only applies to functions",
2875 IDENTIFIER_POINTER (name));
2876 *no_add_attrs = true;
2882 /* Handle an "interrupt" or "isr" attribute;
2883 arguments as in struct attribute_spec.handler. */
2885 arm_handle_isr_attribute (tree *node, tree name, tree args, int flags,
2890 if (TREE_CODE (*node) != FUNCTION_DECL)
2892 warning (OPT_Wattributes, "%qs attribute only applies to functions",
2893 IDENTIFIER_POINTER (name));
2894 *no_add_attrs = true;
2896 /* FIXME: the argument if any is checked for type attributes;
2897 should it be checked for decl ones? */
2901 if (TREE_CODE (*node) == FUNCTION_TYPE
2902 || TREE_CODE (*node) == METHOD_TYPE)
2904 if (arm_isr_value (args) == ARM_FT_UNKNOWN)
2906 warning (OPT_Wattributes, "%qs attribute ignored",
2907 IDENTIFIER_POINTER (name));
2908 *no_add_attrs = true;
2911 else if (TREE_CODE (*node) == POINTER_TYPE
2912 && (TREE_CODE (TREE_TYPE (*node)) == FUNCTION_TYPE
2913 || TREE_CODE (TREE_TYPE (*node)) == METHOD_TYPE)
2914 && arm_isr_value (args) != ARM_FT_UNKNOWN)
2916 *node = build_variant_type_copy (*node);
2917 TREE_TYPE (*node) = build_type_attribute_variant
2919 tree_cons (name, args, TYPE_ATTRIBUTES (TREE_TYPE (*node))));
2920 *no_add_attrs = true;
2924 /* Possibly pass this attribute on from the type to a decl. */
2925 if (flags & ((int) ATTR_FLAG_DECL_NEXT
2926 | (int) ATTR_FLAG_FUNCTION_NEXT
2927 | (int) ATTR_FLAG_ARRAY_NEXT))
2929 *no_add_attrs = true;
2930 return tree_cons (name, args, NULL_TREE);
2934 warning (OPT_Wattributes, "%qs attribute ignored",
2935 IDENTIFIER_POINTER (name));
2943 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
2944 /* Handle the "notshared" attribute. This attribute is another way of
2945 requesting hidden visibility. ARM's compiler supports
2946 "__declspec(notshared)"; we support the same thing via an
2950 arm_handle_notshared_attribute (tree *node,
2951 tree name ATTRIBUTE_UNUSED,
2952 tree args ATTRIBUTE_UNUSED,
2953 int flags ATTRIBUTE_UNUSED,
2956 tree decl = TYPE_NAME (*node);
2960 DECL_VISIBILITY (decl) = VISIBILITY_HIDDEN;
2961 DECL_VISIBILITY_SPECIFIED (decl) = 1;
2962 *no_add_attrs = false;
2968 /* Return 0 if the attributes for two types are incompatible, 1 if they
2969 are compatible, and 2 if they are nearly compatible (which causes a
2970 warning to be generated). */
2972 arm_comp_type_attributes (tree type1, tree type2)
2976 /* Check for mismatch of non-default calling convention. */
2977 if (TREE_CODE (type1) != FUNCTION_TYPE)
2980 /* Check for mismatched call attributes. */
2981 l1 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type1)) != NULL;
2982 l2 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type2)) != NULL;
2983 s1 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type1)) != NULL;
2984 s2 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type2)) != NULL;
2986 /* Only bother to check if an attribute is defined. */
2987 if (l1 | l2 | s1 | s2)
2989 /* If one type has an attribute, the other must have the same attribute. */
2990 if ((l1 != l2) || (s1 != s2))
2993 /* Disallow mixed attributes. */
2994 if ((l1 & s2) || (l2 & s1))
2998 /* Check for mismatched ISR attribute. */
2999 l1 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type1)) != NULL;
3001 l1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type1)) != NULL;
3002 l2 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type2)) != NULL;
3004 l1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type2)) != NULL;
3011 /* Encode long_call or short_call attribute by prefixing
3012 symbol name in DECL with a special character FLAG. */
3014 arm_encode_call_attribute (tree decl, int flag)
3016 const char * str = XSTR (XEXP (DECL_RTL (decl), 0), 0);
3017 int len = strlen (str);
3020 /* Do not allow weak functions to be treated as short call. */
3021 if (DECL_WEAK (decl) && flag == SHORT_CALL_FLAG_CHAR)
3024 newstr = alloca (len + 2);
3026 strcpy (newstr + 1, str);
3028 newstr = (char *) ggc_alloc_string (newstr, len + 1);
3029 XSTR (XEXP (DECL_RTL (decl), 0), 0) = newstr;
3032 /* Assigns default attributes to newly defined type. This is used to
3033 set short_call/long_call attributes for function types of
3034 functions defined inside corresponding #pragma scopes. */
3036 arm_set_default_type_attributes (tree type)
3038 /* Add __attribute__ ((long_call)) to all functions, when
3039 inside #pragma long_calls or __attribute__ ((short_call)),
3040 when inside #pragma no_long_calls. */
3041 if (TREE_CODE (type) == FUNCTION_TYPE || TREE_CODE (type) == METHOD_TYPE)
3043 tree type_attr_list, attr_name;
3044 type_attr_list = TYPE_ATTRIBUTES (type);
3046 if (arm_pragma_long_calls == LONG)
3047 attr_name = get_identifier ("long_call");
3048 else if (arm_pragma_long_calls == SHORT)
3049 attr_name = get_identifier ("short_call");
3053 type_attr_list = tree_cons (attr_name, NULL_TREE, type_attr_list);
3054 TYPE_ATTRIBUTES (type) = type_attr_list;
3058 /* Return 1 if the operand is a SYMBOL_REF for a function known to be
3059 defined within the current compilation unit. If this cannot be
3060 determined, then 0 is returned. */
3062 current_file_function_operand (rtx sym_ref)
3064 /* This is a bit of a fib. A function will have a short call flag
3065 applied to its name if it has the short call attribute, or it has
3066 already been defined within the current compilation unit. */
3067 if (ENCODED_SHORT_CALL_ATTR_P (XSTR (sym_ref, 0)))
3070 /* The current function is always defined within the current compilation
3071 unit. If it s a weak definition however, then this may not be the real
3072 definition of the function, and so we have to say no. */
3073 if (sym_ref == XEXP (DECL_RTL (current_function_decl), 0)
3074 && !DECL_WEAK (current_function_decl))
3077 /* We cannot make the determination - default to returning 0. */
3081 /* Return nonzero if a 32 bit "long_call" should be generated for
3082 this call. We generate a long_call if the function:
3084 a. has an __attribute__((long call))
3085 or b. is within the scope of a #pragma long_calls
3086 or c. the -mlong-calls command line switch has been specified
3088 1. -ffunction-sections is in effect
3089 or 2. the current function has __attribute__ ((section))
3090 or 3. the target function has __attribute__ ((section))
3092 However we do not generate a long call if the function:
3094 d. has an __attribute__ ((short_call))
3095 or e. is inside the scope of a #pragma no_long_calls
3096 or f. is defined within the current compilation unit.
3098 This function will be called by C fragments contained in the machine
3099 description file. SYM_REF and CALL_COOKIE correspond to the matched
3100 rtl operands. CALL_SYMBOL is used to distinguish between
3101 two different callers of the function. It is set to 1 in the
3102 "call_symbol" and "call_symbol_value" patterns and to 0 in the "call"
3103 and "call_value" patterns. This is because of the difference in the
3104 SYM_REFs passed by these patterns. */
3106 arm_is_longcall_p (rtx sym_ref, int call_cookie, int call_symbol)
3110 if (GET_CODE (sym_ref) != MEM)
3113 sym_ref = XEXP (sym_ref, 0);
3116 if (GET_CODE (sym_ref) != SYMBOL_REF)
3119 if (call_cookie & CALL_SHORT)
3122 if (TARGET_LONG_CALLS)
3124 if (flag_function_sections
3125 || DECL_SECTION_NAME (current_function_decl))
3126 /* c.3 is handled by the definition of the
3127 ARM_DECLARE_FUNCTION_SIZE macro. */
3131 if (current_file_function_operand (sym_ref))
3134 return (call_cookie & CALL_LONG)
3135 || ENCODED_LONG_CALL_ATTR_P (XSTR (sym_ref, 0))
3136 || TARGET_LONG_CALLS;
3139 /* Return nonzero if it is ok to make a tail-call to DECL. */
3141 arm_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
3143 int call_type = TARGET_LONG_CALLS ? CALL_LONG : CALL_NORMAL;
3145 if (cfun->machine->sibcall_blocked)
3148 /* Never tailcall something for which we have no decl, or if we
3149 are in Thumb mode. */
3150 if (decl == NULL || TARGET_THUMB)
3153 /* Get the calling method. */
3154 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (TREE_TYPE (decl))))
3155 call_type = CALL_SHORT;
3156 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (TREE_TYPE (decl))))
3157 call_type = CALL_LONG;
3159 /* Cannot tail-call to long calls, since these are out of range of
3160 a branch instruction. However, if not compiling PIC, we know
3161 we can reach the symbol if it is in this compilation unit. */
3162 if (call_type == CALL_LONG && (flag_pic || !TREE_ASM_WRITTEN (decl)))
3165 /* If we are interworking and the function is not declared static
3166 then we can't tail-call it unless we know that it exists in this
3167 compilation unit (since it might be a Thumb routine). */
3168 if (TARGET_INTERWORK && TREE_PUBLIC (decl) && !TREE_ASM_WRITTEN (decl))
3171 /* Never tailcall from an ISR routine - it needs a special exit sequence. */
3172 if (IS_INTERRUPT (arm_current_func_type ()))
3175 /* Everything else is ok. */
3180 /* Addressing mode support functions. */
3182 /* Return nonzero if X is a legitimate immediate operand when compiling
3183 for PIC. We know that X satisfies CONSTANT_P and flag_pic is true. */
3185 legitimate_pic_operand_p (rtx x)
3187 if (GET_CODE (x) == SYMBOL_REF
3188 || (GET_CODE (x) == CONST
3189 && GET_CODE (XEXP (x, 0)) == PLUS
3190 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF))
3197 legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg)
3199 if (GET_CODE (orig) == SYMBOL_REF
3200 || GET_CODE (orig) == LABEL_REF)
3202 #ifndef AOF_ASSEMBLER
3203 rtx pic_ref, address;
3208 /* If this function doesn't have a pic register, create one now.
3209 A lot of the logic here is made obscure by the fact that this
3210 routine gets called as part of the rtx cost estimation
3211 process. We don't want those calls to affect any assumptions
3212 about the real function; and further, we can't call
3213 entry_of_function() until we start the real expansion
3215 if (!current_function_uses_pic_offset_table)
3217 gcc_assert (!no_new_pseudos);
3218 if (arm_pic_register != INVALID_REGNUM)
3220 if (!cfun->machine->pic_reg)
3221 cfun->machine->pic_reg = gen_rtx_REG (Pmode, arm_pic_register);
3223 /* Play games to avoid marking the function as needing pic
3224 if we are being called as part of the cost-estimation
3227 current_function_uses_pic_offset_table = 1;
3233 if (!cfun->machine->pic_reg)
3234 cfun->machine->pic_reg = gen_reg_rtx (Pmode);
3236 /* Play games to avoid marking the function as needing pic
3237 if we are being called as part of the cost-estimation
3241 current_function_uses_pic_offset_table = 1;
3244 arm_load_pic_register (0UL);
3248 emit_insn_after (seq, entry_of_function ());
3255 gcc_assert (!no_new_pseudos);
3256 reg = gen_reg_rtx (Pmode);
3261 #ifdef AOF_ASSEMBLER
3262 /* The AOF assembler can generate relocations for these directly, and
3263 understands that the PIC register has to be added into the offset. */
3264 insn = emit_insn (gen_pic_load_addr_based (reg, orig));
3267 address = gen_reg_rtx (Pmode);
3272 emit_insn (gen_pic_load_addr_arm (address, orig));
3274 emit_insn (gen_pic_load_addr_thumb (address, orig));
3276 if ((GET_CODE (orig) == LABEL_REF
3277 || (GET_CODE (orig) == SYMBOL_REF &&
3278 SYMBOL_REF_LOCAL_P (orig)))
3280 pic_ref = gen_rtx_PLUS (Pmode, cfun->machine->pic_reg, address);
3283 pic_ref = gen_const_mem (Pmode,
3284 gen_rtx_PLUS (Pmode, cfun->machine->pic_reg,
3288 insn = emit_move_insn (reg, pic_ref);
3290 /* Put a REG_EQUAL note on this insn, so that it can be optimized
3292 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig,
3296 else if (GET_CODE (orig) == CONST)
3300 if (GET_CODE (XEXP (orig, 0)) == PLUS
3301 && XEXP (XEXP (orig, 0), 0) == cfun->machine->pic_reg)
3304 if (GET_CODE (XEXP (orig, 0)) == UNSPEC
3305 && XINT (XEXP (orig, 0), 1) == UNSPEC_TLS)
3310 gcc_assert (!no_new_pseudos);
3311 reg = gen_reg_rtx (Pmode);
3314 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
3316 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
3317 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
3318 base == reg ? 0 : reg);
3320 if (GET_CODE (offset) == CONST_INT)
3322 /* The base register doesn't really matter, we only want to
3323 test the index for the appropriate mode. */
3324 if (!arm_legitimate_index_p (mode, offset, SET, 0))
3326 gcc_assert (!no_new_pseudos);
3327 offset = force_reg (Pmode, offset);
3330 if (GET_CODE (offset) == CONST_INT)
3331 return plus_constant (base, INTVAL (offset));
3334 if (GET_MODE_SIZE (mode) > 4
3335 && (GET_MODE_CLASS (mode) == MODE_INT
3336 || TARGET_SOFT_FLOAT))
3338 emit_insn (gen_addsi3 (reg, base, offset));
3342 return gen_rtx_PLUS (Pmode, base, offset);
3349 /* Find a spare low register to use during the prolog of a function. */
3352 thumb_find_work_register (unsigned long pushed_regs_mask)
3356 /* Check the argument registers first as these are call-used. The
3357 register allocation order means that sometimes r3 might be used
3358 but earlier argument registers might not, so check them all. */
3359 for (reg = LAST_ARG_REGNUM; reg >= 0; reg --)
3360 if (!regs_ever_live[reg])
3363 /* Before going on to check the call-saved registers we can try a couple
3364 more ways of deducing that r3 is available. The first is when we are
3365 pushing anonymous arguments onto the stack and we have less than 4
3366 registers worth of fixed arguments(*). In this case r3 will be part of
3367 the variable argument list and so we can be sure that it will be
3368 pushed right at the start of the function. Hence it will be available
3369 for the rest of the prologue.
3370 (*): ie current_function_pretend_args_size is greater than 0. */
3371 if (cfun->machine->uses_anonymous_args
3372 && current_function_pretend_args_size > 0)
3373 return LAST_ARG_REGNUM;
3375 /* The other case is when we have fixed arguments but less than 4 registers
3376 worth. In this case r3 might be used in the body of the function, but
3377 it is not being used to convey an argument into the function. In theory
3378 we could just check current_function_args_size to see how many bytes are
3379 being passed in argument registers, but it seems that it is unreliable.
3380 Sometimes it will have the value 0 when in fact arguments are being
3381 passed. (See testcase execute/20021111-1.c for an example). So we also
3382 check the args_info.nregs field as well. The problem with this field is
3383 that it makes no allowances for arguments that are passed to the
3384 function but which are not used. Hence we could miss an opportunity
3385 when a function has an unused argument in r3. But it is better to be
3386 safe than to be sorry. */
3387 if (! cfun->machine->uses_anonymous_args
3388 && current_function_args_size >= 0
3389 && current_function_args_size <= (LAST_ARG_REGNUM * UNITS_PER_WORD)
3390 && cfun->args_info.nregs < 4)
3391 return LAST_ARG_REGNUM;
3393 /* Otherwise look for a call-saved register that is going to be pushed. */
3394 for (reg = LAST_LO_REGNUM; reg > LAST_ARG_REGNUM; reg --)
3395 if (pushed_regs_mask & (1 << reg))
3398 /* Something went wrong - thumb_compute_save_reg_mask()
3399 should have arranged for a suitable register to be pushed. */
3403 static GTY(()) int pic_labelno;
3405 /* Generate code to load the PIC register. In thumb mode SCRATCH is a
3409 arm_load_pic_register (unsigned long saved_regs ATTRIBUTE_UNUSED)
3411 #ifndef AOF_ASSEMBLER
3412 rtx l1, labelno, pic_tmp, pic_tmp2, pic_rtx;
3413 rtx global_offset_table;
3415 if (current_function_uses_pic_offset_table == 0 || TARGET_SINGLE_PIC_BASE)
3418 gcc_assert (flag_pic);
3420 /* We use an UNSPEC rather than a LABEL_REF because this label never appears
3421 in the code stream. */
3423 labelno = GEN_INT (pic_labelno++);
3424 l1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, labelno), UNSPEC_PIC_LABEL);
3425 l1 = gen_rtx_CONST (VOIDmode, l1);
3427 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3428 /* On the ARM the PC register contains 'dot + 8' at the time of the
3429 addition, on the Thumb it is 'dot + 4'. */
3430 pic_tmp = plus_constant (l1, TARGET_ARM ? 8 : 4);
3432 pic_tmp2 = gen_rtx_CONST (VOIDmode,
3433 gen_rtx_PLUS (Pmode, global_offset_table, pc_rtx));
3435 pic_tmp2 = gen_rtx_CONST (VOIDmode, global_offset_table);
3437 pic_rtx = gen_rtx_CONST (Pmode, gen_rtx_MINUS (Pmode, pic_tmp2, pic_tmp));
3441 emit_insn (gen_pic_load_addr_arm (cfun->machine->pic_reg, pic_rtx));
3442 emit_insn (gen_pic_add_dot_plus_eight (cfun->machine->pic_reg,
3443 cfun->machine->pic_reg, labelno));
3447 if (arm_pic_register != INVALID_REGNUM
3448 && REGNO (cfun->machine->pic_reg) > LAST_LO_REGNUM)
3450 /* We will have pushed the pic register, so we should always be
3451 able to find a work register. */
3452 pic_tmp = gen_rtx_REG (SImode,
3453 thumb_find_work_register (saved_regs));
3454 emit_insn (gen_pic_load_addr_thumb (pic_tmp, pic_rtx));
3455 emit_insn (gen_movsi (pic_offset_table_rtx, pic_tmp));
3458 emit_insn (gen_pic_load_addr_thumb (cfun->machine->pic_reg, pic_rtx));
3459 emit_insn (gen_pic_add_dot_plus_four (cfun->machine->pic_reg,
3460 cfun->machine->pic_reg, labelno));
3463 /* Need to emit this whether or not we obey regdecls,
3464 since setjmp/longjmp can cause life info to screw up. */
3465 emit_insn (gen_rtx_USE (VOIDmode, cfun->machine->pic_reg));
3466 #endif /* AOF_ASSEMBLER */
3470 /* Return nonzero if X is valid as an ARM state addressing register. */
3472 arm_address_register_rtx_p (rtx x, int strict_p)
3476 if (GET_CODE (x) != REG)
3482 return ARM_REGNO_OK_FOR_BASE_P (regno);
3484 return (regno <= LAST_ARM_REGNUM
3485 || regno >= FIRST_PSEUDO_REGISTER
3486 || regno == FRAME_POINTER_REGNUM
3487 || regno == ARG_POINTER_REGNUM);
3490 /* Return TRUE if this rtx is the difference of a symbol and a label,
3491 and will reduce to a PC-relative relocation in the object file.
3492 Expressions like this can be left alone when generating PIC, rather
3493 than forced through the GOT. */
3495 pcrel_constant_p (rtx x)
3497 if (GET_CODE (x) == MINUS)
3498 return symbol_mentioned_p (XEXP (x, 0)) && label_mentioned_p (XEXP (x, 1));
3503 /* Return nonzero if X is a valid ARM state address operand. */
3505 arm_legitimate_address_p (enum machine_mode mode, rtx x, RTX_CODE outer,
3509 enum rtx_code code = GET_CODE (x);
3511 if (arm_address_register_rtx_p (x, strict_p))
3514 use_ldrd = (TARGET_LDRD
3516 || (mode == DFmode && (TARGET_SOFT_FLOAT || TARGET_VFP))));
3518 if (code == POST_INC || code == PRE_DEC
3519 || ((code == PRE_INC || code == POST_DEC)
3520 && (use_ldrd || GET_MODE_SIZE (mode) <= 4)))
3521 return arm_address_register_rtx_p (XEXP (x, 0), strict_p);
3523 else if ((code == POST_MODIFY || code == PRE_MODIFY)
3524 && arm_address_register_rtx_p (XEXP (x, 0), strict_p)
3525 && GET_CODE (XEXP (x, 1)) == PLUS
3526 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
3528 rtx addend = XEXP (XEXP (x, 1), 1);
3530 /* Don't allow ldrd post increment by register because it's hard
3531 to fixup invalid register choices. */
3533 && GET_CODE (x) == POST_MODIFY
3534 && GET_CODE (addend) == REG)
3537 return ((use_ldrd || GET_MODE_SIZE (mode) <= 4)
3538 && arm_legitimate_index_p (mode, addend, outer, strict_p));
3541 /* After reload constants split into minipools will have addresses
3542 from a LABEL_REF. */
3543 else if (reload_completed
3544 && (code == LABEL_REF
3546 && GET_CODE (XEXP (x, 0)) == PLUS
3547 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF
3548 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)))
3551 else if (mode == TImode)
3554 else if (code == PLUS)
3556 rtx xop0 = XEXP (x, 0);
3557 rtx xop1 = XEXP (x, 1);
3559 return ((arm_address_register_rtx_p (xop0, strict_p)
3560 && arm_legitimate_index_p (mode, xop1, outer, strict_p))
3561 || (arm_address_register_rtx_p (xop1, strict_p)
3562 && arm_legitimate_index_p (mode, xop0, outer, strict_p)));
3566 /* Reload currently can't handle MINUS, so disable this for now */
3567 else if (GET_CODE (x) == MINUS)
3569 rtx xop0 = XEXP (x, 0);
3570 rtx xop1 = XEXP (x, 1);
3572 return (arm_address_register_rtx_p (xop0, strict_p)
3573 && arm_legitimate_index_p (mode, xop1, outer, strict_p));
3577 else if (GET_MODE_CLASS (mode) != MODE_FLOAT
3578 && code == SYMBOL_REF
3579 && CONSTANT_POOL_ADDRESS_P (x)
3581 && symbol_mentioned_p (get_pool_constant (x))
3582 && ! pcrel_constant_p (get_pool_constant (x))))
3588 /* Return nonzero if INDEX is valid for an address index operand in
3591 arm_legitimate_index_p (enum machine_mode mode, rtx index, RTX_CODE outer,
3594 HOST_WIDE_INT range;
3595 enum rtx_code code = GET_CODE (index);
3597 /* Standard coprocessor addressing modes. */
3598 if (TARGET_HARD_FLOAT
3599 && (TARGET_FPA || TARGET_MAVERICK)
3600 && (GET_MODE_CLASS (mode) == MODE_FLOAT
3601 || (TARGET_MAVERICK && mode == DImode)))
3602 return (code == CONST_INT && INTVAL (index) < 1024
3603 && INTVAL (index) > -1024
3604 && (INTVAL (index) & 3) == 0);
3606 if (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode))
3608 /* For DImode assume values will usually live in core regs
3609 and only allow LDRD addressing modes. */
3610 if (!TARGET_LDRD || mode != DImode)
3611 return (code == CONST_INT
3612 && INTVAL (index) < 1024
3613 && INTVAL (index) > -1024
3614 && (INTVAL (index) & 3) == 0);
3617 if (arm_address_register_rtx_p (index, strict_p)
3618 && (GET_MODE_SIZE (mode) <= 4))
3621 if (mode == DImode || mode == DFmode)
3623 if (code == CONST_INT)
3625 HOST_WIDE_INT val = INTVAL (index);
3628 return val > -256 && val < 256;
3630 return val > -4096 && val < 4092;
3633 return TARGET_LDRD && arm_address_register_rtx_p (index, strict_p);
3636 if (GET_MODE_SIZE (mode) <= 4
3639 || (mode == QImode && outer == SIGN_EXTEND))))
3643 rtx xiop0 = XEXP (index, 0);
3644 rtx xiop1 = XEXP (index, 1);
3646 return ((arm_address_register_rtx_p (xiop0, strict_p)
3647 && power_of_two_operand (xiop1, SImode))
3648 || (arm_address_register_rtx_p (xiop1, strict_p)
3649 && power_of_two_operand (xiop0, SImode)));
3651 else if (code == LSHIFTRT || code == ASHIFTRT
3652 || code == ASHIFT || code == ROTATERT)
3654 rtx op = XEXP (index, 1);
3656 return (arm_address_register_rtx_p (XEXP (index, 0), strict_p)
3657 && GET_CODE (op) == CONST_INT
3659 && INTVAL (op) <= 31);
3663 /* For ARM v4 we may be doing a sign-extend operation during the
3667 if (mode == HImode || (outer == SIGN_EXTEND && mode == QImode))
3673 range = (mode == HImode) ? 4095 : 4096;
3675 return (code == CONST_INT
3676 && INTVAL (index) < range
3677 && INTVAL (index) > -range);
3680 /* Return nonzero if X is valid as a Thumb state base register. */
3682 thumb_base_register_rtx_p (rtx x, enum machine_mode mode, int strict_p)
3686 if (GET_CODE (x) != REG)
3692 return THUMB_REGNO_MODE_OK_FOR_BASE_P (regno, mode);
3694 return (regno <= LAST_LO_REGNUM
3695 || regno > LAST_VIRTUAL_REGISTER
3696 || regno == FRAME_POINTER_REGNUM
3697 || (GET_MODE_SIZE (mode) >= 4
3698 && (regno == STACK_POINTER_REGNUM
3699 || regno >= FIRST_PSEUDO_REGISTER
3700 || x == hard_frame_pointer_rtx
3701 || x == arg_pointer_rtx)));
3704 /* Return nonzero if x is a legitimate index register. This is the case
3705 for any base register that can access a QImode object. */
3707 thumb_index_register_rtx_p (rtx x, int strict_p)
3709 return thumb_base_register_rtx_p (x, QImode, strict_p);
3712 /* Return nonzero if x is a legitimate Thumb-state address.
3714 The AP may be eliminated to either the SP or the FP, so we use the
3715 least common denominator, e.g. SImode, and offsets from 0 to 64.
3717 ??? Verify whether the above is the right approach.
3719 ??? Also, the FP may be eliminated to the SP, so perhaps that
3720 needs special handling also.
3722 ??? Look at how the mips16 port solves this problem. It probably uses
3723 better ways to solve some of these problems.
3725 Although it is not incorrect, we don't accept QImode and HImode
3726 addresses based on the frame pointer or arg pointer until the
3727 reload pass starts. This is so that eliminating such addresses
3728 into stack based ones won't produce impossible code. */
3730 thumb_legitimate_address_p (enum machine_mode mode, rtx x, int strict_p)
3732 /* ??? Not clear if this is right. Experiment. */
3733 if (GET_MODE_SIZE (mode) < 4
3734 && !(reload_in_progress || reload_completed)
3735 && (reg_mentioned_p (frame_pointer_rtx, x)
3736 || reg_mentioned_p (arg_pointer_rtx, x)
3737 || reg_mentioned_p (virtual_incoming_args_rtx, x)
3738 || reg_mentioned_p (virtual_outgoing_args_rtx, x)
3739 || reg_mentioned_p (virtual_stack_dynamic_rtx, x)
3740 || reg_mentioned_p (virtual_stack_vars_rtx, x)))
3743 /* Accept any base register. SP only in SImode or larger. */
3744 else if (thumb_base_register_rtx_p (x, mode, strict_p))
3747 /* This is PC relative data before arm_reorg runs. */
3748 else if (GET_MODE_SIZE (mode) >= 4 && CONSTANT_P (x)
3749 && GET_CODE (x) == SYMBOL_REF
3750 && CONSTANT_POOL_ADDRESS_P (x) && !flag_pic)
3753 /* This is PC relative data after arm_reorg runs. */
3754 else if (GET_MODE_SIZE (mode) >= 4 && reload_completed
3755 && (GET_CODE (x) == LABEL_REF
3756 || (GET_CODE (x) == CONST
3757 && GET_CODE (XEXP (x, 0)) == PLUS
3758 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF
3759 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)))
3762 /* Post-inc indexing only supported for SImode and larger. */
3763 else if (GET_CODE (x) == POST_INC && GET_MODE_SIZE (mode) >= 4
3764 && thumb_index_register_rtx_p (XEXP (x, 0), strict_p))
3767 else if (GET_CODE (x) == PLUS)
3769 /* REG+REG address can be any two index registers. */
3770 /* We disallow FRAME+REG addressing since we know that FRAME
3771 will be replaced with STACK, and SP relative addressing only
3772 permits SP+OFFSET. */
3773 if (GET_MODE_SIZE (mode) <= 4
3774 && XEXP (x, 0) != frame_pointer_rtx
3775 && XEXP (x, 1) != frame_pointer_rtx
3776 && thumb_index_register_rtx_p (XEXP (x, 0), strict_p)
3777 && thumb_index_register_rtx_p (XEXP (x, 1), strict_p))
3780 /* REG+const has 5-7 bit offset for non-SP registers. */
3781 else if ((thumb_index_register_rtx_p (XEXP (x, 0), strict_p)
3782 || XEXP (x, 0) == arg_pointer_rtx)
3783 && GET_CODE (XEXP (x, 1)) == CONST_INT
3784 && thumb_legitimate_offset_p (mode, INTVAL (XEXP (x, 1))))
3787 /* REG+const has 10 bit offset for SP, but only SImode and
3788 larger is supported. */
3789 /* ??? Should probably check for DI/DFmode overflow here
3790 just like GO_IF_LEGITIMATE_OFFSET does. */
3791 else if (GET_CODE (XEXP (x, 0)) == REG
3792 && REGNO (XEXP (x, 0)) == STACK_POINTER_REGNUM
3793 && GET_MODE_SIZE (mode) >= 4
3794 && GET_CODE (XEXP (x, 1)) == CONST_INT
3795 && INTVAL (XEXP (x, 1)) >= 0
3796 && INTVAL (XEXP (x, 1)) + GET_MODE_SIZE (mode) <= 1024
3797 && (INTVAL (XEXP (x, 1)) & 3) == 0)
3800 else if (GET_CODE (XEXP (x, 0)) == REG
3801 && REGNO (XEXP (x, 0)) == FRAME_POINTER_REGNUM
3802 && GET_MODE_SIZE (mode) >= 4
3803 && GET_CODE (XEXP (x, 1)) == CONST_INT
3804 && (INTVAL (XEXP (x, 1)) & 3) == 0)
3808 else if (GET_MODE_CLASS (mode) != MODE_FLOAT
3809 && GET_MODE_SIZE (mode) == 4
3810 && GET_CODE (x) == SYMBOL_REF
3811 && CONSTANT_POOL_ADDRESS_P (x)
3813 && symbol_mentioned_p (get_pool_constant (x))
3814 && ! pcrel_constant_p (get_pool_constant (x))))
3820 /* Return nonzero if VAL can be used as an offset in a Thumb-state address
3821 instruction of mode MODE. */
3823 thumb_legitimate_offset_p (enum machine_mode mode, HOST_WIDE_INT val)
3825 switch (GET_MODE_SIZE (mode))
3828 return val >= 0 && val < 32;
3831 return val >= 0 && val < 64 && (val & 1) == 0;
3835 && (val + GET_MODE_SIZE (mode)) <= 128
3840 /* Build the SYMBOL_REF for __tls_get_addr. */
3842 static GTY(()) rtx tls_get_addr_libfunc;
3845 get_tls_get_addr (void)
3847 if (!tls_get_addr_libfunc)
3848 tls_get_addr_libfunc = init_one_libfunc ("__tls_get_addr");
3849 return tls_get_addr_libfunc;
3853 arm_load_tp (rtx target)
3856 target = gen_reg_rtx (SImode);
3860 /* Can return in any reg. */
3861 emit_insn (gen_load_tp_hard (target));
3865 /* Always returned in r0. Immediately copy the result into a pseudo,
3866 otherwise other uses of r0 (e.g. setting up function arguments) may
3867 clobber the value. */
3871 emit_insn (gen_load_tp_soft ());
3873 tmp = gen_rtx_REG (SImode, 0);
3874 emit_move_insn (target, tmp);
3880 load_tls_operand (rtx x, rtx reg)
3884 if (reg == NULL_RTX)
3885 reg = gen_reg_rtx (SImode);
3887 tmp = gen_rtx_CONST (SImode, x);
3889 emit_move_insn (reg, tmp);
3895 arm_call_tls_get_addr (rtx x, rtx reg, rtx *valuep, int reloc)
3897 rtx insns, label, labelno, sum;
3901 labelno = GEN_INT (pic_labelno++);
3902 label = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, labelno), UNSPEC_PIC_LABEL);
3903 label = gen_rtx_CONST (VOIDmode, label);
3905 sum = gen_rtx_UNSPEC (Pmode,
3906 gen_rtvec (4, x, GEN_INT (reloc), label,
3907 GEN_INT (TARGET_ARM ? 8 : 4)),
3909 reg = load_tls_operand (sum, reg);
3912 emit_insn (gen_pic_add_dot_plus_eight (reg, reg, labelno));
3914 emit_insn (gen_pic_add_dot_plus_four (reg, reg, labelno));
3916 *valuep = emit_library_call_value (get_tls_get_addr (), NULL_RTX, LCT_PURE, /* LCT_CONST? */
3917 Pmode, 1, reg, Pmode);
3919 insns = get_insns ();
3926 legitimize_tls_address (rtx x, rtx reg)
3928 rtx dest, tp, label, labelno, sum, insns, ret, eqv, addend;
3929 unsigned int model = SYMBOL_REF_TLS_MODEL (x);
3933 case TLS_MODEL_GLOBAL_DYNAMIC:
3934 insns = arm_call_tls_get_addr (x, reg, &ret, TLS_GD32);
3935 dest = gen_reg_rtx (Pmode);
3936 emit_libcall_block (insns, dest, ret, x);
3939 case TLS_MODEL_LOCAL_DYNAMIC:
3940 insns = arm_call_tls_get_addr (x, reg, &ret, TLS_LDM32);
3942 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
3943 share the LDM result with other LD model accesses. */
3944 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const1_rtx),
3946 dest = gen_reg_rtx (Pmode);
3947 emit_libcall_block (insns, dest, ret, eqv);
3949 /* Load the addend. */
3950 addend = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, x, GEN_INT (TLS_LDO32)),
3952 addend = force_reg (SImode, gen_rtx_CONST (SImode, addend));
3953 return gen_rtx_PLUS (Pmode, dest, addend);
3955 case TLS_MODEL_INITIAL_EXEC:
3956 labelno = GEN_INT (pic_labelno++);
3957 label = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, labelno), UNSPEC_PIC_LABEL);
3958 label = gen_rtx_CONST (VOIDmode, label);
3959 sum = gen_rtx_UNSPEC (Pmode,
3960 gen_rtvec (4, x, GEN_INT (TLS_IE32), label,
3961 GEN_INT (TARGET_ARM ? 8 : 4)),
3963 reg = load_tls_operand (sum, reg);
3966 emit_insn (gen_tls_load_dot_plus_eight (reg, reg, labelno));
3969 emit_insn (gen_pic_add_dot_plus_four (reg, reg, labelno));
3970 emit_move_insn (reg, gen_const_mem (SImode, reg));
3973 tp = arm_load_tp (NULL_RTX);
3975 return gen_rtx_PLUS (Pmode, tp, reg);
3977 case TLS_MODEL_LOCAL_EXEC:
3978 tp = arm_load_tp (NULL_RTX);
3980 reg = gen_rtx_UNSPEC (Pmode,
3981 gen_rtvec (2, x, GEN_INT (TLS_LE32)),
3983 reg = force_reg (SImode, gen_rtx_CONST (SImode, reg));
3985 return gen_rtx_PLUS (Pmode, tp, reg);
3992 /* Try machine-dependent ways of modifying an illegitimate address
3993 to be legitimate. If we find one, return the new, valid address. */
3995 arm_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode)
3997 if (arm_tls_symbol_p (x))
3998 return legitimize_tls_address (x, NULL_RTX);
4000 if (GET_CODE (x) == PLUS)
4002 rtx xop0 = XEXP (x, 0);
4003 rtx xop1 = XEXP (x, 1);
4005 if (CONSTANT_P (xop0) && !symbol_mentioned_p (xop0))
4006 xop0 = force_reg (SImode, xop0);
4008 if (CONSTANT_P (xop1) && !symbol_mentioned_p (xop1))
4009 xop1 = force_reg (SImode, xop1);
4011 if (ARM_BASE_REGISTER_RTX_P (xop0)
4012 && GET_CODE (xop1) == CONST_INT)
4014 HOST_WIDE_INT n, low_n;
4018 /* VFP addressing modes actually allow greater offsets, but for
4019 now we just stick with the lowest common denominator. */
4021 || ((TARGET_SOFT_FLOAT || TARGET_VFP) && mode == DFmode))
4033 low_n = ((mode) == TImode ? 0
4034 : n >= 0 ? (n & 0xfff) : -((-n) & 0xfff));
4038 base_reg = gen_reg_rtx (SImode);
4039 val = force_operand (plus_constant (xop0, n), NULL_RTX);
4040 emit_move_insn (base_reg, val);
4041 x = plus_constant (base_reg, low_n);
4043 else if (xop0 != XEXP (x, 0) || xop1 != XEXP (x, 1))
4044 x = gen_rtx_PLUS (SImode, xop0, xop1);
4047 /* XXX We don't allow MINUS any more -- see comment in
4048 arm_legitimate_address_p (). */
4049 else if (GET_CODE (x) == MINUS)
4051 rtx xop0 = XEXP (x, 0);
4052 rtx xop1 = XEXP (x, 1);
4054 if (CONSTANT_P (xop0))
4055 xop0 = force_reg (SImode, xop0);
4057 if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1))
4058 xop1 = force_reg (SImode, xop1);
4060 if (xop0 != XEXP (x, 0) || xop1 != XEXP (x, 1))
4061 x = gen_rtx_MINUS (SImode, xop0, xop1);
4064 /* Make sure to take full advantage of the pre-indexed addressing mode
4065 with absolute addresses which often allows for the base register to
4066 be factorized for multiple adjacent memory references, and it might
4067 even allows for the mini pool to be avoided entirely. */
4068 else if (GET_CODE (x) == CONST_INT && optimize > 0)
4071 HOST_WIDE_INT mask, base, index;
4074 /* ldr and ldrb can use a 12 bit index, ldrsb and the rest can only
4075 use a 8 bit index. So let's use a 12 bit index for SImode only and
4076 hope that arm_gen_constant will enable ldrb to use more bits. */
4077 bits = (mode == SImode) ? 12 : 8;
4078 mask = (1 << bits) - 1;
4079 base = INTVAL (x) & ~mask;
4080 index = INTVAL (x) & mask;
4081 if (bit_count (base & 0xffffffff) > (32 - bits)/2)
4083 /* It'll most probably be more efficient to generate the base
4084 with more bits set and use a negative index instead. */
4088 base_reg = force_reg (SImode, GEN_INT (base));
4089 x = plus_constant (base_reg, index);
4094 /* We need to find and carefully transform any SYMBOL and LABEL
4095 references; so go back to the original address expression. */
4096 rtx new_x = legitimize_pic_address (orig_x, mode, NULL_RTX);
4098 if (new_x != orig_x)
4106 /* Try machine-dependent ways of modifying an illegitimate Thumb address
4107 to be legitimate. If we find one, return the new, valid address. */
4109 thumb_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode)
4111 if (arm_tls_symbol_p (x))
4112 return legitimize_tls_address (x, NULL_RTX);
4114 if (GET_CODE (x) == PLUS
4115 && GET_CODE (XEXP (x, 1)) == CONST_INT
4116 && (INTVAL (XEXP (x, 1)) >= 32 * GET_MODE_SIZE (mode)
4117 || INTVAL (XEXP (x, 1)) < 0))
4119 rtx xop0 = XEXP (x, 0);
4120 rtx xop1 = XEXP (x, 1);
4121 HOST_WIDE_INT offset = INTVAL (xop1);
4123 /* Try and fold the offset into a biasing of the base register and
4124 then offsetting that. Don't do this when optimizing for space
4125 since it can cause too many CSEs. */
4126 if (optimize_size && offset >= 0
4127 && offset < 256 + 31 * GET_MODE_SIZE (mode))
4129 HOST_WIDE_INT delta;
4132 delta = offset - (256 - GET_MODE_SIZE (mode));
4133 else if (offset < 32 * GET_MODE_SIZE (mode) + 8)
4134 delta = 31 * GET_MODE_SIZE (mode);
4136 delta = offset & (~31 * GET_MODE_SIZE (mode));
4138 xop0 = force_operand (plus_constant (xop0, offset - delta),
4140 x = plus_constant (xop0, delta);
4142 else if (offset < 0 && offset > -256)
4143 /* Small negative offsets are best done with a subtract before the
4144 dereference, forcing these into a register normally takes two
4146 x = force_operand (x, NULL_RTX);
4149 /* For the remaining cases, force the constant into a register. */
4150 xop1 = force_reg (SImode, xop1);
4151 x = gen_rtx_PLUS (SImode, xop0, xop1);
4154 else if (GET_CODE (x) == PLUS
4155 && s_register_operand (XEXP (x, 1), SImode)
4156 && !s_register_operand (XEXP (x, 0), SImode))
4158 rtx xop0 = force_operand (XEXP (x, 0), NULL_RTX);
4160 x = gen_rtx_PLUS (SImode, xop0, XEXP (x, 1));
4165 /* We need to find and carefully transform any SYMBOL and LABEL
4166 references; so go back to the original address expression. */
4167 rtx new_x = legitimize_pic_address (orig_x, mode, NULL_RTX);
4169 if (new_x != orig_x)
4177 thumb_legitimize_reload_address (rtx *x_p,
4178 enum machine_mode mode,
4179 int opnum, int type,
4180 int ind_levels ATTRIBUTE_UNUSED)
4184 if (GET_CODE (x) == PLUS
4185 && GET_MODE_SIZE (mode) < 4
4186 && REG_P (XEXP (x, 0))
4187 && XEXP (x, 0) == stack_pointer_rtx
4188 && GET_CODE (XEXP (x, 1)) == CONST_INT
4189 && !thumb_legitimate_offset_p (mode, INTVAL (XEXP (x, 1))))
4194 push_reload (orig_x, NULL_RTX, x_p, NULL, MODE_BASE_REG_CLASS (mode),
4195 Pmode, VOIDmode, 0, 0, opnum, type);
4199 /* If both registers are hi-regs, then it's better to reload the
4200 entire expression rather than each register individually. That
4201 only requires one reload register rather than two. */
4202 if (GET_CODE (x) == PLUS
4203 && REG_P (XEXP (x, 0))
4204 && REG_P (XEXP (x, 1))
4205 && !REG_MODE_OK_FOR_REG_BASE_P (XEXP (x, 0), mode)
4206 && !REG_MODE_OK_FOR_REG_BASE_P (XEXP (x, 1), mode))
4211 push_reload (orig_x, NULL_RTX, x_p, NULL, MODE_BASE_REG_CLASS (mode),
4212 Pmode, VOIDmode, 0, 0, opnum, type);
4219 /* Test for various thread-local symbols. */
4221 /* Return TRUE if X is a thread-local symbol. */
4224 arm_tls_symbol_p (rtx x)
4226 if (! TARGET_HAVE_TLS)
4229 if (GET_CODE (x) != SYMBOL_REF)
4232 return SYMBOL_REF_TLS_MODEL (x) != 0;
4235 /* Helper for arm_tls_referenced_p. */
4238 arm_tls_operand_p_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
4240 if (GET_CODE (*x) == SYMBOL_REF)
4241 return SYMBOL_REF_TLS_MODEL (*x) != 0;
4243 /* Don't recurse into UNSPEC_TLS looking for TLS symbols; these are
4244 TLS offsets, not real symbol references. */
4245 if (GET_CODE (*x) == UNSPEC
4246 && XINT (*x, 1) == UNSPEC_TLS)
4252 /* Return TRUE if X contains any TLS symbol references. */
4255 arm_tls_referenced_p (rtx x)
4257 if (! TARGET_HAVE_TLS)
4260 return for_each_rtx (&x, arm_tls_operand_p_1, NULL);
4263 #define REG_OR_SUBREG_REG(X) \
4264 (GET_CODE (X) == REG \
4265 || (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG))
4267 #define REG_OR_SUBREG_RTX(X) \
4268 (GET_CODE (X) == REG ? (X) : SUBREG_REG (X))
4270 #ifndef COSTS_N_INSNS
4271 #define COSTS_N_INSNS(N) ((N) * 4 - 2)
4274 thumb_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer)
4276 enum machine_mode mode = GET_MODE (x);
4289 return COSTS_N_INSNS (1);
4292 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4295 unsigned HOST_WIDE_INT i = INTVAL (XEXP (x, 1));
4302 return COSTS_N_INSNS (2) + cycles;
4304 return COSTS_N_INSNS (1) + 16;
4307 return (COSTS_N_INSNS (1)
4308 + 4 * ((GET_CODE (SET_SRC (x)) == MEM)
4309 + GET_CODE (SET_DEST (x)) == MEM));
4314 if ((unsigned HOST_WIDE_INT) INTVAL (x) < 256)
4316 if (thumb_shiftable_const (INTVAL (x)))
4317 return COSTS_N_INSNS (2);
4318 return COSTS_N_INSNS (3);
4320 else if ((outer == PLUS || outer == COMPARE)
4321 && INTVAL (x) < 256 && INTVAL (x) > -256)
4323 else if (outer == AND
4324 && INTVAL (x) < 256 && INTVAL (x) >= -256)
4325 return COSTS_N_INSNS (1);
4326 else if (outer == ASHIFT || outer == ASHIFTRT
4327 || outer == LSHIFTRT)
4329 return COSTS_N_INSNS (2);
4335 return COSTS_N_INSNS (3);
4353 /* XXX another guess. */
4354 /* Memory costs quite a lot for the first word, but subsequent words
4355 load at the equivalent of a single insn each. */
4356 return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD)
4357 + ((GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
4362 if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)
4367 /* XXX still guessing. */
4368 switch (GET_MODE (XEXP (x, 0)))
4371 return (1 + (mode == DImode ? 4 : 0)
4372 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
4375 return (4 + (mode == DImode ? 4 : 0)
4376 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
4379 return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
4391 /* Worker routine for arm_rtx_costs. */
4393 arm_rtx_costs_1 (rtx x, enum rtx_code code, enum rtx_code outer)
4395 enum machine_mode mode = GET_MODE (x);
4396 enum rtx_code subcode;
4402 /* Memory costs quite a lot for the first word, but subsequent words
4403 load at the equivalent of a single insn each. */
4404 return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD)
4405 + (GET_CODE (x) == SYMBOL_REF
4406 && CONSTANT_POOL_ADDRESS_P (x) ? 4 : 0));
4412 return optimize_size ? COSTS_N_INSNS (2) : 100;
4415 if (mode == SImode && GET_CODE (XEXP (x, 1)) == REG)
4422 case ASHIFT: case LSHIFTRT: case ASHIFTRT:
4424 return (8 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : 8)
4425 + ((GET_CODE (XEXP (x, 0)) == REG
4426 || (GET_CODE (XEXP (x, 0)) == SUBREG
4427 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG))
4429 return (1 + ((GET_CODE (XEXP (x, 0)) == REG
4430 || (GET_CODE (XEXP (x, 0)) == SUBREG
4431 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG))
4433 + ((GET_CODE (XEXP (x, 1)) == REG
4434 || (GET_CODE (XEXP (x, 1)) == SUBREG
4435 && GET_CODE (SUBREG_REG (XEXP (x, 1))) == REG)
4436 || (GET_CODE (XEXP (x, 1)) == CONST_INT))
4441 return (4 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 8)
4442 + ((REG_OR_SUBREG_REG (XEXP (x, 0))
4443 || (GET_CODE (XEXP (x, 0)) == CONST_INT
4444 && const_ok_for_arm (INTVAL (XEXP (x, 0)))))
4447 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
4448 return (2 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
4449 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
4450 && arm_const_double_rtx (XEXP (x, 1))))
4452 + ((REG_OR_SUBREG_REG (XEXP (x, 0))
4453 || (GET_CODE (XEXP (x, 0)) == CONST_DOUBLE
4454 && arm_const_double_rtx (XEXP (x, 0))))
4457 if (((GET_CODE (XEXP (x, 0)) == CONST_INT
4458 && const_ok_for_arm (INTVAL (XEXP (x, 0)))
4459 && REG_OR_SUBREG_REG (XEXP (x, 1))))
4460 || (((subcode = GET_CODE (XEXP (x, 1))) == ASHIFT
4461 || subcode == ASHIFTRT || subcode == LSHIFTRT
4462 || subcode == ROTATE || subcode == ROTATERT
4464 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4465 && ((INTVAL (XEXP (XEXP (x, 1), 1)) &
4466 (INTVAL (XEXP (XEXP (x, 1), 1)) - 1)) == 0)))
4467 && REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 0))
4468 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 1))
4469 || GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT)
4470 && REG_OR_SUBREG_REG (XEXP (x, 0))))
4475 if (GET_CODE (XEXP (x, 0)) == MULT)
4477 extra_cost = rtx_cost (XEXP (x, 0), code);
4478 if (!REG_OR_SUBREG_REG (XEXP (x, 1)))
4479 extra_cost += 4 * ARM_NUM_REGS (mode);
4483 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
4484 return (2 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)
4485 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
4486 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
4487 && arm_const_double_rtx (XEXP (x, 1))))
4491 case AND: case XOR: case IOR:
4494 /* Normally the frame registers will be spilt into reg+const during
4495 reload, so it is a bad idea to combine them with other instructions,
4496 since then they might not be moved outside of loops. As a compromise
4497 we allow integration with ops that have a constant as their second
4499 if ((REG_OR_SUBREG_REG (XEXP (x, 0))
4500 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))
4501 && GET_CODE (XEXP (x, 1)) != CONST_INT)
4502 || (REG_OR_SUBREG_REG (XEXP (x, 0))
4503 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))))
4507 return (4 + extra_cost + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)
4508 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
4509 || (GET_CODE (XEXP (x, 1)) == CONST_INT
4510 && const_ok_for_op (INTVAL (XEXP (x, 1)), code)))
4513 if (REG_OR_SUBREG_REG (XEXP (x, 0)))
4514 return (1 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : extra_cost)
4515 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
4516 || (GET_CODE (XEXP (x, 1)) == CONST_INT
4517 && const_ok_for_op (INTVAL (XEXP (x, 1)), code)))
4520 else if (REG_OR_SUBREG_REG (XEXP (x, 1)))
4521 return (1 + extra_cost
4522 + ((((subcode = GET_CODE (XEXP (x, 0))) == ASHIFT
4523 || subcode == LSHIFTRT || subcode == ASHIFTRT
4524 || subcode == ROTATE || subcode == ROTATERT
4526 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4527 && ((INTVAL (XEXP (XEXP (x, 0), 1)) &
4528 (INTVAL (XEXP (XEXP (x, 0), 1)) - 1)) == 0)))
4529 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 0)))
4530 && ((REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 1)))
4531 || GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT))
4537 /* This should have been handled by the CPU specific routines. */
4541 if (arm_arch3m && mode == SImode
4542 && GET_CODE (XEXP (x, 0)) == LSHIFTRT
4543 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
4544 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0))
4545 == GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)))
4546 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ZERO_EXTEND
4547 || GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == SIGN_EXTEND))
4552 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
4553 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 6);
4557 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4);
4559 return 1 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4);
4562 if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)
4570 return 4 + (mode == DImode ? 4 : 0);
4573 if (GET_MODE (XEXP (x, 0)) == QImode)
4574 return (4 + (mode == DImode ? 4 : 0)
4575 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
4578 switch (GET_MODE (XEXP (x, 0)))
4581 return (1 + (mode == DImode ? 4 : 0)
4582 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
4585 return (4 + (mode == DImode ? 4 : 0)
4586 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
4589 return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
4604 if (const_ok_for_arm (INTVAL (x)))
4605 return outer == SET ? 2 : -1;
4606 else if (outer == AND
4607 && const_ok_for_arm (~INTVAL (x)))
4609 else if ((outer == COMPARE
4610 || outer == PLUS || outer == MINUS)
4611 && const_ok_for_arm (-INTVAL (x)))
4622 if (arm_const_double_rtx (x))
4623 return outer == SET ? 2 : -1;
4624 else if ((outer == COMPARE || outer == PLUS)
4625 && neg_const_double_rtx_ok_for_fpa (x))
4634 /* RTX costs when optimizing for size. */
4636 arm_size_rtx_costs (rtx x, int code, int outer_code, int *total)
4638 enum machine_mode mode = GET_MODE (x);
4642 /* XXX TBD. For now, use the standard costs. */
4643 *total = thumb_rtx_costs (x, code, outer_code);
4650 /* A memory access costs 1 insn if the mode is small, or the address is
4651 a single register, otherwise it costs one insn per word. */
4652 if (REG_P (XEXP (x, 0)))
4653 *total = COSTS_N_INSNS (1);
4655 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
4662 /* Needs a libcall, so it costs about this. */
4663 *total = COSTS_N_INSNS (2);
4667 if (mode == SImode && GET_CODE (XEXP (x, 1)) == REG)
4669 *total = COSTS_N_INSNS (2) + rtx_cost (XEXP (x, 0), code);
4677 if (mode == DImode && GET_CODE (XEXP (x, 1)) == CONST_INT)
4679 *total = COSTS_N_INSNS (3) + rtx_cost (XEXP (x, 0), code);
4682 else if (mode == SImode)
4684 *total = COSTS_N_INSNS (1) + rtx_cost (XEXP (x, 0), code);
4685 /* Slightly disparage register shifts, but not by much. */
4686 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
4687 *total += 1 + rtx_cost (XEXP (x, 1), code);
4691 /* Needs a libcall. */
4692 *total = COSTS_N_INSNS (2);
4696 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT)
4698 *total = COSTS_N_INSNS (1);
4704 enum rtx_code subcode0 = GET_CODE (XEXP (x, 0));
4705 enum rtx_code subcode1 = GET_CODE (XEXP (x, 1));
4707 if (subcode0 == ROTATE || subcode0 == ROTATERT || subcode0 == ASHIFT
4708 || subcode0 == LSHIFTRT || subcode0 == ASHIFTRT
4709 || subcode1 == ROTATE || subcode1 == ROTATERT
4710 || subcode1 == ASHIFT || subcode1 == LSHIFTRT
4711 || subcode1 == ASHIFTRT)
4713 /* It's just the cost of the two operands. */
4718 *total = COSTS_N_INSNS (1);
4722 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
4726 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT)
4728 *total = COSTS_N_INSNS (1);
4733 case AND: case XOR: case IOR:
4736 enum rtx_code subcode = GET_CODE (XEXP (x, 0));
4738 if (subcode == ROTATE || subcode == ROTATERT || subcode == ASHIFT
4739 || subcode == LSHIFTRT || subcode == ASHIFTRT
4740 || (code == AND && subcode == NOT))
4742 /* It's just the cost of the two operands. */
4748 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
4752 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
4756 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT)
4757 *total = COSTS_N_INSNS (1);
4760 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
4769 if (cc_register (XEXP (x, 0), VOIDmode))
4772 *total = COSTS_N_INSNS (1);
4776 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT)
4777 *total = COSTS_N_INSNS (1);
4779 *total = COSTS_N_INSNS (1 + ARM_NUM_REGS (mode));
4784 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) < 4)
4786 if (!(arm_arch4 && MEM_P (XEXP (x, 0))))
4787 *total += COSTS_N_INSNS (arm_arch6 ? 1 : 2);
4790 *total += COSTS_N_INSNS (1);
4795 if (!(arm_arch4 && MEM_P (XEXP (x, 0))))
4797 switch (GET_MODE (XEXP (x, 0)))
4800 *total += COSTS_N_INSNS (1);
4804 *total += COSTS_N_INSNS (arm_arch6 ? 1 : 2);
4810 *total += COSTS_N_INSNS (2);
4815 *total += COSTS_N_INSNS (1);
4820 if (const_ok_for_arm (INTVAL (x)))
4821 *total = COSTS_N_INSNS (outer_code == SET ? 1 : 0);
4822 else if (const_ok_for_arm (~INTVAL (x)))
4823 *total = COSTS_N_INSNS (outer_code == AND ? 0 : 1);
4824 else if (const_ok_for_arm (-INTVAL (x)))
4826 if (outer_code == COMPARE || outer_code == PLUS
4827 || outer_code == MINUS)
4830 *total = COSTS_N_INSNS (1);
4833 *total = COSTS_N_INSNS (2);
4839 *total = COSTS_N_INSNS (2);
4843 *total = COSTS_N_INSNS (4);
4847 if (mode != VOIDmode)
4848 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
4850 *total = COSTS_N_INSNS (4); /* How knows? */
4855 /* RTX costs for cores with a slow MUL implementation. */
4858 arm_slowmul_rtx_costs (rtx x, int code, int outer_code, int *total)
4860 enum machine_mode mode = GET_MODE (x);
4864 *total = thumb_rtx_costs (x, code, outer_code);
4871 if (GET_MODE_CLASS (mode) == MODE_FLOAT
4878 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4880 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
4881 & (unsigned HOST_WIDE_INT) 0xffffffff);
4882 int cost, const_ok = const_ok_for_arm (i);
4883 int j, booth_unit_size;
4885 /* Tune as appropriate. */
4886 cost = const_ok ? 4 : 8;
4887 booth_unit_size = 2;
4888 for (j = 0; i && j < 32; j += booth_unit_size)
4890 i >>= booth_unit_size;
4898 *total = 30 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)
4899 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4);
4903 *total = arm_rtx_costs_1 (x, code, outer_code);
4909 /* RTX cost for cores with a fast multiply unit (M variants). */
4912 arm_fastmul_rtx_costs (rtx x, int code, int outer_code, int *total)
4914 enum machine_mode mode = GET_MODE (x);
4918 *total = thumb_rtx_costs (x, code, outer_code);
4925 /* There is no point basing this on the tuning, since it is always the
4926 fast variant if it exists at all. */
4928 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
4929 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
4930 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
4937 if (GET_MODE_CLASS (mode) == MODE_FLOAT
4944 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4946 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
4947 & (unsigned HOST_WIDE_INT) 0xffffffff);
4948 int cost, const_ok = const_ok_for_arm (i);
4949 int j, booth_unit_size;
4951 /* Tune as appropriate. */
4952 cost = const_ok ? 4 : 8;
4953 booth_unit_size = 8;
4954 for (j = 0; i && j < 32; j += booth_unit_size)
4956 i >>= booth_unit_size;
4964 *total = 8 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)
4965 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4);
4969 *total = arm_rtx_costs_1 (x, code, outer_code);
4975 /* RTX cost for XScale CPUs. */
4978 arm_xscale_rtx_costs (rtx x, int code, int outer_code, int *total)
4980 enum machine_mode mode = GET_MODE (x);
4984 *total = thumb_rtx_costs (x, code, outer_code);
4991 /* There is no point basing this on the tuning, since it is always the
4992 fast variant if it exists at all. */
4994 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
4995 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
4996 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
5003 if (GET_MODE_CLASS (mode) == MODE_FLOAT
5010 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
5012 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
5013 & (unsigned HOST_WIDE_INT) 0xffffffff);
5014 int cost, const_ok = const_ok_for_arm (i);
5015 unsigned HOST_WIDE_INT masked_const;
5017 /* The cost will be related to two insns.
5018 First a load of the constant (MOV or LDR), then a multiply. */
5021 cost += 1; /* LDR is probably more expensive because
5022 of longer result latency. */
5023 masked_const = i & 0xffff8000;
5024 if (masked_const != 0 && masked_const != 0xffff8000)
5026 masked_const = i & 0xf8000000;
5027 if (masked_const == 0 || masked_const == 0xf8000000)
5036 *total = 8 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)
5037 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4);
5041 /* A COMPARE of a MULT is slow on XScale; the muls instruction
5042 will stall until the multiplication is complete. */
5043 if (GET_CODE (XEXP (x, 0)) == MULT)
5044 *total = 4 + rtx_cost (XEXP (x, 0), code);
5046 *total = arm_rtx_costs_1 (x, code, outer_code);
5050 *total = arm_rtx_costs_1 (x, code, outer_code);
5056 /* RTX costs for 9e (and later) cores. */
5059 arm_9e_rtx_costs (rtx x, int code, int outer_code, int *total)
5061 enum machine_mode mode = GET_MODE (x);
5070 *total = COSTS_N_INSNS (3);
5074 *total = thumb_rtx_costs (x, code, outer_code);
5082 /* There is no point basing this on the tuning, since it is always the
5083 fast variant if it exists at all. */
5085 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
5086 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
5087 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
5094 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
5111 *total = cost + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : nonreg_cost)
5112 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : nonreg_cost);
5116 *total = arm_rtx_costs_1 (x, code, outer_code);
5120 /* All address computations that can be done are free, but rtx cost returns
5121 the same for practically all of them. So we weight the different types
5122 of address here in the order (most pref first):
5123 PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */
5125 arm_arm_address_cost (rtx x)
5127 enum rtx_code c = GET_CODE (x);
5129 if (c == PRE_INC || c == PRE_DEC || c == POST_INC || c == POST_DEC)
5131 if (c == MEM || c == LABEL_REF || c == SYMBOL_REF)
5134 if (c == PLUS || c == MINUS)
5136 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
5139 if (ARITHMETIC_P (XEXP (x, 0)) || ARITHMETIC_P (XEXP (x, 1)))
5149 arm_thumb_address_cost (rtx x)
5151 enum rtx_code c = GET_CODE (x);
5156 && GET_CODE (XEXP (x, 0)) == REG
5157 && GET_CODE (XEXP (x, 1)) == CONST_INT)
5164 arm_address_cost (rtx x)
5166 return TARGET_ARM ? arm_arm_address_cost (x) : arm_thumb_address_cost (x);
5170 arm_adjust_cost (rtx insn, rtx link, rtx dep, int cost)
5174 /* Some true dependencies can have a higher cost depending
5175 on precisely how certain input operands are used. */
5177 && REG_NOTE_KIND (link) == 0
5178 && recog_memoized (insn) >= 0
5179 && recog_memoized (dep) >= 0)
5181 int shift_opnum = get_attr_shift (insn);
5182 enum attr_type attr_type = get_attr_type (dep);
5184 /* If nonzero, SHIFT_OPNUM contains the operand number of a shifted
5185 operand for INSN. If we have a shifted input operand and the
5186 instruction we depend on is another ALU instruction, then we may
5187 have to account for an additional stall. */
5188 if (shift_opnum != 0
5189 && (attr_type == TYPE_ALU_SHIFT || attr_type == TYPE_ALU_SHIFT_REG))
5191 rtx shifted_operand;
5194 /* Get the shifted operand. */
5195 extract_insn (insn);
5196 shifted_operand = recog_data.operand[shift_opnum];
5198 /* Iterate over all the operands in DEP. If we write an operand
5199 that overlaps with SHIFTED_OPERAND, then we have increase the
5200 cost of this dependency. */
5202 preprocess_constraints ();
5203 for (opno = 0; opno < recog_data.n_operands; opno++)
5205 /* We can ignore strict inputs. */
5206 if (recog_data.operand_type[opno] == OP_IN)
5209 if (reg_overlap_mentioned_p (recog_data.operand[opno],
5216 /* XXX This is not strictly true for the FPA. */
5217 if (REG_NOTE_KIND (link) == REG_DEP_ANTI
5218 || REG_NOTE_KIND (link) == REG_DEP_OUTPUT)
5221 /* Call insns don't incur a stall, even if they follow a load. */
5222 if (REG_NOTE_KIND (link) == 0
5223 && GET_CODE (insn) == CALL_INSN)
5226 if ((i_pat = single_set (insn)) != NULL
5227 && GET_CODE (SET_SRC (i_pat)) == MEM
5228 && (d_pat = single_set (dep)) != NULL
5229 && GET_CODE (SET_DEST (d_pat)) == MEM)
5231 rtx src_mem = XEXP (SET_SRC (i_pat), 0);
5232 /* This is a load after a store, there is no conflict if the load reads
5233 from a cached area. Assume that loads from the stack, and from the
5234 constant pool are cached, and that others will miss. This is a
5237 if ((GET_CODE (src_mem) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (src_mem))
5238 || reg_mentioned_p (stack_pointer_rtx, src_mem)
5239 || reg_mentioned_p (frame_pointer_rtx, src_mem)
5240 || reg_mentioned_p (hard_frame_pointer_rtx, src_mem))
5247 static int fp_consts_inited = 0;
5249 /* Only zero is valid for VFP. Other values are also valid for FPA. */
5250 static const char * const strings_fp[8] =
5253 "4", "5", "0.5", "10"
5256 static REAL_VALUE_TYPE values_fp[8];
5259 init_fp_table (void)
5265 fp_consts_inited = 1;
5267 fp_consts_inited = 8;
5269 for (i = 0; i < fp_consts_inited; i++)
5271 r = REAL_VALUE_ATOF (strings_fp[i], DFmode);
5276 /* Return TRUE if rtx X is a valid immediate FP constant. */
5278 arm_const_double_rtx (rtx x)
5283 if (!fp_consts_inited)
5286 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
5287 if (REAL_VALUE_MINUS_ZERO (r))
5290 for (i = 0; i < fp_consts_inited; i++)
5291 if (REAL_VALUES_EQUAL (r, values_fp[i]))
5297 /* Return TRUE if rtx X is a valid immediate FPA constant. */
5299 neg_const_double_rtx_ok_for_fpa (rtx x)
5304 if (!fp_consts_inited)
5307 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
5308 r = REAL_VALUE_NEGATE (r);
5309 if (REAL_VALUE_MINUS_ZERO (r))
5312 for (i = 0; i < 8; i++)
5313 if (REAL_VALUES_EQUAL (r, values_fp[i]))
5319 /* Predicates for `match_operand' and `match_operator'. */
5321 /* Return nonzero if OP is a valid Cirrus memory address pattern. */
5323 cirrus_memory_offset (rtx op)
5325 /* Reject eliminable registers. */
5326 if (! (reload_in_progress || reload_completed)
5327 && ( reg_mentioned_p (frame_pointer_rtx, op)
5328 || reg_mentioned_p (arg_pointer_rtx, op)
5329 || reg_mentioned_p (virtual_incoming_args_rtx, op)
5330 || reg_mentioned_p (virtual_outgoing_args_rtx, op)
5331 || reg_mentioned_p (virtual_stack_dynamic_rtx, op)
5332 || reg_mentioned_p (virtual_stack_vars_rtx, op)))
5335 if (GET_CODE (op) == MEM)
5341 /* Match: (mem (reg)). */
5342 if (GET_CODE (ind) == REG)
5348 if (GET_CODE (ind) == PLUS
5349 && GET_CODE (XEXP (ind, 0)) == REG
5350 && REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode)
5351 && GET_CODE (XEXP (ind, 1)) == CONST_INT)
5358 /* Return TRUE if OP is a valid coprocessor memory address pattern.
5359 WB if true if writeback address modes are allowed. */
5362 arm_coproc_mem_operand (rtx op, bool wb)
5366 /* Reject eliminable registers. */
5367 if (! (reload_in_progress || reload_completed)
5368 && ( reg_mentioned_p (frame_pointer_rtx, op)
5369 || reg_mentioned_p (arg_pointer_rtx, op)
5370 || reg_mentioned_p (virtual_incoming_args_rtx, op)
5371 || reg_mentioned_p (virtual_outgoing_args_rtx, op)
5372 || reg_mentioned_p (virtual_stack_dynamic_rtx, op)
5373 || reg_mentioned_p (virtual_stack_vars_rtx, op)))
5376 /* Constants are converted into offsets from labels. */
5377 if (GET_CODE (op) != MEM)
5382 if (reload_completed
5383 && (GET_CODE (ind) == LABEL_REF
5384 || (GET_CODE (ind) == CONST
5385 && GET_CODE (XEXP (ind, 0)) == PLUS
5386 && GET_CODE (XEXP (XEXP (ind, 0), 0)) == LABEL_REF
5387 && GET_CODE (XEXP (XEXP (ind, 0), 1)) == CONST_INT)))
5390 /* Match: (mem (reg)). */
5391 if (GET_CODE (ind) == REG)
5392 return arm_address_register_rtx_p (ind, 0);
5394 /* Autoincremment addressing modes. */
5396 && (GET_CODE (ind) == PRE_INC
5397 || GET_CODE (ind) == POST_INC
5398 || GET_CODE (ind) == PRE_DEC
5399 || GET_CODE (ind) == POST_DEC))
5400 return arm_address_register_rtx_p (XEXP (ind, 0), 0);
5403 && (GET_CODE (ind) == POST_MODIFY || GET_CODE (ind) == PRE_MODIFY)
5404 && arm_address_register_rtx_p (XEXP (ind, 0), 0)
5405 && GET_CODE (XEXP (ind, 1)) == PLUS
5406 && rtx_equal_p (XEXP (XEXP (ind, 1), 0), XEXP (ind, 0)))
5407 ind = XEXP (ind, 1);
5412 if (GET_CODE (ind) == PLUS
5413 && GET_CODE (XEXP (ind, 0)) == REG
5414 && REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode)
5415 && GET_CODE (XEXP (ind, 1)) == CONST_INT
5416 && INTVAL (XEXP (ind, 1)) > -1024
5417 && INTVAL (XEXP (ind, 1)) < 1024
5418 && (INTVAL (XEXP (ind, 1)) & 3) == 0)
5424 /* Return true if X is a register that will be eliminated later on. */
5426 arm_eliminable_register (rtx x)
5428 return REG_P (x) && (REGNO (x) == FRAME_POINTER_REGNUM
5429 || REGNO (x) == ARG_POINTER_REGNUM
5430 || (REGNO (x) >= FIRST_VIRTUAL_REGISTER
5431 && REGNO (x) <= LAST_VIRTUAL_REGISTER));
5434 /* Return GENERAL_REGS if a scratch register required to reload x to/from
5435 coprocessor registers. Otherwise return NO_REGS. */
5438 coproc_secondary_reload_class (enum machine_mode mode, rtx x, bool wb)
5440 if (arm_coproc_mem_operand (x, wb) || s_register_operand (x, mode))
5443 return GENERAL_REGS;
5446 /* Values which must be returned in the most-significant end of the return
5450 arm_return_in_msb (tree valtype)
5452 return (TARGET_AAPCS_BASED
5454 && (AGGREGATE_TYPE_P (valtype)
5455 || TREE_CODE (valtype) == COMPLEX_TYPE));
5458 /* Returns TRUE if INSN is an "LDR REG, ADDR" instruction.
5459 Use by the Cirrus Maverick code which has to workaround
5460 a hardware bug triggered by such instructions. */
5462 arm_memory_load_p (rtx insn)
5464 rtx body, lhs, rhs;;
5466 if (insn == NULL_RTX || GET_CODE (insn) != INSN)
5469 body = PATTERN (insn);
5471 if (GET_CODE (body) != SET)
5474 lhs = XEXP (body, 0);
5475 rhs = XEXP (body, 1);
5477 lhs = REG_OR_SUBREG_RTX (lhs);
5479 /* If the destination is not a general purpose
5480 register we do not have to worry. */
5481 if (GET_CODE (lhs) != REG
5482 || REGNO_REG_CLASS (REGNO (lhs)) != GENERAL_REGS)
5485 /* As well as loads from memory we also have to react
5486 to loads of invalid constants which will be turned
5487 into loads from the minipool. */
5488 return (GET_CODE (rhs) == MEM
5489 || GET_CODE (rhs) == SYMBOL_REF
5490 || note_invalid_constants (insn, -1, false));
5493 /* Return TRUE if INSN is a Cirrus instruction. */
5495 arm_cirrus_insn_p (rtx insn)
5497 enum attr_cirrus attr;
5499 /* get_attr cannot accept USE or CLOBBER. */
5501 || GET_CODE (insn) != INSN
5502 || GET_CODE (PATTERN (insn)) == USE
5503 || GET_CODE (PATTERN (insn)) == CLOBBER)
5506 attr = get_attr_cirrus (insn);
5508 return attr != CIRRUS_NOT;
5511 /* Cirrus reorg for invalid instruction combinations. */
5513 cirrus_reorg (rtx first)
5515 enum attr_cirrus attr;
5516 rtx body = PATTERN (first);
5520 /* Any branch must be followed by 2 non Cirrus instructions. */
5521 if (GET_CODE (first) == JUMP_INSN && GET_CODE (body) != RETURN)
5524 t = next_nonnote_insn (first);
5526 if (arm_cirrus_insn_p (t))
5529 if (arm_cirrus_insn_p (next_nonnote_insn (t)))
5533 emit_insn_after (gen_nop (), first);
5538 /* (float (blah)) is in parallel with a clobber. */
5539 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0)
5540 body = XVECEXP (body, 0, 0);
5542 if (GET_CODE (body) == SET)
5544 rtx lhs = XEXP (body, 0), rhs = XEXP (body, 1);
5546 /* cfldrd, cfldr64, cfstrd, cfstr64 must
5547 be followed by a non Cirrus insn. */
5548 if (get_attr_cirrus (first) == CIRRUS_DOUBLE)
5550 if (arm_cirrus_insn_p (next_nonnote_insn (first)))
5551 emit_insn_after (gen_nop (), first);
5555 else if (arm_memory_load_p (first))
5557 unsigned int arm_regno;
5559 /* Any ldr/cfmvdlr, ldr/cfmvdhr, ldr/cfmvsr, ldr/cfmv64lr,
5560 ldr/cfmv64hr combination where the Rd field is the same
5561 in both instructions must be split with a non Cirrus
5568 /* Get Arm register number for ldr insn. */
5569 if (GET_CODE (lhs) == REG)
5570 arm_regno = REGNO (lhs);
5573 gcc_assert (GET_CODE (rhs) == REG);
5574 arm_regno = REGNO (rhs);
5578 first = next_nonnote_insn (first);
5580 if (! arm_cirrus_insn_p (first))
5583 body = PATTERN (first);
5585 /* (float (blah)) is in parallel with a clobber. */
5586 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0))
5587 body = XVECEXP (body, 0, 0);
5589 if (GET_CODE (body) == FLOAT)
5590 body = XEXP (body, 0);
5592 if (get_attr_cirrus (first) == CIRRUS_MOVE
5593 && GET_CODE (XEXP (body, 1)) == REG
5594 && arm_regno == REGNO (XEXP (body, 1)))
5595 emit_insn_after (gen_nop (), first);
5601 /* get_attr cannot accept USE or CLOBBER. */
5603 || GET_CODE (first) != INSN
5604 || GET_CODE (PATTERN (first)) == USE
5605 || GET_CODE (PATTERN (first)) == CLOBBER)
5608 attr = get_attr_cirrus (first);
5610 /* Any coprocessor compare instruction (cfcmps, cfcmpd, ...)
5611 must be followed by a non-coprocessor instruction. */
5612 if (attr == CIRRUS_COMPARE)
5616 t = next_nonnote_insn (first);
5618 if (arm_cirrus_insn_p (t))
5621 if (arm_cirrus_insn_p (next_nonnote_insn (t)))
5625 emit_insn_after (gen_nop (), first);
5631 /* Return TRUE if X references a SYMBOL_REF. */
5633 symbol_mentioned_p (rtx x)
5638 if (GET_CODE (x) == SYMBOL_REF)
5641 /* UNSPEC_TLS entries for a symbol include the SYMBOL_REF, but they
5642 are constant offsets, not symbols. */
5643 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLS)
5646 fmt = GET_RTX_FORMAT (GET_CODE (x));
5648 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5654 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
5655 if (symbol_mentioned_p (XVECEXP (x, i, j)))
5658 else if (fmt[i] == 'e' && symbol_mentioned_p (XEXP (x, i)))
5665 /* Return TRUE if X references a LABEL_REF. */
5667 label_mentioned_p (rtx x)
5672 if (GET_CODE (x) == LABEL_REF)
5675 /* UNSPEC_TLS entries for a symbol include a LABEL_REF for the referencing
5676 instruction, but they are constant offsets, not symbols. */
5677 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLS)
5680 fmt = GET_RTX_FORMAT (GET_CODE (x));
5681 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5687 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
5688 if (label_mentioned_p (XVECEXP (x, i, j)))
5691 else if (fmt[i] == 'e' && label_mentioned_p (XEXP (x, i)))
5699 tls_mentioned_p (rtx x)
5701 switch (GET_CODE (x))
5704 return tls_mentioned_p (XEXP (x, 0));
5707 if (XINT (x, 1) == UNSPEC_TLS)
5715 /* Must not copy a SET whose source operand is PC-relative. */
5718 arm_cannot_copy_insn_p (rtx insn)
5720 rtx pat = PATTERN (insn);
5722 if (GET_CODE (pat) == PARALLEL
5723 && GET_CODE (XVECEXP (pat, 0, 0)) == SET)
5725 rtx rhs = SET_SRC (XVECEXP (pat, 0, 0));
5727 if (GET_CODE (rhs) == UNSPEC
5728 && XINT (rhs, 1) == UNSPEC_PIC_BASE)
5731 if (GET_CODE (rhs) == MEM
5732 && GET_CODE (XEXP (rhs, 0)) == UNSPEC
5733 && XINT (XEXP (rhs, 0), 1) == UNSPEC_PIC_BASE)
5743 enum rtx_code code = GET_CODE (x);
5760 /* Return 1 if memory locations are adjacent. */
5762 adjacent_mem_locations (rtx a, rtx b)
5764 /* We don't guarantee to preserve the order of these memory refs. */
5765 if (volatile_refs_p (a) || volatile_refs_p (b))
5768 if ((GET_CODE (XEXP (a, 0)) == REG
5769 || (GET_CODE (XEXP (a, 0)) == PLUS
5770 && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT))
5771 && (GET_CODE (XEXP (b, 0)) == REG
5772 || (GET_CODE (XEXP (b, 0)) == PLUS
5773 && GET_CODE (XEXP (XEXP (b, 0), 1)) == CONST_INT)))
5775 HOST_WIDE_INT val0 = 0, val1 = 0;
5779 if (GET_CODE (XEXP (a, 0)) == PLUS)
5781 reg0 = XEXP (XEXP (a, 0), 0);
5782 val0 = INTVAL (XEXP (XEXP (a, 0), 1));
5787 if (GET_CODE (XEXP (b, 0)) == PLUS)
5789 reg1 = XEXP (XEXP (b, 0), 0);
5790 val1 = INTVAL (XEXP (XEXP (b, 0), 1));
5795 /* Don't accept any offset that will require multiple
5796 instructions to handle, since this would cause the
5797 arith_adjacentmem pattern to output an overlong sequence. */
5798 if (!const_ok_for_op (PLUS, val0) || !const_ok_for_op (PLUS, val1))
5801 /* Don't allow an eliminable register: register elimination can make
5802 the offset too large. */
5803 if (arm_eliminable_register (reg0))
5806 val_diff = val1 - val0;
5810 /* If the target has load delay slots, then there's no benefit
5811 to using an ldm instruction unless the offset is zero and
5812 we are optimizing for size. */
5813 return (optimize_size && (REGNO (reg0) == REGNO (reg1))
5814 && (val0 == 0 || val1 == 0 || val0 == 4 || val1 == 4)
5815 && (val_diff == 4 || val_diff == -4));
5818 return ((REGNO (reg0) == REGNO (reg1))
5819 && (val_diff == 4 || val_diff == -4));
5826 load_multiple_sequence (rtx *operands, int nops, int *regs, int *base,
5827 HOST_WIDE_INT *load_offset)
5829 int unsorted_regs[4];
5830 HOST_WIDE_INT unsorted_offsets[4];
5835 /* Can only handle 2, 3, or 4 insns at present,
5836 though could be easily extended if required. */
5837 gcc_assert (nops >= 2 && nops <= 4);
5839 /* Loop over the operands and check that the memory references are
5840 suitable (i.e. immediate offsets from the same base register). At
5841 the same time, extract the target register, and the memory
5843 for (i = 0; i < nops; i++)
5848 /* Convert a subreg of a mem into the mem itself. */
5849 if (GET_CODE (operands[nops + i]) == SUBREG)
5850 operands[nops + i] = alter_subreg (operands + (nops + i));
5852 gcc_assert (GET_CODE (operands[nops + i]) == MEM);
5854 /* Don't reorder volatile memory references; it doesn't seem worth
5855 looking for the case where the order is ok anyway. */
5856 if (MEM_VOLATILE_P (operands[nops + i]))
5859 offset = const0_rtx;
5861 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
5862 || (GET_CODE (reg) == SUBREG
5863 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
5864 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
5865 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
5867 || (GET_CODE (reg) == SUBREG
5868 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
5869 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
5874 base_reg = REGNO (reg);
5875 unsorted_regs[0] = (GET_CODE (operands[i]) == REG
5876 ? REGNO (operands[i])
5877 : REGNO (SUBREG_REG (operands[i])));
5882 if (base_reg != (int) REGNO (reg))
5883 /* Not addressed from the same base register. */
5886 unsorted_regs[i] = (GET_CODE (operands[i]) == REG
5887 ? REGNO (operands[i])
5888 : REGNO (SUBREG_REG (operands[i])));
5889 if (unsorted_regs[i] < unsorted_regs[order[0]])
5893 /* If it isn't an integer register, or if it overwrites the
5894 base register but isn't the last insn in the list, then
5895 we can't do this. */
5896 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14
5897 || (i != nops - 1 && unsorted_regs[i] == base_reg))
5900 unsorted_offsets[i] = INTVAL (offset);
5903 /* Not a suitable memory address. */
5907 /* All the useful information has now been extracted from the
5908 operands into unsorted_regs and unsorted_offsets; additionally,
5909 order[0] has been set to the lowest numbered register in the
5910 list. Sort the registers into order, and check that the memory
5911 offsets are ascending and adjacent. */
5913 for (i = 1; i < nops; i++)
5917 order[i] = order[i - 1];
5918 for (j = 0; j < nops; j++)
5919 if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
5920 && (order[i] == order[i - 1]
5921 || unsorted_regs[j] < unsorted_regs[order[i]]))
5924 /* Have we found a suitable register? if not, one must be used more
5926 if (order[i] == order[i - 1])
5929 /* Is the memory address adjacent and ascending? */
5930 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
5938 for (i = 0; i < nops; i++)
5939 regs[i] = unsorted_regs[order[i]];
5941 *load_offset = unsorted_offsets[order[0]];
5944 if (unsorted_offsets[order[0]] == 0)
5945 return 1; /* ldmia */
5947 if (unsorted_offsets[order[0]] == 4)
5948 return 2; /* ldmib */
5950 if (unsorted_offsets[order[nops - 1]] == 0)
5951 return 3; /* ldmda */
5953 if (unsorted_offsets[order[nops - 1]] == -4)
5954 return 4; /* ldmdb */
5956 /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm
5957 if the offset isn't small enough. The reason 2 ldrs are faster
5958 is because these ARMs are able to do more than one cache access
5959 in a single cycle. The ARM9 and StrongARM have Harvard caches,
5960 whilst the ARM8 has a double bandwidth cache. This means that
5961 these cores can do both an instruction fetch and a data fetch in
5962 a single cycle, so the trick of calculating the address into a
5963 scratch register (one of the result regs) and then doing a load
5964 multiple actually becomes slower (and no smaller in code size).
5965 That is the transformation
5967 ldr rd1, [rbase + offset]
5968 ldr rd2, [rbase + offset + 4]
5972 add rd1, rbase, offset
5973 ldmia rd1, {rd1, rd2}
5975 produces worse code -- '3 cycles + any stalls on rd2' instead of
5976 '2 cycles + any stalls on rd2'. On ARMs with only one cache
5977 access per cycle, the first sequence could never complete in less
5978 than 6 cycles, whereas the ldm sequence would only take 5 and
5979 would make better use of sequential accesses if not hitting the
5982 We cheat here and test 'arm_ld_sched' which we currently know to
5983 only be true for the ARM8, ARM9 and StrongARM. If this ever
5984 changes, then the test below needs to be reworked. */
5985 if (nops == 2 && arm_ld_sched)
5988 /* Can't do it without setting up the offset, only do this if it takes
5989 no more than one insn. */
5990 return (const_ok_for_arm (unsorted_offsets[order[0]])
5991 || const_ok_for_arm (-unsorted_offsets[order[0]])) ? 5 : 0;
5995 emit_ldm_seq (rtx *operands, int nops)
5999 HOST_WIDE_INT offset;
6003 switch (load_multiple_sequence (operands, nops, regs, &base_reg, &offset))
6006 strcpy (buf, "ldm%?ia\t");
6010 strcpy (buf, "ldm%?ib\t");
6014 strcpy (buf, "ldm%?da\t");
6018 strcpy (buf, "ldm%?db\t");
6023 sprintf (buf, "add%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
6024 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
6027 sprintf (buf, "sub%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
6028 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
6030 output_asm_insn (buf, operands);
6032 strcpy (buf, "ldm%?ia\t");
6039 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
6040 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
6042 for (i = 1; i < nops; i++)
6043 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
6044 reg_names[regs[i]]);
6046 strcat (buf, "}\t%@ phole ldm");
6048 output_asm_insn (buf, operands);
6053 store_multiple_sequence (rtx *operands, int nops, int *regs, int *base,
6054 HOST_WIDE_INT * load_offset)
6056 int unsorted_regs[4];
6057 HOST_WIDE_INT unsorted_offsets[4];
6062 /* Can only handle 2, 3, or 4 insns at present, though could be easily
6063 extended if required. */
6064 gcc_assert (nops >= 2 && nops <= 4);
6066 /* Loop over the operands and check that the memory references are
6067 suitable (i.e. immediate offsets from the same base register). At
6068 the same time, extract the target register, and the memory
6070 for (i = 0; i < nops; i++)
6075 /* Convert a subreg of a mem into the mem itself. */
6076 if (GET_CODE (operands[nops + i]) == SUBREG)
6077 operands[nops + i] = alter_subreg (operands + (nops + i));
6079 gcc_assert (GET_CODE (operands[nops + i]) == MEM);
6081 /* Don't reorder volatile memory references; it doesn't seem worth
6082 looking for the case where the order is ok anyway. */
6083 if (MEM_VOLATILE_P (operands[nops + i]))
6086 offset = const0_rtx;
6088 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
6089 || (GET_CODE (reg) == SUBREG
6090 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
6091 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
6092 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
6094 || (GET_CODE (reg) == SUBREG
6095 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
6096 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
6101 base_reg = REGNO (reg);
6102 unsorted_regs[0] = (GET_CODE (operands[i]) == REG
6103 ? REGNO (operands[i])
6104 : REGNO (SUBREG_REG (operands[i])));
6109 if (base_reg != (int) REGNO (reg))
6110 /* Not addressed from the same base register. */
6113 unsorted_regs[i] = (GET_CODE (operands[i]) == REG
6114 ? REGNO (operands[i])
6115 : REGNO (SUBREG_REG (operands[i])));
6116 if (unsorted_regs[i] < unsorted_regs[order[0]])
6120 /* If it isn't an integer register, then we can't do this. */
6121 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14)
6124 unsorted_offsets[i] = INTVAL (offset);
6127 /* Not a suitable memory address. */
6131 /* All the useful information has now been extracted from the
6132 operands into unsorted_regs and unsorted_offsets; additionally,
6133 order[0] has been set to the lowest numbered register in the
6134 list. Sort the registers into order, and check that the memory
6135 offsets are ascending and adjacent. */
6137 for (i = 1; i < nops; i++)
6141 order[i] = order[i - 1];
6142 for (j = 0; j < nops; j++)
6143 if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
6144 && (order[i] == order[i - 1]
6145 || unsorted_regs[j] < unsorted_regs[order[i]]))
6148 /* Have we found a suitable register? if not, one must be used more
6150 if (order[i] == order[i - 1])
6153 /* Is the memory address adjacent and ascending? */
6154 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
6162 for (i = 0; i < nops; i++)
6163 regs[i] = unsorted_regs[order[i]];
6165 *load_offset = unsorted_offsets[order[0]];
6168 if (unsorted_offsets[order[0]] == 0)
6169 return 1; /* stmia */
6171 if (unsorted_offsets[order[0]] == 4)
6172 return 2; /* stmib */
6174 if (unsorted_offsets[order[nops - 1]] == 0)
6175 return 3; /* stmda */
6177 if (unsorted_offsets[order[nops - 1]] == -4)
6178 return 4; /* stmdb */
6184 emit_stm_seq (rtx *operands, int nops)
6188 HOST_WIDE_INT offset;
6192 switch (store_multiple_sequence (operands, nops, regs, &base_reg, &offset))
6195 strcpy (buf, "stm%?ia\t");
6199 strcpy (buf, "stm%?ib\t");
6203 strcpy (buf, "stm%?da\t");
6207 strcpy (buf, "stm%?db\t");
6214 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
6215 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
6217 for (i = 1; i < nops; i++)
6218 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
6219 reg_names[regs[i]]);
6221 strcat (buf, "}\t%@ phole stm");
6223 output_asm_insn (buf, operands);
6227 /* Routines for use in generating RTL. */
6230 arm_gen_load_multiple (int base_regno, int count, rtx from, int up,
6231 int write_back, rtx basemem, HOST_WIDE_INT *offsetp)
6233 HOST_WIDE_INT offset = *offsetp;
6236 int sign = up ? 1 : -1;
6239 /* XScale has load-store double instructions, but they have stricter
6240 alignment requirements than load-store multiple, so we cannot
6243 For XScale ldm requires 2 + NREGS cycles to complete and blocks
6244 the pipeline until completion.
6252 An ldr instruction takes 1-3 cycles, but does not block the
6261 Best case ldr will always win. However, the more ldr instructions
6262 we issue, the less likely we are to be able to schedule them well.
6263 Using ldr instructions also increases code size.
6265 As a compromise, we use ldr for counts of 1 or 2 regs, and ldm
6266 for counts of 3 or 4 regs. */
6267 if (arm_tune_xscale && count <= 2 && ! optimize_size)
6273 for (i = 0; i < count; i++)
6275 addr = plus_constant (from, i * 4 * sign);
6276 mem = adjust_automodify_address (basemem, SImode, addr, offset);
6277 emit_move_insn (gen_rtx_REG (SImode, base_regno + i), mem);
6283 emit_move_insn (from, plus_constant (from, count * 4 * sign));
6293 result = gen_rtx_PARALLEL (VOIDmode,
6294 rtvec_alloc (count + (write_back ? 1 : 0)));
6297 XVECEXP (result, 0, 0)
6298 = gen_rtx_SET (VOIDmode, from, plus_constant (from, count * 4 * sign));
6303 for (j = 0; i < count; i++, j++)
6305 addr = plus_constant (from, j * 4 * sign);
6306 mem = adjust_automodify_address_nv (basemem, SImode, addr, offset);
6307 XVECEXP (result, 0, i)
6308 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, base_regno + j), mem);
6319 arm_gen_store_multiple (int base_regno, int count, rtx to, int up,
6320 int write_back, rtx basemem, HOST_WIDE_INT *offsetp)
6322 HOST_WIDE_INT offset = *offsetp;
6325 int sign = up ? 1 : -1;
6328 /* See arm_gen_load_multiple for discussion of
6329 the pros/cons of ldm/stm usage for XScale. */
6330 if (arm_tune_xscale && count <= 2 && ! optimize_size)
6336 for (i = 0; i < count; i++)
6338 addr = plus_constant (to, i * 4 * sign);
6339 mem = adjust_automodify_address (basemem, SImode, addr, offset);
6340 emit_move_insn (mem, gen_rtx_REG (SImode, base_regno + i));
6346 emit_move_insn (to, plus_constant (to, count * 4 * sign));
6356 result = gen_rtx_PARALLEL (VOIDmode,
6357 rtvec_alloc (count + (write_back ? 1 : 0)));
6360 XVECEXP (result, 0, 0)
6361 = gen_rtx_SET (VOIDmode, to,
6362 plus_constant (to, count * 4 * sign));
6367 for (j = 0; i < count; i++, j++)
6369 addr = plus_constant (to, j * 4 * sign);
6370 mem = adjust_automodify_address_nv (basemem, SImode, addr, offset);
6371 XVECEXP (result, 0, i)
6372 = gen_rtx_SET (VOIDmode, mem, gen_rtx_REG (SImode, base_regno + j));
6383 arm_gen_movmemqi (rtx *operands)
6385 HOST_WIDE_INT in_words_to_go, out_words_to_go, last_bytes;
6386 HOST_WIDE_INT srcoffset, dstoffset;
6388 rtx src, dst, srcbase, dstbase;
6389 rtx part_bytes_reg = NULL;
6392 if (GET_CODE (operands[2]) != CONST_INT
6393 || GET_CODE (operands[3]) != CONST_INT
6394 || INTVAL (operands[2]) > 64
6395 || INTVAL (operands[3]) & 3)
6398 dstbase = operands[0];
6399 srcbase = operands[1];
6401 dst = copy_to_mode_reg (SImode, XEXP (dstbase, 0));
6402 src = copy_to_mode_reg (SImode, XEXP (srcbase, 0));
6404 in_words_to_go = ARM_NUM_INTS (INTVAL (operands[2]));
6405 out_words_to_go = INTVAL (operands[2]) / 4;
6406 last_bytes = INTVAL (operands[2]) & 3;
6407 dstoffset = srcoffset = 0;
6409 if (out_words_to_go != in_words_to_go && ((in_words_to_go - 1) & 3) != 0)
6410 part_bytes_reg = gen_rtx_REG (SImode, (in_words_to_go - 1) & 3);
6412 for (i = 0; in_words_to_go >= 2; i+=4)
6414 if (in_words_to_go > 4)
6415 emit_insn (arm_gen_load_multiple (0, 4, src, TRUE, TRUE,
6416 srcbase, &srcoffset));
6418 emit_insn (arm_gen_load_multiple (0, in_words_to_go, src, TRUE,
6419 FALSE, srcbase, &srcoffset));
6421 if (out_words_to_go)
6423 if (out_words_to_go > 4)
6424 emit_insn (arm_gen_store_multiple (0, 4, dst, TRUE, TRUE,
6425 dstbase, &dstoffset));
6426 else if (out_words_to_go != 1)
6427 emit_insn (arm_gen_store_multiple (0, out_words_to_go,
6431 dstbase, &dstoffset));
6434 mem = adjust_automodify_address (dstbase, SImode, dst, dstoffset);
6435 emit_move_insn (mem, gen_rtx_REG (SImode, 0));
6436 if (last_bytes != 0)
6438 emit_insn (gen_addsi3 (dst, dst, GEN_INT (4)));
6444 in_words_to_go -= in_words_to_go < 4 ? in_words_to_go : 4;
6445 out_words_to_go -= out_words_to_go < 4 ? out_words_to_go : 4;
6448 /* OUT_WORDS_TO_GO will be zero here if there are byte stores to do. */
6449 if (out_words_to_go)
6453 mem = adjust_automodify_address (srcbase, SImode, src, srcoffset);
6454 sreg = copy_to_reg (mem);
6456 mem = adjust_automodify_address (dstbase, SImode, dst, dstoffset);
6457 emit_move_insn (mem, sreg);
6460 gcc_assert (!in_words_to_go); /* Sanity check */
6465 gcc_assert (in_words_to_go > 0);
6467 mem = adjust_automodify_address (srcbase, SImode, src, srcoffset);
6468 part_bytes_reg = copy_to_mode_reg (SImode, mem);
6471 gcc_assert (!last_bytes || part_bytes_reg);
6473 if (BYTES_BIG_ENDIAN && last_bytes)
6475 rtx tmp = gen_reg_rtx (SImode);
6477 /* The bytes we want are in the top end of the word. */
6478 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg,
6479 GEN_INT (8 * (4 - last_bytes))));
6480 part_bytes_reg = tmp;
6484 mem = adjust_automodify_address (dstbase, QImode,
6485 plus_constant (dst, last_bytes - 1),
6486 dstoffset + last_bytes - 1);
6487 emit_move_insn (mem, gen_lowpart (QImode, part_bytes_reg));
6491 tmp = gen_reg_rtx (SImode);
6492 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (8)));
6493 part_bytes_reg = tmp;
6502 mem = adjust_automodify_address (dstbase, HImode, dst, dstoffset);
6503 emit_move_insn (mem, gen_lowpart (HImode, part_bytes_reg));
6507 rtx tmp = gen_reg_rtx (SImode);
6508 emit_insn (gen_addsi3 (dst, dst, const2_rtx));
6509 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (16)));
6510 part_bytes_reg = tmp;
6517 mem = adjust_automodify_address (dstbase, QImode, dst, dstoffset);
6518 emit_move_insn (mem, gen_lowpart (QImode, part_bytes_reg));
6525 /* Select a dominance comparison mode if possible for a test of the general
6526 form (OP (COND_OR (X) (Y)) (const_int 0)). We support three forms.
6527 COND_OR == DOM_CC_X_AND_Y => (X && Y)
6528 COND_OR == DOM_CC_NX_OR_Y => ((! X) || Y)
6529 COND_OR == DOM_CC_X_OR_Y => (X || Y)
6530 In all cases OP will be either EQ or NE, but we don't need to know which
6531 here. If we are unable to support a dominance comparison we return
6532 CC mode. This will then fail to match for the RTL expressions that
6533 generate this call. */
6535 arm_select_dominance_cc_mode (rtx x, rtx y, HOST_WIDE_INT cond_or)
6537 enum rtx_code cond1, cond2;
6540 /* Currently we will probably get the wrong result if the individual
6541 comparisons are not simple. This also ensures that it is safe to
6542 reverse a comparison if necessary. */
6543 if ((arm_select_cc_mode (cond1 = GET_CODE (x), XEXP (x, 0), XEXP (x, 1))
6545 || (arm_select_cc_mode (cond2 = GET_CODE (y), XEXP (y, 0), XEXP (y, 1))
6549 /* The if_then_else variant of this tests the second condition if the
6550 first passes, but is true if the first fails. Reverse the first
6551 condition to get a true "inclusive-or" expression. */
6552 if (cond_or == DOM_CC_NX_OR_Y)
6553 cond1 = reverse_condition (cond1);
6555 /* If the comparisons are not equal, and one doesn't dominate the other,
6556 then we can't do this. */
6558 && !comparison_dominates_p (cond1, cond2)
6559 && (swapped = 1, !comparison_dominates_p (cond2, cond1)))
6564 enum rtx_code temp = cond1;
6572 if (cond_or == DOM_CC_X_AND_Y)
6577 case EQ: return CC_DEQmode;
6578 case LE: return CC_DLEmode;
6579 case LEU: return CC_DLEUmode;
6580 case GE: return CC_DGEmode;
6581 case GEU: return CC_DGEUmode;
6582 default: gcc_unreachable ();
6586 if (cond_or == DOM_CC_X_AND_Y)
6602 if (cond_or == DOM_CC_X_AND_Y)
6618 if (cond_or == DOM_CC_X_AND_Y)
6634 if (cond_or == DOM_CC_X_AND_Y)
6649 /* The remaining cases only occur when both comparisons are the
6652 gcc_assert (cond1 == cond2);
6656 gcc_assert (cond1 == cond2);
6660 gcc_assert (cond1 == cond2);
6664 gcc_assert (cond1 == cond2);
6668 gcc_assert (cond1 == cond2);
6677 arm_select_cc_mode (enum rtx_code op, rtx x, rtx y)
6679 /* All floating point compares return CCFP if it is an equality
6680 comparison, and CCFPE otherwise. */
6681 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
6701 if (TARGET_HARD_FLOAT && TARGET_MAVERICK)
6710 /* A compare with a shifted operand. Because of canonicalization, the
6711 comparison will have to be swapped when we emit the assembler. */
6712 if (GET_MODE (y) == SImode && GET_CODE (y) == REG
6713 && (GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
6714 || GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ROTATE
6715 || GET_CODE (x) == ROTATERT))
6718 /* This operation is performed swapped, but since we only rely on the Z
6719 flag we don't need an additional mode. */
6720 if (GET_MODE (y) == SImode && REG_P (y)
6721 && GET_CODE (x) == NEG
6722 && (op == EQ || op == NE))
6725 /* This is a special case that is used by combine to allow a
6726 comparison of a shifted byte load to be split into a zero-extend
6727 followed by a comparison of the shifted integer (only valid for
6728 equalities and unsigned inequalities). */
6729 if (GET_MODE (x) == SImode
6730 && GET_CODE (x) == ASHIFT
6731 && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 24
6732 && GET_CODE (XEXP (x, 0)) == SUBREG
6733 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == MEM
6734 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == QImode
6735 && (op == EQ || op == NE
6736 || op == GEU || op == GTU || op == LTU || op == LEU)
6737 && GET_CODE (y) == CONST_INT)
6740 /* A construct for a conditional compare, if the false arm contains
6741 0, then both conditions must be true, otherwise either condition
6742 must be true. Not all conditions are possible, so CCmode is
6743 returned if it can't be done. */
6744 if (GET_CODE (x) == IF_THEN_ELSE
6745 && (XEXP (x, 2) == const0_rtx
6746 || XEXP (x, 2) == const1_rtx)
6747 && COMPARISON_P (XEXP (x, 0))
6748 && COMPARISON_P (XEXP (x, 1)))
6749 return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
6750 INTVAL (XEXP (x, 2)));
6752 /* Alternate canonicalizations of the above. These are somewhat cleaner. */
6753 if (GET_CODE (x) == AND
6754 && COMPARISON_P (XEXP (x, 0))
6755 && COMPARISON_P (XEXP (x, 1)))
6756 return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
6759 if (GET_CODE (x) == IOR
6760 && COMPARISON_P (XEXP (x, 0))
6761 && COMPARISON_P (XEXP (x, 1)))
6762 return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
6765 /* An operation (on Thumb) where we want to test for a single bit.
6766 This is done by shifting that bit up into the top bit of a
6767 scratch register; we can then branch on the sign bit. */
6769 && GET_MODE (x) == SImode
6770 && (op == EQ || op == NE)
6771 && GET_CODE (x) == ZERO_EXTRACT
6772 && XEXP (x, 1) == const1_rtx)
6775 /* An operation that sets the condition codes as a side-effect, the
6776 V flag is not set correctly, so we can only use comparisons where
6777 this doesn't matter. (For LT and GE we can use "mi" and "pl"
6779 if (GET_MODE (x) == SImode
6781 && (op == EQ || op == NE || op == LT || op == GE)
6782 && (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS
6783 || GET_CODE (x) == AND || GET_CODE (x) == IOR
6784 || GET_CODE (x) == XOR || GET_CODE (x) == MULT
6785 || GET_CODE (x) == NOT || GET_CODE (x) == NEG
6786 || GET_CODE (x) == LSHIFTRT
6787 || GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
6788 || GET_CODE (x) == ROTATERT
6789 || (TARGET_ARM && GET_CODE (x) == ZERO_EXTRACT)))
6792 if (GET_MODE (x) == QImode && (op == EQ || op == NE))
6795 if (GET_MODE (x) == SImode && (op == LTU || op == GEU)
6796 && GET_CODE (x) == PLUS
6797 && (rtx_equal_p (XEXP (x, 0), y) || rtx_equal_p (XEXP (x, 1), y)))
6803 /* X and Y are two things to compare using CODE. Emit the compare insn and
6804 return the rtx for register 0 in the proper mode. FP means this is a
6805 floating point compare: I don't think that it is needed on the arm. */
6807 arm_gen_compare_reg (enum rtx_code code, rtx x, rtx y)
6809 enum machine_mode mode = SELECT_CC_MODE (code, x, y);
6810 rtx cc_reg = gen_rtx_REG (mode, CC_REGNUM);
6812 emit_set_insn (cc_reg, gen_rtx_COMPARE (mode, x, y));
6817 /* Generate a sequence of insns that will generate the correct return
6818 address mask depending on the physical architecture that the program
6821 arm_gen_return_addr_mask (void)
6823 rtx reg = gen_reg_rtx (Pmode);
6825 emit_insn (gen_return_addr_mask (reg));
6830 arm_reload_in_hi (rtx *operands)
6832 rtx ref = operands[1];
6834 HOST_WIDE_INT offset = 0;
6836 if (GET_CODE (ref) == SUBREG)
6838 offset = SUBREG_BYTE (ref);
6839 ref = SUBREG_REG (ref);
6842 if (GET_CODE (ref) == REG)
6844 /* We have a pseudo which has been spilt onto the stack; there
6845 are two cases here: the first where there is a simple
6846 stack-slot replacement and a second where the stack-slot is
6847 out of range, or is used as a subreg. */
6848 if (reg_equiv_mem[REGNO (ref)])
6850 ref = reg_equiv_mem[REGNO (ref)];
6851 base = find_replacement (&XEXP (ref, 0));
6854 /* The slot is out of range, or was dressed up in a SUBREG. */
6855 base = reg_equiv_address[REGNO (ref)];
6858 base = find_replacement (&XEXP (ref, 0));
6860 /* Handle the case where the address is too complex to be offset by 1. */
6861 if (GET_CODE (base) == MINUS
6862 || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT))
6864 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
6866 emit_set_insn (base_plus, base);
6869 else if (GET_CODE (base) == PLUS)
6871 /* The addend must be CONST_INT, or we would have dealt with it above. */
6872 HOST_WIDE_INT hi, lo;
6874 offset += INTVAL (XEXP (base, 1));
6875 base = XEXP (base, 0);
6877 /* Rework the address into a legal sequence of insns. */
6878 /* Valid range for lo is -4095 -> 4095 */
6881 : -((-offset) & 0xfff));
6883 /* Corner case, if lo is the max offset then we would be out of range
6884 once we have added the additional 1 below, so bump the msb into the
6885 pre-loading insn(s). */
6889 hi = ((((offset - lo) & (HOST_WIDE_INT) 0xffffffff)
6890 ^ (HOST_WIDE_INT) 0x80000000)
6891 - (HOST_WIDE_INT) 0x80000000);
6893 gcc_assert (hi + lo == offset);
6897 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
6899 /* Get the base address; addsi3 knows how to handle constants
6900 that require more than one insn. */
6901 emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi)));
6907 /* Operands[2] may overlap operands[0] (though it won't overlap
6908 operands[1]), that's why we asked for a DImode reg -- so we can
6909 use the bit that does not overlap. */
6910 if (REGNO (operands[2]) == REGNO (operands[0]))
6911 scratch = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
6913 scratch = gen_rtx_REG (SImode, REGNO (operands[2]));
6915 emit_insn (gen_zero_extendqisi2 (scratch,
6916 gen_rtx_MEM (QImode,
6917 plus_constant (base,
6919 emit_insn (gen_zero_extendqisi2 (gen_rtx_SUBREG (SImode, operands[0], 0),
6920 gen_rtx_MEM (QImode,
6921 plus_constant (base,
6923 if (!BYTES_BIG_ENDIAN)
6924 emit_set_insn (gen_rtx_SUBREG (SImode, operands[0], 0),
6925 gen_rtx_IOR (SImode,
6928 gen_rtx_SUBREG (SImode, operands[0], 0),
6932 emit_set_insn (gen_rtx_SUBREG (SImode, operands[0], 0),
6933 gen_rtx_IOR (SImode,
6934 gen_rtx_ASHIFT (SImode, scratch,
6936 gen_rtx_SUBREG (SImode, operands[0], 0)));
6939 /* Handle storing a half-word to memory during reload by synthesizing as two
6940 byte stores. Take care not to clobber the input values until after we
6941 have moved them somewhere safe. This code assumes that if the DImode
6942 scratch in operands[2] overlaps either the input value or output address
6943 in some way, then that value must die in this insn (we absolutely need
6944 two scratch registers for some corner cases). */
6946 arm_reload_out_hi (rtx *operands)
6948 rtx ref = operands[0];
6949 rtx outval = operands[1];
6951 HOST_WIDE_INT offset = 0;
6953 if (GET_CODE (ref) == SUBREG)
6955 offset = SUBREG_BYTE (ref);
6956 ref = SUBREG_REG (ref);
6959 if (GET_CODE (ref) == REG)
6961 /* We have a pseudo which has been spilt onto the stack; there
6962 are two cases here: the first where there is a simple
6963 stack-slot replacement and a second where the stack-slot is
6964 out of range, or is used as a subreg. */
6965 if (reg_equiv_mem[REGNO (ref)])
6967 ref = reg_equiv_mem[REGNO (ref)];
6968 base = find_replacement (&XEXP (ref, 0));
6971 /* The slot is out of range, or was dressed up in a SUBREG. */
6972 base = reg_equiv_address[REGNO (ref)];
6975 base = find_replacement (&XEXP (ref, 0));
6977 scratch = gen_rtx_REG (SImode, REGNO (operands[2]));
6979 /* Handle the case where the address is too complex to be offset by 1. */
6980 if (GET_CODE (base) == MINUS
6981 || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT))
6983 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
6985 /* Be careful not to destroy OUTVAL. */
6986 if (reg_overlap_mentioned_p (base_plus, outval))
6988 /* Updating base_plus might destroy outval, see if we can
6989 swap the scratch and base_plus. */
6990 if (!reg_overlap_mentioned_p (scratch, outval))
6993 scratch = base_plus;
6998 rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2]));
7000 /* Be conservative and copy OUTVAL into the scratch now,
7001 this should only be necessary if outval is a subreg
7002 of something larger than a word. */
7003 /* XXX Might this clobber base? I can't see how it can,
7004 since scratch is known to overlap with OUTVAL, and
7005 must be wider than a word. */
7006 emit_insn (gen_movhi (scratch_hi, outval));
7007 outval = scratch_hi;
7011 emit_set_insn (base_plus, base);
7014 else if (GET_CODE (base) == PLUS)
7016 /* The addend must be CONST_INT, or we would have dealt with it above. */
7017 HOST_WIDE_INT hi, lo;
7019 offset += INTVAL (XEXP (base, 1));
7020 base = XEXP (base, 0);
7022 /* Rework the address into a legal sequence of insns. */
7023 /* Valid range for lo is -4095 -> 4095 */
7026 : -((-offset) & 0xfff));
7028 /* Corner case, if lo is the max offset then we would be out of range
7029 once we have added the additional 1 below, so bump the msb into the
7030 pre-loading insn(s). */
7034 hi = ((((offset - lo) & (HOST_WIDE_INT) 0xffffffff)
7035 ^ (HOST_WIDE_INT) 0x80000000)
7036 - (HOST_WIDE_INT) 0x80000000);
7038 gcc_assert (hi + lo == offset);
7042 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
7044 /* Be careful not to destroy OUTVAL. */
7045 if (reg_overlap_mentioned_p (base_plus, outval))
7047 /* Updating base_plus might destroy outval, see if we
7048 can swap the scratch and base_plus. */
7049 if (!reg_overlap_mentioned_p (scratch, outval))
7052 scratch = base_plus;
7057 rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2]));
7059 /* Be conservative and copy outval into scratch now,
7060 this should only be necessary if outval is a
7061 subreg of something larger than a word. */
7062 /* XXX Might this clobber base? I can't see how it
7063 can, since scratch is known to overlap with
7065 emit_insn (gen_movhi (scratch_hi, outval));
7066 outval = scratch_hi;
7070 /* Get the base address; addsi3 knows how to handle constants
7071 that require more than one insn. */
7072 emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi)));
7078 if (BYTES_BIG_ENDIAN)
7080 emit_insn (gen_movqi (gen_rtx_MEM (QImode,
7081 plus_constant (base, offset + 1)),
7082 gen_lowpart (QImode, outval)));
7083 emit_insn (gen_lshrsi3 (scratch,
7084 gen_rtx_SUBREG (SImode, outval, 0),
7086 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),
7087 gen_lowpart (QImode, scratch)));
7091 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),
7092 gen_lowpart (QImode, outval)));
7093 emit_insn (gen_lshrsi3 (scratch,
7094 gen_rtx_SUBREG (SImode, outval, 0),
7096 emit_insn (gen_movqi (gen_rtx_MEM (QImode,
7097 plus_constant (base, offset + 1)),
7098 gen_lowpart (QImode, scratch)));
7102 /* Return true if a type must be passed in memory. For AAPCS, small aggregates
7103 (padded to the size of a word) should be passed in a register. */
7106 arm_must_pass_in_stack (enum machine_mode mode, tree type)
7108 if (TARGET_AAPCS_BASED)
7109 return must_pass_in_stack_var_size (mode, type);
7111 return must_pass_in_stack_var_size_or_pad (mode, type);
7115 /* For use by FUNCTION_ARG_PADDING (MODE, TYPE).
7116 Return true if an argument passed on the stack should be padded upwards,
7117 i.e. if the least-significant byte has useful data.
7118 For legacy APCS ABIs we use the default. For AAPCS based ABIs small
7119 aggregate types are placed in the lowest memory address. */
7122 arm_pad_arg_upward (enum machine_mode mode, tree type)
7124 if (!TARGET_AAPCS_BASED)
7125 return DEFAULT_FUNCTION_ARG_PADDING(mode, type) == upward;
7127 if (type && BYTES_BIG_ENDIAN && INTEGRAL_TYPE_P (type))
7134 /* Similarly, for use by BLOCK_REG_PADDING (MODE, TYPE, FIRST).
7135 For non-AAPCS, return !BYTES_BIG_ENDIAN if the least significant
7136 byte of the register has useful data, and return the opposite if the
7137 most significant byte does.
7138 For AAPCS, small aggregates and small complex types are always padded
7142 arm_pad_reg_upward (enum machine_mode mode ATTRIBUTE_UNUSED,
7143 tree type, int first ATTRIBUTE_UNUSED)
7145 if (TARGET_AAPCS_BASED
7147 && (AGGREGATE_TYPE_P (type) || TREE_CODE (type) == COMPLEX_TYPE)
7148 && int_size_in_bytes (type) <= 4)
7151 /* Otherwise, use default padding. */
7152 return !BYTES_BIG_ENDIAN;
7156 /* Print a symbolic form of X to the debug file, F. */
7158 arm_print_value (FILE *f, rtx x)
7160 switch (GET_CODE (x))
7163 fprintf (f, HOST_WIDE_INT_PRINT_HEX, INTVAL (x));
7167 fprintf (f, "<0x%lx,0x%lx>", (long)XWINT (x, 2), (long)XWINT (x, 3));
7175 for (i = 0; i < CONST_VECTOR_NUNITS (x); i++)
7177 fprintf (f, HOST_WIDE_INT_PRINT_HEX, INTVAL (CONST_VECTOR_ELT (x, i)));
7178 if (i < (CONST_VECTOR_NUNITS (x) - 1))
7186 fprintf (f, "\"%s\"", XSTR (x, 0));
7190 fprintf (f, "`%s'", XSTR (x, 0));
7194 fprintf (f, "L%d", INSN_UID (XEXP (x, 0)));
7198 arm_print_value (f, XEXP (x, 0));
7202 arm_print_value (f, XEXP (x, 0));
7204 arm_print_value (f, XEXP (x, 1));
7212 fprintf (f, "????");
7217 /* Routines for manipulation of the constant pool. */
7219 /* Arm instructions cannot load a large constant directly into a
7220 register; they have to come from a pc relative load. The constant
7221 must therefore be placed in the addressable range of the pc
7222 relative load. Depending on the precise pc relative load
7223 instruction the range is somewhere between 256 bytes and 4k. This
7224 means that we often have to dump a constant inside a function, and
7225 generate code to branch around it.
7227 It is important to minimize this, since the branches will slow
7228 things down and make the code larger.
7230 Normally we can hide the table after an existing unconditional
7231 branch so that there is no interruption of the flow, but in the
7232 worst case the code looks like this:
7250 We fix this by performing a scan after scheduling, which notices
7251 which instructions need to have their operands fetched from the
7252 constant table and builds the table.
7254 The algorithm starts by building a table of all the constants that
7255 need fixing up and all the natural barriers in the function (places
7256 where a constant table can be dropped without breaking the flow).
7257 For each fixup we note how far the pc-relative replacement will be
7258 able to reach and the offset of the instruction into the function.
7260 Having built the table we then group the fixes together to form
7261 tables that are as large as possible (subject to addressing
7262 constraints) and emit each table of constants after the last
7263 barrier that is within range of all the instructions in the group.
7264 If a group does not contain a barrier, then we forcibly create one
7265 by inserting a jump instruction into the flow. Once the table has
7266 been inserted, the insns are then modified to reference the
7267 relevant entry in the pool.
7269 Possible enhancements to the algorithm (not implemented) are:
7271 1) For some processors and object formats, there may be benefit in
7272 aligning the pools to the start of cache lines; this alignment
7273 would need to be taken into account when calculating addressability
7276 /* These typedefs are located at the start of this file, so that
7277 they can be used in the prototypes there. This comment is to
7278 remind readers of that fact so that the following structures
7279 can be understood more easily.
7281 typedef struct minipool_node Mnode;
7282 typedef struct minipool_fixup Mfix; */
7284 struct minipool_node
7286 /* Doubly linked chain of entries. */
7289 /* The maximum offset into the code that this entry can be placed. While
7290 pushing fixes for forward references, all entries are sorted in order
7291 of increasing max_address. */
7292 HOST_WIDE_INT max_address;
7293 /* Similarly for an entry inserted for a backwards ref. */
7294 HOST_WIDE_INT min_address;
7295 /* The number of fixes referencing this entry. This can become zero
7296 if we "unpush" an entry. In this case we ignore the entry when we
7297 come to emit the code. */
7299 /* The offset from the start of the minipool. */
7300 HOST_WIDE_INT offset;
7301 /* The value in table. */
7303 /* The mode of value. */
7304 enum machine_mode mode;
7305 /* The size of the value. With iWMMXt enabled
7306 sizes > 4 also imply an alignment of 8-bytes. */
7310 struct minipool_fixup
7314 HOST_WIDE_INT address;
7316 enum machine_mode mode;
7320 HOST_WIDE_INT forwards;
7321 HOST_WIDE_INT backwards;
7324 /* Fixes less than a word need padding out to a word boundary. */
7325 #define MINIPOOL_FIX_SIZE(mode) \
7326 (GET_MODE_SIZE ((mode)) >= 4 ? GET_MODE_SIZE ((mode)) : 4)
7328 static Mnode * minipool_vector_head;
7329 static Mnode * minipool_vector_tail;
7330 static rtx minipool_vector_label;
7331 static int minipool_pad;
7333 /* The linked list of all minipool fixes required for this function. */
7334 Mfix * minipool_fix_head;
7335 Mfix * minipool_fix_tail;
7336 /* The fix entry for the current minipool, once it has been placed. */
7337 Mfix * minipool_barrier;
7339 /* Determines if INSN is the start of a jump table. Returns the end
7340 of the TABLE or NULL_RTX. */
7342 is_jump_table (rtx insn)
7346 if (GET_CODE (insn) == JUMP_INSN
7347 && JUMP_LABEL (insn) != NULL
7348 && ((table = next_real_insn (JUMP_LABEL (insn)))
7349 == next_real_insn (insn))
7351 && GET_CODE (table) == JUMP_INSN
7352 && (GET_CODE (PATTERN (table)) == ADDR_VEC
7353 || GET_CODE (PATTERN (table)) == ADDR_DIFF_VEC))
7359 #ifndef JUMP_TABLES_IN_TEXT_SECTION
7360 #define JUMP_TABLES_IN_TEXT_SECTION 0
7363 static HOST_WIDE_INT
7364 get_jump_table_size (rtx insn)
7366 /* ADDR_VECs only take room if read-only data does into the text
7368 if (JUMP_TABLES_IN_TEXT_SECTION || readonly_data_section == text_section)
7370 rtx body = PATTERN (insn);
7371 int elt = GET_CODE (body) == ADDR_DIFF_VEC ? 1 : 0;
7373 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, elt);
7379 /* Move a minipool fix MP from its current location to before MAX_MP.
7380 If MAX_MP is NULL, then MP doesn't need moving, but the addressing
7381 constraints may need updating. */
7383 move_minipool_fix_forward_ref (Mnode *mp, Mnode *max_mp,
7384 HOST_WIDE_INT max_address)
7386 /* The code below assumes these are different. */
7387 gcc_assert (mp != max_mp);
7391 if (max_address < mp->max_address)
7392 mp->max_address = max_address;
7396 if (max_address > max_mp->max_address - mp->fix_size)
7397 mp->max_address = max_mp->max_address - mp->fix_size;
7399 mp->max_address = max_address;
7401 /* Unlink MP from its current position. Since max_mp is non-null,
7402 mp->prev must be non-null. */
7403 mp->prev->next = mp->next;
7404 if (mp->next != NULL)
7405 mp->next->prev = mp->prev;
7407 minipool_vector_tail = mp->prev;
7409 /* Re-insert it before MAX_MP. */
7411 mp->prev = max_mp->prev;
7414 if (mp->prev != NULL)
7415 mp->prev->next = mp;
7417 minipool_vector_head = mp;
7420 /* Save the new entry. */
7423 /* Scan over the preceding entries and adjust their addresses as
7425 while (mp->prev != NULL
7426 && mp->prev->max_address > mp->max_address - mp->prev->fix_size)
7428 mp->prev->max_address = mp->max_address - mp->prev->fix_size;
7435 /* Add a constant to the minipool for a forward reference. Returns the
7436 node added or NULL if the constant will not fit in this pool. */
7438 add_minipool_forward_ref (Mfix *fix)
7440 /* If set, max_mp is the first pool_entry that has a lower
7441 constraint than the one we are trying to add. */
7442 Mnode * max_mp = NULL;
7443 HOST_WIDE_INT max_address = fix->address + fix->forwards - minipool_pad;
7446 /* If the minipool starts before the end of FIX->INSN then this FIX
7447 can not be placed into the current pool. Furthermore, adding the
7448 new constant pool entry may cause the pool to start FIX_SIZE bytes
7450 if (minipool_vector_head &&
7451 (fix->address + get_attr_length (fix->insn)
7452 >= minipool_vector_head->max_address - fix->fix_size))
7455 /* Scan the pool to see if a constant with the same value has
7456 already been added. While we are doing this, also note the
7457 location where we must insert the constant if it doesn't already
7459 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
7461 if (GET_CODE (fix->value) == GET_CODE (mp->value)
7462 && fix->mode == mp->mode
7463 && (GET_CODE (fix->value) != CODE_LABEL
7464 || (CODE_LABEL_NUMBER (fix->value)
7465 == CODE_LABEL_NUMBER (mp->value)))
7466 && rtx_equal_p (fix->value, mp->value))
7468 /* More than one fix references this entry. */
7470 return move_minipool_fix_forward_ref (mp, max_mp, max_address);
7473 /* Note the insertion point if necessary. */
7475 && mp->max_address > max_address)
7478 /* If we are inserting an 8-bytes aligned quantity and
7479 we have not already found an insertion point, then
7480 make sure that all such 8-byte aligned quantities are
7481 placed at the start of the pool. */
7482 if (ARM_DOUBLEWORD_ALIGN
7484 && fix->fix_size == 8
7485 && mp->fix_size != 8)
7488 max_address = mp->max_address;
7492 /* The value is not currently in the minipool, so we need to create
7493 a new entry for it. If MAX_MP is NULL, the entry will be put on
7494 the end of the list since the placement is less constrained than
7495 any existing entry. Otherwise, we insert the new fix before
7496 MAX_MP and, if necessary, adjust the constraints on the other
7499 mp->fix_size = fix->fix_size;
7500 mp->mode = fix->mode;
7501 mp->value = fix->value;
7503 /* Not yet required for a backwards ref. */
7504 mp->min_address = -65536;
7508 mp->max_address = max_address;
7510 mp->prev = minipool_vector_tail;
7512 if (mp->prev == NULL)
7514 minipool_vector_head = mp;
7515 minipool_vector_label = gen_label_rtx ();
7518 mp->prev->next = mp;
7520 minipool_vector_tail = mp;
7524 if (max_address > max_mp->max_address - mp->fix_size)
7525 mp->max_address = max_mp->max_address - mp->fix_size;
7527 mp->max_address = max_address;
7530 mp->prev = max_mp->prev;
7532 if (mp->prev != NULL)
7533 mp->prev->next = mp;
7535 minipool_vector_head = mp;
7538 /* Save the new entry. */
7541 /* Scan over the preceding entries and adjust their addresses as
7543 while (mp->prev != NULL
7544 && mp->prev->max_address > mp->max_address - mp->prev->fix_size)
7546 mp->prev->max_address = mp->max_address - mp->prev->fix_size;
7554 move_minipool_fix_backward_ref (Mnode *mp, Mnode *min_mp,
7555 HOST_WIDE_INT min_address)
7557 HOST_WIDE_INT offset;
7559 /* The code below assumes these are different. */
7560 gcc_assert (mp != min_mp);
7564 if (min_address > mp->min_address)
7565 mp->min_address = min_address;
7569 /* We will adjust this below if it is too loose. */
7570 mp->min_address = min_address;
7572 /* Unlink MP from its current position. Since min_mp is non-null,
7573 mp->next must be non-null. */
7574 mp->next->prev = mp->prev;
7575 if (mp->prev != NULL)
7576 mp->prev->next = mp->next;
7578 minipool_vector_head = mp->next;
7580 /* Reinsert it after MIN_MP. */
7582 mp->next = min_mp->next;
7584 if (mp->next != NULL)
7585 mp->next->prev = mp;
7587 minipool_vector_tail = mp;
7593 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
7595 mp->offset = offset;
7596 if (mp->refcount > 0)
7597 offset += mp->fix_size;
7599 if (mp->next && mp->next->min_address < mp->min_address + mp->fix_size)
7600 mp->next->min_address = mp->min_address + mp->fix_size;
7606 /* Add a constant to the minipool for a backward reference. Returns the
7607 node added or NULL if the constant will not fit in this pool.
7609 Note that the code for insertion for a backwards reference can be
7610 somewhat confusing because the calculated offsets for each fix do
7611 not take into account the size of the pool (which is still under
7614 add_minipool_backward_ref (Mfix *fix)
7616 /* If set, min_mp is the last pool_entry that has a lower constraint
7617 than the one we are trying to add. */
7618 Mnode *min_mp = NULL;
7619 /* This can be negative, since it is only a constraint. */
7620 HOST_WIDE_INT min_address = fix->address - fix->backwards;
7623 /* If we can't reach the current pool from this insn, or if we can't
7624 insert this entry at the end of the pool without pushing other
7625 fixes out of range, then we don't try. This ensures that we
7626 can't fail later on. */
7627 if (min_address >= minipool_barrier->address
7628 || (minipool_vector_tail->min_address + fix->fix_size
7629 >= minipool_barrier->address))
7632 /* Scan the pool to see if a constant with the same value has
7633 already been added. While we are doing this, also note the
7634 location where we must insert the constant if it doesn't already
7636 for (mp = minipool_vector_tail; mp != NULL; mp = mp->prev)
7638 if (GET_CODE (fix->value) == GET_CODE (mp->value)
7639 && fix->mode == mp->mode
7640 && (GET_CODE (fix->value) != CODE_LABEL
7641 || (CODE_LABEL_NUMBER (fix->value)
7642 == CODE_LABEL_NUMBER (mp->value)))
7643 && rtx_equal_p (fix->value, mp->value)
7644 /* Check that there is enough slack to move this entry to the
7645 end of the table (this is conservative). */
7647 > (minipool_barrier->address
7648 + minipool_vector_tail->offset
7649 + minipool_vector_tail->fix_size)))
7652 return move_minipool_fix_backward_ref (mp, min_mp, min_address);
7656 mp->min_address += fix->fix_size;
7659 /* Note the insertion point if necessary. */
7660 if (mp->min_address < min_address)
7662 /* For now, we do not allow the insertion of 8-byte alignment
7663 requiring nodes anywhere but at the start of the pool. */
7664 if (ARM_DOUBLEWORD_ALIGN
7665 && fix->fix_size == 8 && mp->fix_size != 8)
7670 else if (mp->max_address
7671 < minipool_barrier->address + mp->offset + fix->fix_size)
7673 /* Inserting before this entry would push the fix beyond
7674 its maximum address (which can happen if we have
7675 re-located a forwards fix); force the new fix to come
7678 min_address = mp->min_address + fix->fix_size;
7680 /* If we are inserting an 8-bytes aligned quantity and
7681 we have not already found an insertion point, then
7682 make sure that all such 8-byte aligned quantities are
7683 placed at the start of the pool. */
7684 else if (ARM_DOUBLEWORD_ALIGN
7686 && fix->fix_size == 8
7687 && mp->fix_size < 8)
7690 min_address = mp->min_address + fix->fix_size;
7695 /* We need to create a new entry. */
7697 mp->fix_size = fix->fix_size;
7698 mp->mode = fix->mode;
7699 mp->value = fix->value;
7701 mp->max_address = minipool_barrier->address + 65536;
7703 mp->min_address = min_address;
7708 mp->next = minipool_vector_head;
7710 if (mp->next == NULL)
7712 minipool_vector_tail = mp;
7713 minipool_vector_label = gen_label_rtx ();
7716 mp->next->prev = mp;
7718 minipool_vector_head = mp;
7722 mp->next = min_mp->next;
7726 if (mp->next != NULL)
7727 mp->next->prev = mp;
7729 minipool_vector_tail = mp;
7732 /* Save the new entry. */
7740 /* Scan over the following entries and adjust their offsets. */
7741 while (mp->next != NULL)
7743 if (mp->next->min_address < mp->min_address + mp->fix_size)
7744 mp->next->min_address = mp->min_address + mp->fix_size;
7747 mp->next->offset = mp->offset + mp->fix_size;
7749 mp->next->offset = mp->offset;
7758 assign_minipool_offsets (Mfix *barrier)
7760 HOST_WIDE_INT offset = 0;
7763 minipool_barrier = barrier;
7765 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
7767 mp->offset = offset;
7769 if (mp->refcount > 0)
7770 offset += mp->fix_size;
7774 /* Output the literal table */
7776 dump_minipool (rtx scan)
7782 if (ARM_DOUBLEWORD_ALIGN)
7783 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
7784 if (mp->refcount > 0 && mp->fix_size == 8)
7792 ";; Emitting minipool after insn %u; address %ld; align %d (bytes)\n",
7793 INSN_UID (scan), (unsigned long) minipool_barrier->address, align64 ? 8 : 4);
7795 scan = emit_label_after (gen_label_rtx (), scan);
7796 scan = emit_insn_after (align64 ? gen_align_8 () : gen_align_4 (), scan);
7797 scan = emit_label_after (minipool_vector_label, scan);
7799 for (mp = minipool_vector_head; mp != NULL; mp = nmp)
7801 if (mp->refcount > 0)
7806 ";; Offset %u, min %ld, max %ld ",
7807 (unsigned) mp->offset, (unsigned long) mp->min_address,
7808 (unsigned long) mp->max_address);
7809 arm_print_value (dump_file, mp->value);
7810 fputc ('\n', dump_file);
7813 switch (mp->fix_size)
7815 #ifdef HAVE_consttable_1
7817 scan = emit_insn_after (gen_consttable_1 (mp->value), scan);
7821 #ifdef HAVE_consttable_2
7823 scan = emit_insn_after (gen_consttable_2 (mp->value), scan);
7827 #ifdef HAVE_consttable_4
7829 scan = emit_insn_after (gen_consttable_4 (mp->value), scan);
7833 #ifdef HAVE_consttable_8
7835 scan = emit_insn_after (gen_consttable_8 (mp->value), scan);
7848 minipool_vector_head = minipool_vector_tail = NULL;
7849 scan = emit_insn_after (gen_consttable_end (), scan);
7850 scan = emit_barrier_after (scan);
7853 /* Return the cost of forcibly inserting a barrier after INSN. */
7855 arm_barrier_cost (rtx insn)
7857 /* Basing the location of the pool on the loop depth is preferable,
7858 but at the moment, the basic block information seems to be
7859 corrupt by this stage of the compilation. */
7861 rtx next = next_nonnote_insn (insn);
7863 if (next != NULL && GET_CODE (next) == CODE_LABEL)
7866 switch (GET_CODE (insn))
7869 /* It will always be better to place the table before the label, rather
7878 return base_cost - 10;
7881 return base_cost + 10;
7885 /* Find the best place in the insn stream in the range
7886 (FIX->address,MAX_ADDRESS) to forcibly insert a minipool barrier.
7887 Create the barrier by inserting a jump and add a new fix entry for
7890 create_fix_barrier (Mfix *fix, HOST_WIDE_INT max_address)
7892 HOST_WIDE_INT count = 0;
7894 rtx from = fix->insn;
7895 /* The instruction after which we will insert the jump. */
7896 rtx selected = NULL;
7898 /* The address at which the jump instruction will be placed. */
7899 HOST_WIDE_INT selected_address;
7901 HOST_WIDE_INT max_count = max_address - fix->address;
7902 rtx label = gen_label_rtx ();
7904 selected_cost = arm_barrier_cost (from);
7905 selected_address = fix->address;
7907 while (from && count < max_count)
7912 /* This code shouldn't have been called if there was a natural barrier
7914 gcc_assert (GET_CODE (from) != BARRIER);
7916 /* Count the length of this insn. */
7917 count += get_attr_length (from);
7919 /* If there is a jump table, add its length. */
7920 tmp = is_jump_table (from);
7923 count += get_jump_table_size (tmp);
7925 /* Jump tables aren't in a basic block, so base the cost on
7926 the dispatch insn. If we select this location, we will
7927 still put the pool after the table. */
7928 new_cost = arm_barrier_cost (from);
7930 if (count < max_count
7931 && (!selected || new_cost <= selected_cost))
7934 selected_cost = new_cost;
7935 selected_address = fix->address + count;
7938 /* Continue after the dispatch table. */
7939 from = NEXT_INSN (tmp);
7943 new_cost = arm_barrier_cost (from);
7945 if (count < max_count
7946 && (!selected || new_cost <= selected_cost))
7949 selected_cost = new_cost;
7950 selected_address = fix->address + count;
7953 from = NEXT_INSN (from);
7956 /* Make sure that we found a place to insert the jump. */
7957 gcc_assert (selected);
7959 /* Create a new JUMP_INSN that branches around a barrier. */
7960 from = emit_jump_insn_after (gen_jump (label), selected);
7961 JUMP_LABEL (from) = label;
7962 barrier = emit_barrier_after (from);
7963 emit_label_after (label, barrier);
7965 /* Create a minipool barrier entry for the new barrier. */
7966 new_fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* new_fix));
7967 new_fix->insn = barrier;
7968 new_fix->address = selected_address;
7969 new_fix->next = fix->next;
7970 fix->next = new_fix;
7975 /* Record that there is a natural barrier in the insn stream at
7978 push_minipool_barrier (rtx insn, HOST_WIDE_INT address)
7980 Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix));
7983 fix->address = address;
7986 if (minipool_fix_head != NULL)
7987 minipool_fix_tail->next = fix;
7989 minipool_fix_head = fix;
7991 minipool_fix_tail = fix;
7994 /* Record INSN, which will need fixing up to load a value from the
7995 minipool. ADDRESS is the offset of the insn since the start of the
7996 function; LOC is a pointer to the part of the insn which requires
7997 fixing; VALUE is the constant that must be loaded, which is of type
8000 push_minipool_fix (rtx insn, HOST_WIDE_INT address, rtx *loc,
8001 enum machine_mode mode, rtx value)
8003 Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix));
8005 #ifdef AOF_ASSEMBLER
8006 /* PIC symbol references need to be converted into offsets into the
8008 /* XXX This shouldn't be done here. */
8009 if (flag_pic && GET_CODE (value) == SYMBOL_REF)
8010 value = aof_pic_entry (value);
8011 #endif /* AOF_ASSEMBLER */
8014 fix->address = address;
8017 fix->fix_size = MINIPOOL_FIX_SIZE (mode);
8019 fix->forwards = get_attr_pool_range (insn);
8020 fix->backwards = get_attr_neg_pool_range (insn);
8021 fix->minipool = NULL;
8023 /* If an insn doesn't have a range defined for it, then it isn't
8024 expecting to be reworked by this code. Better to stop now than
8025 to generate duff assembly code. */
8026 gcc_assert (fix->forwards || fix->backwards);
8028 /* If an entry requires 8-byte alignment then assume all constant pools
8029 require 4 bytes of padding. Trying to do this later on a per-pool
8030 basis is awkward because existing pool entries have to be modified. */
8031 if (ARM_DOUBLEWORD_ALIGN && fix->fix_size == 8)
8037 ";; %smode fixup for i%d; addr %lu, range (%ld,%ld): ",
8038 GET_MODE_NAME (mode),
8039 INSN_UID (insn), (unsigned long) address,
8040 -1 * (long)fix->backwards, (long)fix->forwards);
8041 arm_print_value (dump_file, fix->value);
8042 fprintf (dump_file, "\n");
8045 /* Add it to the chain of fixes. */
8048 if (minipool_fix_head != NULL)
8049 minipool_fix_tail->next = fix;
8051 minipool_fix_head = fix;
8053 minipool_fix_tail = fix;
8056 /* Return the cost of synthesizing a 64-bit constant VAL inline.
8057 Returns the number of insns needed, or 99 if we don't know how to
8060 arm_const_double_inline_cost (rtx val)
8062 rtx lowpart, highpart;
8063 enum machine_mode mode;
8065 mode = GET_MODE (val);
8067 if (mode == VOIDmode)
8070 gcc_assert (GET_MODE_SIZE (mode) == 8);
8072 lowpart = gen_lowpart (SImode, val);
8073 highpart = gen_highpart_mode (SImode, mode, val);
8075 gcc_assert (GET_CODE (lowpart) == CONST_INT);
8076 gcc_assert (GET_CODE (highpart) == CONST_INT);
8078 return (arm_gen_constant (SET, SImode, NULL_RTX, INTVAL (lowpart),
8079 NULL_RTX, NULL_RTX, 0, 0)
8080 + arm_gen_constant (SET, SImode, NULL_RTX, INTVAL (highpart),
8081 NULL_RTX, NULL_RTX, 0, 0));
8084 /* Return true if it is worthwhile to split a 64-bit constant into two
8085 32-bit operations. This is the case if optimizing for size, or
8086 if we have load delay slots, or if one 32-bit part can be done with
8087 a single data operation. */
8089 arm_const_double_by_parts (rtx val)
8091 enum machine_mode mode = GET_MODE (val);
8094 if (optimize_size || arm_ld_sched)
8097 if (mode == VOIDmode)
8100 part = gen_highpart_mode (SImode, mode, val);
8102 gcc_assert (GET_CODE (part) == CONST_INT);
8104 if (const_ok_for_arm (INTVAL (part))
8105 || const_ok_for_arm (~INTVAL (part)))
8108 part = gen_lowpart (SImode, val);
8110 gcc_assert (GET_CODE (part) == CONST_INT);
8112 if (const_ok_for_arm (INTVAL (part))
8113 || const_ok_for_arm (~INTVAL (part)))
8119 /* Scan INSN and note any of its operands that need fixing.
8120 If DO_PUSHES is false we do not actually push any of the fixups
8121 needed. The function returns TRUE if any fixups were needed/pushed.
8122 This is used by arm_memory_load_p() which needs to know about loads
8123 of constants that will be converted into minipool loads. */
8125 note_invalid_constants (rtx insn, HOST_WIDE_INT address, int do_pushes)
8127 bool result = false;
8130 extract_insn (insn);
8132 if (!constrain_operands (1))
8133 fatal_insn_not_found (insn);
8135 if (recog_data.n_alternatives == 0)
8138 /* Fill in recog_op_alt with information about the constraints of
8140 preprocess_constraints ();
8142 for (opno = 0; opno < recog_data.n_operands; opno++)
8144 /* Things we need to fix can only occur in inputs. */
8145 if (recog_data.operand_type[opno] != OP_IN)
8148 /* If this alternative is a memory reference, then any mention
8149 of constants in this alternative is really to fool reload
8150 into allowing us to accept one there. We need to fix them up
8151 now so that we output the right code. */
8152 if (recog_op_alt[opno][which_alternative].memory_ok)
8154 rtx op = recog_data.operand[opno];
8156 if (CONSTANT_P (op))
8159 push_minipool_fix (insn, address, recog_data.operand_loc[opno],
8160 recog_data.operand_mode[opno], op);
8163 else if (GET_CODE (op) == MEM
8164 && GET_CODE (XEXP (op, 0)) == SYMBOL_REF
8165 && CONSTANT_POOL_ADDRESS_P (XEXP (op, 0)))
8169 rtx cop = avoid_constant_pool_reference (op);
8171 /* Casting the address of something to a mode narrower
8172 than a word can cause avoid_constant_pool_reference()
8173 to return the pool reference itself. That's no good to
8174 us here. Lets just hope that we can use the
8175 constant pool value directly. */
8177 cop = get_pool_constant (XEXP (op, 0));
8179 push_minipool_fix (insn, address,
8180 recog_data.operand_loc[opno],
8181 recog_data.operand_mode[opno], cop);
8192 /* Gcc puts the pool in the wrong place for ARM, since we can only
8193 load addresses a limited distance around the pc. We do some
8194 special munging to move the constant pool values to the correct
8195 point in the code. */
8200 HOST_WIDE_INT address = 0;
8203 minipool_fix_head = minipool_fix_tail = NULL;
8205 /* The first insn must always be a note, or the code below won't
8206 scan it properly. */
8207 insn = get_insns ();
8208 gcc_assert (GET_CODE (insn) == NOTE);
8211 /* Scan all the insns and record the operands that will need fixing. */
8212 for (insn = next_nonnote_insn (insn); insn; insn = next_nonnote_insn (insn))
8214 if (TARGET_CIRRUS_FIX_INVALID_INSNS
8215 && (arm_cirrus_insn_p (insn)
8216 || GET_CODE (insn) == JUMP_INSN
8217 || arm_memory_load_p (insn)))
8218 cirrus_reorg (insn);
8220 if (GET_CODE (insn) == BARRIER)
8221 push_minipool_barrier (insn, address);
8222 else if (INSN_P (insn))
8226 note_invalid_constants (insn, address, true);
8227 address += get_attr_length (insn);
8229 /* If the insn is a vector jump, add the size of the table
8230 and skip the table. */
8231 if ((table = is_jump_table (insn)) != NULL)
8233 address += get_jump_table_size (table);
8239 fix = minipool_fix_head;
8241 /* Now scan the fixups and perform the required changes. */
8246 Mfix * last_added_fix;
8247 Mfix * last_barrier = NULL;
8250 /* Skip any further barriers before the next fix. */
8251 while (fix && GET_CODE (fix->insn) == BARRIER)
8254 /* No more fixes. */
8258 last_added_fix = NULL;
8260 for (ftmp = fix; ftmp; ftmp = ftmp->next)
8262 if (GET_CODE (ftmp->insn) == BARRIER)
8264 if (ftmp->address >= minipool_vector_head->max_address)
8267 last_barrier = ftmp;
8269 else if ((ftmp->minipool = add_minipool_forward_ref (ftmp)) == NULL)
8272 last_added_fix = ftmp; /* Keep track of the last fix added. */
8275 /* If we found a barrier, drop back to that; any fixes that we
8276 could have reached but come after the barrier will now go in
8277 the next mini-pool. */
8278 if (last_barrier != NULL)
8280 /* Reduce the refcount for those fixes that won't go into this
8282 for (fdel = last_barrier->next;
8283 fdel && fdel != ftmp;
8286 fdel->minipool->refcount--;
8287 fdel->minipool = NULL;
8290 ftmp = last_barrier;
8294 /* ftmp is first fix that we can't fit into this pool and
8295 there no natural barriers that we could use. Insert a
8296 new barrier in the code somewhere between the previous
8297 fix and this one, and arrange to jump around it. */
8298 HOST_WIDE_INT max_address;
8300 /* The last item on the list of fixes must be a barrier, so
8301 we can never run off the end of the list of fixes without
8302 last_barrier being set. */
8305 max_address = minipool_vector_head->max_address;
8306 /* Check that there isn't another fix that is in range that
8307 we couldn't fit into this pool because the pool was
8308 already too large: we need to put the pool before such an
8309 instruction. The pool itself may come just after the
8310 fix because create_fix_barrier also allows space for a
8311 jump instruction. */
8312 if (ftmp->address < max_address)
8313 max_address = ftmp->address + 1;
8315 last_barrier = create_fix_barrier (last_added_fix, max_address);
8318 assign_minipool_offsets (last_barrier);
8322 if (GET_CODE (ftmp->insn) != BARRIER
8323 && ((ftmp->minipool = add_minipool_backward_ref (ftmp))
8330 /* Scan over the fixes we have identified for this pool, fixing them
8331 up and adding the constants to the pool itself. */
8332 for (this_fix = fix; this_fix && ftmp != this_fix;
8333 this_fix = this_fix->next)
8334 if (GET_CODE (this_fix->insn) != BARRIER)
8337 = plus_constant (gen_rtx_LABEL_REF (VOIDmode,
8338 minipool_vector_label),
8339 this_fix->minipool->offset);
8340 *this_fix->loc = gen_rtx_MEM (this_fix->mode, addr);
8343 dump_minipool (last_barrier->insn);
8347 /* From now on we must synthesize any constants that we can't handle
8348 directly. This can happen if the RTL gets split during final
8349 instruction generation. */
8350 after_arm_reorg = 1;
8352 /* Free the minipool memory. */
8353 obstack_free (&minipool_obstack, minipool_startobj);
8356 /* Routines to output assembly language. */
8358 /* If the rtx is the correct value then return the string of the number.
8359 In this way we can ensure that valid double constants are generated even
8360 when cross compiling. */
8362 fp_immediate_constant (rtx x)
8367 if (!fp_consts_inited)
8370 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
8371 for (i = 0; i < 8; i++)
8372 if (REAL_VALUES_EQUAL (r, values_fp[i]))
8373 return strings_fp[i];
8378 /* As for fp_immediate_constant, but value is passed directly, not in rtx. */
8380 fp_const_from_val (REAL_VALUE_TYPE *r)
8384 if (!fp_consts_inited)
8387 for (i = 0; i < 8; i++)
8388 if (REAL_VALUES_EQUAL (*r, values_fp[i]))
8389 return strings_fp[i];
8394 /* Output the operands of a LDM/STM instruction to STREAM.
8395 MASK is the ARM register set mask of which only bits 0-15 are important.
8396 REG is the base register, either the frame pointer or the stack pointer,
8397 INSTR is the possibly suffixed load or store instruction. */
8400 print_multi_reg (FILE *stream, const char *instr, unsigned reg,
8404 bool not_first = FALSE;
8406 fputc ('\t', stream);
8407 asm_fprintf (stream, instr, reg);
8408 fputs (", {", stream);
8410 for (i = 0; i <= LAST_ARM_REGNUM; i++)
8411 if (mask & (1 << i))
8414 fprintf (stream, ", ");
8416 asm_fprintf (stream, "%r", i);
8420 fprintf (stream, "}\n");
8424 /* Output a FLDMX instruction to STREAM.
8425 BASE if the register containing the address.
8426 REG and COUNT specify the register range.
8427 Extra registers may be added to avoid hardware bugs. */
8430 arm_output_fldmx (FILE * stream, unsigned int base, int reg, int count)
8434 /* Workaround ARM10 VFPr1 bug. */
8435 if (count == 2 && !arm_arch6)
8442 fputc ('\t', stream);
8443 asm_fprintf (stream, "fldmfdx\t%r!, {", base);
8445 for (i = reg; i < reg + count; i++)
8448 fputs (", ", stream);
8449 asm_fprintf (stream, "d%d", i);
8451 fputs ("}\n", stream);
8456 /* Output the assembly for a store multiple. */
8459 vfp_output_fstmx (rtx * operands)
8466 strcpy (pattern, "fstmfdx\t%m0!, {%P1");
8467 p = strlen (pattern);
8469 gcc_assert (GET_CODE (operands[1]) == REG);
8471 base = (REGNO (operands[1]) - FIRST_VFP_REGNUM) / 2;
8472 for (i = 1; i < XVECLEN (operands[2], 0); i++)
8474 p += sprintf (&pattern[p], ", d%d", base + i);
8476 strcpy (&pattern[p], "}");
8478 output_asm_insn (pattern, operands);
8483 /* Emit RTL to save block of VFP register pairs to the stack. Returns the
8484 number of bytes pushed. */
8487 vfp_emit_fstmx (int base_reg, int count)
8494 /* Workaround ARM10 VFPr1 bug. Data corruption can occur when exactly two
8495 register pairs are stored by a store multiple insn. We avoid this
8496 by pushing an extra pair. */
8497 if (count == 2 && !arm_arch6)
8499 if (base_reg == LAST_VFP_REGNUM - 3)
8504 /* ??? The frame layout is implementation defined. We describe
8505 standard format 1 (equivalent to a FSTMD insn and unused pad word).
8506 We really need some way of representing the whole block so that the
8507 unwinder can figure it out at runtime. */
8508 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
8509 dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (count + 1));
8511 reg = gen_rtx_REG (DFmode, base_reg);
8515 = gen_rtx_SET (VOIDmode,
8516 gen_frame_mem (BLKmode,
8517 gen_rtx_PRE_DEC (BLKmode,
8518 stack_pointer_rtx)),
8519 gen_rtx_UNSPEC (BLKmode,
8523 tmp = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
8524 plus_constant (stack_pointer_rtx, -(count * 8 + 4)));
8525 RTX_FRAME_RELATED_P (tmp) = 1;
8526 XVECEXP (dwarf, 0, 0) = tmp;
8528 tmp = gen_rtx_SET (VOIDmode,
8529 gen_frame_mem (DFmode, stack_pointer_rtx),
8531 RTX_FRAME_RELATED_P (tmp) = 1;
8532 XVECEXP (dwarf, 0, 1) = tmp;
8534 for (i = 1; i < count; i++)
8536 reg = gen_rtx_REG (DFmode, base_reg);
8538 XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode, reg);
8540 tmp = gen_rtx_SET (VOIDmode,
8541 gen_frame_mem (DFmode,
8542 plus_constant (stack_pointer_rtx,
8545 RTX_FRAME_RELATED_P (tmp) = 1;
8546 XVECEXP (dwarf, 0, i + 1) = tmp;
8549 par = emit_insn (par);
8550 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
8552 RTX_FRAME_RELATED_P (par) = 1;
8554 return count * 8 + 4;
8558 /* Output a 'call' insn. */
8560 output_call (rtx *operands)
8562 gcc_assert (!arm_arch5); /* Patterns should call blx <reg> directly. */
8564 /* Handle calls to lr using ip (which may be clobbered in subr anyway). */
8565 if (REGNO (operands[0]) == LR_REGNUM)
8567 operands[0] = gen_rtx_REG (SImode, IP_REGNUM);
8568 output_asm_insn ("mov%?\t%0, %|lr", operands);
8571 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
8573 if (TARGET_INTERWORK || arm_arch4t)
8574 output_asm_insn ("bx%?\t%0", operands);
8576 output_asm_insn ("mov%?\t%|pc, %0", operands);
8581 /* Output a 'call' insn that is a reference in memory. */
8583 output_call_mem (rtx *operands)
8585 if (TARGET_INTERWORK && !arm_arch5)
8587 output_asm_insn ("ldr%?\t%|ip, %0", operands);
8588 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
8589 output_asm_insn ("bx%?\t%|ip", operands);
8591 else if (regno_use_in (LR_REGNUM, operands[0]))
8593 /* LR is used in the memory address. We load the address in the
8594 first instruction. It's safe to use IP as the target of the
8595 load since the call will kill it anyway. */
8596 output_asm_insn ("ldr%?\t%|ip, %0", operands);
8598 output_asm_insn ("blx%?\t%|ip", operands);
8601 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
8603 output_asm_insn ("bx%?\t%|ip", operands);
8605 output_asm_insn ("mov%?\t%|pc, %|ip", operands);
8610 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
8611 output_asm_insn ("ldr%?\t%|pc, %0", operands);
8618 /* Output a move from arm registers to an fpa registers.
8619 OPERANDS[0] is an fpa register.
8620 OPERANDS[1] is the first registers of an arm register pair. */
8622 output_mov_long_double_fpa_from_arm (rtx *operands)
8624 int arm_reg0 = REGNO (operands[1]);
8627 gcc_assert (arm_reg0 != IP_REGNUM);
8629 ops[0] = gen_rtx_REG (SImode, arm_reg0);
8630 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
8631 ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0);
8633 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1, %2}", ops);
8634 output_asm_insn ("ldf%?e\t%0, [%|sp], #12", operands);
8639 /* Output a move from an fpa register to arm registers.
8640 OPERANDS[0] is the first registers of an arm register pair.
8641 OPERANDS[1] is an fpa register. */
8643 output_mov_long_double_arm_from_fpa (rtx *operands)
8645 int arm_reg0 = REGNO (operands[0]);
8648 gcc_assert (arm_reg0 != IP_REGNUM);
8650 ops[0] = gen_rtx_REG (SImode, arm_reg0);
8651 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
8652 ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0);
8654 output_asm_insn ("stf%?e\t%1, [%|sp, #-12]!", operands);
8655 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1, %2}", ops);
8659 /* Output a move from arm registers to arm registers of a long double
8660 OPERANDS[0] is the destination.
8661 OPERANDS[1] is the source. */
8663 output_mov_long_double_arm_from_arm (rtx *operands)
8665 /* We have to be careful here because the two might overlap. */
8666 int dest_start = REGNO (operands[0]);
8667 int src_start = REGNO (operands[1]);
8671 if (dest_start < src_start)
8673 for (i = 0; i < 3; i++)
8675 ops[0] = gen_rtx_REG (SImode, dest_start + i);
8676 ops[1] = gen_rtx_REG (SImode, src_start + i);
8677 output_asm_insn ("mov%?\t%0, %1", ops);
8682 for (i = 2; i >= 0; i--)
8684 ops[0] = gen_rtx_REG (SImode, dest_start + i);
8685 ops[1] = gen_rtx_REG (SImode, src_start + i);
8686 output_asm_insn ("mov%?\t%0, %1", ops);
8694 /* Output a move from arm registers to an fpa registers.
8695 OPERANDS[0] is an fpa register.
8696 OPERANDS[1] is the first registers of an arm register pair. */
8698 output_mov_double_fpa_from_arm (rtx *operands)
8700 int arm_reg0 = REGNO (operands[1]);
8703 gcc_assert (arm_reg0 != IP_REGNUM);
8705 ops[0] = gen_rtx_REG (SImode, arm_reg0);
8706 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
8707 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1}", ops);
8708 output_asm_insn ("ldf%?d\t%0, [%|sp], #8", operands);
8712 /* Output a move from an fpa register to arm registers.
8713 OPERANDS[0] is the first registers of an arm register pair.
8714 OPERANDS[1] is an fpa register. */
8716 output_mov_double_arm_from_fpa (rtx *operands)
8718 int arm_reg0 = REGNO (operands[0]);
8721 gcc_assert (arm_reg0 != IP_REGNUM);
8723 ops[0] = gen_rtx_REG (SImode, arm_reg0);
8724 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
8725 output_asm_insn ("stf%?d\t%1, [%|sp, #-8]!", operands);
8726 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1}", ops);
8730 /* Output a move between double words.
8731 It must be REG<-REG, REG<-CONST_DOUBLE, REG<-CONST_INT, REG<-MEM
8732 or MEM<-REG and all MEMs must be offsettable addresses. */
8734 output_move_double (rtx *operands)
8736 enum rtx_code code0 = GET_CODE (operands[0]);
8737 enum rtx_code code1 = GET_CODE (operands[1]);
8742 int reg0 = REGNO (operands[0]);
8744 otherops[0] = gen_rtx_REG (SImode, 1 + reg0);
8746 gcc_assert (code1 == MEM); /* Constraints should ensure this. */
8748 switch (GET_CODE (XEXP (operands[1], 0)))
8751 output_asm_insn ("ldm%?ia\t%m1, %M0", operands);
8755 gcc_assert (TARGET_LDRD);
8756 output_asm_insn ("ldr%?d\t%0, [%m1, #8]!", operands);
8760 output_asm_insn ("ldm%?db\t%m1!, %M0", operands);
8764 output_asm_insn ("ldm%?ia\t%m1!, %M0", operands);
8768 gcc_assert (TARGET_LDRD);
8769 output_asm_insn ("ldr%?d\t%0, [%m1], #-8", operands);
8774 otherops[0] = operands[0];
8775 otherops[1] = XEXP (XEXP (XEXP (operands[1], 0), 1), 0);
8776 otherops[2] = XEXP (XEXP (XEXP (operands[1], 0), 1), 1);
8778 if (GET_CODE (XEXP (operands[1], 0)) == PRE_MODIFY)
8780 if (reg_overlap_mentioned_p (otherops[0], otherops[2]))
8782 /* Registers overlap so split out the increment. */
8783 output_asm_insn ("add%?\t%1, %1, %2", otherops);
8784 output_asm_insn ("ldr%?d\t%0, [%1] @split", otherops);
8788 /* IWMMXT allows offsets larger than ldrd can handle,
8789 fix these up with a pair of ldr. */
8790 if (GET_CODE (otherops[2]) == CONST_INT
8791 && (INTVAL(otherops[2]) <= -256
8792 || INTVAL(otherops[2]) >= 256))
8794 output_asm_insn ("ldr%?\t%0, [%1, %2]!", otherops);
8795 otherops[0] = gen_rtx_REG (SImode, 1 + reg0);
8796 output_asm_insn ("ldr%?\t%0, [%1, #4]", otherops);
8799 output_asm_insn ("ldr%?d\t%0, [%1, %2]!", otherops);
8804 /* IWMMXT allows offsets larger than ldrd can handle,
8805 fix these up with a pair of ldr. */
8806 if (GET_CODE (otherops[2]) == CONST_INT
8807 && (INTVAL(otherops[2]) <= -256
8808 || INTVAL(otherops[2]) >= 256))
8810 otherops[0] = gen_rtx_REG (SImode, 1 + reg0);
8811 output_asm_insn ("ldr%?\t%0, [%1, #4]", otherops);
8812 otherops[0] = operands[0];
8813 output_asm_insn ("ldr%?\t%0, [%1], %2", otherops);
8816 /* We only allow constant increments, so this is safe. */
8817 output_asm_insn ("ldr%?d\t%0, [%1], %2", otherops);
8823 output_asm_insn ("adr%?\t%0, %1", operands);
8824 output_asm_insn ("ldm%?ia\t%0, %M0", operands);
8828 if (arm_add_operand (XEXP (XEXP (operands[1], 0), 1),
8829 GET_MODE (XEXP (XEXP (operands[1], 0), 1))))
8831 otherops[0] = operands[0];
8832 otherops[1] = XEXP (XEXP (operands[1], 0), 0);
8833 otherops[2] = XEXP (XEXP (operands[1], 0), 1);
8835 if (GET_CODE (XEXP (operands[1], 0)) == PLUS)
8837 if (GET_CODE (otherops[2]) == CONST_INT)
8839 switch ((int) INTVAL (otherops[2]))
8842 output_asm_insn ("ldm%?db\t%1, %M0", otherops);
8845 output_asm_insn ("ldm%?da\t%1, %M0", otherops);
8848 output_asm_insn ("ldm%?ib\t%1, %M0", otherops);
8853 && (GET_CODE (otherops[2]) == REG
8854 || (GET_CODE (otherops[2]) == CONST_INT
8855 && INTVAL (otherops[2]) > -256
8856 && INTVAL (otherops[2]) < 256)))
8858 if (reg_overlap_mentioned_p (otherops[0],
8861 /* Swap base and index registers over to
8862 avoid a conflict. */
8863 otherops[1] = XEXP (XEXP (operands[1], 0), 1);
8864 otherops[2] = XEXP (XEXP (operands[1], 0), 0);
8866 /* If both registers conflict, it will usually
8867 have been fixed by a splitter. */
8868 if (reg_overlap_mentioned_p (otherops[0], otherops[2]))
8870 output_asm_insn ("add%?\t%1, %1, %2", otherops);
8871 output_asm_insn ("ldr%?d\t%0, [%1]",
8875 output_asm_insn ("ldr%?d\t%0, [%1, %2]", otherops);
8879 if (GET_CODE (otherops[2]) == CONST_INT)
8881 if (!(const_ok_for_arm (INTVAL (otherops[2]))))
8882 output_asm_insn ("sub%?\t%0, %1, #%n2", otherops);
8884 output_asm_insn ("add%?\t%0, %1, %2", otherops);
8887 output_asm_insn ("add%?\t%0, %1, %2", otherops);
8890 output_asm_insn ("sub%?\t%0, %1, %2", otherops);
8892 return "ldm%?ia\t%0, %M0";
8896 otherops[1] = adjust_address (operands[1], SImode, 4);
8897 /* Take care of overlapping base/data reg. */
8898 if (reg_mentioned_p (operands[0], operands[1]))
8900 output_asm_insn ("ldr%?\t%0, %1", otherops);
8901 output_asm_insn ("ldr%?\t%0, %1", operands);
8905 output_asm_insn ("ldr%?\t%0, %1", operands);
8906 output_asm_insn ("ldr%?\t%0, %1", otherops);
8913 /* Constraints should ensure this. */
8914 gcc_assert (code0 == MEM && code1 == REG);
8915 gcc_assert (REGNO (operands[1]) != IP_REGNUM);
8917 switch (GET_CODE (XEXP (operands[0], 0)))
8920 output_asm_insn ("stm%?ia\t%m0, %M1", operands);
8924 gcc_assert (TARGET_LDRD);
8925 output_asm_insn ("str%?d\t%1, [%m0, #8]!", operands);
8929 output_asm_insn ("stm%?db\t%m0!, %M1", operands);
8933 output_asm_insn ("stm%?ia\t%m0!, %M1", operands);
8937 gcc_assert (TARGET_LDRD);
8938 output_asm_insn ("str%?d\t%1, [%m0], #-8", operands);
8943 otherops[0] = operands[1];
8944 otherops[1] = XEXP (XEXP (XEXP (operands[0], 0), 1), 0);
8945 otherops[2] = XEXP (XEXP (XEXP (operands[0], 0), 1), 1);
8947 /* IWMMXT allows offsets larger than ldrd can handle,
8948 fix these up with a pair of ldr. */
8949 if (GET_CODE (otherops[2]) == CONST_INT
8950 && (INTVAL(otherops[2]) <= -256
8951 || INTVAL(otherops[2]) >= 256))
8954 reg1 = gen_rtx_REG (SImode, 1 + REGNO (operands[1]));
8955 if (GET_CODE (XEXP (operands[0], 0)) == PRE_MODIFY)
8957 output_asm_insn ("ldr%?\t%0, [%1, %2]!", otherops);
8959 output_asm_insn ("ldr%?\t%0, [%1, #4]", otherops);
8964 output_asm_insn ("ldr%?\t%0, [%1, #4]", otherops);
8965 otherops[0] = operands[1];
8966 output_asm_insn ("ldr%?\t%0, [%1], %2", otherops);
8969 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_MODIFY)
8970 output_asm_insn ("str%?d\t%0, [%1, %2]!", otherops);
8972 output_asm_insn ("str%?d\t%0, [%1], %2", otherops);
8976 otherops[2] = XEXP (XEXP (operands[0], 0), 1);
8977 if (GET_CODE (otherops[2]) == CONST_INT)
8979 switch ((int) INTVAL (XEXP (XEXP (operands[0], 0), 1)))
8982 output_asm_insn ("stm%?db\t%m0, %M1", operands);
8986 output_asm_insn ("stm%?da\t%m0, %M1", operands);
8990 output_asm_insn ("stm%?ib\t%m0, %M1", operands);
8995 && (GET_CODE (otherops[2]) == REG
8996 || (GET_CODE (otherops[2]) == CONST_INT
8997 && INTVAL (otherops[2]) > -256
8998 && INTVAL (otherops[2]) < 256)))
9000 otherops[0] = operands[1];
9001 otherops[1] = XEXP (XEXP (operands[0], 0), 0);
9002 output_asm_insn ("str%?d\t%0, [%1, %2]", otherops);
9008 otherops[0] = adjust_address (operands[0], SImode, 4);
9009 otherops[1] = gen_rtx_REG (SImode, 1 + REGNO (operands[1]));
9010 output_asm_insn ("str%?\t%1, %0", operands);
9011 output_asm_insn ("str%?\t%1, %0", otherops);
9018 /* Output an ADD r, s, #n where n may be too big for one instruction.
9019 If adding zero to one register, output nothing. */
9021 output_add_immediate (rtx *operands)
9023 HOST_WIDE_INT n = INTVAL (operands[2]);
9025 if (n != 0 || REGNO (operands[0]) != REGNO (operands[1]))
9028 output_multi_immediate (operands,
9029 "sub%?\t%0, %1, %2", "sub%?\t%0, %0, %2", 2,
9032 output_multi_immediate (operands,
9033 "add%?\t%0, %1, %2", "add%?\t%0, %0, %2", 2,
9040 /* Output a multiple immediate operation.
9041 OPERANDS is the vector of operands referred to in the output patterns.
9042 INSTR1 is the output pattern to use for the first constant.
9043 INSTR2 is the output pattern to use for subsequent constants.
9044 IMMED_OP is the index of the constant slot in OPERANDS.
9045 N is the constant value. */
9047 output_multi_immediate (rtx *operands, const char *instr1, const char *instr2,
9048 int immed_op, HOST_WIDE_INT n)
9050 #if HOST_BITS_PER_WIDE_INT > 32
9056 /* Quick and easy output. */
9057 operands[immed_op] = const0_rtx;
9058 output_asm_insn (instr1, operands);
9063 const char * instr = instr1;
9065 /* Note that n is never zero here (which would give no output). */
9066 for (i = 0; i < 32; i += 2)
9070 operands[immed_op] = GEN_INT (n & (255 << i));
9071 output_asm_insn (instr, operands);
9081 /* Return the appropriate ARM instruction for the operation code.
9082 The returned result should not be overwritten. OP is the rtx of the
9083 operation. SHIFT_FIRST_ARG is TRUE if the first argument of the operator
9086 arithmetic_instr (rtx op, int shift_first_arg)
9088 switch (GET_CODE (op))
9094 return shift_first_arg ? "rsb" : "sub";
9110 /* Ensure valid constant shifts and return the appropriate shift mnemonic
9111 for the operation code. The returned result should not be overwritten.
9112 OP is the rtx code of the shift.
9113 On exit, *AMOUNTP will be -1 if the shift is by a register, or a constant
9116 shift_op (rtx op, HOST_WIDE_INT *amountp)
9119 enum rtx_code code = GET_CODE (op);
9121 switch (GET_CODE (XEXP (op, 1)))
9129 *amountp = INTVAL (XEXP (op, 1));
9151 gcc_assert (*amountp != -1);
9152 *amountp = 32 - *amountp;
9161 /* We never have to worry about the amount being other than a
9162 power of 2, since this case can never be reloaded from a reg. */
9163 gcc_assert (*amountp != -1);
9164 *amountp = int_log2 (*amountp);
9173 /* This is not 100% correct, but follows from the desire to merge
9174 multiplication by a power of 2 with the recognizer for a
9175 shift. >=32 is not a valid shift for "asl", so we must try and
9176 output a shift that produces the correct arithmetical result.
9177 Using lsr #32 is identical except for the fact that the carry bit
9178 is not set correctly if we set the flags; but we never use the
9179 carry bit from such an operation, so we can ignore that. */
9180 if (code == ROTATERT)
9181 /* Rotate is just modulo 32. */
9183 else if (*amountp != (*amountp & 31))
9190 /* Shifts of 0 are no-ops. */
9198 /* Obtain the shift from the POWER of two. */
9200 static HOST_WIDE_INT
9201 int_log2 (HOST_WIDE_INT power)
9203 HOST_WIDE_INT shift = 0;
9205 while ((((HOST_WIDE_INT) 1 << shift) & power) == 0)
9207 gcc_assert (shift <= 31);
9214 /* Output a .ascii pseudo-op, keeping track of lengths. This is
9215 because /bin/as is horribly restrictive. The judgement about
9216 whether or not each character is 'printable' (and can be output as
9217 is) or not (and must be printed with an octal escape) must be made
9218 with reference to the *host* character set -- the situation is
9219 similar to that discussed in the comments above pp_c_char in
9220 c-pretty-print.c. */
9222 #define MAX_ASCII_LEN 51
9225 output_ascii_pseudo_op (FILE *stream, const unsigned char *p, int len)
9230 fputs ("\t.ascii\t\"", stream);
9232 for (i = 0; i < len; i++)
9236 if (len_so_far >= MAX_ASCII_LEN)
9238 fputs ("\"\n\t.ascii\t\"", stream);
9244 if (c == '\\' || c == '\"')
9246 putc ('\\', stream);
9254 fprintf (stream, "\\%03o", c);
9259 fputs ("\"\n", stream);
9262 /* Compute the register save mask for registers 0 through 12
9263 inclusive. This code is used by arm_compute_save_reg_mask. */
9265 static unsigned long
9266 arm_compute_save_reg0_reg12_mask (void)
9268 unsigned long func_type = arm_current_func_type ();
9269 unsigned long save_reg_mask = 0;
9272 if (IS_INTERRUPT (func_type))
9274 unsigned int max_reg;
9275 /* Interrupt functions must not corrupt any registers,
9276 even call clobbered ones. If this is a leaf function
9277 we can just examine the registers used by the RTL, but
9278 otherwise we have to assume that whatever function is
9279 called might clobber anything, and so we have to save
9280 all the call-clobbered registers as well. */
9281 if (ARM_FUNC_TYPE (func_type) == ARM_FT_FIQ)
9282 /* FIQ handlers have registers r8 - r12 banked, so
9283 we only need to check r0 - r7, Normal ISRs only
9284 bank r14 and r15, so we must check up to r12.
9285 r13 is the stack pointer which is always preserved,
9286 so we do not need to consider it here. */
9291 for (reg = 0; reg <= max_reg; reg++)
9292 if (regs_ever_live[reg]
9293 || (! current_function_is_leaf && call_used_regs [reg]))
9294 save_reg_mask |= (1 << reg);
9296 /* Also save the pic base register if necessary. */
9298 && !TARGET_SINGLE_PIC_BASE
9299 && arm_pic_register != INVALID_REGNUM
9300 && current_function_uses_pic_offset_table)
9301 save_reg_mask |= 1 << PIC_OFFSET_TABLE_REGNUM;
9305 /* In the normal case we only need to save those registers
9306 which are call saved and which are used by this function. */
9307 for (reg = 0; reg <= 10; reg++)
9308 if (regs_ever_live[reg] && ! call_used_regs [reg])
9309 save_reg_mask |= (1 << reg);
9311 /* Handle the frame pointer as a special case. */
9312 if (! TARGET_APCS_FRAME
9313 && ! frame_pointer_needed
9314 && regs_ever_live[HARD_FRAME_POINTER_REGNUM]
9315 && ! call_used_regs[HARD_FRAME_POINTER_REGNUM])
9316 save_reg_mask |= 1 << HARD_FRAME_POINTER_REGNUM;
9318 /* If we aren't loading the PIC register,
9319 don't stack it even though it may be live. */
9321 && !TARGET_SINGLE_PIC_BASE
9322 && arm_pic_register != INVALID_REGNUM
9323 && (regs_ever_live[PIC_OFFSET_TABLE_REGNUM]
9324 || current_function_uses_pic_offset_table))
9325 save_reg_mask |= 1 << PIC_OFFSET_TABLE_REGNUM;
9328 /* Save registers so the exception handler can modify them. */
9329 if (current_function_calls_eh_return)
9335 reg = EH_RETURN_DATA_REGNO (i);
9336 if (reg == INVALID_REGNUM)
9338 save_reg_mask |= 1 << reg;
9342 return save_reg_mask;
9345 /* Compute a bit mask of which registers need to be
9346 saved on the stack for the current function. */
9348 static unsigned long
9349 arm_compute_save_reg_mask (void)
9351 unsigned int save_reg_mask = 0;
9352 unsigned long func_type = arm_current_func_type ();
9354 if (IS_NAKED (func_type))
9355 /* This should never really happen. */
9358 /* If we are creating a stack frame, then we must save the frame pointer,
9359 IP (which will hold the old stack pointer), LR and the PC. */
9360 if (frame_pointer_needed)
9362 (1 << ARM_HARD_FRAME_POINTER_REGNUM)
9367 /* Volatile functions do not return, so there
9368 is no need to save any other registers. */
9369 if (IS_VOLATILE (func_type))
9370 return save_reg_mask;
9372 save_reg_mask |= arm_compute_save_reg0_reg12_mask ();
9374 /* Decide if we need to save the link register.
9375 Interrupt routines have their own banked link register,
9376 so they never need to save it.
9377 Otherwise if we do not use the link register we do not need to save
9378 it. If we are pushing other registers onto the stack however, we
9379 can save an instruction in the epilogue by pushing the link register
9380 now and then popping it back into the PC. This incurs extra memory
9381 accesses though, so we only do it when optimizing for size, and only
9382 if we know that we will not need a fancy return sequence. */
9383 if (regs_ever_live [LR_REGNUM]
9386 && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL
9387 && !current_function_calls_eh_return))
9388 save_reg_mask |= 1 << LR_REGNUM;
9390 if (cfun->machine->lr_save_eliminated)
9391 save_reg_mask &= ~ (1 << LR_REGNUM);
9393 if (TARGET_REALLY_IWMMXT
9394 && ((bit_count (save_reg_mask)
9395 + ARM_NUM_INTS (current_function_pretend_args_size)) % 2) != 0)
9399 /* The total number of registers that are going to be pushed
9400 onto the stack is odd. We need to ensure that the stack
9401 is 64-bit aligned before we start to save iWMMXt registers,
9402 and also before we start to create locals. (A local variable
9403 might be a double or long long which we will load/store using
9404 an iWMMXt instruction). Therefore we need to push another
9405 ARM register, so that the stack will be 64-bit aligned. We
9406 try to avoid using the arg registers (r0 -r3) as they might be
9407 used to pass values in a tail call. */
9408 for (reg = 4; reg <= 12; reg++)
9409 if ((save_reg_mask & (1 << reg)) == 0)
9413 save_reg_mask |= (1 << reg);
9416 cfun->machine->sibcall_blocked = 1;
9417 save_reg_mask |= (1 << 3);
9421 return save_reg_mask;
9425 /* Compute a bit mask of which registers need to be
9426 saved on the stack for the current function. */
9427 static unsigned long
9428 thumb_compute_save_reg_mask (void)
9434 for (reg = 0; reg < 12; reg ++)
9435 if (regs_ever_live[reg] && !call_used_regs[reg])
9439 && !TARGET_SINGLE_PIC_BASE
9440 && arm_pic_register != INVALID_REGNUM
9441 && current_function_uses_pic_offset_table)
9442 mask |= 1 << PIC_OFFSET_TABLE_REGNUM;
9444 /* See if we might need r11 for calls to _interwork_r11_call_via_rN(). */
9445 if (!frame_pointer_needed && CALLER_INTERWORKING_SLOT_SIZE > 0)
9446 mask |= 1 << ARM_HARD_FRAME_POINTER_REGNUM;
9448 /* LR will also be pushed if any lo regs are pushed. */
9449 if (mask & 0xff || thumb_force_lr_save ())
9450 mask |= (1 << LR_REGNUM);
9452 /* Make sure we have a low work register if we need one.
9453 We will need one if we are going to push a high register,
9454 but we are not currently intending to push a low register. */
9455 if ((mask & 0xff) == 0
9456 && ((mask & 0x0f00) || TARGET_BACKTRACE))
9458 /* Use thumb_find_work_register to choose which register
9459 we will use. If the register is live then we will
9460 have to push it. Use LAST_LO_REGNUM as our fallback
9461 choice for the register to select. */
9462 reg = thumb_find_work_register (1 << LAST_LO_REGNUM);
9464 if (! call_used_regs[reg])
9472 /* Return the number of bytes required to save VFP registers. */
9474 arm_get_vfp_saved_size (void)
9481 /* Space for saved VFP registers. */
9482 if (TARGET_HARD_FLOAT && TARGET_VFP)
9485 for (regno = FIRST_VFP_REGNUM;
9486 regno < LAST_VFP_REGNUM;
9489 if ((!regs_ever_live[regno] || call_used_regs[regno])
9490 && (!regs_ever_live[regno + 1] || call_used_regs[regno + 1]))
9494 /* Workaround ARM10 VFPr1 bug. */
9495 if (count == 2 && !arm_arch6)
9497 saved += count * 8 + 4;
9506 if (count == 2 && !arm_arch6)
9508 saved += count * 8 + 4;
9515 /* Generate a function exit sequence. If REALLY_RETURN is false, then do
9516 everything bar the final return instruction. */
9518 output_return_instruction (rtx operand, int really_return, int reverse)
9520 char conditional[10];
9523 unsigned long live_regs_mask;
9524 unsigned long func_type;
9525 arm_stack_offsets *offsets;
9527 func_type = arm_current_func_type ();
9529 if (IS_NAKED (func_type))
9532 if (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN)
9534 /* If this function was declared non-returning, and we have
9535 found a tail call, then we have to trust that the called
9536 function won't return. */
9541 /* Otherwise, trap an attempted return by aborting. */
9543 ops[1] = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)"
9545 assemble_external_libcall (ops[1]);
9546 output_asm_insn (reverse ? "bl%D0\t%a1" : "bl%d0\t%a1", ops);
9552 gcc_assert (!current_function_calls_alloca || really_return);
9554 sprintf (conditional, "%%?%%%c0", reverse ? 'D' : 'd');
9556 return_used_this_function = 1;
9558 live_regs_mask = arm_compute_save_reg_mask ();
9562 const char * return_reg;
9564 /* If we do not have any special requirements for function exit
9565 (e.g. interworking, or ISR) then we can load the return address
9566 directly into the PC. Otherwise we must load it into LR. */
9568 && ! TARGET_INTERWORK)
9569 return_reg = reg_names[PC_REGNUM];
9571 return_reg = reg_names[LR_REGNUM];
9573 if ((live_regs_mask & (1 << IP_REGNUM)) == (1 << IP_REGNUM))
9575 /* There are three possible reasons for the IP register
9576 being saved. 1) a stack frame was created, in which case
9577 IP contains the old stack pointer, or 2) an ISR routine
9578 corrupted it, or 3) it was saved to align the stack on
9579 iWMMXt. In case 1, restore IP into SP, otherwise just
9581 if (frame_pointer_needed)
9583 live_regs_mask &= ~ (1 << IP_REGNUM);
9584 live_regs_mask |= (1 << SP_REGNUM);
9587 gcc_assert (IS_INTERRUPT (func_type) || TARGET_REALLY_IWMMXT);
9590 /* On some ARM architectures it is faster to use LDR rather than
9591 LDM to load a single register. On other architectures, the
9592 cost is the same. In 26 bit mode, or for exception handlers,
9593 we have to use LDM to load the PC so that the CPSR is also
9595 for (reg = 0; reg <= LAST_ARM_REGNUM; reg++)
9596 if (live_regs_mask == (1U << reg))
9599 if (reg <= LAST_ARM_REGNUM
9600 && (reg != LR_REGNUM
9602 || ! IS_INTERRUPT (func_type)))
9604 sprintf (instr, "ldr%s\t%%|%s, [%%|sp], #4", conditional,
9605 (reg == LR_REGNUM) ? return_reg : reg_names[reg]);
9612 /* Generate the load multiple instruction to restore the
9613 registers. Note we can get here, even if
9614 frame_pointer_needed is true, but only if sp already
9615 points to the base of the saved core registers. */
9616 if (live_regs_mask & (1 << SP_REGNUM))
9618 unsigned HOST_WIDE_INT stack_adjust;
9620 offsets = arm_get_frame_offsets ();
9621 stack_adjust = offsets->outgoing_args - offsets->saved_regs;
9622 gcc_assert (stack_adjust == 0 || stack_adjust == 4);
9624 if (stack_adjust && arm_arch5)
9625 sprintf (instr, "ldm%sib\t%%|sp, {", conditional);
9628 /* If we can't use ldmib (SA110 bug),
9629 then try to pop r3 instead. */
9631 live_regs_mask |= 1 << 3;
9632 sprintf (instr, "ldm%sfd\t%%|sp, {", conditional);
9636 sprintf (instr, "ldm%sfd\t%%|sp!, {", conditional);
9638 p = instr + strlen (instr);
9640 for (reg = 0; reg <= SP_REGNUM; reg++)
9641 if (live_regs_mask & (1 << reg))
9643 int l = strlen (reg_names[reg]);
9649 memcpy (p, ", ", 2);
9653 memcpy (p, "%|", 2);
9654 memcpy (p + 2, reg_names[reg], l);
9658 if (live_regs_mask & (1 << LR_REGNUM))
9660 sprintf (p, "%s%%|%s}", first ? "" : ", ", return_reg);
9661 /* If returning from an interrupt, restore the CPSR. */
9662 if (IS_INTERRUPT (func_type))
9669 output_asm_insn (instr, & operand);
9671 /* See if we need to generate an extra instruction to
9672 perform the actual function return. */
9674 && func_type != ARM_FT_INTERWORKED
9675 && (live_regs_mask & (1 << LR_REGNUM)) != 0)
9677 /* The return has already been handled
9678 by loading the LR into the PC. */
9685 switch ((int) ARM_FUNC_TYPE (func_type))
9689 sprintf (instr, "sub%ss\t%%|pc, %%|lr, #4", conditional);
9692 case ARM_FT_INTERWORKED:
9693 sprintf (instr, "bx%s\t%%|lr", conditional);
9696 case ARM_FT_EXCEPTION:
9697 sprintf (instr, "mov%ss\t%%|pc, %%|lr", conditional);
9701 /* Use bx if it's available. */
9702 if (arm_arch5 || arm_arch4t)
9703 sprintf (instr, "bx%s\t%%|lr", conditional);
9705 sprintf (instr, "mov%s\t%%|pc, %%|lr", conditional);
9709 output_asm_insn (instr, & operand);
9715 /* Write the function name into the code section, directly preceding
9716 the function prologue.
9718 Code will be output similar to this:
9720 .ascii "arm_poke_function_name", 0
9723 .word 0xff000000 + (t1 - t0)
9724 arm_poke_function_name
9726 stmfd sp!, {fp, ip, lr, pc}
9729 When performing a stack backtrace, code can inspect the value
9730 of 'pc' stored at 'fp' + 0. If the trace function then looks
9731 at location pc - 12 and the top 8 bits are set, then we know
9732 that there is a function name embedded immediately preceding this
9733 location and has length ((pc[-3]) & 0xff000000).
9735 We assume that pc is declared as a pointer to an unsigned long.
9737 It is of no benefit to output the function name if we are assembling
9738 a leaf function. These function types will not contain a stack
9739 backtrace structure, therefore it is not possible to determine the
9742 arm_poke_function_name (FILE *stream, const char *name)
9744 unsigned long alignlength;
9745 unsigned long length;
9748 length = strlen (name) + 1;
9749 alignlength = ROUND_UP_WORD (length);
9751 ASM_OUTPUT_ASCII (stream, name, length);
9752 ASM_OUTPUT_ALIGN (stream, 2);
9753 x = GEN_INT ((unsigned HOST_WIDE_INT) 0xff000000 + alignlength);
9754 assemble_aligned_integer (UNITS_PER_WORD, x);
9757 /* Place some comments into the assembler stream
9758 describing the current function. */
9760 arm_output_function_prologue (FILE *f, HOST_WIDE_INT frame_size)
9762 unsigned long func_type;
9766 thumb_output_function_prologue (f, frame_size);
9771 gcc_assert (!arm_ccfsm_state && !arm_target_insn);
9773 func_type = arm_current_func_type ();
9775 switch ((int) ARM_FUNC_TYPE (func_type))
9780 case ARM_FT_INTERWORKED:
9781 asm_fprintf (f, "\t%@ Function supports interworking.\n");
9784 asm_fprintf (f, "\t%@ Interrupt Service Routine.\n");
9787 asm_fprintf (f, "\t%@ Fast Interrupt Service Routine.\n");
9789 case ARM_FT_EXCEPTION:
9790 asm_fprintf (f, "\t%@ ARM Exception Handler.\n");
9794 if (IS_NAKED (func_type))
9795 asm_fprintf (f, "\t%@ Naked Function: prologue and epilogue provided by programmer.\n");
9797 if (IS_VOLATILE (func_type))
9798 asm_fprintf (f, "\t%@ Volatile: function does not return.\n");
9800 if (IS_NESTED (func_type))
9801 asm_fprintf (f, "\t%@ Nested: function declared inside another function.\n");
9803 asm_fprintf (f, "\t%@ args = %d, pretend = %d, frame = %wd\n",
9804 current_function_args_size,
9805 current_function_pretend_args_size, frame_size);
9807 asm_fprintf (f, "\t%@ frame_needed = %d, uses_anonymous_args = %d\n",
9808 frame_pointer_needed,
9809 cfun->machine->uses_anonymous_args);
9811 if (cfun->machine->lr_save_eliminated)
9812 asm_fprintf (f, "\t%@ link register save eliminated.\n");
9814 if (current_function_calls_eh_return)
9815 asm_fprintf (f, "\t@ Calls __builtin_eh_return.\n");
9817 #ifdef AOF_ASSEMBLER
9819 asm_fprintf (f, "\tmov\t%r, %r\n", IP_REGNUM, PIC_OFFSET_TABLE_REGNUM);
9822 return_used_this_function = 0;
9826 arm_output_epilogue (rtx sibling)
9829 unsigned long saved_regs_mask;
9830 unsigned long func_type;
9831 /* Floats_offset is the offset from the "virtual" frame. In an APCS
9832 frame that is $fp + 4 for a non-variadic function. */
9833 int floats_offset = 0;
9835 FILE * f = asm_out_file;
9836 unsigned int lrm_count = 0;
9837 int really_return = (sibling == NULL);
9839 arm_stack_offsets *offsets;
9841 /* If we have already generated the return instruction
9842 then it is futile to generate anything else. */
9843 if (use_return_insn (FALSE, sibling) && return_used_this_function)
9846 func_type = arm_current_func_type ();
9848 if (IS_NAKED (func_type))
9849 /* Naked functions don't have epilogues. */
9852 if (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN)
9856 /* A volatile function should never return. Call abort. */
9857 op = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)" : "abort");
9858 assemble_external_libcall (op);
9859 output_asm_insn ("bl\t%a0", &op);
9864 /* If we are throwing an exception, then we really must be doing a
9865 return, so we can't tail-call. */
9866 gcc_assert (!current_function_calls_eh_return || really_return);
9868 offsets = arm_get_frame_offsets ();
9869 saved_regs_mask = arm_compute_save_reg_mask ();
9872 lrm_count = bit_count (saved_regs_mask);
9874 floats_offset = offsets->saved_args;
9875 /* Compute how far away the floats will be. */
9876 for (reg = 0; reg <= LAST_ARM_REGNUM; reg++)
9877 if (saved_regs_mask & (1 << reg))
9880 if (frame_pointer_needed)
9882 /* This variable is for the Virtual Frame Pointer, not VFP regs. */
9883 int vfp_offset = offsets->frame;
9885 if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
9887 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
9888 if (regs_ever_live[reg] && !call_used_regs[reg])
9890 floats_offset += 12;
9891 asm_fprintf (f, "\tldfe\t%r, [%r, #-%d]\n",
9892 reg, FP_REGNUM, floats_offset - vfp_offset);
9897 start_reg = LAST_FPA_REGNUM;
9899 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
9901 if (regs_ever_live[reg] && !call_used_regs[reg])
9903 floats_offset += 12;
9905 /* We can't unstack more than four registers at once. */
9906 if (start_reg - reg == 3)
9908 asm_fprintf (f, "\tlfm\t%r, 4, [%r, #-%d]\n",
9909 reg, FP_REGNUM, floats_offset - vfp_offset);
9910 start_reg = reg - 1;
9915 if (reg != start_reg)
9916 asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n",
9917 reg + 1, start_reg - reg,
9918 FP_REGNUM, floats_offset - vfp_offset);
9919 start_reg = reg - 1;
9923 /* Just in case the last register checked also needs unstacking. */
9924 if (reg != start_reg)
9925 asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n",
9926 reg + 1, start_reg - reg,
9927 FP_REGNUM, floats_offset - vfp_offset);
9930 if (TARGET_HARD_FLOAT && TARGET_VFP)
9934 /* The fldmx insn does not have base+offset addressing modes,
9935 so we use IP to hold the address. */
9936 saved_size = arm_get_vfp_saved_size ();
9940 floats_offset += saved_size;
9941 asm_fprintf (f, "\tsub\t%r, %r, #%d\n", IP_REGNUM,
9942 FP_REGNUM, floats_offset - vfp_offset);
9944 start_reg = FIRST_VFP_REGNUM;
9945 for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2)
9947 if ((!regs_ever_live[reg] || call_used_regs[reg])
9948 && (!regs_ever_live[reg + 1] || call_used_regs[reg + 1]))
9950 if (start_reg != reg)
9951 arm_output_fldmx (f, IP_REGNUM,
9952 (start_reg - FIRST_VFP_REGNUM) / 2,
9953 (reg - start_reg) / 2);
9954 start_reg = reg + 2;
9957 if (start_reg != reg)
9958 arm_output_fldmx (f, IP_REGNUM,
9959 (start_reg - FIRST_VFP_REGNUM) / 2,
9960 (reg - start_reg) / 2);
9965 /* The frame pointer is guaranteed to be non-double-word aligned.
9966 This is because it is set to (old_stack_pointer - 4) and the
9967 old_stack_pointer was double word aligned. Thus the offset to
9968 the iWMMXt registers to be loaded must also be non-double-word
9969 sized, so that the resultant address *is* double-word aligned.
9970 We can ignore floats_offset since that was already included in
9971 the live_regs_mask. */
9972 lrm_count += (lrm_count % 2 ? 2 : 1);
9974 for (reg = LAST_IWMMXT_REGNUM; reg >= FIRST_IWMMXT_REGNUM; reg--)
9975 if (regs_ever_live[reg] && !call_used_regs[reg])
9977 asm_fprintf (f, "\twldrd\t%r, [%r, #-%d]\n",
9978 reg, FP_REGNUM, lrm_count * 4);
9983 /* saved_regs_mask should contain the IP, which at the time of stack
9984 frame generation actually contains the old stack pointer. So a
9985 quick way to unwind the stack is just pop the IP register directly
9986 into the stack pointer. */
9987 gcc_assert (saved_regs_mask & (1 << IP_REGNUM));
9988 saved_regs_mask &= ~ (1 << IP_REGNUM);
9989 saved_regs_mask |= (1 << SP_REGNUM);
9991 /* There are two registers left in saved_regs_mask - LR and PC. We
9992 only need to restore the LR register (the return address), but to
9993 save time we can load it directly into the PC, unless we need a
9994 special function exit sequence, or we are not really returning. */
9996 && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL
9997 && !current_function_calls_eh_return)
9998 /* Delete the LR from the register mask, so that the LR on
9999 the stack is loaded into the PC in the register mask. */
10000 saved_regs_mask &= ~ (1 << LR_REGNUM);
10002 saved_regs_mask &= ~ (1 << PC_REGNUM);
10004 /* We must use SP as the base register, because SP is one of the
10005 registers being restored. If an interrupt or page fault
10006 happens in the ldm instruction, the SP might or might not
10007 have been restored. That would be bad, as then SP will no
10008 longer indicate the safe area of stack, and we can get stack
10009 corruption. Using SP as the base register means that it will
10010 be reset correctly to the original value, should an interrupt
10011 occur. If the stack pointer already points at the right
10012 place, then omit the subtraction. */
10013 if (offsets->outgoing_args != (1 + (int) bit_count (saved_regs_mask))
10014 || current_function_calls_alloca)
10015 asm_fprintf (f, "\tsub\t%r, %r, #%d\n", SP_REGNUM, FP_REGNUM,
10016 4 * bit_count (saved_regs_mask));
10017 print_multi_reg (f, "ldmfd\t%r", SP_REGNUM, saved_regs_mask);
10019 if (IS_INTERRUPT (func_type))
10020 /* Interrupt handlers will have pushed the
10021 IP onto the stack, so restore it now. */
10022 print_multi_reg (f, "ldmfd\t%r!", SP_REGNUM, 1 << IP_REGNUM);
10026 /* Restore stack pointer if necessary. */
10027 if (offsets->outgoing_args != offsets->saved_regs)
10029 operands[0] = operands[1] = stack_pointer_rtx;
10030 operands[2] = GEN_INT (offsets->outgoing_args - offsets->saved_regs);
10031 output_add_immediate (operands);
10034 if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
10036 for (reg = FIRST_FPA_REGNUM; reg <= LAST_FPA_REGNUM; reg++)
10037 if (regs_ever_live[reg] && !call_used_regs[reg])
10038 asm_fprintf (f, "\tldfe\t%r, [%r], #12\n",
10043 start_reg = FIRST_FPA_REGNUM;
10045 for (reg = FIRST_FPA_REGNUM; reg <= LAST_FPA_REGNUM; reg++)
10047 if (regs_ever_live[reg] && !call_used_regs[reg])
10049 if (reg - start_reg == 3)
10051 asm_fprintf (f, "\tlfmfd\t%r, 4, [%r]!\n",
10052 start_reg, SP_REGNUM);
10053 start_reg = reg + 1;
10058 if (reg != start_reg)
10059 asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n",
10060 start_reg, reg - start_reg,
10063 start_reg = reg + 1;
10067 /* Just in case the last register checked also needs unstacking. */
10068 if (reg != start_reg)
10069 asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n",
10070 start_reg, reg - start_reg, SP_REGNUM);
10073 if (TARGET_HARD_FLOAT && TARGET_VFP)
10075 start_reg = FIRST_VFP_REGNUM;
10076 for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2)
10078 if ((!regs_ever_live[reg] || call_used_regs[reg])
10079 && (!regs_ever_live[reg + 1] || call_used_regs[reg + 1]))
10081 if (start_reg != reg)
10082 arm_output_fldmx (f, SP_REGNUM,
10083 (start_reg - FIRST_VFP_REGNUM) / 2,
10084 (reg - start_reg) / 2);
10085 start_reg = reg + 2;
10088 if (start_reg != reg)
10089 arm_output_fldmx (f, SP_REGNUM,
10090 (start_reg - FIRST_VFP_REGNUM) / 2,
10091 (reg - start_reg) / 2);
10094 for (reg = FIRST_IWMMXT_REGNUM; reg <= LAST_IWMMXT_REGNUM; reg++)
10095 if (regs_ever_live[reg] && !call_used_regs[reg])
10096 asm_fprintf (f, "\twldrd\t%r, [%r], #8\n", reg, SP_REGNUM);
10098 /* If we can, restore the LR into the PC. */
10099 if (ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL
10101 && current_function_pretend_args_size == 0
10102 && saved_regs_mask & (1 << LR_REGNUM)
10103 && !current_function_calls_eh_return)
10105 saved_regs_mask &= ~ (1 << LR_REGNUM);
10106 saved_regs_mask |= (1 << PC_REGNUM);
10109 /* Load the registers off the stack. If we only have one register
10110 to load use the LDR instruction - it is faster. */
10111 if (saved_regs_mask == (1 << LR_REGNUM))
10113 asm_fprintf (f, "\tldr\t%r, [%r], #4\n", LR_REGNUM, SP_REGNUM);
10115 else if (saved_regs_mask)
10117 if (saved_regs_mask & (1 << SP_REGNUM))
10118 /* Note - write back to the stack register is not enabled
10119 (i.e. "ldmfd sp!..."). We know that the stack pointer is
10120 in the list of registers and if we add writeback the
10121 instruction becomes UNPREDICTABLE. */
10122 print_multi_reg (f, "ldmfd\t%r", SP_REGNUM, saved_regs_mask);
10124 print_multi_reg (f, "ldmfd\t%r!", SP_REGNUM, saved_regs_mask);
10127 if (current_function_pretend_args_size)
10129 /* Unwind the pre-pushed regs. */
10130 operands[0] = operands[1] = stack_pointer_rtx;
10131 operands[2] = GEN_INT (current_function_pretend_args_size);
10132 output_add_immediate (operands);
10136 /* We may have already restored PC directly from the stack. */
10137 if (!really_return || saved_regs_mask & (1 << PC_REGNUM))
10140 /* Stack adjustment for exception handler. */
10141 if (current_function_calls_eh_return)
10142 asm_fprintf (f, "\tadd\t%r, %r, %r\n", SP_REGNUM, SP_REGNUM,
10143 ARM_EH_STACKADJ_REGNUM);
10145 /* Generate the return instruction. */
10146 switch ((int) ARM_FUNC_TYPE (func_type))
10150 asm_fprintf (f, "\tsubs\t%r, %r, #4\n", PC_REGNUM, LR_REGNUM);
10153 case ARM_FT_EXCEPTION:
10154 asm_fprintf (f, "\tmovs\t%r, %r\n", PC_REGNUM, LR_REGNUM);
10157 case ARM_FT_INTERWORKED:
10158 asm_fprintf (f, "\tbx\t%r\n", LR_REGNUM);
10162 if (arm_arch5 || arm_arch4t)
10163 asm_fprintf (f, "\tbx\t%r\n", LR_REGNUM);
10165 asm_fprintf (f, "\tmov\t%r, %r\n", PC_REGNUM, LR_REGNUM);
10173 arm_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
10174 HOST_WIDE_INT frame_size ATTRIBUTE_UNUSED)
10176 arm_stack_offsets *offsets;
10182 /* Emit any call-via-reg trampolines that are needed for v4t support
10183 of call_reg and call_value_reg type insns. */
10184 for (regno = 0; regno < LR_REGNUM; regno++)
10186 rtx label = cfun->machine->call_via[regno];
10190 switch_to_section (function_section (current_function_decl));
10191 targetm.asm_out.internal_label (asm_out_file, "L",
10192 CODE_LABEL_NUMBER (label));
10193 asm_fprintf (asm_out_file, "\tbx\t%r\n", regno);
10197 /* ??? Probably not safe to set this here, since it assumes that a
10198 function will be emitted as assembly immediately after we generate
10199 RTL for it. This does not happen for inline functions. */
10200 return_used_this_function = 0;
10204 /* We need to take into account any stack-frame rounding. */
10205 offsets = arm_get_frame_offsets ();
10207 gcc_assert (!use_return_insn (FALSE, NULL)
10208 || !return_used_this_function
10209 || offsets->saved_regs == offsets->outgoing_args
10210 || frame_pointer_needed);
10212 /* Reset the ARM-specific per-function variables. */
10213 after_arm_reorg = 0;
10217 /* Generate and emit an insn that we will recognize as a push_multi.
10218 Unfortunately, since this insn does not reflect very well the actual
10219 semantics of the operation, we need to annotate the insn for the benefit
10220 of DWARF2 frame unwind information. */
10222 emit_multi_reg_push (unsigned long mask)
10225 int num_dwarf_regs;
10229 int dwarf_par_index;
10232 for (i = 0; i <= LAST_ARM_REGNUM; i++)
10233 if (mask & (1 << i))
10236 gcc_assert (num_regs && num_regs <= 16);
10238 /* We don't record the PC in the dwarf frame information. */
10239 num_dwarf_regs = num_regs;
10240 if (mask & (1 << PC_REGNUM))
10243 /* For the body of the insn we are going to generate an UNSPEC in
10244 parallel with several USEs. This allows the insn to be recognized
10245 by the push_multi pattern in the arm.md file. The insn looks
10246 something like this:
10249 (set (mem:BLK (pre_dec:BLK (reg:SI sp)))
10250 (unspec:BLK [(reg:SI r4)] UNSPEC_PUSH_MULT))
10251 (use (reg:SI 11 fp))
10252 (use (reg:SI 12 ip))
10253 (use (reg:SI 14 lr))
10254 (use (reg:SI 15 pc))
10257 For the frame note however, we try to be more explicit and actually
10258 show each register being stored into the stack frame, plus a (single)
10259 decrement of the stack pointer. We do it this way in order to be
10260 friendly to the stack unwinding code, which only wants to see a single
10261 stack decrement per instruction. The RTL we generate for the note looks
10262 something like this:
10265 (set (reg:SI sp) (plus:SI (reg:SI sp) (const_int -20)))
10266 (set (mem:SI (reg:SI sp)) (reg:SI r4))
10267 (set (mem:SI (plus:SI (reg:SI sp) (const_int 4))) (reg:SI fp))
10268 (set (mem:SI (plus:SI (reg:SI sp) (const_int 8))) (reg:SI ip))
10269 (set (mem:SI (plus:SI (reg:SI sp) (const_int 12))) (reg:SI lr))
10272 This sequence is used both by the code to support stack unwinding for
10273 exceptions handlers and the code to generate dwarf2 frame debugging. */
10275 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (num_regs));
10276 dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (num_dwarf_regs + 1));
10277 dwarf_par_index = 1;
10279 for (i = 0; i <= LAST_ARM_REGNUM; i++)
10281 if (mask & (1 << i))
10283 reg = gen_rtx_REG (SImode, i);
10285 XVECEXP (par, 0, 0)
10286 = gen_rtx_SET (VOIDmode,
10287 gen_frame_mem (BLKmode,
10288 gen_rtx_PRE_DEC (BLKmode,
10289 stack_pointer_rtx)),
10290 gen_rtx_UNSPEC (BLKmode,
10291 gen_rtvec (1, reg),
10292 UNSPEC_PUSH_MULT));
10294 if (i != PC_REGNUM)
10296 tmp = gen_rtx_SET (VOIDmode,
10297 gen_frame_mem (SImode, stack_pointer_rtx),
10299 RTX_FRAME_RELATED_P (tmp) = 1;
10300 XVECEXP (dwarf, 0, dwarf_par_index) = tmp;
10308 for (j = 1, i++; j < num_regs; i++)
10310 if (mask & (1 << i))
10312 reg = gen_rtx_REG (SImode, i);
10314 XVECEXP (par, 0, j) = gen_rtx_USE (VOIDmode, reg);
10316 if (i != PC_REGNUM)
10319 = gen_rtx_SET (VOIDmode,
10320 gen_frame_mem (SImode,
10321 plus_constant (stack_pointer_rtx,
10324 RTX_FRAME_RELATED_P (tmp) = 1;
10325 XVECEXP (dwarf, 0, dwarf_par_index++) = tmp;
10332 par = emit_insn (par);
10334 tmp = gen_rtx_SET (VOIDmode,
10336 plus_constant (stack_pointer_rtx, -4 * num_regs));
10337 RTX_FRAME_RELATED_P (tmp) = 1;
10338 XVECEXP (dwarf, 0, 0) = tmp;
10340 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
10345 /* Calculate the size of the return value that is passed in registers. */
10347 arm_size_return_regs (void)
10349 enum machine_mode mode;
10351 if (current_function_return_rtx != 0)
10352 mode = GET_MODE (current_function_return_rtx);
10354 mode = DECL_MODE (DECL_RESULT (current_function_decl));
10356 return GET_MODE_SIZE (mode);
10360 emit_sfm (int base_reg, int count)
10367 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
10368 dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (count + 1));
10370 reg = gen_rtx_REG (XFmode, base_reg++);
10372 XVECEXP (par, 0, 0)
10373 = gen_rtx_SET (VOIDmode,
10374 gen_frame_mem (BLKmode,
10375 gen_rtx_PRE_DEC (BLKmode,
10376 stack_pointer_rtx)),
10377 gen_rtx_UNSPEC (BLKmode,
10378 gen_rtvec (1, reg),
10379 UNSPEC_PUSH_MULT));
10380 tmp = gen_rtx_SET (VOIDmode,
10381 gen_frame_mem (XFmode, stack_pointer_rtx), reg);
10382 RTX_FRAME_RELATED_P (tmp) = 1;
10383 XVECEXP (dwarf, 0, 1) = tmp;
10385 for (i = 1; i < count; i++)
10387 reg = gen_rtx_REG (XFmode, base_reg++);
10388 XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode, reg);
10390 tmp = gen_rtx_SET (VOIDmode,
10391 gen_frame_mem (XFmode,
10392 plus_constant (stack_pointer_rtx,
10395 RTX_FRAME_RELATED_P (tmp) = 1;
10396 XVECEXP (dwarf, 0, i + 1) = tmp;
10399 tmp = gen_rtx_SET (VOIDmode,
10401 plus_constant (stack_pointer_rtx, -12 * count));
10403 RTX_FRAME_RELATED_P (tmp) = 1;
10404 XVECEXP (dwarf, 0, 0) = tmp;
10406 par = emit_insn (par);
10407 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
10413 /* Return true if the current function needs to save/restore LR. */
10416 thumb_force_lr_save (void)
10418 return !cfun->machine->lr_save_eliminated
10419 && (!leaf_function_p ()
10420 || thumb_far_jump_used_p ()
10421 || regs_ever_live [LR_REGNUM]);
10425 /* Compute the distance from register FROM to register TO.
10426 These can be the arg pointer (26), the soft frame pointer (25),
10427 the stack pointer (13) or the hard frame pointer (11).
10428 In thumb mode r7 is used as the soft frame pointer, if needed.
10429 Typical stack layout looks like this:
10431 old stack pointer -> | |
10434 | | saved arguments for
10435 | | vararg functions
10438 hard FP & arg pointer -> | | \
10446 soft frame pointer -> | | /
10451 locals base pointer -> | | /
10456 current stack pointer -> | | /
10459 For a given function some or all of these stack components
10460 may not be needed, giving rise to the possibility of
10461 eliminating some of the registers.
10463 The values returned by this function must reflect the behavior
10464 of arm_expand_prologue() and arm_compute_save_reg_mask().
10466 The sign of the number returned reflects the direction of stack
10467 growth, so the values are positive for all eliminations except
10468 from the soft frame pointer to the hard frame pointer.
10470 SFP may point just inside the local variables block to ensure correct
10474 /* Calculate stack offsets. These are used to calculate register elimination
10475 offsets and in prologue/epilogue code. */
10477 static arm_stack_offsets *
10478 arm_get_frame_offsets (void)
10480 struct arm_stack_offsets *offsets;
10481 unsigned long func_type;
10484 HOST_WIDE_INT frame_size;
10486 offsets = &cfun->machine->stack_offsets;
10488 /* We need to know if we are a leaf function. Unfortunately, it
10489 is possible to be called after start_sequence has been called,
10490 which causes get_insns to return the insns for the sequence,
10491 not the function, which will cause leaf_function_p to return
10492 the incorrect result.
10494 to know about leaf functions once reload has completed, and the
10495 frame size cannot be changed after that time, so we can safely
10496 use the cached value. */
10498 if (reload_completed)
10501 /* Initially this is the size of the local variables. It will translated
10502 into an offset once we have determined the size of preceding data. */
10503 frame_size = ROUND_UP_WORD (get_frame_size ());
10505 leaf = leaf_function_p ();
10507 /* Space for variadic functions. */
10508 offsets->saved_args = current_function_pretend_args_size;
10510 offsets->frame = offsets->saved_args + (frame_pointer_needed ? 4 : 0);
10514 unsigned int regno;
10516 saved = bit_count (arm_compute_save_reg_mask ()) * 4;
10518 /* We know that SP will be doubleword aligned on entry, and we must
10519 preserve that condition at any subroutine call. We also require the
10520 soft frame pointer to be doubleword aligned. */
10522 if (TARGET_REALLY_IWMMXT)
10524 /* Check for the call-saved iWMMXt registers. */
10525 for (regno = FIRST_IWMMXT_REGNUM;
10526 regno <= LAST_IWMMXT_REGNUM;
10528 if (regs_ever_live [regno] && ! call_used_regs [regno])
10532 func_type = arm_current_func_type ();
10533 if (! IS_VOLATILE (func_type))
10535 /* Space for saved FPA registers. */
10536 for (regno = FIRST_FPA_REGNUM; regno <= LAST_FPA_REGNUM; regno++)
10537 if (regs_ever_live[regno] && ! call_used_regs[regno])
10540 /* Space for saved VFP registers. */
10541 if (TARGET_HARD_FLOAT && TARGET_VFP)
10542 saved += arm_get_vfp_saved_size ();
10545 else /* TARGET_THUMB */
10547 saved = bit_count (thumb_compute_save_reg_mask ()) * 4;
10548 if (TARGET_BACKTRACE)
10552 /* Saved registers include the stack frame. */
10553 offsets->saved_regs = offsets->saved_args + saved;
10554 offsets->soft_frame = offsets->saved_regs + CALLER_INTERWORKING_SLOT_SIZE;
10555 /* A leaf function does not need any stack alignment if it has nothing
10557 if (leaf && frame_size == 0)
10559 offsets->outgoing_args = offsets->soft_frame;
10560 offsets->locals_base = offsets->soft_frame;
10564 /* Ensure SFP has the correct alignment. */
10565 if (ARM_DOUBLEWORD_ALIGN
10566 && (offsets->soft_frame & 7))
10567 offsets->soft_frame += 4;
10569 offsets->locals_base = offsets->soft_frame + frame_size;
10570 offsets->outgoing_args = (offsets->locals_base
10571 + current_function_outgoing_args_size);
10573 if (ARM_DOUBLEWORD_ALIGN)
10575 /* Ensure SP remains doubleword aligned. */
10576 if (offsets->outgoing_args & 7)
10577 offsets->outgoing_args += 4;
10578 gcc_assert (!(offsets->outgoing_args & 7));
10585 /* Calculate the relative offsets for the different stack pointers. Positive
10586 offsets are in the direction of stack growth. */
10589 arm_compute_initial_elimination_offset (unsigned int from, unsigned int to)
10591 arm_stack_offsets *offsets;
10593 offsets = arm_get_frame_offsets ();
10595 /* OK, now we have enough information to compute the distances.
10596 There must be an entry in these switch tables for each pair
10597 of registers in ELIMINABLE_REGS, even if some of the entries
10598 seem to be redundant or useless. */
10601 case ARG_POINTER_REGNUM:
10604 case THUMB_HARD_FRAME_POINTER_REGNUM:
10607 case FRAME_POINTER_REGNUM:
10608 /* This is the reverse of the soft frame pointer
10609 to hard frame pointer elimination below. */
10610 return offsets->soft_frame - offsets->saved_args;
10612 case ARM_HARD_FRAME_POINTER_REGNUM:
10613 /* If there is no stack frame then the hard
10614 frame pointer and the arg pointer coincide. */
10615 if (offsets->frame == offsets->saved_regs)
10617 /* FIXME: Not sure about this. Maybe we should always return 0 ? */
10618 return (frame_pointer_needed
10619 && cfun->static_chain_decl != NULL
10620 && ! cfun->machine->uses_anonymous_args) ? 4 : 0;
10622 case STACK_POINTER_REGNUM:
10623 /* If nothing has been pushed on the stack at all
10624 then this will return -4. This *is* correct! */
10625 return offsets->outgoing_args - (offsets->saved_args + 4);
10628 gcc_unreachable ();
10630 gcc_unreachable ();
10632 case FRAME_POINTER_REGNUM:
10635 case THUMB_HARD_FRAME_POINTER_REGNUM:
10638 case ARM_HARD_FRAME_POINTER_REGNUM:
10639 /* The hard frame pointer points to the top entry in the
10640 stack frame. The soft frame pointer to the bottom entry
10641 in the stack frame. If there is no stack frame at all,
10642 then they are identical. */
10644 return offsets->frame - offsets->soft_frame;
10646 case STACK_POINTER_REGNUM:
10647 return offsets->outgoing_args - offsets->soft_frame;
10650 gcc_unreachable ();
10652 gcc_unreachable ();
10655 /* You cannot eliminate from the stack pointer.
10656 In theory you could eliminate from the hard frame
10657 pointer to the stack pointer, but this will never
10658 happen, since if a stack frame is not needed the
10659 hard frame pointer will never be used. */
10660 gcc_unreachable ();
10665 /* Generate the prologue instructions for entry into an ARM function. */
10667 arm_expand_prologue (void)
10673 unsigned long live_regs_mask;
10674 unsigned long func_type;
10676 int saved_pretend_args = 0;
10677 int saved_regs = 0;
10678 unsigned HOST_WIDE_INT args_to_push;
10679 arm_stack_offsets *offsets;
10681 func_type = arm_current_func_type ();
10683 /* Naked functions don't have prologues. */
10684 if (IS_NAKED (func_type))
10687 /* Make a copy of c_f_p_a_s as we may need to modify it locally. */
10688 args_to_push = current_function_pretend_args_size;
10690 /* Compute which register we will have to save onto the stack. */
10691 live_regs_mask = arm_compute_save_reg_mask ();
10693 ip_rtx = gen_rtx_REG (SImode, IP_REGNUM);
10695 if (frame_pointer_needed)
10697 if (IS_INTERRUPT (func_type))
10699 /* Interrupt functions must not corrupt any registers.
10700 Creating a frame pointer however, corrupts the IP
10701 register, so we must push it first. */
10702 insn = emit_multi_reg_push (1 << IP_REGNUM);
10704 /* Do not set RTX_FRAME_RELATED_P on this insn.
10705 The dwarf stack unwinding code only wants to see one
10706 stack decrement per function, and this is not it. If
10707 this instruction is labeled as being part of the frame
10708 creation sequence then dwarf2out_frame_debug_expr will
10709 die when it encounters the assignment of IP to FP
10710 later on, since the use of SP here establishes SP as
10711 the CFA register and not IP.
10713 Anyway this instruction is not really part of the stack
10714 frame creation although it is part of the prologue. */
10716 else if (IS_NESTED (func_type))
10718 /* The Static chain register is the same as the IP register
10719 used as a scratch register during stack frame creation.
10720 To get around this need to find somewhere to store IP
10721 whilst the frame is being created. We try the following
10724 1. The last argument register.
10725 2. A slot on the stack above the frame. (This only
10726 works if the function is not a varargs function).
10727 3. Register r3, after pushing the argument registers
10730 Note - we only need to tell the dwarf2 backend about the SP
10731 adjustment in the second variant; the static chain register
10732 doesn't need to be unwound, as it doesn't contain a value
10733 inherited from the caller. */
10735 if (regs_ever_live[3] == 0)
10736 insn = emit_set_insn (gen_rtx_REG (SImode, 3), ip_rtx);
10737 else if (args_to_push == 0)
10741 insn = gen_rtx_PRE_DEC (SImode, stack_pointer_rtx);
10742 insn = emit_set_insn (gen_frame_mem (SImode, insn), ip_rtx);
10745 /* Just tell the dwarf backend that we adjusted SP. */
10746 dwarf = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
10747 plus_constant (stack_pointer_rtx,
10749 RTX_FRAME_RELATED_P (insn) = 1;
10750 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
10751 dwarf, REG_NOTES (insn));
10755 /* Store the args on the stack. */
10756 if (cfun->machine->uses_anonymous_args)
10757 insn = emit_multi_reg_push
10758 ((0xf0 >> (args_to_push / 4)) & 0xf);
10761 (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
10762 GEN_INT (- args_to_push)));
10764 RTX_FRAME_RELATED_P (insn) = 1;
10766 saved_pretend_args = 1;
10767 fp_offset = args_to_push;
10770 /* Now reuse r3 to preserve IP. */
10771 emit_set_insn (gen_rtx_REG (SImode, 3), ip_rtx);
10775 insn = emit_set_insn (ip_rtx,
10776 plus_constant (stack_pointer_rtx, fp_offset));
10777 RTX_FRAME_RELATED_P (insn) = 1;
10782 /* Push the argument registers, or reserve space for them. */
10783 if (cfun->machine->uses_anonymous_args)
10784 insn = emit_multi_reg_push
10785 ((0xf0 >> (args_to_push / 4)) & 0xf);
10788 (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
10789 GEN_INT (- args_to_push)));
10790 RTX_FRAME_RELATED_P (insn) = 1;
10793 /* If this is an interrupt service routine, and the link register
10794 is going to be pushed, and we are not creating a stack frame,
10795 (which would involve an extra push of IP and a pop in the epilogue)
10796 subtracting four from LR now will mean that the function return
10797 can be done with a single instruction. */
10798 if ((func_type == ARM_FT_ISR || func_type == ARM_FT_FIQ)
10799 && (live_regs_mask & (1 << LR_REGNUM)) != 0
10800 && ! frame_pointer_needed)
10802 rtx lr = gen_rtx_REG (SImode, LR_REGNUM);
10804 emit_set_insn (lr, plus_constant (lr, -4));
10807 if (live_regs_mask)
10809 insn = emit_multi_reg_push (live_regs_mask);
10810 saved_regs += bit_count (live_regs_mask) * 4;
10811 RTX_FRAME_RELATED_P (insn) = 1;
10815 for (reg = LAST_IWMMXT_REGNUM; reg >= FIRST_IWMMXT_REGNUM; reg--)
10816 if (regs_ever_live[reg] && ! call_used_regs [reg])
10818 insn = gen_rtx_PRE_DEC (V2SImode, stack_pointer_rtx);
10819 insn = gen_frame_mem (V2SImode, insn);
10820 insn = emit_set_insn (insn, gen_rtx_REG (V2SImode, reg));
10821 RTX_FRAME_RELATED_P (insn) = 1;
10825 if (! IS_VOLATILE (func_type))
10829 /* Save any floating point call-saved registers used by this
10831 if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
10833 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
10834 if (regs_ever_live[reg] && !call_used_regs[reg])
10836 insn = gen_rtx_PRE_DEC (XFmode, stack_pointer_rtx);
10837 insn = gen_frame_mem (XFmode, insn);
10838 insn = emit_set_insn (insn, gen_rtx_REG (XFmode, reg));
10839 RTX_FRAME_RELATED_P (insn) = 1;
10845 start_reg = LAST_FPA_REGNUM;
10847 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
10849 if (regs_ever_live[reg] && !call_used_regs[reg])
10851 if (start_reg - reg == 3)
10853 insn = emit_sfm (reg, 4);
10854 RTX_FRAME_RELATED_P (insn) = 1;
10856 start_reg = reg - 1;
10861 if (start_reg != reg)
10863 insn = emit_sfm (reg + 1, start_reg - reg);
10864 RTX_FRAME_RELATED_P (insn) = 1;
10865 saved_regs += (start_reg - reg) * 12;
10867 start_reg = reg - 1;
10871 if (start_reg != reg)
10873 insn = emit_sfm (reg + 1, start_reg - reg);
10874 saved_regs += (start_reg - reg) * 12;
10875 RTX_FRAME_RELATED_P (insn) = 1;
10878 if (TARGET_HARD_FLOAT && TARGET_VFP)
10880 start_reg = FIRST_VFP_REGNUM;
10882 for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2)
10884 if ((!regs_ever_live[reg] || call_used_regs[reg])
10885 && (!regs_ever_live[reg + 1] || call_used_regs[reg + 1]))
10887 if (start_reg != reg)
10888 saved_regs += vfp_emit_fstmx (start_reg,
10889 (reg - start_reg) / 2);
10890 start_reg = reg + 2;
10893 if (start_reg != reg)
10894 saved_regs += vfp_emit_fstmx (start_reg,
10895 (reg - start_reg) / 2);
10899 if (frame_pointer_needed)
10901 /* Create the new frame pointer. */
10902 insn = GEN_INT (-(4 + args_to_push + fp_offset));
10903 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx, ip_rtx, insn));
10904 RTX_FRAME_RELATED_P (insn) = 1;
10906 if (IS_NESTED (func_type))
10908 /* Recover the static chain register. */
10909 if (regs_ever_live [3] == 0
10910 || saved_pretend_args)
10911 insn = gen_rtx_REG (SImode, 3);
10912 else /* if (current_function_pretend_args_size == 0) */
10914 insn = plus_constant (hard_frame_pointer_rtx, 4);
10915 insn = gen_frame_mem (SImode, insn);
10918 emit_set_insn (ip_rtx, insn);
10919 /* Add a USE to stop propagate_one_insn() from barfing. */
10920 emit_insn (gen_prologue_use (ip_rtx));
10924 offsets = arm_get_frame_offsets ();
10925 if (offsets->outgoing_args != offsets->saved_args + saved_regs)
10927 /* This add can produce multiple insns for a large constant, so we
10928 need to get tricky. */
10929 rtx last = get_last_insn ();
10931 amount = GEN_INT (offsets->saved_args + saved_regs
10932 - offsets->outgoing_args);
10934 insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
10938 last = last ? NEXT_INSN (last) : get_insns ();
10939 RTX_FRAME_RELATED_P (last) = 1;
10941 while (last != insn);
10943 /* If the frame pointer is needed, emit a special barrier that
10944 will prevent the scheduler from moving stores to the frame
10945 before the stack adjustment. */
10946 if (frame_pointer_needed)
10947 insn = emit_insn (gen_stack_tie (stack_pointer_rtx,
10948 hard_frame_pointer_rtx));
10952 if (flag_pic && arm_pic_register != INVALID_REGNUM)
10953 arm_load_pic_register (0UL);
10955 /* If we are profiling, make sure no instructions are scheduled before
10956 the call to mcount. Similarly if the user has requested no
10957 scheduling in the prolog. Similarly if we want non-call exceptions
10958 using the EABI unwinder, to prevent faulting instructions from being
10959 swapped with a stack adjustment. */
10960 if (current_function_profile || !TARGET_SCHED_PROLOG
10961 || (ARM_EABI_UNWIND_TABLES && flag_non_call_exceptions))
10962 emit_insn (gen_blockage ());
10964 /* If the link register is being kept alive, with the return address in it,
10965 then make sure that it does not get reused by the ce2 pass. */
10966 if ((live_regs_mask & (1 << LR_REGNUM)) == 0)
10968 emit_insn (gen_prologue_use (gen_rtx_REG (SImode, LR_REGNUM)));
10969 cfun->machine->lr_save_eliminated = 1;
10973 /* If CODE is 'd', then the X is a condition operand and the instruction
10974 should only be executed if the condition is true.
10975 if CODE is 'D', then the X is a condition operand and the instruction
10976 should only be executed if the condition is false: however, if the mode
10977 of the comparison is CCFPEmode, then always execute the instruction -- we
10978 do this because in these circumstances !GE does not necessarily imply LT;
10979 in these cases the instruction pattern will take care to make sure that
10980 an instruction containing %d will follow, thereby undoing the effects of
10981 doing this instruction unconditionally.
10982 If CODE is 'N' then X is a floating point operand that must be negated
10984 If CODE is 'B' then output a bitwise inverted value of X (a const int).
10985 If X is a REG and CODE is `M', output a ldm/stm style multi-reg. */
10987 arm_print_operand (FILE *stream, rtx x, int code)
10992 fputs (ASM_COMMENT_START, stream);
10996 fputs (user_label_prefix, stream);
11000 fputs (REGISTER_PREFIX, stream);
11004 if (arm_ccfsm_state == 3 || arm_ccfsm_state == 4)
11008 output_operand_lossage ("predicated Thumb instruction");
11011 if (current_insn_predicate != NULL)
11013 output_operand_lossage
11014 ("predicated instruction in conditional sequence");
11018 fputs (arm_condition_codes[arm_current_cc], stream);
11020 else if (current_insn_predicate)
11022 enum arm_cond_code code;
11026 output_operand_lossage ("predicated Thumb instruction");
11030 code = get_arm_condition_code (current_insn_predicate);
11031 fputs (arm_condition_codes[code], stream);
11038 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
11039 r = REAL_VALUE_NEGATE (r);
11040 fprintf (stream, "%s", fp_const_from_val (&r));
11045 if (GET_CODE (x) == CONST_INT)
11048 val = ARM_SIGN_EXTEND (~INTVAL (x));
11049 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, val);
11053 putc ('~', stream);
11054 output_addr_const (stream, x);
11059 fprintf (stream, "%s", arithmetic_instr (x, 1));
11062 /* Truncate Cirrus shift counts. */
11064 if (GET_CODE (x) == CONST_INT)
11066 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0x3f);
11069 arm_print_operand (stream, x, 0);
11073 fprintf (stream, "%s", arithmetic_instr (x, 0));
11081 if (!shift_operator (x, SImode))
11083 output_operand_lossage ("invalid shift operand");
11087 shift = shift_op (x, &val);
11091 fprintf (stream, ", %s ", shift);
11093 arm_print_operand (stream, XEXP (x, 1), 0);
11095 fprintf (stream, "#" HOST_WIDE_INT_PRINT_DEC, val);
11100 /* An explanation of the 'Q', 'R' and 'H' register operands:
11102 In a pair of registers containing a DI or DF value the 'Q'
11103 operand returns the register number of the register containing
11104 the least significant part of the value. The 'R' operand returns
11105 the register number of the register containing the most
11106 significant part of the value.
11108 The 'H' operand returns the higher of the two register numbers.
11109 On a run where WORDS_BIG_ENDIAN is true the 'H' operand is the
11110 same as the 'Q' operand, since the most significant part of the
11111 value is held in the lower number register. The reverse is true
11112 on systems where WORDS_BIG_ENDIAN is false.
11114 The purpose of these operands is to distinguish between cases
11115 where the endian-ness of the values is important (for example
11116 when they are added together), and cases where the endian-ness
11117 is irrelevant, but the order of register operations is important.
11118 For example when loading a value from memory into a register
11119 pair, the endian-ness does not matter. Provided that the value
11120 from the lower memory address is put into the lower numbered
11121 register, and the value from the higher address is put into the
11122 higher numbered register, the load will work regardless of whether
11123 the value being loaded is big-wordian or little-wordian. The
11124 order of the two register loads can matter however, if the address
11125 of the memory location is actually held in one of the registers
11126 being overwritten by the load. */
11128 if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM)
11130 output_operand_lossage ("invalid operand for code '%c'", code);
11134 asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 1 : 0));
11138 if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM)
11140 output_operand_lossage ("invalid operand for code '%c'", code);
11144 asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 0 : 1));
11148 if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM)
11150 output_operand_lossage ("invalid operand for code '%c'", code);
11154 asm_fprintf (stream, "%r", REGNO (x) + 1);
11158 asm_fprintf (stream, "%r",
11159 GET_CODE (XEXP (x, 0)) == REG
11160 ? REGNO (XEXP (x, 0)) : REGNO (XEXP (XEXP (x, 0), 0)));
11164 asm_fprintf (stream, "{%r-%r}",
11166 REGNO (x) + ARM_NUM_REGS (GET_MODE (x)) - 1);
11170 /* CONST_TRUE_RTX means always -- that's the default. */
11171 if (x == const_true_rtx)
11174 if (!COMPARISON_P (x))
11176 output_operand_lossage ("invalid operand for code '%c'", code);
11180 fputs (arm_condition_codes[get_arm_condition_code (x)],
11185 /* CONST_TRUE_RTX means not always -- i.e. never. We shouldn't ever
11186 want to do that. */
11187 if (x == const_true_rtx)
11189 output_operand_lossage ("instruction never exectued");
11192 if (!COMPARISON_P (x))
11194 output_operand_lossage ("invalid operand for code '%c'", code);
11198 fputs (arm_condition_codes[ARM_INVERSE_CONDITION_CODE
11199 (get_arm_condition_code (x))],
11203 /* Cirrus registers can be accessed in a variety of ways:
11204 single floating point (f)
11205 double floating point (d)
11207 64bit integer (dx). */
11208 case 'W': /* Cirrus register in F mode. */
11209 case 'X': /* Cirrus register in D mode. */
11210 case 'Y': /* Cirrus register in FX mode. */
11211 case 'Z': /* Cirrus register in DX mode. */
11212 gcc_assert (GET_CODE (x) == REG
11213 && REGNO_REG_CLASS (REGNO (x)) == CIRRUS_REGS);
11215 fprintf (stream, "mv%s%s",
11217 : code == 'X' ? "d"
11218 : code == 'Y' ? "fx" : "dx", reg_names[REGNO (x)] + 2);
11222 /* Print cirrus register in the mode specified by the register's mode. */
11225 int mode = GET_MODE (x);
11227 if (GET_CODE (x) != REG || REGNO_REG_CLASS (REGNO (x)) != CIRRUS_REGS)
11229 output_operand_lossage ("invalid operand for code '%c'", code);
11233 fprintf (stream, "mv%s%s",
11234 mode == DFmode ? "d"
11235 : mode == SImode ? "fx"
11236 : mode == DImode ? "dx"
11237 : "f", reg_names[REGNO (x)] + 2);
11243 if (GET_CODE (x) != REG
11244 || REGNO (x) < FIRST_IWMMXT_GR_REGNUM
11245 || REGNO (x) > LAST_IWMMXT_GR_REGNUM)
11246 /* Bad value for wCG register number. */
11248 output_operand_lossage ("invalid operand for code '%c'", code);
11253 fprintf (stream, "%d", REGNO (x) - FIRST_IWMMXT_GR_REGNUM);
11256 /* Print an iWMMXt control register name. */
11258 if (GET_CODE (x) != CONST_INT
11260 || INTVAL (x) >= 16)
11261 /* Bad value for wC register number. */
11263 output_operand_lossage ("invalid operand for code '%c'", code);
11269 static const char * wc_reg_names [16] =
11271 "wCID", "wCon", "wCSSF", "wCASF",
11272 "wC4", "wC5", "wC6", "wC7",
11273 "wCGR0", "wCGR1", "wCGR2", "wCGR3",
11274 "wC12", "wC13", "wC14", "wC15"
11277 fprintf (stream, wc_reg_names [INTVAL (x)]);
11281 /* Print a VFP double precision register name. */
11284 int mode = GET_MODE (x);
11287 if (mode != DImode && mode != DFmode)
11289 output_operand_lossage ("invalid operand for code '%c'", code);
11293 if (GET_CODE (x) != REG
11294 || !IS_VFP_REGNUM (REGNO (x)))
11296 output_operand_lossage ("invalid operand for code '%c'", code);
11300 num = REGNO(x) - FIRST_VFP_REGNUM;
11303 output_operand_lossage ("invalid operand for code '%c'", code);
11307 fprintf (stream, "d%d", num >> 1);
11314 output_operand_lossage ("missing operand");
11318 switch (GET_CODE (x))
11321 asm_fprintf (stream, "%r", REGNO (x));
11325 output_memory_reference_mode = GET_MODE (x);
11326 output_address (XEXP (x, 0));
11330 fprintf (stream, "#%s", fp_immediate_constant (x));
11334 gcc_assert (GET_CODE (x) != NEG);
11335 fputc ('#', stream);
11336 output_addr_const (stream, x);
11342 #ifndef AOF_ASSEMBLER
11343 /* Target hook for assembling integer objects. The ARM version needs to
11344 handle word-sized values specially. */
11346 arm_assemble_integer (rtx x, unsigned int size, int aligned_p)
11348 if (size == UNITS_PER_WORD && aligned_p)
11350 fputs ("\t.word\t", asm_out_file);
11351 output_addr_const (asm_out_file, x);
11353 /* Mark symbols as position independent. We only do this in the
11354 .text segment, not in the .data segment. */
11355 if (NEED_GOT_RELOC && flag_pic && making_const_table &&
11356 (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF))
11358 if (GET_CODE (x) == SYMBOL_REF
11359 && (CONSTANT_POOL_ADDRESS_P (x)
11360 || SYMBOL_REF_LOCAL_P (x)))
11361 fputs ("(GOTOFF)", asm_out_file);
11362 else if (GET_CODE (x) == LABEL_REF)
11363 fputs ("(GOTOFF)", asm_out_file);
11365 fputs ("(GOT)", asm_out_file);
11367 fputc ('\n', asm_out_file);
11371 if (arm_vector_mode_supported_p (GET_MODE (x)))
11375 gcc_assert (GET_CODE (x) == CONST_VECTOR);
11377 units = CONST_VECTOR_NUNITS (x);
11379 switch (GET_MODE (x))
11381 case V2SImode: size = 4; break;
11382 case V4HImode: size = 2; break;
11383 case V8QImode: size = 1; break;
11385 gcc_unreachable ();
11388 for (i = 0; i < units; i++)
11392 elt = CONST_VECTOR_ELT (x, i);
11394 (elt, size, i == 0 ? BIGGEST_ALIGNMENT : size * BITS_PER_UNIT, 1);
11400 return default_assemble_integer (x, size, aligned_p);
11404 /* Add a function to the list of static constructors. */
11407 arm_elf_asm_constructor (rtx symbol, int priority ATTRIBUTE_UNUSED)
11409 if (!TARGET_AAPCS_BASED)
11411 default_named_section_asm_out_constructor (symbol, priority);
11415 /* Put these in the .init_array section, using a special relocation. */
11416 switch_to_section (ctors_section);
11417 assemble_align (POINTER_SIZE);
11418 fputs ("\t.word\t", asm_out_file);
11419 output_addr_const (asm_out_file, symbol);
11420 fputs ("(target1)\n", asm_out_file);
11424 /* A finite state machine takes care of noticing whether or not instructions
11425 can be conditionally executed, and thus decrease execution time and code
11426 size by deleting branch instructions. The fsm is controlled by
11427 final_prescan_insn, and controls the actions of ASM_OUTPUT_OPCODE. */
11429 /* The state of the fsm controlling condition codes are:
11430 0: normal, do nothing special
11431 1: make ASM_OUTPUT_OPCODE not output this instruction
11432 2: make ASM_OUTPUT_OPCODE not output this instruction
11433 3: make instructions conditional
11434 4: make instructions conditional
11436 State transitions (state->state by whom under condition):
11437 0 -> 1 final_prescan_insn if the `target' is a label
11438 0 -> 2 final_prescan_insn if the `target' is an unconditional branch
11439 1 -> 3 ASM_OUTPUT_OPCODE after not having output the conditional branch
11440 2 -> 4 ASM_OUTPUT_OPCODE after not having output the conditional branch
11441 3 -> 0 (*targetm.asm_out.internal_label) if the `target' label is reached
11442 (the target label has CODE_LABEL_NUMBER equal to arm_target_label).
11443 4 -> 0 final_prescan_insn if the `target' unconditional branch is reached
11444 (the target insn is arm_target_insn).
11446 If the jump clobbers the conditions then we use states 2 and 4.
11448 A similar thing can be done with conditional return insns.
11450 XXX In case the `target' is an unconditional branch, this conditionalising
11451 of the instructions always reduces code size, but not always execution
11452 time. But then, I want to reduce the code size to somewhere near what
11453 /bin/cc produces. */
11455 /* Returns the index of the ARM condition code string in
11456 `arm_condition_codes'. COMPARISON should be an rtx like
11457 `(eq (...) (...))'. */
11458 static enum arm_cond_code
11459 get_arm_condition_code (rtx comparison)
11461 enum machine_mode mode = GET_MODE (XEXP (comparison, 0));
11463 enum rtx_code comp_code = GET_CODE (comparison);
11465 if (GET_MODE_CLASS (mode) != MODE_CC)
11466 mode = SELECT_CC_MODE (comp_code, XEXP (comparison, 0),
11467 XEXP (comparison, 1));
11471 case CC_DNEmode: code = ARM_NE; goto dominance;
11472 case CC_DEQmode: code = ARM_EQ; goto dominance;
11473 case CC_DGEmode: code = ARM_GE; goto dominance;
11474 case CC_DGTmode: code = ARM_GT; goto dominance;
11475 case CC_DLEmode: code = ARM_LE; goto dominance;
11476 case CC_DLTmode: code = ARM_LT; goto dominance;
11477 case CC_DGEUmode: code = ARM_CS; goto dominance;
11478 case CC_DGTUmode: code = ARM_HI; goto dominance;
11479 case CC_DLEUmode: code = ARM_LS; goto dominance;
11480 case CC_DLTUmode: code = ARM_CC;
11483 gcc_assert (comp_code == EQ || comp_code == NE);
11485 if (comp_code == EQ)
11486 return ARM_INVERSE_CONDITION_CODE (code);
11492 case NE: return ARM_NE;
11493 case EQ: return ARM_EQ;
11494 case GE: return ARM_PL;
11495 case LT: return ARM_MI;
11496 default: gcc_unreachable ();
11502 case NE: return ARM_NE;
11503 case EQ: return ARM_EQ;
11504 default: gcc_unreachable ();
11510 case NE: return ARM_MI;
11511 case EQ: return ARM_PL;
11512 default: gcc_unreachable ();
11517 /* These encodings assume that AC=1 in the FPA system control
11518 byte. This allows us to handle all cases except UNEQ and
11522 case GE: return ARM_GE;
11523 case GT: return ARM_GT;
11524 case LE: return ARM_LS;
11525 case LT: return ARM_MI;
11526 case NE: return ARM_NE;
11527 case EQ: return ARM_EQ;
11528 case ORDERED: return ARM_VC;
11529 case UNORDERED: return ARM_VS;
11530 case UNLT: return ARM_LT;
11531 case UNLE: return ARM_LE;
11532 case UNGT: return ARM_HI;
11533 case UNGE: return ARM_PL;
11534 /* UNEQ and LTGT do not have a representation. */
11535 case UNEQ: /* Fall through. */
11536 case LTGT: /* Fall through. */
11537 default: gcc_unreachable ();
11543 case NE: return ARM_NE;
11544 case EQ: return ARM_EQ;
11545 case GE: return ARM_LE;
11546 case GT: return ARM_LT;
11547 case LE: return ARM_GE;
11548 case LT: return ARM_GT;
11549 case GEU: return ARM_LS;
11550 case GTU: return ARM_CC;
11551 case LEU: return ARM_CS;
11552 case LTU: return ARM_HI;
11553 default: gcc_unreachable ();
11559 case LTU: return ARM_CS;
11560 case GEU: return ARM_CC;
11561 default: gcc_unreachable ();
11567 case NE: return ARM_NE;
11568 case EQ: return ARM_EQ;
11569 case GE: return ARM_GE;
11570 case GT: return ARM_GT;
11571 case LE: return ARM_LE;
11572 case LT: return ARM_LT;
11573 case GEU: return ARM_CS;
11574 case GTU: return ARM_HI;
11575 case LEU: return ARM_LS;
11576 case LTU: return ARM_CC;
11577 default: gcc_unreachable ();
11580 default: gcc_unreachable ();
11585 arm_final_prescan_insn (rtx insn)
11587 /* BODY will hold the body of INSN. */
11588 rtx body = PATTERN (insn);
11590 /* This will be 1 if trying to repeat the trick, and things need to be
11591 reversed if it appears to fail. */
11594 /* JUMP_CLOBBERS will be one implies that the conditions if a branch is
11595 taken are clobbered, even if the rtl suggests otherwise. It also
11596 means that we have to grub around within the jump expression to find
11597 out what the conditions are when the jump isn't taken. */
11598 int jump_clobbers = 0;
11600 /* If we start with a return insn, we only succeed if we find another one. */
11601 int seeking_return = 0;
11603 /* START_INSN will hold the insn from where we start looking. This is the
11604 first insn after the following code_label if REVERSE is true. */
11605 rtx start_insn = insn;
11607 /* If in state 4, check if the target branch is reached, in order to
11608 change back to state 0. */
11609 if (arm_ccfsm_state == 4)
11611 if (insn == arm_target_insn)
11613 arm_target_insn = NULL;
11614 arm_ccfsm_state = 0;
11619 /* If in state 3, it is possible to repeat the trick, if this insn is an
11620 unconditional branch to a label, and immediately following this branch
11621 is the previous target label which is only used once, and the label this
11622 branch jumps to is not too far off. */
11623 if (arm_ccfsm_state == 3)
11625 if (simplejump_p (insn))
11627 start_insn = next_nonnote_insn (start_insn);
11628 if (GET_CODE (start_insn) == BARRIER)
11630 /* XXX Isn't this always a barrier? */
11631 start_insn = next_nonnote_insn (start_insn);
11633 if (GET_CODE (start_insn) == CODE_LABEL
11634 && CODE_LABEL_NUMBER (start_insn) == arm_target_label
11635 && LABEL_NUSES (start_insn) == 1)
11640 else if (GET_CODE (body) == RETURN)
11642 start_insn = next_nonnote_insn (start_insn);
11643 if (GET_CODE (start_insn) == BARRIER)
11644 start_insn = next_nonnote_insn (start_insn);
11645 if (GET_CODE (start_insn) == CODE_LABEL
11646 && CODE_LABEL_NUMBER (start_insn) == arm_target_label
11647 && LABEL_NUSES (start_insn) == 1)
11650 seeking_return = 1;
11659 gcc_assert (!arm_ccfsm_state || reverse);
11660 if (GET_CODE (insn) != JUMP_INSN)
11663 /* This jump might be paralleled with a clobber of the condition codes
11664 the jump should always come first */
11665 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0)
11666 body = XVECEXP (body, 0, 0);
11669 || (GET_CODE (body) == SET && GET_CODE (SET_DEST (body)) == PC
11670 && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE))
11673 int fail = FALSE, succeed = FALSE;
11674 /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */
11675 int then_not_else = TRUE;
11676 rtx this_insn = start_insn, label = 0;
11678 /* If the jump cannot be done with one instruction, we cannot
11679 conditionally execute the instruction in the inverse case. */
11680 if (get_attr_conds (insn) == CONDS_JUMP_CLOB)
11686 /* Register the insn jumped to. */
11689 if (!seeking_return)
11690 label = XEXP (SET_SRC (body), 0);
11692 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == LABEL_REF)
11693 label = XEXP (XEXP (SET_SRC (body), 1), 0);
11694 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == LABEL_REF)
11696 label = XEXP (XEXP (SET_SRC (body), 2), 0);
11697 then_not_else = FALSE;
11699 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == RETURN)
11700 seeking_return = 1;
11701 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == RETURN)
11703 seeking_return = 1;
11704 then_not_else = FALSE;
11707 gcc_unreachable ();
11709 /* See how many insns this branch skips, and what kind of insns. If all
11710 insns are okay, and the label or unconditional branch to the same
11711 label is not too far away, succeed. */
11712 for (insns_skipped = 0;
11713 !fail && !succeed && insns_skipped++ < max_insns_skipped;)
11717 this_insn = next_nonnote_insn (this_insn);
11721 switch (GET_CODE (this_insn))
11724 /* Succeed if it is the target label, otherwise fail since
11725 control falls in from somewhere else. */
11726 if (this_insn == label)
11730 arm_ccfsm_state = 2;
11731 this_insn = next_nonnote_insn (this_insn);
11734 arm_ccfsm_state = 1;
11742 /* Succeed if the following insn is the target label.
11744 If return insns are used then the last insn in a function
11745 will be a barrier. */
11746 this_insn = next_nonnote_insn (this_insn);
11747 if (this_insn && this_insn == label)
11751 arm_ccfsm_state = 2;
11752 this_insn = next_nonnote_insn (this_insn);
11755 arm_ccfsm_state = 1;
11763 /* The AAPCS says that conditional calls should not be
11764 used since they make interworking inefficient (the
11765 linker can't transform BL<cond> into BLX). That's
11766 only a problem if the machine has BLX. */
11773 /* Succeed if the following insn is the target label, or
11774 if the following two insns are a barrier and the
11776 this_insn = next_nonnote_insn (this_insn);
11777 if (this_insn && GET_CODE (this_insn) == BARRIER)
11778 this_insn = next_nonnote_insn (this_insn);
11780 if (this_insn && this_insn == label
11781 && insns_skipped < max_insns_skipped)
11785 arm_ccfsm_state = 2;
11786 this_insn = next_nonnote_insn (this_insn);
11789 arm_ccfsm_state = 1;
11797 /* If this is an unconditional branch to the same label, succeed.
11798 If it is to another label, do nothing. If it is conditional,
11800 /* XXX Probably, the tests for SET and the PC are
11803 scanbody = PATTERN (this_insn);
11804 if (GET_CODE (scanbody) == SET
11805 && GET_CODE (SET_DEST (scanbody)) == PC)
11807 if (GET_CODE (SET_SRC (scanbody)) == LABEL_REF
11808 && XEXP (SET_SRC (scanbody), 0) == label && !reverse)
11810 arm_ccfsm_state = 2;
11813 else if (GET_CODE (SET_SRC (scanbody)) == IF_THEN_ELSE)
11816 /* Fail if a conditional return is undesirable (e.g. on a
11817 StrongARM), but still allow this if optimizing for size. */
11818 else if (GET_CODE (scanbody) == RETURN
11819 && !use_return_insn (TRUE, NULL)
11822 else if (GET_CODE (scanbody) == RETURN
11825 arm_ccfsm_state = 2;
11828 else if (GET_CODE (scanbody) == PARALLEL)
11830 switch (get_attr_conds (this_insn))
11840 fail = TRUE; /* Unrecognized jump (e.g. epilogue). */
11845 /* Instructions using or affecting the condition codes make it
11847 scanbody = PATTERN (this_insn);
11848 if (!(GET_CODE (scanbody) == SET
11849 || GET_CODE (scanbody) == PARALLEL)
11850 || get_attr_conds (this_insn) != CONDS_NOCOND)
11853 /* A conditional cirrus instruction must be followed by
11854 a non Cirrus instruction. However, since we
11855 conditionalize instructions in this function and by
11856 the time we get here we can't add instructions
11857 (nops), because shorten_branches() has already been
11858 called, we will disable conditionalizing Cirrus
11859 instructions to be safe. */
11860 if (GET_CODE (scanbody) != USE
11861 && GET_CODE (scanbody) != CLOBBER
11862 && get_attr_cirrus (this_insn) != CIRRUS_NOT)
11872 if ((!seeking_return) && (arm_ccfsm_state == 1 || reverse))
11873 arm_target_label = CODE_LABEL_NUMBER (label);
11876 gcc_assert (seeking_return || arm_ccfsm_state == 2);
11878 while (this_insn && GET_CODE (PATTERN (this_insn)) == USE)
11880 this_insn = next_nonnote_insn (this_insn);
11881 gcc_assert (!this_insn
11882 || (GET_CODE (this_insn) != BARRIER
11883 && GET_CODE (this_insn) != CODE_LABEL));
11887 /* Oh, dear! we ran off the end.. give up. */
11888 recog (PATTERN (insn), insn, NULL);
11889 arm_ccfsm_state = 0;
11890 arm_target_insn = NULL;
11893 arm_target_insn = this_insn;
11897 gcc_assert (!reverse);
11899 get_arm_condition_code (XEXP (XEXP (XEXP (SET_SRC (body),
11901 if (GET_CODE (XEXP (XEXP (SET_SRC (body), 0), 0)) == AND)
11902 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
11903 if (GET_CODE (XEXP (SET_SRC (body), 0)) == NE)
11904 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
11908 /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from
11911 arm_current_cc = get_arm_condition_code (XEXP (SET_SRC (body),
11915 if (reverse || then_not_else)
11916 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
11919 /* Restore recog_data (getting the attributes of other insns can
11920 destroy this array, but final.c assumes that it remains intact
11921 across this call; since the insn has been recognized already we
11922 call recog direct). */
11923 recog (PATTERN (insn), insn, NULL);
11927 /* Returns true if REGNO is a valid register
11928 for holding a quantity of type MODE. */
11930 arm_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode)
11932 if (GET_MODE_CLASS (mode) == MODE_CC)
11933 return (regno == CC_REGNUM
11934 || (TARGET_HARD_FLOAT && TARGET_VFP
11935 && regno == VFPCC_REGNUM));
11938 /* For the Thumb we only allow values bigger than SImode in
11939 registers 0 - 6, so that there is always a second low
11940 register available to hold the upper part of the value.
11941 We probably we ought to ensure that the register is the
11942 start of an even numbered register pair. */
11943 return (ARM_NUM_REGS (mode) < 2) || (regno < LAST_LO_REGNUM);
11945 if (TARGET_HARD_FLOAT && TARGET_MAVERICK
11946 && IS_CIRRUS_REGNUM (regno))
11947 /* We have outlawed SI values in Cirrus registers because they
11948 reside in the lower 32 bits, but SF values reside in the
11949 upper 32 bits. This causes gcc all sorts of grief. We can't
11950 even split the registers into pairs because Cirrus SI values
11951 get sign extended to 64bits-- aldyh. */
11952 return (GET_MODE_CLASS (mode) == MODE_FLOAT) || (mode == DImode);
11954 if (TARGET_HARD_FLOAT && TARGET_VFP
11955 && IS_VFP_REGNUM (regno))
11957 if (mode == SFmode || mode == SImode)
11960 /* DFmode values are only valid in even register pairs. */
11961 if (mode == DFmode)
11962 return ((regno - FIRST_VFP_REGNUM) & 1) == 0;
11966 if (TARGET_REALLY_IWMMXT)
11968 if (IS_IWMMXT_GR_REGNUM (regno))
11969 return mode == SImode;
11971 if (IS_IWMMXT_REGNUM (regno))
11972 return VALID_IWMMXT_REG_MODE (mode);
11975 /* We allow any value to be stored in the general registers.
11976 Restrict doubleword quantities to even register pairs so that we can
11978 if (regno <= LAST_ARM_REGNUM)
11979 return !(TARGET_LDRD && GET_MODE_SIZE (mode) > 4 && (regno & 1) != 0);
11981 if (regno == FRAME_POINTER_REGNUM
11982 || regno == ARG_POINTER_REGNUM)
11983 /* We only allow integers in the fake hard registers. */
11984 return GET_MODE_CLASS (mode) == MODE_INT;
11986 /* The only registers left are the FPA registers
11987 which we only allow to hold FP values. */
11988 return (TARGET_HARD_FLOAT && TARGET_FPA
11989 && GET_MODE_CLASS (mode) == MODE_FLOAT
11990 && regno >= FIRST_FPA_REGNUM
11991 && regno <= LAST_FPA_REGNUM);
11995 arm_regno_class (int regno)
11999 if (regno == STACK_POINTER_REGNUM)
12001 if (regno == CC_REGNUM)
12008 if ( regno <= LAST_ARM_REGNUM
12009 || regno == FRAME_POINTER_REGNUM
12010 || regno == ARG_POINTER_REGNUM)
12011 return GENERAL_REGS;
12013 if (regno == CC_REGNUM || regno == VFPCC_REGNUM)
12016 if (IS_CIRRUS_REGNUM (regno))
12017 return CIRRUS_REGS;
12019 if (IS_VFP_REGNUM (regno))
12022 if (IS_IWMMXT_REGNUM (regno))
12023 return IWMMXT_REGS;
12025 if (IS_IWMMXT_GR_REGNUM (regno))
12026 return IWMMXT_GR_REGS;
12031 /* Handle a special case when computing the offset
12032 of an argument from the frame pointer. */
12034 arm_debugger_arg_offset (int value, rtx addr)
12038 /* We are only interested if dbxout_parms() failed to compute the offset. */
12042 /* We can only cope with the case where the address is held in a register. */
12043 if (GET_CODE (addr) != REG)
12046 /* If we are using the frame pointer to point at the argument, then
12047 an offset of 0 is correct. */
12048 if (REGNO (addr) == (unsigned) HARD_FRAME_POINTER_REGNUM)
12051 /* If we are using the stack pointer to point at the
12052 argument, then an offset of 0 is correct. */
12053 if ((TARGET_THUMB || !frame_pointer_needed)
12054 && REGNO (addr) == SP_REGNUM)
12057 /* Oh dear. The argument is pointed to by a register rather
12058 than being held in a register, or being stored at a known
12059 offset from the frame pointer. Since GDB only understands
12060 those two kinds of argument we must translate the address
12061 held in the register into an offset from the frame pointer.
12062 We do this by searching through the insns for the function
12063 looking to see where this register gets its value. If the
12064 register is initialized from the frame pointer plus an offset
12065 then we are in luck and we can continue, otherwise we give up.
12067 This code is exercised by producing debugging information
12068 for a function with arguments like this:
12070 double func (double a, double b, int c, double d) {return d;}
12072 Without this code the stab for parameter 'd' will be set to
12073 an offset of 0 from the frame pointer, rather than 8. */
12075 /* The if() statement says:
12077 If the insn is a normal instruction
12078 and if the insn is setting the value in a register
12079 and if the register being set is the register holding the address of the argument
12080 and if the address is computing by an addition
12081 that involves adding to a register
12082 which is the frame pointer
12087 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
12089 if ( GET_CODE (insn) == INSN
12090 && GET_CODE (PATTERN (insn)) == SET
12091 && REGNO (XEXP (PATTERN (insn), 0)) == REGNO (addr)
12092 && GET_CODE (XEXP (PATTERN (insn), 1)) == PLUS
12093 && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 0)) == REG
12094 && REGNO (XEXP (XEXP (PATTERN (insn), 1), 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
12095 && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 1)) == CONST_INT
12098 value = INTVAL (XEXP (XEXP (PATTERN (insn), 1), 1));
12107 warning (0, "unable to compute real location of stacked parameter");
12108 value = 8; /* XXX magic hack */
12114 #define def_mbuiltin(MASK, NAME, TYPE, CODE) \
12117 if ((MASK) & insn_flags) \
12118 lang_hooks.builtin_function ((NAME), (TYPE), (CODE), \
12119 BUILT_IN_MD, NULL, NULL_TREE); \
12123 struct builtin_description
12125 const unsigned int mask;
12126 const enum insn_code icode;
12127 const char * const name;
12128 const enum arm_builtins code;
12129 const enum rtx_code comparison;
12130 const unsigned int flag;
12133 static const struct builtin_description bdesc_2arg[] =
12135 #define IWMMXT_BUILTIN(code, string, builtin) \
12136 { FL_IWMMXT, CODE_FOR_##code, "__builtin_arm_" string, \
12137 ARM_BUILTIN_##builtin, 0, 0 },
12139 IWMMXT_BUILTIN (addv8qi3, "waddb", WADDB)
12140 IWMMXT_BUILTIN (addv4hi3, "waddh", WADDH)
12141 IWMMXT_BUILTIN (addv2si3, "waddw", WADDW)
12142 IWMMXT_BUILTIN (subv8qi3, "wsubb", WSUBB)
12143 IWMMXT_BUILTIN (subv4hi3, "wsubh", WSUBH)
12144 IWMMXT_BUILTIN (subv2si3, "wsubw", WSUBW)
12145 IWMMXT_BUILTIN (ssaddv8qi3, "waddbss", WADDSSB)
12146 IWMMXT_BUILTIN (ssaddv4hi3, "waddhss", WADDSSH)
12147 IWMMXT_BUILTIN (ssaddv2si3, "waddwss", WADDSSW)
12148 IWMMXT_BUILTIN (sssubv8qi3, "wsubbss", WSUBSSB)
12149 IWMMXT_BUILTIN (sssubv4hi3, "wsubhss", WSUBSSH)
12150 IWMMXT_BUILTIN (sssubv2si3, "wsubwss", WSUBSSW)
12151 IWMMXT_BUILTIN (usaddv8qi3, "waddbus", WADDUSB)
12152 IWMMXT_BUILTIN (usaddv4hi3, "waddhus", WADDUSH)
12153 IWMMXT_BUILTIN (usaddv2si3, "waddwus", WADDUSW)
12154 IWMMXT_BUILTIN (ussubv8qi3, "wsubbus", WSUBUSB)
12155 IWMMXT_BUILTIN (ussubv4hi3, "wsubhus", WSUBUSH)
12156 IWMMXT_BUILTIN (ussubv2si3, "wsubwus", WSUBUSW)
12157 IWMMXT_BUILTIN (mulv4hi3, "wmulul", WMULUL)
12158 IWMMXT_BUILTIN (smulv4hi3_highpart, "wmulsm", WMULSM)
12159 IWMMXT_BUILTIN (umulv4hi3_highpart, "wmulum", WMULUM)
12160 IWMMXT_BUILTIN (eqv8qi3, "wcmpeqb", WCMPEQB)
12161 IWMMXT_BUILTIN (eqv4hi3, "wcmpeqh", WCMPEQH)
12162 IWMMXT_BUILTIN (eqv2si3, "wcmpeqw", WCMPEQW)
12163 IWMMXT_BUILTIN (gtuv8qi3, "wcmpgtub", WCMPGTUB)
12164 IWMMXT_BUILTIN (gtuv4hi3, "wcmpgtuh", WCMPGTUH)
12165 IWMMXT_BUILTIN (gtuv2si3, "wcmpgtuw", WCMPGTUW)
12166 IWMMXT_BUILTIN (gtv8qi3, "wcmpgtsb", WCMPGTSB)
12167 IWMMXT_BUILTIN (gtv4hi3, "wcmpgtsh", WCMPGTSH)
12168 IWMMXT_BUILTIN (gtv2si3, "wcmpgtsw", WCMPGTSW)
12169 IWMMXT_BUILTIN (umaxv8qi3, "wmaxub", WMAXUB)
12170 IWMMXT_BUILTIN (smaxv8qi3, "wmaxsb", WMAXSB)
12171 IWMMXT_BUILTIN (umaxv4hi3, "wmaxuh", WMAXUH)
12172 IWMMXT_BUILTIN (smaxv4hi3, "wmaxsh", WMAXSH)
12173 IWMMXT_BUILTIN (umaxv2si3, "wmaxuw", WMAXUW)
12174 IWMMXT_BUILTIN (smaxv2si3, "wmaxsw", WMAXSW)
12175 IWMMXT_BUILTIN (uminv8qi3, "wminub", WMINUB)
12176 IWMMXT_BUILTIN (sminv8qi3, "wminsb", WMINSB)
12177 IWMMXT_BUILTIN (uminv4hi3, "wminuh", WMINUH)
12178 IWMMXT_BUILTIN (sminv4hi3, "wminsh", WMINSH)
12179 IWMMXT_BUILTIN (uminv2si3, "wminuw", WMINUW)
12180 IWMMXT_BUILTIN (sminv2si3, "wminsw", WMINSW)
12181 IWMMXT_BUILTIN (iwmmxt_anddi3, "wand", WAND)
12182 IWMMXT_BUILTIN (iwmmxt_nanddi3, "wandn", WANDN)
12183 IWMMXT_BUILTIN (iwmmxt_iordi3, "wor", WOR)
12184 IWMMXT_BUILTIN (iwmmxt_xordi3, "wxor", WXOR)
12185 IWMMXT_BUILTIN (iwmmxt_uavgv8qi3, "wavg2b", WAVG2B)
12186 IWMMXT_BUILTIN (iwmmxt_uavgv4hi3, "wavg2h", WAVG2H)
12187 IWMMXT_BUILTIN (iwmmxt_uavgrndv8qi3, "wavg2br", WAVG2BR)
12188 IWMMXT_BUILTIN (iwmmxt_uavgrndv4hi3, "wavg2hr", WAVG2HR)
12189 IWMMXT_BUILTIN (iwmmxt_wunpckilb, "wunpckilb", WUNPCKILB)
12190 IWMMXT_BUILTIN (iwmmxt_wunpckilh, "wunpckilh", WUNPCKILH)
12191 IWMMXT_BUILTIN (iwmmxt_wunpckilw, "wunpckilw", WUNPCKILW)
12192 IWMMXT_BUILTIN (iwmmxt_wunpckihb, "wunpckihb", WUNPCKIHB)
12193 IWMMXT_BUILTIN (iwmmxt_wunpckihh, "wunpckihh", WUNPCKIHH)
12194 IWMMXT_BUILTIN (iwmmxt_wunpckihw, "wunpckihw", WUNPCKIHW)
12195 IWMMXT_BUILTIN (iwmmxt_wmadds, "wmadds", WMADDS)
12196 IWMMXT_BUILTIN (iwmmxt_wmaddu, "wmaddu", WMADDU)
12198 #define IWMMXT_BUILTIN2(code, builtin) \
12199 { FL_IWMMXT, CODE_FOR_##code, NULL, ARM_BUILTIN_##builtin, 0, 0 },
12201 IWMMXT_BUILTIN2 (iwmmxt_wpackhss, WPACKHSS)
12202 IWMMXT_BUILTIN2 (iwmmxt_wpackwss, WPACKWSS)
12203 IWMMXT_BUILTIN2 (iwmmxt_wpackdss, WPACKDSS)
12204 IWMMXT_BUILTIN2 (iwmmxt_wpackhus, WPACKHUS)
12205 IWMMXT_BUILTIN2 (iwmmxt_wpackwus, WPACKWUS)
12206 IWMMXT_BUILTIN2 (iwmmxt_wpackdus, WPACKDUS)
12207 IWMMXT_BUILTIN2 (ashlv4hi3_di, WSLLH)
12208 IWMMXT_BUILTIN2 (ashlv4hi3, WSLLHI)
12209 IWMMXT_BUILTIN2 (ashlv2si3_di, WSLLW)
12210 IWMMXT_BUILTIN2 (ashlv2si3, WSLLWI)
12211 IWMMXT_BUILTIN2 (ashldi3_di, WSLLD)
12212 IWMMXT_BUILTIN2 (ashldi3_iwmmxt, WSLLDI)
12213 IWMMXT_BUILTIN2 (lshrv4hi3_di, WSRLH)
12214 IWMMXT_BUILTIN2 (lshrv4hi3, WSRLHI)
12215 IWMMXT_BUILTIN2 (lshrv2si3_di, WSRLW)
12216 IWMMXT_BUILTIN2 (lshrv2si3, WSRLWI)
12217 IWMMXT_BUILTIN2 (lshrdi3_di, WSRLD)
12218 IWMMXT_BUILTIN2 (lshrdi3_iwmmxt, WSRLDI)
12219 IWMMXT_BUILTIN2 (ashrv4hi3_di, WSRAH)
12220 IWMMXT_BUILTIN2 (ashrv4hi3, WSRAHI)
12221 IWMMXT_BUILTIN2 (ashrv2si3_di, WSRAW)
12222 IWMMXT_BUILTIN2 (ashrv2si3, WSRAWI)
12223 IWMMXT_BUILTIN2 (ashrdi3_di, WSRAD)
12224 IWMMXT_BUILTIN2 (ashrdi3_iwmmxt, WSRADI)
12225 IWMMXT_BUILTIN2 (rorv4hi3_di, WRORH)
12226 IWMMXT_BUILTIN2 (rorv4hi3, WRORHI)
12227 IWMMXT_BUILTIN2 (rorv2si3_di, WRORW)
12228 IWMMXT_BUILTIN2 (rorv2si3, WRORWI)
12229 IWMMXT_BUILTIN2 (rordi3_di, WRORD)
12230 IWMMXT_BUILTIN2 (rordi3, WRORDI)
12231 IWMMXT_BUILTIN2 (iwmmxt_wmacuz, WMACUZ)
12232 IWMMXT_BUILTIN2 (iwmmxt_wmacsz, WMACSZ)
12235 static const struct builtin_description bdesc_1arg[] =
12237 IWMMXT_BUILTIN (iwmmxt_tmovmskb, "tmovmskb", TMOVMSKB)
12238 IWMMXT_BUILTIN (iwmmxt_tmovmskh, "tmovmskh", TMOVMSKH)
12239 IWMMXT_BUILTIN (iwmmxt_tmovmskw, "tmovmskw", TMOVMSKW)
12240 IWMMXT_BUILTIN (iwmmxt_waccb, "waccb", WACCB)
12241 IWMMXT_BUILTIN (iwmmxt_wacch, "wacch", WACCH)
12242 IWMMXT_BUILTIN (iwmmxt_waccw, "waccw", WACCW)
12243 IWMMXT_BUILTIN (iwmmxt_wunpckehub, "wunpckehub", WUNPCKEHUB)
12244 IWMMXT_BUILTIN (iwmmxt_wunpckehuh, "wunpckehuh", WUNPCKEHUH)
12245 IWMMXT_BUILTIN (iwmmxt_wunpckehuw, "wunpckehuw", WUNPCKEHUW)
12246 IWMMXT_BUILTIN (iwmmxt_wunpckehsb, "wunpckehsb", WUNPCKEHSB)
12247 IWMMXT_BUILTIN (iwmmxt_wunpckehsh, "wunpckehsh", WUNPCKEHSH)
12248 IWMMXT_BUILTIN (iwmmxt_wunpckehsw, "wunpckehsw", WUNPCKEHSW)
12249 IWMMXT_BUILTIN (iwmmxt_wunpckelub, "wunpckelub", WUNPCKELUB)
12250 IWMMXT_BUILTIN (iwmmxt_wunpckeluh, "wunpckeluh", WUNPCKELUH)
12251 IWMMXT_BUILTIN (iwmmxt_wunpckeluw, "wunpckeluw", WUNPCKELUW)
12252 IWMMXT_BUILTIN (iwmmxt_wunpckelsb, "wunpckelsb", WUNPCKELSB)
12253 IWMMXT_BUILTIN (iwmmxt_wunpckelsh, "wunpckelsh", WUNPCKELSH)
12254 IWMMXT_BUILTIN (iwmmxt_wunpckelsw, "wunpckelsw", WUNPCKELSW)
12257 /* Set up all the iWMMXt builtins. This is
12258 not called if TARGET_IWMMXT is zero. */
12261 arm_init_iwmmxt_builtins (void)
12263 const struct builtin_description * d;
12265 tree endlink = void_list_node;
12267 tree V2SI_type_node = build_vector_type_for_mode (intSI_type_node, V2SImode);
12268 tree V4HI_type_node = build_vector_type_for_mode (intHI_type_node, V4HImode);
12269 tree V8QI_type_node = build_vector_type_for_mode (intQI_type_node, V8QImode);
12272 = build_function_type (integer_type_node,
12273 tree_cons (NULL_TREE, integer_type_node, endlink));
12274 tree v8qi_ftype_v8qi_v8qi_int
12275 = build_function_type (V8QI_type_node,
12276 tree_cons (NULL_TREE, V8QI_type_node,
12277 tree_cons (NULL_TREE, V8QI_type_node,
12278 tree_cons (NULL_TREE,
12281 tree v4hi_ftype_v4hi_int
12282 = build_function_type (V4HI_type_node,
12283 tree_cons (NULL_TREE, V4HI_type_node,
12284 tree_cons (NULL_TREE, integer_type_node,
12286 tree v2si_ftype_v2si_int
12287 = build_function_type (V2SI_type_node,
12288 tree_cons (NULL_TREE, V2SI_type_node,
12289 tree_cons (NULL_TREE, integer_type_node,
12291 tree v2si_ftype_di_di
12292 = build_function_type (V2SI_type_node,
12293 tree_cons (NULL_TREE, long_long_integer_type_node,
12294 tree_cons (NULL_TREE, long_long_integer_type_node,
12296 tree di_ftype_di_int
12297 = build_function_type (long_long_integer_type_node,
12298 tree_cons (NULL_TREE, long_long_integer_type_node,
12299 tree_cons (NULL_TREE, integer_type_node,
12301 tree di_ftype_di_int_int
12302 = build_function_type (long_long_integer_type_node,
12303 tree_cons (NULL_TREE, long_long_integer_type_node,
12304 tree_cons (NULL_TREE, integer_type_node,
12305 tree_cons (NULL_TREE,
12308 tree int_ftype_v8qi
12309 = build_function_type (integer_type_node,
12310 tree_cons (NULL_TREE, V8QI_type_node,
12312 tree int_ftype_v4hi
12313 = build_function_type (integer_type_node,
12314 tree_cons (NULL_TREE, V4HI_type_node,
12316 tree int_ftype_v2si
12317 = build_function_type (integer_type_node,
12318 tree_cons (NULL_TREE, V2SI_type_node,
12320 tree int_ftype_v8qi_int
12321 = build_function_type (integer_type_node,
12322 tree_cons (NULL_TREE, V8QI_type_node,
12323 tree_cons (NULL_TREE, integer_type_node,
12325 tree int_ftype_v4hi_int
12326 = build_function_type (integer_type_node,
12327 tree_cons (NULL_TREE, V4HI_type_node,
12328 tree_cons (NULL_TREE, integer_type_node,
12330 tree int_ftype_v2si_int
12331 = build_function_type (integer_type_node,
12332 tree_cons (NULL_TREE, V2SI_type_node,
12333 tree_cons (NULL_TREE, integer_type_node,
12335 tree v8qi_ftype_v8qi_int_int
12336 = build_function_type (V8QI_type_node,
12337 tree_cons (NULL_TREE, V8QI_type_node,
12338 tree_cons (NULL_TREE, integer_type_node,
12339 tree_cons (NULL_TREE,
12342 tree v4hi_ftype_v4hi_int_int
12343 = build_function_type (V4HI_type_node,
12344 tree_cons (NULL_TREE, V4HI_type_node,
12345 tree_cons (NULL_TREE, integer_type_node,
12346 tree_cons (NULL_TREE,
12349 tree v2si_ftype_v2si_int_int
12350 = build_function_type (V2SI_type_node,
12351 tree_cons (NULL_TREE, V2SI_type_node,
12352 tree_cons (NULL_TREE, integer_type_node,
12353 tree_cons (NULL_TREE,
12356 /* Miscellaneous. */
12357 tree v8qi_ftype_v4hi_v4hi
12358 = build_function_type (V8QI_type_node,
12359 tree_cons (NULL_TREE, V4HI_type_node,
12360 tree_cons (NULL_TREE, V4HI_type_node,
12362 tree v4hi_ftype_v2si_v2si
12363 = build_function_type (V4HI_type_node,
12364 tree_cons (NULL_TREE, V2SI_type_node,
12365 tree_cons (NULL_TREE, V2SI_type_node,
12367 tree v2si_ftype_v4hi_v4hi
12368 = build_function_type (V2SI_type_node,
12369 tree_cons (NULL_TREE, V4HI_type_node,
12370 tree_cons (NULL_TREE, V4HI_type_node,
12372 tree v2si_ftype_v8qi_v8qi
12373 = build_function_type (V2SI_type_node,
12374 tree_cons (NULL_TREE, V8QI_type_node,
12375 tree_cons (NULL_TREE, V8QI_type_node,
12377 tree v4hi_ftype_v4hi_di
12378 = build_function_type (V4HI_type_node,
12379 tree_cons (NULL_TREE, V4HI_type_node,
12380 tree_cons (NULL_TREE,
12381 long_long_integer_type_node,
12383 tree v2si_ftype_v2si_di
12384 = build_function_type (V2SI_type_node,
12385 tree_cons (NULL_TREE, V2SI_type_node,
12386 tree_cons (NULL_TREE,
12387 long_long_integer_type_node,
12389 tree void_ftype_int_int
12390 = build_function_type (void_type_node,
12391 tree_cons (NULL_TREE, integer_type_node,
12392 tree_cons (NULL_TREE, integer_type_node,
12395 = build_function_type (long_long_unsigned_type_node, endlink);
12397 = build_function_type (long_long_integer_type_node,
12398 tree_cons (NULL_TREE, V8QI_type_node,
12401 = build_function_type (long_long_integer_type_node,
12402 tree_cons (NULL_TREE, V4HI_type_node,
12405 = build_function_type (long_long_integer_type_node,
12406 tree_cons (NULL_TREE, V2SI_type_node,
12408 tree v2si_ftype_v4hi
12409 = build_function_type (V2SI_type_node,
12410 tree_cons (NULL_TREE, V4HI_type_node,
12412 tree v4hi_ftype_v8qi
12413 = build_function_type (V4HI_type_node,
12414 tree_cons (NULL_TREE, V8QI_type_node,
12417 tree di_ftype_di_v4hi_v4hi
12418 = build_function_type (long_long_unsigned_type_node,
12419 tree_cons (NULL_TREE,
12420 long_long_unsigned_type_node,
12421 tree_cons (NULL_TREE, V4HI_type_node,
12422 tree_cons (NULL_TREE,
12426 tree di_ftype_v4hi_v4hi
12427 = build_function_type (long_long_unsigned_type_node,
12428 tree_cons (NULL_TREE, V4HI_type_node,
12429 tree_cons (NULL_TREE, V4HI_type_node,
12432 /* Normal vector binops. */
12433 tree v8qi_ftype_v8qi_v8qi
12434 = build_function_type (V8QI_type_node,
12435 tree_cons (NULL_TREE, V8QI_type_node,
12436 tree_cons (NULL_TREE, V8QI_type_node,
12438 tree v4hi_ftype_v4hi_v4hi
12439 = build_function_type (V4HI_type_node,
12440 tree_cons (NULL_TREE, V4HI_type_node,
12441 tree_cons (NULL_TREE, V4HI_type_node,
12443 tree v2si_ftype_v2si_v2si
12444 = build_function_type (V2SI_type_node,
12445 tree_cons (NULL_TREE, V2SI_type_node,
12446 tree_cons (NULL_TREE, V2SI_type_node,
12448 tree di_ftype_di_di
12449 = build_function_type (long_long_unsigned_type_node,
12450 tree_cons (NULL_TREE, long_long_unsigned_type_node,
12451 tree_cons (NULL_TREE,
12452 long_long_unsigned_type_node,
12455 /* Add all builtins that are more or less simple operations on two
12457 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
12459 /* Use one of the operands; the target can have a different mode for
12460 mask-generating compares. */
12461 enum machine_mode mode;
12467 mode = insn_data[d->icode].operand[1].mode;
12472 type = v8qi_ftype_v8qi_v8qi;
12475 type = v4hi_ftype_v4hi_v4hi;
12478 type = v2si_ftype_v2si_v2si;
12481 type = di_ftype_di_di;
12485 gcc_unreachable ();
12488 def_mbuiltin (d->mask, d->name, type, d->code);
12491 /* Add the remaining MMX insns with somewhat more complicated types. */
12492 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wzero", di_ftype_void, ARM_BUILTIN_WZERO);
12493 def_mbuiltin (FL_IWMMXT, "__builtin_arm_setwcx", void_ftype_int_int, ARM_BUILTIN_SETWCX);
12494 def_mbuiltin (FL_IWMMXT, "__builtin_arm_getwcx", int_ftype_int, ARM_BUILTIN_GETWCX);
12496 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSLLH);
12497 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllw", v2si_ftype_v2si_di, ARM_BUILTIN_WSLLW);
12498 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wslld", di_ftype_di_di, ARM_BUILTIN_WSLLD);
12499 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSLLHI);
12500 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllwi", v2si_ftype_v2si_int, ARM_BUILTIN_WSLLWI);
12501 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wslldi", di_ftype_di_int, ARM_BUILTIN_WSLLDI);
12503 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSRLH);
12504 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlw", v2si_ftype_v2si_di, ARM_BUILTIN_WSRLW);
12505 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrld", di_ftype_di_di, ARM_BUILTIN_WSRLD);
12506 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSRLHI);
12507 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlwi", v2si_ftype_v2si_int, ARM_BUILTIN_WSRLWI);
12508 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrldi", di_ftype_di_int, ARM_BUILTIN_WSRLDI);
12510 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrah", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSRAH);
12511 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsraw", v2si_ftype_v2si_di, ARM_BUILTIN_WSRAW);
12512 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrad", di_ftype_di_di, ARM_BUILTIN_WSRAD);
12513 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrahi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSRAHI);
12514 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrawi", v2si_ftype_v2si_int, ARM_BUILTIN_WSRAWI);
12515 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsradi", di_ftype_di_int, ARM_BUILTIN_WSRADI);
12517 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WRORH);
12518 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorw", v2si_ftype_v2si_di, ARM_BUILTIN_WRORW);
12519 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrord", di_ftype_di_di, ARM_BUILTIN_WRORD);
12520 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WRORHI);
12521 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorwi", v2si_ftype_v2si_int, ARM_BUILTIN_WRORWI);
12522 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrordi", di_ftype_di_int, ARM_BUILTIN_WRORDI);
12524 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wshufh", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSHUFH);
12526 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadb", v2si_ftype_v8qi_v8qi, ARM_BUILTIN_WSADB);
12527 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadh", v2si_ftype_v4hi_v4hi, ARM_BUILTIN_WSADH);
12528 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadbz", v2si_ftype_v8qi_v8qi, ARM_BUILTIN_WSADBZ);
12529 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadhz", v2si_ftype_v4hi_v4hi, ARM_BUILTIN_WSADHZ);
12531 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsb", int_ftype_v8qi_int, ARM_BUILTIN_TEXTRMSB);
12532 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsh", int_ftype_v4hi_int, ARM_BUILTIN_TEXTRMSH);
12533 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsw", int_ftype_v2si_int, ARM_BUILTIN_TEXTRMSW);
12534 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmub", int_ftype_v8qi_int, ARM_BUILTIN_TEXTRMUB);
12535 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmuh", int_ftype_v4hi_int, ARM_BUILTIN_TEXTRMUH);
12536 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmuw", int_ftype_v2si_int, ARM_BUILTIN_TEXTRMUW);
12537 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrb", v8qi_ftype_v8qi_int_int, ARM_BUILTIN_TINSRB);
12538 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrh", v4hi_ftype_v4hi_int_int, ARM_BUILTIN_TINSRH);
12539 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrw", v2si_ftype_v2si_int_int, ARM_BUILTIN_TINSRW);
12541 def_mbuiltin (FL_IWMMXT, "__builtin_arm_waccb", di_ftype_v8qi, ARM_BUILTIN_WACCB);
12542 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wacch", di_ftype_v4hi, ARM_BUILTIN_WACCH);
12543 def_mbuiltin (FL_IWMMXT, "__builtin_arm_waccw", di_ftype_v2si, ARM_BUILTIN_WACCW);
12545 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskb", int_ftype_v8qi, ARM_BUILTIN_TMOVMSKB);
12546 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskh", int_ftype_v4hi, ARM_BUILTIN_TMOVMSKH);
12547 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskw", int_ftype_v2si, ARM_BUILTIN_TMOVMSKW);
12549 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackhss", v8qi_ftype_v4hi_v4hi, ARM_BUILTIN_WPACKHSS);
12550 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackhus", v8qi_ftype_v4hi_v4hi, ARM_BUILTIN_WPACKHUS);
12551 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackwus", v4hi_ftype_v2si_v2si, ARM_BUILTIN_WPACKWUS);
12552 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackwss", v4hi_ftype_v2si_v2si, ARM_BUILTIN_WPACKWSS);
12553 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackdus", v2si_ftype_di_di, ARM_BUILTIN_WPACKDUS);
12554 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackdss", v2si_ftype_di_di, ARM_BUILTIN_WPACKDSS);
12556 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehub", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKEHUB);
12557 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehuh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKEHUH);
12558 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehuw", di_ftype_v2si, ARM_BUILTIN_WUNPCKEHUW);
12559 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsb", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKEHSB);
12560 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKEHSH);
12561 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsw", di_ftype_v2si, ARM_BUILTIN_WUNPCKEHSW);
12562 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelub", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKELUB);
12563 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckeluh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKELUH);
12564 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckeluw", di_ftype_v2si, ARM_BUILTIN_WUNPCKELUW);
12565 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsb", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKELSB);
12566 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKELSH);
12567 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsw", di_ftype_v2si, ARM_BUILTIN_WUNPCKELSW);
12569 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacs", di_ftype_di_v4hi_v4hi, ARM_BUILTIN_WMACS);
12570 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacsz", di_ftype_v4hi_v4hi, ARM_BUILTIN_WMACSZ);
12571 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacu", di_ftype_di_v4hi_v4hi, ARM_BUILTIN_WMACU);
12572 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacuz", di_ftype_v4hi_v4hi, ARM_BUILTIN_WMACUZ);
12574 def_mbuiltin (FL_IWMMXT, "__builtin_arm_walign", v8qi_ftype_v8qi_v8qi_int, ARM_BUILTIN_WALIGN);
12575 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmia", di_ftype_di_int_int, ARM_BUILTIN_TMIA);
12576 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiaph", di_ftype_di_int_int, ARM_BUILTIN_TMIAPH);
12577 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiabb", di_ftype_di_int_int, ARM_BUILTIN_TMIABB);
12578 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiabt", di_ftype_di_int_int, ARM_BUILTIN_TMIABT);
12579 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiatb", di_ftype_di_int_int, ARM_BUILTIN_TMIATB);
12580 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiatt", di_ftype_di_int_int, ARM_BUILTIN_TMIATT);
12584 arm_init_tls_builtins (void)
12587 tree nothrow = tree_cons (get_identifier ("nothrow"), NULL, NULL);
12588 tree const_nothrow = tree_cons (get_identifier ("const"), NULL, nothrow);
12590 ftype = build_function_type (ptr_type_node, void_list_node);
12591 lang_hooks.builtin_function ("__builtin_thread_pointer", ftype,
12592 ARM_BUILTIN_THREAD_POINTER, BUILT_IN_MD,
12593 NULL, const_nothrow);
12597 arm_init_builtins (void)
12599 arm_init_tls_builtins ();
12601 if (TARGET_REALLY_IWMMXT)
12602 arm_init_iwmmxt_builtins ();
12605 /* Errors in the source file can cause expand_expr to return const0_rtx
12606 where we expect a vector. To avoid crashing, use one of the vector
12607 clear instructions. */
12610 safe_vector_operand (rtx x, enum machine_mode mode)
12612 if (x != const0_rtx)
12614 x = gen_reg_rtx (mode);
12616 emit_insn (gen_iwmmxt_clrdi (mode == DImode ? x
12617 : gen_rtx_SUBREG (DImode, x, 0)));
12621 /* Subroutine of arm_expand_builtin to take care of binop insns. */
12624 arm_expand_binop_builtin (enum insn_code icode,
12625 tree arglist, rtx target)
12628 tree arg0 = TREE_VALUE (arglist);
12629 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
12630 rtx op0 = expand_normal (arg0);
12631 rtx op1 = expand_normal (arg1);
12632 enum machine_mode tmode = insn_data[icode].operand[0].mode;
12633 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
12634 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
12636 if (VECTOR_MODE_P (mode0))
12637 op0 = safe_vector_operand (op0, mode0);
12638 if (VECTOR_MODE_P (mode1))
12639 op1 = safe_vector_operand (op1, mode1);
12642 || GET_MODE (target) != tmode
12643 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12644 target = gen_reg_rtx (tmode);
12646 gcc_assert (GET_MODE (op0) == mode0 && GET_MODE (op1) == mode1);
12648 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
12649 op0 = copy_to_mode_reg (mode0, op0);
12650 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
12651 op1 = copy_to_mode_reg (mode1, op1);
12653 pat = GEN_FCN (icode) (target, op0, op1);
12660 /* Subroutine of arm_expand_builtin to take care of unop insns. */
12663 arm_expand_unop_builtin (enum insn_code icode,
12664 tree arglist, rtx target, int do_load)
12667 tree arg0 = TREE_VALUE (arglist);
12668 rtx op0 = expand_normal (arg0);
12669 enum machine_mode tmode = insn_data[icode].operand[0].mode;
12670 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
12673 || GET_MODE (target) != tmode
12674 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12675 target = gen_reg_rtx (tmode);
12677 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
12680 if (VECTOR_MODE_P (mode0))
12681 op0 = safe_vector_operand (op0, mode0);
12683 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
12684 op0 = copy_to_mode_reg (mode0, op0);
12687 pat = GEN_FCN (icode) (target, op0);
12694 /* Expand an expression EXP that calls a built-in function,
12695 with result going to TARGET if that's convenient
12696 (and in mode MODE if that's convenient).
12697 SUBTARGET may be used as the target for computing one of EXP's operands.
12698 IGNORE is nonzero if the value is to be ignored. */
12701 arm_expand_builtin (tree exp,
12703 rtx subtarget ATTRIBUTE_UNUSED,
12704 enum machine_mode mode ATTRIBUTE_UNUSED,
12705 int ignore ATTRIBUTE_UNUSED)
12707 const struct builtin_description * d;
12708 enum insn_code icode;
12709 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
12710 tree arglist = TREE_OPERAND (exp, 1);
12718 int fcode = DECL_FUNCTION_CODE (fndecl);
12720 enum machine_mode tmode;
12721 enum machine_mode mode0;
12722 enum machine_mode mode1;
12723 enum machine_mode mode2;
12727 case ARM_BUILTIN_TEXTRMSB:
12728 case ARM_BUILTIN_TEXTRMUB:
12729 case ARM_BUILTIN_TEXTRMSH:
12730 case ARM_BUILTIN_TEXTRMUH:
12731 case ARM_BUILTIN_TEXTRMSW:
12732 case ARM_BUILTIN_TEXTRMUW:
12733 icode = (fcode == ARM_BUILTIN_TEXTRMSB ? CODE_FOR_iwmmxt_textrmsb
12734 : fcode == ARM_BUILTIN_TEXTRMUB ? CODE_FOR_iwmmxt_textrmub
12735 : fcode == ARM_BUILTIN_TEXTRMSH ? CODE_FOR_iwmmxt_textrmsh
12736 : fcode == ARM_BUILTIN_TEXTRMUH ? CODE_FOR_iwmmxt_textrmuh
12737 : CODE_FOR_iwmmxt_textrmw);
12739 arg0 = TREE_VALUE (arglist);
12740 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
12741 op0 = expand_normal (arg0);
12742 op1 = expand_normal (arg1);
12743 tmode = insn_data[icode].operand[0].mode;
12744 mode0 = insn_data[icode].operand[1].mode;
12745 mode1 = insn_data[icode].operand[2].mode;
12747 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
12748 op0 = copy_to_mode_reg (mode0, op0);
12749 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
12751 /* @@@ better error message */
12752 error ("selector must be an immediate");
12753 return gen_reg_rtx (tmode);
12756 || GET_MODE (target) != tmode
12757 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12758 target = gen_reg_rtx (tmode);
12759 pat = GEN_FCN (icode) (target, op0, op1);
12765 case ARM_BUILTIN_TINSRB:
12766 case ARM_BUILTIN_TINSRH:
12767 case ARM_BUILTIN_TINSRW:
12768 icode = (fcode == ARM_BUILTIN_TINSRB ? CODE_FOR_iwmmxt_tinsrb
12769 : fcode == ARM_BUILTIN_TINSRH ? CODE_FOR_iwmmxt_tinsrh
12770 : CODE_FOR_iwmmxt_tinsrw);
12771 arg0 = TREE_VALUE (arglist);
12772 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
12773 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
12774 op0 = expand_normal (arg0);
12775 op1 = expand_normal (arg1);
12776 op2 = expand_normal (arg2);
12777 tmode = insn_data[icode].operand[0].mode;
12778 mode0 = insn_data[icode].operand[1].mode;
12779 mode1 = insn_data[icode].operand[2].mode;
12780 mode2 = insn_data[icode].operand[3].mode;
12782 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
12783 op0 = copy_to_mode_reg (mode0, op0);
12784 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
12785 op1 = copy_to_mode_reg (mode1, op1);
12786 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
12788 /* @@@ better error message */
12789 error ("selector must be an immediate");
12793 || GET_MODE (target) != tmode
12794 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12795 target = gen_reg_rtx (tmode);
12796 pat = GEN_FCN (icode) (target, op0, op1, op2);
12802 case ARM_BUILTIN_SETWCX:
12803 arg0 = TREE_VALUE (arglist);
12804 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
12805 op0 = force_reg (SImode, expand_normal (arg0));
12806 op1 = expand_normal (arg1);
12807 emit_insn (gen_iwmmxt_tmcr (op1, op0));
12810 case ARM_BUILTIN_GETWCX:
12811 arg0 = TREE_VALUE (arglist);
12812 op0 = expand_normal (arg0);
12813 target = gen_reg_rtx (SImode);
12814 emit_insn (gen_iwmmxt_tmrc (target, op0));
12817 case ARM_BUILTIN_WSHUFH:
12818 icode = CODE_FOR_iwmmxt_wshufh;
12819 arg0 = TREE_VALUE (arglist);
12820 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
12821 op0 = expand_normal (arg0);
12822 op1 = expand_normal (arg1);
12823 tmode = insn_data[icode].operand[0].mode;
12824 mode1 = insn_data[icode].operand[1].mode;
12825 mode2 = insn_data[icode].operand[2].mode;
12827 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
12828 op0 = copy_to_mode_reg (mode1, op0);
12829 if (! (*insn_data[icode].operand[2].predicate) (op1, mode2))
12831 /* @@@ better error message */
12832 error ("mask must be an immediate");
12836 || GET_MODE (target) != tmode
12837 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12838 target = gen_reg_rtx (tmode);
12839 pat = GEN_FCN (icode) (target, op0, op1);
12845 case ARM_BUILTIN_WSADB:
12846 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadb, arglist, target);
12847 case ARM_BUILTIN_WSADH:
12848 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadh, arglist, target);
12849 case ARM_BUILTIN_WSADBZ:
12850 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadbz, arglist, target);
12851 case ARM_BUILTIN_WSADHZ:
12852 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadhz, arglist, target);
12854 /* Several three-argument builtins. */
12855 case ARM_BUILTIN_WMACS:
12856 case ARM_BUILTIN_WMACU:
12857 case ARM_BUILTIN_WALIGN:
12858 case ARM_BUILTIN_TMIA:
12859 case ARM_BUILTIN_TMIAPH:
12860 case ARM_BUILTIN_TMIATT:
12861 case ARM_BUILTIN_TMIATB:
12862 case ARM_BUILTIN_TMIABT:
12863 case ARM_BUILTIN_TMIABB:
12864 icode = (fcode == ARM_BUILTIN_WMACS ? CODE_FOR_iwmmxt_wmacs
12865 : fcode == ARM_BUILTIN_WMACU ? CODE_FOR_iwmmxt_wmacu
12866 : fcode == ARM_BUILTIN_TMIA ? CODE_FOR_iwmmxt_tmia
12867 : fcode == ARM_BUILTIN_TMIAPH ? CODE_FOR_iwmmxt_tmiaph
12868 : fcode == ARM_BUILTIN_TMIABB ? CODE_FOR_iwmmxt_tmiabb
12869 : fcode == ARM_BUILTIN_TMIABT ? CODE_FOR_iwmmxt_tmiabt
12870 : fcode == ARM_BUILTIN_TMIATB ? CODE_FOR_iwmmxt_tmiatb
12871 : fcode == ARM_BUILTIN_TMIATT ? CODE_FOR_iwmmxt_tmiatt
12872 : CODE_FOR_iwmmxt_walign);
12873 arg0 = TREE_VALUE (arglist);
12874 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
12875 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
12876 op0 = expand_normal (arg0);
12877 op1 = expand_normal (arg1);
12878 op2 = expand_normal (arg2);
12879 tmode = insn_data[icode].operand[0].mode;
12880 mode0 = insn_data[icode].operand[1].mode;
12881 mode1 = insn_data[icode].operand[2].mode;
12882 mode2 = insn_data[icode].operand[3].mode;
12884 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
12885 op0 = copy_to_mode_reg (mode0, op0);
12886 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
12887 op1 = copy_to_mode_reg (mode1, op1);
12888 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
12889 op2 = copy_to_mode_reg (mode2, op2);
12891 || GET_MODE (target) != tmode
12892 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12893 target = gen_reg_rtx (tmode);
12894 pat = GEN_FCN (icode) (target, op0, op1, op2);
12900 case ARM_BUILTIN_WZERO:
12901 target = gen_reg_rtx (DImode);
12902 emit_insn (gen_iwmmxt_clrdi (target));
12905 case ARM_BUILTIN_THREAD_POINTER:
12906 return arm_load_tp (target);
12912 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
12913 if (d->code == (const enum arm_builtins) fcode)
12914 return arm_expand_binop_builtin (d->icode, arglist, target);
12916 for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
12917 if (d->code == (const enum arm_builtins) fcode)
12918 return arm_expand_unop_builtin (d->icode, arglist, target, 0);
12920 /* @@@ Should really do something sensible here. */
12924 /* Return the number (counting from 0) of
12925 the least significant set bit in MASK. */
12928 number_of_first_bit_set (unsigned mask)
12933 (mask & (1 << bit)) == 0;
12940 /* Emit code to push or pop registers to or from the stack. F is the
12941 assembly file. MASK is the registers to push or pop. PUSH is
12942 nonzero if we should push, and zero if we should pop. For debugging
12943 output, if pushing, adjust CFA_OFFSET by the amount of space added
12944 to the stack. REAL_REGS should have the same number of bits set as
12945 MASK, and will be used instead (in the same order) to describe which
12946 registers were saved - this is used to mark the save slots when we
12947 push high registers after moving them to low registers. */
12949 thumb_pushpop (FILE *f, unsigned long mask, int push, int *cfa_offset,
12950 unsigned long real_regs)
12953 int lo_mask = mask & 0xFF;
12954 int pushed_words = 0;
12958 if (lo_mask == 0 && !push && (mask & (1 << PC_REGNUM)))
12960 /* Special case. Do not generate a POP PC statement here, do it in
12962 thumb_exit (f, -1);
12966 if (ARM_EABI_UNWIND_TABLES && push)
12968 fprintf (f, "\t.save\t{");
12969 for (regno = 0; regno < 15; regno++)
12971 if (real_regs & (1 << regno))
12973 if (real_regs & ((1 << regno) -1))
12975 asm_fprintf (f, "%r", regno);
12978 fprintf (f, "}\n");
12981 fprintf (f, "\t%s\t{", push ? "push" : "pop");
12983 /* Look at the low registers first. */
12984 for (regno = 0; regno <= LAST_LO_REGNUM; regno++, lo_mask >>= 1)
12988 asm_fprintf (f, "%r", regno);
12990 if ((lo_mask & ~1) != 0)
12997 if (push && (mask & (1 << LR_REGNUM)))
12999 /* Catch pushing the LR. */
13003 asm_fprintf (f, "%r", LR_REGNUM);
13007 else if (!push && (mask & (1 << PC_REGNUM)))
13009 /* Catch popping the PC. */
13010 if (TARGET_INTERWORK || TARGET_BACKTRACE
13011 || current_function_calls_eh_return)
13013 /* The PC is never poped directly, instead
13014 it is popped into r3 and then BX is used. */
13015 fprintf (f, "}\n");
13017 thumb_exit (f, -1);
13026 asm_fprintf (f, "%r", PC_REGNUM);
13030 fprintf (f, "}\n");
13032 if (push && pushed_words && dwarf2out_do_frame ())
13034 char *l = dwarf2out_cfi_label ();
13035 int pushed_mask = real_regs;
13037 *cfa_offset += pushed_words * 4;
13038 dwarf2out_def_cfa (l, SP_REGNUM, *cfa_offset);
13041 pushed_mask = real_regs;
13042 for (regno = 0; regno <= 14; regno++, pushed_mask >>= 1)
13044 if (pushed_mask & 1)
13045 dwarf2out_reg_save (l, regno, 4 * pushed_words++ - *cfa_offset);
13050 /* Generate code to return from a thumb function.
13051 If 'reg_containing_return_addr' is -1, then the return address is
13052 actually on the stack, at the stack pointer. */
13054 thumb_exit (FILE *f, int reg_containing_return_addr)
13056 unsigned regs_available_for_popping;
13057 unsigned regs_to_pop;
13059 unsigned available;
13063 int restore_a4 = FALSE;
13065 /* Compute the registers we need to pop. */
13069 if (reg_containing_return_addr == -1)
13071 regs_to_pop |= 1 << LR_REGNUM;
13075 if (TARGET_BACKTRACE)
13077 /* Restore the (ARM) frame pointer and stack pointer. */
13078 regs_to_pop |= (1 << ARM_HARD_FRAME_POINTER_REGNUM) | (1 << SP_REGNUM);
13082 /* If there is nothing to pop then just emit the BX instruction and
13084 if (pops_needed == 0)
13086 if (current_function_calls_eh_return)
13087 asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, ARM_EH_STACKADJ_REGNUM);
13089 asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
13092 /* Otherwise if we are not supporting interworking and we have not created
13093 a backtrace structure and the function was not entered in ARM mode then
13094 just pop the return address straight into the PC. */
13095 else if (!TARGET_INTERWORK
13096 && !TARGET_BACKTRACE
13097 && !is_called_in_ARM_mode (current_function_decl)
13098 && !current_function_calls_eh_return)
13100 asm_fprintf (f, "\tpop\t{%r}\n", PC_REGNUM);
13104 /* Find out how many of the (return) argument registers we can corrupt. */
13105 regs_available_for_popping = 0;
13107 /* If returning via __builtin_eh_return, the bottom three registers
13108 all contain information needed for the return. */
13109 if (current_function_calls_eh_return)
13113 /* If we can deduce the registers used from the function's
13114 return value. This is more reliable that examining
13115 regs_ever_live[] because that will be set if the register is
13116 ever used in the function, not just if the register is used
13117 to hold a return value. */
13119 if (current_function_return_rtx != 0)
13120 mode = GET_MODE (current_function_return_rtx);
13122 mode = DECL_MODE (DECL_RESULT (current_function_decl));
13124 size = GET_MODE_SIZE (mode);
13128 /* In a void function we can use any argument register.
13129 In a function that returns a structure on the stack
13130 we can use the second and third argument registers. */
13131 if (mode == VOIDmode)
13132 regs_available_for_popping =
13133 (1 << ARG_REGISTER (1))
13134 | (1 << ARG_REGISTER (2))
13135 | (1 << ARG_REGISTER (3));
13137 regs_available_for_popping =
13138 (1 << ARG_REGISTER (2))
13139 | (1 << ARG_REGISTER (3));
13141 else if (size <= 4)
13142 regs_available_for_popping =
13143 (1 << ARG_REGISTER (2))
13144 | (1 << ARG_REGISTER (3));
13145 else if (size <= 8)
13146 regs_available_for_popping =
13147 (1 << ARG_REGISTER (3));
13150 /* Match registers to be popped with registers into which we pop them. */
13151 for (available = regs_available_for_popping,
13152 required = regs_to_pop;
13153 required != 0 && available != 0;
13154 available &= ~(available & - available),
13155 required &= ~(required & - required))
13158 /* If we have any popping registers left over, remove them. */
13160 regs_available_for_popping &= ~available;
13162 /* Otherwise if we need another popping register we can use
13163 the fourth argument register. */
13164 else if (pops_needed)
13166 /* If we have not found any free argument registers and
13167 reg a4 contains the return address, we must move it. */
13168 if (regs_available_for_popping == 0
13169 && reg_containing_return_addr == LAST_ARG_REGNUM)
13171 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM);
13172 reg_containing_return_addr = LR_REGNUM;
13174 else if (size > 12)
13176 /* Register a4 is being used to hold part of the return value,
13177 but we have dire need of a free, low register. */
13180 asm_fprintf (f, "\tmov\t%r, %r\n",IP_REGNUM, LAST_ARG_REGNUM);
13183 if (reg_containing_return_addr != LAST_ARG_REGNUM)
13185 /* The fourth argument register is available. */
13186 regs_available_for_popping |= 1 << LAST_ARG_REGNUM;
13192 /* Pop as many registers as we can. */
13193 thumb_pushpop (f, regs_available_for_popping, FALSE, NULL,
13194 regs_available_for_popping);
13196 /* Process the registers we popped. */
13197 if (reg_containing_return_addr == -1)
13199 /* The return address was popped into the lowest numbered register. */
13200 regs_to_pop &= ~(1 << LR_REGNUM);
13202 reg_containing_return_addr =
13203 number_of_first_bit_set (regs_available_for_popping);
13205 /* Remove this register for the mask of available registers, so that
13206 the return address will not be corrupted by further pops. */
13207 regs_available_for_popping &= ~(1 << reg_containing_return_addr);
13210 /* If we popped other registers then handle them here. */
13211 if (regs_available_for_popping)
13215 /* Work out which register currently contains the frame pointer. */
13216 frame_pointer = number_of_first_bit_set (regs_available_for_popping);
13218 /* Move it into the correct place. */
13219 asm_fprintf (f, "\tmov\t%r, %r\n",
13220 ARM_HARD_FRAME_POINTER_REGNUM, frame_pointer);
13222 /* (Temporarily) remove it from the mask of popped registers. */
13223 regs_available_for_popping &= ~(1 << frame_pointer);
13224 regs_to_pop &= ~(1 << ARM_HARD_FRAME_POINTER_REGNUM);
13226 if (regs_available_for_popping)
13230 /* We popped the stack pointer as well,
13231 find the register that contains it. */
13232 stack_pointer = number_of_first_bit_set (regs_available_for_popping);
13234 /* Move it into the stack register. */
13235 asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, stack_pointer);
13237 /* At this point we have popped all necessary registers, so
13238 do not worry about restoring regs_available_for_popping
13239 to its correct value:
13241 assert (pops_needed == 0)
13242 assert (regs_available_for_popping == (1 << frame_pointer))
13243 assert (regs_to_pop == (1 << STACK_POINTER)) */
13247 /* Since we have just move the popped value into the frame
13248 pointer, the popping register is available for reuse, and
13249 we know that we still have the stack pointer left to pop. */
13250 regs_available_for_popping |= (1 << frame_pointer);
13254 /* If we still have registers left on the stack, but we no longer have
13255 any registers into which we can pop them, then we must move the return
13256 address into the link register and make available the register that
13258 if (regs_available_for_popping == 0 && pops_needed > 0)
13260 regs_available_for_popping |= 1 << reg_containing_return_addr;
13262 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM,
13263 reg_containing_return_addr);
13265 reg_containing_return_addr = LR_REGNUM;
13268 /* If we have registers left on the stack then pop some more.
13269 We know that at most we will want to pop FP and SP. */
13270 if (pops_needed > 0)
13275 thumb_pushpop (f, regs_available_for_popping, FALSE, NULL,
13276 regs_available_for_popping);
13278 /* We have popped either FP or SP.
13279 Move whichever one it is into the correct register. */
13280 popped_into = number_of_first_bit_set (regs_available_for_popping);
13281 move_to = number_of_first_bit_set (regs_to_pop);
13283 asm_fprintf (f, "\tmov\t%r, %r\n", move_to, popped_into);
13285 regs_to_pop &= ~(1 << move_to);
13290 /* If we still have not popped everything then we must have only
13291 had one register available to us and we are now popping the SP. */
13292 if (pops_needed > 0)
13296 thumb_pushpop (f, regs_available_for_popping, FALSE, NULL,
13297 regs_available_for_popping);
13299 popped_into = number_of_first_bit_set (regs_available_for_popping);
13301 asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, popped_into);
13303 assert (regs_to_pop == (1 << STACK_POINTER))
13304 assert (pops_needed == 1)
13308 /* If necessary restore the a4 register. */
13311 if (reg_containing_return_addr != LR_REGNUM)
13313 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM);
13314 reg_containing_return_addr = LR_REGNUM;
13317 asm_fprintf (f, "\tmov\t%r, %r\n", LAST_ARG_REGNUM, IP_REGNUM);
13320 if (current_function_calls_eh_return)
13321 asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, ARM_EH_STACKADJ_REGNUM);
13323 /* Return to caller. */
13324 asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
13329 thumb_final_prescan_insn (rtx insn)
13331 if (flag_print_asm_name)
13332 asm_fprintf (asm_out_file, "%@ 0x%04x\n",
13333 INSN_ADDRESSES (INSN_UID (insn)));
13337 thumb_shiftable_const (unsigned HOST_WIDE_INT val)
13339 unsigned HOST_WIDE_INT mask = 0xff;
13342 if (val == 0) /* XXX */
13345 for (i = 0; i < 25; i++)
13346 if ((val & (mask << i)) == val)
13352 /* Returns nonzero if the current function contains,
13353 or might contain a far jump. */
13355 thumb_far_jump_used_p (void)
13359 /* This test is only important for leaf functions. */
13360 /* assert (!leaf_function_p ()); */
13362 /* If we have already decided that far jumps may be used,
13363 do not bother checking again, and always return true even if
13364 it turns out that they are not being used. Once we have made
13365 the decision that far jumps are present (and that hence the link
13366 register will be pushed onto the stack) we cannot go back on it. */
13367 if (cfun->machine->far_jump_used)
13370 /* If this function is not being called from the prologue/epilogue
13371 generation code then it must be being called from the
13372 INITIAL_ELIMINATION_OFFSET macro. */
13373 if (!(ARM_DOUBLEWORD_ALIGN || reload_completed))
13375 /* In this case we know that we are being asked about the elimination
13376 of the arg pointer register. If that register is not being used,
13377 then there are no arguments on the stack, and we do not have to
13378 worry that a far jump might force the prologue to push the link
13379 register, changing the stack offsets. In this case we can just
13380 return false, since the presence of far jumps in the function will
13381 not affect stack offsets.
13383 If the arg pointer is live (or if it was live, but has now been
13384 eliminated and so set to dead) then we do have to test to see if
13385 the function might contain a far jump. This test can lead to some
13386 false negatives, since before reload is completed, then length of
13387 branch instructions is not known, so gcc defaults to returning their
13388 longest length, which in turn sets the far jump attribute to true.
13390 A false negative will not result in bad code being generated, but it
13391 will result in a needless push and pop of the link register. We
13392 hope that this does not occur too often.
13394 If we need doubleword stack alignment this could affect the other
13395 elimination offsets so we can't risk getting it wrong. */
13396 if (regs_ever_live [ARG_POINTER_REGNUM])
13397 cfun->machine->arg_pointer_live = 1;
13398 else if (!cfun->machine->arg_pointer_live)
13402 /* Check to see if the function contains a branch
13403 insn with the far jump attribute set. */
13404 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
13406 if (GET_CODE (insn) == JUMP_INSN
13407 /* Ignore tablejump patterns. */
13408 && GET_CODE (PATTERN (insn)) != ADDR_VEC
13409 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
13410 && get_attr_far_jump (insn) == FAR_JUMP_YES
13413 /* Record the fact that we have decided that
13414 the function does use far jumps. */
13415 cfun->machine->far_jump_used = 1;
13423 /* Return nonzero if FUNC must be entered in ARM mode. */
13425 is_called_in_ARM_mode (tree func)
13427 gcc_assert (TREE_CODE (func) == FUNCTION_DECL);
13429 /* Ignore the problem about functions whose address is taken. */
13430 if (TARGET_CALLEE_INTERWORKING && TREE_PUBLIC (func))
13434 return lookup_attribute ("interfacearm", DECL_ATTRIBUTES (func)) != NULL_TREE;
13440 /* The bits which aren't usefully expanded as rtl. */
13442 thumb_unexpanded_epilogue (void)
13445 unsigned long live_regs_mask = 0;
13446 int high_regs_pushed = 0;
13447 int had_to_push_lr;
13450 if (return_used_this_function)
13453 if (IS_NAKED (arm_current_func_type ()))
13456 live_regs_mask = thumb_compute_save_reg_mask ();
13457 high_regs_pushed = bit_count (live_regs_mask & 0x0f00);
13459 /* If we can deduce the registers used from the function's return value.
13460 This is more reliable that examining regs_ever_live[] because that
13461 will be set if the register is ever used in the function, not just if
13462 the register is used to hold a return value. */
13463 size = arm_size_return_regs ();
13465 /* The prolog may have pushed some high registers to use as
13466 work registers. e.g. the testsuite file:
13467 gcc/testsuite/gcc/gcc.c-torture/execute/complex-2.c
13468 compiles to produce:
13469 push {r4, r5, r6, r7, lr}
13473 as part of the prolog. We have to undo that pushing here. */
13475 if (high_regs_pushed)
13477 unsigned long mask = live_regs_mask & 0xff;
13480 /* The available low registers depend on the size of the value we are
13488 /* Oh dear! We have no low registers into which we can pop
13491 ("no low registers available for popping high registers");
13493 for (next_hi_reg = 8; next_hi_reg < 13; next_hi_reg++)
13494 if (live_regs_mask & (1 << next_hi_reg))
13497 while (high_regs_pushed)
13499 /* Find lo register(s) into which the high register(s) can
13501 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
13503 if (mask & (1 << regno))
13504 high_regs_pushed--;
13505 if (high_regs_pushed == 0)
13509 mask &= (2 << regno) - 1; /* A noop if regno == 8 */
13511 /* Pop the values into the low register(s). */
13512 thumb_pushpop (asm_out_file, mask, 0, NULL, mask);
13514 /* Move the value(s) into the high registers. */
13515 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
13517 if (mask & (1 << regno))
13519 asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", next_hi_reg,
13522 for (next_hi_reg++; next_hi_reg < 13; next_hi_reg++)
13523 if (live_regs_mask & (1 << next_hi_reg))
13528 live_regs_mask &= ~0x0f00;
13531 had_to_push_lr = (live_regs_mask & (1 << LR_REGNUM)) != 0;
13532 live_regs_mask &= 0xff;
13534 if (current_function_pretend_args_size == 0 || TARGET_BACKTRACE)
13536 /* Pop the return address into the PC. */
13537 if (had_to_push_lr)
13538 live_regs_mask |= 1 << PC_REGNUM;
13540 /* Either no argument registers were pushed or a backtrace
13541 structure was created which includes an adjusted stack
13542 pointer, so just pop everything. */
13543 if (live_regs_mask)
13544 thumb_pushpop (asm_out_file, live_regs_mask, FALSE, NULL,
13547 /* We have either just popped the return address into the
13548 PC or it is was kept in LR for the entire function. */
13549 if (!had_to_push_lr)
13550 thumb_exit (asm_out_file, LR_REGNUM);
13554 /* Pop everything but the return address. */
13555 if (live_regs_mask)
13556 thumb_pushpop (asm_out_file, live_regs_mask, FALSE, NULL,
13559 if (had_to_push_lr)
13563 /* We have no free low regs, so save one. */
13564 asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", IP_REGNUM,
13568 /* Get the return address into a temporary register. */
13569 thumb_pushpop (asm_out_file, 1 << LAST_ARG_REGNUM, 0, NULL,
13570 1 << LAST_ARG_REGNUM);
13574 /* Move the return address to lr. */
13575 asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", LR_REGNUM,
13577 /* Restore the low register. */
13578 asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", LAST_ARG_REGNUM,
13583 regno = LAST_ARG_REGNUM;
13588 /* Remove the argument registers that were pushed onto the stack. */
13589 asm_fprintf (asm_out_file, "\tadd\t%r, %r, #%d\n",
13590 SP_REGNUM, SP_REGNUM,
13591 current_function_pretend_args_size);
13593 thumb_exit (asm_out_file, regno);
13599 /* Functions to save and restore machine-specific function data. */
13600 static struct machine_function *
13601 arm_init_machine_status (void)
13603 struct machine_function *machine;
13604 machine = (machine_function *) ggc_alloc_cleared (sizeof (machine_function));
13606 #if ARM_FT_UNKNOWN != 0
13607 machine->func_type = ARM_FT_UNKNOWN;
13612 /* Return an RTX indicating where the return address to the
13613 calling function can be found. */
13615 arm_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
13620 return get_hard_reg_initial_val (Pmode, LR_REGNUM);
13623 /* Do anything needed before RTL is emitted for each function. */
13625 arm_init_expanders (void)
13627 /* Arrange to initialize and mark the machine per-function status. */
13628 init_machine_status = arm_init_machine_status;
13630 /* This is to stop the combine pass optimizing away the alignment
13631 adjustment of va_arg. */
13632 /* ??? It is claimed that this should not be necessary. */
13634 mark_reg_pointer (arg_pointer_rtx, PARM_BOUNDARY);
13638 /* Like arm_compute_initial_elimination offset. Simpler because there
13639 isn't an ABI specified frame pointer for Thumb. Instead, we set it
13640 to point at the base of the local variables after static stack
13641 space for a function has been allocated. */
13644 thumb_compute_initial_elimination_offset (unsigned int from, unsigned int to)
13646 arm_stack_offsets *offsets;
13648 offsets = arm_get_frame_offsets ();
13652 case ARG_POINTER_REGNUM:
13655 case STACK_POINTER_REGNUM:
13656 return offsets->outgoing_args - offsets->saved_args;
13658 case FRAME_POINTER_REGNUM:
13659 return offsets->soft_frame - offsets->saved_args;
13661 case ARM_HARD_FRAME_POINTER_REGNUM:
13662 return offsets->saved_regs - offsets->saved_args;
13664 case THUMB_HARD_FRAME_POINTER_REGNUM:
13665 return offsets->locals_base - offsets->saved_args;
13668 gcc_unreachable ();
13672 case FRAME_POINTER_REGNUM:
13675 case STACK_POINTER_REGNUM:
13676 return offsets->outgoing_args - offsets->soft_frame;
13678 case ARM_HARD_FRAME_POINTER_REGNUM:
13679 return offsets->saved_regs - offsets->soft_frame;
13681 case THUMB_HARD_FRAME_POINTER_REGNUM:
13682 return offsets->locals_base - offsets->soft_frame;
13685 gcc_unreachable ();
13690 gcc_unreachable ();
13695 /* Generate the rest of a function's prologue. */
13697 thumb_expand_prologue (void)
13701 HOST_WIDE_INT amount;
13702 arm_stack_offsets *offsets;
13703 unsigned long func_type;
13705 unsigned long live_regs_mask;
13707 func_type = arm_current_func_type ();
13709 /* Naked functions don't have prologues. */
13710 if (IS_NAKED (func_type))
13713 if (IS_INTERRUPT (func_type))
13715 error ("interrupt Service Routines cannot be coded in Thumb mode");
13719 live_regs_mask = thumb_compute_save_reg_mask ();
13720 /* Load the pic register before setting the frame pointer,
13721 so we can use r7 as a temporary work register. */
13722 if (flag_pic && arm_pic_register != INVALID_REGNUM)
13723 arm_load_pic_register (live_regs_mask);
13725 if (!frame_pointer_needed && CALLER_INTERWORKING_SLOT_SIZE > 0)
13726 emit_move_insn (gen_rtx_REG (Pmode, ARM_HARD_FRAME_POINTER_REGNUM),
13727 stack_pointer_rtx);
13729 offsets = arm_get_frame_offsets ();
13730 amount = offsets->outgoing_args - offsets->saved_regs;
13735 insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
13736 GEN_INT (- amount)));
13737 RTX_FRAME_RELATED_P (insn) = 1;
13743 /* The stack decrement is too big for an immediate value in a single
13744 insn. In theory we could issue multiple subtracts, but after
13745 three of them it becomes more space efficient to place the full
13746 value in the constant pool and load into a register. (Also the
13747 ARM debugger really likes to see only one stack decrement per
13748 function). So instead we look for a scratch register into which
13749 we can load the decrement, and then we subtract this from the
13750 stack pointer. Unfortunately on the thumb the only available
13751 scratch registers are the argument registers, and we cannot use
13752 these as they may hold arguments to the function. Instead we
13753 attempt to locate a call preserved register which is used by this
13754 function. If we can find one, then we know that it will have
13755 been pushed at the start of the prologue and so we can corrupt
13757 for (regno = LAST_ARG_REGNUM + 1; regno <= LAST_LO_REGNUM; regno++)
13758 if (live_regs_mask & (1 << regno)
13759 && !(frame_pointer_needed
13760 && (regno == THUMB_HARD_FRAME_POINTER_REGNUM)))
13763 if (regno > LAST_LO_REGNUM) /* Very unlikely. */
13765 rtx spare = gen_rtx_REG (SImode, IP_REGNUM);
13767 /* Choose an arbitrary, non-argument low register. */
13768 reg = gen_rtx_REG (SImode, LAST_LO_REGNUM);
13770 /* Save it by copying it into a high, scratch register. */
13771 emit_insn (gen_movsi (spare, reg));
13772 /* Add a USE to stop propagate_one_insn() from barfing. */
13773 emit_insn (gen_prologue_use (spare));
13775 /* Decrement the stack. */
13776 emit_insn (gen_movsi (reg, GEN_INT (- amount)));
13777 insn = emit_insn (gen_addsi3 (stack_pointer_rtx,
13778 stack_pointer_rtx, reg));
13779 RTX_FRAME_RELATED_P (insn) = 1;
13780 dwarf = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
13781 plus_constant (stack_pointer_rtx,
13783 RTX_FRAME_RELATED_P (dwarf) = 1;
13785 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
13788 /* Restore the low register's original value. */
13789 emit_insn (gen_movsi (reg, spare));
13791 /* Emit a USE of the restored scratch register, so that flow
13792 analysis will not consider the restore redundant. The
13793 register won't be used again in this function and isn't
13794 restored by the epilogue. */
13795 emit_insn (gen_prologue_use (reg));
13799 reg = gen_rtx_REG (SImode, regno);
13801 emit_insn (gen_movsi (reg, GEN_INT (- amount)));
13803 insn = emit_insn (gen_addsi3 (stack_pointer_rtx,
13804 stack_pointer_rtx, reg));
13805 RTX_FRAME_RELATED_P (insn) = 1;
13806 dwarf = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
13807 plus_constant (stack_pointer_rtx,
13809 RTX_FRAME_RELATED_P (dwarf) = 1;
13811 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
13817 if (frame_pointer_needed)
13819 amount = offsets->outgoing_args - offsets->locals_base;
13822 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
13823 stack_pointer_rtx, GEN_INT (amount)));
13826 emit_insn (gen_movsi (hard_frame_pointer_rtx, GEN_INT (amount)));
13827 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
13828 hard_frame_pointer_rtx,
13829 stack_pointer_rtx));
13830 dwarf = gen_rtx_SET (VOIDmode, hard_frame_pointer_rtx,
13831 plus_constant (stack_pointer_rtx, amount));
13832 RTX_FRAME_RELATED_P (dwarf) = 1;
13833 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
13837 RTX_FRAME_RELATED_P (insn) = 1;
13840 /* If we are profiling, make sure no instructions are scheduled before
13841 the call to mcount. Similarly if the user has requested no
13842 scheduling in the prolog. Similarly if we want non-call exceptions
13843 using the EABI unwinder, to prevent faulting instructions from being
13844 swapped with a stack adjustment. */
13845 if (current_function_profile || !TARGET_SCHED_PROLOG
13846 || (ARM_EABI_UNWIND_TABLES && flag_non_call_exceptions))
13847 emit_insn (gen_blockage ());
13849 cfun->machine->lr_save_eliminated = !thumb_force_lr_save ();
13850 if (live_regs_mask & 0xff)
13851 cfun->machine->lr_save_eliminated = 0;
13853 /* If the link register is being kept alive, with the return address in it,
13854 then make sure that it does not get reused by the ce2 pass. */
13855 if (cfun->machine->lr_save_eliminated)
13856 emit_insn (gen_prologue_use (gen_rtx_REG (SImode, LR_REGNUM)));
13861 thumb_expand_epilogue (void)
13863 HOST_WIDE_INT amount;
13864 arm_stack_offsets *offsets;
13867 /* Naked functions don't have prologues. */
13868 if (IS_NAKED (arm_current_func_type ()))
13871 offsets = arm_get_frame_offsets ();
13872 amount = offsets->outgoing_args - offsets->saved_regs;
13874 if (frame_pointer_needed)
13876 emit_insn (gen_movsi (stack_pointer_rtx, hard_frame_pointer_rtx));
13877 amount = offsets->locals_base - offsets->saved_regs;
13880 gcc_assert (amount >= 0);
13884 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
13885 GEN_INT (amount)));
13888 /* r3 is always free in the epilogue. */
13889 rtx reg = gen_rtx_REG (SImode, LAST_ARG_REGNUM);
13891 emit_insn (gen_movsi (reg, GEN_INT (amount)));
13892 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, reg));
13896 /* Emit a USE (stack_pointer_rtx), so that
13897 the stack adjustment will not be deleted. */
13898 emit_insn (gen_prologue_use (stack_pointer_rtx));
13900 if (current_function_profile || !TARGET_SCHED_PROLOG)
13901 emit_insn (gen_blockage ());
13903 /* Emit a clobber for each insn that will be restored in the epilogue,
13904 so that flow2 will get register lifetimes correct. */
13905 for (regno = 0; regno < 13; regno++)
13906 if (regs_ever_live[regno] && !call_used_regs[regno])
13907 emit_insn (gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, regno)));
13909 if (! regs_ever_live[LR_REGNUM])
13910 emit_insn (gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, LR_REGNUM)));
13914 thumb_output_function_prologue (FILE *f, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
13916 unsigned long live_regs_mask = 0;
13917 unsigned long l_mask;
13918 unsigned high_regs_pushed = 0;
13919 int cfa_offset = 0;
13922 if (IS_NAKED (arm_current_func_type ()))
13925 if (is_called_in_ARM_mode (current_function_decl))
13929 gcc_assert (GET_CODE (DECL_RTL (current_function_decl)) == MEM);
13930 gcc_assert (GET_CODE (XEXP (DECL_RTL (current_function_decl), 0))
13932 name = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
13934 /* Generate code sequence to switch us into Thumb mode. */
13935 /* The .code 32 directive has already been emitted by
13936 ASM_DECLARE_FUNCTION_NAME. */
13937 asm_fprintf (f, "\torr\t%r, %r, #1\n", IP_REGNUM, PC_REGNUM);
13938 asm_fprintf (f, "\tbx\t%r\n", IP_REGNUM);
13940 /* Generate a label, so that the debugger will notice the
13941 change in instruction sets. This label is also used by
13942 the assembler to bypass the ARM code when this function
13943 is called from a Thumb encoded function elsewhere in the
13944 same file. Hence the definition of STUB_NAME here must
13945 agree with the definition in gas/config/tc-arm.c. */
13947 #define STUB_NAME ".real_start_of"
13949 fprintf (f, "\t.code\t16\n");
13951 if (arm_dllexport_name_p (name))
13952 name = arm_strip_name_encoding (name);
13954 asm_fprintf (f, "\t.globl %s%U%s\n", STUB_NAME, name);
13955 fprintf (f, "\t.thumb_func\n");
13956 asm_fprintf (f, "%s%U%s:\n", STUB_NAME, name);
13959 if (current_function_pretend_args_size)
13961 /* Output unwind directive for the stack adjustment. */
13962 if (ARM_EABI_UNWIND_TABLES)
13963 fprintf (f, "\t.pad #%d\n",
13964 current_function_pretend_args_size);
13966 if (cfun->machine->uses_anonymous_args)
13970 fprintf (f, "\tpush\t{");
13972 num_pushes = ARM_NUM_INTS (current_function_pretend_args_size);
13974 for (regno = LAST_ARG_REGNUM + 1 - num_pushes;
13975 regno <= LAST_ARG_REGNUM;
13977 asm_fprintf (f, "%r%s", regno,
13978 regno == LAST_ARG_REGNUM ? "" : ", ");
13980 fprintf (f, "}\n");
13983 asm_fprintf (f, "\tsub\t%r, %r, #%d\n",
13984 SP_REGNUM, SP_REGNUM,
13985 current_function_pretend_args_size);
13987 /* We don't need to record the stores for unwinding (would it
13988 help the debugger any if we did?), but record the change in
13989 the stack pointer. */
13990 if (dwarf2out_do_frame ())
13992 char *l = dwarf2out_cfi_label ();
13994 cfa_offset = cfa_offset + current_function_pretend_args_size;
13995 dwarf2out_def_cfa (l, SP_REGNUM, cfa_offset);
13999 /* Get the registers we are going to push. */
14000 live_regs_mask = thumb_compute_save_reg_mask ();
14001 /* Extract a mask of the ones we can give to the Thumb's push instruction. */
14002 l_mask = live_regs_mask & 0x40ff;
14003 /* Then count how many other high registers will need to be pushed. */
14004 high_regs_pushed = bit_count (live_regs_mask & 0x0f00);
14006 if (TARGET_BACKTRACE)
14009 unsigned work_register;
14011 /* We have been asked to create a stack backtrace structure.
14012 The code looks like this:
14016 0 sub SP, #16 Reserve space for 4 registers.
14017 2 push {R7} Push low registers.
14018 4 add R7, SP, #20 Get the stack pointer before the push.
14019 6 str R7, [SP, #8] Store the stack pointer (before reserving the space).
14020 8 mov R7, PC Get hold of the start of this code plus 12.
14021 10 str R7, [SP, #16] Store it.
14022 12 mov R7, FP Get hold of the current frame pointer.
14023 14 str R7, [SP, #4] Store it.
14024 16 mov R7, LR Get hold of the current return address.
14025 18 str R7, [SP, #12] Store it.
14026 20 add R7, SP, #16 Point at the start of the backtrace structure.
14027 22 mov FP, R7 Put this value into the frame pointer. */
14029 work_register = thumb_find_work_register (live_regs_mask);
14031 if (ARM_EABI_UNWIND_TABLES)
14032 asm_fprintf (f, "\t.pad #16\n");
14035 (f, "\tsub\t%r, %r, #16\t%@ Create stack backtrace structure\n",
14036 SP_REGNUM, SP_REGNUM);
14038 if (dwarf2out_do_frame ())
14040 char *l = dwarf2out_cfi_label ();
14042 cfa_offset = cfa_offset + 16;
14043 dwarf2out_def_cfa (l, SP_REGNUM, cfa_offset);
14048 thumb_pushpop (f, l_mask, 1, &cfa_offset, l_mask);
14049 offset = bit_count (l_mask) * UNITS_PER_WORD;
14054 asm_fprintf (f, "\tadd\t%r, %r, #%d\n", work_register, SP_REGNUM,
14055 offset + 16 + current_function_pretend_args_size);
14057 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
14060 /* Make sure that the instruction fetching the PC is in the right place
14061 to calculate "start of backtrace creation code + 12". */
14064 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, PC_REGNUM);
14065 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
14067 asm_fprintf (f, "\tmov\t%r, %r\n", work_register,
14068 ARM_HARD_FRAME_POINTER_REGNUM);
14069 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
14074 asm_fprintf (f, "\tmov\t%r, %r\n", work_register,
14075 ARM_HARD_FRAME_POINTER_REGNUM);
14076 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
14078 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, PC_REGNUM);
14079 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
14083 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, LR_REGNUM);
14084 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
14086 asm_fprintf (f, "\tadd\t%r, %r, #%d\n", work_register, SP_REGNUM,
14088 asm_fprintf (f, "\tmov\t%r, %r\t\t%@ Backtrace structure created\n",
14089 ARM_HARD_FRAME_POINTER_REGNUM, work_register);
14091 /* Optimization: If we are not pushing any low registers but we are going
14092 to push some high registers then delay our first push. This will just
14093 be a push of LR and we can combine it with the push of the first high
14095 else if ((l_mask & 0xff) != 0
14096 || (high_regs_pushed == 0 && l_mask))
14097 thumb_pushpop (f, l_mask, 1, &cfa_offset, l_mask);
14099 if (high_regs_pushed)
14101 unsigned pushable_regs;
14102 unsigned next_hi_reg;
14104 for (next_hi_reg = 12; next_hi_reg > LAST_LO_REGNUM; next_hi_reg--)
14105 if (live_regs_mask & (1 << next_hi_reg))
14108 pushable_regs = l_mask & 0xff;
14110 if (pushable_regs == 0)
14111 pushable_regs = 1 << thumb_find_work_register (live_regs_mask);
14113 while (high_regs_pushed > 0)
14115 unsigned long real_regs_mask = 0;
14117 for (regno = LAST_LO_REGNUM; regno >= 0; regno --)
14119 if (pushable_regs & (1 << regno))
14121 asm_fprintf (f, "\tmov\t%r, %r\n", regno, next_hi_reg);
14123 high_regs_pushed --;
14124 real_regs_mask |= (1 << next_hi_reg);
14126 if (high_regs_pushed)
14128 for (next_hi_reg --; next_hi_reg > LAST_LO_REGNUM;
14130 if (live_regs_mask & (1 << next_hi_reg))
14135 pushable_regs &= ~((1 << regno) - 1);
14141 /* If we had to find a work register and we have not yet
14142 saved the LR then add it to the list of regs to push. */
14143 if (l_mask == (1 << LR_REGNUM))
14145 thumb_pushpop (f, pushable_regs | (1 << LR_REGNUM),
14147 real_regs_mask | (1 << LR_REGNUM));
14151 thumb_pushpop (f, pushable_regs, 1, &cfa_offset, real_regs_mask);
14156 /* Handle the case of a double word load into a low register from
14157 a computed memory address. The computed address may involve a
14158 register which is overwritten by the load. */
14160 thumb_load_double_from_address (rtx *operands)
14168 gcc_assert (GET_CODE (operands[0]) == REG);
14169 gcc_assert (GET_CODE (operands[1]) == MEM);
14171 /* Get the memory address. */
14172 addr = XEXP (operands[1], 0);
14174 /* Work out how the memory address is computed. */
14175 switch (GET_CODE (addr))
14178 operands[2] = adjust_address (operands[1], SImode, 4);
14180 if (REGNO (operands[0]) == REGNO (addr))
14182 output_asm_insn ("ldr\t%H0, %2", operands);
14183 output_asm_insn ("ldr\t%0, %1", operands);
14187 output_asm_insn ("ldr\t%0, %1", operands);
14188 output_asm_insn ("ldr\t%H0, %2", operands);
14193 /* Compute <address> + 4 for the high order load. */
14194 operands[2] = adjust_address (operands[1], SImode, 4);
14196 output_asm_insn ("ldr\t%0, %1", operands);
14197 output_asm_insn ("ldr\t%H0, %2", operands);
14201 arg1 = XEXP (addr, 0);
14202 arg2 = XEXP (addr, 1);
14204 if (CONSTANT_P (arg1))
14205 base = arg2, offset = arg1;
14207 base = arg1, offset = arg2;
14209 gcc_assert (GET_CODE (base) == REG);
14211 /* Catch the case of <address> = <reg> + <reg> */
14212 if (GET_CODE (offset) == REG)
14214 int reg_offset = REGNO (offset);
14215 int reg_base = REGNO (base);
14216 int reg_dest = REGNO (operands[0]);
14218 /* Add the base and offset registers together into the
14219 higher destination register. */
14220 asm_fprintf (asm_out_file, "\tadd\t%r, %r, %r",
14221 reg_dest + 1, reg_base, reg_offset);
14223 /* Load the lower destination register from the address in
14224 the higher destination register. */
14225 asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #0]",
14226 reg_dest, reg_dest + 1);
14228 /* Load the higher destination register from its own address
14230 asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #4]",
14231 reg_dest + 1, reg_dest + 1);
14235 /* Compute <address> + 4 for the high order load. */
14236 operands[2] = adjust_address (operands[1], SImode, 4);
14238 /* If the computed address is held in the low order register
14239 then load the high order register first, otherwise always
14240 load the low order register first. */
14241 if (REGNO (operands[0]) == REGNO (base))
14243 output_asm_insn ("ldr\t%H0, %2", operands);
14244 output_asm_insn ("ldr\t%0, %1", operands);
14248 output_asm_insn ("ldr\t%0, %1", operands);
14249 output_asm_insn ("ldr\t%H0, %2", operands);
14255 /* With no registers to worry about we can just load the value
14257 operands[2] = adjust_address (operands[1], SImode, 4);
14259 output_asm_insn ("ldr\t%H0, %2", operands);
14260 output_asm_insn ("ldr\t%0, %1", operands);
14264 gcc_unreachable ();
14271 thumb_output_move_mem_multiple (int n, rtx *operands)
14278 if (REGNO (operands[4]) > REGNO (operands[5]))
14281 operands[4] = operands[5];
14284 output_asm_insn ("ldmia\t%1!, {%4, %5}", operands);
14285 output_asm_insn ("stmia\t%0!, {%4, %5}", operands);
14289 if (REGNO (operands[4]) > REGNO (operands[5]))
14292 operands[4] = operands[5];
14295 if (REGNO (operands[5]) > REGNO (operands[6]))
14298 operands[5] = operands[6];
14301 if (REGNO (operands[4]) > REGNO (operands[5]))
14304 operands[4] = operands[5];
14308 output_asm_insn ("ldmia\t%1!, {%4, %5, %6}", operands);
14309 output_asm_insn ("stmia\t%0!, {%4, %5, %6}", operands);
14313 gcc_unreachable ();
14319 /* Output a call-via instruction for thumb state. */
14321 thumb_call_via_reg (rtx reg)
14323 int regno = REGNO (reg);
14326 gcc_assert (regno < LR_REGNUM);
14328 /* If we are in the normal text section we can use a single instance
14329 per compilation unit. If we are doing function sections, then we need
14330 an entry per section, since we can't rely on reachability. */
14331 if (in_section == text_section)
14333 thumb_call_reg_needed = 1;
14335 if (thumb_call_via_label[regno] == NULL)
14336 thumb_call_via_label[regno] = gen_label_rtx ();
14337 labelp = thumb_call_via_label + regno;
14341 if (cfun->machine->call_via[regno] == NULL)
14342 cfun->machine->call_via[regno] = gen_label_rtx ();
14343 labelp = cfun->machine->call_via + regno;
14346 output_asm_insn ("bl\t%a0", labelp);
14350 /* Routines for generating rtl. */
14352 thumb_expand_movmemqi (rtx *operands)
14354 rtx out = copy_to_mode_reg (SImode, XEXP (operands[0], 0));
14355 rtx in = copy_to_mode_reg (SImode, XEXP (operands[1], 0));
14356 HOST_WIDE_INT len = INTVAL (operands[2]);
14357 HOST_WIDE_INT offset = 0;
14361 emit_insn (gen_movmem12b (out, in, out, in));
14367 emit_insn (gen_movmem8b (out, in, out, in));
14373 rtx reg = gen_reg_rtx (SImode);
14374 emit_insn (gen_movsi (reg, gen_rtx_MEM (SImode, in)));
14375 emit_insn (gen_movsi (gen_rtx_MEM (SImode, out), reg));
14382 rtx reg = gen_reg_rtx (HImode);
14383 emit_insn (gen_movhi (reg, gen_rtx_MEM (HImode,
14384 plus_constant (in, offset))));
14385 emit_insn (gen_movhi (gen_rtx_MEM (HImode, plus_constant (out, offset)),
14393 rtx reg = gen_reg_rtx (QImode);
14394 emit_insn (gen_movqi (reg, gen_rtx_MEM (QImode,
14395 plus_constant (in, offset))));
14396 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (out, offset)),
14402 thumb_reload_out_hi (rtx *operands)
14404 emit_insn (gen_thumb_movhi_clobber (operands[0], operands[1], operands[2]));
14407 /* Handle reading a half-word from memory during reload. */
14409 thumb_reload_in_hi (rtx *operands ATTRIBUTE_UNUSED)
14411 gcc_unreachable ();
14414 /* Return the length of a function name prefix
14415 that starts with the character 'c'. */
14417 arm_get_strip_length (int c)
14421 ARM_NAME_ENCODING_LENGTHS
14426 /* Return a pointer to a function's name with any
14427 and all prefix encodings stripped from it. */
14429 arm_strip_name_encoding (const char *name)
14433 while ((skip = arm_get_strip_length (* name)))
14439 /* If there is a '*' anywhere in the name's prefix, then
14440 emit the stripped name verbatim, otherwise prepend an
14441 underscore if leading underscores are being used. */
14443 arm_asm_output_labelref (FILE *stream, const char *name)
14448 while ((skip = arm_get_strip_length (* name)))
14450 verbatim |= (*name == '*');
14455 fputs (name, stream);
14457 asm_fprintf (stream, "%U%s", name);
14461 arm_file_end (void)
14465 if (! thumb_call_reg_needed)
14468 switch_to_section (text_section);
14469 asm_fprintf (asm_out_file, "\t.code 16\n");
14470 ASM_OUTPUT_ALIGN (asm_out_file, 1);
14472 for (regno = 0; regno < LR_REGNUM; regno++)
14474 rtx label = thumb_call_via_label[regno];
14478 targetm.asm_out.internal_label (asm_out_file, "L",
14479 CODE_LABEL_NUMBER (label));
14480 asm_fprintf (asm_out_file, "\tbx\t%r\n", regno);
14487 #ifdef AOF_ASSEMBLER
14488 /* Special functions only needed when producing AOF syntax assembler. */
14492 struct pic_chain * next;
14493 const char * symname;
14496 static struct pic_chain * aof_pic_chain = NULL;
14499 aof_pic_entry (rtx x)
14501 struct pic_chain ** chainp;
14504 if (aof_pic_label == NULL_RTX)
14506 aof_pic_label = gen_rtx_SYMBOL_REF (Pmode, "x$adcons");
14509 for (offset = 0, chainp = &aof_pic_chain; *chainp;
14510 offset += 4, chainp = &(*chainp)->next)
14511 if ((*chainp)->symname == XSTR (x, 0))
14512 return plus_constant (aof_pic_label, offset);
14514 *chainp = (struct pic_chain *) xmalloc (sizeof (struct pic_chain));
14515 (*chainp)->next = NULL;
14516 (*chainp)->symname = XSTR (x, 0);
14517 return plus_constant (aof_pic_label, offset);
14521 aof_dump_pic_table (FILE *f)
14523 struct pic_chain * chain;
14525 if (aof_pic_chain == NULL)
14528 asm_fprintf (f, "\tAREA |%r$$adcons|, BASED %r\n",
14529 PIC_OFFSET_TABLE_REGNUM,
14530 PIC_OFFSET_TABLE_REGNUM);
14531 fputs ("|x$adcons|\n", f);
14533 for (chain = aof_pic_chain; chain; chain = chain->next)
14535 fputs ("\tDCD\t", f);
14536 assemble_name (f, chain->symname);
14541 int arm_text_section_count = 1;
14543 /* A get_unnamed_section callback for switching to the text section. */
14546 aof_output_text_section_asm_op (const void *data ATTRIBUTE_UNUSED)
14548 fprintf (asm_out_file, "\tAREA |C$$code%d|, CODE, READONLY",
14549 arm_text_section_count++);
14551 fprintf (asm_out_file, ", PIC, REENTRANT");
14552 fprintf (asm_out_file, "\n");
14555 static int arm_data_section_count = 1;
14557 /* A get_unnamed_section callback for switching to the data section. */
14560 aof_output_data_section_asm_op (const void *data ATTRIBUTE_UNUSED)
14562 fprintf (asm_out_file, "\tAREA |C$$data%d|, DATA\n",
14563 arm_data_section_count++);
14566 /* Implement TARGET_ASM_INIT_SECTIONS.
14568 AOF Assembler syntax is a nightmare when it comes to areas, since once
14569 we change from one area to another, we can't go back again. Instead,
14570 we must create a new area with the same attributes and add the new output
14571 to that. Unfortunately, there is nothing we can do here to guarantee that
14572 two areas with the same attributes will be linked adjacently in the
14573 resulting executable, so we have to be careful not to do pc-relative
14574 addressing across such boundaries. */
14577 aof_asm_init_sections (void)
14579 text_section = get_unnamed_section (SECTION_CODE,
14580 aof_output_text_section_asm_op, NULL);
14581 data_section = get_unnamed_section (SECTION_WRITE,
14582 aof_output_data_section_asm_op, NULL);
14583 readonly_data_section = text_section;
14587 zero_init_section (void)
14589 static int zero_init_count = 1;
14591 fprintf (asm_out_file, "\tAREA |C$$zidata%d|,NOINIT\n", zero_init_count++);
14595 /* The AOF assembler is religiously strict about declarations of
14596 imported and exported symbols, so that it is impossible to declare
14597 a function as imported near the beginning of the file, and then to
14598 export it later on. It is, however, possible to delay the decision
14599 until all the functions in the file have been compiled. To get
14600 around this, we maintain a list of the imports and exports, and
14601 delete from it any that are subsequently defined. At the end of
14602 compilation we spit the remainder of the list out before the END
14607 struct import * next;
14611 static struct import * imports_list = NULL;
14614 aof_add_import (const char *name)
14616 struct import * new;
14618 for (new = imports_list; new; new = new->next)
14619 if (new->name == name)
14622 new = (struct import *) xmalloc (sizeof (struct import));
14623 new->next = imports_list;
14624 imports_list = new;
14629 aof_delete_import (const char *name)
14631 struct import ** old;
14633 for (old = &imports_list; *old; old = & (*old)->next)
14635 if ((*old)->name == name)
14637 *old = (*old)->next;
14643 int arm_main_function = 0;
14646 aof_dump_imports (FILE *f)
14648 /* The AOF assembler needs this to cause the startup code to be extracted
14649 from the library. Brining in __main causes the whole thing to work
14651 if (arm_main_function)
14653 switch_to_section (text_section);
14654 fputs ("\tIMPORT __main\n", f);
14655 fputs ("\tDCD __main\n", f);
14658 /* Now dump the remaining imports. */
14659 while (imports_list)
14661 fprintf (f, "\tIMPORT\t");
14662 assemble_name (f, imports_list->name);
14664 imports_list = imports_list->next;
14669 aof_globalize_label (FILE *stream, const char *name)
14671 default_globalize_label (stream, name);
14672 if (! strcmp (name, "main"))
14673 arm_main_function = 1;
14677 aof_file_start (void)
14679 fputs ("__r0\tRN\t0\n", asm_out_file);
14680 fputs ("__a1\tRN\t0\n", asm_out_file);
14681 fputs ("__a2\tRN\t1\n", asm_out_file);
14682 fputs ("__a3\tRN\t2\n", asm_out_file);
14683 fputs ("__a4\tRN\t3\n", asm_out_file);
14684 fputs ("__v1\tRN\t4\n", asm_out_file);
14685 fputs ("__v2\tRN\t5\n", asm_out_file);
14686 fputs ("__v3\tRN\t6\n", asm_out_file);
14687 fputs ("__v4\tRN\t7\n", asm_out_file);
14688 fputs ("__v5\tRN\t8\n", asm_out_file);
14689 fputs ("__v6\tRN\t9\n", asm_out_file);
14690 fputs ("__sl\tRN\t10\n", asm_out_file);
14691 fputs ("__fp\tRN\t11\n", asm_out_file);
14692 fputs ("__ip\tRN\t12\n", asm_out_file);
14693 fputs ("__sp\tRN\t13\n", asm_out_file);
14694 fputs ("__lr\tRN\t14\n", asm_out_file);
14695 fputs ("__pc\tRN\t15\n", asm_out_file);
14696 fputs ("__f0\tFN\t0\n", asm_out_file);
14697 fputs ("__f1\tFN\t1\n", asm_out_file);
14698 fputs ("__f2\tFN\t2\n", asm_out_file);
14699 fputs ("__f3\tFN\t3\n", asm_out_file);
14700 fputs ("__f4\tFN\t4\n", asm_out_file);
14701 fputs ("__f5\tFN\t5\n", asm_out_file);
14702 fputs ("__f6\tFN\t6\n", asm_out_file);
14703 fputs ("__f7\tFN\t7\n", asm_out_file);
14704 switch_to_section (text_section);
14708 aof_file_end (void)
14711 aof_dump_pic_table (asm_out_file);
14713 aof_dump_imports (asm_out_file);
14714 fputs ("\tEND\n", asm_out_file);
14716 #endif /* AOF_ASSEMBLER */
14719 /* Symbols in the text segment can be accessed without indirecting via the
14720 constant pool; it may take an extra binary operation, but this is still
14721 faster than indirecting via memory. Don't do this when not optimizing,
14722 since we won't be calculating al of the offsets necessary to do this
14726 arm_encode_section_info (tree decl, rtx rtl, int first)
14728 /* This doesn't work with AOF syntax, since the string table may be in
14729 a different AREA. */
14730 #ifndef AOF_ASSEMBLER
14731 if (optimize > 0 && TREE_CONSTANT (decl))
14732 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1;
14735 /* If we are referencing a function that is weak then encode a long call
14736 flag in the function name, otherwise if the function is static or
14737 or known to be defined in this file then encode a short call flag. */
14738 if (first && DECL_P (decl))
14740 if (TREE_CODE (decl) == FUNCTION_DECL && DECL_WEAK (decl))
14741 arm_encode_call_attribute (decl, LONG_CALL_FLAG_CHAR);
14742 else if (! TREE_PUBLIC (decl))
14743 arm_encode_call_attribute (decl, SHORT_CALL_FLAG_CHAR);
14746 default_encode_section_info (decl, rtl, first);
14748 #endif /* !ARM_PE */
14751 arm_internal_label (FILE *stream, const char *prefix, unsigned long labelno)
14753 if (arm_ccfsm_state == 3 && (unsigned) arm_target_label == labelno
14754 && !strcmp (prefix, "L"))
14756 arm_ccfsm_state = 0;
14757 arm_target_insn = NULL;
14759 default_internal_label (stream, prefix, labelno);
14762 /* Output code to add DELTA to the first argument, and then jump
14763 to FUNCTION. Used for C++ multiple inheritance. */
14765 arm_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
14766 HOST_WIDE_INT delta,
14767 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
14770 static int thunk_label = 0;
14773 int mi_delta = delta;
14774 const char *const mi_op = mi_delta < 0 ? "sub" : "add";
14776 int this_regno = (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function)
14779 mi_delta = - mi_delta;
14782 int labelno = thunk_label++;
14783 ASM_GENERATE_INTERNAL_LABEL (label, "LTHUMBFUNC", labelno);
14784 fputs ("\tldr\tr12, ", file);
14785 assemble_name (file, label);
14786 fputc ('\n', file);
14789 /* If we are generating PIC, the ldr instruction below loads
14790 "(target - 7) - .LTHUNKPCn" into r12. The pc reads as
14791 the address of the add + 8, so we have:
14793 r12 = (target - 7) - .LTHUNKPCn + (.LTHUNKPCn + 8)
14796 Note that we have "+ 1" because some versions of GNU ld
14797 don't set the low bit of the result for R_ARM_REL32
14798 relocations against thumb function symbols. */
14799 ASM_GENERATE_INTERNAL_LABEL (labelpc, "LTHUNKPC", labelno);
14800 assemble_name (file, labelpc);
14801 fputs (":\n", file);
14802 fputs ("\tadd\tr12, pc, r12\n", file);
14805 while (mi_delta != 0)
14807 if ((mi_delta & (3 << shift)) == 0)
14811 asm_fprintf (file, "\t%s\t%r, %r, #%d\n",
14812 mi_op, this_regno, this_regno,
14813 mi_delta & (0xff << shift));
14814 mi_delta &= ~(0xff << shift);
14820 fprintf (file, "\tbx\tr12\n");
14821 ASM_OUTPUT_ALIGN (file, 2);
14822 assemble_name (file, label);
14823 fputs (":\n", file);
14826 /* Output ".word .LTHUNKn-7-.LTHUNKPCn". */
14827 rtx tem = XEXP (DECL_RTL (function), 0);
14828 tem = gen_rtx_PLUS (GET_MODE (tem), tem, GEN_INT (-7));
14829 tem = gen_rtx_MINUS (GET_MODE (tem),
14831 gen_rtx_SYMBOL_REF (Pmode,
14832 ggc_strdup (labelpc)));
14833 assemble_integer (tem, 4, BITS_PER_WORD, 1);
14836 /* Output ".word .LTHUNKn". */
14837 assemble_integer (XEXP (DECL_RTL (function), 0), 4, BITS_PER_WORD, 1);
14841 fputs ("\tb\t", file);
14842 assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0));
14843 if (NEED_PLT_RELOC)
14844 fputs ("(PLT)", file);
14845 fputc ('\n', file);
14850 arm_emit_vector_const (FILE *file, rtx x)
14853 const char * pattern;
14855 gcc_assert (GET_CODE (x) == CONST_VECTOR);
14857 switch (GET_MODE (x))
14859 case V2SImode: pattern = "%08x"; break;
14860 case V4HImode: pattern = "%04x"; break;
14861 case V8QImode: pattern = "%02x"; break;
14862 default: gcc_unreachable ();
14865 fprintf (file, "0x");
14866 for (i = CONST_VECTOR_NUNITS (x); i--;)
14870 element = CONST_VECTOR_ELT (x, i);
14871 fprintf (file, pattern, INTVAL (element));
14878 arm_output_load_gr (rtx *operands)
14885 if (GET_CODE (operands [1]) != MEM
14886 || GET_CODE (sum = XEXP (operands [1], 0)) != PLUS
14887 || GET_CODE (reg = XEXP (sum, 0)) != REG
14888 || GET_CODE (offset = XEXP (sum, 1)) != CONST_INT
14889 || ((INTVAL (offset) < 1024) && (INTVAL (offset) > -1024)))
14890 return "wldrw%?\t%0, %1";
14892 /* Fix up an out-of-range load of a GR register. */
14893 output_asm_insn ("str%?\t%0, [sp, #-4]!\t@ Start of GR load expansion", & reg);
14894 wcgr = operands[0];
14896 output_asm_insn ("ldr%?\t%0, %1", operands);
14898 operands[0] = wcgr;
14900 output_asm_insn ("tmcr%?\t%0, %1", operands);
14901 output_asm_insn ("ldr%?\t%0, [sp], #4\t@ End of GR load expansion", & reg);
14906 /* Worker function for TARGET_SETUP_INCOMING_VARARGS.
14908 On the ARM, PRETEND_SIZE is set in order to have the prologue push the last
14909 named arg and all anonymous args onto the stack.
14910 XXX I know the prologue shouldn't be pushing registers, but it is faster
14914 arm_setup_incoming_varargs (CUMULATIVE_ARGS *cum,
14915 enum machine_mode mode ATTRIBUTE_UNUSED,
14916 tree type ATTRIBUTE_UNUSED,
14918 int second_time ATTRIBUTE_UNUSED)
14920 cfun->machine->uses_anonymous_args = 1;
14921 if (cum->nregs < NUM_ARG_REGS)
14922 *pretend_size = (NUM_ARG_REGS - cum->nregs) * UNITS_PER_WORD;
14925 /* Return nonzero if the CONSUMER instruction (a store) does not need
14926 PRODUCER's value to calculate the address. */
14929 arm_no_early_store_addr_dep (rtx producer, rtx consumer)
14931 rtx value = PATTERN (producer);
14932 rtx addr = PATTERN (consumer);
14934 if (GET_CODE (value) == COND_EXEC)
14935 value = COND_EXEC_CODE (value);
14936 if (GET_CODE (value) == PARALLEL)
14937 value = XVECEXP (value, 0, 0);
14938 value = XEXP (value, 0);
14939 if (GET_CODE (addr) == COND_EXEC)
14940 addr = COND_EXEC_CODE (addr);
14941 if (GET_CODE (addr) == PARALLEL)
14942 addr = XVECEXP (addr, 0, 0);
14943 addr = XEXP (addr, 0);
14945 return !reg_overlap_mentioned_p (value, addr);
14948 /* Return nonzero if the CONSUMER instruction (an ALU op) does not
14949 have an early register shift value or amount dependency on the
14950 result of PRODUCER. */
14953 arm_no_early_alu_shift_dep (rtx producer, rtx consumer)
14955 rtx value = PATTERN (producer);
14956 rtx op = PATTERN (consumer);
14959 if (GET_CODE (value) == COND_EXEC)
14960 value = COND_EXEC_CODE (value);
14961 if (GET_CODE (value) == PARALLEL)
14962 value = XVECEXP (value, 0, 0);
14963 value = XEXP (value, 0);
14964 if (GET_CODE (op) == COND_EXEC)
14965 op = COND_EXEC_CODE (op);
14966 if (GET_CODE (op) == PARALLEL)
14967 op = XVECEXP (op, 0, 0);
14970 early_op = XEXP (op, 0);
14971 /* This is either an actual independent shift, or a shift applied to
14972 the first operand of another operation. We want the whole shift
14974 if (GET_CODE (early_op) == REG)
14977 return !reg_overlap_mentioned_p (value, early_op);
14980 /* Return nonzero if the CONSUMER instruction (an ALU op) does not
14981 have an early register shift value dependency on the result of
14985 arm_no_early_alu_shift_value_dep (rtx producer, rtx consumer)
14987 rtx value = PATTERN (producer);
14988 rtx op = PATTERN (consumer);
14991 if (GET_CODE (value) == COND_EXEC)
14992 value = COND_EXEC_CODE (value);
14993 if (GET_CODE (value) == PARALLEL)
14994 value = XVECEXP (value, 0, 0);
14995 value = XEXP (value, 0);
14996 if (GET_CODE (op) == COND_EXEC)
14997 op = COND_EXEC_CODE (op);
14998 if (GET_CODE (op) == PARALLEL)
14999 op = XVECEXP (op, 0, 0);
15002 early_op = XEXP (op, 0);
15004 /* This is either an actual independent shift, or a shift applied to
15005 the first operand of another operation. We want the value being
15006 shifted, in either case. */
15007 if (GET_CODE (early_op) != REG)
15008 early_op = XEXP (early_op, 0);
15010 return !reg_overlap_mentioned_p (value, early_op);
15013 /* Return nonzero if the CONSUMER (a mul or mac op) does not
15014 have an early register mult dependency on the result of
15018 arm_no_early_mul_dep (rtx producer, rtx consumer)
15020 rtx value = PATTERN (producer);
15021 rtx op = PATTERN (consumer);
15023 if (GET_CODE (value) == COND_EXEC)
15024 value = COND_EXEC_CODE (value);
15025 if (GET_CODE (value) == PARALLEL)
15026 value = XVECEXP (value, 0, 0);
15027 value = XEXP (value, 0);
15028 if (GET_CODE (op) == COND_EXEC)
15029 op = COND_EXEC_CODE (op);
15030 if (GET_CODE (op) == PARALLEL)
15031 op = XVECEXP (op, 0, 0);
15034 return (GET_CODE (op) == PLUS
15035 && !reg_overlap_mentioned_p (value, XEXP (op, 0)));
15039 /* We can't rely on the caller doing the proper promotion when
15040 using APCS or ATPCS. */
15043 arm_promote_prototypes (tree t ATTRIBUTE_UNUSED)
15045 return !TARGET_AAPCS_BASED;
15049 /* AAPCS based ABIs use short enums by default. */
15052 arm_default_short_enums (void)
15054 return TARGET_AAPCS_BASED && arm_abi != ARM_ABI_AAPCS_LINUX;
15058 /* AAPCS requires that anonymous bitfields affect structure alignment. */
15061 arm_align_anon_bitfield (void)
15063 return TARGET_AAPCS_BASED;
15067 /* The generic C++ ABI says 64-bit (long long). The EABI says 32-bit. */
15070 arm_cxx_guard_type (void)
15072 return TARGET_AAPCS_BASED ? integer_type_node : long_long_integer_type_node;
15076 /* The EABI says test the least significant bit of a guard variable. */
15079 arm_cxx_guard_mask_bit (void)
15081 return TARGET_AAPCS_BASED;
15085 /* The EABI specifies that all array cookies are 8 bytes long. */
15088 arm_get_cookie_size (tree type)
15092 if (!TARGET_AAPCS_BASED)
15093 return default_cxx_get_cookie_size (type);
15095 size = build_int_cst (sizetype, 8);
15100 /* The EABI says that array cookies should also contain the element size. */
15103 arm_cookie_has_size (void)
15105 return TARGET_AAPCS_BASED;
15109 /* The EABI says constructors and destructors should return a pointer to
15110 the object constructed/destroyed. */
15113 arm_cxx_cdtor_returns_this (void)
15115 return TARGET_AAPCS_BASED;
15118 /* The EABI says that an inline function may never be the key
15122 arm_cxx_key_method_may_be_inline (void)
15124 return !TARGET_AAPCS_BASED;
15128 arm_cxx_determine_class_data_visibility (tree decl)
15130 if (!TARGET_AAPCS_BASED)
15133 /* In general, \S 3.2.5.5 of the ARM EABI requires that class data
15134 is exported. However, on systems without dynamic vague linkage,
15135 \S 3.2.5.6 says that COMDAT class data has hidden linkage. */
15136 if (!TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P && DECL_COMDAT (decl))
15137 DECL_VISIBILITY (decl) = VISIBILITY_HIDDEN;
15139 DECL_VISIBILITY (decl) = VISIBILITY_DEFAULT;
15140 DECL_VISIBILITY_SPECIFIED (decl) = 1;
15144 arm_cxx_class_data_always_comdat (void)
15146 /* \S 3.2.5.4 of the ARM C++ ABI says that class data only have
15147 vague linkage if the class has no key function. */
15148 return !TARGET_AAPCS_BASED;
15152 /* The EABI says __aeabi_atexit should be used to register static
15156 arm_cxx_use_aeabi_atexit (void)
15158 return TARGET_AAPCS_BASED;
15163 arm_set_return_address (rtx source, rtx scratch)
15165 arm_stack_offsets *offsets;
15166 HOST_WIDE_INT delta;
15168 unsigned long saved_regs;
15170 saved_regs = arm_compute_save_reg_mask ();
15172 if ((saved_regs & (1 << LR_REGNUM)) == 0)
15173 emit_move_insn (gen_rtx_REG (Pmode, LR_REGNUM), source);
15176 if (frame_pointer_needed)
15177 addr = plus_constant(hard_frame_pointer_rtx, -4);
15180 /* LR will be the first saved register. */
15181 offsets = arm_get_frame_offsets ();
15182 delta = offsets->outgoing_args - (offsets->frame + 4);
15187 emit_insn (gen_addsi3 (scratch, stack_pointer_rtx,
15188 GEN_INT (delta & ~4095)));
15193 addr = stack_pointer_rtx;
15195 addr = plus_constant (addr, delta);
15197 emit_move_insn (gen_frame_mem (Pmode, addr), source);
15203 thumb_set_return_address (rtx source, rtx scratch)
15205 arm_stack_offsets *offsets;
15206 HOST_WIDE_INT delta;
15209 unsigned long mask;
15211 emit_insn (gen_rtx_USE (VOIDmode, source));
15213 mask = thumb_compute_save_reg_mask ();
15214 if (mask & (1 << LR_REGNUM))
15216 offsets = arm_get_frame_offsets ();
15218 /* Find the saved regs. */
15219 if (frame_pointer_needed)
15221 delta = offsets->soft_frame - offsets->saved_args;
15222 reg = THUMB_HARD_FRAME_POINTER_REGNUM;
15226 delta = offsets->outgoing_args - offsets->saved_args;
15229 /* Allow for the stack frame. */
15230 if (TARGET_BACKTRACE)
15232 /* The link register is always the first saved register. */
15235 /* Construct the address. */
15236 addr = gen_rtx_REG (SImode, reg);
15237 if ((reg != SP_REGNUM && delta >= 128)
15240 emit_insn (gen_movsi (scratch, GEN_INT (delta)));
15241 emit_insn (gen_addsi3 (scratch, scratch, stack_pointer_rtx));
15245 addr = plus_constant (addr, delta);
15247 emit_move_insn (gen_frame_mem (Pmode, addr), source);
15250 emit_move_insn (gen_rtx_REG (Pmode, LR_REGNUM), source);
15253 /* Implements target hook vector_mode_supported_p. */
15255 arm_vector_mode_supported_p (enum machine_mode mode)
15257 if ((mode == V2SImode)
15258 || (mode == V4HImode)
15259 || (mode == V8QImode))
15265 /* Implement TARGET_SHIFT_TRUNCATION_MASK. SImode shifts use normal
15266 ARM insns and therefore guarantee that the shift count is modulo 256.
15267 DImode shifts (those implemented by lib1funcs.asm or by optabs.c)
15268 guarantee no particular behavior for out-of-range counts. */
15270 static unsigned HOST_WIDE_INT
15271 arm_shift_truncation_mask (enum machine_mode mode)
15273 return mode == SImode ? 255 : 0;
15277 /* Map internal gcc register numbers to DWARF2 register numbers. */
15280 arm_dbx_register_number (unsigned int regno)
15285 /* TODO: Legacy targets output FPA regs as registers 16-23 for backwards
15286 compatibility. The EABI defines them as registers 96-103. */
15287 if (IS_FPA_REGNUM (regno))
15288 return (TARGET_AAPCS_BASED ? 96 : 16) + regno - FIRST_FPA_REGNUM;
15290 if (IS_VFP_REGNUM (regno))
15291 return 64 + regno - FIRST_VFP_REGNUM;
15293 if (IS_IWMMXT_GR_REGNUM (regno))
15294 return 104 + regno - FIRST_IWMMXT_GR_REGNUM;
15296 if (IS_IWMMXT_REGNUM (regno))
15297 return 112 + regno - FIRST_IWMMXT_REGNUM;
15299 gcc_unreachable ();
15303 #ifdef TARGET_UNWIND_INFO
15304 /* Emit unwind directives for a store-multiple instruction. This should
15305 only ever be generated by the function prologue code, so we expect it
15306 to have a particular form. */
15309 arm_unwind_emit_stm (FILE * asm_out_file, rtx p)
15312 HOST_WIDE_INT offset;
15313 HOST_WIDE_INT nregs;
15319 /* First insn will adjust the stack pointer. */
15320 e = XVECEXP (p, 0, 0);
15321 if (GET_CODE (e) != SET
15322 || GET_CODE (XEXP (e, 0)) != REG
15323 || REGNO (XEXP (e, 0)) != SP_REGNUM
15324 || GET_CODE (XEXP (e, 1)) != PLUS)
15327 offset = -INTVAL (XEXP (XEXP (e, 1), 1));
15328 nregs = XVECLEN (p, 0) - 1;
15330 reg = REGNO (XEXP (XVECEXP (p, 0, 1), 1));
15333 /* The function prologue may also push pc, but not annotate it as it is
15334 never restored. We turn this into a stack pointer adjustment. */
15335 if (nregs * 4 == offset - 4)
15337 fprintf (asm_out_file, "\t.pad #4\n");
15342 else if (IS_VFP_REGNUM (reg))
15344 /* FPA register saves use an additional word. */
15348 else if (reg >= FIRST_FPA_REGNUM && reg <= LAST_FPA_REGNUM)
15350 /* FPA registers are done differently. */
15351 asm_fprintf (asm_out_file, "\t.save %r, %wd\n", reg, nregs);
15355 /* Unknown register type. */
15358 /* If the stack increment doesn't match the size of the saved registers,
15359 something has gone horribly wrong. */
15360 if (offset != nregs * reg_size)
15363 fprintf (asm_out_file, "\t.save {");
15367 /* The remaining insns will describe the stores. */
15368 for (i = 1; i <= nregs; i++)
15370 /* Expect (set (mem <addr>) (reg)).
15371 Where <addr> is (reg:SP) or (plus (reg:SP) (const_int)). */
15372 e = XVECEXP (p, 0, i);
15373 if (GET_CODE (e) != SET
15374 || GET_CODE (XEXP (e, 0)) != MEM
15375 || GET_CODE (XEXP (e, 1)) != REG)
15378 reg = REGNO (XEXP (e, 1));
15383 fprintf (asm_out_file, ", ");
15384 /* We can't use %r for vfp because we need to use the
15385 double precision register names. */
15386 if (IS_VFP_REGNUM (reg))
15387 asm_fprintf (asm_out_file, "d%d", (reg - FIRST_VFP_REGNUM) / 2);
15389 asm_fprintf (asm_out_file, "%r", reg);
15391 #ifdef ENABLE_CHECKING
15392 /* Check that the addresses are consecutive. */
15393 e = XEXP (XEXP (e, 0), 0);
15394 if (GET_CODE (e) == PLUS)
15396 offset += reg_size;
15397 if (GET_CODE (XEXP (e, 0)) != REG
15398 || REGNO (XEXP (e, 0)) != SP_REGNUM
15399 || GET_CODE (XEXP (e, 1)) != CONST_INT
15400 || offset != INTVAL (XEXP (e, 1)))
15404 || GET_CODE (e) != REG
15405 || REGNO (e) != SP_REGNUM)
15409 fprintf (asm_out_file, "}\n");
15412 /* Emit unwind directives for a SET. */
15415 arm_unwind_emit_set (FILE * asm_out_file, rtx p)
15422 switch (GET_CODE (e0))
15425 /* Pushing a single register. */
15426 if (GET_CODE (XEXP (e0, 0)) != PRE_DEC
15427 || GET_CODE (XEXP (XEXP (e0, 0), 0)) != REG
15428 || REGNO (XEXP (XEXP (e0, 0), 0)) != SP_REGNUM)
15431 asm_fprintf (asm_out_file, "\t.save ");
15432 if (IS_VFP_REGNUM (REGNO (e1)))
15433 asm_fprintf(asm_out_file, "{d%d}\n",
15434 (REGNO (e1) - FIRST_VFP_REGNUM) / 2);
15436 asm_fprintf(asm_out_file, "{%r}\n", REGNO (e1));
15440 if (REGNO (e0) == SP_REGNUM)
15442 /* A stack increment. */
15443 if (GET_CODE (e1) != PLUS
15444 || GET_CODE (XEXP (e1, 0)) != REG
15445 || REGNO (XEXP (e1, 0)) != SP_REGNUM
15446 || GET_CODE (XEXP (e1, 1)) != CONST_INT)
15449 asm_fprintf (asm_out_file, "\t.pad #%wd\n",
15450 -INTVAL (XEXP (e1, 1)));
15452 else if (REGNO (e0) == HARD_FRAME_POINTER_REGNUM)
15454 HOST_WIDE_INT offset;
15457 if (GET_CODE (e1) == PLUS)
15459 if (GET_CODE (XEXP (e1, 0)) != REG
15460 || GET_CODE (XEXP (e1, 1)) != CONST_INT)
15462 reg = REGNO (XEXP (e1, 0));
15463 offset = INTVAL (XEXP (e1, 1));
15464 asm_fprintf (asm_out_file, "\t.setfp %r, %r, #%wd\n",
15465 HARD_FRAME_POINTER_REGNUM, reg,
15466 INTVAL (XEXP (e1, 1)));
15468 else if (GET_CODE (e1) == REG)
15471 asm_fprintf (asm_out_file, "\t.setfp %r, %r\n",
15472 HARD_FRAME_POINTER_REGNUM, reg);
15477 else if (GET_CODE (e1) == REG && REGNO (e1) == SP_REGNUM)
15479 /* Move from sp to reg. */
15480 asm_fprintf (asm_out_file, "\t.movsp %r\n", REGNO (e0));
15482 else if (GET_CODE (e1) == PLUS
15483 && GET_CODE (XEXP (e1, 0)) == REG
15484 && REGNO (XEXP (e1, 0)) == SP_REGNUM
15485 && GET_CODE (XEXP (e1, 1)) == CONST_INT)
15487 /* Set reg to offset from sp. */
15488 asm_fprintf (asm_out_file, "\t.movsp %r, #%d\n",
15489 REGNO (e0), (int)INTVAL(XEXP (e1, 1)));
15501 /* Emit unwind directives for the given insn. */
15504 arm_unwind_emit (FILE * asm_out_file, rtx insn)
15508 if (!ARM_EABI_UNWIND_TABLES)
15511 if (GET_CODE (insn) == NOTE || !RTX_FRAME_RELATED_P (insn))
15514 pat = find_reg_note (insn, REG_FRAME_RELATED_EXPR, NULL_RTX);
15516 pat = XEXP (pat, 0);
15518 pat = PATTERN (insn);
15520 switch (GET_CODE (pat))
15523 arm_unwind_emit_set (asm_out_file, pat);
15527 /* Store multiple. */
15528 arm_unwind_emit_stm (asm_out_file, pat);
15537 /* Output a reference from a function exception table to the type_info
15538 object X. The EABI specifies that the symbol should be relocated by
15539 an R_ARM_TARGET2 relocation. */
15542 arm_output_ttype (rtx x)
15544 fputs ("\t.word\t", asm_out_file);
15545 output_addr_const (asm_out_file, x);
15546 /* Use special relocations for symbol references. */
15547 if (GET_CODE (x) != CONST_INT)
15548 fputs ("(TARGET2)", asm_out_file);
15549 fputc ('\n', asm_out_file);
15553 #endif /* TARGET_UNWIND_INFO */
15556 /* Output unwind directives for the start/end of a function. */
15559 arm_output_fn_unwind (FILE * f, bool prologue)
15561 if (!ARM_EABI_UNWIND_TABLES)
15565 fputs ("\t.fnstart\n", f);
15567 fputs ("\t.fnend\n", f);
15571 arm_emit_tls_decoration (FILE *fp, rtx x)
15573 enum tls_reloc reloc;
15576 val = XVECEXP (x, 0, 0);
15577 reloc = INTVAL (XVECEXP (x, 0, 1));
15579 output_addr_const (fp, val);
15584 fputs ("(tlsgd)", fp);
15587 fputs ("(tlsldm)", fp);
15590 fputs ("(tlsldo)", fp);
15593 fputs ("(gottpoff)", fp);
15596 fputs ("(tpoff)", fp);
15599 gcc_unreachable ();
15607 fputs (" + (. - ", fp);
15608 output_addr_const (fp, XVECEXP (x, 0, 2));
15610 output_addr_const (fp, XVECEXP (x, 0, 3));
15621 arm_output_addr_const_extra (FILE *fp, rtx x)
15623 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLS)
15624 return arm_emit_tls_decoration (fp, x);
15625 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_PIC_LABEL)
15628 int labelno = INTVAL (XVECEXP (x, 0, 0));
15630 ASM_GENERATE_INTERNAL_LABEL (label, "LPIC", labelno);
15631 assemble_name_raw (fp, label);
15635 else if (GET_CODE (x) == CONST_VECTOR)
15636 return arm_emit_vector_const (fp, x);
15641 #include "gt-arm.h"