1 /* Definitions of target machine for GNU compiler, for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
5 and Martin Simmons (@harleqn.co.uk).
6 More major hacks by Richard Earnshaw (rearnsha@arm.com)
7 Minor hacks by Nick Clifton (nickc@cygnus.com)
9 This file is part of GCC.
11 GCC is free software; you can redistribute it and/or modify it
12 under the terms of the GNU General Public License as published
13 by the Free Software Foundation; either version 2, or (at your
14 option) any later version.
16 GCC is distributed in the hope that it will be useful, but WITHOUT
17 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
18 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
19 License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GCC; see the file COPYING. If not, write to
23 the Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
24 MA 02110-1301, USA. */
29 /* The architecture define. */
30 extern char arm_arch_name[];
32 /* Target CPU builtins. */
33 #define TARGET_CPU_CPP_BUILTINS() \
36 /* Define __arm__ even when in thumb mode, for \
37 consistency with armcc. */ \
38 builtin_define ("__arm__"); \
39 builtin_define ("__APCS_32__"); \
41 builtin_define ("__thumb__"); \
45 builtin_define ("__ARMEB__"); \
47 builtin_define ("__THUMBEB__"); \
48 if (TARGET_LITTLE_WORDS) \
49 builtin_define ("__ARMWEL__"); \
53 builtin_define ("__ARMEL__"); \
55 builtin_define ("__THUMBEL__"); \
58 if (TARGET_SOFT_FLOAT) \
59 builtin_define ("__SOFTFP__"); \
62 builtin_define ("__VFP_FP__"); \
64 /* Add a define for interworking. \
65 Needed when building libgcc.a. */ \
66 if (arm_cpp_interwork) \
67 builtin_define ("__THUMB_INTERWORK__"); \
69 builtin_assert ("cpu=arm"); \
70 builtin_assert ("machine=arm"); \
72 builtin_define (arm_arch_name); \
73 if (arm_arch_cirrus) \
74 builtin_define ("__MAVERICK__"); \
75 if (arm_arch_xscale) \
76 builtin_define ("__XSCALE__"); \
77 if (arm_arch_iwmmxt) \
78 builtin_define ("__IWMMXT__"); \
79 if (TARGET_AAPCS_BASED) \
80 builtin_define ("__ARM_EABI__"); \
83 /* The various ARM cores. */
86 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
88 #include "arm-cores.def"
90 /* Used to indicate that no processor has been specified. */
96 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
98 #include "arm-cores.def"
103 /* The processor for which instructions should be scheduled. */
104 extern enum processor_type arm_tune;
106 typedef enum arm_cond_code
108 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC,
109 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV
113 extern arm_cc arm_current_cc;
115 #define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1))
117 extern int arm_target_label;
118 extern int arm_ccfsm_state;
119 extern GTY(()) rtx arm_target_insn;
120 /* Define the information needed to generate branch insns. This is
121 stored from the compare operation. */
122 extern GTY(()) rtx arm_compare_op0;
123 extern GTY(()) rtx arm_compare_op1;
124 /* The label of the current constant pool. */
125 extern rtx pool_vector_label;
126 /* Set to 1 when a return insn is output, this means that the epilogue
128 extern int return_used_this_function;
129 /* Used to produce AOF syntax assembler. */
130 extern GTY(()) rtx aof_pic_label;
132 /* Just in case configure has failed to define anything. */
133 #ifndef TARGET_CPU_DEFAULT
134 #define TARGET_CPU_DEFAULT TARGET_CPU_generic
139 #define CPP_SPEC "%(subtarget_cpp_spec) \
140 %{msoft-float:%{mhard-float: \
141 %e-msoft-float and -mhard_float may not be used together}} \
142 %{mbig-endian:%{mlittle-endian: \
143 %e-mbig-endian and -mlittle-endian may not be used together}}"
149 /* This macro defines names of additional specifications to put in the specs
150 that can be used in various specifications like CC1_SPEC. Its definition
151 is an initializer with a subgrouping for each command option.
153 Each subgrouping contains a string constant, that defines the
154 specification name, and a string constant that used by the GCC driver
157 Do not define this macro if it does not need to do anything. */
158 #define EXTRA_SPECS \
159 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
160 SUBTARGET_EXTRA_SPECS
162 #ifndef SUBTARGET_EXTRA_SPECS
163 #define SUBTARGET_EXTRA_SPECS
166 #ifndef SUBTARGET_CPP_SPEC
167 #define SUBTARGET_CPP_SPEC ""
170 /* Run-time Target Specification. */
171 #ifndef TARGET_VERSION
172 #define TARGET_VERSION fputs (" (ARM/generic)", stderr);
175 #define TARGET_SOFT_FLOAT (arm_float_abi == ARM_FLOAT_ABI_SOFT)
176 /* Use hardware floating point instructions. */
177 #define TARGET_HARD_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT)
178 /* Use hardware floating point calling convention. */
179 #define TARGET_HARD_FLOAT_ABI (arm_float_abi == ARM_FLOAT_ABI_HARD)
180 #define TARGET_FPA (arm_fp_model == ARM_FP_MODEL_FPA)
181 #define TARGET_MAVERICK (arm_fp_model == ARM_FP_MODEL_MAVERICK)
182 #define TARGET_VFP (arm_fp_model == ARM_FP_MODEL_VFP)
183 #define TARGET_IWMMXT (arm_arch_iwmmxt)
184 #define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_ARM)
185 #define TARGET_IWMMXT_ABI (TARGET_ARM && arm_abi == ARM_ABI_IWMMXT)
186 #define TARGET_ARM (! TARGET_THUMB)
187 #define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */
188 #define TARGET_BACKTRACE (leaf_function_p () \
189 ? TARGET_TPCS_LEAF_FRAME \
191 #define TARGET_LDRD (arm_arch5e && ARM_DOUBLEWORD_ALIGN)
192 #define TARGET_AAPCS_BASED \
193 (arm_abi != ARM_ABI_APCS && arm_abi != ARM_ABI_ATPCS)
195 #define TARGET_HARD_TP (target_thread_pointer == TP_CP15)
196 #define TARGET_SOFT_TP (target_thread_pointer == TP_SOFT)
198 /* True iff the full BPABI is being used. If TARGET_BPABI is true,
199 then TARGET_AAPCS_BASED must be true -- but the converse does not
200 hold. TARGET_BPABI implies the use of the BPABI runtime library,
201 etc., in addition to just the AAPCS calling conventions. */
203 #define TARGET_BPABI false
206 /* Support for a compile-time default CPU, et cetera. The rules are:
207 --with-arch is ignored if -march or -mcpu are specified.
208 --with-cpu is ignored if -march or -mcpu are specified, and is overridden
210 --with-tune is ignored if -mtune or -mcpu are specified (but not affected
212 --with-float is ignored if -mhard-float, -msoft-float or -mfloat-abi are
214 --with-fpu is ignored if -mfpu is specified.
215 --with-abi is ignored is -mabi is specified. */
216 #define OPTION_DEFAULT_SPECS \
217 {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \
218 {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \
219 {"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}" }, \
221 "%{!msoft-float:%{!mhard-float:%{!mfloat-abi=*:-mfloat-abi=%(VALUE)}}}" }, \
222 {"fpu", "%{!mfpu=*:-mfpu=%(VALUE)}"}, \
223 {"abi", "%{!mabi=*:-mabi=%(VALUE)}"}, \
224 {"mode", "%{!marm:%{!mthumb:-m%(VALUE)}}"},
226 /* Which floating point model to use. */
229 ARM_FP_MODEL_UNKNOWN,
230 /* FPA model (Hardware or software). */
232 /* Cirrus Maverick floating point model. */
233 ARM_FP_MODEL_MAVERICK,
234 /* VFP floating point model. */
238 extern enum arm_fp_model arm_fp_model;
240 /* Which floating point hardware is available. Also update
241 fp_model_for_fpu in arm.c when adding entries to this list. */
244 /* No FP hardware. */
246 /* Full FPA support. */
248 /* Emulated FPA hardware, Issue 2 emulator (no LFM/SFM). */
250 /* Emulated FPA hardware, Issue 3 emulator. */
252 /* Cirrus Maverick floating point co-processor. */
258 /* Recast the floating point class to be the floating point attribute. */
259 #define arm_fpu_attr ((enum attr_fpu) arm_fpu_tune)
261 /* What type of floating point to tune for */
262 extern enum fputype arm_fpu_tune;
264 /* What type of floating point instructions are available */
265 extern enum fputype arm_fpu_arch;
270 ARM_FLOAT_ABI_SOFTFP,
274 extern enum float_abi_type arm_float_abi;
276 #ifndef TARGET_DEFAULT_FLOAT_ABI
277 #define TARGET_DEFAULT_FLOAT_ABI ARM_FLOAT_ABI_SOFT
280 /* Which ABI to use. */
290 extern enum arm_abi_type arm_abi;
292 #ifndef ARM_DEFAULT_ABI
293 #define ARM_DEFAULT_ABI ARM_ABI_APCS
296 /* Which thread pointer access sequence to use. */
303 extern enum arm_tp_type target_thread_pointer;
305 /* Nonzero if this chip supports the ARM Architecture 3M extensions. */
306 extern int arm_arch3m;
308 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
309 extern int arm_arch4;
311 /* Nonzero if this chip supports the ARM Architecture 4T extensions. */
312 extern int arm_arch4t;
314 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
315 extern int arm_arch5;
317 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
318 extern int arm_arch5e;
320 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */
321 extern int arm_arch6;
323 /* Nonzero if this chip can benefit from load scheduling. */
324 extern int arm_ld_sched;
326 /* Nonzero if generating thumb code. */
327 extern int thumb_code;
329 /* Nonzero if this chip is a StrongARM. */
330 extern int arm_tune_strongarm;
332 /* Nonzero if this chip is a Cirrus variant. */
333 extern int arm_arch_cirrus;
335 /* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */
336 extern int arm_arch_iwmmxt;
338 /* Nonzero if this chip is an XScale. */
339 extern int arm_arch_xscale;
341 /* Nonzero if tuning for XScale. */
342 extern int arm_tune_xscale;
344 /* Nonzero if tuning for stores via the write buffer. */
345 extern int arm_tune_wbuf;
347 /* Nonzero if we should define __THUMB_INTERWORK__ in the
349 XXX This is a bit of a hack, it's intended to help work around
350 problems in GLD which doesn't understand that armv5t code is
351 interworking clean. */
352 extern int arm_cpp_interwork;
354 #ifndef TARGET_DEFAULT
355 #define TARGET_DEFAULT (MASK_APCS_FRAME)
358 /* The frame pointer register used in gcc has nothing to do with debugging;
359 that is controlled by the APCS-FRAME option. */
360 #define CAN_DEBUG_WITHOUT_FP
362 #define OVERRIDE_OPTIONS arm_override_options ()
364 /* Nonzero if PIC code requires explicit qualifiers to generate
365 PLT and GOT relocs rather than the assembler doing so implicitly.
366 Subtargets can override these if required. */
367 #ifndef NEED_GOT_RELOC
368 #define NEED_GOT_RELOC 0
370 #ifndef NEED_PLT_RELOC
371 #define NEED_PLT_RELOC 0
374 /* Nonzero if we need to refer to the GOT with a PC-relative
375 offset. In other words, generate
377 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)]
381 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8)
383 The default is true, which matches NetBSD. Subtargets can
384 override this if required. */
389 /* Target machine storage Layout. */
392 /* Define this macro if it is advisable to hold scalars in registers
393 in a wider mode than that declared by the program. In such cases,
394 the value is constrained to be within the bounds of the declared
395 type, but kept valid in the wider mode. The signedness of the
396 extension may differ from that of the type. */
398 /* It is far faster to zero extend chars than to sign extend them */
400 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
401 if (GET_MODE_CLASS (MODE) == MODE_INT \
402 && GET_MODE_SIZE (MODE) < 4) \
404 if (MODE == QImode) \
406 else if (MODE == HImode) \
411 #define PROMOTE_FUNCTION_MODE(MODE, UNSIGNEDP, TYPE) \
412 if ((GET_MODE_CLASS (MODE) == MODE_INT \
413 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_INT) \
414 && GET_MODE_SIZE (MODE) < 4) \
417 /* Define this if most significant bit is lowest numbered
418 in instructions that operate on numbered bit-fields. */
419 #define BITS_BIG_ENDIAN 0
421 /* Define this if most significant byte of a word is the lowest numbered.
422 Most ARM processors are run in little endian mode, so that is the default.
423 If you want to have it run-time selectable, change the definition in a
424 cover file to be TARGET_BIG_ENDIAN. */
425 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
427 /* Define this if most significant word of a multiword number is the lowest
429 This is always false, even when in big-endian mode. */
430 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS)
432 /* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based
433 on processor pre-defineds when compiling libgcc2.c. */
434 #if defined(__ARMEB__) && !defined(__ARMWEL__)
435 #define LIBGCC2_WORDS_BIG_ENDIAN 1
437 #define LIBGCC2_WORDS_BIG_ENDIAN 0
440 /* Define this if most significant word of doubles is the lowest numbered.
441 The rules are different based on whether or not we use FPA-format,
442 VFP-format or some other floating point co-processor's format doubles. */
443 #define FLOAT_WORDS_BIG_ENDIAN (arm_float_words_big_endian ())
445 #define UNITS_PER_WORD 4
447 /* True if natural alignment is used for doubleword types. */
448 #define ARM_DOUBLEWORD_ALIGN TARGET_AAPCS_BASED
450 #define DOUBLEWORD_ALIGNMENT 64
452 #define PARM_BOUNDARY 32
454 #define STACK_BOUNDARY (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
456 #define PREFERRED_STACK_BOUNDARY \
457 (arm_abi == ARM_ABI_ATPCS ? 64 : STACK_BOUNDARY)
459 #define FUNCTION_BOUNDARY 32
461 /* The lowest bit is used to indicate Thumb-mode functions, so the
462 vbit must go into the delta field of pointers to member
464 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
466 #define EMPTY_FIELD_BOUNDARY 32
468 #define BIGGEST_ALIGNMENT (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
470 /* XXX Blah -- this macro is used directly by libobjc. Since it
471 supports no vector modes, cut out the complexity and fall back
472 on BIGGEST_FIELD_ALIGNMENT. */
473 #ifdef IN_TARGET_LIBS
474 #define BIGGEST_FIELD_ALIGNMENT 64
477 /* Make strings word-aligned so strcpy from constants will be faster. */
478 #define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_tune_xscale ? 1 : 2)
480 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
481 ((TREE_CODE (EXP) == STRING_CST \
482 && (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \
483 ? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN))
485 /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the
486 value set in previous versions of this toolchain was 8, which produces more
487 compact structures. The command line option -mstructure_size_boundary=<n>
488 can be used to change this value. For compatibility with the ARM SDK
489 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI
490 0020D) page 2-20 says "Structures are aligned on word boundaries".
491 The AAPCS specifies a value of 8. */
492 #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary
493 extern int arm_structure_size_boundary;
495 /* This is the value used to initialize arm_structure_size_boundary. If a
496 particular arm target wants to change the default value it should change
497 the definition of this macro, not STRUCTURE_SIZE_BOUNDARY. See netbsd.h
498 for an example of this. */
499 #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY
500 #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32
503 /* Nonzero if move instructions will actually fail to work
504 when given unaligned data. */
505 #define STRICT_ALIGNMENT 1
507 /* wchar_t is unsigned under the AAPCS. */
509 #define WCHAR_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "int")
510 #undef WCHAR_TYPE_SIZE
511 #define WCHAR_TYPE_SIZE BITS_PER_WORD
515 #define SIZE_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "long unsigned int")
519 #define PTRDIFF_TYPE (TARGET_AAPCS_BASED ? "int" : "long int")
522 /* AAPCS requires that structure alignment is affected by bitfields. */
523 #ifndef PCC_BITFIELD_TYPE_MATTERS
524 #define PCC_BITFIELD_TYPE_MATTERS TARGET_AAPCS_BASED
528 /* Standard register usage. */
530 /* Register allocation in ARM Procedure Call Standard (as used on RISCiX):
531 (S - saved over call).
533 r0 * argument word/integer result
536 r4-r8 S register variable
537 r9 S (rfp) register variable (real frame pointer)
539 r10 F S (sl) stack limit (used by -mapcs-stack-check)
540 r11 F S (fp) argument pointer
541 r12 (ip) temp workspace
542 r13 F S (sp) lower end of current stack frame
543 r14 (lr) link address/workspace
544 r15 F (pc) program counter
546 f0 floating point result
547 f1-f3 floating point scratch
549 f4-f7 S floating point variable
551 cc This is NOT a real register, but is used internally
552 to represent things that use or set the condition
554 sfp This isn't either. It is used during rtl generation
555 since the offset between the frame pointer and the
556 auto's isn't known until after register allocation.
557 afp Nor this, we only need this because of non-local
558 goto. Without it fp appears to be used and the
559 elimination code won't get rid of sfp. It tracks
560 fp exactly at all times.
562 *: See CONDITIONAL_REGISTER_USAGE */
565 mvf0 Cirrus floating point result
566 mvf1-mvf3 Cirrus floating point scratch
567 mvf4-mvf15 S Cirrus floating point variable. */
569 /* s0-s15 VFP scratch (aka d0-d7).
570 s16-s31 S VFP variable (aka d8-d15).
571 vfpcc Not a real register. Represents the VFP condition
574 /* The stack backtrace structure is as follows:
575 fp points to here: | save code pointer | [fp]
576 | return link value | [fp, #-4]
577 | return sp value | [fp, #-8]
578 | return fp value | [fp, #-12]
579 [| saved r10 value |]
590 [| saved f7 value |] three words
591 [| saved f6 value |] three words
592 [| saved f5 value |] three words
593 [| saved f4 value |] three words
594 r0-r3 are not normally saved in a C function. */
596 /* 1 for registers that have pervasive standard uses
597 and are not available for the register allocator. */
598 #define FIXED_REGISTERS \
616 /* 1 for registers not available across function calls.
617 These must include the FIXED_REGISTERS and also any
618 registers that can be used without being saved.
619 The latter must include the registers where values are returned
620 and the register where structure-value addresses are passed.
621 Aside from that, you can include as many other registers as you like.
622 The CC is not preserved over function calls on the ARM 6, so it is
623 easier to assume this for all. SFP is preserved, since FP is. */
624 #define CALL_USED_REGISTERS \
642 #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
643 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
646 #define CONDITIONAL_REGISTER_USAGE \
650 if (TARGET_SOFT_FLOAT || TARGET_THUMB || !TARGET_FPA) \
652 for (regno = FIRST_FPA_REGNUM; \
653 regno <= LAST_FPA_REGNUM; ++regno) \
654 fixed_regs[regno] = call_used_regs[regno] = 1; \
657 if (TARGET_THUMB && optimize_size) \
659 /* When optimizing for size, it's better not to use \
660 the HI regs, because of the overhead of stacking \
662 for (regno = FIRST_HI_REGNUM; \
663 regno <= LAST_HI_REGNUM; ++regno) \
664 fixed_regs[regno] = call_used_regs[regno] = 1; \
667 /* The link register can be clobbered by any branch insn, \
668 but we have no way to track that at present, so mark \
669 it as unavailable. */ \
671 fixed_regs[LR_REGNUM] = call_used_regs[LR_REGNUM] = 1; \
673 if (TARGET_ARM && TARGET_HARD_FLOAT) \
675 if (TARGET_MAVERICK) \
677 for (regno = FIRST_FPA_REGNUM; \
678 regno <= LAST_FPA_REGNUM; ++ regno) \
679 fixed_regs[regno] = call_used_regs[regno] = 1; \
680 for (regno = FIRST_CIRRUS_FP_REGNUM; \
681 regno <= LAST_CIRRUS_FP_REGNUM; ++ regno) \
683 fixed_regs[regno] = 0; \
684 call_used_regs[regno] = regno < FIRST_CIRRUS_FP_REGNUM + 4; \
689 for (regno = FIRST_VFP_REGNUM; \
690 regno <= LAST_VFP_REGNUM; ++ regno) \
692 fixed_regs[regno] = 0; \
693 call_used_regs[regno] = regno < FIRST_VFP_REGNUM + 16; \
698 if (TARGET_REALLY_IWMMXT) \
700 regno = FIRST_IWMMXT_GR_REGNUM; \
701 /* The 2002/10/09 revision of the XScale ABI has wCG0 \
702 and wCG1 as call-preserved registers. The 2002/11/21 \
703 revision changed this so that all wCG registers are \
704 scratch registers. */ \
705 for (regno = FIRST_IWMMXT_GR_REGNUM; \
706 regno <= LAST_IWMMXT_GR_REGNUM; ++ regno) \
707 fixed_regs[regno] = 0; \
708 /* The XScale ABI has wR0 - wR9 as scratch registers, \
709 the rest as call-preserved registers. */ \
710 for (regno = FIRST_IWMMXT_REGNUM; \
711 regno <= LAST_IWMMXT_REGNUM; ++ regno) \
713 fixed_regs[regno] = 0; \
714 call_used_regs[regno] = regno < FIRST_IWMMXT_REGNUM + 10; \
718 if ((unsigned) PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
720 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
721 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
723 else if (TARGET_APCS_STACK) \
725 fixed_regs[10] = 1; \
726 call_used_regs[10] = 1; \
728 /* -mcaller-super-interworking reserves r11 for calls to \
729 _interwork_r11_call_via_rN(). Making the register global \
730 is an easy way of ensuring that it remains valid for all \
732 if (TARGET_APCS_FRAME || TARGET_CALLER_INTERWORKING \
733 || TARGET_TPCS_FRAME || TARGET_TPCS_LEAF_FRAME) \
735 fixed_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
736 call_used_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
737 if (TARGET_CALLER_INTERWORKING) \
738 global_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
740 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
743 /* These are a couple of extensions to the formats accepted
745 %@ prints out ASM_COMMENT_START
746 %r prints out REGISTER_PREFIX reg_names[arg] */
747 #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \
749 fputs (ASM_COMMENT_START, FILE); \
753 fputs (REGISTER_PREFIX, FILE); \
754 fputs (reg_names [va_arg (ARGS, int)], FILE); \
757 /* Round X up to the nearest word. */
758 #define ROUND_UP_WORD(X) (((X) + 3) & ~3)
760 /* Convert fron bytes to ints. */
761 #define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
763 /* The number of (integer) registers required to hold a quantity of type MODE.
764 Also used for VFP registers. */
765 #define ARM_NUM_REGS(MODE) \
766 ARM_NUM_INTS (GET_MODE_SIZE (MODE))
768 /* The number of (integer) registers required to hold a quantity of TYPE MODE. */
769 #define ARM_NUM_REGS2(MODE, TYPE) \
770 ARM_NUM_INTS ((MODE) == BLKmode ? \
771 int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE))
773 /* The number of (integer) argument register available. */
774 #define NUM_ARG_REGS 4
776 /* Return the register number of the N'th (integer) argument. */
777 #define ARG_REGISTER(N) (N - 1)
779 /* Specify the registers used for certain standard purposes.
780 The values of these macros are register numbers. */
782 /* The number of the last argument register. */
783 #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS)
785 /* The numbers of the Thumb register ranges. */
786 #define FIRST_LO_REGNUM 0
787 #define LAST_LO_REGNUM 7
788 #define FIRST_HI_REGNUM 8
789 #define LAST_HI_REGNUM 11
791 #ifndef TARGET_UNWIND_INFO
792 /* We use sjlj exceptions for backwards compatibility. */
793 #define MUST_USE_SJLJ_EXCEPTIONS 1
796 /* We can generate DWARF2 Unwind info, even though we don't use it. */
797 #define DWARF2_UNWIND_INFO 1
799 /* Use r0 and r1 to pass exception handling information. */
800 #define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? N : INVALID_REGNUM)
802 /* The register that holds the return address in exception handlers. */
803 #define ARM_EH_STACKADJ_REGNUM 2
804 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, ARM_EH_STACKADJ_REGNUM)
806 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain
807 as an invisible last argument (possible since varargs don't exist in
808 Pascal), so the following is not true. */
809 #define STATIC_CHAIN_REGNUM (TARGET_ARM ? 12 : 9)
811 /* Define this to be where the real frame pointer is if it is not possible to
812 work out the offset between the frame pointer and the automatic variables
813 until after register allocation has taken place. FRAME_POINTER_REGNUM
814 should point to a special register that we will make sure is eliminated.
816 For the Thumb we have another problem. The TPCS defines the frame pointer
817 as r11, and GCC believes that it is always possible to use the frame pointer
818 as base register for addressing purposes. (See comments in
819 find_reloads_address()). But - the Thumb does not allow high registers,
820 including r11, to be used as base address registers. Hence our problem.
822 The solution used here, and in the old thumb port is to use r7 instead of
823 r11 as the hard frame pointer and to have special code to generate
824 backtrace structures on the stack (if required to do so via a command line
825 option) using r11. This is the only 'user visible' use of r11 as a frame
827 #define ARM_HARD_FRAME_POINTER_REGNUM 11
828 #define THUMB_HARD_FRAME_POINTER_REGNUM 7
830 #define HARD_FRAME_POINTER_REGNUM \
832 ? ARM_HARD_FRAME_POINTER_REGNUM \
833 : THUMB_HARD_FRAME_POINTER_REGNUM)
835 #define FP_REGNUM HARD_FRAME_POINTER_REGNUM
837 /* Register to use for pushing function arguments. */
838 #define STACK_POINTER_REGNUM SP_REGNUM
840 /* ARM floating pointer registers. */
841 #define FIRST_FPA_REGNUM 16
842 #define LAST_FPA_REGNUM 23
843 #define IS_FPA_REGNUM(REGNUM) \
844 (((REGNUM) >= FIRST_FPA_REGNUM) && ((REGNUM) <= LAST_FPA_REGNUM))
846 #define FIRST_IWMMXT_GR_REGNUM 43
847 #define LAST_IWMMXT_GR_REGNUM 46
848 #define FIRST_IWMMXT_REGNUM 47
849 #define LAST_IWMMXT_REGNUM 62
850 #define IS_IWMMXT_REGNUM(REGNUM) \
851 (((REGNUM) >= FIRST_IWMMXT_REGNUM) && ((REGNUM) <= LAST_IWMMXT_REGNUM))
852 #define IS_IWMMXT_GR_REGNUM(REGNUM) \
853 (((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <= LAST_IWMMXT_GR_REGNUM))
855 /* Base register for access to local variables of the function. */
856 #define FRAME_POINTER_REGNUM 25
858 /* Base register for access to arguments of the function. */
859 #define ARG_POINTER_REGNUM 26
861 #define FIRST_CIRRUS_FP_REGNUM 27
862 #define LAST_CIRRUS_FP_REGNUM 42
863 #define IS_CIRRUS_REGNUM(REGNUM) \
864 (((REGNUM) >= FIRST_CIRRUS_FP_REGNUM) && ((REGNUM) <= LAST_CIRRUS_FP_REGNUM))
866 #define FIRST_VFP_REGNUM 63
867 #define LAST_VFP_REGNUM 94
868 #define IS_VFP_REGNUM(REGNUM) \
869 (((REGNUM) >= FIRST_VFP_REGNUM) && ((REGNUM) <= LAST_VFP_REGNUM))
871 /* The number of hard registers is 16 ARM + 8 FPA + 1 CC + 1 SFP + 1 AFP. */
872 /* + 16 Cirrus registers take us up to 43. */
873 /* Intel Wireless MMX Technology registers add 16 + 4 more. */
874 /* VFP adds 32 + 1 more. */
875 #define FIRST_PSEUDO_REGISTER 96
877 #define DBX_REGISTER_NUMBER(REGNO) arm_dbx_register_number (REGNO)
879 /* Value should be nonzero if functions must have frame pointers.
880 Zero means the frame pointer need not be set up (and parms may be accessed
881 via the stack pointer) in functions that seem suitable.
882 If we have to have a frame pointer we might as well make use of it.
883 APCS says that the frame pointer does not need to be pushed in leaf
884 functions, or simple tail call functions. */
886 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED
887 #define SUBTARGET_FRAME_POINTER_REQUIRED 0
890 #define FRAME_POINTER_REQUIRED \
891 (current_function_has_nonlocal_label \
892 || SUBTARGET_FRAME_POINTER_REQUIRED \
893 || (TARGET_ARM && TARGET_APCS_FRAME && ! leaf_function_p ()))
895 /* Return number of consecutive hard regs needed starting at reg REGNO
896 to hold something of mode MODE.
897 This is ordinarily the length in words of a value of mode MODE
898 but can be less for certain modes in special long registers.
900 On the ARM regs are UNITS_PER_WORD bits wide; FPA regs can hold any FP
902 #define HARD_REGNO_NREGS(REGNO, MODE) \
904 && REGNO >= FIRST_FPA_REGNUM \
905 && REGNO != FRAME_POINTER_REGNUM \
906 && REGNO != ARG_POINTER_REGNUM) \
907 && !IS_VFP_REGNUM (REGNO) \
908 ? 1 : ARM_NUM_REGS (MODE))
910 /* Return true if REGNO is suitable for holding a quantity of type MODE. */
911 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
912 arm_hard_regno_mode_ok ((REGNO), (MODE))
914 /* Value is 1 if it is a good idea to tie two pseudo registers
915 when one has mode MODE1 and one has mode MODE2.
916 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
917 for any hard reg, then this must be 0 for correct output. */
918 #define MODES_TIEABLE_P(MODE1, MODE2) \
919 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
921 #define VALID_IWMMXT_REG_MODE(MODE) \
922 (arm_vector_mode_supported_p (MODE) || (MODE) == DImode)
924 /* The order in which register should be allocated. It is good to use ip
925 since no saving is required (though calls clobber it) and it never contains
926 function parameters. It is quite good to use lr since other calls may
927 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
928 least likely to contain a function parameter; in addition results are
931 #define REG_ALLOC_ORDER \
933 3, 2, 1, 0, 12, 14, 4, 5, \
934 6, 7, 8, 10, 9, 11, 13, 15, \
935 16, 17, 18, 19, 20, 21, 22, 23, \
936 27, 28, 29, 30, 31, 32, 33, 34, \
937 35, 36, 37, 38, 39, 40, 41, 42, \
938 43, 44, 45, 46, 47, 48, 49, 50, \
939 51, 52, 53, 54, 55, 56, 57, 58, \
942 78, 77, 76, 75, 74, 73, 72, 71, \
943 70, 69, 68, 67, 66, 65, 64, 63, \
944 79, 80, 81, 82, 83, 84, 85, 86, \
945 87, 88, 89, 90, 91, 92, 93, 94, \
949 /* Interrupt functions can only use registers that have already been
950 saved by the prologue, even if they would normally be
952 #define HARD_REGNO_RENAME_OK(SRC, DST) \
953 (! IS_INTERRUPT (cfun->machine->func_type) || \
956 /* Register and constant classes. */
958 /* Register classes: used to be simple, just all ARM regs or all FPA regs
959 Now that the Thumb is involved it has become more complicated. */
979 #define N_REG_CLASSES (int) LIM_REG_CLASSES
981 /* Give names of register classes as strings for dump file. */
982 #define REG_CLASS_NAMES \
1000 /* Define which registers fit in which classes.
1001 This is an initializer for a vector of HARD_REG_SET
1002 of length N_REG_CLASSES. */
1003 #define REG_CLASS_CONTENTS \
1005 { 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1006 { 0x00FF0000, 0x00000000, 0x00000000 }, /* FPA_REGS */ \
1007 { 0xF8000000, 0x000007FF, 0x00000000 }, /* CIRRUS_REGS */ \
1008 { 0x00000000, 0x80000000, 0x7FFFFFFF }, /* VFP_REGS */ \
1009 { 0x00000000, 0x00007800, 0x00000000 }, /* IWMMXT_GR_REGS */ \
1010 { 0x00000000, 0x7FFF8000, 0x00000000 }, /* IWMMXT_REGS */ \
1011 { 0x000000FF, 0x00000000, 0x00000000 }, /* LO_REGS */ \
1012 { 0x00002000, 0x00000000, 0x00000000 }, /* STACK_REG */ \
1013 { 0x000020FF, 0x00000000, 0x00000000 }, /* BASE_REGS */ \
1014 { 0x0000FF00, 0x00000000, 0x00000000 }, /* HI_REGS */ \
1015 { 0x01000000, 0x00000000, 0x00000000 }, /* CC_REG */ \
1016 { 0x00000000, 0x00000000, 0x80000000 }, /* VFPCC_REG */ \
1017 { 0x0200FFFF, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \
1018 { 0xFAFFFFFF, 0xFFFFFFFF, 0x7FFFFFFF } /* ALL_REGS */ \
1021 /* The same information, inverted:
1022 Return the class number of the smallest class containing
1023 reg number REGNO. This could be a conditional expression
1024 or could index an array. */
1025 #define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO)
1027 /* FPA registers can't do subreg as all values are reformatted to internal
1028 precision. VFP registers may only be accessed in the mode they
1030 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1031 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
1032 ? reg_classes_intersect_p (FPA_REGS, (CLASS)) \
1033 || reg_classes_intersect_p (VFP_REGS, (CLASS)) \
1036 /* We need to define this for LO_REGS on thumb. Otherwise we can end up
1037 using r0-r4 for function arguments, r7 for the stack frame and don't
1038 have enough left over to do doubleword arithmetic. */
1039 #define CLASS_LIKELY_SPILLED_P(CLASS) \
1040 ((TARGET_THUMB && (CLASS) == LO_REGS) \
1041 || (CLASS) == CC_REG)
1043 /* The class value for index registers, and the one for base regs. */
1044 #define INDEX_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS)
1045 #define BASE_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS)
1047 /* For the Thumb the high registers cannot be used as base registers
1048 when addressing quantities in QI or HI mode; if we don't know the
1049 mode, then we must be conservative. */
1050 #define MODE_BASE_REG_CLASS(MODE) \
1051 (TARGET_ARM ? GENERAL_REGS : \
1052 (((MODE) == SImode) ? BASE_REGS : LO_REGS))
1054 /* For Thumb we can not support SP+reg addressing, so we return LO_REGS
1055 instead of BASE_REGS. */
1056 #define MODE_BASE_REG_REG_CLASS(MODE) BASE_REG_CLASS
1058 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1059 registers explicitly used in the rtl to be used as spill registers
1060 but prevents the compiler from extending the lifetime of these
1062 #define SMALL_REGISTER_CLASSES TARGET_THUMB
1064 /* Given an rtx X being reloaded into a reg required to be
1065 in class CLASS, return the class of reg to actually use.
1066 In general this is just CLASS, but for the Thumb we prefer
1067 a LO_REGS class or a subset. */
1068 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1069 (TARGET_ARM ? (CLASS) : \
1070 ((CLASS) == BASE_REGS ? (CLASS) : LO_REGS))
1072 /* Must leave BASE_REGS reloads alone */
1073 #define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1074 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1075 ? ((true_regnum (X) == -1 ? LO_REGS \
1076 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1080 #define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1081 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1082 ? ((true_regnum (X) == -1 ? LO_REGS \
1083 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1087 /* Return the register class of a scratch register needed to copy IN into
1088 or out of a register in CLASS in MODE. If it can be done directly,
1089 NO_REGS is returned. */
1090 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1091 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \
1092 ((TARGET_VFP && TARGET_HARD_FLOAT \
1093 && (CLASS) == VFP_REGS) \
1094 ? coproc_secondary_reload_class (MODE, X, FALSE) \
1095 : (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) \
1096 ? coproc_secondary_reload_class (MODE, X, TRUE) \
1098 ? (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \
1099 ? GENERAL_REGS : NO_REGS) \
1100 : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X))
1102 /* If we need to load shorts byte-at-a-time, then we need a scratch. */
1103 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1104 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \
1105 ((TARGET_VFP && TARGET_HARD_FLOAT \
1106 && (CLASS) == VFP_REGS) \
1107 ? coproc_secondary_reload_class (MODE, X, FALSE) : \
1108 (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) ? \
1109 coproc_secondary_reload_class (MODE, X, TRUE) : \
1110 /* Cannot load constants into Cirrus registers. */ \
1111 (TARGET_MAVERICK && TARGET_HARD_FLOAT \
1112 && (CLASS) == CIRRUS_REGS \
1113 && (CONSTANT_P (X) || GET_CODE (X) == SYMBOL_REF)) \
1116 (((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \
1117 && CONSTANT_P (X)) \
1119 (((MODE) == HImode && ! arm_arch4 \
1120 && (GET_CODE (X) == MEM \
1121 || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \
1122 && true_regnum (X) == -1))) \
1123 ? GENERAL_REGS : NO_REGS) \
1124 : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X)))
1126 /* Try a machine-dependent way of reloading an illegitimate address
1127 operand. If we find one, push the reload and jump to WIN. This
1128 macro is used in only one place: `find_reloads_address' in reload.c.
1130 For the ARM, we wish to handle large displacements off a base
1131 register by splitting the addend across a MOV and the mem insn.
1132 This can cut the number of reloads needed. */
1133 #define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \
1136 if (GET_CODE (X) == PLUS \
1137 && GET_CODE (XEXP (X, 0)) == REG \
1138 && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \
1139 && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \
1140 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1142 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1143 HOST_WIDE_INT low, high; \
1145 if (MODE == DImode || (MODE == DFmode && TARGET_SOFT_FLOAT)) \
1146 low = ((val & 0xf) ^ 0x8) - 0x8; \
1147 else if (TARGET_MAVERICK && TARGET_HARD_FLOAT) \
1148 /* Need to be careful, -256 is not a valid offset. */ \
1149 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1150 else if (MODE == SImode \
1151 || (MODE == SFmode && TARGET_SOFT_FLOAT) \
1152 || ((MODE == HImode || MODE == QImode) && ! arm_arch4)) \
1153 /* Need to be careful, -4096 is not a valid offset. */ \
1154 low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff); \
1155 else if ((MODE == HImode || MODE == QImode) && arm_arch4) \
1156 /* Need to be careful, -256 is not a valid offset. */ \
1157 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1158 else if (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1159 && TARGET_HARD_FLOAT && TARGET_FPA) \
1160 /* Need to be careful, -1024 is not a valid offset. */ \
1161 low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \
1165 high = ((((val - low) & (unsigned HOST_WIDE_INT) 0xffffffff) \
1166 ^ (unsigned HOST_WIDE_INT) 0x80000000) \
1167 - (unsigned HOST_WIDE_INT) 0x80000000); \
1168 /* Check for overflow or zero */ \
1169 if (low == 0 || high == 0 || (high + low != val)) \
1172 /* Reload the high part into a base reg; leave the low part \
1174 X = gen_rtx_PLUS (GET_MODE (X), \
1175 gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \
1178 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
1179 MODE_BASE_REG_CLASS (MODE), GET_MODE (X), \
1180 VOIDmode, 0, 0, OPNUM, TYPE); \
1186 /* XXX If an HImode FP+large_offset address is converted to an HImode
1187 SP+large_offset address, then reload won't know how to fix it. It sees
1188 only that SP isn't valid for HImode, and so reloads the SP into an index
1189 register, but the resulting address is still invalid because the offset
1190 is too big. We fix it here instead by reloading the entire address. */
1191 /* We could probably achieve better results by defining PROMOTE_MODE to help
1192 cope with the variances between the Thumb's signed and unsigned byte and
1193 halfword load instructions. */
1194 #define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_L, WIN) \
1196 rtx new_x = thumb_legitimize_reload_address (&X, MODE, OPNUM, TYPE, IND_L); \
1204 #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1206 ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \
1208 THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN)
1210 /* Return the maximum number of consecutive registers
1211 needed to represent mode MODE in a register of class CLASS.
1212 ARM regs are UNITS_PER_WORD bits while FPA regs can hold any FP mode */
1213 #define CLASS_MAX_NREGS(CLASS, MODE) \
1214 (((CLASS) == FPA_REGS || (CLASS) == CIRRUS_REGS) ? 1 : ARM_NUM_REGS (MODE))
1216 /* If defined, gives a class of registers that cannot be used as the
1217 operand of a SUBREG that changes the mode of the object illegally. */
1219 /* Moves between FPA_REGS and GENERAL_REGS are two memory insns. */
1220 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
1222 ((FROM) == FPA_REGS && (TO) != FPA_REGS ? 20 : \
1223 (FROM) != FPA_REGS && (TO) == FPA_REGS ? 20 : \
1224 (FROM) == VFP_REGS && (TO) != VFP_REGS ? 10 : \
1225 (FROM) != VFP_REGS && (TO) == VFP_REGS ? 10 : \
1226 (FROM) == IWMMXT_REGS && (TO) != IWMMXT_REGS ? 4 : \
1227 (FROM) != IWMMXT_REGS && (TO) == IWMMXT_REGS ? 4 : \
1228 (FROM) == IWMMXT_GR_REGS || (TO) == IWMMXT_GR_REGS ? 20 : \
1229 (FROM) == CIRRUS_REGS && (TO) != CIRRUS_REGS ? 20 : \
1230 (FROM) != CIRRUS_REGS && (TO) == CIRRUS_REGS ? 20 : \
1233 ((FROM) == HI_REGS || (TO) == HI_REGS) ? 4 : 2)
1235 /* Stack layout; function entry, exit and calling. */
1237 /* Define this if pushing a word on the stack
1238 makes the stack pointer a smaller address. */
1239 #define STACK_GROWS_DOWNWARD 1
1241 /* Define this to nonzero if the nominal address of the stack frame
1242 is at the high-address end of the local variables;
1243 that is, each additional local variable allocated
1244 goes at a more negative offset in the frame. */
1245 #define FRAME_GROWS_DOWNWARD 1
1247 /* The amount of scratch space needed by _interwork_{r7,r11}_call_via_rN().
1248 When present, it is one word in size, and sits at the top of the frame,
1249 between the soft frame pointer and either r7 or r11.
1251 We only need _interwork_rM_call_via_rN() for -mcaller-super-interworking,
1252 and only then if some outgoing arguments are passed on the stack. It would
1253 be tempting to also check whether the stack arguments are passed by indirect
1254 calls, but there seems to be no reason in principle why a post-reload pass
1255 couldn't convert a direct call into an indirect one. */
1256 #define CALLER_INTERWORKING_SLOT_SIZE \
1257 (TARGET_CALLER_INTERWORKING \
1258 && current_function_outgoing_args_size != 0 \
1259 ? UNITS_PER_WORD : 0)
1261 /* Offset within stack frame to start allocating local variables at.
1262 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1263 first local allocated. Otherwise, it is the offset to the BEGINNING
1264 of the first local allocated. */
1265 #define STARTING_FRAME_OFFSET 0
1267 /* If we generate an insn to push BYTES bytes,
1268 this says how many the stack pointer really advances by. */
1269 /* The push insns do not do this rounding implicitly.
1270 So don't define this. */
1271 /* #define PUSH_ROUNDING(NPUSHED) ROUND_UP_WORD (NPUSHED) */
1273 /* Define this if the maximum size of all the outgoing args is to be
1274 accumulated and pushed during the prologue. The amount can be
1275 found in the variable current_function_outgoing_args_size. */
1276 #define ACCUMULATE_OUTGOING_ARGS 1
1278 /* Offset of first parameter from the argument pointer register value. */
1279 #define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0)
1281 /* Value is the number of byte of arguments automatically
1282 popped when returning from a subroutine call.
1283 FUNDECL is the declaration node of the function (as a tree),
1284 FUNTYPE is the data type of the function (as a tree),
1285 or for a library call it is an identifier node for the subroutine name.
1286 SIZE is the number of bytes of arguments passed on the stack.
1288 On the ARM, the caller does not pop any of its arguments that were passed
1290 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0
1292 /* Define how to find the value returned by a library function
1293 assuming the value has mode MODE. */
1294 #define LIBCALL_VALUE(MODE) \
1295 (TARGET_ARM && TARGET_HARD_FLOAT_ABI && TARGET_FPA \
1296 && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1297 ? gen_rtx_REG (MODE, FIRST_FPA_REGNUM) \
1298 : TARGET_ARM && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK \
1299 && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1300 ? gen_rtx_REG (MODE, FIRST_CIRRUS_FP_REGNUM) \
1301 : TARGET_IWMMXT_ABI && arm_vector_mode_supported_p (MODE) \
1302 ? gen_rtx_REG (MODE, FIRST_IWMMXT_REGNUM) \
1303 : gen_rtx_REG (MODE, ARG_REGISTER (1)))
1305 /* Define how to find the value returned by a function.
1306 VALTYPE is the data type of the value (as a tree).
1307 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1308 otherwise, FUNC is 0. */
1309 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1310 arm_function_value (VALTYPE, FUNC);
1312 /* 1 if N is a possible register number for a function value.
1313 On the ARM, only r0 and f0 can return results. */
1314 /* On a Cirrus chip, mvf0 can return results. */
1315 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1316 ((REGNO) == ARG_REGISTER (1) \
1317 || (TARGET_ARM && ((REGNO) == FIRST_CIRRUS_FP_REGNUM) \
1318 && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK) \
1319 || ((REGNO) == FIRST_IWMMXT_REGNUM && TARGET_IWMMXT_ABI) \
1320 || (TARGET_ARM && ((REGNO) == FIRST_FPA_REGNUM) \
1321 && TARGET_HARD_FLOAT_ABI && TARGET_FPA))
1323 /* Amount of memory needed for an untyped call to save all possible return
1325 #define APPLY_RESULT_SIZE arm_apply_result_size()
1327 /* How large values are returned */
1328 /* A C expression which can inhibit the returning of certain function values
1329 in registers, based on the type of value. */
1330 #define RETURN_IN_MEMORY(TYPE) arm_return_in_memory (TYPE)
1332 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return
1333 values must be in memory. On the ARM, they need only do so if larger
1334 than a word, or if they contain elements offset from zero in the struct. */
1335 #define DEFAULT_PCC_STRUCT_RETURN 0
1337 /* Flags for the call/call_value rtl operations set up by function_arg. */
1338 #define CALL_NORMAL 0x00000000 /* No special processing. */
1339 #define CALL_LONG 0x00000001 /* Always call indirect. */
1340 #define CALL_SHORT 0x00000002 /* Never call indirect. */
1342 /* These bits describe the different types of function supported
1343 by the ARM backend. They are exclusive. i.e. a function cannot be both a
1344 normal function and an interworked function, for example. Knowing the
1345 type of a function is important for determining its prologue and
1347 Note value 7 is currently unassigned. Also note that the interrupt
1348 function types all have bit 2 set, so that they can be tested for easily.
1349 Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the
1350 machine_function structure is initialized (to zero) func_type will
1351 default to unknown. This will force the first use of arm_current_func_type
1352 to call arm_compute_func_type. */
1353 #define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */
1354 #define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */
1355 #define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */
1356 #define ARM_FT_ISR 4 /* An interrupt service routine. */
1357 #define ARM_FT_FIQ 5 /* A fast interrupt service routine. */
1358 #define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */
1360 #define ARM_FT_TYPE_MASK ((1 << 3) - 1)
1362 /* In addition functions can have several type modifiers,
1363 outlined by these bit masks: */
1364 #define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */
1365 #define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */
1366 #define ARM_FT_VOLATILE (1 << 4) /* Does not return. */
1367 #define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */
1369 /* Some macros to test these flags. */
1370 #define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK)
1371 #define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT)
1372 #define IS_VOLATILE(t) (t & ARM_FT_VOLATILE)
1373 #define IS_NAKED(t) (t & ARM_FT_NAKED)
1374 #define IS_NESTED(t) (t & ARM_FT_NESTED)
1377 /* Structure used to hold the function stack frame layout. Offsets are
1378 relative to the stack pointer on function entry. Positive offsets are
1379 in the direction of stack growth.
1380 Only soft_frame is used in thumb mode. */
1382 typedef struct arm_stack_offsets GTY(())
1384 int saved_args; /* ARG_POINTER_REGNUM. */
1385 int frame; /* ARM_HARD_FRAME_POINTER_REGNUM. */
1387 int soft_frame; /* FRAME_POINTER_REGNUM. */
1388 int locals_base; /* THUMB_HARD_FRAME_POINTER_REGNUM. */
1389 int outgoing_args; /* STACK_POINTER_REGNUM. */
1393 /* A C structure for machine-specific, per-function data.
1394 This is added to the cfun structure. */
1395 typedef struct machine_function GTY(())
1397 /* Additional stack adjustment in __builtin_eh_throw. */
1398 rtx eh_epilogue_sp_ofs;
1399 /* Records if LR has to be saved for far jumps. */
1401 /* Records if ARG_POINTER was ever live. */
1402 int arg_pointer_live;
1403 /* Records if the save of LR has been eliminated. */
1404 int lr_save_eliminated;
1405 /* The size of the stack frame. Only valid after reload. */
1406 arm_stack_offsets stack_offsets;
1407 /* Records the type of the current function. */
1408 unsigned long func_type;
1409 /* Record if the function has a variable argument list. */
1410 int uses_anonymous_args;
1411 /* Records if sibcalls are blocked because an argument
1412 register is needed to preserve stack alignment. */
1413 int sibcall_blocked;
1414 /* The PIC register for this function. This might be a pseudo. */
1416 /* Labels for per-function Thumb call-via stubs. One per potential calling
1417 register. We can never call via LR or PC. We can call via SP if a
1418 trampoline happens to be on the top of the stack. */
1423 /* As in the machine_function, a global set of call-via labels, for code
1424 that is in text_section. */
1425 extern GTY(()) rtx thumb_call_via_label[14];
1427 /* A C type for declaring a variable that is used as the first argument of
1428 `FUNCTION_ARG' and other related values. For some target machines, the
1429 type `int' suffices and can hold the number of bytes of argument so far. */
1432 /* This is the number of registers of arguments scanned so far. */
1434 /* This is the number of iWMMXt register arguments scanned so far. */
1438 /* One of CALL_NORMAL, CALL_LONG or CALL_SHORT. */
1443 /* Define where to put the arguments to a function.
1444 Value is zero to push the argument on the stack,
1445 or a hard register in which to store the argument.
1447 MODE is the argument's machine mode.
1448 TYPE is the data type of the argument (as a tree).
1449 This is null for libcalls where that information may
1451 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1452 the preceding args and about the function being called.
1453 NAMED is nonzero if this argument is a named parameter
1454 (otherwise it is an extra parameter matching an ellipsis).
1456 On the ARM, normally the first 16 bytes are passed in registers r0-r3; all
1457 other arguments are passed on the stack. If (NAMED == 0) (which happens
1458 only in assign_parms, since TARGET_SETUP_INCOMING_VARARGS is
1459 defined), say it is passed in the stack (function_prologue will
1460 indeed make it pass in the stack if necessary). */
1461 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1462 arm_function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1464 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
1465 (arm_pad_arg_upward (MODE, TYPE) ? upward : downward)
1467 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
1468 (arm_pad_reg_upward (MODE, TYPE, FIRST) ? upward : downward)
1470 /* For AAPCS, padding should never be below the argument. For other ABIs,
1471 * mimic the default. */
1472 #define PAD_VARARGS_DOWN \
1473 ((TARGET_AAPCS_BASED) ? 0 : BYTES_BIG_ENDIAN)
1475 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1476 for a call to a function whose data type is FNTYPE.
1477 For a library call, FNTYPE is 0.
1478 On the ARM, the offset starts at 0. */
1479 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1480 arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL))
1482 /* Update the data in CUM to advance over an argument
1483 of mode MODE and data type TYPE.
1484 (TYPE is null for libcalls where that information may not be available.) */
1485 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1487 if (arm_vector_mode_supported_p (MODE) \
1488 && (CUM).named_count > (CUM).nargs) \
1489 (CUM).iwmmxt_nregs += 1; \
1491 (CUM).nregs += ARM_NUM_REGS2 (MODE, TYPE)
1493 /* If defined, a C expression that gives the alignment boundary, in bits, of an
1494 argument with the specified mode and type. If it is not defined,
1495 `PARM_BOUNDARY' is used for all arguments. */
1496 #define FUNCTION_ARG_BOUNDARY(MODE,TYPE) \
1497 ((ARM_DOUBLEWORD_ALIGN && arm_needs_doubleword_align (MODE, TYPE)) \
1498 ? DOUBLEWORD_ALIGNMENT \
1501 /* 1 if N is a possible register number for function argument passing.
1502 On the ARM, r0-r3 are used to pass args. */
1503 #define FUNCTION_ARG_REGNO_P(REGNO) \
1504 (IN_RANGE ((REGNO), 0, 3) \
1505 || (TARGET_IWMMXT_ABI \
1506 && IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9)))
1509 /* If your target environment doesn't prefix user functions with an
1510 underscore, you may wish to re-define this to prevent any conflicts.
1511 e.g. AOF may prefix mcount with an underscore. */
1512 #ifndef ARM_MCOUNT_NAME
1513 #define ARM_MCOUNT_NAME "*mcount"
1516 /* Call the function profiler with a given profile label. The Acorn
1517 compiler puts this BEFORE the prolog but gcc puts it afterwards.
1518 On the ARM the full profile code will look like:
1527 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER
1528 will output the .text section.
1530 The ``mov ip,lr'' seems like a good idea to stick with cc convention.
1531 ``prof'' doesn't seem to mind about this!
1533 Note - this version of the code is designed to work in both ARM and
1535 #ifndef ARM_FUNCTION_PROFILER
1536 #define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \
1541 asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \
1542 IP_REGNUM, LR_REGNUM); \
1543 assemble_name (STREAM, ARM_MCOUNT_NAME); \
1544 fputc ('\n', STREAM); \
1545 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \
1546 sym = gen_rtx_SYMBOL_REF (Pmode, temp); \
1547 assemble_aligned_integer (UNITS_PER_WORD, sym); \
1551 #ifdef THUMB_FUNCTION_PROFILER
1552 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1554 ARM_FUNCTION_PROFILER (STREAM, LABELNO) \
1556 THUMB_FUNCTION_PROFILER (STREAM, LABELNO)
1558 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1559 ARM_FUNCTION_PROFILER (STREAM, LABELNO)
1562 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1563 the stack pointer does not matter. The value is tested only in
1564 functions that have frame pointers.
1565 No definition is equivalent to always zero.
1567 On the ARM, the function epilogue recovers the stack pointer from the
1569 #define EXIT_IGNORE_STACK 1
1571 #define EPILOGUE_USES(REGNO) (reload_completed && (REGNO) == LR_REGNUM)
1573 /* Determine if the epilogue should be output as RTL.
1574 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
1575 #define USE_RETURN_INSN(ISCOND) \
1576 (TARGET_ARM ? use_return_insn (ISCOND, NULL) : 0)
1578 /* Definitions for register eliminations.
1580 This is an array of structures. Each structure initializes one pair
1581 of eliminable registers. The "from" register number is given first,
1582 followed by "to". Eliminations of the same "from" register are listed
1583 in order of preference.
1585 We have two registers that can be eliminated on the ARM. First, the
1586 arg pointer register can often be eliminated in favor of the stack
1587 pointer register. Secondly, the pseudo frame pointer register can always
1588 be eliminated; it is replaced with either the stack or the real frame
1589 pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM
1590 because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */
1592 #define ELIMINABLE_REGS \
1593 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1594 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\
1595 { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1596 { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\
1597 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1598 { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1599 { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }}
1601 /* Given FROM and TO register numbers, say whether this elimination is
1602 allowed. Frame pointer elimination is automatically handled.
1604 All eliminations are permissible. Note that ARG_POINTER_REGNUM and
1605 HARD_FRAME_POINTER_REGNUM are in fact the same thing. If we need a frame
1606 pointer, we must eliminate FRAME_POINTER_REGNUM into
1607 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM or
1608 ARG_POINTER_REGNUM. */
1609 #define CAN_ELIMINATE(FROM, TO) \
1610 (((TO) == FRAME_POINTER_REGNUM && (FROM) == ARG_POINTER_REGNUM) ? 0 : \
1611 ((TO) == STACK_POINTER_REGNUM && frame_pointer_needed) ? 0 : \
1612 ((TO) == ARM_HARD_FRAME_POINTER_REGNUM && TARGET_THUMB) ? 0 : \
1613 ((TO) == THUMB_HARD_FRAME_POINTER_REGNUM && TARGET_ARM) ? 0 : \
1616 /* Define the offset between two registers, one to be eliminated, and the
1617 other its replacement, at the start of a routine. */
1618 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1620 (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \
1622 (OFFSET) = thumb_compute_initial_elimination_offset (FROM, TO)
1624 /* Special case handling of the location of arguments passed on the stack. */
1625 #define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr)
1627 /* Initialize data used by insn expanders. This is called from insn_emit,
1628 once for every function before code is generated. */
1629 #define INIT_EXPANDERS arm_init_expanders ()
1631 /* Output assembler code for a block containing the constant parts
1632 of a trampoline, leaving space for the variable parts.
1634 On the ARM, (if r8 is the static chain regnum, and remembering that
1635 referencing pc adds an offset of 8) the trampoline looks like:
1638 .word static chain value
1639 .word function's address
1640 XXX FIXME: When the trampoline returns, r8 will be clobbered. */
1641 #define ARM_TRAMPOLINE_TEMPLATE(FILE) \
1643 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
1644 STATIC_CHAIN_REGNUM, PC_REGNUM); \
1645 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
1646 PC_REGNUM, PC_REGNUM); \
1647 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1648 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1651 /* On the Thumb we always switch into ARM mode to execute the trampoline.
1652 Why - because it is easier. This code will always be branched to via
1653 a BX instruction and since the compiler magically generates the address
1654 of the function the linker has no opportunity to ensure that the
1655 bottom bit is set. Thus the processor will be in ARM mode when it
1656 reaches this code. So we duplicate the ARM trampoline code and add
1657 a switch into Thumb mode as well. */
1658 #define THUMB_TRAMPOLINE_TEMPLATE(FILE) \
1660 fprintf (FILE, "\t.code 32\n"); \
1661 fprintf (FILE, ".Ltrampoline_start:\n"); \
1662 asm_fprintf (FILE, "\tldr\t%r, [%r, #8]\n", \
1663 STATIC_CHAIN_REGNUM, PC_REGNUM); \
1664 asm_fprintf (FILE, "\tldr\t%r, [%r, #8]\n", \
1665 IP_REGNUM, PC_REGNUM); \
1666 asm_fprintf (FILE, "\torr\t%r, %r, #1\n", \
1667 IP_REGNUM, IP_REGNUM); \
1668 asm_fprintf (FILE, "\tbx\t%r\n", IP_REGNUM); \
1669 fprintf (FILE, "\t.word\t0\n"); \
1670 fprintf (FILE, "\t.word\t0\n"); \
1671 fprintf (FILE, "\t.code 16\n"); \
1674 #define TRAMPOLINE_TEMPLATE(FILE) \
1676 ARM_TRAMPOLINE_TEMPLATE (FILE) \
1678 THUMB_TRAMPOLINE_TEMPLATE (FILE)
1680 /* Length in units of the trampoline for entering a nested function. */
1681 #define TRAMPOLINE_SIZE (TARGET_ARM ? 16 : 24)
1683 /* Alignment required for a trampoline in bits. */
1684 #define TRAMPOLINE_ALIGNMENT 32
1687 /* Emit RTL insns to initialize the variable parts of a trampoline.
1688 FNADDR is an RTX for the address of the function's pure code.
1689 CXT is an RTX for the static chain value for the function. */
1690 #ifndef INITIALIZE_TRAMPOLINE
1691 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1693 emit_move_insn (gen_rtx_MEM (SImode, \
1694 plus_constant (TRAMP, \
1695 TARGET_ARM ? 8 : 16)), \
1697 emit_move_insn (gen_rtx_MEM (SImode, \
1698 plus_constant (TRAMP, \
1699 TARGET_ARM ? 12 : 20)), \
1701 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__clear_cache"), \
1702 0, VOIDmode, 2, TRAMP, Pmode, \
1703 plus_constant (TRAMP, TRAMPOLINE_SIZE), Pmode); \
1708 /* Addressing modes, and classification of registers for them. */
1709 #define HAVE_POST_INCREMENT 1
1710 #define HAVE_PRE_INCREMENT TARGET_ARM
1711 #define HAVE_POST_DECREMENT TARGET_ARM
1712 #define HAVE_PRE_DECREMENT TARGET_ARM
1713 #define HAVE_PRE_MODIFY_DISP TARGET_ARM
1714 #define HAVE_POST_MODIFY_DISP TARGET_ARM
1715 #define HAVE_PRE_MODIFY_REG TARGET_ARM
1716 #define HAVE_POST_MODIFY_REG TARGET_ARM
1718 /* Macros to check register numbers against specific register classes. */
1720 /* These assume that REGNO is a hard or pseudo reg number.
1721 They give nonzero only if REGNO is a hard reg of the suitable class
1722 or a pseudo reg currently allocated to a suitable hard reg.
1723 Since they use reg_renumber, they are safe only once reg_renumber
1724 has been allocated, which happens in local-alloc.c. */
1725 #define TEST_REGNO(R, TEST, VALUE) \
1726 ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE))
1728 /* On the ARM, don't allow the pc to be used. */
1729 #define ARM_REGNO_OK_FOR_BASE_P(REGNO) \
1730 (TEST_REGNO (REGNO, <, PC_REGNUM) \
1731 || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \
1732 || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM))
1734 #define THUMB_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1735 (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \
1736 || (GET_MODE_SIZE (MODE) >= 4 \
1737 && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)))
1739 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1741 ? THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \
1742 : ARM_REGNO_OK_FOR_BASE_P (REGNO))
1744 /* Nonzero if X can be the base register in a reg+reg addressing mode.
1745 For Thumb, we can not use SP + reg, so reject SP. */
1746 #define REGNO_MODE_OK_FOR_REG_BASE_P(X, MODE) \
1747 REGNO_OK_FOR_INDEX_P (X)
1749 /* For ARM code, we don't care about the mode, but for Thumb, the index
1750 must be suitable for use in a QImode load. */
1751 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1752 REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode)
1754 /* Maximum number of registers that can appear in a valid memory address.
1755 Shifts in addresses can't be by a register. */
1756 #define MAX_REGS_PER_ADDRESS 2
1758 /* Recognize any constant value that is a valid address. */
1759 /* XXX We can address any constant, eventually... */
1761 #ifdef AOF_ASSEMBLER
1763 #define CONSTANT_ADDRESS_P(X) \
1764 (GET_CODE (X) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (X))
1768 #define CONSTANT_ADDRESS_P(X) \
1769 (GET_CODE (X) == SYMBOL_REF \
1770 && (CONSTANT_POOL_ADDRESS_P (X) \
1771 || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X))))
1773 #endif /* AOF_ASSEMBLER */
1775 /* Nonzero if the constant value X is a legitimate general operand.
1776 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1778 On the ARM, allow any integer (invalid ones are removed later by insn
1779 patterns), nice doubles and symbol_refs which refer to the function's
1782 When generating pic allow anything. */
1783 #define ARM_LEGITIMATE_CONSTANT_P(X) (flag_pic || ! label_mentioned_p (X))
1785 #define THUMB_LEGITIMATE_CONSTANT_P(X) \
1786 ( GET_CODE (X) == CONST_INT \
1787 || GET_CODE (X) == CONST_DOUBLE \
1788 || CONSTANT_ADDRESS_P (X) \
1791 #define LEGITIMATE_CONSTANT_P(X) \
1792 (!arm_tls_referenced_p (X) \
1793 && (TARGET_ARM ? ARM_LEGITIMATE_CONSTANT_P (X) \
1794 : THUMB_LEGITIMATE_CONSTANT_P (X)))
1796 /* Special characters prefixed to function names
1797 in order to encode attribute like information.
1798 Note, '@' and '*' have already been taken. */
1799 #define SHORT_CALL_FLAG_CHAR '^'
1800 #define LONG_CALL_FLAG_CHAR '#'
1802 #define ENCODED_SHORT_CALL_ATTR_P(SYMBOL_NAME) \
1803 (*(SYMBOL_NAME) == SHORT_CALL_FLAG_CHAR)
1805 #define ENCODED_LONG_CALL_ATTR_P(SYMBOL_NAME) \
1806 (*(SYMBOL_NAME) == LONG_CALL_FLAG_CHAR)
1808 #ifndef SUBTARGET_NAME_ENCODING_LENGTHS
1809 #define SUBTARGET_NAME_ENCODING_LENGTHS
1812 /* This is a C fragment for the inside of a switch statement.
1813 Each case label should return the number of characters to
1814 be stripped from the start of a function's name, if that
1815 name starts with the indicated character. */
1816 #define ARM_NAME_ENCODING_LENGTHS \
1817 case SHORT_CALL_FLAG_CHAR: return 1; \
1818 case LONG_CALL_FLAG_CHAR: return 1; \
1819 case '*': return 1; \
1820 SUBTARGET_NAME_ENCODING_LENGTHS
1822 /* This is how to output a reference to a user-level label named NAME.
1823 `assemble_name' uses this. */
1824 #undef ASM_OUTPUT_LABELREF
1825 #define ASM_OUTPUT_LABELREF(FILE, NAME) \
1826 arm_asm_output_labelref (FILE, NAME)
1828 /* The EABI specifies that constructors should go in .init_array.
1829 Other targets use .ctors for compatibility. */
1830 #ifndef ARM_EABI_CTORS_SECTION_OP
1831 #define ARM_EABI_CTORS_SECTION_OP \
1832 "\t.section\t.init_array,\"aw\",%init_array"
1834 #ifndef ARM_EABI_DTORS_SECTION_OP
1835 #define ARM_EABI_DTORS_SECTION_OP \
1836 "\t.section\t.fini_array,\"aw\",%fini_array"
1838 #define ARM_CTORS_SECTION_OP \
1839 "\t.section\t.ctors,\"aw\",%progbits"
1840 #define ARM_DTORS_SECTION_OP \
1841 "\t.section\t.dtors,\"aw\",%progbits"
1843 /* Define CTORS_SECTION_ASM_OP. */
1844 #undef CTORS_SECTION_ASM_OP
1845 #undef DTORS_SECTION_ASM_OP
1847 # define CTORS_SECTION_ASM_OP \
1848 (TARGET_AAPCS_BASED ? ARM_EABI_CTORS_SECTION_OP : ARM_CTORS_SECTION_OP)
1849 # define DTORS_SECTION_ASM_OP \
1850 (TARGET_AAPCS_BASED ? ARM_EABI_DTORS_SECTION_OP : ARM_DTORS_SECTION_OP)
1851 #else /* !defined (IN_LIBGCC2) */
1852 /* In libgcc, CTORS_SECTION_ASM_OP must be a compile-time constant,
1853 so we cannot use the definition above. */
1854 # ifdef __ARM_EABI__
1855 /* The .ctors section is not part of the EABI, so we do not define
1856 CTORS_SECTION_ASM_OP when in libgcc; that prevents crtstuff
1857 from trying to use it. We do define it when doing normal
1858 compilation, as .init_array can be used instead of .ctors. */
1859 /* There is no need to emit begin or end markers when using
1860 init_array; the dynamic linker will compute the size of the
1861 array itself based on special symbols created by the static
1862 linker. However, we do need to arrange to set up
1863 exception-handling here. */
1864 # define CTOR_LIST_BEGIN asm (ARM_EABI_CTORS_SECTION_OP)
1865 # define CTOR_LIST_END /* empty */
1866 # define DTOR_LIST_BEGIN asm (ARM_EABI_DTORS_SECTION_OP)
1867 # define DTOR_LIST_END /* empty */
1868 # else /* !defined (__ARM_EABI__) */
1870 # define CTORS_SECTION_ASM_OP ARM_CTORS_SECTION_OP
1871 # define DTORS_SECTION_ASM_OP ARM_DTORS_SECTION_OP
1873 # endif /* !defined (__ARM_EABI__) */
1874 #endif /* !defined (IN_LIBCC2) */
1876 /* True if the operating system can merge entities with vague linkage
1877 (e.g., symbols in COMDAT group) during dynamic linking. */
1878 #ifndef TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P
1879 #define TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P true
1882 /* Set the short-call flag for any function compiled in the current
1883 compilation unit. We skip this for functions with the section
1884 attribute when long-calls are in effect as this tells the compiler
1885 that the section might be placed a long way from the caller.
1886 See arm_is_longcall_p() for more information. */
1887 #define ARM_DECLARE_FUNCTION_SIZE(STREAM, NAME, DECL) \
1888 if (!TARGET_LONG_CALLS || ! DECL_SECTION_NAME (DECL)) \
1889 arm_encode_call_attribute (DECL, SHORT_CALL_FLAG_CHAR)
1891 #define ARM_OUTPUT_FN_UNWIND(F, PROLOGUE) arm_output_fn_unwind (F, PROLOGUE)
1893 #ifdef TARGET_UNWIND_INFO
1894 #define ARM_EABI_UNWIND_TABLES \
1895 ((!USING_SJLJ_EXCEPTIONS && flag_exceptions) || flag_unwind_tables)
1897 #define ARM_EABI_UNWIND_TABLES 0
1900 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1901 and check its validity for a certain class.
1902 We have two alternate definitions for each of them.
1903 The usual definition accepts all pseudo regs; the other rejects
1904 them unless they have been allocated suitable hard regs.
1905 The symbol REG_OK_STRICT causes the latter definition to be used. */
1906 #ifndef REG_OK_STRICT
1908 #define ARM_REG_OK_FOR_BASE_P(X) \
1909 (REGNO (X) <= LAST_ARM_REGNUM \
1910 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
1911 || REGNO (X) == FRAME_POINTER_REGNUM \
1912 || REGNO (X) == ARG_POINTER_REGNUM)
1914 #define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \
1915 (REGNO (X) <= LAST_LO_REGNUM \
1916 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
1917 || (GET_MODE_SIZE (MODE) >= 4 \
1918 && (REGNO (X) == STACK_POINTER_REGNUM \
1919 || (X) == hard_frame_pointer_rtx \
1920 || (X) == arg_pointer_rtx)))
1922 #define REG_STRICT_P 0
1924 #else /* REG_OK_STRICT */
1926 #define ARM_REG_OK_FOR_BASE_P(X) \
1927 ARM_REGNO_OK_FOR_BASE_P (REGNO (X))
1929 #define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \
1930 THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE)
1932 #define REG_STRICT_P 1
1934 #endif /* REG_OK_STRICT */
1936 /* Now define some helpers in terms of the above. */
1938 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
1940 ? THUMB_REG_MODE_OK_FOR_BASE_P (X, MODE) \
1941 : ARM_REG_OK_FOR_BASE_P (X))
1943 #define ARM_REG_OK_FOR_INDEX_P(X) ARM_REG_OK_FOR_BASE_P (X)
1945 /* For Thumb, a valid index register is anything that can be used in
1946 a byte load instruction. */
1947 #define THUMB_REG_OK_FOR_INDEX_P(X) THUMB_REG_MODE_OK_FOR_BASE_P (X, QImode)
1949 /* Nonzero if X is a hard reg that can be used as an index
1950 or if it is a pseudo reg. On the Thumb, the stack pointer
1952 #define REG_OK_FOR_INDEX_P(X) \
1954 ? THUMB_REG_OK_FOR_INDEX_P (X) \
1955 : ARM_REG_OK_FOR_INDEX_P (X))
1957 /* Nonzero if X can be the base register in a reg+reg addressing mode.
1958 For Thumb, we can not use SP + reg, so reject SP. */
1959 #define REG_MODE_OK_FOR_REG_BASE_P(X, MODE) \
1960 REG_OK_FOR_INDEX_P (X)
1962 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1963 that is a valid memory address for an instruction.
1964 The MODE argument is the machine mode for the MEM expression
1965 that wants to use this address. */
1967 #define ARM_BASE_REGISTER_RTX_P(X) \
1968 (GET_CODE (X) == REG && ARM_REG_OK_FOR_BASE_P (X))
1970 #define ARM_INDEX_REGISTER_RTX_P(X) \
1971 (GET_CODE (X) == REG && ARM_REG_OK_FOR_INDEX_P (X))
1973 #define ARM_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
1975 if (arm_legitimate_address_p (MODE, X, SET, REG_STRICT_P)) \
1979 #define THUMB_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
1981 if (thumb_legitimate_address_p (MODE, X, REG_STRICT_P)) \
1985 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \
1987 ARM_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN) \
1988 else /* if (TARGET_THUMB) */ \
1989 THUMB_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN)
1992 /* Try machine-dependent ways of modifying an illegitimate address
1993 to be legitimate. If we find one, return the new, valid address. */
1994 #define ARM_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1996 X = arm_legitimize_address (X, OLDX, MODE); \
1999 #define THUMB_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2001 X = thumb_legitimize_address (X, OLDX, MODE); \
2004 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2007 ARM_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
2009 THUMB_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
2011 if (memory_address_p (MODE, X)) \
2015 /* Go to LABEL if ADDR (a legitimate address expression)
2016 has an effect that depends on the machine mode it is used for. */
2017 #define ARM_GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2019 if ( GET_CODE (ADDR) == PRE_DEC || GET_CODE (ADDR) == POST_DEC \
2020 || GET_CODE (ADDR) == PRE_INC || GET_CODE (ADDR) == POST_INC) \
2024 /* Nothing helpful to do for the Thumb */
2025 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2027 ARM_GO_IF_MODE_DEPENDENT_ADDRESS (ADDR, LABEL)
2030 /* Specify the machine mode that this machine uses
2031 for the index in the tablejump instruction. */
2032 #define CASE_VECTOR_MODE Pmode
2034 /* signed 'char' is most compatible, but RISC OS wants it unsigned.
2035 unsigned is probably best, but may break some code. */
2036 #ifndef DEFAULT_SIGNED_CHAR
2037 #define DEFAULT_SIGNED_CHAR 0
2040 /* Max number of bytes we can move from memory to memory
2041 in one reasonably fast instruction. */
2045 #define MOVE_RATIO (arm_tune_xscale ? 4 : 2)
2047 /* Define if operations between registers always perform the operation
2048 on the full register even if a narrower mode is specified. */
2049 #define WORD_REGISTER_OPERATIONS
2051 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2052 will either zero-extend or sign-extend. The value of this macro should
2053 be the code that says which one of the two operations is implicitly
2054 done, UNKNOWN if none. */
2055 #define LOAD_EXTEND_OP(MODE) \
2056 (TARGET_THUMB ? ZERO_EXTEND : \
2057 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \
2058 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : UNKNOWN)))
2060 /* Nonzero if access to memory by bytes is slow and undesirable. */
2061 #define SLOW_BYTE_ACCESS 0
2063 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1
2065 /* Immediate shift counts are truncated by the output routines (or was it
2066 the assembler?). Shift counts in a register are truncated by ARM. Note
2067 that the native compiler puts too large (> 32) immediate shift counts
2068 into a register and shifts by the register, letting the ARM decide what
2069 to do instead of doing that itself. */
2070 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
2071 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
2072 On the arm, Y in a register is used modulo 256 for the shift. Only for
2073 rotates is modulo 32 used. */
2074 /* #define SHIFT_COUNT_TRUNCATED 1 */
2076 /* All integers have the same format so truncation is easy. */
2077 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2079 /* Calling from registers is a massive pain. */
2080 #define NO_FUNCTION_CSE 1
2082 /* The machine modes of pointers and functions */
2083 #define Pmode SImode
2084 #define FUNCTION_MODE Pmode
2086 #define ARM_FRAME_RTX(X) \
2087 ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
2088 || (X) == arg_pointer_rtx)
2090 /* Moves to and from memory are quite expensive */
2091 #define MEMORY_MOVE_COST(M, CLASS, IN) \
2092 (TARGET_ARM ? 10 : \
2093 ((GET_MODE_SIZE (M) < 4 ? 8 : 2 * GET_MODE_SIZE (M)) \
2094 * (CLASS == LO_REGS ? 1 : 2)))
2096 /* Try to generate sequences that don't involve branches, we can then use
2097 conditional instructions */
2098 #define BRANCH_COST \
2099 (TARGET_ARM ? 4 : (optimize > 1 ? 1 : 0))
2101 /* Position Independent Code. */
2102 /* We decide which register to use based on the compilation options and
2103 the assembler in use; this is more general than the APCS restriction of
2104 using sb (r9) all the time. */
2105 extern unsigned arm_pic_register;
2107 /* The register number of the register used to address a table of static
2108 data addresses in memory. */
2109 #define PIC_OFFSET_TABLE_REGNUM arm_pic_register
2111 /* We can't directly access anything that contains a symbol,
2112 nor can we indirect via the constant pool. One exception is
2113 UNSPEC_TLS, which is always PIC. */
2114 #define LEGITIMATE_PIC_OPERAND_P(X) \
2115 (!(symbol_mentioned_p (X) \
2116 || label_mentioned_p (X) \
2117 || (GET_CODE (X) == SYMBOL_REF \
2118 && CONSTANT_POOL_ADDRESS_P (X) \
2119 && (symbol_mentioned_p (get_pool_constant (X)) \
2120 || label_mentioned_p (get_pool_constant (X))))) \
2121 || tls_mentioned_p (X))
2123 /* We need to know when we are making a constant pool; this determines
2124 whether data needs to be in the GOT or can be referenced via a GOT
2126 extern int making_const_table;
2128 /* Handle pragmas for compatibility with Intel's compilers. */
2129 #define REGISTER_TARGET_PRAGMAS() do { \
2130 c_register_pragma (0, "long_calls", arm_pr_long_calls); \
2131 c_register_pragma (0, "no_long_calls", arm_pr_no_long_calls); \
2132 c_register_pragma (0, "long_calls_off", arm_pr_long_calls_off); \
2135 /* Condition code information. */
2136 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2137 return the mode to be used for the comparison. */
2139 #define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y)
2141 #define REVERSIBLE_CC_MODE(MODE) 1
2143 #define REVERSE_CONDITION(CODE,MODE) \
2144 (((MODE) == CCFPmode || (MODE) == CCFPEmode) \
2145 ? reverse_condition_maybe_unordered (code) \
2146 : reverse_condition (code))
2148 #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \
2151 if (GET_CODE (OP1) == CONST_INT \
2152 && ! (const_ok_for_arm (INTVAL (OP1)) \
2153 || (const_ok_for_arm (- INTVAL (OP1))))) \
2155 rtx const_op = OP1; \
2156 CODE = arm_canonicalize_comparison ((CODE), GET_MODE (OP0), \
2163 /* The arm5 clz instruction returns 32. */
2164 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
2167 #define ASM_APP_OFF (TARGET_THUMB ? "\t.code\t16\n" : "")
2169 /* Output a push or a pop instruction (only used when profiling). */
2170 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \
2174 asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", \
2175 STACK_POINTER_REGNUM, REGNO); \
2177 asm_fprintf (STREAM, "\tpush {%r}\n", REGNO); \
2181 #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \
2185 asm_fprintf (STREAM, "\tldmfd\t%r!,{%r}\n", \
2186 STACK_POINTER_REGNUM, REGNO); \
2188 asm_fprintf (STREAM, "\tpop {%r}\n", REGNO); \
2191 /* This is how to output a label which precedes a jumptable. Since
2192 Thumb instructions are 2 bytes, we may need explicit alignment here. */
2193 #undef ASM_OUTPUT_CASE_LABEL
2194 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, JUMPTABLE) \
2198 ASM_OUTPUT_ALIGN (FILE, 2); \
2199 (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \
2203 #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \
2208 if (is_called_in_ARM_mode (DECL) \
2209 || current_function_is_thunk) \
2210 fprintf (STREAM, "\t.code 32\n") ; \
2212 fprintf (STREAM, "\t.code 16\n\t.thumb_func\n") ; \
2214 if (TARGET_POKE_FUNCTION_NAME) \
2215 arm_poke_function_name (STREAM, (char *) NAME); \
2219 /* For aliases of functions we use .thumb_set instead. */
2220 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \
2223 const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \
2224 const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \
2226 if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \
2228 fprintf (FILE, "\t.thumb_set "); \
2229 assemble_name (FILE, LABEL1); \
2230 fprintf (FILE, ","); \
2231 assemble_name (FILE, LABEL2); \
2232 fprintf (FILE, "\n"); \
2235 ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \
2239 #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN
2240 /* To support -falign-* switches we need to use .p2align so
2241 that alignment directives in code sections will be padded
2242 with no-op instructions, rather than zeroes. */
2243 #define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE, LOG, MAX_SKIP) \
2246 if ((MAX_SKIP) == 0) \
2247 fprintf ((FILE), "\t.p2align %d\n", (int) (LOG)); \
2249 fprintf ((FILE), "\t.p2align %d,,%d\n", \
2250 (int) (LOG), (int) (MAX_SKIP)); \
2254 /* Only perform branch elimination (by making instructions conditional) if
2255 we're optimizing. Otherwise it's of no use anyway. */
2256 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2257 if (TARGET_ARM && optimize) \
2258 arm_final_prescan_insn (INSN); \
2259 else if (TARGET_THUMB) \
2260 thumb_final_prescan_insn (INSN)
2262 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2263 (CODE == '@' || CODE == '|' \
2264 || (TARGET_ARM && (CODE == '?')) \
2265 || (TARGET_THUMB && (CODE == '_')))
2267 /* Output an operand of an instruction. */
2268 #define PRINT_OPERAND(STREAM, X, CODE) \
2269 arm_print_operand (STREAM, X, CODE)
2271 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \
2272 (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \
2273 : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\
2274 ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \
2275 ? ((~ (unsigned HOST_WIDE_INT) 0) \
2276 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \
2279 /* Output the address of an operand. */
2280 #define ARM_PRINT_OPERAND_ADDRESS(STREAM, X) \
2282 int is_minus = GET_CODE (X) == MINUS; \
2284 if (GET_CODE (X) == REG) \
2285 asm_fprintf (STREAM, "[%r, #0]", REGNO (X)); \
2286 else if (GET_CODE (X) == PLUS || is_minus) \
2288 rtx base = XEXP (X, 0); \
2289 rtx index = XEXP (X, 1); \
2290 HOST_WIDE_INT offset = 0; \
2291 if (GET_CODE (base) != REG) \
2293 /* Ensure that BASE is a register. */ \
2294 /* (one of them must be). */ \
2299 switch (GET_CODE (index)) \
2302 offset = INTVAL (index); \
2305 asm_fprintf (STREAM, "[%r, #%wd]", \
2306 REGNO (base), offset); \
2310 asm_fprintf (STREAM, "[%r, %s%r]", \
2311 REGNO (base), is_minus ? "-" : "", \
2321 asm_fprintf (STREAM, "[%r, %s%r", \
2322 REGNO (base), is_minus ? "-" : "", \
2323 REGNO (XEXP (index, 0))); \
2324 arm_print_operand (STREAM, index, 'S'); \
2325 fputs ("]", STREAM); \
2330 gcc_unreachable (); \
2333 else if (GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC \
2334 || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC) \
2336 extern enum machine_mode output_memory_reference_mode; \
2338 gcc_assert (GET_CODE (XEXP (X, 0)) == REG); \
2340 if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \
2341 asm_fprintf (STREAM, "[%r, #%s%d]!", \
2342 REGNO (XEXP (X, 0)), \
2343 GET_CODE (X) == PRE_DEC ? "-" : "", \
2344 GET_MODE_SIZE (output_memory_reference_mode)); \
2346 asm_fprintf (STREAM, "[%r], #%s%d", \
2347 REGNO (XEXP (X, 0)), \
2348 GET_CODE (X) == POST_DEC ? "-" : "", \
2349 GET_MODE_SIZE (output_memory_reference_mode)); \
2351 else if (GET_CODE (X) == PRE_MODIFY) \
2353 asm_fprintf (STREAM, "[%r, ", REGNO (XEXP (X, 0))); \
2354 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \
2355 asm_fprintf (STREAM, "#%wd]!", \
2356 INTVAL (XEXP (XEXP (X, 1), 1))); \
2358 asm_fprintf (STREAM, "%r]!", \
2359 REGNO (XEXP (XEXP (X, 1), 1))); \
2361 else if (GET_CODE (X) == POST_MODIFY) \
2363 asm_fprintf (STREAM, "[%r], ", REGNO (XEXP (X, 0))); \
2364 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \
2365 asm_fprintf (STREAM, "#%wd", \
2366 INTVAL (XEXP (XEXP (X, 1), 1))); \
2368 asm_fprintf (STREAM, "%r", \
2369 REGNO (XEXP (XEXP (X, 1), 1))); \
2371 else output_addr_const (STREAM, X); \
2374 #define THUMB_PRINT_OPERAND_ADDRESS(STREAM, X) \
2376 if (GET_CODE (X) == REG) \
2377 asm_fprintf (STREAM, "[%r]", REGNO (X)); \
2378 else if (GET_CODE (X) == POST_INC) \
2379 asm_fprintf (STREAM, "%r!", REGNO (XEXP (X, 0))); \
2380 else if (GET_CODE (X) == PLUS) \
2382 gcc_assert (GET_CODE (XEXP (X, 0)) == REG); \
2383 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2384 asm_fprintf (STREAM, "[%r, #%wd]", \
2385 REGNO (XEXP (X, 0)), \
2386 INTVAL (XEXP (X, 1))); \
2388 asm_fprintf (STREAM, "[%r, %r]", \
2389 REGNO (XEXP (X, 0)), \
2390 REGNO (XEXP (X, 1))); \
2393 output_addr_const (STREAM, X); \
2396 #define PRINT_OPERAND_ADDRESS(STREAM, X) \
2398 ARM_PRINT_OPERAND_ADDRESS (STREAM, X) \
2400 THUMB_PRINT_OPERAND_ADDRESS (STREAM, X)
2402 #define OUTPUT_ADDR_CONST_EXTRA(file, x, fail) \
2403 if (arm_output_addr_const_extra (file, x) == FALSE) \
2406 /* A C expression whose value is RTL representing the value of the return
2407 address for the frame COUNT steps up from the current frame. */
2409 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2410 arm_return_addr (COUNT, FRAME)
2412 /* Mask of the bits in the PC that contain the real return address
2413 when running in 26-bit mode. */
2414 #define RETURN_ADDR_MASK26 (0x03fffffc)
2416 /* Pick up the return address upon entry to a procedure. Used for
2417 dwarf2 unwind information. This also enables the table driven
2419 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM)
2420 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM)
2422 /* Used to mask out junk bits from the return address, such as
2423 processor state, interrupt status, condition codes and the like. */
2424 #define MASK_RETURN_ADDR \
2425 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \
2426 in 26 bit mode, the condition codes must be masked out of the \
2427 return address. This does not apply to ARM6 and later processors \
2428 when running in 32 bit mode. */ \
2429 ((arm_arch4 || TARGET_THUMB) \
2430 ? (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \
2431 : arm_gen_return_addr_mask ())
2441 ARM_BUILTIN_WAVG2BR,
2442 ARM_BUILTIN_WAVG2HR,
2469 ARM_BUILTIN_TMOVMSKB,
2470 ARM_BUILTIN_TMOVMSKH,
2471 ARM_BUILTIN_TMOVMSKW,
2480 ARM_BUILTIN_WPACKHSS,
2481 ARM_BUILTIN_WPACKWSS,
2482 ARM_BUILTIN_WPACKDSS,
2483 ARM_BUILTIN_WPACKHUS,
2484 ARM_BUILTIN_WPACKWUS,
2485 ARM_BUILTIN_WPACKDUS,
2490 ARM_BUILTIN_WADDSSB,
2491 ARM_BUILTIN_WADDSSH,
2492 ARM_BUILTIN_WADDSSW,
2493 ARM_BUILTIN_WADDUSB,
2494 ARM_BUILTIN_WADDUSH,
2495 ARM_BUILTIN_WADDUSW,
2499 ARM_BUILTIN_WSUBSSB,
2500 ARM_BUILTIN_WSUBSSH,
2501 ARM_BUILTIN_WSUBSSW,
2502 ARM_BUILTIN_WSUBUSB,
2503 ARM_BUILTIN_WSUBUSH,
2504 ARM_BUILTIN_WSUBUSW,
2511 ARM_BUILTIN_WCMPEQB,
2512 ARM_BUILTIN_WCMPEQH,
2513 ARM_BUILTIN_WCMPEQW,
2514 ARM_BUILTIN_WCMPGTUB,
2515 ARM_BUILTIN_WCMPGTUH,
2516 ARM_BUILTIN_WCMPGTUW,
2517 ARM_BUILTIN_WCMPGTSB,
2518 ARM_BUILTIN_WCMPGTSH,
2519 ARM_BUILTIN_WCMPGTSW,
2521 ARM_BUILTIN_TEXTRMSB,
2522 ARM_BUILTIN_TEXTRMSH,
2523 ARM_BUILTIN_TEXTRMSW,
2524 ARM_BUILTIN_TEXTRMUB,
2525 ARM_BUILTIN_TEXTRMUH,
2526 ARM_BUILTIN_TEXTRMUW,
2576 ARM_BUILTIN_WUNPCKIHB,
2577 ARM_BUILTIN_WUNPCKIHH,
2578 ARM_BUILTIN_WUNPCKIHW,
2579 ARM_BUILTIN_WUNPCKILB,
2580 ARM_BUILTIN_WUNPCKILH,
2581 ARM_BUILTIN_WUNPCKILW,
2583 ARM_BUILTIN_WUNPCKEHSB,
2584 ARM_BUILTIN_WUNPCKEHSH,
2585 ARM_BUILTIN_WUNPCKEHSW,
2586 ARM_BUILTIN_WUNPCKEHUB,
2587 ARM_BUILTIN_WUNPCKEHUH,
2588 ARM_BUILTIN_WUNPCKEHUW,
2589 ARM_BUILTIN_WUNPCKELSB,
2590 ARM_BUILTIN_WUNPCKELSH,
2591 ARM_BUILTIN_WUNPCKELSW,
2592 ARM_BUILTIN_WUNPCKELUB,
2593 ARM_BUILTIN_WUNPCKELUH,
2594 ARM_BUILTIN_WUNPCKELUW,
2596 ARM_BUILTIN_THREAD_POINTER,
2600 #endif /* ! GCC_ARM_H */
projects / FreeBSD / releng / 10.0.git / blob