1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by A. Lichnewsky (lich@inria.inria.fr).
5 Changed by Michael Meissner (meissner@osf.org).
6 64 bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
7 Brendan Eich (brendan@microunity.com).
9 This file is part of GCC.
11 GCC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GCC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GCC; see the file COPYING. If not, write to
23 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
24 Boston, MA 02110-1301, USA. */
27 /* MIPS external variables defined in mips.c. */
29 /* Which processor to schedule for. Since there is no difference between
30 a R2000 and R3000 in terms of the scheduler, we collapse them into
31 just an R3000. The elements of the enumeration must match exactly
32 the cpu attribute in the mips.md machine description. */
67 /* Costs of various operations on the different architectures. */
69 struct mips_rtx_cost_data
71 unsigned short fp_add;
72 unsigned short fp_mult_sf;
73 unsigned short fp_mult_df;
74 unsigned short fp_div_sf;
75 unsigned short fp_div_df;
76 unsigned short int_mult_si;
77 unsigned short int_mult_di;
78 unsigned short int_div_si;
79 unsigned short int_div_di;
80 unsigned short branch_cost;
81 unsigned short memory_latency;
84 /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
85 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended
86 to work on a 64 bit machine. */
94 /* Information about one recognized processor. Defined here for the
95 benefit of TARGET_CPU_CPP_BUILTINS. */
96 struct mips_cpu_info {
97 /* The 'canonical' name of the processor as far as GCC is concerned.
98 It's typically a manufacturer's prefix followed by a numerical
99 designation. It should be lower case. */
102 /* The internal processor number that most closely matches this
103 entry. Several processors can have the same value, if there's no
104 difference between them from GCC's point of view. */
105 enum processor_type cpu;
107 /* The ISA level that the processor implements. */
111 #ifndef USED_FOR_TARGET
112 extern char mips_print_operand_punct[256]; /* print_operand punctuation chars */
113 extern const char *current_function_file; /* filename current function is in */
114 extern int num_source_filenames; /* current .file # */
115 extern int mips_section_threshold; /* # bytes of data/sdata cutoff */
116 extern int sym_lineno; /* sgi next label # for each stmt */
117 extern int set_noreorder; /* # of nested .set noreorder's */
118 extern int set_nomacro; /* # of nested .set nomacro's */
119 extern int set_noat; /* # of nested .set noat's */
120 extern int set_volatile; /* # of nested .set volatile's */
121 extern int mips_branch_likely; /* emit 'l' after br (branch likely) */
122 extern int mips_dbx_regno[]; /* Map register # to debug register # */
123 extern bool mips_split_p[];
124 extern GTY(()) rtx cmp_operands[2];
125 extern enum processor_type mips_arch; /* which cpu to codegen for */
126 extern enum processor_type mips_tune; /* which cpu to schedule for */
127 extern int mips_isa; /* architectural level */
128 extern int mips_abi; /* which ABI to use */
129 extern int mips16_hard_float; /* mips16 without -msoft-float */
130 extern const struct mips_cpu_info mips_cpu_info_table[];
131 extern const struct mips_cpu_info *mips_arch_info;
132 extern const struct mips_cpu_info *mips_tune_info;
133 extern const struct mips_rtx_cost_data *mips_cost;
136 /* Macros to silence warnings about numbers being signed in traditional
137 C and unsigned in ISO C when compiled on 32-bit hosts. */
139 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
140 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
141 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
144 /* Run-time compilation parameters selecting different hardware subsets. */
146 /* True if the call patterns should be split into a jalr followed by
147 an instruction to restore $gp. This is only ever true for SVR4 PIC,
148 in which $gp is call-clobbered. It is only safe to split the load
149 from the call when every use of $gp is explicit. */
151 #define TARGET_SPLIT_CALLS \
152 (TARGET_EXPLICIT_RELOCS && TARGET_ABICALLS && !TARGET_NEWABI)
154 /* True if we're generating a form of -mabicalls in which we can use
155 operators like %hi and %lo to refer to locally-binding symbols.
156 We can only do this for -mno-shared, and only then if we can use
157 relocation operations instead of assembly macros. It isn't really
158 worth using absolute sequences for 64-bit symbols because GOT
159 accesses are so much shorter. */
161 #define TARGET_ABSOLUTE_ABICALLS \
164 && TARGET_EXPLICIT_RELOCS \
165 && !ABI_HAS_64BIT_SYMBOLS)
167 /* True if we can optimize sibling calls. For simplicity, we only
168 handle cases in which call_insn_operand will reject invalid
169 sibcall addresses. There are two cases in which this isn't true:
171 - TARGET_MIPS16. call_insn_operand accepts constant addresses
172 but there is no direct jump instruction. It isn't worth
173 using sibling calls in this case anyway; they would usually
174 be longer than normal calls.
176 - TARGET_ABICALLS && !TARGET_EXPLICIT_RELOCS. call_insn_operand
177 accepts global constants, but "jr $25" is the only allowed
180 #define TARGET_SIBCALLS \
181 (!TARGET_MIPS16 && (!TARGET_ABICALLS || TARGET_EXPLICIT_RELOCS))
183 /* True if .gpword or .gpdword should be used for switch tables.
185 Although GAS does understand .gpdword, the SGI linker mishandles
186 the relocations GAS generates (R_MIPS_GPREL32 followed by R_MIPS_64).
187 We therefore disable GP-relative switch tables for n64 on IRIX targets. */
188 #define TARGET_GPWORD (TARGET_ABICALLS && !(mips_abi == ABI_64 && TARGET_IRIX))
190 /* Generate mips16 code */
191 #define TARGET_MIPS16 ((target_flags & MASK_MIPS16) != 0)
192 /* Generate mips16e code. Default 16bit ASE for mips32/mips32r2/mips64 */
193 #define GENERATE_MIPS16E (TARGET_MIPS16 && mips_isa >= 32)
195 /* Generic ISA defines. */
196 #define ISA_MIPS1 (mips_isa == 1)
197 #define ISA_MIPS2 (mips_isa == 2)
198 #define ISA_MIPS3 (mips_isa == 3)
199 #define ISA_MIPS4 (mips_isa == 4)
200 #define ISA_MIPS32 (mips_isa == 32)
201 #define ISA_MIPS32R2 (mips_isa == 33)
202 #define ISA_MIPS64 (mips_isa == 64)
203 #define ISA_MIPS64R2 (mips_isa == 65)
205 /* Architecture target defines. */
206 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
207 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
208 #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
209 #define TARGET_MIPS4130 (mips_arch == PROCESSOR_R4130)
210 #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
211 #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
212 #define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000)
213 #define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000)
214 #define TARGET_SB1 (mips_arch == PROCESSOR_SB1 \
215 || mips_arch == PROCESSOR_SB1A)
216 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
217 #define TARGET_OCTEON (mips_arch == PROCESSOR_OCTEON)
219 /* Scheduling target defines. */
220 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
221 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
222 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
223 #define TUNE_MIPS4120 (mips_tune == PROCESSOR_R4120)
224 #define TUNE_MIPS4130 (mips_tune == PROCESSOR_R4130)
225 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
226 #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
227 #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
228 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
229 #define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000)
230 #define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000)
231 #define TUNE_SB1 (mips_tune == PROCESSOR_SB1 \
232 || mips_tune == PROCESSOR_SB1A)
233 #define TUNE_OCTEON (mips_tune == PROCESSOR_OCTEON)
235 /* True if the pre-reload scheduler should try to create chains of
236 multiply-add or multiply-subtract instructions. For example,
244 t1 will have a higher priority than t2 and t3 will have a higher
245 priority than t4. However, before reload, there is no dependence
246 between t1 and t3, and they can often have similar priorities.
247 The scheduler will then tend to prefer:
254 which stops us from making full use of macc/madd-style instructions.
255 This sort of situation occurs frequently in Fourier transforms and
258 To counter this, the TUNE_MACC_CHAINS code will reorder the ready
259 queue so that chained multiply-add and multiply-subtract instructions
260 appear ahead of any other instruction that is likely to clobber lo.
261 In the example above, if t2 and t3 become ready at the same time,
262 the code ensures that t2 is scheduled first.
264 Multiply-accumulate instructions are a bigger win for some targets
265 than others, so this macro is defined on an opt-in basis. */
266 #define TUNE_MACC_CHAINS (TUNE_MIPS5500 \
270 #define TARGET_OLDABI (mips_abi == ABI_32 || mips_abi == ABI_O64)
271 #define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)
273 /* IRIX specific stuff. */
274 #define TARGET_IRIX 0
275 #define TARGET_IRIX6 0
277 /* Define preprocessor macros for the -march and -mtune options.
278 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
279 processor. If INFO's canonical name is "foo", define PREFIX to
280 be "foo", and define an additional macro PREFIX_FOO. */
281 #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \
286 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \
287 for (p = macro; *p != 0; p++) \
290 builtin_define (macro); \
291 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \
296 /* Target CPU builtins. */
297 #define TARGET_CPU_CPP_BUILTINS() \
300 /* Everyone but IRIX defines this to mips. */ \
302 builtin_assert ("machine=mips"); \
304 builtin_assert ("cpu=mips"); \
305 builtin_define ("__mips__"); \
306 builtin_define ("_mips"); \
308 /* We do this here because __mips is defined below \
309 and so we can't use builtin_define_std. */ \
311 builtin_define ("mips"); \
314 builtin_define ("__mips64"); \
318 /* Treat _R3000 and _R4000 like register-size \
319 defines, which is how they've historically \
323 builtin_define_std ("R4000"); \
324 builtin_define ("_R4000"); \
328 builtin_define_std ("R3000"); \
329 builtin_define ("_R3000"); \
332 if (TARGET_FLOAT64) \
333 builtin_define ("__mips_fpr=64"); \
335 builtin_define ("__mips_fpr=32"); \
338 builtin_define ("__mips16"); \
341 builtin_define ("__mips3d"); \
344 builtin_define ("__mips_dsp"); \
346 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
347 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
351 builtin_define ("__mips=1"); \
352 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
354 else if (ISA_MIPS2) \
356 builtin_define ("__mips=2"); \
357 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
359 else if (ISA_MIPS3) \
361 builtin_define ("__mips=3"); \
362 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
364 else if (ISA_MIPS4) \
366 builtin_define ("__mips=4"); \
367 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
369 else if (ISA_MIPS32) \
371 builtin_define ("__mips=32"); \
372 builtin_define ("__mips_isa_rev=1"); \
373 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
375 else if (ISA_MIPS32R2) \
377 builtin_define ("__mips=32"); \
378 builtin_define ("__mips_isa_rev=2"); \
379 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
381 else if (ISA_MIPS64) \
383 builtin_define ("__mips=64"); \
384 builtin_define ("__mips_isa_rev=1"); \
385 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
387 else if (ISA_MIPS64R2) \
389 builtin_define ("__mips=64"); \
390 builtin_define ("__mips_isa_rev=2"); \
391 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
394 if (TARGET_HARD_FLOAT) \
395 builtin_define ("__mips_hard_float"); \
396 else if (TARGET_SOFT_FLOAT) \
397 builtin_define ("__mips_soft_float"); \
399 if (TARGET_SINGLE_FLOAT) \
400 builtin_define ("__mips_single_float"); \
402 if (TARGET_PAIRED_SINGLE_FLOAT) \
403 builtin_define ("__mips_paired_single_float"); \
405 if (TARGET_BIG_ENDIAN) \
407 builtin_define_std ("MIPSEB"); \
408 builtin_define ("_MIPSEB"); \
412 builtin_define_std ("MIPSEL"); \
413 builtin_define ("_MIPSEL"); \
416 /* Macros dependent on the C dialect. */ \
417 if (preprocessing_asm_p ()) \
419 builtin_define_std ("LANGUAGE_ASSEMBLY"); \
420 builtin_define ("_LANGUAGE_ASSEMBLY"); \
422 else if (c_dialect_cxx ()) \
424 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
425 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
426 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
430 builtin_define_std ("LANGUAGE_C"); \
431 builtin_define ("_LANGUAGE_C"); \
433 if (c_dialect_objc ()) \
435 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
436 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
437 /* Bizarre, but needed at least for Irix. */ \
438 builtin_define_std ("LANGUAGE_C"); \
439 builtin_define ("_LANGUAGE_C"); \
442 if (mips_abi == ABI_EABI) \
443 builtin_define ("__mips_eabi"); \
447 /* Default target_flags if no switches are specified */
449 #ifndef TARGET_DEFAULT
450 #define TARGET_DEFAULT 0
453 #ifndef TARGET_CPU_DEFAULT
454 #define TARGET_CPU_DEFAULT 0
457 #ifndef TARGET_ENDIAN_DEFAULT
458 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
461 #ifndef TARGET_FP_EXCEPTIONS_DEFAULT
462 #define TARGET_FP_EXCEPTIONS_DEFAULT MASK_FP_EXCEPTIONS
465 /* 'from-abi' makes a good default: you get whatever the ABI requires. */
466 #ifndef MIPS_ISA_DEFAULT
467 #ifndef MIPS_CPU_STRING_DEFAULT
468 #define MIPS_CPU_STRING_DEFAULT "from-abi"
474 /* Make this compile time constant for libgcc2 */
476 #define TARGET_64BIT 1
478 #define TARGET_64BIT 0
480 #endif /* IN_LIBGCC2 */
482 #define TARGET_LIBGCC_SDATA_SECTION ".sdata"
484 #ifndef MULTILIB_ENDIAN_DEFAULT
485 #if TARGET_ENDIAN_DEFAULT == 0
486 #define MULTILIB_ENDIAN_DEFAULT "EL"
488 #define MULTILIB_ENDIAN_DEFAULT "EB"
492 #ifndef MULTILIB_ISA_DEFAULT
493 # if MIPS_ISA_DEFAULT == 1
494 # define MULTILIB_ISA_DEFAULT "mips1"
496 # if MIPS_ISA_DEFAULT == 2
497 # define MULTILIB_ISA_DEFAULT "mips2"
499 # if MIPS_ISA_DEFAULT == 3
500 # define MULTILIB_ISA_DEFAULT "mips3"
502 # if MIPS_ISA_DEFAULT == 4
503 # define MULTILIB_ISA_DEFAULT "mips4"
505 # if MIPS_ISA_DEFAULT == 32
506 # define MULTILIB_ISA_DEFAULT "mips32"
508 # if MIPS_ISA_DEFAULT == 33
509 # define MULTILIB_ISA_DEFAULT "mips32r2"
511 # if MIPS_ISA_DEFAULT == 64
512 # define MULTILIB_ISA_DEFAULT "mips64"
514 # if MIPS_ISA_DEFAULT == 65
515 # define MULTILIB_ISA_DEFAULT "mips64r2"
517 # define MULTILIB_ISA_DEFAULT "mips1"
528 #ifndef MULTILIB_DEFAULTS
529 #define MULTILIB_DEFAULTS \
530 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
533 /* We must pass -EL to the linker by default for little endian embedded
534 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
535 linker will default to using big-endian output files. The OUTPUT_FORMAT
536 line must be in the linker script, otherwise -EB/-EL will not work. */
539 #if TARGET_ENDIAN_DEFAULT == 0
540 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
542 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
546 /* Support for a compile-time default CPU, et cetera. The rules are:
547 --with-arch is ignored if -march is specified or a -mips is specified
548 (other than -mips16).
549 --with-tune is ignored if -mtune is specified.
550 --with-abi is ignored if -mabi is specified.
551 --with-float is ignored if -mhard-float or -msoft-float are
553 --with-divide is ignored if -mdivide-traps or -mdivide-breaks are
555 #define OPTION_DEFAULT_SPECS \
556 {"arch", "%{!march=*:%{mips16:-march=%(VALUE)}%{!mips*:-march=%(VALUE)}}" }, \
557 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
558 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
559 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }, \
560 {"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" }
563 #define GENERATE_DIVIDE_TRAPS (TARGET_DIVIDE_TRAPS \
564 && ISA_HAS_COND_TRAP)
566 #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY \
570 /* Generate three-operand multiply instructions for SImode. */
571 #define GENERATE_MULT3_SI ((TARGET_MIPS3900 \
583 /* Generate three-operand multiply instructions for DImode. */
584 #define GENERATE_MULT3_DI ((TARGET_MIPS3900) \
587 /* True if the ABI can only work with 64-bit integer registers. We
588 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
589 otherwise floating-point registers must also be 64-bit. */
590 #define ABI_NEEDS_64BIT_REGS (TARGET_NEWABI || mips_abi == ABI_O64)
592 /* Likewise for 32-bit regs. */
593 #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
595 /* True if symbols are 64 bits wide. At present, n64 is the only
596 ABI for which this is true. */
597 #define ABI_HAS_64BIT_SYMBOLS (mips_abi == ABI_64 && !TARGET_SYM32)
599 /* ISA has instructions for managing 64 bit fp and gp regs (e.g. mips3). */
600 #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
605 /* ISA has branch likely instructions (e.g. mips2). */
606 /* Disable branchlikely for tx39 until compare rewrite. They haven't
607 been generated up to this point. */
608 #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1)
610 /* ISA has the conditional move instructions introduced in mips4. */
611 #define ISA_HAS_CONDMOVE ((ISA_MIPS4 \
616 && !TARGET_MIPS5500 \
619 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
620 branch on CC, and move (both FP and non-FP) on CC. */
621 #define ISA_HAS_8CC (ISA_MIPS4 \
627 /* This is a catch all for other mips4 instructions: indexed load, the
628 FP madd and msub instructions, and the FP recip and recip sqrt
630 #define ISA_HAS_FP4 ((ISA_MIPS4 \
635 /* ISA has conditional trap instructions. */
636 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
639 /* ISA has integer multiply-accumulate instructions, madd and msub. */
640 #define ISA_HAS_MADD_MSUB ((ISA_MIPS32 \
646 /* ISA has floating-point nmadd and nmsub instructions. */
647 #define ISA_HAS_NMADD_NMSUB ((ISA_MIPS4 \
650 && (!TARGET_MIPS5400 || TARGET_MAD) \
653 /* ISA has count leading zeroes/ones instruction (not implemented). */
654 #define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \
660 /* ISA has double-word count leading zeroes/ones instruction (not
662 #define ISA_HAS_DCLZ_DCLO (ISA_MIPS64 \
666 /* ISA has three operand multiply instructions that put
667 the high part in an accumulator: mulhi or mulhiu. */
668 #define ISA_HAS_MULHI (TARGET_MIPS5400 \
673 /* ISA has three operand multiply instructions that
674 negates the result and puts the result in an accumulator. */
675 #define ISA_HAS_MULS (TARGET_MIPS5400 \
680 /* ISA has three operand multiply instructions that subtracts the
681 result from a 4th operand and puts the result in an accumulator. */
682 #define ISA_HAS_MSAC (TARGET_MIPS5400 \
686 /* ISA has three operand multiply instructions that the result
687 from a 4th operand and puts the result in an accumulator. */
688 #define ISA_HAS_MACC ((TARGET_MIPS4120 && !TARGET_MIPS16) \
689 || (TARGET_MIPS4130 && !TARGET_MIPS16) \
695 /* ISA has NEC VR-style MACC, MACCHI, DMACC and DMACCHI instructions. */
696 #define ISA_HAS_MACCHI (!TARGET_MIPS16 \
697 && (TARGET_MIPS4120 \
700 /* ISA has 32-bit rotate right instruction. */
701 #define ISA_HAS_ROTR_SI (!TARGET_MIPS16 \
709 /* ISA has 64-bit rotate right instruction. */
710 #define ISA_HAS_ROTR_DI (TARGET_64BIT \
712 && (TARGET_MIPS5400 \
717 /* ISA has data prefetch instructions. This controls use of 'pref'. */
718 #define ISA_HAS_PREFETCH ((ISA_MIPS4 \
725 /* ISA has data indexed prefetch instructions. This controls use of
726 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT.
727 (prefx is a cop1x instruction, so can only be used if FP is
729 #define ISA_HAS_PREFETCHX ((ISA_MIPS4 \
734 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
735 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
736 also requires TARGET_DOUBLE_FLOAT. */
737 #define ISA_HAS_TRUNC_W (!ISA_MIPS1)
739 /* ISA includes the MIPS32r2 seb and seh instructions. */
740 #define ISA_HAS_SEB_SEH (!TARGET_MIPS16 \
745 /* ISA includes the MIPS32/64 rev 2 ext and ins instructions. */
746 #define ISA_HAS_EXT_INS (!TARGET_MIPS16 \
751 /* True if the result of a load is not available to the next instruction.
752 A nop will then be needed between instructions like "lw $4,..."
753 and "addiu $4,$4,1". */
754 #define ISA_HAS_LOAD_DELAY (mips_isa == 1 \
755 && !TARGET_MIPS3900 \
758 /* Likewise mtc1 and mfc1. */
759 #define ISA_HAS_XFER_DELAY (mips_isa <= 3)
761 /* Likewise floating-point comparisons. */
762 #define ISA_HAS_FCMP_DELAY (mips_isa <= 3)
764 /* True if mflo and mfhi can be immediately followed by instructions
765 which write to the HI and LO registers.
767 According to MIPS specifications, MIPS ISAs I, II, and III need
768 (at least) two instructions between the reads of HI/LO and
769 instructions which write them, and later ISAs do not. Contradicting
770 the MIPS specifications, some MIPS IV processor user manuals (e.g.
771 the UM for the NEC Vr5000) document needing the instructions between
772 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
773 MIPS64 and later ISAs to have the interlocks, plus any specific
774 earlier-ISA CPUs for which CPU documentation declares that the
775 instructions are really interlocked. */
776 #define ISA_HAS_HILO_INTERLOCKS (ISA_MIPS32 \
782 /* Add -G xx support. */
784 #undef SWITCH_TAKES_ARG
785 #define SWITCH_TAKES_ARG(CHAR) \
786 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
788 #define OVERRIDE_OPTIONS override_options ()
790 #define CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage ()
792 /* Show we can debug even without a frame pointer. */
793 #define CAN_DEBUG_WITHOUT_FP
795 /* Tell collect what flags to pass to nm. */
797 #define NM_FLAGS "-Bn"
801 #ifndef MIPS_ABI_DEFAULT
802 #define MIPS_ABI_DEFAULT ABI_32
805 /* Use the most portable ABI flag for the ASM specs. */
807 #if MIPS_ABI_DEFAULT == ABI_32
808 #define MULTILIB_ABI_DEFAULT "mabi=32"
811 #if MIPS_ABI_DEFAULT == ABI_O64
812 #define MULTILIB_ABI_DEFAULT "mabi=o64"
815 #if MIPS_ABI_DEFAULT == ABI_N32
816 #define MULTILIB_ABI_DEFAULT "mabi=n32"
819 #if MIPS_ABI_DEFAULT == ABI_64
820 #define MULTILIB_ABI_DEFAULT "mabi=64"
823 #if MIPS_ABI_DEFAULT == ABI_EABI
824 #define MULTILIB_ABI_DEFAULT "mabi=eabi"
827 /* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options
828 to the assembler. It may be overridden by subtargets. */
829 #ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
830 #define SUBTARGET_ASM_OPTIMIZING_SPEC "\
832 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
835 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
836 the assembler. It may be overridden by subtargets.
838 Beginning with gas 2.13, -mdebug must be passed to correctly handle
839 COFF debugging info. */
841 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
842 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
843 %{g} %{g0} %{g1} %{g2} %{g3} \
844 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
845 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
846 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
847 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
848 %{gcoff*:-mdebug} %{!gcoff*:-no-mdebug}"
851 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
852 overridden by subtargets. */
854 #ifndef SUBTARGET_ASM_SPEC
855 #define SUBTARGET_ASM_SPEC ""
860 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
861 %{mips32} %{mips32r2} %{mips64} \
862 %{mips16:%{!mno-mips16:-mips16}} %{mno-mips16:-no-mips16} \
865 %{mfix-vr4120} %{mfix-vr4130} \
866 %(subtarget_asm_optimizing_spec) \
867 %(subtarget_asm_debugging_spec) \
868 %{mabi=*} %{!mabi*: %(asm_abi_default_spec)} \
869 %{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \
870 %{mshared} %{mno-shared} \
871 %{msym32} %{mno-sym32} \
873 %(subtarget_asm_spec)"
875 /* Extra switches sometimes passed to the linker. */
876 /* ??? The bestGnum will never be passed to the linker, because the gcc driver
877 will interpret it as a -b option. */
882 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32} %{mips32r2} %{mips64} \
883 %{bestGnum} %{shared} %{non_shared}"
884 #endif /* LINK_SPEC defined */
887 /* Specs for the compiler proper */
889 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
890 overridden by subtargets. */
891 #ifndef SUBTARGET_CC1_SPEC
892 #define SUBTARGET_CC1_SPEC ""
895 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
899 %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
900 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
902 %(subtarget_cc1_spec)"
904 /* Preprocessor specs. */
906 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
907 overridden by subtargets. */
908 #ifndef SUBTARGET_CPP_SPEC
909 #define SUBTARGET_CPP_SPEC ""
912 #define CPP_SPEC "%(subtarget_cpp_spec)"
914 /* This macro defines names of additional specifications to put in the specs
915 that can be used in various specifications like CC1_SPEC. Its definition
916 is an initializer with a subgrouping for each command option.
918 Each subgrouping contains a string constant, that defines the
919 specification name, and a string constant that used by the GCC driver
922 Do not define this macro if it does not need to do anything. */
924 #define EXTRA_SPECS \
925 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
926 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
927 { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \
928 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
929 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
930 { "asm_abi_default_spec", "-" MULTILIB_ABI_DEFAULT }, \
931 { "endian_spec", ENDIAN_SPEC }, \
932 SUBTARGET_EXTRA_SPECS
934 #ifndef SUBTARGET_EXTRA_SPECS
935 #define SUBTARGET_EXTRA_SPECS
938 #define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */
939 #define MIPS_DEBUGGING_INFO 1 /* MIPS specific debugging info */
940 #define DWARF2_DEBUGGING_INFO 1 /* dwarf2 debugging info */
942 #ifndef PREFERRED_DEBUGGING_TYPE
943 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
946 #define DWARF2_ADDR_SIZE (ABI_HAS_64BIT_SYMBOLS ? 8 : 4)
948 /* By default, turn on GDB extensions. */
949 #define DEFAULT_GDB_EXTENSIONS 1
951 /* Local compiler-generated symbols must have a prefix that the assembler
952 understands. By default, this is $, although some targets (e.g.,
953 NetBSD-ELF) need to override this. */
955 #ifndef LOCAL_LABEL_PREFIX
956 #define LOCAL_LABEL_PREFIX "$"
959 /* By default on the mips, external symbols do not have an underscore
960 prepended, but some targets (e.g., NetBSD) require this. */
962 #ifndef USER_LABEL_PREFIX
963 #define USER_LABEL_PREFIX ""
966 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
967 since the length can run past this up to a continuation point. */
968 #undef DBX_CONTIN_LENGTH
969 #define DBX_CONTIN_LENGTH 1500
971 /* How to renumber registers for dbx and gdb. */
972 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[ (REGNO) ]
974 /* The mapping from gcc register number to DWARF 2 CFA column number. */
975 #define DWARF_FRAME_REGNUM(REG) (REG)
977 /* The DWARF 2 CFA column which tracks the return address. */
978 #define DWARF_FRAME_RETURN_COLUMN (GP_REG_FIRST + 31)
980 /* The DWARF 2 CFA column which tracks the return address from a
981 signal handler context. */
982 #define SIGNAL_UNWIND_RETURN_COLUMN (FP_REG_LAST + 1)
984 /* Before the prologue, RA lives in r31. */
985 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
987 /* Describe how we implement __builtin_eh_return. */
988 #define EH_RETURN_DATA_REGNO(N) \
989 ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
991 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
993 /* Offsets recorded in opcodes are a multiple of this alignment factor.
994 The default for this in 64-bit mode is 8, which causes problems with
995 SFmode register saves. */
996 #define DWARF_CIE_DATA_ALIGNMENT -4
998 /* Correct the offset of automatic variables and arguments. Note that
999 the MIPS debug format wants all automatic variables and arguments
1000 to be in terms of the virtual frame pointer (stack pointer before
1001 any adjustment in the function), while the MIPS 3.0 linker wants
1002 the frame pointer to be the stack pointer after the initial
1005 #define DEBUGGER_AUTO_OFFSET(X) \
1006 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1007 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1008 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1010 /* Target machine storage layout */
1012 #define BITS_BIG_ENDIAN 0
1013 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1014 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1016 /* Define this to set the endianness to use in libgcc2.c, which can
1017 not depend on target_flags. */
1018 #if !defined(MIPSEL) && !defined(__MIPSEL__)
1019 #define LIBGCC2_WORDS_BIG_ENDIAN 1
1021 #define LIBGCC2_WORDS_BIG_ENDIAN 0
1024 #define MAX_BITS_PER_WORD 64
1026 /* Width of a word, in units (bytes). */
1027 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1029 #define MIN_UNITS_PER_WORD 4
1032 /* For MIPS, width of a floating point register. */
1033 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1035 /* If register $f0 holds a floating-point value, $f(0 + FP_INC) is
1036 the next available register. */
1037 #define FP_INC (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
1039 /* The largest size of value that can be held in floating-point
1040 registers and moved with a single instruction. */
1041 #define UNITS_PER_HWFPVALUE (TARGET_SOFT_FLOAT ? 0 : FP_INC * UNITS_PER_FPREG)
1043 /* The largest size of value that can be held in floating-point
1045 #define UNITS_PER_FPVALUE \
1046 (TARGET_SOFT_FLOAT ? 0 \
1047 : TARGET_SINGLE_FLOAT ? UNITS_PER_FPREG \
1048 : LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)
1050 /* The number of bytes in a double. */
1051 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
1053 #define UNITS_PER_SIMD_WORD (TARGET_PAIRED_SINGLE_FLOAT ? 8 : UNITS_PER_WORD)
1055 /* Set the sizes of the core types. */
1056 #define SHORT_TYPE_SIZE 16
1057 #define INT_TYPE_SIZE 32
1058 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1059 #define LONG_LONG_TYPE_SIZE 64
1061 #define FLOAT_TYPE_SIZE 32
1062 #define DOUBLE_TYPE_SIZE 64
1063 #define LONG_DOUBLE_TYPE_SIZE (TARGET_NEWABI ? 128 : 64)
1065 /* long double is not a fixed mode, but the idea is that, if we
1066 support long double, we also want a 128-bit integer type. */
1067 #define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE
1070 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
1071 || (defined _ABI64 && _MIPS_SIM == _ABI64)
1072 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
1074 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
1078 /* Width in bits of a pointer. */
1079 #ifndef POINTER_SIZE
1080 #define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32)
1083 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1084 #define PARM_BOUNDARY BITS_PER_WORD
1086 /* Allocation boundary (in *bits*) for the code of a function. */
1087 #define FUNCTION_BOUNDARY 32
1089 /* Alignment of field after `int : 0' in a structure. */
1090 #define EMPTY_FIELD_BOUNDARY 32
1092 /* Every structure's size must be a multiple of this. */
1093 /* 8 is observed right on a DECstation and on riscos 4.02. */
1094 #define STRUCTURE_SIZE_BOUNDARY 8
1096 /* There is no point aligning anything to a rounder boundary than this. */
1097 #define BIGGEST_ALIGNMENT LONG_DOUBLE_TYPE_SIZE
1099 /* All accesses must be aligned. */
1100 #define STRICT_ALIGNMENT 1
1102 /* Define this if you wish to imitate the way many other C compilers
1103 handle alignment of bitfields and the structures that contain
1106 The behavior is that the type written for a bit-field (`int',
1107 `short', or other integer type) imposes an alignment for the
1108 entire structure, as if the structure really did contain an
1109 ordinary field of that type. In addition, the bit-field is placed
1110 within the structure so that it would fit within such a field,
1111 not crossing a boundary for it.
1113 Thus, on most machines, a bit-field whose type is written as `int'
1114 would not cross a four-byte boundary, and would force four-byte
1115 alignment for the whole structure. (The alignment used may not
1116 be four bytes; it is controlled by the other alignment
1119 If the macro is defined, its definition should be a C expression;
1120 a nonzero value for the expression enables this behavior. */
1122 #define PCC_BITFIELD_TYPE_MATTERS 1
1124 /* If defined, a C expression to compute the alignment given to a
1125 constant that is being placed in memory. CONSTANT is the constant
1126 and ALIGN is the alignment that the object would ordinarily have.
1127 The value of this macro is used instead of that alignment to align
1130 If this macro is not defined, then ALIGN is used.
1132 The typical use of this macro is to increase alignment for string
1133 constants to be word aligned so that `strcpy' calls that copy
1134 constants can be done inline. */
1136 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1137 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1138 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1140 /* If defined, a C expression to compute the alignment for a static
1141 variable. TYPE is the data type, and ALIGN is the alignment that
1142 the object would ordinarily have. The value of this macro is used
1143 instead of that alignment to align the object.
1145 If this macro is not defined, then ALIGN is used.
1147 One use of this macro is to increase alignment of medium-size
1148 data to make it all fit in fewer cache lines. Another is to
1149 cause character arrays to be word-aligned so that `strcpy' calls
1150 that copy constants to character arrays can be done inline. */
1152 #undef DATA_ALIGNMENT
1153 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1154 ((((ALIGN) < BITS_PER_WORD) \
1155 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1156 || TREE_CODE (TYPE) == UNION_TYPE \
1157 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1160 #define PAD_VARARGS_DOWN \
1161 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
1163 /* Define if operations between registers always perform the operation
1164 on the full register even if a narrower mode is specified. */
1165 #define WORD_REGISTER_OPERATIONS
1167 /* When in 64 bit mode, move insns will sign extend SImode and CCmode
1168 moves. All other references are zero extended. */
1169 #define LOAD_EXTEND_OP(MODE) \
1170 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1171 ? SIGN_EXTEND : ZERO_EXTEND)
1173 /* Define this macro if it is advisable to hold scalars in registers
1174 in a wider mode than that declared by the program. In such cases,
1175 the value is constrained to be within the bounds of the declared
1176 type, but kept valid in the wider mode. The signedness of the
1177 extension may differ from that of the type. */
1179 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1180 if (GET_MODE_CLASS (MODE) == MODE_INT \
1181 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
1183 if ((MODE) == SImode) \
1188 /* Define if loading short immediate values into registers sign extends. */
1189 #define SHORT_IMMEDIATES_SIGN_EXTEND
1191 /* The [d]clz instructions have the natural values at 0. */
1193 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1194 ((VALUE) = GET_MODE_BITSIZE (MODE), true)
1196 /* Standard register usage. */
1198 /* Number of hardware registers. We have:
1200 - 32 integer registers
1201 - 32 floating point registers
1202 - 8 condition code registers
1203 - 2 accumulator registers (hi and lo)
1204 - 32 registers each for coprocessors 0, 2 and 3
1206 - ARG_POINTER_REGNUM
1207 - FRAME_POINTER_REGNUM
1208 - FAKE_CALL_REGNO (see the comment above load_callsi for details)
1209 - 3 dummy entries that were used at various times in the past.
1210 - 6 DSP accumulator registers (3 hi-lo pairs) for MIPS DSP ASE
1211 - 6 DSP control registers */
1213 #define FIRST_PSEUDO_REGISTER 188
1215 /* By default, fix the kernel registers ($26 and $27), the global
1216 pointer ($28) and the stack pointer ($29). This can change
1217 depending on the command-line options.
1219 Regarding coprocessor registers: without evidence to the contrary,
1220 it's best to assume that each coprocessor register has a unique
1221 use. This can be overridden, in, e.g., override_options() or
1222 CONDITIONAL_REGISTER_USAGE should the assumption be inappropriate
1223 for a particular target. */
1225 #define FIXED_REGISTERS \
1227 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1228 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \
1229 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1230 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1231 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \
1232 /* COP0 registers */ \
1233 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1234 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1235 /* COP2 registers */ \
1236 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1237 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1238 /* COP3 registers */ \
1239 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1240 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1241 /* 6 DSP accumulator registers & 6 control registers */ \
1242 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1 \
1246 /* Set up this array for o32 by default.
1248 Note that we don't mark $31 as a call-clobbered register. The idea is
1249 that it's really the call instructions themselves which clobber $31.
1250 We don't care what the called function does with it afterwards.
1252 This approach makes it easier to implement sibcalls. Unlike normal
1253 calls, sibcalls don't clobber $31, so the register reaches the
1254 called function in tact. EPILOGUE_USES says that $31 is useful
1255 to the called function. */
1257 #define CALL_USED_REGISTERS \
1259 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1260 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
1261 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1262 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1263 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1264 /* COP0 registers */ \
1265 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1266 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1267 /* COP2 registers */ \
1268 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1269 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1270 /* COP3 registers */ \
1271 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1272 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1273 /* 6 DSP accumulator registers & 6 control registers */ \
1274 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1278 /* Define this since $28, though fixed, is call-saved in many ABIs. */
1280 #define CALL_REALLY_USED_REGISTERS \
1281 { /* General registers. */ \
1282 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1283 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \
1284 /* Floating-point registers. */ \
1285 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1286 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1288 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1289 /* COP0 registers */ \
1290 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1291 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1292 /* COP2 registers */ \
1293 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1294 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1295 /* COP3 registers */ \
1296 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1297 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1298 /* 6 DSP accumulator registers & 6 control registers */ \
1299 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0 \
1302 /* Internal macros to classify a register number as to whether it's a
1303 general purpose register, a floating point register, a
1304 multiply/divide register, or a status register. */
1306 #define GP_REG_FIRST 0
1307 #define GP_REG_LAST 31
1308 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1309 #define GP_DBX_FIRST 0
1311 #define FP_REG_FIRST 32
1312 #define FP_REG_LAST 63
1313 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1314 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1316 #define MD_REG_FIRST 64
1317 #define MD_REG_LAST 65
1318 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1319 #define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM)
1321 #define ST_REG_FIRST 67
1322 #define ST_REG_LAST 74
1323 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1326 /* FIXME: renumber. */
1327 #define COP0_REG_FIRST 80
1328 #define COP0_REG_LAST 111
1329 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1331 #define COP2_REG_FIRST 112
1332 #define COP2_REG_LAST 143
1333 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1335 #define COP3_REG_FIRST 144
1336 #define COP3_REG_LAST 175
1337 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1338 /* ALL_COP_REG_NUM assumes that COP0,2,and 3 are numbered consecutively. */
1339 #define ALL_COP_REG_NUM (COP3_REG_LAST - COP0_REG_FIRST + 1)
1341 #define DSP_ACC_REG_FIRST 176
1342 #define DSP_ACC_REG_LAST 181
1343 #define DSP_ACC_REG_NUM (DSP_ACC_REG_LAST - DSP_ACC_REG_FIRST + 1)
1345 #define AT_REGNUM (GP_REG_FIRST + 1)
1346 #define HI_REGNUM (MD_REG_FIRST + 0)
1347 #define LO_REGNUM (MD_REG_FIRST + 1)
1348 #define AC1HI_REGNUM (DSP_ACC_REG_FIRST + 0)
1349 #define AC1LO_REGNUM (DSP_ACC_REG_FIRST + 1)
1350 #define AC2HI_REGNUM (DSP_ACC_REG_FIRST + 2)
1351 #define AC2LO_REGNUM (DSP_ACC_REG_FIRST + 3)
1352 #define AC3HI_REGNUM (DSP_ACC_REG_FIRST + 4)
1353 #define AC3LO_REGNUM (DSP_ACC_REG_FIRST + 5)
1355 /* FPSW_REGNUM is the single condition code used if !ISA_HAS_8CC.
1356 If ISA_HAS_8CC, it should not be used, and an arbitrary ST_REG
1357 should be used instead. */
1358 #define FPSW_REGNUM ST_REG_FIRST
1360 #define GP_REG_P(REGNO) \
1361 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1362 #define M16_REG_P(REGNO) \
1363 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1364 #define FP_REG_P(REGNO) \
1365 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1366 #define MD_REG_P(REGNO) \
1367 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1368 #define ST_REG_P(REGNO) \
1369 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1370 #define COP0_REG_P(REGNO) \
1371 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1372 #define COP2_REG_P(REGNO) \
1373 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1374 #define COP3_REG_P(REGNO) \
1375 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1376 #define ALL_COP_REG_P(REGNO) \
1377 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1378 /* Test if REGNO is one of the 6 new DSP accumulators. */
1379 #define DSP_ACC_REG_P(REGNO) \
1380 ((unsigned int) ((int) (REGNO) - DSP_ACC_REG_FIRST) < DSP_ACC_REG_NUM)
1381 /* Test if REGNO is hi, lo, or one of the 6 new DSP accumulators. */
1382 #define ACC_REG_P(REGNO) \
1383 (MD_REG_P (REGNO) || DSP_ACC_REG_P (REGNO))
1384 /* Test if REGNO is HI or the first register of 3 new DSP accumulator pairs. */
1385 #define ACC_HI_REG_P(REGNO) \
1386 ((REGNO) == HI_REGNUM || (REGNO) == AC1HI_REGNUM || (REGNO) == AC2HI_REGNUM \
1387 || (REGNO) == AC3HI_REGNUM)
1389 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X)))
1391 /* True if X is (const (unspec [(const_int 0)] UNSPEC_GP)). This is used
1392 to initialize the mips16 gp pseudo register. */
1393 #define CONST_GP_P(X) \
1394 (GET_CODE (X) == CONST \
1395 && GET_CODE (XEXP (X, 0)) == UNSPEC \
1396 && XINT (XEXP (X, 0), 1) == UNSPEC_GP)
1398 /* Return coprocessor number from register number. */
1400 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
1401 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \
1402 : COP3_REG_P (REGNO) ? '3' : '?')
1405 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
1407 /* To make the code simpler, HARD_REGNO_MODE_OK just references an
1408 array built in override_options. Because machmodes.h is not yet
1409 included before this file is processed, the MODE bound can't be
1412 extern char mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
1414 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1415 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1417 /* Value is 1 if it is a good idea to tie two pseudo registers
1418 when one has mode MODE1 and one has mode MODE2.
1419 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1420 for any hard reg, then this must be 0 for correct output. */
1421 #define MODES_TIEABLE_P(MODE1, MODE2) \
1422 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
1423 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
1424 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
1425 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
1427 /* Register to use for pushing function arguments. */
1428 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1430 /* These two registers don't really exist: they get eliminated to either
1431 the stack or hard frame pointer. */
1432 #define ARG_POINTER_REGNUM 77
1433 #define FRAME_POINTER_REGNUM 78
1435 /* $30 is not available on the mips16, so we use $17 as the frame
1437 #define HARD_FRAME_POINTER_REGNUM \
1438 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1440 /* Value should be nonzero if functions must have frame pointers.
1441 Zero means the frame pointer need not be set up (and parms
1442 may be accessed via the stack pointer) in functions that seem suitable.
1443 This is computed in `reload', in reload1.c. */
1444 #define FRAME_POINTER_REQUIRED (current_function_calls_alloca)
1446 /* Register in which static-chain is passed to a function. */
1447 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2)
1449 /* Registers used as temporaries in prologue/epilogue code. If we're
1450 generating mips16 code, these registers must come from the core set
1451 of 8. The prologue register mustn't conflict with any incoming
1452 arguments, the static chain pointer, or the frame pointer. The
1453 epilogue temporary mustn't conflict with the return registers, the
1454 frame pointer, the EH stack adjustment, or the EH data registers. */
1456 #define MIPS_PROLOGUE_TEMP_REGNUM (GP_REG_FIRST + 3)
1457 #define MIPS_EPILOGUE_TEMP_REGNUM (GP_REG_FIRST + (TARGET_MIPS16 ? 6 : 8))
1459 #define MIPS_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP_REGNUM)
1460 #define MIPS_EPILOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_EPILOGUE_TEMP_REGNUM)
1462 /* Define this macro if it is as good or better to call a constant
1463 function address than to call an address kept in a register. */
1464 #define NO_FUNCTION_CSE 1
1466 /* The ABI-defined global pointer. Sometimes we use a different
1467 register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */
1468 #define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28)
1470 /* We normally use $28 as the global pointer. However, when generating
1471 n32/64 PIC, it is better for leaf functions to use a call-clobbered
1472 register instead. They can then avoid saving and restoring $28
1473 and perhaps avoid using a frame at all.
1475 When a leaf function uses something other than $28, mips_expand_prologue
1476 will modify pic_offset_table_rtx in place. Take the register number
1477 from there after reload. */
1478 #define PIC_OFFSET_TABLE_REGNUM \
1479 (reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM)
1481 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
1483 /* Define the classes of registers for register constraints in the
1484 machine description. Also define ranges of constants.
1486 One of the classes must always be named ALL_REGS and include all hard regs.
1487 If there is more than one class, another class must be named NO_REGS
1488 and contain no registers.
1490 The name GENERAL_REGS must be the name of a class (or an alias for
1491 another name such as ALL_REGS). This is the class of registers
1492 that is allowed by "g" or "r" in a register constraint.
1493 Also, registers outside this class are allocated only when
1494 instructions express preferences for them.
1496 The classes must be numbered in nondecreasing order; that is,
1497 a larger-numbered class must never be contained completely
1498 in a smaller-numbered class.
1500 For any two classes, it is very desirable that there be another
1501 class that represents their union. */
1505 NO_REGS, /* no registers in set */
1506 M16_NA_REGS, /* mips16 regs not used to pass args */
1507 M16_REGS, /* mips16 directly accessible registers */
1508 T_REG, /* mips16 T register ($24) */
1509 M16_T_REGS, /* mips16 registers plus T register */
1510 PIC_FN_ADDR_REG, /* SVR4 PIC function address register */
1511 V1_REG, /* Register $v1 ($3) used for TLS access. */
1512 LEA_REGS, /* Every GPR except $25 */
1513 GR_REGS, /* integer registers */
1514 FP_REGS, /* floating point registers */
1515 HI_REG, /* hi register */
1516 LO_REG, /* lo register */
1517 MD_REGS, /* multiply/divide registers (hi/lo) */
1518 COP0_REGS, /* generic coprocessor classes */
1521 HI_AND_GR_REGS, /* union classes */
1528 ALL_COP_AND_GR_REGS,
1529 ST_REGS, /* status registers (fp status) */
1530 DSP_ACC_REGS, /* DSP accumulator registers */
1531 ACC_REGS, /* Hi/Lo and DSP accumulator registers */
1532 ALL_REGS, /* all registers */
1533 LIM_REG_CLASSES /* max value + 1 */
1536 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1538 #define GENERAL_REGS GR_REGS
1540 /* An initializer containing the names of the register classes as C
1541 string constants. These names are used in writing some of the
1544 #define REG_CLASS_NAMES \
1551 "PIC_FN_ADDR_REG", \
1559 /* coprocessor registers */ \
1566 "COP0_AND_GR_REGS", \
1567 "COP2_AND_GR_REGS", \
1568 "COP3_AND_GR_REGS", \
1570 "ALL_COP_AND_GR_REGS", \
1577 /* An initializer containing the contents of the register classes,
1578 as integers which are bit masks. The Nth integer specifies the
1579 contents of class N. The way the integer MASK is interpreted is
1580 that register R is in the class if `MASK & (1 << R)' is 1.
1582 When the machine has more than 32 registers, an integer does not
1583 suffice. Then the integers are replaced by sub-initializers,
1584 braced groupings containing several integers. Each
1585 sub-initializer must be suitable as an initializer for the type
1586 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1588 #define REG_CLASS_CONTENTS \
1590 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* no registers */ \
1591 { 0x0003000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 nonarg regs */\
1592 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 registers */ \
1593 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 T register */ \
1594 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 and T regs */ \
1595 { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* SVR4 PIC function address register */ \
1596 { 0x00000008, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* only $v1 */ \
1597 { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* Every other GPR except $25 */ \
1598 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* integer registers */ \
1599 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* floating registers*/ \
1600 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* hi register */ \
1601 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* lo register */ \
1602 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* mul/div registers */ \
1603 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* cop0 registers */ \
1604 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* cop2 registers */ \
1605 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* cop3 registers */ \
1606 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* union classes */ \
1607 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, \
1608 { 0x00000000, 0xffffffff, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, \
1609 { 0xffffffff, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, \
1610 { 0xffffffff, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, \
1611 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, \
1612 { 0x00000000, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
1613 { 0xffffffff, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
1614 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* status registers */ \
1615 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x003f0000 }, /* dsp accumulator registers */ \
1616 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* hi/lo and dsp accumulator registers */ \
1617 { 0xffffffff, 0xffffffff, 0xffff07ff, 0xffffffff, 0xffffffff, 0x0fffffff } /* all registers */ \
1621 /* A C expression whose value is a register class containing hard
1622 register REGNO. In general there is more that one such class;
1623 choose a class which is "minimal", meaning that no smaller class
1624 also contains the register. */
1626 extern const enum reg_class mips_regno_to_class[];
1628 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1630 /* A macro whose definition is the name of the class to which a
1631 valid base register must belong. A base register is one used in
1632 an address which is the register value plus a displacement. */
1634 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
1636 /* A macro whose definition is the name of the class to which a
1637 valid index register must belong. An index register is one used
1638 in an address where its value is either multiplied by a scale
1639 factor or added to another register (as well as added to a
1642 #define INDEX_REG_CLASS NO_REGS
1644 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1645 registers explicitly used in the rtl to be used as spill registers
1646 but prevents the compiler from extending the lifetime of these
1649 #define SMALL_REGISTER_CLASSES (TARGET_MIPS16)
1651 /* This macro is used later on in the file. */
1652 #define GR_REG_CLASS_P(CLASS) \
1653 ((CLASS) == GR_REGS || (CLASS) == M16_REGS || (CLASS) == T_REG \
1654 || (CLASS) == M16_T_REGS || (CLASS) == M16_NA_REGS \
1655 || (CLASS) == V1_REG \
1656 || (CLASS) == PIC_FN_ADDR_REG || (CLASS) == LEA_REGS)
1658 /* This macro is also used later on in the file. */
1659 #define COP_REG_CLASS_P(CLASS) \
1660 ((CLASS) == COP0_REGS || (CLASS) == COP2_REGS || (CLASS) == COP3_REGS)
1662 /* REG_ALLOC_ORDER is to order in which to allocate registers. This
1663 is the default value (allocate the registers in numeric order). We
1664 define it just so that we can override it for the mips16 target in
1665 ORDER_REGS_FOR_LOCAL_ALLOC. */
1667 #define REG_ALLOC_ORDER \
1668 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
1669 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
1670 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
1671 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
1672 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
1673 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
1674 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
1675 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
1676 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
1677 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
1678 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175, \
1679 176,177,178,179,180,181,182,183,184,185,186,187 \
1682 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
1683 to be rearranged based on a particular function. On the mips16, we
1684 want to allocate $24 (T_REG) before other registers for
1685 instructions for which it is possible. */
1687 #define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc ()
1689 /* True if VALUE is an unsigned 6-bit number. */
1691 #define UIMM6_OPERAND(VALUE) \
1692 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0x3f) == 0)
1694 /* True if VALUE is a signed 10-bit number. */
1696 #define IMM10_OPERAND(VALUE) \
1697 ((unsigned HOST_WIDE_INT) (VALUE) + 0x200 < 0x400)
1699 /* True if VALUE is a signed 16-bit number. */
1701 #define SMALL_OPERAND(VALUE) \
1702 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
1704 /* True if VALUE is an unsigned 16-bit number. */
1706 #define SMALL_OPERAND_UNSIGNED(VALUE) \
1707 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
1709 /* True if VALUE can be loaded into a register using LUI. */
1711 #define LUI_OPERAND(VALUE) \
1712 (((VALUE) | 0x7fff0000) == 0x7fff0000 \
1713 || ((VALUE) | 0x7fff0000) + 0x10000 == 0)
1715 /* Return a value X with the low 16 bits clear, and such that
1716 VALUE - X is a signed 16-bit value. */
1718 #define CONST_HIGH_PART(VALUE) \
1719 (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff)
1721 #define CONST_LOW_PART(VALUE) \
1722 ((VALUE) - CONST_HIGH_PART (VALUE))
1724 #define SMALL_INT(X) SMALL_OPERAND (INTVAL (X))
1725 #define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X))
1726 #define LUI_INT(X) LUI_OPERAND (INTVAL (X))
1728 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1729 mips_preferred_reload_class (X, CLASS)
1731 /* Certain machines have the property that some registers cannot be
1732 copied to some other registers without using memory. Define this
1733 macro on those machines to be a C expression that is nonzero if
1734 objects of mode MODE in registers of CLASS1 can only be copied to
1735 registers of class CLASS2 by storing a register of CLASS1 into
1736 memory and loading that memory location into a register of CLASS2.
1738 Do not define this macro if its value would always be zero. */
1740 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
1741 ((!TARGET_DEBUG_H_MODE \
1742 && GET_MODE_CLASS (MODE) == MODE_INT \
1743 && ((CLASS1 == FP_REGS && GR_REG_CLASS_P (CLASS2)) \
1744 || (GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS))) \
1745 || (TARGET_FLOAT64 && !TARGET_64BIT && (MODE) == DFmode \
1746 && ((GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS) \
1747 || (GR_REG_CLASS_P (CLASS2) && CLASS1 == FP_REGS))))
1749 /* The HI and LO registers can only be reloaded via the general
1750 registers. Condition code registers can only be loaded to the
1751 general registers, and from the floating point registers. */
1753 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1754 mips_secondary_reload_class (CLASS, MODE, X, 1)
1755 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1756 mips_secondary_reload_class (CLASS, MODE, X, 0)
1758 /* Return the maximum number of consecutive registers
1759 needed to represent mode MODE in a register of class CLASS. */
1761 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
1763 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1764 mips_cannot_change_mode_class (FROM, TO, CLASS)
1766 /* Stack layout; function entry, exit and calling. */
1768 #define STACK_GROWS_DOWNWARD
1770 /* The offset of the first local variable from the beginning of the frame.
1771 See compute_frame_size for details about the frame layout.
1773 ??? If flag_profile_values is true, and we are generating 32-bit code, then
1774 we assume that we will need 16 bytes of argument space. This is because
1775 the value profiling code may emit calls to cmpdi2 in leaf functions.
1776 Without this hack, the local variables will start at sp+8 and the gp save
1777 area will be at sp+16, and thus they will overlap. compute_frame_size is
1778 OK because it uses STARTING_FRAME_OFFSET to compute cprestore_size, which
1779 will end up as 24 instead of 8. This won't be needed if profiling code is
1780 inserted before virtual register instantiation. */
1782 #define STARTING_FRAME_OFFSET \
1783 ((flag_profile_values && ! TARGET_64BIT \
1784 ? MAX (REG_PARM_STACK_SPACE(NULL), current_function_outgoing_args_size) \
1785 : current_function_outgoing_args_size) \
1786 + (TARGET_ABICALLS && !TARGET_NEWABI \
1787 ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0))
1789 #define RETURN_ADDR_RTX mips_return_addr
1791 /* Since the mips16 ISA mode is encoded in the least-significant bit
1792 of the address, mask it off return addresses for purposes of
1793 finding exception handling regions. */
1795 #define MASK_RETURN_ADDR GEN_INT (-2)
1798 /* Similarly, don't use the least-significant bit to tell pointers to
1799 code from vtable index. */
1801 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
1803 /* The eliminations to $17 are only used for mips16 code. See the
1804 definition of HARD_FRAME_POINTER_REGNUM. */
1806 #define ELIMINABLE_REGS \
1807 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1808 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
1809 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
1810 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1811 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
1812 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
1814 /* We can always eliminate to the hard frame pointer. We can eliminate
1815 to the stack pointer unless a frame pointer is needed.
1817 In mips16 mode, we need a frame pointer for a large frame; otherwise,
1818 reload may be unable to compute the address of a local variable,
1819 since there is no way to add a large constant to the stack pointer
1820 without using a temporary register. */
1821 #define CAN_ELIMINATE(FROM, TO) \
1822 ((TO) == HARD_FRAME_POINTER_REGNUM \
1823 || ((TO) == STACK_POINTER_REGNUM && !frame_pointer_needed \
1824 && (!TARGET_MIPS16 \
1825 || compute_frame_size (get_frame_size ()) < 32768)))
1827 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1828 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
1830 /* Allocate stack space for arguments at the beginning of each function. */
1831 #define ACCUMULATE_OUTGOING_ARGS 1
1833 /* The argument pointer always points to the first argument. */
1834 #define FIRST_PARM_OFFSET(FNDECL) 0
1836 /* o32 and o64 reserve stack space for all argument registers. */
1837 #define REG_PARM_STACK_SPACE(FNDECL) \
1839 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) \
1842 /* Define this if it is the responsibility of the caller to
1843 allocate the area reserved for arguments passed in registers.
1844 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
1845 of this macro is to determine whether the space is included in
1846 `current_function_outgoing_args_size'. */
1847 #define OUTGOING_REG_PARM_STACK_SPACE
1849 #define STACK_BOUNDARY (TARGET_NEWABI ? 128 : 64)
1851 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1853 /* Symbolic macros for the registers used to return integer and floating
1856 #define GP_RETURN (GP_REG_FIRST + 2)
1857 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
1859 #define MAX_ARGS_IN_REGISTERS (TARGET_OLDABI ? 4 : 8)
1861 /* Symbolic macros for the first/last argument registers. */
1863 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
1864 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
1865 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
1866 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
1868 #define LIBCALL_VALUE(MODE) \
1869 mips_function_value (NULL_TREE, NULL, (MODE))
1871 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1872 mips_function_value ((VALTYPE), (FUNC), VOIDmode)
1874 /* 1 if N is a possible register number for a function value.
1875 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
1876 Currently, R2 and F0 are only implemented here (C has no complex type) */
1878 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN \
1879 || (LONG_DOUBLE_TYPE_SIZE == 128 && FP_RETURN != GP_RETURN \
1880 && (N) == FP_RETURN + 2))
1882 /* 1 if N is a possible register number for function argument passing.
1883 We have no FP argument registers when soft-float. When FP registers
1884 are 32 bits, we can't directly reference the odd numbered ones. */
1886 #define FUNCTION_ARG_REGNO_P(N) \
1887 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \
1888 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST))) \
1891 /* This structure has to cope with two different argument allocation
1892 schemes. Most MIPS ABIs view the arguments as a structure, of which
1893 the first N words go in registers and the rest go on the stack. If I
1894 < N, the Ith word might go in Ith integer argument register or in a
1895 floating-point register. For these ABIs, we only need to remember
1896 the offset of the current argument into the structure.
1898 The EABI instead allocates the integer and floating-point arguments
1899 separately. The first N words of FP arguments go in FP registers,
1900 the rest go on the stack. Likewise, the first N words of the other
1901 arguments go in integer registers, and the rest go on the stack. We
1902 need to maintain three counts: the number of integer registers used,
1903 the number of floating-point registers used, and the number of words
1904 passed on the stack.
1906 We could keep separate information for the two ABIs (a word count for
1907 the standard ABIs, and three separate counts for the EABI). But it
1908 seems simpler to view the standard ABIs as forms of EABI that do not
1909 allocate floating-point registers.
1911 So for the standard ABIs, the first N words are allocated to integer
1912 registers, and function_arg decides on an argument-by-argument basis
1913 whether that argument should really go in an integer register, or in
1914 a floating-point one. */
1916 typedef struct mips_args {
1917 /* Always true for varargs functions. Otherwise true if at least
1918 one argument has been passed in an integer register. */
1921 /* The number of arguments seen so far. */
1922 unsigned int arg_number;
1924 /* The number of integer registers used so far. For all ABIs except
1925 EABI, this is the number of words that have been added to the
1926 argument structure, limited to MAX_ARGS_IN_REGISTERS. */
1927 unsigned int num_gprs;
1929 /* For EABI, the number of floating-point registers used so far. */
1930 unsigned int num_fprs;
1932 /* The number of words passed on the stack. */
1933 unsigned int stack_words;
1935 /* On the mips16, we need to keep track of which floating point
1936 arguments were passed in general registers, but would have been
1937 passed in the FP regs if this were a 32 bit function, so that we
1938 can move them to the FP regs if we wind up calling a 32 bit
1939 function. We record this information in fp_code, encoded in base
1940 four. A zero digit means no floating point argument, a one digit
1941 means an SFmode argument, and a two digit means a DFmode argument,
1942 and a three digit is not used. The low order digit is the first
1943 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
1944 an SFmode argument. ??? A more sophisticated approach will be
1945 needed if MIPS_ABI != ABI_32. */
1948 /* True if the function has a prototype. */
1952 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1953 for a call to a function whose data type is FNTYPE.
1954 For a library call, FNTYPE is 0. */
1956 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
1957 init_cumulative_args (&CUM, FNTYPE, LIBNAME) \
1959 /* Update the data in CUM to advance over an argument
1960 of mode MODE and data type TYPE.
1961 (TYPE is null for libcalls where that information may not be available.) */
1963 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1964 function_arg_advance (&CUM, MODE, TYPE, NAMED)
1966 /* Determine where to put an argument to a function.
1967 Value is zero to push the argument on the stack,
1968 or a hard register in which to store the argument.
1970 MODE is the argument's machine mode.
1971 TYPE is the data type of the argument (as a tree).
1972 This is null for libcalls where that information may
1974 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1975 the preceding args and about the function being called.
1976 NAMED is nonzero if this argument is a named parameter
1977 (otherwise it is an extra parameter matching an ellipsis). */
1979 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1980 function_arg( &CUM, MODE, TYPE, NAMED)
1982 #define FUNCTION_ARG_BOUNDARY function_arg_boundary
1984 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
1985 (mips_pad_arg_upward (MODE, TYPE) ? upward : downward)
1987 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
1988 (mips_pad_reg_upward (MODE, TYPE) ? upward : downward)
1990 /* True if using EABI and varargs can be passed in floating-point
1991 registers. Under these conditions, we need a more complex form
1992 of va_list, which tracks GPR, FPR and stack arguments separately. */
1993 #define EABI_FLOAT_VARARGS_P \
1994 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
1997 /* Say that the epilogue uses the return address register. Note that
1998 in the case of sibcalls, the values "used by the epilogue" are
1999 considered live at the start of the called function. */
2000 #define EPILOGUE_USES(REGNO) ((REGNO) == 31)
2002 /* Treat LOC as a byte offset from the stack pointer and round it up
2003 to the next fully-aligned offset. */
2004 #define MIPS_STACK_ALIGN(LOC) \
2005 (TARGET_NEWABI ? ((LOC) + 15) & -16 : ((LOC) + 7) & -8)
2008 /* Implement `va_start' for varargs and stdarg. */
2009 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
2010 mips_va_start (valist, nextarg)
2012 /* Output assembler code to FILE to increment profiler label # LABELNO
2013 for profiling a function entry. */
2015 #define FUNCTION_PROFILER(FILE, LABELNO) \
2017 if (TARGET_MIPS16) \
2018 sorry ("mips16 function profiling"); \
2019 fprintf (FILE, "\t.set\tnoat\n"); \
2020 fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \
2021 reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \
2022 if (!TARGET_NEWABI) \
2025 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \
2026 TARGET_64BIT ? "dsubu" : "subu", \
2027 reg_names[STACK_POINTER_REGNUM], \
2028 reg_names[STACK_POINTER_REGNUM], \
2029 Pmode == DImode ? 16 : 8); \
2031 fprintf (FILE, "\tjal\t_mcount\n"); \
2032 fprintf (FILE, "\t.set\tat\n"); \
2035 /* No mips port has ever used the profiler counter word, so don't emit it
2036 or the label for it. */
2038 #define NO_PROFILE_COUNTERS 1
2040 /* Define this macro if the code for function profiling should come
2041 before the function prologue. Normally, the profiling code comes
2044 /* #define PROFILE_BEFORE_PROLOGUE */
2046 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2047 the stack pointer does not matter. The value is tested only in
2048 functions that have frame pointers.
2049 No definition is equivalent to always zero. */
2051 #define EXIT_IGNORE_STACK 1
2054 /* A C statement to output, on the stream FILE, assembler code for a
2055 block of data that contains the constant parts of a trampoline.
2056 This code should not include a label--the label is taken care of
2059 #define TRAMPOLINE_TEMPLATE(STREAM) \
2061 if (ptr_mode == DImode) \
2062 fprintf (STREAM, "\t.word\t0x03e0082d\t\t# dmove $1,$31\n"); \
2064 fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \
2065 fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \
2066 fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \
2067 if (ptr_mode == DImode) \
2069 fprintf (STREAM, "\t.word\t0xdfe30014\t\t# ld $3,20($31)\n"); \
2070 fprintf (STREAM, "\t.word\t0xdfe2001c\t\t# ld $2,28($31)\n"); \
2071 fprintf (STREAM, "\t.word\t0x0060c82d\t\t# dmove $25,$3\n"); \
2075 fprintf (STREAM, "\t.word\t0x8fe30014\t\t# lw $3,20($31)\n"); \
2076 fprintf (STREAM, "\t.word\t0x8fe20018\t\t# lw $2,24($31)\n"); \
2077 fprintf (STREAM, "\t.word\t0x0060c821\t\t# move $25,$3\n"); \
2079 fprintf (STREAM, "\t.word\t0x00600008\t\t# jr $3\n"); \
2080 if (ptr_mode == DImode) \
2082 fprintf (STREAM, "\t.word\t0x0020f82d\t\t# dmove $31,$1\n"); \
2083 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \
2084 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \
2088 fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \
2089 fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
2090 fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
2094 /* A C expression for the size in bytes of the trampoline, as an
2097 #define TRAMPOLINE_SIZE (32 + GET_MODE_SIZE (ptr_mode) * 2)
2099 /* Alignment required for trampolines, in bits. */
2101 #define TRAMPOLINE_ALIGNMENT GET_MODE_BITSIZE (ptr_mode)
2103 /* INITIALIZE_TRAMPOLINE calls this library function to flush
2104 program and data caches. */
2106 #ifndef CACHE_FLUSH_FUNC
2107 #define CACHE_FLUSH_FUNC "_flush_cache"
2110 /* A C statement to initialize the variable parts of a trampoline.
2111 ADDR is an RTX for the address of the trampoline; FNADDR is an
2112 RTX for the address of the nested function; STATIC_CHAIN is an
2113 RTX for the static chain value that should be passed to the
2114 function when it is called. */
2116 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
2118 rtx func_addr, chain_addr; \
2120 func_addr = plus_constant (ADDR, 32); \
2121 chain_addr = plus_constant (func_addr, GET_MODE_SIZE (ptr_mode)); \
2122 emit_move_insn (gen_rtx_MEM (ptr_mode, func_addr), FUNC); \
2123 emit_move_insn (gen_rtx_MEM (ptr_mode, chain_addr), CHAIN); \
2125 /* Flush both caches. We need to flush the data cache in case \
2126 the system has a write-back cache. */ \
2127 /* ??? Should check the return value for errors. */ \
2128 if (mips_cache_flush_func && mips_cache_flush_func[0]) \
2129 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
2130 0, VOIDmode, 3, ADDR, Pmode, \
2131 GEN_INT (TRAMPOLINE_SIZE), TYPE_MODE (integer_type_node),\
2132 GEN_INT (3), TYPE_MODE (integer_type_node)); \
2135 /* Addressing modes, and classification of registers for them. */
2137 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
2138 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2139 mips_regno_mode_ok_for_base_p (REGNO, MODE, 1)
2141 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2142 and check its validity for a certain class.
2143 We have two alternate definitions for each of them.
2144 The usual definition accepts all pseudo regs; the other rejects them all.
2145 The symbol REG_OK_STRICT causes the latter definition to be used.
2147 Most source files want to accept pseudo regs in the hope that
2148 they will get allocated to the class that the insn wants them to be in.
2149 Some source files that are used after register allocation
2150 need to be strict. */
2152 #ifndef REG_OK_STRICT
2153 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2154 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 0)
2156 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2157 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 1)
2160 #define REG_OK_FOR_INDEX_P(X) 0
2163 /* Maximum number of registers that can appear in a valid memory address. */
2165 #define MAX_REGS_PER_ADDRESS 1
2167 #ifdef REG_OK_STRICT
2168 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2170 if (mips_legitimate_address_p (MODE, X, 1)) \
2174 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2176 if (mips_legitimate_address_p (MODE, X, 0)) \
2181 /* Check for constness inline but use mips_legitimate_address_p
2182 to check whether a constant really is an address. */
2184 #define CONSTANT_ADDRESS_P(X) \
2185 (CONSTANT_P (X) && mips_legitimate_address_p (SImode, X, 0))
2187 #define LEGITIMATE_CONSTANT_P(X) (mips_const_insns (X) > 0)
2189 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2191 if (mips_legitimize_address (&(X), MODE)) \
2196 /* A C statement or compound statement with a conditional `goto
2197 LABEL;' executed if memory address X (an RTX) can have different
2198 meanings depending on the machine mode of the memory reference it
2201 Autoincrement and autodecrement addresses typically have
2202 mode-dependent effects because the amount of the increment or
2203 decrement is the size of the operand being addressed. Some
2204 machines have other mode-dependent addresses. Many RISC machines
2205 have no mode-dependent addresses.
2207 You may assume that ADDR is a valid address for the machine. */
2209 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
2211 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
2212 'the start of the function that this code is output in'. */
2214 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
2215 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
2216 asm_fprintf ((FILE), "%U%s", \
2217 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
2219 asm_fprintf ((FILE), "%U%s", (NAME))
2221 /* Flag to mark a function decl symbol that requires a long call. */
2222 #define SYMBOL_FLAG_LONG_CALL (SYMBOL_FLAG_MACH_DEP << 0)
2223 #define SYMBOL_REF_LONG_CALL_P(X) \
2224 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_LONG_CALL) != 0)
2226 /* Specify the machine mode that this machine uses
2227 for the index in the tablejump instruction.
2228 ??? Using HImode in mips16 mode can cause overflow. */
2229 #define CASE_VECTOR_MODE \
2230 (TARGET_MIPS16 ? HImode : ptr_mode)
2232 /* Define as C expression which evaluates to nonzero if the tablejump
2233 instruction expects the table to contain offsets from the address of the
2235 Do not define this if the table should contain absolute addresses. */
2236 #define CASE_VECTOR_PC_RELATIVE (TARGET_MIPS16)
2238 /* Define this as 1 if `char' should by default be signed; else as 0. */
2239 #ifndef DEFAULT_SIGNED_CHAR
2240 #define DEFAULT_SIGNED_CHAR 1
2243 /* Max number of bytes we can move from memory to memory
2244 in one reasonably fast instruction. */
2245 #define MOVE_MAX (TARGET_64BIT ? 8 : 4)
2246 #define MAX_MOVE_MAX 8
2248 /* Define this macro as a C expression which is nonzero if
2249 accessing less than a word of memory (i.e. a `char' or a
2250 `short') is no faster than accessing a word of memory, i.e., if
2251 such access require more than one instruction or if there is no
2252 difference in cost between byte and (aligned) word loads.
2254 On RISC machines, it tends to generate better code to define
2255 this as 1, since it avoids making a QI or HI mode register. */
2256 #define SLOW_BYTE_ACCESS 1
2258 /* Define this to be nonzero if shift instructions ignore all but the low-order
2260 #define SHIFT_COUNT_TRUNCATED 1
2262 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2263 is done just by pretending it is already truncated. */
2264 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
2265 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
2268 /* Specify the machine mode that pointers have.
2269 After generation of rtl, the compiler makes no further distinction
2270 between pointers and any other objects of this machine mode. */
2273 #define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode)
2276 /* Give call MEMs SImode since it is the "most permissive" mode
2277 for both 32-bit and 64-bit targets. */
2279 #define FUNCTION_MODE SImode
2282 /* The cost of loading values from the constant pool. It should be
2283 larger than the cost of any constant we want to synthesize in-line. */
2285 #define CONSTANT_POOL_COST COSTS_N_INSNS (8)
2287 /* A C expression for the cost of moving data from a register in
2288 class FROM to one in class TO. The classes are expressed using
2289 the enumeration values such as `GENERAL_REGS'. A value of 2 is
2290 the default; other values are interpreted relative to that.
2292 It is not required that the cost always equal 2 when FROM is the
2293 same as TO; on some machines it is expensive to move between
2294 registers if they are not general registers.
2296 If reload sees an insn consisting of a single `set' between two
2297 hard registers, and if `REGISTER_MOVE_COST' applied to their
2298 classes returns a value of 2, reload does not check to ensure
2299 that the constraints of the insn are met. Setting a cost of
2300 other than 2 will allow reload to verify that the constraints are
2301 met. You should do this if the `movM' pattern's constraints do
2302 not allow such copying. */
2304 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
2305 mips_register_move_cost (MODE, FROM, TO)
2307 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
2308 (mips_cost->memory_latency \
2309 + memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
2311 /* Define if copies to/from condition code registers should be avoided.
2313 This is needed for the MIPS because reload_outcc is not complete;
2314 it needs to handle cases where the source is a general or another
2315 condition code register. */
2316 #define AVOID_CCMODE_COPIES
2318 /* A C expression for the cost of a branch instruction. A value of
2319 1 is the default; other values are interpreted relative to that. */
2321 #define BRANCH_COST mips_cost->branch_cost
2322 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
2324 /* If defined, modifies the length assigned to instruction INSN as a
2325 function of the context in which it is used. LENGTH is an lvalue
2326 that contains the initially computed length of the insn and should
2327 be updated with the correct length of the insn. */
2328 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
2329 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
2331 /* Return the asm template for a non-MIPS16 conditional branch instruction.
2332 OPCODE is the opcode's mnemonic and OPERANDS is the asm template for
2334 #define MIPS_BRANCH(OPCODE, OPERANDS) \
2335 "%*" OPCODE "%?\t" OPERANDS "%/"
2337 /* Return the asm template for a call. INSN is the instruction's mnemonic
2338 ("j" or "jal"), OPERANDS are its operands, and OPNO is the operand number
2341 When generating -mabicalls without explicit relocation operators,
2342 all calls should use assembly macros. Otherwise, all indirect
2343 calls should use "jr" or "jalr"; we will arrange to restore $gp
2344 afterwards if necessary. Finally, we can only generate direct
2345 calls for -mabicalls by temporarily switching to non-PIC mode. */
2346 #define MIPS_CALL(INSN, OPERANDS, OPNO) \
2347 (TARGET_ABICALLS && !TARGET_EXPLICIT_RELOCS \
2348 ? "%*" INSN "\t%" #OPNO "%/" \
2349 : REG_P (OPERANDS[OPNO]) \
2350 ? "%*" INSN "r\t%" #OPNO "%/" \
2352 ? (".option\tpic0\n\t" \
2353 "%*" INSN "\t%" #OPNO "%/\n\t" \
2355 : "%*" INSN "\t%" #OPNO "%/")
2357 /* Control the assembler format that we output. */
2359 /* Output to assembler file text saying following lines
2360 may contain character constants, extra white space, comments, etc. */
2363 #define ASM_APP_ON " #APP\n"
2366 /* Output to assembler file text saying following lines
2367 no longer contain unusual constructs. */
2370 #define ASM_APP_OFF " #NO_APP\n"
2373 #define REGISTER_NAMES \
2374 { "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", \
2375 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", \
2376 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \
2377 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31", \
2378 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
2379 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
2380 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
2381 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
2382 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
2383 "$fcc5","$fcc6","$fcc7","", "", "$arg", "$frame", "$fakec", \
2384 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7", \
2385 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15", \
2386 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23", \
2387 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31", \
2388 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7", \
2389 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15", \
2390 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23", \
2391 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31", \
2392 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7", \
2393 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15", \
2394 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23", \
2395 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31", \
2396 "$ac1hi","$ac1lo","$ac2hi","$ac2lo","$ac3hi","$ac3lo","$dsp_po","$dsp_sc", \
2397 "$dsp_ca","$dsp_ou","$dsp_cc","$dsp_ef" }
2399 /* List the "software" names for each register. Also list the numerical
2400 names for $fp and $sp. */
2402 #define ADDITIONAL_REGISTER_NAMES \
2404 { "$29", 29 + GP_REG_FIRST }, \
2405 { "$30", 30 + GP_REG_FIRST }, \
2406 { "at", 1 + GP_REG_FIRST }, \
2407 { "v0", 2 + GP_REG_FIRST }, \
2408 { "v1", 3 + GP_REG_FIRST }, \
2409 { "a0", 4 + GP_REG_FIRST }, \
2410 { "a1", 5 + GP_REG_FIRST }, \
2411 { "a2", 6 + GP_REG_FIRST }, \
2412 { "a3", 7 + GP_REG_FIRST }, \
2413 { "t0", 8 + GP_REG_FIRST }, \
2414 { "t1", 9 + GP_REG_FIRST }, \
2415 { "t2", 10 + GP_REG_FIRST }, \
2416 { "t3", 11 + GP_REG_FIRST }, \
2417 { "t4", 12 + GP_REG_FIRST }, \
2418 { "t5", 13 + GP_REG_FIRST }, \
2419 { "t6", 14 + GP_REG_FIRST }, \
2420 { "t7", 15 + GP_REG_FIRST }, \
2421 { "s0", 16 + GP_REG_FIRST }, \
2422 { "s1", 17 + GP_REG_FIRST }, \
2423 { "s2", 18 + GP_REG_FIRST }, \
2424 { "s3", 19 + GP_REG_FIRST }, \
2425 { "s4", 20 + GP_REG_FIRST }, \
2426 { "s5", 21 + GP_REG_FIRST }, \
2427 { "s6", 22 + GP_REG_FIRST }, \
2428 { "s7", 23 + GP_REG_FIRST }, \
2429 { "t8", 24 + GP_REG_FIRST }, \
2430 { "t9", 25 + GP_REG_FIRST }, \
2431 { "k0", 26 + GP_REG_FIRST }, \
2432 { "k1", 27 + GP_REG_FIRST }, \
2433 { "gp", 28 + GP_REG_FIRST }, \
2434 { "sp", 29 + GP_REG_FIRST }, \
2435 { "fp", 30 + GP_REG_FIRST }, \
2436 { "ra", 31 + GP_REG_FIRST }, \
2437 ALL_COP_ADDITIONAL_REGISTER_NAMES \
2440 /* This is meant to be redefined in the host dependent files. It is a
2441 set of alternative names and regnums for mips coprocessors. */
2443 #define ALL_COP_ADDITIONAL_REGISTER_NAMES
2445 /* A C compound statement to output to stdio stream STREAM the
2446 assembler syntax for an instruction operand X. X is an RTL
2449 CODE is a value that can be used to specify one of several ways
2450 of printing the operand. It is used when identical operands
2451 must be printed differently depending on the context. CODE
2452 comes from the `%' specification that was used to request
2453 printing of the operand. If the specification was just `%DIGIT'
2454 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
2455 is the ASCII code for LTR.
2457 If X is a register, this macro should print the register's name.
2458 The names can be found in an array `reg_names' whose type is
2459 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
2461 When the machine description has a specification `%PUNCT' (a `%'
2462 followed by a punctuation character), this macro is called with
2463 a null pointer for X and the punctuation character for CODE.
2465 See mips.c for the MIPS specific codes. */
2467 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2469 /* A C expression which evaluates to true if CODE is a valid
2470 punctuation character for use in the `PRINT_OPERAND' macro. If
2471 `PRINT_OPERAND_PUNCT_VALID_P' is not defined, it means that no
2472 punctuation characters (except for the standard one, `%') are
2473 used in this way. */
2475 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
2477 /* A C compound statement to output to stdio stream STREAM the
2478 assembler syntax for an instruction operand that is a memory
2479 reference whose address is ADDR. ADDR is an RTL expression. */
2481 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
2484 /* A C statement, to be executed after all slot-filler instructions
2485 have been output. If necessary, call `dbr_sequence_length' to
2486 determine the number of slots filled in a sequence (zero if not
2487 currently outputting a sequence), to decide how many no-ops to
2488 output, or whatever.
2490 Don't define this macro if it has nothing to do, but it is
2491 helpful in reading assembly output if the extent of the delay
2492 sequence is made explicit (e.g. with white space).
2494 Note that output routines for instructions with delay slots must
2495 be prepared to deal with not being output as part of a sequence
2496 (i.e. when the scheduling pass is not run, or when no slot
2497 fillers could be found.) The variable `final_sequence' is null
2498 when not processing a sequence, otherwise it contains the
2499 `sequence' rtx being output. */
2501 #define DBR_OUTPUT_SEQEND(STREAM) \
2504 if (set_nomacro > 0 && --set_nomacro == 0) \
2505 fputs ("\t.set\tmacro\n", STREAM); \
2507 if (set_noreorder > 0 && --set_noreorder == 0) \
2508 fputs ("\t.set\treorder\n", STREAM); \
2510 fputs ("\n", STREAM); \
2515 /* How to tell the debugger about changes of source files. */
2516 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
2517 mips_output_filename (STREAM, NAME)
2519 /* mips-tfile does not understand .stabd directives. */
2520 #define DBX_OUTPUT_SOURCE_LINE(STREAM, LINE, COUNTER) do { \
2521 dbxout_begin_stabn_sline (LINE); \
2522 dbxout_stab_value_internal_label ("LM", &COUNTER); \
2525 /* Use .loc directives for SDB line numbers. */
2526 #define SDB_OUTPUT_SOURCE_LINE(STREAM, LINE) \
2527 fprintf (STREAM, "\t.loc\t%d %d\n", num_source_filenames, LINE)
2529 /* The MIPS implementation uses some labels for its own purpose. The
2530 following lists what labels are created, and are all formed by the
2531 pattern $L[a-z].*. The machine independent portion of GCC creates
2532 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
2534 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
2535 $Lb[0-9]+ Begin blocks for MIPS debug support
2536 $Lc[0-9]+ Label for use in s<xx> operation.
2537 $Le[0-9]+ End blocks for MIPS debug support */
2539 #undef ASM_DECLARE_OBJECT_NAME
2540 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
2541 mips_declare_object (STREAM, NAME, "", ":\n", 0)
2543 /* Globalizing directive for a label. */
2544 #define GLOBAL_ASM_OP "\t.globl\t"
2546 /* This says how to define a global common symbol. */
2548 #define ASM_OUTPUT_ALIGNED_DECL_COMMON mips_output_aligned_decl_common
2550 /* This says how to define a local common symbol (i.e., not visible to
2553 #ifndef ASM_OUTPUT_ALIGNED_LOCAL
2554 #define ASM_OUTPUT_ALIGNED_LOCAL(STREAM, NAME, SIZE, ALIGN) \
2555 mips_declare_common_object (STREAM, NAME, "\n\t.lcomm\t", SIZE, ALIGN, false)
2558 /* This says how to output an external. It would be possible not to
2559 output anything and let undefined symbol become external. However
2560 the assembler uses length information on externals to allocate in
2561 data/sdata bss/sbss, thereby saving exec time. */
2563 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
2564 mips_output_external(STREAM,DECL,NAME)
2566 /* This is how to declare a function name. The actual work of
2567 emitting the label is moved to function_prologue, so that we can
2568 get the line number correctly emitted before the .ent directive,
2569 and after any .file directives. Define as empty so that the function
2570 is not declared before the .ent directive elsewhere. */
2572 #undef ASM_DECLARE_FUNCTION_NAME
2573 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
2575 #ifndef FUNCTION_NAME_ALREADY_DECLARED
2576 #define FUNCTION_NAME_ALREADY_DECLARED 0
2579 /* This is how to store into the string LABEL
2580 the symbol_ref name of an internal numbered label where
2581 PREFIX is the class of label and NUM is the number within the class.
2582 This is suitable for output with `assemble_name'. */
2584 #undef ASM_GENERATE_INTERNAL_LABEL
2585 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2586 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
2588 /* This is how to output an element of a case-vector that is absolute. */
2590 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
2591 fprintf (STREAM, "\t%s\t%sL%d\n", \
2592 ptr_mode == DImode ? ".dword" : ".word", \
2593 LOCAL_LABEL_PREFIX, \
2596 /* This is how to output an element of a case-vector. We can make the
2597 entries PC-relative in MIPS16 code and GP-relative when .gp(d)word
2600 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
2602 if (TARGET_MIPS16) \
2603 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
2604 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
2605 else if (TARGET_GPWORD) \
2606 fprintf (STREAM, "\t%s\t%sL%d\n", \
2607 ptr_mode == DImode ? ".gpdword" : ".gpword", \
2608 LOCAL_LABEL_PREFIX, VALUE); \
2610 fprintf (STREAM, "\t%s\t%sL%d\n", \
2611 ptr_mode == DImode ? ".dword" : ".word", \
2612 LOCAL_LABEL_PREFIX, VALUE); \
2615 /* When generating MIPS16 code, we want the jump table to be in the text
2616 section so that we can load its address using a PC-relative addition. */
2617 #define JUMP_TABLES_IN_TEXT_SECTION TARGET_MIPS16
2619 /* This is how to output an assembler line
2620 that says to advance the location counter
2621 to a multiple of 2**LOG bytes. */
2623 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
2624 fprintf (STREAM, "\t.align\t%d\n", (LOG))
2626 /* This is how to output an assembler line to advance the location
2627 counter by SIZE bytes. */
2629 #undef ASM_OUTPUT_SKIP
2630 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
2631 fprintf (STREAM, "\t.space\t"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
2633 /* This is how to output a string. */
2634 #undef ASM_OUTPUT_ASCII
2635 #define ASM_OUTPUT_ASCII(STREAM, STRING, LEN) \
2636 mips_output_ascii (STREAM, STRING, LEN, "\t.ascii\t")
2638 /* Output #ident as a in the read-only data section. */
2639 #undef ASM_OUTPUT_IDENT
2640 #define ASM_OUTPUT_IDENT(FILE, STRING) \
2642 const char *p = STRING; \
2643 int size = strlen (p) + 1; \
2644 switch_to_section (readonly_data_section); \
2645 assemble_string (p, size); \
2648 /* Default to -G 8 */
2649 #ifndef MIPS_DEFAULT_GVALUE
2650 #define MIPS_DEFAULT_GVALUE 8
2653 /* Define the strings to put out for each section in the object file. */
2654 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
2655 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
2657 #undef READONLY_DATA_SECTION_ASM_OP
2658 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
2660 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
2663 fprintf (STREAM, "\t%s\t%s,%s,8\n\t%s\t%s,0(%s)\n", \
2664 TARGET_64BIT ? "dsubu" : "subu", \
2665 reg_names[STACK_POINTER_REGNUM], \
2666 reg_names[STACK_POINTER_REGNUM], \
2667 TARGET_64BIT ? "sd" : "sw", \
2669 reg_names[STACK_POINTER_REGNUM]); \
2673 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
2676 if (! set_noreorder) \
2677 fprintf (STREAM, "\t.set\tnoreorder\n"); \
2679 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
2680 TARGET_64BIT ? "ld" : "lw", \
2682 reg_names[STACK_POINTER_REGNUM], \
2683 TARGET_64BIT ? "daddu" : "addu", \
2684 reg_names[STACK_POINTER_REGNUM], \
2685 reg_names[STACK_POINTER_REGNUM]); \
2687 if (! set_noreorder) \
2688 fprintf (STREAM, "\t.set\treorder\n"); \
2692 /* How to start an assembler comment.
2693 The leading space is important (the mips native assembler requires it). */
2694 #ifndef ASM_COMMENT_START
2695 #define ASM_COMMENT_START " #"
2698 /* Default definitions for size_t and ptrdiff_t. We must override the
2699 definitions from ../svr4.h on mips-*-linux-gnu. */
2702 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
2705 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
2708 /* Since the bits of the _init and _fini function is spread across
2709 many object files, each potentially with its own GP, we must assume
2710 we need to load our GP. We don't preserve $gp or $ra, since each
2711 init/fini chunk is supposed to initialize $gp, and crti/crtn
2712 already take care of preserving $ra and, when appropriate, $gp. */
2713 #if (defined _ABIO32 && _MIPS_SIM == _ABIO32)
2714 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2715 asm (SECTION_OP "\n\
2721 jal " USER_LABEL_PREFIX #FUNC "\n\
2722 " TEXT_SECTION_ASM_OP);
2723 #endif /* Switch to #elif when we're no longer limited by K&R C. */
2724 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
2725 || (defined _ABI64 && _MIPS_SIM == _ABI64)
2726 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2727 asm (SECTION_OP "\n\
2732 .cpsetup $31, $2, 1b\n\
2733 jal " USER_LABEL_PREFIX #FUNC "\n\
2734 " TEXT_SECTION_ASM_OP);
2739 #define HAVE_AS_TLS 0
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