contrib/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp

   1 //===-- ARMMCTargetDesc.cpp - ARM Target Descriptions ---------------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file provides ARM specific target descriptions.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "ARMBaseInfo.h"
  15 #include "ARMELFStreamer.h"
  16 #include "ARMMCAsmInfo.h"
  17 #include "ARMMCTargetDesc.h"
  18 #include "InstPrinter/ARMInstPrinter.h"
  19 #include "llvm/ADT/Triple.h"
  20 #include "llvm/MC/MCCodeGenInfo.h"
  21 #include "llvm/MC/MCInstrAnalysis.h"
  22 #include "llvm/MC/MCInstrInfo.h"
  23 #include "llvm/MC/MCRegisterInfo.h"
  24 #include "llvm/MC/MCStreamer.h"
  25 #include "llvm/MC/MCSubtargetInfo.h"
  26 #include "llvm/Support/ErrorHandling.h"
  27 #include "llvm/Support/TargetRegistry.h"
  28
  29 #define GET_REGINFO_MC_DESC
  30 #include "ARMGenRegisterInfo.inc"
  31
  32 #define GET_INSTRINFO_MC_DESC
  33 #include "ARMGenInstrInfo.inc"
  34
  35 #define GET_SUBTARGETINFO_MC_DESC
  36 #include "ARMGenSubtargetInfo.inc"
  37
  38 using namespace llvm;
  39
  40 std::string ARM_MC::ParseARMTriple(StringRef TT, StringRef CPU) {
  41   Triple triple(TT);
  42
  43   // Set the boolean corresponding to the current target triple, or the default
  44   // if one cannot be determined, to true.
  45   unsigned Len = TT.size();
  46   unsigned Idx = 0;
  47
  48   // FIXME: Enhance Triple helper class to extract ARM version.
  49   bool isThumb = false;
  50   if (Len >= 5 && TT.substr(0, 4) == "armv")
  51     Idx = 4;
  52   else if (Len >= 6 && TT.substr(0, 5) == "thumb") {
  53     isThumb = true;
  54     if (Len >= 7 && TT[5] == 'v')
  55       Idx = 6;
  56   }
  57
  58   bool NoCPU = CPU == "generic" || CPU.empty();
  59   std::string ARMArchFeature;
  60   if (Idx) {
  61     unsigned SubVer = TT[Idx];
  62     if (SubVer >= '7' && SubVer <= '9') {
  63       if (Len >= Idx+2 && TT[Idx+1] == 'm') {
  64         if (NoCPU)
  65           // v7m: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureMClass
  66           ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+mclass";
  67         else
  68           // Use CPU to figure out the exact features.
  69           ARMArchFeature = "+v7";
  70       } else if (Len >= Idx+3 && TT[Idx+1] == 'e'&& TT[Idx+2] == 'm') {
  71         if (NoCPU)
  72           // v7em: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureDSPThumb2,
  73           //       FeatureT2XtPk, FeatureMClass
  74           ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+t2dsp,t2xtpk,+mclass";
  75         else
  76           // Use CPU to figure out the exact features.
  77           ARMArchFeature = "+v7";
  78       } else if (Len >= Idx+2 && TT[Idx+1] == 's') {
  79         if (NoCPU)
  80           // v7s: FeatureNEON, FeatureDB, FeatureDSPThumb2, FeatureT2XtPk
  81           //      Swift
  82           ARMArchFeature = "+v7,+swift,+neon,+db,+t2dsp,+t2xtpk";
  83         else
  84           // Use CPU to figure out the exact features.
  85           ARMArchFeature = "+v7";
  86       } else {
  87         // v7 CPUs have lots of different feature sets. If no CPU is specified,
  88         // then assume v7a (e.g. cortex-a8) feature set. Otherwise, return
  89         // the "minimum" feature set and use CPU string to figure out the exact
  90         // features.
  91         if (NoCPU)
  92           // v7a: FeatureNEON, FeatureDB, FeatureDSPThumb2, FeatureT2XtPk
  93           ARMArchFeature = "+v7,+neon,+db,+t2dsp,+t2xtpk";
  94         else
  95           // Use CPU to figure out the exact features.
  96           ARMArchFeature = "+v7";
  97       }
  98     } else if (SubVer == '6') {
  99       if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == '2')
 100         ARMArchFeature = "+v6t2";
 101       else if (Len >= Idx+2 && TT[Idx+1] == 'm') {
 102         if (NoCPU)
 103           // v6m: FeatureNoARM, FeatureMClass
 104           ARMArchFeature = "+v6,+noarm,+mclass";
 105         else
 106           ARMArchFeature = "+v6";
 107       } else
 108         ARMArchFeature = "+v6";
 109     } else if (SubVer == '5') {
 110       if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == 'e')
 111         ARMArchFeature = "+v5te";
 112       else
 113         ARMArchFeature = "+v5t";
 114     } else if (SubVer == '4' && Len >= Idx+2 && TT[Idx+1] == 't')
 115       ARMArchFeature = "+v4t";
 116   }
 117
 118   if (isThumb) {
 119     if (ARMArchFeature.empty())
 120       ARMArchFeature = "+thumb-mode";
 121     else
 122       ARMArchFeature += ",+thumb-mode";
 123   }
 124
 125   if (triple.isOSNaCl()) {
 126     if (ARMArchFeature.empty())
 127       ARMArchFeature = "+nacl-trap";
 128     else
 129       ARMArchFeature += ",+nacl-trap";
 130   }
 131
 132   return ARMArchFeature;
 133 }
 134
 135 MCSubtargetInfo *ARM_MC::createARMMCSubtargetInfo(StringRef TT, StringRef CPU,
 136                                                   StringRef FS) {
 137   std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU);
 138   if (!FS.empty()) {
 139     if (!ArchFS.empty())
 140       ArchFS = ArchFS + "," + FS.str();
 141     else
 142       ArchFS = FS;
 143   }
 144
 145   MCSubtargetInfo *X = new MCSubtargetInfo();
 146   InitARMMCSubtargetInfo(X, TT, CPU, ArchFS);
 147   return X;
 148 }
 149
 150 static MCInstrInfo *createARMMCInstrInfo() {
 151   MCInstrInfo *X = new MCInstrInfo();
 152   InitARMMCInstrInfo(X);
 153   return X;
 154 }
 155
 156 static MCRegisterInfo *createARMMCRegisterInfo(StringRef Triple) {
 157   MCRegisterInfo *X = new MCRegisterInfo();
 158   InitARMMCRegisterInfo(X, ARM::LR, 0, 0, ARM::PC);
 159   return X;
 160 }
 161
 162 static MCAsmInfo *createARMMCAsmInfo(const Target &T, StringRef TT) {
 163   Triple TheTriple(TT);
 164
 165   if (TheTriple.isOSDarwin())
 166     return new ARMMCAsmInfoDarwin();
 167
 168   return new ARMELFMCAsmInfo();
 169 }
 170
 171 static MCCodeGenInfo *createARMMCCodeGenInfo(StringRef TT, Reloc::Model RM,
 172                                              CodeModel::Model CM,
 173                                              CodeGenOpt::Level OL) {
 174   MCCodeGenInfo *X = new MCCodeGenInfo();
 175   if (RM == Reloc::Default) {
 176     Triple TheTriple(TT);
 177     // Default relocation model on Darwin is PIC, not DynamicNoPIC.
 178     RM = TheTriple.isOSDarwin() ? Reloc::PIC_ : Reloc::DynamicNoPIC;
 179   }
 180   X->InitMCCodeGenInfo(RM, CM, OL);
 181   return X;
 182 }
 183
 184 // This is duplicated code. Refactor this.
 185 static MCStreamer *createMCStreamer(const Target &T, StringRef TT,
 186                                     MCContext &Ctx, MCAsmBackend &MAB,
 187                                     raw_ostream &OS,
 188                                     MCCodeEmitter *Emitter,
 189                                     bool RelaxAll,
 190                                     bool NoExecStack) {
 191   Triple TheTriple(TT);
 192
 193   if (TheTriple.isOSDarwin())
 194     return createMachOStreamer(Ctx, MAB, OS, Emitter, false);
 195
 196   if (TheTriple.isOSWindows()) {
 197     llvm_unreachable("ARM does not support Windows COFF format");
 198   }
 199
 200   return createARMELFStreamer(Ctx, MAB, OS, Emitter, false, NoExecStack,
 201                               TheTriple.getArch() == Triple::thumb);
 202 }
 203
 204 static MCInstPrinter *createARMMCInstPrinter(const Target &T,
 205                                              unsigned SyntaxVariant,
 206                                              const MCAsmInfo &MAI,
 207                                              const MCInstrInfo &MII,
 208                                              const MCRegisterInfo &MRI,
 209                                              const MCSubtargetInfo &STI) {
 210   if (SyntaxVariant == 0)
 211     return new ARMInstPrinter(MAI, MII, MRI, STI);
 212   return 0;
 213 }
 214
 215 namespace {
 216
 217 class ARMMCInstrAnalysis : public MCInstrAnalysis {
 218 public:
 219   ARMMCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {}
 220
 221   virtual bool isUnconditionalBranch(const MCInst &Inst) const {
 222     // BCCs with the "always" predicate are unconditional branches.
 223     if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
 224       return true;
 225     return MCInstrAnalysis::isUnconditionalBranch(Inst);
 226   }
 227
 228   virtual bool isConditionalBranch(const MCInst &Inst) const {
 229     // BCCs with the "always" predicate are unconditional branches.
 230     if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
 231       return false;
 232     return MCInstrAnalysis::isConditionalBranch(Inst);
 233   }
 234
 235   uint64_t evaluateBranch(const MCInst &Inst, uint64_t Addr,
 236                           uint64_t Size) const {
 237     // We only handle PCRel branches for now.
 238     if (Info->get(Inst.getOpcode()).OpInfo[0].OperandType!=MCOI::OPERAND_PCREL)
 239       return -1ULL;
 240
 241     int64_t Imm = Inst.getOperand(0).getImm();
 242     // FIXME: This is not right for thumb.
 243     return Addr+Imm+8; // In ARM mode the PC is always off by 8 bytes.
 244   }
 245 };
 246
 247 }
 248
 249 static MCInstrAnalysis *createARMMCInstrAnalysis(const MCInstrInfo *Info) {
 250   return new ARMMCInstrAnalysis(Info);
 251 }
 252
 253 // Force static initialization.
 254 extern "C" void LLVMInitializeARMTargetMC() {
 255   // Register the MC asm info.
 256   RegisterMCAsmInfoFn A(TheARMTarget, createARMMCAsmInfo);
 257   RegisterMCAsmInfoFn B(TheThumbTarget, createARMMCAsmInfo);
 258
 259   // Register the MC codegen info.
 260   TargetRegistry::RegisterMCCodeGenInfo(TheARMTarget, createARMMCCodeGenInfo);
 261   TargetRegistry::RegisterMCCodeGenInfo(TheThumbTarget, createARMMCCodeGenInfo);
 262
 263   // Register the MC instruction info.
 264   TargetRegistry::RegisterMCInstrInfo(TheARMTarget, createARMMCInstrInfo);
 265   TargetRegistry::RegisterMCInstrInfo(TheThumbTarget, createARMMCInstrInfo);
 266
 267   // Register the MC register info.
 268   TargetRegistry::RegisterMCRegInfo(TheARMTarget, createARMMCRegisterInfo);
 269   TargetRegistry::RegisterMCRegInfo(TheThumbTarget, createARMMCRegisterInfo);
 270
 271   // Register the MC subtarget info.
 272   TargetRegistry::RegisterMCSubtargetInfo(TheARMTarget,
 273                                           ARM_MC::createARMMCSubtargetInfo);
 274   TargetRegistry::RegisterMCSubtargetInfo(TheThumbTarget,
 275                                           ARM_MC::createARMMCSubtargetInfo);
 276
 277   // Register the MC instruction analyzer.
 278   TargetRegistry::RegisterMCInstrAnalysis(TheARMTarget,
 279                                           createARMMCInstrAnalysis);
 280   TargetRegistry::RegisterMCInstrAnalysis(TheThumbTarget,
 281                                           createARMMCInstrAnalysis);
 282
 283   // Register the MC Code Emitter
 284   TargetRegistry::RegisterMCCodeEmitter(TheARMTarget, createARMMCCodeEmitter);
 285   TargetRegistry::RegisterMCCodeEmitter(TheThumbTarget, createARMMCCodeEmitter);
 286
 287   // Register the asm backend.
 288   TargetRegistry::RegisterMCAsmBackend(TheARMTarget, createARMAsmBackend);
 289   TargetRegistry::RegisterMCAsmBackend(TheThumbTarget, createARMAsmBackend);
 290
 291   // Register the object streamer.
 292   TargetRegistry::RegisterMCObjectStreamer(TheARMTarget, createMCStreamer);
 293   TargetRegistry::RegisterMCObjectStreamer(TheThumbTarget, createMCStreamer);
 294
 295   // Register the MCInstPrinter.
 296   TargetRegistry::RegisterMCInstPrinter(TheARMTarget, createARMMCInstPrinter);
 297   TargetRegistry::RegisterMCInstPrinter(TheThumbTarget, createARMMCInstPrinter);
 298 }