contrib/llvm/lib/Target/Mips/MipsInstrInfo.h

   1 //===-- MipsInstrInfo.h - Mips Instruction Information ----------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the Mips implementation of the TargetInstrInfo class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #ifndef MIPSINSTRUCTIONINFO_H
  15 #define MIPSINSTRUCTIONINFO_H
  16
  17 #include "Mips.h"
  18 #include "MipsAnalyzeImmediate.h"
  19 #include "MipsRegisterInfo.h"
  20 #include "llvm/Support/ErrorHandling.h"
  21 #include "llvm/Target/TargetInstrInfo.h"
  22
  23 #define GET_INSTRINFO_HEADER
  24 #include "MipsGenInstrInfo.inc"
  25
  26 namespace llvm {
  27
  28 class MipsInstrInfo : public MipsGenInstrInfo {
  29 protected:
  30   MipsTargetMachine &TM;
  31   unsigned UncondBrOpc;
  32
  33 public:
  34   enum BranchType {
  35     BT_None,       // Couldn't analyze branch.
  36     BT_NoBranch,   // No branches found.
  37     BT_Uncond,     // One unconditional branch.
  38     BT_Cond,       // One conditional branch.
  39     BT_CondUncond, // A conditional branch followed by an unconditional branch.
  40     BT_Indirect    // One indirct branch.
  41   };
  42
  43   explicit MipsInstrInfo(MipsTargetMachine &TM, unsigned UncondBrOpc);
  44
  45   static const MipsInstrInfo *create(MipsTargetMachine &TM);
  46
  47   /// Branch Analysis
  48   virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
  49                              MachineBasicBlock *&FBB,
  50                              SmallVectorImpl<MachineOperand> &Cond,
  51                              bool AllowModify) const;
  52
  53   virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
  54
  55   virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
  56                                 MachineBasicBlock *FBB,
  57                                 const SmallVectorImpl<MachineOperand> &Cond,
  58                                 DebugLoc DL) const;
  59
  60   virtual
  61   bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
  62
  63   BranchType AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
  64                            MachineBasicBlock *&FBB,
  65                            SmallVectorImpl<MachineOperand> &Cond,
  66                            bool AllowModify,
  67                            SmallVectorImpl<MachineInstr*> &BranchInstrs) const;
  68
  69   virtual MachineInstr* emitFrameIndexDebugValue(MachineFunction &MF,
  70                                                  int FrameIx, uint64_t Offset,
  71                                                  const MDNode *MDPtr,
  72                                                  DebugLoc DL) const;
  73
  74   /// Insert nop instruction when hazard condition is found
  75   virtual void insertNoop(MachineBasicBlock &MBB,
  76                           MachineBasicBlock::iterator MI) const;
  77
  78   /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
  79   /// such, whenever a client has an instance of instruction info, it should
  80   /// always be able to get register info as well (through this method).
  81   ///
  82   virtual const MipsRegisterInfo &getRegisterInfo() const = 0;
  83
  84   virtual unsigned GetOppositeBranchOpc(unsigned Opc) const = 0;
  85
  86   /// Return the number of bytes of code the specified instruction may be.
  87   unsigned GetInstSizeInBytes(const MachineInstr *MI) const;
  88
  89   virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
  90                                    MachineBasicBlock::iterator MBBI,
  91                                    unsigned SrcReg, bool isKill, int FrameIndex,
  92                                    const TargetRegisterClass *RC,
  93                                    const TargetRegisterInfo *TRI) const {
  94     storeRegToStack(MBB, MBBI, SrcReg, isKill, FrameIndex, RC, TRI, 0);
  95   }
  96
  97   virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
  98                                     MachineBasicBlock::iterator MBBI,
  99                                     unsigned DestReg, int FrameIndex,
 100                                     const TargetRegisterClass *RC,
 101                                     const TargetRegisterInfo *TRI) const {
 102     loadRegFromStack(MBB, MBBI, DestReg, FrameIndex, RC, TRI, 0);
 103   }
 104
 105   virtual void storeRegToStack(MachineBasicBlock &MBB,
 106                                MachineBasicBlock::iterator MI,
 107                                unsigned SrcReg, bool isKill, int FrameIndex,
 108                                const TargetRegisterClass *RC,
 109                                const TargetRegisterInfo *TRI,
 110                                int64_t Offset) const = 0;
 111
 112   virtual void loadRegFromStack(MachineBasicBlock &MBB,
 113                                 MachineBasicBlock::iterator MI,
 114                                 unsigned DestReg, int FrameIndex,
 115                                 const TargetRegisterClass *RC,
 116                                 const TargetRegisterInfo *TRI,
 117                                 int64_t Offset) const = 0;
 118
 119 protected:
 120   bool isZeroImm(const MachineOperand &op) const;
 121
 122   MachineMemOperand *GetMemOperand(MachineBasicBlock &MBB, int FI,
 123                                    unsigned Flag) const;
 124
 125 private:
 126   virtual unsigned GetAnalyzableBrOpc(unsigned Opc) const = 0;
 127
 128   void AnalyzeCondBr(const MachineInstr *Inst, unsigned Opc,
 129                      MachineBasicBlock *&BB,
 130                      SmallVectorImpl<MachineOperand> &Cond) const;
 131
 132   void BuildCondBr(MachineBasicBlock &MBB, MachineBasicBlock *TBB, DebugLoc DL,
 133                    const SmallVectorImpl<MachineOperand>& Cond) const;
 134 };
 135
 136 /// Create MipsInstrInfo objects.
 137 const MipsInstrInfo *createMips16InstrInfo(MipsTargetMachine &TM);
 138 const MipsInstrInfo *createMipsSEInstrInfo(MipsTargetMachine &TM);
 139
 140 }
 141
 142 #endif