contrib/llvm/lib/Target/PowerPC/PPCScheduleA2.td

   1 //===- PPCScheduleA2.td - PPC A2 Scheduling Definitions --*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9
  10 // Primary reference:
  11 // A2 Processor User's Manual.
  12 // IBM (as updated in) 2010.
  13
  14 //===----------------------------------------------------------------------===//
  15 // Functional units on the PowerPC A2 chip sets
  16 //
  17 def IU0to3_0  : FuncUnit; // Fetch unit 1 to 4 slot 1
  18 def IU0to3_1  : FuncUnit; // Fetch unit 1 to 4 slot 2
  19 def IU0to3_2  : FuncUnit; // Fetch unit 1 to 4 slot 3
  20 def IU0to3_3  : FuncUnit; // Fetch unit 1 to 4 slot 4
  21 def IU4_0  : FuncUnit; // Instruction buffer slot 1
  22 def IU4_1  : FuncUnit; // Instruction buffer slot 2
  23 def IU4_2  : FuncUnit; // Instruction buffer slot 3
  24 def IU4_3  : FuncUnit; // Instruction buffer slot 4
  25 def IU4_4  : FuncUnit; // Instruction buffer slot 5
  26 def IU4_5  : FuncUnit; // Instruction buffer slot 6
  27 def IU4_6  : FuncUnit; // Instruction buffer slot 7
  28 def IU4_7  : FuncUnit; // Instruction buffer slot 8
  29 def IU5    : FuncUnit; // Dependency resolution
  30 def IU6    : FuncUnit; // Instruction issue
  31 def RF0    : FuncUnit;
  32 def XRF1   : FuncUnit;
  33 def XEX1   : FuncUnit; // Execution stage 1 for the XU pipeline
  34 def XEX2   : FuncUnit; // Execution stage 2 for the XU pipeline
  35 def XEX3   : FuncUnit; // Execution stage 3 for the XU pipeline
  36 def XEX4   : FuncUnit; // Execution stage 4 for the XU pipeline
  37 def XEX5   : FuncUnit; // Execution stage 5 for the XU pipeline
  38 def XEX6   : FuncUnit; // Execution stage 6 for the XU pipeline
  39 def FRF1   : FuncUnit;
  40 def FEX1   : FuncUnit; // Execution stage 1 for the FU pipeline
  41 def FEX2   : FuncUnit; // Execution stage 2 for the FU pipeline
  42 def FEX3   : FuncUnit; // Execution stage 3 for the FU pipeline
  43 def FEX4   : FuncUnit; // Execution stage 4 for the FU pipeline
  44 def FEX5   : FuncUnit; // Execution stage 5 for the FU pipeline
  45 def FEX6   : FuncUnit; // Execution stage 6 for the FU pipeline
  46
  47 def CR_Bypass  : Bypass; // The bypass for condition regs.
  48 //def GPR_Bypass : Bypass; // The bypass for general-purpose regs.
  49 //def FPR_Bypass : Bypass; // The bypass for floating-point regs.
  50
  51 //
  52 // This file defines the itinerary class data for the PPC A2 processor.
  53 //
  54 //===----------------------------------------------------------------------===//
  55
  56
  57 def PPCA2Itineraries : ProcessorItineraries<
  58   [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3,
  59    IU4_0, IU4_1, IU4_2, IU4_3, IU4_4, IU4_5, IU4_6, IU4_7,
  60    IU5, IU6, RF0, XRF1, XEX1, XEX2, XEX3, XEX4, XEX5, XEX6,
  61    FRF1, FEX1, FEX2, FEX3, FEX4, FEX5, FEX6],
  62   [CR_Bypass, GPR_Bypass, FPR_Bypass], [
  63   InstrItinData<IntSimple   , [InstrStage<4,
  64                                  [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
  65                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
  66                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
  67                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
  68                                InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
  69                                InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
  70                                InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
  71                                InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
  72                               [10, 7, 7],
  73                               [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
  74   InstrItinData<IntGeneral  , [InstrStage<4,
  75                                  [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
  76                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
  77                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
  78                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
  79                                InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
  80                                InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
  81                                InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
  82                                InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
  83                               [10, 7, 7],
  84                               [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
  85   InstrItinData<IntCompare  , [InstrStage<4,
  86                                  [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
  87                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
  88                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
  89                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
  90                                InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
  91                                InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
  92                                InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
  93                                InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
  94                               [10, 7, 7],
  95                               [CR_Bypass, GPR_Bypass, GPR_Bypass]>,
  96   InstrItinData<IntDivW     , [InstrStage<4,
  97                                  [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
  98                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
  99                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 100                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 101                                InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
 102                                InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
 103                                InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
 104                                InstrStage<1, [XEX5]>, InstrStage<38, [XEX6]>],
 105                               [53, 7, 7],
 106                               [NoBypass, GPR_Bypass, GPR_Bypass]>,
 107   InstrItinData<IntMFFS     , [InstrStage<4,
 108                                  [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 109                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 110                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 111                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 112                                InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
 113                                InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
 114                                InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
 115                                InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
 116                               [10, 7, 7],
 117                               [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
 118   InstrItinData<IntMTFSB0   , [InstrStage<4,
 119                                  [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 120                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 121                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 122                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 123                                InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
 124                                InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
 125                                InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
 126                                InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
 127                               [10, 7, 7],
 128                               [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
 129   InstrItinData<IntMulHW    , [InstrStage<4,
 130                                  [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 131                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 132                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 133                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 134                                InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
 135                                InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
 136                                InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
 137                                InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
 138                               [14, 7, 7],
 139                               [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
 140   InstrItinData<IntMulHWU   , [InstrStage<4,
 141                                  [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 142                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 143                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 144                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 145                                InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
 146                                InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
 147                                InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
 148                                InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
 149                               [14, 7, 7],
 150                               [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
 151   InstrItinData<IntMulLI    , [InstrStage<4,
 152                                  [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 153                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 154                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 155                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 156                                InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
 157                                InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
 158                                InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
 159                                InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
 160                               [15, 7, 7],
 161                               [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
 162   InstrItinData<IntRotate   , [InstrStage<4,
 163                                  [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 164                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 165                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 166                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 167                                InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
 168                                InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
 169                                InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
 170                                InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
 171                               [10, 7, 7],
 172                               [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
 173   InstrItinData<IntRotateD  , [InstrStage<4,
 174                                  [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 175                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 176                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 177                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 178                                InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
 179                                InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
 180                                InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
 181                                InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
 182                               [10, 7, 7],
 183                               [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
 184   InstrItinData<IntRotateDI , [InstrStage<4,
 185                                  [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 186                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 187                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 188                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 189                                InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
 190                                InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
 191                                InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
 192                                InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
 193                               [10, 7, 7],
 194                               [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
 195   InstrItinData<IntShift    , [InstrStage<4,
 196                                  [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 197                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 198                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 199                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 200                                InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
 201                                InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
 202                                InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
 203                                InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
 204                               [10, 7, 7],
 205                               [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
 206   InstrItinData<IntTrapW    , [InstrStage<4,
 207                                  [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 208                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 209                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 210                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 211                                InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
 212                                InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
 213                                InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
 214                                InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
 215                               [10, 7, 7],
 216                               [GPR_Bypass, GPR_Bypass]>,
 217   InstrItinData<IntTrapD    , [InstrStage<4,
 218                                  [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 219                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 220                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 221                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 222                                InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
 223                                InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
 224                                InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
 225                                InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
 226                               [10, 7, 7],
 227                               [GPR_Bypass, GPR_Bypass]>,
 228   InstrItinData<BrB         , [InstrStage<4,
 229                                  [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 230                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 231                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 232                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 233                                InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
 234                                InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
 235                                InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
 236                                InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
 237                               [15, 7, 7],
 238                               [NoBypass, GPR_Bypass]>,
 239   InstrItinData<BrCR        , [InstrStage<4,
 240                                  [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 241                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 242                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 243                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 244                                InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
 245                                InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
 246                                InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
 247                                InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
 248                               [10, 7, 7],
 249                               [CR_Bypass, CR_Bypass, CR_Bypass]>,
 250   InstrItinData<BrMCR       , [InstrStage<4,
 251                                  [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 252                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 253                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 254                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 255                                InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
 256                                InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
 257                                InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
 258                                InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
 259                               [10, 7, 7],
 260                               [CR_Bypass, CR_Bypass, CR_Bypass]>,
 261   InstrItinData<BrMCRX      , [InstrStage<4,
 262                                  [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 263                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 264                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 265                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 266                                InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
 267                                InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
 268                                InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
 269                                InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
 270                               [10, 7, 7],
 271                               [CR_Bypass, GPR_Bypass, GPR_Bypass]>,
 272   InstrItinData<LdStDCBA    , [InstrStage<4,
 273                                  [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 274                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 275                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 276                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 277                                InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
 278                                InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
 279                                InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
 280                                InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
 281                               [13, 11],
 282                               [NoBypass, GPR_Bypass]>,
 283   InstrItinData<LdStDCBF    , [InstrStage<4,
 284                                  [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 285                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 286                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 287                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 288                                InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
 289                                InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
 290                                InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
 291                                InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
 292                               [13, 11],
 293                               [NoBypass, GPR_Bypass]>,
 294   InstrItinData<LdStDCBI    , [InstrStage<4,
 295                                  [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 296                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 297                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 298                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 299                                InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
 300                                InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
 301                                InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
 302                                InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
 303                               [13, 11],
 304                               [NoBypass, GPR_Bypass]>,
 305   InstrItinData<LdStLoad    , [InstrStage<4,
 306                                  [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 307                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 308                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 309                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 310                                InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
 311                                InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
 312                                InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
 313                                InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
 314                               [14, 7],
 315                               [GPR_Bypass, GPR_Bypass]>,
 316   InstrItinData<LdStLoadUpd , [InstrStage<4,
 317                                  [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 318                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 319                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 320                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 321                                InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
 322                                InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
 323                                InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
 324                                InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
 325                               [14, 7],
 326                               [GPR_Bypass, GPR_Bypass]>,
 327   InstrItinData<LdStLDU     , [InstrStage<4,
 328                                  [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 329                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 330                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 331                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 332                                InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
 333                                InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
 334                                InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
 335                                InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
 336                               [14, 7],
 337                               [GPR_Bypass, GPR_Bypass]>,
 338   InstrItinData<LdStStore   , [InstrStage<4,
 339                                  [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 340                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 341                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 342                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 343                                InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
 344                                InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
 345                                InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
 346                                InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
 347                               [13, 7],
 348                               [GPR_Bypass, GPR_Bypass]>,
 349   InstrItinData<LdStStoreUpd, [InstrStage<4,
 350                                  [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 351                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 352                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 353                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 354                                InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
 355                                InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
 356                                InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
 357                                InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
 358                               [13, 7],
 359                               [GPR_Bypass, GPR_Bypass]>,
 360   InstrItinData<LdStICBI    , [InstrStage<4,
 361                                  [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 362                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 363                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 364                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 365                                InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
 366                                InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
 367                                InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
 368                                InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
 369                               [14, 7],
 370                               [NoBypass, GPR_Bypass]>,
 371   InstrItinData<LdStSTFD    , [InstrStage<4,
 372                                  [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 373                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 374                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 375                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 376                                InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
 377                                InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
 378                                InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
 379                                InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
 380                               [14, 7, 7],
 381                               [NoBypass, FPR_Bypass, FPR_Bypass]>,
 382   InstrItinData<LdStSTFDU   , [InstrStage<4,
 383                                  [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 384                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 385                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 386                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 387                                InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
 388                                InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
 389                                InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
 390                                InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
 391                               [14, 7, 7],
 392                               [NoBypass, FPR_Bypass, FPR_Bypass]>,
 393   InstrItinData<LdStLFD     , [InstrStage<4,
 394                                  [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 395                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 396                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 397                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 398                                InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
 399                                InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
 400                                InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
 401                                InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
 402                               [14, 7, 7],
 403                               [FPR_Bypass, GPR_Bypass, GPR_Bypass]>,
 404   InstrItinData<LdStLFDU    , [InstrStage<4,
 405                                  [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 406                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 407                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 408                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 409                                InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
 410                                InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
 411                                InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
 412                                InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
 413                               [14, 7, 7],
 414                               [FPR_Bypass, GPR_Bypass, GPR_Bypass]>,
 415   InstrItinData<LdStLHA     , [InstrStage<4,
 416                                  [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 417                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 418                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 419                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 420                                InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
 421                                InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
 422                                InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
 423                                InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
 424                               [14, 7],
 425                               [NoBypass, GPR_Bypass]>,
 426   InstrItinData<LdStLHAU    , [InstrStage<4,
 427                                  [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 428                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 429                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 430                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 431                                InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
 432                                InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
 433                                InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
 434                                InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
 435                               [14, 7],
 436                               [NoBypass, GPR_Bypass]>,
 437   InstrItinData<LdStLMW     , [InstrStage<4,
 438                                  [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 439                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 440                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 441                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 442                                InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
 443                                InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
 444                                InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
 445                                InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
 446                               [14, 7],
 447                               [NoBypass, GPR_Bypass]>,
 448   InstrItinData<LdStLWARX   , [InstrStage<4,
 449                                  [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 450                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 451                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 452                                InstrStage<1, [IU5]>, InstrStage<13, [IU6]>,
 453                                InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
 454                                InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
 455                                InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
 456                                InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
 457                               [26, 7],
 458                               [NoBypass, GPR_Bypass]>,
 459   InstrItinData<LdStSTD     , [InstrStage<4,
 460                                  [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 461                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 462                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 463                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 464                                InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
 465                                InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
 466                                InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
 467                                InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
 468                               [13, 7],
 469                               [GPR_Bypass, GPR_Bypass]>,
 470   InstrItinData<LdStSTDU    , [InstrStage<4,
 471                                  [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 472                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 473                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 474                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 475                                InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
 476                                InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
 477                                InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
 478                                InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
 479                               [13, 7],
 480                               [GPR_Bypass, GPR_Bypass]>,
 481   InstrItinData<LdStSTDCX   , [InstrStage<4,
 482                                  [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 483                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 484                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 485                                InstrStage<1, [IU5]>, InstrStage<13, [IU6]>,
 486                                InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
 487                                InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
 488                                InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
 489                                InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
 490                               [26, 7],
 491                               [NoBypass, GPR_Bypass]>,
 492   InstrItinData<LdStSTWCX   , [InstrStage<4,
 493                                  [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 494                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 495                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 496                                InstrStage<1, [IU5]>, InstrStage<13, [IU6]>,
 497                                InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
 498                                InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
 499                                InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
 500                                InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
 501                               [26, 7],
 502                               [NoBypass, GPR_Bypass]>,
 503   InstrItinData<LdStSync    , [InstrStage<4,
 504                                  [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 505                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 506                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 507                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 508                                InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
 509                                InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
 510                                InstrStage<1, [XEX3]>, InstrStage<12, [XEX4]>,
 511                                InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>]>,
 512   InstrItinData<SprISYNC    , [InstrStage<4,
 513                                  [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 514                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 515                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 516                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 517                                InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
 518                                InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
 519                                InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
 520                                InstrStage<1, [XEX5]>, InstrStage<14, [XEX6]>]>,
 521   InstrItinData<SprMFSR     , [InstrStage<4,
 522                                  [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 523                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 524                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 525                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 526                                InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
 527                                InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
 528                                InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
 529                                InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
 530                               [15, 7],
 531                               [GPR_Bypass, NoBypass]>,
 532   InstrItinData<SprMTMSR    , [InstrStage<4,
 533                                  [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 534                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 535                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 536                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 537                                InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
 538                                InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
 539                                InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
 540                                InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
 541                               [15, 7],
 542                               [NoBypass, GPR_Bypass]>,
 543   InstrItinData<SprMTSR     , [InstrStage<4,
 544                                  [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 545                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 546                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 547                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 548                                InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
 549                                InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
 550                                InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
 551                                InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
 552                               [15, 7],
 553                               [NoBypass, GPR_Bypass]>,
 554   InstrItinData<SprTLBSYNC  , [InstrStage<4,
 555                                  [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 556                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 557                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 558                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 559                                InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
 560                                InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
 561                                InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
 562                                InstrStage<1, [XEX5]>, InstrStage<14, [XEX6]>]>,
 563   InstrItinData<SprMFCR     , [InstrStage<4,
 564                                  [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 565                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 566                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 567                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 568                                InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
 569                                InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
 570                                InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
 571                                InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
 572                               [10, 7],
 573                               [GPR_Bypass, CR_Bypass]>,
 574   InstrItinData<SprMFMSR    , [InstrStage<4,
 575                                  [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 576                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 577                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 578                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 579                                InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
 580                                InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
 581                                InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
 582                                InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
 583                               [15, 7],
 584                               [GPR_Bypass, NoBypass]>,
 585   InstrItinData<SprMFSPR    , [InstrStage<4,
 586                                  [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 587                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 588                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 589                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 590                                InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
 591                                InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
 592                                InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
 593                                InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
 594                               [15, 7],
 595                               [NoBypass, GPR_Bypass]>,
 596   InstrItinData<SprMFTB     , [InstrStage<4,
 597                                  [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 598                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 599                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 600                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 601                                InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
 602                                InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
 603                                InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
 604                                InstrStage<1, [XEX5]>, InstrStage<14, [XEX6]>],
 605                               [29, 7],
 606                               [NoBypass, GPR_Bypass]>,
 607   InstrItinData<SprMTSPR    , [InstrStage<4,
 608                                  [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 609                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 610                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 611                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 612                                InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
 613                                InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
 614                                InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
 615                                InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
 616                               [15, 7],
 617                               [NoBypass, GPR_Bypass]>,
 618   InstrItinData<SprMTSRIN   , [InstrStage<4,
 619                                  [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 620                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 621                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 622                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 623                                InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
 624                                InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
 625                                InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
 626                                InstrStage<1, [XEX5]>, InstrStage<14, [XEX6]>],
 627                               [29, 7],
 628                               [NoBypass, GPR_Bypass]>,
 629   InstrItinData<SprRFI      , [InstrStage<4,
 630                                  [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 631                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 632                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 633                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 634                                InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
 635                                InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
 636                                InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
 637                                InstrStage<1, [XEX5]>, InstrStage<14, [XEX6]>],
 638                               [29, 7],
 639                               [NoBypass, GPR_Bypass]>,
 640   InstrItinData<SprSC       , [InstrStage<4,
 641                                  [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 642                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 643                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 644                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 645                                InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
 646                                InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
 647                                InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
 648                                InstrStage<1, [XEX5]>, InstrStage<14, [XEX6]>],
 649                               [29, 7],
 650                               [NoBypass, GPR_Bypass]>,
 651   InstrItinData<FPGeneral   , [InstrStage<4,
 652                                  [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 653                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 654                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 655                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 656                                InstrStage<1, [RF0]>, InstrStage<1, [FRF1]>,
 657                                InstrStage<1, [FEX1]>, InstrStage<1, [FEX2]>,
 658                                InstrStage<1, [FEX3]>, InstrStage<1, [FEX4]>,
 659                                InstrStage<1, [FEX5]>, InstrStage<1, [FEX6]>],
 660                               [15, 7, 7],
 661                               [FPR_Bypass, FPR_Bypass, FPR_Bypass]>,
 662   InstrItinData<FPAddSub    , [InstrStage<4,
 663                                  [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 664                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 665                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 666                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 667                                InstrStage<1, [RF0]>, InstrStage<1, [FRF1]>,
 668                                InstrStage<1, [FEX1]>, InstrStage<1, [FEX2]>,
 669                                InstrStage<1, [FEX3]>, InstrStage<1, [FEX4]>,
 670                                InstrStage<1, [FEX5]>, InstrStage<1, [FEX6]>],
 671                               [15, 7, 7],
 672                               [FPR_Bypass, FPR_Bypass, FPR_Bypass]>,
 673   InstrItinData<FPCompare   , [InstrStage<4,
 674                                  [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 675                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 676                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 677                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 678                                InstrStage<1, [RF0]>, InstrStage<1, [FRF1]>,
 679                                InstrStage<1, [FEX1]>, InstrStage<1, [FEX2]>,
 680                                InstrStage<1, [FEX3]>, InstrStage<1, [FEX4]>,
 681                                InstrStage<1, [FEX5]>, InstrStage<1, [FEX6]>],
 682                               [13, 7, 7],
 683                               [CR_Bypass, FPR_Bypass, FPR_Bypass]>,
 684   InstrItinData<FPDivD      , [InstrStage<4,
 685                                  [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 686                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 687                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 688                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 689                                InstrStage<1, [RF0]>, InstrStage<71, [FRF1], 0>,
 690                                InstrStage<71, [FEX1], 0>,
 691                                   InstrStage<71, [FEX2], 0>,
 692                                InstrStage<71, [FEX3], 0>,
 693                                   InstrStage<71, [FEX4], 0>,
 694                                InstrStage<71, [FEX5], 0>,
 695                                   InstrStage<71, [FEX6]>],
 696                               [86, 7, 7],
 697                               [NoBypass, FPR_Bypass, FPR_Bypass]>,
 698   InstrItinData<FPDivS      , [InstrStage<4,
 699                                  [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 700                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 701                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 702                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 703                                InstrStage<1, [RF0]>, InstrStage<58, [FRF1], 0>,
 704                                InstrStage<58, [FEX1], 0>,
 705                                   InstrStage<58, [FEX2], 0>,
 706                                InstrStage<58, [FEX3], 0>,
 707                                   InstrStage<58, [FEX4], 0>,
 708                                InstrStage<58, [FEX5], 0>,
 709                                   InstrStage<58, [FEX6]>],
 710                               [73, 7, 7],
 711                               [NoBypass, FPR_Bypass, FPR_Bypass]>,
 712   InstrItinData<FPSqrt      , [InstrStage<4,
 713                                  [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 714                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 715                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 716                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 717                                InstrStage<1, [RF0]>, InstrStage<68, [FRF1], 0>,
 718                                InstrStage<68, [FEX1], 0>,
 719                                   InstrStage<68, [FEX2], 0>,
 720                                InstrStage<68, [FEX3], 0>,
 721                                   InstrStage<68, [FEX4], 0>,
 722                                InstrStage<68, [FEX5], 0>,
 723                                   InstrStage<68, [FEX6]>],
 724                               [86, 7], // FIXME: should be [86, 7] for double
 725                                        // and [82, 7] for single. Likewise,
 726                                        // the FEX? cycle count should be 68
 727                                        // for double and 64 for single.
 728                               [NoBypass, FPR_Bypass]>,
 729   InstrItinData<FPFused     , [InstrStage<4,
 730                                  [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 731                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 732                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 733                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 734                                InstrStage<1, [RF0]>, InstrStage<1, [FRF1]>,
 735                                InstrStage<1, [FEX1]>, InstrStage<1, [FEX2]>,
 736                                InstrStage<1, [FEX3]>, InstrStage<1, [FEX4]>,
 737                                InstrStage<1, [FEX5]>, InstrStage<1, [FEX6]>],
 738                               [15, 7, 7, 7],
 739                               [FPR_Bypass, FPR_Bypass, FPR_Bypass, FPR_Bypass]>,
 740   InstrItinData<FPRes       , [InstrStage<4,
 741                                  [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 742                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 743                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 744                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 745                                InstrStage<1, [RF0]>, InstrStage<1, [FRF1]>,
 746                                InstrStage<1, [FEX1]>, InstrStage<1, [FEX2]>,
 747                                InstrStage<1, [FEX3]>, InstrStage<1, [FEX4]>,
 748                                InstrStage<1, [FEX5]>, InstrStage<1, [FEX6]>],
 749                               [15, 7],
 750                               [FPR_Bypass, FPR_Bypass]>
 751 ]>;
 752
 753 // ===---------------------------------------------------------------------===//
 754 // A2 machine model for scheduling and other instruction cost heuristics.
 755
 756 def PPCA2Model : SchedMachineModel {
 757   let IssueWidth = 1;  // 2 micro-ops are dispatched per cycle.
 758   let MinLatency = -1; // OperandCycles are interpreted as MinLatency.
 759   let LoadLatency = 6; // Optimistic load latency assuming bypass.
 760                        // This is overriden by OperandCycles if the
 761                        // Itineraries are queried instead.
 762   let MispredictPenalty = 13;
 763
 764   let Itineraries = PPCA2Itineraries;
 765 }
 766