contrib/llvm/lib/Target/PowerPC/PPCScheduleE500mc.td

   1 //===-- PPCScheduleE500mc.td - e500mc Scheduling Defs ------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines the itinerary class data for the Freescale e500mc 32-bit
  11 // Power processor.
  12 //
  13 // All information is derived from the "e500mc Core Reference Manual",
  14 // Freescale Document Number E500MCRM, Rev. 1, 03/2012.
  15 //
  16 //===----------------------------------------------------------------------===//
  17 // Relevant functional units in the Freescale e500mc core:
  18 //
  19 //  * Decode & Dispatch
  20 //    Can dispatch up to 2 instructions per clock cycle to either the GPR Issue
  21 //    queues (GIQx), FP Issue Queue (FIQ), or Branch issue queue (BIQ).
  22 def DIS0 : FuncUnit; // Dispatch stage - insn 1
  23 def DIS1 : FuncUnit; // Dispatch stage - insn 2
  24
  25 //  * Execute
  26 //    6 pipelined execution units: SFX0, SFX1, BU, FPU, LSU, CFX.
  27 //    Some instructions can only execute in SFX0 but not SFX1.
  28 //    The CFX has a bypass path, allowing non-divide instructions to execute
  29 //    while a divide instruction is executed.
  30 def SFX0  : FuncUnit; // Simple unit 0
  31 def SFX1  : FuncUnit; // Simple unit 1
  32 def BU    : FuncUnit; // Branch unit
  33 def CFX_DivBypass
  34           : FuncUnit; // CFX divide bypass path
  35 def CFX_0 : FuncUnit; // CFX pipeline
  36 def LSU_0 : FuncUnit; // LSU pipeline
  37 def FPU_0 : FuncUnit; // FPU pipeline
  38
  39 def PPCE500mcItineraries : ProcessorItineraries<
  40   [DIS0, DIS1, SFX0, SFX1, BU, CFX_DivBypass, CFX_0, LSU_0, FPU_0],
  41   [CR_Bypass, GPR_Bypass, FPR_Bypass], [
  42   InstrItinData<IntSimple   , [InstrStage<1, [DIS0, DIS1], 0>,
  43                                InstrStage<1, [SFX0, SFX1]>],
  44                               [4, 1, 1], // Latency = 1
  45                               [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
  46   InstrItinData<IntGeneral  , [InstrStage<1, [DIS0, DIS1], 0>,
  47                                InstrStage<1, [SFX0, SFX1]>],
  48                               [4, 1, 1], // Latency = 1
  49                               [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
  50   InstrItinData<IntCompare  , [InstrStage<1, [DIS0, DIS1], 0>,
  51                                InstrStage<1, [SFX0, SFX1]>],
  52                               [5, 1, 1], // Latency = 1 or 2
  53                               [CR_Bypass, GPR_Bypass, GPR_Bypass]>,
  54   InstrItinData<IntDivW     , [InstrStage<1, [DIS0, DIS1], 0>,
  55                                InstrStage<1, [CFX_0], 0>,
  56                                InstrStage<14, [CFX_DivBypass]>],
  57                               [17, 1, 1], // Latency=4..35, Repeat= 4..35
  58                               [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
  59   InstrItinData<IntMFFS     , [InstrStage<1, [DIS0, DIS1], 0>,
  60                                InstrStage<8, [FPU_0]>],
  61                               [11], // Latency = 8
  62                               [FPR_Bypass]>,
  63   InstrItinData<IntMTFSB0   , [InstrStage<1, [DIS0, DIS1], 0>,
  64                                InstrStage<8, [FPU_0]>],
  65                               [11, 1, 1], // Latency = 8
  66                               [NoBypass, NoBypass, NoBypass]>,
  67   InstrItinData<IntMulHW    , [InstrStage<1, [DIS0, DIS1], 0>,
  68                                InstrStage<1, [CFX_0]>],
  69                               [7, 1, 1], // Latency = 4, Repeat rate = 1
  70                               [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
  71   InstrItinData<IntMulHWU   , [InstrStage<1, [DIS0, DIS1], 0>,
  72                                InstrStage<1, [CFX_0]>],
  73                               [7, 1, 1], // Latency = 4, Repeat rate = 1
  74                               [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
  75   InstrItinData<IntMulLI    , [InstrStage<1, [DIS0, DIS1], 0>,
  76                                InstrStage<1, [CFX_0]>],
  77                               [7, 1, 1], // Latency = 4, Repeat rate = 1
  78                               [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
  79   InstrItinData<IntRotate   , [InstrStage<1, [DIS0, DIS1], 0>,
  80                                InstrStage<1, [SFX0, SFX1]>],
  81                               [4, 1, 1], // Latency = 1
  82                               [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
  83   InstrItinData<IntShift    , [InstrStage<1, [DIS0, DIS1], 0>,
  84                                InstrStage<1, [SFX0, SFX1]>],
  85                               [4, 1, 1], // Latency = 1
  86                               [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
  87   InstrItinData<IntTrapW    , [InstrStage<1, [DIS0, DIS1], 0>,
  88                                InstrStage<2, [SFX0]>],
  89                               [5, 1], // Latency = 2, Repeat rate = 2
  90                               [GPR_Bypass, GPR_Bypass]>,
  91   InstrItinData<BrB         , [InstrStage<1, [DIS0, DIS1], 0>,
  92                                InstrStage<1, [BU]>],
  93                               [4, 1], // Latency = 1
  94                               [NoBypass, GPR_Bypass]>,
  95   InstrItinData<BrCR        , [InstrStage<1, [DIS0, DIS1], 0>,
  96                                InstrStage<1, [BU]>],
  97                               [4, 1, 1], // Latency = 1
  98                               [CR_Bypass, CR_Bypass, CR_Bypass]>,
  99   InstrItinData<BrMCR       , [InstrStage<1, [DIS0, DIS1], 0>,
 100                                InstrStage<1, [BU]>],
 101                               [4, 1], // Latency = 1
 102                               [CR_Bypass, CR_Bypass]>,
 103   InstrItinData<BrMCRX      , [InstrStage<1, [DIS0, DIS1], 0>,
 104                                InstrStage<1, [SFX0, SFX1]>],
 105                               [4, 1, 1], // Latency = 1
 106                               [CR_Bypass, GPR_Bypass]>,
 107   InstrItinData<LdStDCBA    , [InstrStage<1, [DIS0, DIS1], 0>,
 108                                InstrStage<1, [LSU_0]>],
 109                               [6, 1], // Latency = 3, Repeat rate = 1
 110                               [GPR_Bypass, GPR_Bypass]>,
 111   InstrItinData<LdStDCBF    , [InstrStage<1, [DIS0, DIS1], 0>,
 112                                InstrStage<1, [LSU_0]>],
 113                               [6, 1], // Latency = 3
 114                               [GPR_Bypass, GPR_Bypass]>,
 115   InstrItinData<LdStDCBI    , [InstrStage<1, [DIS0, DIS1], 0>,
 116                                InstrStage<1, [LSU_0]>],
 117                               [6, 1], // Latency = 3
 118                               [GPR_Bypass, GPR_Bypass]>,
 119   InstrItinData<LdStLoad    , [InstrStage<1, [DIS0, DIS1], 0>,
 120                                InstrStage<1, [LSU_0]>],
 121                               [6, 1], // Latency = 3
 122                               [GPR_Bypass, GPR_Bypass]>,
 123   InstrItinData<LdStLoadUpd , [InstrStage<1, [DIS0, DIS1], 0>,
 124                                InstrStage<1, [SFX0, SFX1], 0>,
 125                                InstrStage<1, [LSU_0]>],
 126                               [6, 1], // Latency = 3
 127                               [GPR_Bypass, GPR_Bypass],
 128                               2>, // 2 micro-ops
 129   InstrItinData<LdStStore   , [InstrStage<1, [DIS0, DIS1], 0>,
 130                                InstrStage<1, [LSU_0]>],
 131                               [6, 1], // Latency = 3
 132                               [NoBypass, GPR_Bypass]>,
 133   InstrItinData<LdStStoreUpd, [InstrStage<1, [DIS0, DIS1], 0>,
 134                                InstrStage<1, [SFX0, SFX1], 0>,
 135                                InstrStage<1, [LSU_0]>],
 136                               [6, 1], // Latency = 3
 137                               [NoBypass, GPR_Bypass],
 138                               2>, // 2 micro-ops
 139   InstrItinData<LdStICBI    , [InstrStage<1, [DIS0, DIS1], 0>,
 140                                InstrStage<1, [LSU_0]>],
 141                               [6, 1], // Latency = 3
 142                               [NoBypass, GPR_Bypass]>,
 143   InstrItinData<LdStSTFD    , [InstrStage<1, [DIS0, DIS1], 0>,
 144                                InstrStage<1, [LSU_0]>],
 145                               [6, 1, 1], // Latency = 3
 146                               [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
 147   InstrItinData<LdStSTFDU   , [InstrStage<1, [DIS0, DIS1], 0>,
 148                                InstrStage<1, [SFX0, SFX1], 0>,
 149                                InstrStage<1, [LSU_0]>],
 150                               [6, 1, 1], // Latency = 3
 151                               [GPR_Bypass, GPR_Bypass, GPR_Bypass],
 152                               2>, // 2 micro-ops
 153   InstrItinData<LdStLFD     , [InstrStage<1, [DIS0, DIS1], 0>,
 154                                InstrStage<1, [LSU_0]>],
 155                               [7, 1, 1], // Latency = 4
 156                               [FPR_Bypass, GPR_Bypass, GPR_Bypass]>,
 157   InstrItinData<LdStLFDU    , [InstrStage<1, [DIS0, DIS1], 0>,
 158                                InstrStage<1, [SFX0, SFX1], 0>,
 159                                InstrStage<1, [LSU_0]>],
 160                               [7, 1, 1], // Latency = 4
 161                               [FPR_Bypass, GPR_Bypass, GPR_Bypass],
 162                               2>, // 2 micro-ops
 163   InstrItinData<LdStLHA     , [InstrStage<1, [DIS0, DIS1], 0>,
 164                                InstrStage<1, [LSU_0]>],
 165                               [6, 1], // Latency = 3
 166                               [GPR_Bypass, GPR_Bypass]>,
 167   InstrItinData<LdStLHAU    , [InstrStage<1, [DIS0, DIS1], 0>,
 168                                InstrStage<1, [SFX0, SFX1], 0>,
 169                                InstrStage<1, [LSU_0]>],
 170                               [6, 1], // Latency = 3
 171                               [GPR_Bypass, GPR_Bypass]>,
 172   InstrItinData<LdStLMW     , [InstrStage<1, [DIS0, DIS1], 0>,
 173                                InstrStage<1, [LSU_0]>],
 174                               [7, 1], // Latency = r+3
 175                               [NoBypass, GPR_Bypass]>,
 176   InstrItinData<LdStLWARX   , [InstrStage<1, [DIS0, DIS1], 0>,
 177                                InstrStage<3, [LSU_0]>],
 178                               [6, 1, 1], // Latency = 3, Repeat rate = 3
 179                               [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
 180   InstrItinData<LdStSTWCX   , [InstrStage<1, [DIS0, DIS1], 0>,
 181                                InstrStage<1, [LSU_0]>],
 182                               [6, 1], // Latency = 3
 183                               [NoBypass, GPR_Bypass]>,
 184   InstrItinData<LdStSync    , [InstrStage<1, [DIS0, DIS1], 0>,
 185                                InstrStage<1, [LSU_0]>]>,
 186   InstrItinData<SprMFSR     , [InstrStage<1, [DIS0, DIS1], 0>,
 187                                InstrStage<4, [SFX0]>],
 188                               [7, 1],
 189                               [GPR_Bypass, GPR_Bypass]>,
 190   InstrItinData<SprMTMSR    , [InstrStage<1, [DIS0, DIS1], 0>,
 191                                InstrStage<2, [SFX0, SFX1]>],
 192                               [5, 1], // Latency = 2, Repeat rate = 4
 193                               [GPR_Bypass, GPR_Bypass]>,
 194   InstrItinData<SprMTSR     , [InstrStage<1, [DIS0, DIS1], 0>,
 195                                InstrStage<1, [SFX0]>],
 196                               [5, 1],
 197                               [NoBypass, GPR_Bypass]>,
 198   InstrItinData<SprTLBSYNC  , [InstrStage<1, [DIS0, DIS1], 0>,
 199                                InstrStage<1, [LSU_0], 0>]>,
 200   InstrItinData<SprMFCR     , [InstrStage<1, [DIS0, DIS1], 0>,
 201                                InstrStage<5, [SFX0]>],
 202                               [8, 1],
 203                               [GPR_Bypass, CR_Bypass]>,
 204   InstrItinData<SprMFMSR    , [InstrStage<1, [DIS0, DIS1], 0>,
 205                                InstrStage<4, [SFX0]>],
 206                               [7, 1], // Latency = 4, Repeat rate = 4
 207                               [GPR_Bypass, GPR_Bypass]>,
 208   InstrItinData<SprMFSPR    , [InstrStage<1, [DIS0, DIS1], 0>,
 209                                InstrStage<1, [SFX0, SFX1]>],
 210                               [4, 1], // Latency = 1, Repeat rate = 1
 211                               [GPR_Bypass, CR_Bypass]>,
 212   InstrItinData<SprMFTB     , [InstrStage<1, [DIS0, DIS1], 0>,
 213                                InstrStage<4, [SFX0]>],
 214                               [7, 1], // Latency = 4, Repeat rate = 4
 215                               [NoBypass, GPR_Bypass]>,
 216   InstrItinData<SprMTSPR    , [InstrStage<1, [DIS0, DIS1], 0>,
 217                                InstrStage<1, [SFX0, SFX1]>],
 218                               [4, 1], // Latency = 1, Repeat rate = 1
 219                               [CR_Bypass, GPR_Bypass]>,
 220   InstrItinData<SprMTSRIN   , [InstrStage<1, [DIS0, DIS1], 0>,
 221                                InstrStage<1, [SFX0]>],
 222                               [4, 1],
 223                               [NoBypass, GPR_Bypass]>,
 224   InstrItinData<FPGeneral   , [InstrStage<1, [DIS0, DIS1], 0>,
 225                                InstrStage<2, [FPU_0]>],
 226                               [11, 1, 1], // Latency = 8, Repeat rate = 2
 227                               [FPR_Bypass, FPR_Bypass, FPR_Bypass]>,
 228   InstrItinData<FPAddSub    , [InstrStage<1, [DIS0, DIS1], 0>,
 229                                InstrStage<4, [FPU_0]>],
 230                               [13, 1, 1], // Latency = 10, Repeat rate = 4
 231                               [FPR_Bypass, FPR_Bypass, FPR_Bypass]>,
 232   InstrItinData<FPCompare   , [InstrStage<1, [DIS0, DIS1], 0>,
 233                                InstrStage<2, [FPU_0]>],
 234                               [11, 1, 1], // Latency = 8, Repeat rate = 2
 235                               [CR_Bypass, FPR_Bypass, FPR_Bypass]>,
 236   InstrItinData<FPDivD      , [InstrStage<1, [DIS0, DIS1], 0>,
 237                                InstrStage<68, [FPU_0]>],
 238                               [71, 1, 1], // Latency = 68, Repeat rate = 68
 239                               [FPR_Bypass, FPR_Bypass, FPR_Bypass]>,
 240   InstrItinData<FPDivS      , [InstrStage<1, [DIS0, DIS1], 0>,
 241                                InstrStage<38, [FPU_0]>],
 242                               [41, 1, 1], // Latency = 38, Repeat rate = 38
 243                               [FPR_Bypass, FPR_Bypass, FPR_Bypass]>,
 244   InstrItinData<FPFused     , [InstrStage<1, [DIS0, DIS1], 0>,
 245                                InstrStage<4, [FPU_0]>],
 246                               [13, 1, 1, 1], // Latency = 10, Repeat rate = 4
 247                               [FPR_Bypass, FPR_Bypass, FPR_Bypass, FPR_Bypass]>,
 248   InstrItinData<FPRes       , [InstrStage<1, [DIS0, DIS1], 0>,
 249                                InstrStage<38, [FPU_0]>],
 250                               [41, 1], // Latency = 38, Repeat rate = 38
 251                               [FPR_Bypass, FPR_Bypass]>
 252 ]>;
 253
 254 // ===---------------------------------------------------------------------===//
 255 // e500mc machine model for scheduling and other instruction cost heuristics.
 256
 257 def PPCE500mcModel : SchedMachineModel {
 258   let IssueWidth = 2;  // 2 micro-ops are dispatched per cycle.
 259   let MinLatency = -1; // OperandCycles are interpreted as MinLatency.
 260   let LoadLatency = 5; // Optimistic load latency assuming bypass.
 261                        // This is overriden by OperandCycles if the
 262                        // Itineraries are queried instead.
 263
 264   let Itineraries = PPCE500mcItineraries;
 265 }