contrib/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h

   1 /*===-- X86DisassemblerDecoderCommon.h - Disassembler decoder -----*- C -*-===*
   2  *
   3  *                     The LLVM Compiler Infrastructure
   4  *
   5  * This file is distributed under the University of Illinois Open Source
   6  * License. See LICENSE.TXT for details.
   7  *
   8  *===----------------------------------------------------------------------===*
   9  *
  10  * This file is part of the X86 Disassembler.
  11  * It contains common definitions used by both the disassembler and the table
  12  *  generator.
  13  * Documentation for the disassembler can be found in X86Disassembler.h.
  14  *
  15  *===----------------------------------------------------------------------===*/
  16
  17 /*
  18  * This header file provides those definitions that need to be shared between
  19  * the decoder and the table generator in a C-friendly manner.
  20  */
  21
  22 #ifndef X86DISASSEMBLERDECODERCOMMON_H
  23 #define X86DISASSEMBLERDECODERCOMMON_H
  24
  25 #include "llvm/Support/DataTypes.h"
  26
  27 #define INSTRUCTIONS_SYM  x86DisassemblerInstrSpecifiers
  28 #define CONTEXTS_SYM      x86DisassemblerContexts
  29 #define ONEBYTE_SYM       x86DisassemblerOneByteOpcodes
  30 #define TWOBYTE_SYM       x86DisassemblerTwoByteOpcodes
  31 #define THREEBYTE38_SYM   x86DisassemblerThreeByte38Opcodes
  32 #define THREEBYTE3A_SYM   x86DisassemblerThreeByte3AOpcodes
  33 #define THREEBYTEA6_SYM   x86DisassemblerThreeByteA6Opcodes
  34 #define THREEBYTEA7_SYM   x86DisassemblerThreeByteA7Opcodes
  35
  36 #define INSTRUCTIONS_STR  "x86DisassemblerInstrSpecifiers"
  37 #define CONTEXTS_STR      "x86DisassemblerContexts"
  38 #define ONEBYTE_STR       "x86DisassemblerOneByteOpcodes"
  39 #define TWOBYTE_STR       "x86DisassemblerTwoByteOpcodes"
  40 #define THREEBYTE38_STR   "x86DisassemblerThreeByte38Opcodes"
  41 #define THREEBYTE3A_STR   "x86DisassemblerThreeByte3AOpcodes"
  42 #define THREEBYTEA6_STR   "x86DisassemblerThreeByteA6Opcodes"
  43 #define THREEBYTEA7_STR   "x86DisassemblerThreeByteA7Opcodes"
  44
  45 /*
  46  * Attributes of an instruction that must be known before the opcode can be
  47  * processed correctly.  Most of these indicate the presence of particular
  48  * prefixes, but ATTR_64BIT is simply an attribute of the decoding context.
  49  */
  50 #define ATTRIBUTE_BITS          \
  51   ENUM_ENTRY(ATTR_NONE,   0x00) \
  52   ENUM_ENTRY(ATTR_64BIT,  0x01) \
  53   ENUM_ENTRY(ATTR_XS,     0x02) \
  54   ENUM_ENTRY(ATTR_XD,     0x04) \
  55   ENUM_ENTRY(ATTR_REXW,   0x08) \
  56   ENUM_ENTRY(ATTR_OPSIZE, 0x10) \
  57   ENUM_ENTRY(ATTR_ADSIZE, 0x20) \
  58   ENUM_ENTRY(ATTR_VEX,    0x40) \
  59   ENUM_ENTRY(ATTR_VEXL,   0x80)
  60
  61 #define ENUM_ENTRY(n, v) n = v,
  62 enum attributeBits {
  63   ATTRIBUTE_BITS
  64   ATTR_max
  65 };
  66 #undef ENUM_ENTRY
  67
  68 /*
  69  * Combinations of the above attributes that are relevant to instruction
  70  * decode.  Although other combinations are possible, they can be reduced to
  71  * these without affecting the ultimately decoded instruction.
  72  */
  73
  74 /*           Class name           Rank  Rationale for rank assignment         */
  75 #define INSTRUCTION_CONTEXTS                                                   \
  76   ENUM_ENTRY(IC,                    0,  "says nothing about the instruction")  \
  77   ENUM_ENTRY(IC_64BIT,              1,  "says the instruction applies in "     \
  78                                         "64-bit mode but no more")             \
  79   ENUM_ENTRY(IC_OPSIZE,             3,  "requires an OPSIZE prefix, so "       \
  80                                         "operands change width")               \
  81   ENUM_ENTRY(IC_ADSIZE,             3,  "requires an ADSIZE prefix, so "       \
  82                                         "operands change width")               \
  83   ENUM_ENTRY(IC_XD,                 2,  "may say something about the opcode "  \
  84                                         "but not the operands")                \
  85   ENUM_ENTRY(IC_XS,                 2,  "may say something about the opcode "  \
  86                                         "but not the operands")                \
  87   ENUM_ENTRY(IC_XD_OPSIZE,          3,  "requires an OPSIZE prefix, so "       \
  88                                         "operands change width")               \
  89   ENUM_ENTRY(IC_XS_OPSIZE,          3,  "requires an OPSIZE prefix, so "       \
  90                                         "operands change width")               \
  91   ENUM_ENTRY(IC_64BIT_REXW,         4,  "requires a REX.W prefix, so operands "\
  92                                         "change width; overrides IC_OPSIZE")   \
  93   ENUM_ENTRY(IC_64BIT_OPSIZE,       3,  "Just as meaningful as IC_OPSIZE")     \
  94   ENUM_ENTRY(IC_64BIT_ADSIZE,       3,  "Just as meaningful as IC_ADSIZE")     \
  95   ENUM_ENTRY(IC_64BIT_XD,           5,  "XD instructions are SSE; REX.W is "   \
  96                                         "secondary")                           \
  97   ENUM_ENTRY(IC_64BIT_XS,           5,  "Just as meaningful as IC_64BIT_XD")   \
  98   ENUM_ENTRY(IC_64BIT_XD_OPSIZE,    3,  "Just as meaningful as IC_XD_OPSIZE")  \
  99   ENUM_ENTRY(IC_64BIT_XS_OPSIZE,    3,  "Just as meaningful as IC_XS_OPSIZE")  \
 100   ENUM_ENTRY(IC_64BIT_REXW_XS,      6,  "OPSIZE could mean a different "       \
 101                                         "opcode")                              \
 102   ENUM_ENTRY(IC_64BIT_REXW_XD,      6,  "Just as meaningful as "               \
 103                                         "IC_64BIT_REXW_XS")                    \
 104   ENUM_ENTRY(IC_64BIT_REXW_OPSIZE,  7,  "The Dynamic Duo!  Prefer over all "   \
 105                                         "else because this changes most "      \
 106                                         "operands' meaning")                   \
 107   ENUM_ENTRY(IC_VEX,                1,  "requires a VEX prefix")               \
 108   ENUM_ENTRY(IC_VEX_XS,             2,  "requires VEX and the XS prefix")      \
 109   ENUM_ENTRY(IC_VEX_XD,             2,  "requires VEX and the XD prefix")      \
 110   ENUM_ENTRY(IC_VEX_OPSIZE,         2,  "requires VEX and the OpSize prefix")  \
 111   ENUM_ENTRY(IC_VEX_W,              3,  "requires VEX and the W prefix")       \
 112   ENUM_ENTRY(IC_VEX_W_XS,           4,  "requires VEX, W, and XS prefix")      \
 113   ENUM_ENTRY(IC_VEX_W_XD,           4,  "requires VEX, W, and XD prefix")      \
 114   ENUM_ENTRY(IC_VEX_W_OPSIZE,       4,  "requires VEX, W, and OpSize")         \
 115   ENUM_ENTRY(IC_VEX_L,              3,  "requires VEX and the L prefix")       \
 116   ENUM_ENTRY(IC_VEX_L_XS,           4,  "requires VEX and the L and XS prefix")\
 117   ENUM_ENTRY(IC_VEX_L_XD,           4,  "requires VEX and the L and XD prefix")\
 118   ENUM_ENTRY(IC_VEX_L_OPSIZE,       4,  "requires VEX, L, and OpSize")         \
 119   ENUM_ENTRY(IC_VEX_L_W_OPSIZE,     5,  "requires VEX, L, W and OpSize")
 120
 121
 122 #define ENUM_ENTRY(n, r, d) n,
 123 typedef enum {
 124   INSTRUCTION_CONTEXTS
 125   IC_max
 126 } InstructionContext;
 127 #undef ENUM_ENTRY
 128
 129 /*
 130  * Opcode types, which determine which decode table to use, both in the Intel
 131  * manual and also for the decoder.
 132  */
 133 typedef enum {
 134   ONEBYTE       = 0,
 135   TWOBYTE       = 1,
 136   THREEBYTE_38  = 2,
 137   THREEBYTE_3A  = 3,
 138   THREEBYTE_A6  = 4,
 139   THREEBYTE_A7  = 5
 140 } OpcodeType;
 141
 142 /*
 143  * The following structs are used for the hierarchical decode table.  After
 144  * determining the instruction's class (i.e., which IC_* constant applies to
 145  * it), the decoder reads the opcode.  Some instructions require specific
 146  * values of the ModR/M byte, so the ModR/M byte indexes into the final table.
 147  *
 148  * If a ModR/M byte is not required, "required" is left unset, and the values
 149  * for each instructionID are identical.
 150  */
 151
 152 typedef uint16_t InstrUID;
 153
 154 /*
 155  * ModRMDecisionType - describes the type of ModR/M decision, allowing the
 156  * consumer to determine the number of entries in it.
 157  *
 158  * MODRM_ONEENTRY - No matter what the value of the ModR/M byte is, the decoded
 159  *                  instruction is the same.
 160  * MODRM_SPLITRM  - If the ModR/M byte is between 0x00 and 0xbf, the opcode
 161  *                  corresponds to one instruction; otherwise, it corresponds to
 162  *                  a different instruction.
 163  * MODRM_SPLITMISC- If the ModR/M byte is between 0x00 and 0xbf, ModR/M byte
 164  *                  divided by 8 is used to select instruction; otherwise, each
 165  *                  value of the ModR/M byte could correspond to a different
 166  *                  instruction.
 167  * MODRM_SPLITREG - ModR/M byte divided by 8 is used to select instruction. This
 168                     corresponds to instructions that use reg field as opcode
 169  * MODRM_FULL     - Potentially, each value of the ModR/M byte could correspond
 170  *                  to a different instruction.
 171  */
 172
 173 #define MODRMTYPES            \
 174   ENUM_ENTRY(MODRM_ONEENTRY)  \
 175   ENUM_ENTRY(MODRM_SPLITRM)   \
 176   ENUM_ENTRY(MODRM_SPLITMISC)  \
 177   ENUM_ENTRY(MODRM_SPLITREG)  \
 178   ENUM_ENTRY(MODRM_FULL)
 179
 180 #define ENUM_ENTRY(n) n,
 181 typedef enum {
 182   MODRMTYPES
 183   MODRM_max
 184 } ModRMDecisionType;
 185 #undef ENUM_ENTRY
 186
 187 /*
 188  * ModRMDecision - Specifies whether a ModR/M byte is needed and (if so) which
 189  *  instruction each possible value of the ModR/M byte corresponds to.  Once
 190  *  this information is known, we have narrowed down to a single instruction.
 191  */
 192 struct ModRMDecision {
 193   uint8_t     modrm_type;
 194
 195   /* The macro below must be defined wherever this file is included. */
 196   INSTRUCTION_IDS
 197 };
 198
 199 /*
 200  * OpcodeDecision - Specifies which set of ModR/M->instruction tables to look at
 201  *   given a particular opcode.
 202  */
 203 struct OpcodeDecision {
 204   struct ModRMDecision modRMDecisions[256];
 205 };
 206
 207 /*
 208  * ContextDecision - Specifies which opcode->instruction tables to look at given
 209  *   a particular context (set of attributes).  Since there are many possible
 210  *   contexts, the decoder first uses CONTEXTS_SYM to determine which context
 211  *   applies given a specific set of attributes.  Hence there are only IC_max
 212  *   entries in this table, rather than 2^(ATTR_max).
 213  */
 214 struct ContextDecision {
 215   struct OpcodeDecision opcodeDecisions[IC_max];
 216 };
 217
 218 /*
 219  * Physical encodings of instruction operands.
 220  */
 221
 222 #define ENCODINGS                                                              \
 223   ENUM_ENTRY(ENCODING_NONE,   "")                                              \
 224   ENUM_ENTRY(ENCODING_REG,    "Register operand in ModR/M byte.")              \
 225   ENUM_ENTRY(ENCODING_RM,     "R/M operand in ModR/M byte.")                   \
 226   ENUM_ENTRY(ENCODING_VVVV,   "Register operand in VEX.vvvv byte.")            \
 227   ENUM_ENTRY(ENCODING_CB,     "1-byte code offset (possible new CS value)")    \
 228   ENUM_ENTRY(ENCODING_CW,     "2-byte")                                        \
 229   ENUM_ENTRY(ENCODING_CD,     "4-byte")                                        \
 230   ENUM_ENTRY(ENCODING_CP,     "6-byte")                                        \
 231   ENUM_ENTRY(ENCODING_CO,     "8-byte")                                        \
 232   ENUM_ENTRY(ENCODING_CT,     "10-byte")                                       \
 233   ENUM_ENTRY(ENCODING_IB,     "1-byte immediate")                              \
 234   ENUM_ENTRY(ENCODING_IW,     "2-byte")                                        \
 235   ENUM_ENTRY(ENCODING_ID,     "4-byte")                                        \
 236   ENUM_ENTRY(ENCODING_IO,     "8-byte")                                        \
 237   ENUM_ENTRY(ENCODING_RB,     "(AL..DIL, R8L..R15L) Register code added to "   \
 238                               "the opcode byte")                               \
 239   ENUM_ENTRY(ENCODING_RW,     "(AX..DI, R8W..R15W)")                           \
 240   ENUM_ENTRY(ENCODING_RD,     "(EAX..EDI, R8D..R15D)")                         \
 241   ENUM_ENTRY(ENCODING_RO,     "(RAX..RDI, R8..R15)")                           \
 242   ENUM_ENTRY(ENCODING_I,      "Position on floating-point stack added to the " \
 243                               "opcode byte")                                   \
 244                                                                                \
 245   ENUM_ENTRY(ENCODING_Iv,     "Immediate of operand size")                     \
 246   ENUM_ENTRY(ENCODING_Ia,     "Immediate of address size")                     \
 247   ENUM_ENTRY(ENCODING_Rv,     "Register code of operand size added to the "    \
 248                               "opcode byte")                                   \
 249   ENUM_ENTRY(ENCODING_DUP,    "Duplicate of another operand; ID is encoded "   \
 250                               "in type")
 251
 252 #define ENUM_ENTRY(n, d) n,
 253   typedef enum {
 254     ENCODINGS
 255     ENCODING_max
 256   } OperandEncoding;
 257 #undef ENUM_ENTRY
 258
 259 /*
 260  * Semantic interpretations of instruction operands.
 261  */
 262
 263 #define TYPES                                                                  \
 264   ENUM_ENTRY(TYPE_NONE,       "")                                              \
 265   ENUM_ENTRY(TYPE_REL8,       "1-byte immediate address")                      \
 266   ENUM_ENTRY(TYPE_REL16,      "2-byte")                                        \
 267   ENUM_ENTRY(TYPE_REL32,      "4-byte")                                        \
 268   ENUM_ENTRY(TYPE_REL64,      "8-byte")                                        \
 269   ENUM_ENTRY(TYPE_PTR1616,    "2+2-byte segment+offset address")               \
 270   ENUM_ENTRY(TYPE_PTR1632,    "2+4-byte")                                      \
 271   ENUM_ENTRY(TYPE_PTR1664,    "2+8-byte")                                      \
 272   ENUM_ENTRY(TYPE_R8,         "1-byte register operand")                       \
 273   ENUM_ENTRY(TYPE_R16,        "2-byte")                                        \
 274   ENUM_ENTRY(TYPE_R32,        "4-byte")                                        \
 275   ENUM_ENTRY(TYPE_R64,        "8-byte")                                        \
 276   ENUM_ENTRY(TYPE_IMM8,       "1-byte immediate operand")                      \
 277   ENUM_ENTRY(TYPE_IMM16,      "2-byte")                                        \
 278   ENUM_ENTRY(TYPE_IMM32,      "4-byte")                                        \
 279   ENUM_ENTRY(TYPE_IMM64,      "8-byte")                                        \
 280   ENUM_ENTRY(TYPE_IMM3,       "1-byte immediate operand between 0 and 7")      \
 281   ENUM_ENTRY(TYPE_IMM5,       "1-byte immediate operand between 0 and 31")     \
 282   ENUM_ENTRY(TYPE_RM8,        "1-byte register or memory operand")             \
 283   ENUM_ENTRY(TYPE_RM16,       "2-byte")                                        \
 284   ENUM_ENTRY(TYPE_RM32,       "4-byte")                                        \
 285   ENUM_ENTRY(TYPE_RM64,       "8-byte")                                        \
 286   ENUM_ENTRY(TYPE_M,          "Memory operand")                                \
 287   ENUM_ENTRY(TYPE_M8,         "1-byte")                                        \
 288   ENUM_ENTRY(TYPE_M16,        "2-byte")                                        \
 289   ENUM_ENTRY(TYPE_M32,        "4-byte")                                        \
 290   ENUM_ENTRY(TYPE_M64,        "8-byte")                                        \
 291   ENUM_ENTRY(TYPE_LEA,        "Effective address")                             \
 292   ENUM_ENTRY(TYPE_M128,       "16-byte (SSE/SSE2)")                            \
 293   ENUM_ENTRY(TYPE_M256,       "256-byte (AVX)")                                \
 294   ENUM_ENTRY(TYPE_M1616,      "2+2-byte segment+offset address")               \
 295   ENUM_ENTRY(TYPE_M1632,      "2+4-byte")                                      \
 296   ENUM_ENTRY(TYPE_M1664,      "2+8-byte")                                      \
 297   ENUM_ENTRY(TYPE_M16_32,     "2+4-byte two-part memory operand (LIDT, LGDT)") \
 298   ENUM_ENTRY(TYPE_M16_16,     "2+2-byte (BOUND)")                              \
 299   ENUM_ENTRY(TYPE_M32_32,     "4+4-byte (BOUND)")                              \
 300   ENUM_ENTRY(TYPE_M16_64,     "2+8-byte (LIDT, LGDT)")                         \
 301   ENUM_ENTRY(TYPE_MOFFS8,     "1-byte memory offset (relative to segment "     \
 302                               "base)")                                         \
 303   ENUM_ENTRY(TYPE_MOFFS16,    "2-byte")                                        \
 304   ENUM_ENTRY(TYPE_MOFFS32,    "4-byte")                                        \
 305   ENUM_ENTRY(TYPE_MOFFS64,    "8-byte")                                        \
 306   ENUM_ENTRY(TYPE_SREG,       "Byte with single bit set: 0 = ES, 1 = CS, "     \
 307                               "2 = SS, 3 = DS, 4 = FS, 5 = GS")                \
 308   ENUM_ENTRY(TYPE_M32FP,      "32-bit IEE754 memory floating-point operand")   \
 309   ENUM_ENTRY(TYPE_M64FP,      "64-bit")                                        \
 310   ENUM_ENTRY(TYPE_M80FP,      "80-bit extended")                               \
 311   ENUM_ENTRY(TYPE_M16INT,     "2-byte memory integer operand for use in "      \
 312                               "floating-point instructions")                   \
 313   ENUM_ENTRY(TYPE_M32INT,     "4-byte")                                        \
 314   ENUM_ENTRY(TYPE_M64INT,     "8-byte")                                        \
 315   ENUM_ENTRY(TYPE_ST,         "Position on the floating-point stack")          \
 316   ENUM_ENTRY(TYPE_MM,         "MMX register operand")                          \
 317   ENUM_ENTRY(TYPE_MM32,       "4-byte MMX register or memory operand")         \
 318   ENUM_ENTRY(TYPE_MM64,       "8-byte")                                        \
 319   ENUM_ENTRY(TYPE_XMM,        "XMM register operand")                          \
 320   ENUM_ENTRY(TYPE_XMM32,      "4-byte XMM register or memory operand")         \
 321   ENUM_ENTRY(TYPE_XMM64,      "8-byte")                                        \
 322   ENUM_ENTRY(TYPE_XMM128,     "16-byte")                                       \
 323   ENUM_ENTRY(TYPE_XMM256,     "32-byte")                                       \
 324   ENUM_ENTRY(TYPE_XMM0,       "Implicit use of XMM0")                          \
 325   ENUM_ENTRY(TYPE_SEGMENTREG, "Segment register operand")                      \
 326   ENUM_ENTRY(TYPE_DEBUGREG,   "Debug register operand")                        \
 327   ENUM_ENTRY(TYPE_CONTROLREG, "Control register operand")                      \
 328                                                                                \
 329   ENUM_ENTRY(TYPE_Mv,         "Memory operand of operand size")                \
 330   ENUM_ENTRY(TYPE_Rv,         "Register operand of operand size")              \
 331   ENUM_ENTRY(TYPE_IMMv,       "Immediate operand of operand size")             \
 332   ENUM_ENTRY(TYPE_RELv,       "Immediate address of operand size")             \
 333   ENUM_ENTRY(TYPE_DUP0,       "Duplicate of operand 0")                        \
 334   ENUM_ENTRY(TYPE_DUP1,       "operand 1")                                     \
 335   ENUM_ENTRY(TYPE_DUP2,       "operand 2")                                     \
 336   ENUM_ENTRY(TYPE_DUP3,       "operand 3")                                     \
 337   ENUM_ENTRY(TYPE_DUP4,       "operand 4")                                     \
 338   ENUM_ENTRY(TYPE_M512,       "512-bit FPU/MMX/XMM/MXCSR state")
 339
 340 #define ENUM_ENTRY(n, d) n,
 341 typedef enum {
 342   TYPES
 343   TYPE_max
 344 } OperandType;
 345 #undef ENUM_ENTRY
 346
 347 /*
 348  * OperandSpecifier - The specification for how to extract and interpret one
 349  *   operand.
 350  */
 351 struct OperandSpecifier {
 352   uint8_t encoding;
 353   uint8_t type;
 354 };
 355
 356 /*
 357  * Indicates where the opcode modifier (if any) is to be found.  Extended
 358  * opcodes with AddRegFrm have the opcode modifier in the ModR/M byte.
 359  */
 360
 361 #define MODIFIER_TYPES        \
 362   ENUM_ENTRY(MODIFIER_NONE)   \
 363   ENUM_ENTRY(MODIFIER_OPCODE) \
 364   ENUM_ENTRY(MODIFIER_MODRM)
 365
 366 #define ENUM_ENTRY(n) n,
 367 typedef enum {
 368   MODIFIER_TYPES
 369   MODIFIER_max
 370 } ModifierType;
 371 #undef ENUM_ENTRY
 372
 373 #define X86_MAX_OPERANDS 5
 374
 375 /*
 376  * The specification for how to extract and interpret a full instruction and
 377  * its operands.
 378  */
 379 struct InstructionSpecifier {
 380   uint8_t modifierType;
 381   uint8_t modifierBase;
 382
 383   /* The macro below must be defined wherever this file is included. */
 384   INSTRUCTION_SPECIFIER_FIELDS
 385 };
 386
 387 /*
 388  * Decoding mode for the Intel disassembler.  16-bit, 32-bit, and 64-bit mode
 389  * are supported, and represent real mode, IA-32e, and IA-32e in 64-bit mode,
 390  * respectively.
 391  */
 392 typedef enum {
 393   MODE_16BIT,
 394   MODE_32BIT,
 395   MODE_64BIT
 396 } DisassemblerMode;
 397
 398 #endif