1 //===-- RegisterContextDarwin_x86_64.cpp ------------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
13 #include <stddef.h> // offsetof
16 // Other libraries and framework includes
17 #include "lldb/Core/DataBufferHeap.h"
18 #include "lldb/Core/DataExtractor.h"
19 #include "lldb/Core/Log.h"
20 #include "lldb/Core/RegisterValue.h"
21 #include "lldb/Core/Scalar.h"
22 #include "lldb/Host/Endian.h"
23 #include "llvm/Support/Compiler.h"
25 // Support building against older versions of LLVM, this macro was added
27 #ifndef LLVM_EXTENSION
28 #define LLVM_EXTENSION
32 #include "RegisterContextDarwin_x86_64.h"
35 using namespace lldb_private;
112 enum gcc_dwarf_regnums
114 gcc_dwarf_gpr_rax = 0,
192 gdb_fpu_fctrl = 32, gdb_fpu_fcw = gdb_fpu_fctrl,
193 gdb_fpu_fstat = 33, gdb_fpu_fsw = gdb_fpu_fstat,
194 gdb_fpu_ftag = 34, gdb_fpu_ftw = gdb_fpu_ftag,
195 gdb_fpu_fiseg = 35, gdb_fpu_cs = gdb_fpu_fiseg,
196 gdb_fpu_fioff = 36, gdb_fpu_ip = gdb_fpu_fioff,
197 gdb_fpu_foseg = 37, gdb_fpu_ds = gdb_fpu_foseg,
198 gdb_fpu_fooff = 38, gdb_fpu_dp = gdb_fpu_fooff,
219 RegisterContextDarwin_x86_64::RegisterContextDarwin_x86_64 (Thread &thread, uint32_t concrete_frame_idx) :
220 RegisterContext (thread, concrete_frame_idx),
226 for (i=0; i<kNumErrors; i++)
234 RegisterContextDarwin_x86_64::~RegisterContextDarwin_x86_64()
238 #define GPR_OFFSET(reg) (LLVM_EXTENSION offsetof (RegisterContextDarwin_x86_64::GPR, reg))
239 #define FPU_OFFSET(reg) (LLVM_EXTENSION offsetof (RegisterContextDarwin_x86_64::FPU, reg) + sizeof (RegisterContextDarwin_x86_64::GPR))
240 #define EXC_OFFSET(reg) (LLVM_EXTENSION offsetof (RegisterContextDarwin_x86_64::EXC, reg) + sizeof (RegisterContextDarwin_x86_64::GPR) + sizeof (RegisterContextDarwin_x86_64::FPU))
242 // These macros will auto define the register name, alt name, register size,
243 // register offset, encoding, format and native register. This ensures that
244 // the register state structures are defined correctly and have the correct
245 // sizes and offsets.
246 #define DEFINE_GPR(reg, alt) #reg, alt, sizeof(((RegisterContextDarwin_x86_64::GPR *)NULL)->reg), GPR_OFFSET(reg), eEncodingUint, eFormatHex
247 #define DEFINE_FPU_UINT(reg) #reg, NULL, sizeof(((RegisterContextDarwin_x86_64::FPU *)NULL)->reg), FPU_OFFSET(reg), eEncodingUint, eFormatHex
248 #define DEFINE_FPU_VECT(reg, i) #reg#i, NULL, sizeof(((RegisterContextDarwin_x86_64::FPU *)NULL)->reg[i].bytes), FPU_OFFSET(reg[i]), eEncodingVector, eFormatVectorOfUInt8, { gcc_dwarf_fpu_##reg##i, gcc_dwarf_fpu_##reg##i, LLDB_INVALID_REGNUM, gdb_fpu_##reg##i, fpu_##reg##i }, NULL, NULL
249 #define DEFINE_EXC(reg) #reg, NULL, sizeof(((RegisterContextDarwin_x86_64::EXC *)NULL)->reg), EXC_OFFSET(reg), eEncodingUint, eFormatHex
251 #define REG_CONTEXT_SIZE (sizeof (RegisterContextDarwin_x86_64::GPR) + sizeof (RegisterContextDarwin_x86_64::FPU) + sizeof (RegisterContextDarwin_x86_64::EXC))
253 // General purpose registers for 64 bit
254 static RegisterInfo g_register_infos[] =
256 // Macro auto defines most stuff GCC DWARF GENERIC GDB LLDB VALUE REGS INVALIDATE REGS
257 // =============================== ====================== =================== ========================== ==================== =================== ========== ===============
258 { DEFINE_GPR (rax , NULL) , { gcc_dwarf_gpr_rax , gcc_dwarf_gpr_rax , LLDB_INVALID_REGNUM , gdb_gpr_rax , gpr_rax }, NULL, NULL},
259 { DEFINE_GPR (rbx , NULL) , { gcc_dwarf_gpr_rbx , gcc_dwarf_gpr_rbx , LLDB_INVALID_REGNUM , gdb_gpr_rbx , gpr_rbx }, NULL, NULL},
260 { DEFINE_GPR (rcx , NULL) , { gcc_dwarf_gpr_rcx , gcc_dwarf_gpr_rcx , LLDB_INVALID_REGNUM , gdb_gpr_rcx , gpr_rcx }, NULL, NULL},
261 { DEFINE_GPR (rdx , NULL) , { gcc_dwarf_gpr_rdx , gcc_dwarf_gpr_rdx , LLDB_INVALID_REGNUM , gdb_gpr_rdx , gpr_rdx }, NULL, NULL},
262 { DEFINE_GPR (rdi , NULL) , { gcc_dwarf_gpr_rdi , gcc_dwarf_gpr_rdi , LLDB_INVALID_REGNUM , gdb_gpr_rdi , gpr_rdi }, NULL, NULL},
263 { DEFINE_GPR (rsi , NULL) , { gcc_dwarf_gpr_rsi , gcc_dwarf_gpr_rsi , LLDB_INVALID_REGNUM , gdb_gpr_rsi , gpr_rsi }, NULL, NULL},
264 { DEFINE_GPR (rbp , "fp") , { gcc_dwarf_gpr_rbp , gcc_dwarf_gpr_rbp , LLDB_REGNUM_GENERIC_FP , gdb_gpr_rbp , gpr_rbp }, NULL, NULL},
265 { DEFINE_GPR (rsp , "sp") , { gcc_dwarf_gpr_rsp , gcc_dwarf_gpr_rsp , LLDB_REGNUM_GENERIC_SP , gdb_gpr_rsp , gpr_rsp }, NULL, NULL},
266 { DEFINE_GPR (r8 , NULL) , { gcc_dwarf_gpr_r8 , gcc_dwarf_gpr_r8 , LLDB_INVALID_REGNUM , gdb_gpr_r8 , gpr_r8 }, NULL, NULL},
267 { DEFINE_GPR (r9 , NULL) , { gcc_dwarf_gpr_r9 , gcc_dwarf_gpr_r9 , LLDB_INVALID_REGNUM , gdb_gpr_r9 , gpr_r9 }, NULL, NULL},
268 { DEFINE_GPR (r10 , NULL) , { gcc_dwarf_gpr_r10 , gcc_dwarf_gpr_r10 , LLDB_INVALID_REGNUM , gdb_gpr_r10 , gpr_r10 }, NULL, NULL},
269 { DEFINE_GPR (r11 , NULL) , { gcc_dwarf_gpr_r11 , gcc_dwarf_gpr_r11 , LLDB_INVALID_REGNUM , gdb_gpr_r11 , gpr_r11 }, NULL, NULL},
270 { DEFINE_GPR (r12 , NULL) , { gcc_dwarf_gpr_r12 , gcc_dwarf_gpr_r12 , LLDB_INVALID_REGNUM , gdb_gpr_r12 , gpr_r12 }, NULL, NULL},
271 { DEFINE_GPR (r13 , NULL) , { gcc_dwarf_gpr_r13 , gcc_dwarf_gpr_r13 , LLDB_INVALID_REGNUM , gdb_gpr_r13 , gpr_r13 }, NULL, NULL},
272 { DEFINE_GPR (r14 , NULL) , { gcc_dwarf_gpr_r14 , gcc_dwarf_gpr_r14 , LLDB_INVALID_REGNUM , gdb_gpr_r14 , gpr_r14 }, NULL, NULL},
273 { DEFINE_GPR (r15 , NULL) , { gcc_dwarf_gpr_r15 , gcc_dwarf_gpr_r15 , LLDB_INVALID_REGNUM , gdb_gpr_r15 , gpr_r15 }, NULL, NULL},
274 { DEFINE_GPR (rip , "pc") , { gcc_dwarf_gpr_rip , gcc_dwarf_gpr_rip , LLDB_REGNUM_GENERIC_PC , gdb_gpr_rip , gpr_rip }, NULL, NULL},
275 { DEFINE_GPR (rflags, "flags") , { LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_REGNUM_GENERIC_FLAGS, gdb_gpr_rflags , gpr_rflags }, NULL, NULL},
276 { DEFINE_GPR (cs , NULL) , { LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM , gdb_gpr_cs , gpr_cs }, NULL, NULL},
277 { DEFINE_GPR (fs , NULL) , { LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM , gdb_gpr_fs , gpr_fs }, NULL, NULL},
278 { DEFINE_GPR (gs , NULL) , { LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM , gdb_gpr_gs , gpr_gs }, NULL, NULL},
280 { DEFINE_FPU_UINT(fcw) , { LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM , gdb_fpu_fcw , fpu_fcw }, NULL, NULL},
281 { DEFINE_FPU_UINT(fsw) , { LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM , gdb_fpu_fsw , fpu_fsw }, NULL, NULL},
282 { DEFINE_FPU_UINT(ftw) , { LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM , gdb_fpu_ftw , fpu_ftw }, NULL, NULL},
283 { DEFINE_FPU_UINT(fop) , { LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM , gdb_fpu_fop , fpu_fop }, NULL, NULL},
284 { DEFINE_FPU_UINT(ip) , { LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM , gdb_fpu_ip , fpu_ip }, NULL, NULL},
285 { DEFINE_FPU_UINT(cs) , { LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM , gdb_fpu_cs , fpu_cs }, NULL, NULL},
286 { DEFINE_FPU_UINT(dp) , { LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM , gdb_fpu_dp , fpu_dp }, NULL, NULL},
287 { DEFINE_FPU_UINT(ds) , { LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM , gdb_fpu_ds , fpu_ds }, NULL, NULL},
288 { DEFINE_FPU_UINT(mxcsr) , { LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM , gdb_fpu_mxcsr , fpu_mxcsr }, NULL, NULL},
289 { DEFINE_FPU_UINT(mxcsrmask) , { LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, fpu_mxcsrmask }, NULL, NULL},
290 { DEFINE_FPU_VECT(stmm,0) },
291 { DEFINE_FPU_VECT(stmm,1) },
292 { DEFINE_FPU_VECT(stmm,2) },
293 { DEFINE_FPU_VECT(stmm,3) },
294 { DEFINE_FPU_VECT(stmm,4) },
295 { DEFINE_FPU_VECT(stmm,5) },
296 { DEFINE_FPU_VECT(stmm,6) },
297 { DEFINE_FPU_VECT(stmm,7) },
298 { DEFINE_FPU_VECT(xmm,0) },
299 { DEFINE_FPU_VECT(xmm,1) },
300 { DEFINE_FPU_VECT(xmm,2) },
301 { DEFINE_FPU_VECT(xmm,3) },
302 { DEFINE_FPU_VECT(xmm,4) },
303 { DEFINE_FPU_VECT(xmm,5) },
304 { DEFINE_FPU_VECT(xmm,6) },
305 { DEFINE_FPU_VECT(xmm,7) },
306 { DEFINE_FPU_VECT(xmm,8) },
307 { DEFINE_FPU_VECT(xmm,9) },
308 { DEFINE_FPU_VECT(xmm,10) },
309 { DEFINE_FPU_VECT(xmm,11) },
310 { DEFINE_FPU_VECT(xmm,12) },
311 { DEFINE_FPU_VECT(xmm,13) },
312 { DEFINE_FPU_VECT(xmm,14) },
313 { DEFINE_FPU_VECT(xmm,15) },
315 { DEFINE_EXC(trapno) , { LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, exc_trapno }, NULL, NULL},
316 { DEFINE_EXC(err) , { LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, exc_err }, NULL, NULL},
317 { DEFINE_EXC(faultvaddr) , { LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM, exc_faultvaddr }, NULL, NULL}
320 static size_t k_num_register_infos = (sizeof(g_register_infos)/sizeof(RegisterInfo));
324 RegisterContextDarwin_x86_64::InvalidateAllRegisters ()
326 InvalidateAllRegisterStates();
331 RegisterContextDarwin_x86_64::GetRegisterCount ()
333 assert(k_num_register_infos == k_num_registers);
334 return k_num_registers;
339 RegisterContextDarwin_x86_64::GetRegisterInfoAtIndex (size_t reg)
341 assert(k_num_register_infos == k_num_registers);
342 if (reg < k_num_registers)
343 return &g_register_infos[reg];
349 RegisterContextDarwin_x86_64::GetRegisterInfosCount ()
351 return k_num_register_infos;
354 const lldb_private::RegisterInfo *
355 RegisterContextDarwin_x86_64::GetRegisterInfos ()
357 return g_register_infos;
362 static uint32_t g_gpr_regnums[] =
387 static uint32_t g_fpu_regnums[] =
433 // Number of registers in each register set
434 const size_t k_num_gpr_registers = sizeof(g_gpr_regnums) / sizeof(uint32_t);
435 const size_t k_num_fpu_registers = sizeof(g_fpu_regnums) / sizeof(uint32_t);
436 const size_t k_num_exc_registers = sizeof(g_exc_regnums) / sizeof(uint32_t);
438 //----------------------------------------------------------------------
439 // Register set definitions. The first definitions at register set index
440 // of zero is for all registers, followed by other registers sets. The
441 // register information for the all register set need not be filled in.
442 //----------------------------------------------------------------------
443 static const RegisterSet g_reg_sets[] =
445 { "General Purpose Registers", "gpr", k_num_gpr_registers, g_gpr_regnums, },
446 { "Floating Point Registers", "fpu", k_num_fpu_registers, g_fpu_regnums },
447 { "Exception State Registers", "exc", k_num_exc_registers, g_exc_regnums }
450 const size_t k_num_regsets = sizeof(g_reg_sets) / sizeof(RegisterSet);
454 RegisterContextDarwin_x86_64::GetRegisterSetCount ()
456 return k_num_regsets;
460 RegisterContextDarwin_x86_64::GetRegisterSet (size_t reg_set)
462 if (reg_set < k_num_regsets)
463 return &g_reg_sets[reg_set];
468 RegisterContextDarwin_x86_64::GetSetForNativeRegNum (int reg_num)
470 if (reg_num < fpu_fcw)
472 else if (reg_num < exc_trapno)
474 else if (reg_num < k_num_registers)
480 RegisterContextDarwin_x86_64::LogGPR(Log *log, const char *format, ...)
487 va_start (args, format);
488 log->VAPrintf (format, args);
491 for (uint32_t i=0; i<k_num_gpr_registers; i++)
493 uint32_t reg = gpr_rax + i;
494 log->Printf("%12s = 0x%16.16" PRIx64, g_register_infos[reg].name, (&gpr.rax)[reg]);
500 RegisterContextDarwin_x86_64::ReadGPR (bool force)
503 if (force || !RegisterSetIsCached(set))
505 SetError(set, Read, DoReadGPR(GetThreadID(), set, gpr));
507 return GetError(GPRRegSet, Read);
511 RegisterContextDarwin_x86_64::ReadFPU (bool force)
514 if (force || !RegisterSetIsCached(set))
516 SetError(set, Read, DoReadFPU(GetThreadID(), set, fpu));
518 return GetError(FPURegSet, Read);
522 RegisterContextDarwin_x86_64::ReadEXC (bool force)
525 if (force || !RegisterSetIsCached(set))
527 SetError(set, Read, DoReadEXC(GetThreadID(), set, exc));
529 return GetError(EXCRegSet, Read);
533 RegisterContextDarwin_x86_64::WriteGPR ()
536 if (!RegisterSetIsCached(set))
538 SetError (set, Write, -1);
541 SetError (set, Write, DoWriteGPR(GetThreadID(), set, gpr));
542 SetError (set, Read, -1);
543 return GetError (set, Write);
547 RegisterContextDarwin_x86_64::WriteFPU ()
550 if (!RegisterSetIsCached(set))
552 SetError (set, Write, -1);
555 SetError (set, Write, DoWriteFPU(GetThreadID(), set, fpu));
556 SetError (set, Read, -1);
557 return GetError (set, Write);
561 RegisterContextDarwin_x86_64::WriteEXC ()
564 if (!RegisterSetIsCached(set))
566 SetError (set, Write, -1);
569 SetError (set, Write, DoWriteEXC(GetThreadID(), set, exc));
570 SetError (set, Read, -1);
571 return GetError (set, Write);
575 RegisterContextDarwin_x86_64::ReadRegisterSet(uint32_t set, bool force)
579 case GPRRegSet: return ReadGPR (force);
580 case FPURegSet: return ReadFPU (force);
581 case EXCRegSet: return ReadEXC (force);
588 RegisterContextDarwin_x86_64::WriteRegisterSet(uint32_t set)
590 // Make sure we have a valid context to set.
593 case GPRRegSet: return WriteGPR ();
594 case FPURegSet: return WriteFPU ();
595 case EXCRegSet: return WriteEXC ();
603 RegisterContextDarwin_x86_64::ReadRegister (const RegisterInfo *reg_info,
604 RegisterValue &value)
606 const uint32_t reg = reg_info->kinds[eRegisterKindLLDB];
607 int set = RegisterContextDarwin_x86_64::GetSetForNativeRegNum (reg);
611 if (ReadRegisterSet(set, false) != 0)
637 value = (&gpr.rax)[reg - gpr_rax];
677 value = fpu.mxcsrmask;
688 value.SetBytes(fpu.stmm[reg - fpu_stmm0].bytes, reg_info->byte_size, lldb::endian::InlHostByteOrder());
707 value.SetBytes(fpu.xmm[reg - fpu_xmm0].bytes, reg_info->byte_size, lldb::endian::InlHostByteOrder());
719 value = exc.faultvaddr;
730 RegisterContextDarwin_x86_64::WriteRegister (const RegisterInfo *reg_info,
731 const RegisterValue &value)
733 const uint32_t reg = reg_info->kinds[eRegisterKindLLDB];
734 int set = RegisterContextDarwin_x86_64::GetSetForNativeRegNum (reg);
739 if (ReadRegisterSet(set, false) != 0)
765 (&gpr.rax)[reg - gpr_rax] = value.GetAsUInt64();
769 fpu.fcw = value.GetAsUInt16();
773 fpu.fsw = value.GetAsUInt16();
777 fpu.ftw = value.GetAsUInt8();
781 fpu.fop = value.GetAsUInt16();
785 fpu.ip = value.GetAsUInt32();
789 fpu.cs = value.GetAsUInt16();
793 fpu.dp = value.GetAsUInt32();
797 fpu.ds = value.GetAsUInt16();
801 fpu.mxcsr = value.GetAsUInt32();
805 fpu.mxcsrmask = value.GetAsUInt32();
816 ::memcpy (fpu.stmm[reg - fpu_stmm0].bytes, value.GetBytes(), value.GetByteSize());
835 ::memcpy (fpu.xmm[reg - fpu_xmm0].bytes, value.GetBytes(), value.GetByteSize());
839 exc.trapno = value.GetAsUInt32();
843 exc.err = value.GetAsUInt32();
847 exc.faultvaddr = value.GetAsUInt64();
853 return WriteRegisterSet(set) == 0;
857 RegisterContextDarwin_x86_64::ReadAllRegisterValues (lldb::DataBufferSP &data_sp)
859 data_sp.reset (new DataBufferHeap (REG_CONTEXT_SIZE, 0));
861 ReadGPR (false) == 0 &&
862 ReadFPU (false) == 0 &&
863 ReadEXC (false) == 0)
865 uint8_t *dst = data_sp->GetBytes();
866 ::memcpy (dst, &gpr, sizeof(gpr));
869 ::memcpy (dst, &fpu, sizeof(fpu));
872 ::memcpy (dst, &exc, sizeof(exc));
879 RegisterContextDarwin_x86_64::WriteAllRegisterValues (const lldb::DataBufferSP &data_sp)
881 if (data_sp && data_sp->GetByteSize() == REG_CONTEXT_SIZE)
883 const uint8_t *src = data_sp->GetBytes();
884 ::memcpy (&gpr, src, sizeof(gpr));
887 ::memcpy (&fpu, src, sizeof(fpu));
890 ::memcpy (&exc, src, sizeof(exc));
891 uint32_t success_count = 0;
898 return success_count == 3;
905 RegisterContextDarwin_x86_64::ConvertRegisterKindToRegisterNumber (uint32_t kind, uint32_t reg)
907 if (kind == eRegisterKindGeneric)
911 case LLDB_REGNUM_GENERIC_PC: return gpr_rip;
912 case LLDB_REGNUM_GENERIC_SP: return gpr_rsp;
913 case LLDB_REGNUM_GENERIC_FP: return gpr_rbp;
914 case LLDB_REGNUM_GENERIC_FLAGS: return gpr_rflags;
915 case LLDB_REGNUM_GENERIC_RA:
920 else if (kind == eRegisterKindGCC || kind == eRegisterKindDWARF)
924 case gcc_dwarf_gpr_rax: return gpr_rax;
925 case gcc_dwarf_gpr_rdx: return gpr_rdx;
926 case gcc_dwarf_gpr_rcx: return gpr_rcx;
927 case gcc_dwarf_gpr_rbx: return gpr_rbx;
928 case gcc_dwarf_gpr_rsi: return gpr_rsi;
929 case gcc_dwarf_gpr_rdi: return gpr_rdi;
930 case gcc_dwarf_gpr_rbp: return gpr_rbp;
931 case gcc_dwarf_gpr_rsp: return gpr_rsp;
932 case gcc_dwarf_gpr_r8: return gpr_r8;
933 case gcc_dwarf_gpr_r9: return gpr_r9;
934 case gcc_dwarf_gpr_r10: return gpr_r10;
935 case gcc_dwarf_gpr_r11: return gpr_r11;
936 case gcc_dwarf_gpr_r12: return gpr_r12;
937 case gcc_dwarf_gpr_r13: return gpr_r13;
938 case gcc_dwarf_gpr_r14: return gpr_r14;
939 case gcc_dwarf_gpr_r15: return gpr_r15;
940 case gcc_dwarf_gpr_rip: return gpr_rip;
941 case gcc_dwarf_fpu_xmm0: return fpu_xmm0;
942 case gcc_dwarf_fpu_xmm1: return fpu_xmm1;
943 case gcc_dwarf_fpu_xmm2: return fpu_xmm2;
944 case gcc_dwarf_fpu_xmm3: return fpu_xmm3;
945 case gcc_dwarf_fpu_xmm4: return fpu_xmm4;
946 case gcc_dwarf_fpu_xmm5: return fpu_xmm5;
947 case gcc_dwarf_fpu_xmm6: return fpu_xmm6;
948 case gcc_dwarf_fpu_xmm7: return fpu_xmm7;
949 case gcc_dwarf_fpu_xmm8: return fpu_xmm8;
950 case gcc_dwarf_fpu_xmm9: return fpu_xmm9;
951 case gcc_dwarf_fpu_xmm10: return fpu_xmm10;
952 case gcc_dwarf_fpu_xmm11: return fpu_xmm11;
953 case gcc_dwarf_fpu_xmm12: return fpu_xmm12;
954 case gcc_dwarf_fpu_xmm13: return fpu_xmm13;
955 case gcc_dwarf_fpu_xmm14: return fpu_xmm14;
956 case gcc_dwarf_fpu_xmm15: return fpu_xmm15;
957 case gcc_dwarf_fpu_stmm0: return fpu_stmm0;
958 case gcc_dwarf_fpu_stmm1: return fpu_stmm1;
959 case gcc_dwarf_fpu_stmm2: return fpu_stmm2;
960 case gcc_dwarf_fpu_stmm3: return fpu_stmm3;
961 case gcc_dwarf_fpu_stmm4: return fpu_stmm4;
962 case gcc_dwarf_fpu_stmm5: return fpu_stmm5;
963 case gcc_dwarf_fpu_stmm6: return fpu_stmm6;
964 case gcc_dwarf_fpu_stmm7: return fpu_stmm7;
969 else if (kind == eRegisterKindGDB)
973 case gdb_gpr_rax : return gpr_rax;
974 case gdb_gpr_rbx : return gpr_rbx;
975 case gdb_gpr_rcx : return gpr_rcx;
976 case gdb_gpr_rdx : return gpr_rdx;
977 case gdb_gpr_rsi : return gpr_rsi;
978 case gdb_gpr_rdi : return gpr_rdi;
979 case gdb_gpr_rbp : return gpr_rbp;
980 case gdb_gpr_rsp : return gpr_rsp;
981 case gdb_gpr_r8 : return gpr_r8;
982 case gdb_gpr_r9 : return gpr_r9;
983 case gdb_gpr_r10 : return gpr_r10;
984 case gdb_gpr_r11 : return gpr_r11;
985 case gdb_gpr_r12 : return gpr_r12;
986 case gdb_gpr_r13 : return gpr_r13;
987 case gdb_gpr_r14 : return gpr_r14;
988 case gdb_gpr_r15 : return gpr_r15;
989 case gdb_gpr_rip : return gpr_rip;
990 case gdb_gpr_rflags : return gpr_rflags;
991 case gdb_gpr_cs : return gpr_cs;
992 case gdb_gpr_ss : return gpr_gs; // HACK: For now for "ss", just copy what is in "gs"
993 case gdb_gpr_ds : return gpr_gs; // HACK: For now for "ds", just copy what is in "gs"
994 case gdb_gpr_es : return gpr_gs; // HACK: For now for "es", just copy what is in "gs"
995 case gdb_gpr_fs : return gpr_fs;
996 case gdb_gpr_gs : return gpr_gs;
997 case gdb_fpu_stmm0 : return fpu_stmm0;
998 case gdb_fpu_stmm1 : return fpu_stmm1;
999 case gdb_fpu_stmm2 : return fpu_stmm2;
1000 case gdb_fpu_stmm3 : return fpu_stmm3;
1001 case gdb_fpu_stmm4 : return fpu_stmm4;
1002 case gdb_fpu_stmm5 : return fpu_stmm5;
1003 case gdb_fpu_stmm6 : return fpu_stmm6;
1004 case gdb_fpu_stmm7 : return fpu_stmm7;
1005 case gdb_fpu_fctrl : return fpu_fctrl;
1006 case gdb_fpu_fstat : return fpu_fstat;
1007 case gdb_fpu_ftag : return fpu_ftag;
1008 case gdb_fpu_fiseg : return fpu_fiseg;
1009 case gdb_fpu_fioff : return fpu_fioff;
1010 case gdb_fpu_foseg : return fpu_foseg;
1011 case gdb_fpu_fooff : return fpu_fooff;
1012 case gdb_fpu_fop : return fpu_fop;
1013 case gdb_fpu_xmm0 : return fpu_xmm0;
1014 case gdb_fpu_xmm1 : return fpu_xmm1;
1015 case gdb_fpu_xmm2 : return fpu_xmm2;
1016 case gdb_fpu_xmm3 : return fpu_xmm3;
1017 case gdb_fpu_xmm4 : return fpu_xmm4;
1018 case gdb_fpu_xmm5 : return fpu_xmm5;
1019 case gdb_fpu_xmm6 : return fpu_xmm6;
1020 case gdb_fpu_xmm7 : return fpu_xmm7;
1021 case gdb_fpu_xmm8 : return fpu_xmm8;
1022 case gdb_fpu_xmm9 : return fpu_xmm9;
1023 case gdb_fpu_xmm10 : return fpu_xmm10;
1024 case gdb_fpu_xmm11 : return fpu_xmm11;
1025 case gdb_fpu_xmm12 : return fpu_xmm12;
1026 case gdb_fpu_xmm13 : return fpu_xmm13;
1027 case gdb_fpu_xmm14 : return fpu_xmm14;
1028 case gdb_fpu_xmm15 : return fpu_xmm15;
1029 case gdb_fpu_mxcsr : return fpu_mxcsr;
1034 else if (kind == eRegisterKindLLDB)
1038 return LLDB_INVALID_REGNUM;
1042 RegisterContextDarwin_x86_64::HardwareSingleStep (bool enable)
1044 if (ReadGPR(true) != 0)
1047 const uint64_t trace_bit = 0x100ull;
1051 if (gpr.rflags & trace_bit)
1052 return true; // trace bit is already set, there is nothing to do
1054 gpr.rflags |= trace_bit;
1058 if (gpr.rflags & trace_bit)
1059 gpr.rflags &= ~trace_bit;
1061 return true; // trace bit is clear, there is nothing to do
1064 return WriteGPR() == 0;