contrib/llvm/tools/lldb/source/Utility/ARM_DWARF_Registers.h

   1 //===-- ARM_DWARF_Registers.h -----------------------------------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9
  10 #ifndef utility_ARM_DWARF_Registers_h_
  11 #define utility_ARM_DWARF_Registers_h_
  12
  13 #include "lldb/lldb-private.h"
  14
  15 enum
  16 {
  17     dwarf_r0 = 0,
  18     dwarf_r1,
  19     dwarf_r2,
  20     dwarf_r3,
  21     dwarf_r4,
  22     dwarf_r5,
  23     dwarf_r6,
  24     dwarf_r7,
  25     dwarf_r8,
  26     dwarf_r9,
  27     dwarf_r10,
  28     dwarf_r11,
  29     dwarf_r12,
  30     dwarf_sp,
  31     dwarf_lr,
  32     dwarf_pc,
  33     dwarf_cpsr,
  34
  35     dwarf_s0 = 64,
  36     dwarf_s1,
  37     dwarf_s2,
  38     dwarf_s3,
  39     dwarf_s4,
  40     dwarf_s5,
  41     dwarf_s6,
  42     dwarf_s7,
  43     dwarf_s8,
  44     dwarf_s9,
  45     dwarf_s10,
  46     dwarf_s11,
  47     dwarf_s12,
  48     dwarf_s13,
  49     dwarf_s14,
  50     dwarf_s15,
  51     dwarf_s16,
  52     dwarf_s17,
  53     dwarf_s18,
  54     dwarf_s19,
  55     dwarf_s20,
  56     dwarf_s21,
  57     dwarf_s22,
  58     dwarf_s23,
  59     dwarf_s24,
  60     dwarf_s25,
  61     dwarf_s26,
  62     dwarf_s27,
  63     dwarf_s28,
  64     dwarf_s29,
  65     dwarf_s30,
  66     dwarf_s31,
  67
  68     // FPA Registers 0-7
  69     dwarf_f0 = 96,
  70     dwarf_f1,
  71     dwarf_f2,
  72     dwarf_f3,
  73     dwarf_f4,
  74     dwarf_f5,
  75     dwarf_f6,
  76     dwarf_f7,
  77
  78     // Intel wireless MMX general purpose registers 0 - 7
  79     dwarf_wCGR0 = 104,
  80     dwarf_wCGR1,
  81     dwarf_wCGR2,
  82     dwarf_wCGR3,
  83     dwarf_wCGR4,
  84     dwarf_wCGR5,
  85     dwarf_wCGR6,
  86     dwarf_wCGR7,
  87
  88     // XScale accumulator register 0 - 7 (they do overlap with wCGR0 - wCGR7)
  89     dwarf_ACC0 = 104,
  90     dwarf_ACC1,
  91     dwarf_ACC2,
  92     dwarf_ACC3,
  93     dwarf_ACC4,
  94     dwarf_ACC5,
  95     dwarf_ACC6,
  96     dwarf_ACC7,
  97
  98     // Intel wireless MMX data registers 0 - 15
  99     dwarf_wR0 = 112,
 100     dwarf_wR1,
 101     dwarf_wR2,
 102     dwarf_wR3,
 103     dwarf_wR4,
 104     dwarf_wR5,
 105     dwarf_wR6,
 106     dwarf_wR7,
 107     dwarf_wR8,
 108     dwarf_wR9,
 109     dwarf_wR10,
 110     dwarf_wR11,
 111     dwarf_wR12,
 112     dwarf_wR13,
 113     dwarf_wR14,
 114     dwarf_wR15,
 115
 116     dwarf_spsr = 128,
 117     dwarf_spsr_fiq,
 118     dwarf_spsr_irq,
 119     dwarf_spsr_abt,
 120     dwarf_spsr_und,
 121     dwarf_spsr_svc,
 122
 123     dwarf_r8_usr = 144,
 124     dwarf_r9_usr,
 125     dwarf_r10_usr,
 126     dwarf_r11_usr,
 127     dwarf_r12_usr,
 128     dwarf_r13_usr,
 129     dwarf_r14_usr,
 130     dwarf_r8_fiq,
 131     dwarf_r9_fiq,
 132     dwarf_r10_fiq,
 133     dwarf_r11_fiq,
 134     dwarf_r12_fiq,
 135     dwarf_r13_fiq,
 136     dwarf_r14_fiq,
 137     dwarf_r13_irq,
 138     dwarf_r14_irq,
 139     dwarf_r13_abt,
 140     dwarf_r14_abt,
 141     dwarf_r13_und,
 142     dwarf_r14_und,
 143     dwarf_r13_svc,
 144     dwarf_r14_svc,
 145
 146     // Intel wireless MMX control register in co-processor 0 - 7
 147     dwarf_wC0 = 192,
 148     dwarf_wC1,
 149     dwarf_wC2,
 150     dwarf_wC3,
 151     dwarf_wC4,
 152     dwarf_wC5,
 153     dwarf_wC6,
 154     dwarf_wC7,
 155
 156     // VFP-v3/Neon
 157     dwarf_d0 = 256,
 158     dwarf_d1,
 159     dwarf_d2,
 160     dwarf_d3,
 161     dwarf_d4,
 162     dwarf_d5,
 163     dwarf_d6,
 164     dwarf_d7,
 165     dwarf_d8,
 166     dwarf_d9,
 167     dwarf_d10,
 168     dwarf_d11,
 169     dwarf_d12,
 170     dwarf_d13,
 171     dwarf_d14,
 172     dwarf_d15,
 173     dwarf_d16,
 174     dwarf_d17,
 175     dwarf_d18,
 176     dwarf_d19,
 177     dwarf_d20,
 178     dwarf_d21,
 179     dwarf_d22,
 180     dwarf_d23,
 181     dwarf_d24,
 182     dwarf_d25,
 183     dwarf_d26,
 184     dwarf_d27,
 185     dwarf_d28,
 186     dwarf_d29,
 187     dwarf_d30,
 188     dwarf_d31,
 189
 190     // Neon quadword registers
 191     dwarf_q0 = 288,
 192     dwarf_q1,
 193     dwarf_q2,
 194     dwarf_q3,
 195     dwarf_q4,
 196     dwarf_q5,
 197     dwarf_q6,
 198     dwarf_q7,
 199     dwarf_q8,
 200     dwarf_q9,
 201     dwarf_q10,
 202     dwarf_q11,
 203     dwarf_q12,
 204     dwarf_q13,
 205     dwarf_q14,
 206     dwarf_q15
 207 };
 208
 209 const char *
 210 GetARMDWARFRegisterName (unsigned reg_num);
 211
 212 bool
 213 GetARMDWARFRegisterInfo (unsigned reg_num,
 214                          lldb_private::RegisterInfo &reg_info);
 215
 216 #endif // utility_ARM_DWARF_Registers_h_
 217