lib/libpmc/libpmc.c

   1 /*-
   2  * Copyright (c) 2003-2008 Joseph Koshy
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  24  * SUCH DAMAGE.
  25  */
  26
  27 #include <sys/cdefs.h>
  28 __FBSDID("$FreeBSD$");
  29
  30 #include <sys/types.h>
  31 #include <sys/module.h>
  32 #include <sys/pmc.h>
  33 #include <sys/syscall.h>
  34
  35 #include <ctype.h>
  36 #include <errno.h>
  37 #include <fcntl.h>
  38 #include <pmc.h>
  39 #include <stdio.h>
  40 #include <stdlib.h>
  41 #include <string.h>
  42 #include <strings.h>
  43 #include <unistd.h>
  44
  45 #include "libpmcinternal.h"
  46
  47 /* Function prototypes */
  48 #if defined(__i386__)
  49 static int k7_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
  50     struct pmc_op_pmcallocate *_pmc_config);
  51 #endif
  52 #if defined(__amd64__) || defined(__i386__)
  53 static int iaf_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
  54     struct pmc_op_pmcallocate *_pmc_config);
  55 static int iap_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
  56     struct pmc_op_pmcallocate *_pmc_config);
  57 static int ucf_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
  58     struct pmc_op_pmcallocate *_pmc_config);
  59 static int ucp_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
  60     struct pmc_op_pmcallocate *_pmc_config);
  61 static int k8_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
  62     struct pmc_op_pmcallocate *_pmc_config);
  63 static int p4_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
  64     struct pmc_op_pmcallocate *_pmc_config);
  65 #endif
  66 #if defined(__i386__)
  67 static int p5_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
  68     struct pmc_op_pmcallocate *_pmc_config);
  69 static int p6_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
  70     struct pmc_op_pmcallocate *_pmc_config);
  71 #endif
  72 #if defined(__amd64__) || defined(__i386__)
  73 static int tsc_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
  74     struct pmc_op_pmcallocate *_pmc_config);
  75 #endif
  76 #if defined(__XSCALE__)
  77 static int xscale_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
  78     struct pmc_op_pmcallocate *_pmc_config);
  79 #endif
  80 #if defined(__mips__)
  81 static int mips_allocate_pmc(enum pmc_event _pe, char* ctrspec,
  82                              struct pmc_op_pmcallocate *_pmc_config);
  83 #endif /* __mips__ */
  84 static int soft_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
  85     struct pmc_op_pmcallocate *_pmc_config);
  86
  87 #if defined(__powerpc__)
  88 static int ppc7450_allocate_pmc(enum pmc_event _pe, char* ctrspec,
  89                              struct pmc_op_pmcallocate *_pmc_config);
  90 #endif /* __powerpc__ */
  91
  92 #define PMC_CALL(cmd, params)                           \
  93         syscall(pmc_syscall, PMC_OP_##cmd, (params))
  94
  95 /*
  96  * Event aliases provide a way for the user to ask for generic events
  97  * like "cache-misses", or "instructions-retired".  These aliases are
  98  * mapped to the appropriate canonical event descriptions using a
  99  * lookup table.
 100  */
 101 struct pmc_event_alias {
 102         const char      *pm_alias;
 103         const char      *pm_spec;
 104 };
 105
 106 static const struct pmc_event_alias *pmc_mdep_event_aliases;
 107
 108 /*
 109  * The pmc_event_descr structure maps symbolic names known to the user
 110  * to integer codes used by the PMC KLD.
 111  */
 112 struct pmc_event_descr {
 113         const char      *pm_ev_name;
 114         enum pmc_event  pm_ev_code;
 115 };
 116
 117 /*
 118  * The pmc_class_descr structure maps class name prefixes for
 119  * event names to event tables and other PMC class data.
 120  */
 121 struct pmc_class_descr {
 122         const char      *pm_evc_name;
 123         size_t          pm_evc_name_size;
 124         enum pmc_class  pm_evc_class;
 125         const struct pmc_event_descr *pm_evc_event_table;
 126         size_t          pm_evc_event_table_size;
 127         int             (*pm_evc_allocate_pmc)(enum pmc_event _pe,
 128                             char *_ctrspec, struct pmc_op_pmcallocate *_pa);
 129 };
 130
 131 #define PMC_TABLE_SIZE(N)       (sizeof(N)/sizeof(N[0]))
 132 #define PMC_EVENT_TABLE_SIZE(N) PMC_TABLE_SIZE(N##_event_table)
 133
 134 #undef  __PMC_EV
 135 #define __PMC_EV(C,N) { #N, PMC_EV_ ## C ## _ ## N },
 136
 137 /*
 138  * PMC_CLASSDEP_TABLE(NAME, CLASS)
 139  *
 140  * Define a table mapping event names and aliases to HWPMC event IDs.
 141  */
 142 #define PMC_CLASSDEP_TABLE(N, C)                                \
 143         static const struct pmc_event_descr N##_event_table[] = \
 144         {                                                       \
 145                 __PMC_EV_##C()                                  \
 146         }
 147
 148 PMC_CLASSDEP_TABLE(iaf, IAF);
 149 PMC_CLASSDEP_TABLE(k7, K7);
 150 PMC_CLASSDEP_TABLE(k8, K8);
 151 PMC_CLASSDEP_TABLE(p4, P4);
 152 PMC_CLASSDEP_TABLE(p5, P5);
 153 PMC_CLASSDEP_TABLE(p6, P6);
 154 PMC_CLASSDEP_TABLE(xscale, XSCALE);
 155 PMC_CLASSDEP_TABLE(mips24k, MIPS24K);
 156 PMC_CLASSDEP_TABLE(octeon, OCTEON);
 157 PMC_CLASSDEP_TABLE(ucf, UCF);
 158 PMC_CLASSDEP_TABLE(ppc7450, PPC7450);
 159
 160 static struct pmc_event_descr soft_event_table[PMC_EV_DYN_COUNT];
 161
 162 #undef  __PMC_EV_ALIAS
 163 #define __PMC_EV_ALIAS(N,CODE)  { N, PMC_EV_##CODE },
 164
 165 static const struct pmc_event_descr atom_event_table[] =
 166 {
 167         __PMC_EV_ALIAS_ATOM()
 168 };
 169
 170 static const struct pmc_event_descr core_event_table[] =
 171 {
 172         __PMC_EV_ALIAS_CORE()
 173 };
 174
 175
 176 static const struct pmc_event_descr core2_event_table[] =
 177 {
 178         __PMC_EV_ALIAS_CORE2()
 179 };
 180
 181 static const struct pmc_event_descr corei7_event_table[] =
 182 {
 183         __PMC_EV_ALIAS_COREI7()
 184 };
 185
 186 static const struct pmc_event_descr haswell_event_table[] =
 187 {
 188         __PMC_EV_ALIAS_HASWELL()
 189 };
 190
 191 static const struct pmc_event_descr ivybridge_event_table[] =
 192 {
 193         __PMC_EV_ALIAS_IVYBRIDGE()
 194 };
 195
 196 static const struct pmc_event_descr ivybridge_xeon_event_table[] =
 197 {
 198         __PMC_EV_ALIAS_IVYBRIDGE_XEON()
 199 };
 200
 201 static const struct pmc_event_descr sandybridge_event_table[] =
 202 {
 203         __PMC_EV_ALIAS_SANDYBRIDGE()
 204 };
 205
 206 static const struct pmc_event_descr sandybridge_xeon_event_table[] =
 207 {
 208         __PMC_EV_ALIAS_SANDYBRIDGE_XEON()
 209 };
 210
 211 static const struct pmc_event_descr westmere_event_table[] =
 212 {
 213         __PMC_EV_ALIAS_WESTMERE()
 214 };
 215
 216 static const struct pmc_event_descr corei7uc_event_table[] =
 217 {
 218         __PMC_EV_ALIAS_COREI7UC()
 219 };
 220
 221 static const struct pmc_event_descr haswelluc_event_table[] =
 222 {
 223         __PMC_EV_ALIAS_HASWELLUC()
 224 };
 225
 226 static const struct pmc_event_descr sandybridgeuc_event_table[] =
 227 {
 228         __PMC_EV_ALIAS_SANDYBRIDGEUC()
 229 };
 230
 231 static const struct pmc_event_descr westmereuc_event_table[] =
 232 {
 233         __PMC_EV_ALIAS_WESTMEREUC()
 234 };
 235
 236 /*
 237  * PMC_MDEP_TABLE(NAME, PRIMARYCLASS, ADDITIONAL_CLASSES...)
 238  *
 239  * Map a CPU to the PMC classes it supports.
 240  */
 241 #define PMC_MDEP_TABLE(N,C,...)                         \
 242         static const enum pmc_class N##_pmc_classes[] = {       \
 243                 PMC_CLASS_##C, __VA_ARGS__                      \
 244         }
 245
 246 PMC_MDEP_TABLE(atom, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC);
 247 PMC_MDEP_TABLE(core, IAP, PMC_CLASS_SOFT, PMC_CLASS_TSC);
 248 PMC_MDEP_TABLE(core2, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC);
 249 PMC_MDEP_TABLE(corei7, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP);
 250 PMC_MDEP_TABLE(haswell, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP);
 251 PMC_MDEP_TABLE(ivybridge, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC);
 252 PMC_MDEP_TABLE(ivybridge_xeon, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC);
 253 PMC_MDEP_TABLE(sandybridge, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP);
 254 PMC_MDEP_TABLE(sandybridge_xeon, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC);
 255 PMC_MDEP_TABLE(westmere, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP);
 256 PMC_MDEP_TABLE(k7, K7, PMC_CLASS_SOFT, PMC_CLASS_TSC);
 257 PMC_MDEP_TABLE(k8, K8, PMC_CLASS_SOFT, PMC_CLASS_TSC);
 258 PMC_MDEP_TABLE(p4, P4, PMC_CLASS_SOFT, PMC_CLASS_TSC);
 259 PMC_MDEP_TABLE(p5, P5, PMC_CLASS_SOFT, PMC_CLASS_TSC);
 260 PMC_MDEP_TABLE(p6, P6, PMC_CLASS_SOFT, PMC_CLASS_TSC);
 261 PMC_MDEP_TABLE(xscale, XSCALE, PMC_CLASS_SOFT, PMC_CLASS_XSCALE);
 262 PMC_MDEP_TABLE(mips24k, MIPS24K, PMC_CLASS_SOFT, PMC_CLASS_MIPS24K);
 263 PMC_MDEP_TABLE(octeon, OCTEON, PMC_CLASS_SOFT, PMC_CLASS_OCTEON);
 264 PMC_MDEP_TABLE(ppc7450, PPC7450, PMC_CLASS_SOFT, PMC_CLASS_PPC7450);
 265 PMC_MDEP_TABLE(generic, SOFT, PMC_CLASS_SOFT);
 266
 267 static const struct pmc_event_descr tsc_event_table[] =
 268 {
 269         __PMC_EV_TSC()
 270 };
 271
 272 #undef  PMC_CLASS_TABLE_DESC
 273 #define PMC_CLASS_TABLE_DESC(NAME, CLASS, EVENTS, ALLOCATOR)    \
 274 static const struct pmc_class_descr NAME##_class_table_descr =  \
 275         {                                                       \
 276                 .pm_evc_name  = #CLASS "-",                     \
 277                 .pm_evc_name_size = sizeof(#CLASS "-") - 1,     \
 278                 .pm_evc_class = PMC_CLASS_##CLASS ,             \
 279                 .pm_evc_event_table = EVENTS##_event_table ,    \
 280                 .pm_evc_event_table_size =                      \
 281                         PMC_EVENT_TABLE_SIZE(EVENTS),           \
 282                 .pm_evc_allocate_pmc = ALLOCATOR##_allocate_pmc \
 283         }
 284
 285 #if     defined(__i386__) || defined(__amd64__)
 286 PMC_CLASS_TABLE_DESC(iaf, IAF, iaf, iaf);
 287 PMC_CLASS_TABLE_DESC(atom, IAP, atom, iap);
 288 PMC_CLASS_TABLE_DESC(core, IAP, core, iap);
 289 PMC_CLASS_TABLE_DESC(core2, IAP, core2, iap);
 290 PMC_CLASS_TABLE_DESC(corei7, IAP, corei7, iap);
 291 PMC_CLASS_TABLE_DESC(haswell, IAP, haswell, iap);
 292 PMC_CLASS_TABLE_DESC(ivybridge, IAP, ivybridge, iap);
 293 PMC_CLASS_TABLE_DESC(ivybridge_xeon, IAP, ivybridge_xeon, iap);
 294 PMC_CLASS_TABLE_DESC(sandybridge, IAP, sandybridge, iap);
 295 PMC_CLASS_TABLE_DESC(sandybridge_xeon, IAP, sandybridge_xeon, iap);
 296 PMC_CLASS_TABLE_DESC(westmere, IAP, westmere, iap);
 297 PMC_CLASS_TABLE_DESC(ucf, UCF, ucf, ucf);
 298 PMC_CLASS_TABLE_DESC(corei7uc, UCP, corei7uc, ucp);
 299 PMC_CLASS_TABLE_DESC(haswelluc, UCP, haswelluc, ucp);
 300 PMC_CLASS_TABLE_DESC(sandybridgeuc, UCP, sandybridgeuc, ucp);
 301 PMC_CLASS_TABLE_DESC(westmereuc, UCP, westmereuc, ucp);
 302 #endif
 303 #if     defined(__i386__)
 304 PMC_CLASS_TABLE_DESC(k7, K7, k7, k7);
 305 #endif
 306 #if     defined(__i386__) || defined(__amd64__)
 307 PMC_CLASS_TABLE_DESC(k8, K8, k8, k8);
 308 PMC_CLASS_TABLE_DESC(p4, P4, p4, p4);
 309 #endif
 310 #if     defined(__i386__)
 311 PMC_CLASS_TABLE_DESC(p5, P5, p5, p5);
 312 PMC_CLASS_TABLE_DESC(p6, P6, p6, p6);
 313 #endif
 314 #if     defined(__i386__) || defined(__amd64__)
 315 PMC_CLASS_TABLE_DESC(tsc, TSC, tsc, tsc);
 316 #endif
 317 #if     defined(__XSCALE__)
 318 PMC_CLASS_TABLE_DESC(xscale, XSCALE, xscale, xscale);
 319 #endif
 320 #if defined(__mips__)
 321 PMC_CLASS_TABLE_DESC(mips24k, MIPS24K, mips24k, mips);
 322 PMC_CLASS_TABLE_DESC(octeon, OCTEON, octeon, mips);
 323 #endif /* __mips__ */
 324 #if defined(__powerpc__)
 325 PMC_CLASS_TABLE_DESC(ppc7450, PPC7450, ppc7450, ppc7450);
 326 #endif
 327
 328 static struct pmc_class_descr soft_class_table_descr =
 329 {
 330         .pm_evc_name  = "SOFT-",
 331         .pm_evc_name_size = sizeof("SOFT-") - 1,
 332         .pm_evc_class = PMC_CLASS_SOFT,
 333         .pm_evc_event_table = NULL,
 334         .pm_evc_event_table_size = 0,
 335         .pm_evc_allocate_pmc = soft_allocate_pmc
 336 };
 337
 338 #undef  PMC_CLASS_TABLE_DESC
 339
 340 static const struct pmc_class_descr **pmc_class_table;
 341 #define PMC_CLASS_TABLE_SIZE    cpu_info.pm_nclass
 342
 343 static const enum pmc_class *pmc_mdep_class_list;
 344 static size_t pmc_mdep_class_list_size;
 345
 346 /*
 347  * Mapping tables, mapping enumeration values to human readable
 348  * strings.
 349  */
 350
 351 static const char * pmc_capability_names[] = {
 352 #undef  __PMC_CAP
 353 #define __PMC_CAP(N,V,D)        #N ,
 354         __PMC_CAPS()
 355 };
 356
 357 static const char * pmc_class_names[] = {
 358 #undef  __PMC_CLASS
 359 #define __PMC_CLASS(C)  #C ,
 360         __PMC_CLASSES()
 361 };
 362
 363 struct pmc_cputype_map {
 364         enum pmc_cputype pm_cputype;
 365         const char      *pm_name;
 366 };
 367
 368 static const struct pmc_cputype_map pmc_cputype_names[] = {
 369 #undef  __PMC_CPU
 370 #define __PMC_CPU(S, V, D) { .pm_cputype = PMC_CPU_##S, .pm_name = #S } ,
 371         __PMC_CPUS()
 372 };
 373
 374 static const char * pmc_disposition_names[] = {
 375 #undef  __PMC_DISP
 376 #define __PMC_DISP(D)   #D ,
 377         __PMC_DISPOSITIONS()
 378 };
 379
 380 static const char * pmc_mode_names[] = {
 381 #undef  __PMC_MODE
 382 #define __PMC_MODE(M,N) #M ,
 383         __PMC_MODES()
 384 };
 385
 386 static const char * pmc_state_names[] = {
 387 #undef  __PMC_STATE
 388 #define __PMC_STATE(S) #S ,
 389         __PMC_STATES()
 390 };
 391
 392 /*
 393  * Filled in by pmc_init().
 394  */
 395 static int pmc_syscall = -1;
 396 static struct pmc_cpuinfo cpu_info;
 397 static struct pmc_op_getdyneventinfo soft_event_info;
 398
 399 /* Event masks for events */
 400 struct pmc_masks {
 401         const char      *pm_name;
 402         const uint64_t  pm_value;
 403 };
 404 #define PMCMASK(N,V)    { .pm_name = #N, .pm_value = (V) }
 405 #define NULLMASK        { .pm_name = NULL }
 406
 407 #if defined(__amd64__) || defined(__i386__)
 408 static int
 409 pmc_parse_mask(const struct pmc_masks *pmask, char *p, uint64_t *evmask)
 410 {
 411         const struct pmc_masks *pm;
 412         char *q, *r;
 413         int c;
 414
 415         if (pmask == NULL)      /* no mask keywords */
 416                 return (-1);
 417         q = strchr(p, '=');     /* skip '=' */
 418         if (*++q == '\0')       /* no more data */
 419                 return (-1);
 420         c = 0;                  /* count of mask keywords seen */
 421         while ((r = strsep(&q, "+")) != NULL) {
 422                 for (pm = pmask; pm->pm_name && strcasecmp(r, pm->pm_name);
 423                     pm++)
 424                         ;
 425                 if (pm->pm_name == NULL) /* not found */
 426                         return (-1);
 427                 *evmask |= pm->pm_value;
 428                 c++;
 429         }
 430         return (c);
 431 }
 432 #endif
 433
 434 #define KWMATCH(p,kw)           (strcasecmp((p), (kw)) == 0)
 435 #define KWPREFIXMATCH(p,kw)     (strncasecmp((p), (kw), sizeof((kw)) - 1) == 0)
 436 #define EV_ALIAS(N,S)           { .pm_alias = N, .pm_spec = S }
 437
 438 #if defined(__i386__)
 439
 440 /*
 441  * AMD K7 (Athlon) CPUs.
 442  */
 443
 444 static struct pmc_event_alias k7_aliases[] = {
 445         EV_ALIAS("branches",            "k7-retired-branches"),
 446         EV_ALIAS("branch-mispredicts",  "k7-retired-branches-mispredicted"),
 447         EV_ALIAS("cycles",              "tsc"),
 448         EV_ALIAS("dc-misses",           "k7-dc-misses"),
 449         EV_ALIAS("ic-misses",           "k7-ic-misses"),
 450         EV_ALIAS("instructions",        "k7-retired-instructions"),
 451         EV_ALIAS("interrupts",          "k7-hardware-interrupts"),
 452         EV_ALIAS(NULL, NULL)
 453 };
 454
 455 #define K7_KW_COUNT     "count"
 456 #define K7_KW_EDGE      "edge"
 457 #define K7_KW_INV       "inv"
 458 #define K7_KW_OS        "os"
 459 #define K7_KW_UNITMASK  "unitmask"
 460 #define K7_KW_USR       "usr"
 461
 462 static int
 463 k7_allocate_pmc(enum pmc_event pe, char *ctrspec,
 464     struct pmc_op_pmcallocate *pmc_config)
 465 {
 466         char            *e, *p, *q;
 467         int             c, has_unitmask;
 468         uint32_t        count, unitmask;
 469
 470         pmc_config->pm_md.pm_amd.pm_amd_config = 0;
 471         pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
 472
 473         if (pe == PMC_EV_K7_DC_REFILLS_FROM_L2 ||
 474             pe == PMC_EV_K7_DC_REFILLS_FROM_SYSTEM ||
 475             pe == PMC_EV_K7_DC_WRITEBACKS) {
 476                 has_unitmask = 1;
 477                 unitmask = AMD_PMC_UNITMASK_MOESI;
 478         } else
 479                 unitmask = has_unitmask = 0;
 480
 481         while ((p = strsep(&ctrspec, ",")) != NULL) {
 482                 if (KWPREFIXMATCH(p, K7_KW_COUNT "=")) {
 483                         q = strchr(p, '=');
 484                         if (*++q == '\0') /* skip '=' */
 485                                 return (-1);
 486
 487                         count = strtol(q, &e, 0);
 488                         if (e == q || *e != '\0')
 489                                 return (-1);
 490
 491                         pmc_config->pm_caps |= PMC_CAP_THRESHOLD;
 492                         pmc_config->pm_md.pm_amd.pm_amd_config |=
 493                             AMD_PMC_TO_COUNTER(count);
 494
 495                 } else if (KWMATCH(p, K7_KW_EDGE)) {
 496                         pmc_config->pm_caps |= PMC_CAP_EDGE;
 497                 } else if (KWMATCH(p, K7_KW_INV)) {
 498                         pmc_config->pm_caps |= PMC_CAP_INVERT;
 499                 } else if (KWMATCH(p, K7_KW_OS)) {
 500                         pmc_config->pm_caps |= PMC_CAP_SYSTEM;
 501                 } else if (KWPREFIXMATCH(p, K7_KW_UNITMASK "=")) {
 502                         if (has_unitmask == 0)
 503                                 return (-1);
 504                         unitmask = 0;
 505                         q = strchr(p, '=');
 506                         if (*++q == '\0') /* skip '=' */
 507                                 return (-1);
 508
 509                         while ((c = tolower(*q++)) != 0)
 510                                 if (c == 'm')
 511                                         unitmask |= AMD_PMC_UNITMASK_M;
 512                                 else if (c == 'o')
 513                                         unitmask |= AMD_PMC_UNITMASK_O;
 514                                 else if (c == 'e')
 515                                         unitmask |= AMD_PMC_UNITMASK_E;
 516                                 else if (c == 's')
 517                                         unitmask |= AMD_PMC_UNITMASK_S;
 518                                 else if (c == 'i')
 519                                         unitmask |= AMD_PMC_UNITMASK_I;
 520                                 else if (c == '+')
 521                                         continue;
 522                                 else
 523                                         return (-1);
 524
 525                         if (unitmask == 0)
 526                                 return (-1);
 527
 528                 } else if (KWMATCH(p, K7_KW_USR)) {
 529                         pmc_config->pm_caps |= PMC_CAP_USER;
 530                 } else
 531                         return (-1);
 532         }
 533
 534         if (has_unitmask) {
 535                 pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
 536                 pmc_config->pm_md.pm_amd.pm_amd_config |=
 537                     AMD_PMC_TO_UNITMASK(unitmask);
 538         }
 539
 540         return (0);
 541
 542 }
 543
 544 #endif
 545
 546 #if defined(__amd64__) || defined(__i386__)
 547
 548 /*
 549  * Intel Core (Family 6, Model E) PMCs.
 550  */
 551
 552 static struct pmc_event_alias core_aliases[] = {
 553         EV_ALIAS("branches",            "iap-br-instr-ret"),
 554         EV_ALIAS("branch-mispredicts",  "iap-br-mispred-ret"),
 555         EV_ALIAS("cycles",              "tsc-tsc"),
 556         EV_ALIAS("ic-misses",           "iap-icache-misses"),
 557         EV_ALIAS("instructions",        "iap-instr-ret"),
 558         EV_ALIAS("interrupts",          "iap-core-hw-int-rx"),
 559         EV_ALIAS("unhalted-cycles",     "iap-unhalted-core-cycles"),
 560         EV_ALIAS(NULL, NULL)
 561 };
 562
 563 /*
 564  * Intel Core2 (Family 6, Model F), Core2Extreme (Family 6, Model 17H)
 565  * and Atom (Family 6, model 1CH) PMCs.
 566  *
 567  * We map aliases to events on the fixed-function counters if these
 568  * are present.  Note that not all CPUs in this family contain fixed-function
 569  * counters.
 570  */
 571
 572 static struct pmc_event_alias core2_aliases[] = {
 573         EV_ALIAS("branches",            "iap-br-inst-retired.any"),
 574         EV_ALIAS("branch-mispredicts",  "iap-br-inst-retired.mispred"),
 575         EV_ALIAS("cycles",              "tsc-tsc"),
 576         EV_ALIAS("ic-misses",           "iap-l1i-misses"),
 577         EV_ALIAS("instructions",        "iaf-instr-retired.any"),
 578         EV_ALIAS("interrupts",          "iap-hw-int-rcv"),
 579         EV_ALIAS("unhalted-cycles",     "iaf-cpu-clk-unhalted.core"),
 580         EV_ALIAS(NULL, NULL)
 581 };
 582
 583 static struct pmc_event_alias core2_aliases_without_iaf[] = {
 584         EV_ALIAS("branches",            "iap-br-inst-retired.any"),
 585         EV_ALIAS("branch-mispredicts",  "iap-br-inst-retired.mispred"),
 586         EV_ALIAS("cycles",              "tsc-tsc"),
 587         EV_ALIAS("ic-misses",           "iap-l1i-misses"),
 588         EV_ALIAS("instructions",        "iap-inst-retired.any_p"),
 589         EV_ALIAS("interrupts",          "iap-hw-int-rcv"),
 590         EV_ALIAS("unhalted-cycles",     "iap-cpu-clk-unhalted.core_p"),
 591         EV_ALIAS(NULL, NULL)
 592 };
 593
 594 #define atom_aliases                    core2_aliases
 595 #define atom_aliases_without_iaf        core2_aliases_without_iaf
 596 #define corei7_aliases                  core2_aliases
 597 #define corei7_aliases_without_iaf      core2_aliases_without_iaf
 598 #define haswell_aliases                 core2_aliases
 599 #define haswell_aliases_without_iaf     core2_aliases_without_iaf
 600 #define ivybridge_aliases               core2_aliases
 601 #define ivybridge_aliases_without_iaf   core2_aliases_without_iaf
 602 #define ivybridge_xeon_aliases          core2_aliases
 603 #define ivybridge_xeon_aliases_without_iaf      core2_aliases_without_iaf
 604 #define sandybridge_aliases             core2_aliases
 605 #define sandybridge_aliases_without_iaf core2_aliases_without_iaf
 606 #define sandybridge_xeon_aliases        core2_aliases
 607 #define sandybridge_xeon_aliases_without_iaf    core2_aliases_without_iaf
 608 #define westmere_aliases                core2_aliases
 609 #define westmere_aliases_without_iaf    core2_aliases_without_iaf
 610
 611 #define IAF_KW_OS               "os"
 612 #define IAF_KW_USR              "usr"
 613 #define IAF_KW_ANYTHREAD        "anythread"
 614
 615 /*
 616  * Parse an event specifier for Intel fixed function counters.
 617  */
 618 static int
 619 iaf_allocate_pmc(enum pmc_event pe, char *ctrspec,
 620     struct pmc_op_pmcallocate *pmc_config)
 621 {
 622         char *p;
 623
 624         (void) pe;
 625
 626         pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
 627         pmc_config->pm_md.pm_iaf.pm_iaf_flags = 0;
 628
 629         while ((p = strsep(&ctrspec, ",")) != NULL) {
 630                 if (KWMATCH(p, IAF_KW_OS))
 631                         pmc_config->pm_caps |= PMC_CAP_SYSTEM;
 632                 else if (KWMATCH(p, IAF_KW_USR))
 633                         pmc_config->pm_caps |= PMC_CAP_USER;
 634                 else if (KWMATCH(p, IAF_KW_ANYTHREAD))
 635                         pmc_config->pm_md.pm_iaf.pm_iaf_flags |= IAF_ANY;
 636                 else
 637                         return (-1);
 638         }
 639
 640         return (0);
 641 }
 642
 643 /*
 644  * Core/Core2 support.
 645  */
 646
 647 #define IAP_KW_AGENT            "agent"
 648 #define IAP_KW_ANYTHREAD        "anythread"
 649 #define IAP_KW_CACHESTATE       "cachestate"
 650 #define IAP_KW_CMASK            "cmask"
 651 #define IAP_KW_CORE             "core"
 652 #define IAP_KW_EDGE             "edge"
 653 #define IAP_KW_INV              "inv"
 654 #define IAP_KW_OS               "os"
 655 #define IAP_KW_PREFETCH         "prefetch"
 656 #define IAP_KW_SNOOPRESPONSE    "snoopresponse"
 657 #define IAP_KW_SNOOPTYPE        "snooptype"
 658 #define IAP_KW_TRANSITION       "trans"
 659 #define IAP_KW_USR              "usr"
 660 #define IAP_KW_RSP              "rsp"
 661
 662 static struct pmc_masks iap_core_mask[] = {
 663         PMCMASK(all,    (0x3 << 14)),
 664         PMCMASK(this,   (0x1 << 14)),
 665         NULLMASK
 666 };
 667
 668 static struct pmc_masks iap_agent_mask[] = {
 669         PMCMASK(this,   0),
 670         PMCMASK(any,    (0x1 << 13)),
 671         NULLMASK
 672 };
 673
 674 static struct pmc_masks iap_prefetch_mask[] = {
 675         PMCMASK(both,           (0x3 << 12)),
 676         PMCMASK(only,           (0x1 << 12)),
 677         PMCMASK(exclude,        0),
 678         NULLMASK
 679 };
 680
 681 static struct pmc_masks iap_cachestate_mask[] = {
 682         PMCMASK(i,              (1 <<  8)),
 683         PMCMASK(s,              (1 <<  9)),
 684         PMCMASK(e,              (1 << 10)),
 685         PMCMASK(m,              (1 << 11)),
 686         NULLMASK
 687 };
 688
 689 static struct pmc_masks iap_snoopresponse_mask[] = {
 690         PMCMASK(clean,          (1 << 8)),
 691         PMCMASK(hit,            (1 << 9)),
 692         PMCMASK(hitm,           (1 << 11)),
 693         NULLMASK
 694 };
 695
 696 static struct pmc_masks iap_snooptype_mask[] = {
 697         PMCMASK(cmp2s,          (1 << 8)),
 698         PMCMASK(cmp2i,          (1 << 9)),
 699         NULLMASK
 700 };
 701
 702 static struct pmc_masks iap_transition_mask[] = {
 703         PMCMASK(any,            0x00),
 704         PMCMASK(frequency,      0x10),
 705         NULLMASK
 706 };
 707
 708 static struct pmc_masks iap_rsp_mask_i7_wm[] = {
 709         PMCMASK(DMND_DATA_RD,           (1 <<  0)),
 710         PMCMASK(DMND_RFO,               (1 <<  1)),
 711         PMCMASK(DMND_IFETCH,            (1 <<  2)),
 712         PMCMASK(WB,                     (1 <<  3)),
 713         PMCMASK(PF_DATA_RD,             (1 <<  4)),
 714         PMCMASK(PF_RFO,                 (1 <<  5)),
 715         PMCMASK(PF_IFETCH,              (1 <<  6)),
 716         PMCMASK(OTHER,                  (1 <<  7)),
 717         PMCMASK(UNCORE_HIT,             (1 <<  8)),
 718         PMCMASK(OTHER_CORE_HIT_SNP,     (1 <<  9)),
 719         PMCMASK(OTHER_CORE_HITM,        (1 << 10)),
 720         PMCMASK(REMOTE_CACHE_FWD,       (1 << 12)),
 721         PMCMASK(REMOTE_DRAM,            (1 << 13)),
 722         PMCMASK(LOCAL_DRAM,             (1 << 14)),
 723         PMCMASK(NON_DRAM,               (1 << 15)),
 724         NULLMASK
 725 };
 726
 727 static struct pmc_masks iap_rsp_mask_sb_sbx_ib[] = {
 728         PMCMASK(REQ_DMND_DATA_RD,       (1ULL <<  0)),
 729         PMCMASK(REQ_DMND_RFO,           (1ULL <<  1)),
 730         PMCMASK(REQ_DMND_IFETCH,        (1ULL <<  2)),
 731         PMCMASK(REQ_WB,                 (1ULL <<  3)),
 732         PMCMASK(REQ_PF_DATA_RD,         (1ULL <<  4)),
 733         PMCMASK(REQ_PF_RFO,             (1ULL <<  5)),
 734         PMCMASK(REQ_PF_IFETCH,          (1ULL <<  6)),
 735         PMCMASK(REQ_PF_LLC_DATA_RD,     (1ULL <<  7)),
 736         PMCMASK(REQ_PF_LLC_RFO,         (1ULL <<  8)),
 737         PMCMASK(REQ_PF_LLC_IFETCH,      (1ULL <<  9)),
 738         PMCMASK(REQ_BUS_LOCKS,          (1ULL << 10)),
 739         PMCMASK(REQ_STRM_ST,            (1ULL << 11)),
 740         PMCMASK(REQ_OTHER,              (1ULL << 15)),
 741         PMCMASK(RES_ANY,                (1ULL << 16)),
 742         PMCMASK(RES_SUPPLIER_SUPP,      (1ULL << 17)),
 743         PMCMASK(RES_SUPPLIER_LLC_HITM,  (1ULL << 18)),
 744         PMCMASK(RES_SUPPLIER_LLC_HITE,  (1ULL << 19)),
 745         PMCMASK(RES_SUPPLIER_LLC_HITS,  (1ULL << 20)),
 746         PMCMASK(RES_SUPPLIER_LLC_HITF,  (1ULL << 21)),
 747         PMCMASK(RES_SUPPLIER_LOCAL,     (1ULL << 22)),
 748         PMCMASK(RES_SNOOP_SNP_NONE,     (1ULL << 31)),
 749         PMCMASK(RES_SNOOP_SNP_NO_NEEDED,(1ULL << 32)),
 750         PMCMASK(RES_SNOOP_SNP_MISS,     (1ULL << 33)),
 751         PMCMASK(RES_SNOOP_HIT_NO_FWD,   (1ULL << 34)),
 752         PMCMASK(RES_SNOOP_HIT_FWD,      (1ULL << 35)),
 753         PMCMASK(RES_SNOOP_HITM,         (1ULL << 36)),
 754         PMCMASK(RES_NON_DRAM,           (1ULL << 37)),
 755         NULLMASK
 756 };
 757
 758 static struct pmc_masks iap_rsp_mask_haswell[] = {
 759         PMCMASK(REQ_DMND_DATA_RD,       (1ULL <<  0)),
 760         PMCMASK(REQ_DMND_RFO,           (1ULL <<  1)),
 761         PMCMASK(REQ_DMND_IFETCH,        (1ULL <<  2)),
 762         PMCMASK(REQ_PF_DATA_RD,         (1ULL <<  4)),
 763         PMCMASK(REQ_PF_RFO,             (1ULL <<  5)),
 764         PMCMASK(REQ_PF_IFETCH,          (1ULL <<  6)),
 765         PMCMASK(REQ_OTHER,              (1ULL << 15)),
 766         PMCMASK(RES_ANY,                (1ULL << 16)),
 767         PMCMASK(RES_SUPPLIER_SUPP,      (1ULL << 17)),
 768         PMCMASK(RES_SUPPLIER_LLC_HITM,  (1ULL << 18)),
 769         PMCMASK(RES_SUPPLIER_LLC_HITE,  (1ULL << 19)),
 770         PMCMASK(RES_SUPPLIER_LLC_HITS,  (1ULL << 20)),
 771         PMCMASK(RES_SUPPLIER_LLC_HITF,  (1ULL << 21)),
 772         PMCMASK(RES_SUPPLIER_LOCAL,     (1ULL << 22)),
 773         PMCMASK(RES_SNOOP_SNP_NONE,     (1ULL << 31)),
 774         PMCMASK(RES_SNOOP_SNP_NO_NEEDED,(1ULL << 32)),
 775         PMCMASK(RES_SNOOP_SNP_MISS,     (1ULL << 33)),
 776         PMCMASK(RES_SNOOP_HIT_NO_FWD,   (1ULL << 34)),
 777         PMCMASK(RES_SNOOP_HIT_FWD,      (1ULL << 35)),
 778         PMCMASK(RES_SNOOP_HITM,         (1ULL << 36)),
 779         PMCMASK(RES_NON_DRAM,           (1ULL << 37)),
 780         NULLMASK
 781 };
 782
 783 static int
 784 iap_allocate_pmc(enum pmc_event pe, char *ctrspec,
 785     struct pmc_op_pmcallocate *pmc_config)
 786 {
 787         char *e, *p, *q;
 788         uint64_t cachestate, evmask, rsp;
 789         int count, n;
 790
 791         pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE |
 792             PMC_CAP_QUALIFIER);
 793         pmc_config->pm_md.pm_iap.pm_iap_config = 0;
 794
 795         cachestate = evmask = rsp = 0;
 796
 797         /* Parse additional modifiers if present */
 798         while ((p = strsep(&ctrspec, ",")) != NULL) {
 799
 800                 n = 0;
 801                 if (KWPREFIXMATCH(p, IAP_KW_CMASK "=")) {
 802                         q = strchr(p, '=');
 803                         if (*++q == '\0') /* skip '=' */
 804                                 return (-1);
 805                         count = strtol(q, &e, 0);
 806                         if (e == q || *e != '\0')
 807                                 return (-1);
 808                         pmc_config->pm_caps |= PMC_CAP_THRESHOLD;
 809                         pmc_config->pm_md.pm_iap.pm_iap_config |=
 810                             IAP_CMASK(count);
 811                 } else if (KWMATCH(p, IAP_KW_EDGE)) {
 812                         pmc_config->pm_caps |= PMC_CAP_EDGE;
 813                 } else if (KWMATCH(p, IAP_KW_INV)) {
 814                         pmc_config->pm_caps |= PMC_CAP_INVERT;
 815                 } else if (KWMATCH(p, IAP_KW_OS)) {
 816                         pmc_config->pm_caps |= PMC_CAP_SYSTEM;
 817                 } else if (KWMATCH(p, IAP_KW_USR)) {
 818                         pmc_config->pm_caps |= PMC_CAP_USER;
 819                 } else if (KWMATCH(p, IAP_KW_ANYTHREAD)) {
 820                         pmc_config->pm_md.pm_iap.pm_iap_config |= IAP_ANY;
 821                 } else if (KWPREFIXMATCH(p, IAP_KW_CORE "=")) {
 822                         n = pmc_parse_mask(iap_core_mask, p, &evmask);
 823                         if (n != 1)
 824                                 return (-1);
 825                 } else if (KWPREFIXMATCH(p, IAP_KW_AGENT "=")) {
 826                         n = pmc_parse_mask(iap_agent_mask, p, &evmask);
 827                         if (n != 1)
 828                                 return (-1);
 829                 } else if (KWPREFIXMATCH(p, IAP_KW_PREFETCH "=")) {
 830                         n = pmc_parse_mask(iap_prefetch_mask, p, &evmask);
 831                         if (n != 1)
 832                                 return (-1);
 833                 } else if (KWPREFIXMATCH(p, IAP_KW_CACHESTATE "=")) {
 834                         n = pmc_parse_mask(iap_cachestate_mask, p, &cachestate);
 835                 } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_CORE &&
 836                     KWPREFIXMATCH(p, IAP_KW_TRANSITION "=")) {
 837                         n = pmc_parse_mask(iap_transition_mask, p, &evmask);
 838                         if (n != 1)
 839                                 return (-1);
 840                 } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_ATOM ||
 841                     cpu_info.pm_cputype == PMC_CPU_INTEL_CORE2 ||
 842                     cpu_info.pm_cputype == PMC_CPU_INTEL_CORE2EXTREME) {
 843                         if (KWPREFIXMATCH(p, IAP_KW_SNOOPRESPONSE "=")) {
 844                                 n = pmc_parse_mask(iap_snoopresponse_mask, p,
 845                                     &evmask);
 846                         } else if (KWPREFIXMATCH(p, IAP_KW_SNOOPTYPE "=")) {
 847                                 n = pmc_parse_mask(iap_snooptype_mask, p,
 848                                     &evmask);
 849                         } else
 850                                 return (-1);
 851                 } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_COREI7 ||
 852                     cpu_info.pm_cputype == PMC_CPU_INTEL_WESTMERE) {
 853                         if (KWPREFIXMATCH(p, IAP_KW_RSP "=")) {
 854                                 n = pmc_parse_mask(iap_rsp_mask_i7_wm, p, &rsp);
 855                         } else
 856                                 return (-1);
 857                 } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_SANDYBRIDGE ||
 858                     cpu_info.pm_cputype == PMC_CPU_INTEL_SANDYBRIDGE_XEON ||
 859                         cpu_info.pm_cputype == PMC_CPU_INTEL_IVYBRIDGE ||
 860                         cpu_info.pm_cputype == PMC_CPU_INTEL_IVYBRIDGE_XEON ) {
 861                         if (KWPREFIXMATCH(p, IAP_KW_RSP "=")) {
 862                                 n = pmc_parse_mask(iap_rsp_mask_sb_sbx_ib, p, &rsp);
 863                         } else
 864                                 return (-1);
 865                 } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_HASWELL) {
 866                         if (KWPREFIXMATCH(p, IAP_KW_RSP "=")) {
 867                                 n = pmc_parse_mask(iap_rsp_mask_haswell, p, &rsp);
 868                         } else
 869                                 return (-1);
 870                 } else
 871                         return (-1);
 872
 873                 if (n < 0)      /* Parsing failed. */
 874                         return (-1);
 875         }
 876
 877         pmc_config->pm_md.pm_iap.pm_iap_config |= evmask;
 878
 879         /*
 880          * If the event requires a 'cachestate' qualifier but was not
 881          * specified by the user, use a sensible default.
 882          */
 883         switch (pe) {
 884         case PMC_EV_IAP_EVENT_28H: /* Core, Core2, Atom */
 885         case PMC_EV_IAP_EVENT_29H: /* Core, Core2, Atom */
 886         case PMC_EV_IAP_EVENT_2AH: /* Core, Core2, Atom */
 887         case PMC_EV_IAP_EVENT_2BH: /* Atom, Core2 */
 888         case PMC_EV_IAP_EVENT_2EH: /* Core, Core2, Atom */
 889         case PMC_EV_IAP_EVENT_30H: /* Core, Core2, Atom */
 890         case PMC_EV_IAP_EVENT_32H: /* Core */
 891         case PMC_EV_IAP_EVENT_40H: /* Core */
 892         case PMC_EV_IAP_EVENT_41H: /* Core */
 893         case PMC_EV_IAP_EVENT_42H: /* Core, Core2, Atom */
 894                 if (cachestate == 0)
 895                         cachestate = (0xF << 8);
 896                 break;
 897         case PMC_EV_IAP_EVENT_77H: /* Atom */
 898                 /* IAP_EVENT_77H only accepts a cachestate qualifier on the
 899                  * Atom processor
 900                  */
 901                 if(cpu_info.pm_cputype == PMC_CPU_INTEL_ATOM && cachestate == 0)
 902                         cachestate = (0xF << 8);
 903             break;
 904         default:
 905                 break;
 906         }
 907
 908         pmc_config->pm_md.pm_iap.pm_iap_config |= cachestate;
 909         pmc_config->pm_md.pm_iap.pm_iap_rsp = rsp;
 910
 911         return (0);
 912 }
 913
 914 /*
 915  * Intel Uncore.
 916  */
 917
 918 static int
 919 ucf_allocate_pmc(enum pmc_event pe, char *ctrspec,
 920     struct pmc_op_pmcallocate *pmc_config)
 921 {
 922         (void) pe;
 923         (void) ctrspec;
 924
 925         pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
 926         pmc_config->pm_md.pm_ucf.pm_ucf_flags = 0;
 927
 928         return (0);
 929 }
 930
 931 #define UCP_KW_CMASK            "cmask"
 932 #define UCP_KW_EDGE             "edge"
 933 #define UCP_KW_INV              "inv"
 934
 935 static int
 936 ucp_allocate_pmc(enum pmc_event pe, char *ctrspec,
 937     struct pmc_op_pmcallocate *pmc_config)
 938 {
 939         char *e, *p, *q;
 940         int count, n;
 941
 942         (void) pe;
 943
 944         pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE |
 945             PMC_CAP_QUALIFIER);
 946         pmc_config->pm_md.pm_ucp.pm_ucp_config = 0;
 947
 948         /* Parse additional modifiers if present */
 949         while ((p = strsep(&ctrspec, ",")) != NULL) {
 950
 951                 n = 0;
 952                 if (KWPREFIXMATCH(p, UCP_KW_CMASK "=")) {
 953                         q = strchr(p, '=');
 954                         if (*++q == '\0') /* skip '=' */
 955                                 return (-1);
 956                         count = strtol(q, &e, 0);
 957                         if (e == q || *e != '\0')
 958                                 return (-1);
 959                         pmc_config->pm_caps |= PMC_CAP_THRESHOLD;
 960                         pmc_config->pm_md.pm_ucp.pm_ucp_config |=
 961                             UCP_CMASK(count);
 962                 } else if (KWMATCH(p, UCP_KW_EDGE)) {
 963                         pmc_config->pm_caps |= PMC_CAP_EDGE;
 964                 } else if (KWMATCH(p, UCP_KW_INV)) {
 965                         pmc_config->pm_caps |= PMC_CAP_INVERT;
 966                 } else
 967                         return (-1);
 968
 969                 if (n < 0)      /* Parsing failed. */
 970                         return (-1);
 971         }
 972
 973         return (0);
 974 }
 975
 976 /*
 977  * AMD K8 PMCs.
 978  *
 979  * These are very similar to AMD K7 PMCs, but support more kinds of
 980  * events.
 981  */
 982
 983 static struct pmc_event_alias k8_aliases[] = {
 984         EV_ALIAS("branches",            "k8-fr-retired-taken-branches"),
 985         EV_ALIAS("branch-mispredicts",
 986             "k8-fr-retired-taken-branches-mispredicted"),
 987         EV_ALIAS("cycles",              "tsc"),
 988         EV_ALIAS("dc-misses",           "k8-dc-miss"),
 989         EV_ALIAS("ic-misses",           "k8-ic-miss"),
 990         EV_ALIAS("instructions",        "k8-fr-retired-x86-instructions"),
 991         EV_ALIAS("interrupts",          "k8-fr-taken-hardware-interrupts"),
 992         EV_ALIAS("unhalted-cycles",     "k8-bu-cpu-clk-unhalted"),
 993         EV_ALIAS(NULL, NULL)
 994 };
 995
 996 #define __K8MASK(N,V) PMCMASK(N,(1 << (V)))
 997
 998 /*
 999  * Parsing tables
1000  */
1001
1002 /* fp dispatched fpu ops */
1003 static const struct pmc_masks k8_mask_fdfo[] = {
1004         __K8MASK(add-pipe-excluding-junk-ops,   0),
1005         __K8MASK(multiply-pipe-excluding-junk-ops,      1),
1006         __K8MASK(store-pipe-excluding-junk-ops, 2),
1007         __K8MASK(add-pipe-junk-ops,             3),
1008         __K8MASK(multiply-pipe-junk-ops,        4),
1009         __K8MASK(store-pipe-junk-ops,           5),
1010         NULLMASK
1011 };
1012
1013 /* ls segment register loads */
1014 static const struct pmc_masks k8_mask_lsrl[] = {
1015         __K8MASK(es,    0),
1016         __K8MASK(cs,    1),
1017         __K8MASK(ss,    2),
1018         __K8MASK(ds,    3),
1019         __K8MASK(fs,    4),
1020         __K8MASK(gs,    5),
1021         __K8MASK(hs,    6),
1022         NULLMASK
1023 };
1024
1025 /* ls locked operation */
1026 static const struct pmc_masks k8_mask_llo[] = {
1027         __K8MASK(locked-instructions,   0),
1028         __K8MASK(cycles-in-request,     1),
1029         __K8MASK(cycles-to-complete,    2),
1030         NULLMASK
1031 };
1032
1033 /* dc refill from {l2,system} and dc copyback */
1034 static const struct pmc_masks k8_mask_dc[] = {
1035         __K8MASK(invalid,       0),
1036         __K8MASK(shared,        1),
1037         __K8MASK(exclusive,     2),
1038         __K8MASK(owner,         3),
1039         __K8MASK(modified,      4),
1040         NULLMASK
1041 };
1042
1043 /* dc one bit ecc error */
1044 static const struct pmc_masks k8_mask_dobee[] = {
1045         __K8MASK(scrubber,      0),
1046         __K8MASK(piggyback,     1),
1047         NULLMASK
1048 };
1049
1050 /* dc dispatched prefetch instructions */
1051 static const struct pmc_masks k8_mask_ddpi[] = {
1052         __K8MASK(load,  0),
1053         __K8MASK(store, 1),
1054         __K8MASK(nta,   2),
1055         NULLMASK
1056 };
1057
1058 /* dc dcache accesses by locks */
1059 static const struct pmc_masks k8_mask_dabl[] = {
1060         __K8MASK(accesses,      0),
1061         __K8MASK(misses,        1),
1062         NULLMASK
1063 };
1064
1065 /* bu internal l2 request */
1066 static const struct pmc_masks k8_mask_bilr[] = {
1067         __K8MASK(ic-fill,       0),
1068         __K8MASK(dc-fill,       1),
1069         __K8MASK(tlb-reload,    2),
1070         __K8MASK(tag-snoop,     3),
1071         __K8MASK(cancelled,     4),
1072         NULLMASK
1073 };
1074
1075 /* bu fill request l2 miss */
1076 static const struct pmc_masks k8_mask_bfrlm[] = {
1077         __K8MASK(ic-fill,       0),
1078         __K8MASK(dc-fill,       1),
1079         __K8MASK(tlb-reload,    2),
1080         NULLMASK
1081 };
1082
1083 /* bu fill into l2 */
1084 static const struct pmc_masks k8_mask_bfil[] = {
1085         __K8MASK(dirty-l2-victim,       0),
1086         __K8MASK(victim-from-l2,        1),
1087         NULLMASK
1088 };
1089
1090 /* fr retired fpu instructions */
1091 static const struct pmc_masks k8_mask_frfi[] = {
1092         __K8MASK(x87,                   0),
1093         __K8MASK(mmx-3dnow,             1),
1094         __K8MASK(packed-sse-sse2,       2),
1095         __K8MASK(scalar-sse-sse2,       3),
1096         NULLMASK
1097 };
1098
1099 /* fr retired fastpath double op instructions */
1100 static const struct pmc_masks k8_mask_frfdoi[] = {
1101         __K8MASK(low-op-pos-0,          0),
1102         __K8MASK(low-op-pos-1,          1),
1103         __K8MASK(low-op-pos-2,          2),
1104         NULLMASK
1105 };
1106
1107 /* fr fpu exceptions */
1108 static const struct pmc_masks k8_mask_ffe[] = {
1109         __K8MASK(x87-reclass-microfaults,       0),
1110         __K8MASK(sse-retype-microfaults,        1),
1111         __K8MASK(sse-reclass-microfaults,       2),
1112         __K8MASK(sse-and-x87-microtraps,        3),
1113         NULLMASK
1114 };
1115
1116 /* nb memory controller page access event */
1117 static const struct pmc_masks k8_mask_nmcpae[] = {
1118         __K8MASK(page-hit,      0),
1119         __K8MASK(page-miss,     1),
1120         __K8MASK(page-conflict, 2),
1121         NULLMASK
1122 };
1123
1124 /* nb memory controller turnaround */
1125 static const struct pmc_masks k8_mask_nmct[] = {
1126         __K8MASK(dimm-turnaround,               0),
1127         __K8MASK(read-to-write-turnaround,      1),
1128         __K8MASK(write-to-read-turnaround,      2),
1129         NULLMASK
1130 };
1131
1132 /* nb memory controller bypass saturation */
1133 static const struct pmc_masks k8_mask_nmcbs[] = {
1134         __K8MASK(memory-controller-hi-pri-bypass,       0),
1135         __K8MASK(memory-controller-lo-pri-bypass,       1),
1136         __K8MASK(dram-controller-interface-bypass,      2),
1137         __K8MASK(dram-controller-queue-bypass,          3),
1138         NULLMASK
1139 };
1140
1141 /* nb sized commands */
1142 static const struct pmc_masks k8_mask_nsc[] = {
1143         __K8MASK(nonpostwrszbyte,       0),
1144         __K8MASK(nonpostwrszdword,      1),
1145         __K8MASK(postwrszbyte,          2),
1146         __K8MASK(postwrszdword,         3),
1147         __K8MASK(rdszbyte,              4),
1148         __K8MASK(rdszdword,             5),
1149         __K8MASK(rdmodwr,               6),
1150         NULLMASK
1151 };
1152
1153 /* nb probe result */
1154 static const struct pmc_masks k8_mask_npr[] = {
1155         __K8MASK(probe-miss,            0),
1156         __K8MASK(probe-hit,             1),
1157         __K8MASK(probe-hit-dirty-no-memory-cancel, 2),
1158         __K8MASK(probe-hit-dirty-with-memory-cancel, 3),
1159         NULLMASK
1160 };
1161
1162 /* nb hypertransport bus bandwidth */
1163 static const struct pmc_masks k8_mask_nhbb[] = { /* HT bus bandwidth */
1164         __K8MASK(command,       0),
1165         __K8MASK(data,  1),
1166         __K8MASK(buffer-release, 2),
1167         __K8MASK(nop,   3),
1168         NULLMASK
1169 };
1170
1171 #undef  __K8MASK
1172
1173 #define K8_KW_COUNT     "count"
1174 #define K8_KW_EDGE      "edge"
1175 #define K8_KW_INV       "inv"
1176 #define K8_KW_MASK      "mask"
1177 #define K8_KW_OS        "os"
1178 #define K8_KW_USR       "usr"
1179
1180 static int
1181 k8_allocate_pmc(enum pmc_event pe, char *ctrspec,
1182     struct pmc_op_pmcallocate *pmc_config)
1183 {
1184         char            *e, *p, *q;
1185         int             n;
1186         uint32_t        count;
1187         uint64_t        evmask;
1188         const struct pmc_masks  *pm, *pmask;
1189
1190         pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
1191         pmc_config->pm_md.pm_amd.pm_amd_config = 0;
1192
1193         pmask = NULL;
1194         evmask = 0;
1195
1196 #define __K8SETMASK(M) pmask = k8_mask_##M
1197
1198         /* setup parsing tables */
1199         switch (pe) {
1200         case PMC_EV_K8_FP_DISPATCHED_FPU_OPS:
1201                 __K8SETMASK(fdfo);
1202                 break;
1203         case PMC_EV_K8_LS_SEGMENT_REGISTER_LOAD:
1204                 __K8SETMASK(lsrl);
1205                 break;
1206         case PMC_EV_K8_LS_LOCKED_OPERATION:
1207                 __K8SETMASK(llo);
1208                 break;
1209         case PMC_EV_K8_DC_REFILL_FROM_L2:
1210         case PMC_EV_K8_DC_REFILL_FROM_SYSTEM:
1211         case PMC_EV_K8_DC_COPYBACK:
1212                 __K8SETMASK(dc);
1213                 break;
1214         case PMC_EV_K8_DC_ONE_BIT_ECC_ERROR:
1215                 __K8SETMASK(dobee);
1216                 break;
1217         case PMC_EV_K8_DC_DISPATCHED_PREFETCH_INSTRUCTIONS:
1218                 __K8SETMASK(ddpi);
1219                 break;
1220         case PMC_EV_K8_DC_DCACHE_ACCESSES_BY_LOCKS:
1221                 __K8SETMASK(dabl);
1222                 break;
1223         case PMC_EV_K8_BU_INTERNAL_L2_REQUEST:
1224                 __K8SETMASK(bilr);
1225                 break;
1226         case PMC_EV_K8_BU_FILL_REQUEST_L2_MISS:
1227                 __K8SETMASK(bfrlm);
1228                 break;
1229         case PMC_EV_K8_BU_FILL_INTO_L2:
1230                 __K8SETMASK(bfil);
1231                 break;
1232         case PMC_EV_K8_FR_RETIRED_FPU_INSTRUCTIONS:
1233                 __K8SETMASK(frfi);
1234                 break;
1235         case PMC_EV_K8_FR_RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS:
1236                 __K8SETMASK(frfdoi);
1237                 break;
1238         case PMC_EV_K8_FR_FPU_EXCEPTIONS:
1239                 __K8SETMASK(ffe);
1240                 break;
1241         case PMC_EV_K8_NB_MEMORY_CONTROLLER_PAGE_ACCESS_EVENT:
1242                 __K8SETMASK(nmcpae);
1243                 break;
1244         case PMC_EV_K8_NB_MEMORY_CONTROLLER_TURNAROUND:
1245                 __K8SETMASK(nmct);
1246                 break;
1247         case PMC_EV_K8_NB_MEMORY_CONTROLLER_BYPASS_SATURATION:
1248                 __K8SETMASK(nmcbs);
1249                 break;
1250         case PMC_EV_K8_NB_SIZED_COMMANDS:
1251                 __K8SETMASK(nsc);
1252                 break;
1253         case PMC_EV_K8_NB_PROBE_RESULT:
1254                 __K8SETMASK(npr);
1255                 break;
1256         case PMC_EV_K8_NB_HT_BUS0_BANDWIDTH:
1257         case PMC_EV_K8_NB_HT_BUS1_BANDWIDTH:
1258         case PMC_EV_K8_NB_HT_BUS2_BANDWIDTH:
1259                 __K8SETMASK(nhbb);
1260                 break;
1261
1262         default:
1263                 break;          /* no options defined */
1264         }
1265
1266         while ((p = strsep(&ctrspec, ",")) != NULL) {
1267                 if (KWPREFIXMATCH(p, K8_KW_COUNT "=")) {
1268                         q = strchr(p, '=');
1269                         if (*++q == '\0') /* skip '=' */
1270                                 return (-1);
1271
1272                         count = strtol(q, &e, 0);
1273                         if (e == q || *e != '\0')
1274                                 return (-1);
1275
1276                         pmc_config->pm_caps |= PMC_CAP_THRESHOLD;
1277                         pmc_config->pm_md.pm_amd.pm_amd_config |=
1278                             AMD_PMC_TO_COUNTER(count);
1279
1280                 } else if (KWMATCH(p, K8_KW_EDGE)) {
1281                         pmc_config->pm_caps |= PMC_CAP_EDGE;
1282                 } else if (KWMATCH(p, K8_KW_INV)) {
1283                         pmc_config->pm_caps |= PMC_CAP_INVERT;
1284                 } else if (KWPREFIXMATCH(p, K8_KW_MASK "=")) {
1285                         if ((n = pmc_parse_mask(pmask, p, &evmask)) < 0)
1286                                 return (-1);
1287                         pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
1288                 } else if (KWMATCH(p, K8_KW_OS)) {
1289                         pmc_config->pm_caps |= PMC_CAP_SYSTEM;
1290                 } else if (KWMATCH(p, K8_KW_USR)) {
1291                         pmc_config->pm_caps |= PMC_CAP_USER;
1292                 } else
1293                         return (-1);
1294         }
1295
1296         /* other post processing */
1297         switch (pe) {
1298         case PMC_EV_K8_FP_DISPATCHED_FPU_OPS:
1299         case PMC_EV_K8_FP_CYCLES_WITH_NO_FPU_OPS_RETIRED:
1300         case PMC_EV_K8_FP_DISPATCHED_FPU_FAST_FLAG_OPS:
1301         case PMC_EV_K8_FR_RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS:
1302         case PMC_EV_K8_FR_RETIRED_FPU_INSTRUCTIONS:
1303         case PMC_EV_K8_FR_FPU_EXCEPTIONS:
1304                 /* XXX only available in rev B and later */
1305                 break;
1306         case PMC_EV_K8_DC_DCACHE_ACCESSES_BY_LOCKS:
1307                 /* XXX only available in rev C and later */
1308                 break;
1309         case PMC_EV_K8_LS_LOCKED_OPERATION:
1310                 /* XXX CPU Rev A,B evmask is to be zero */
1311                 if (evmask & (evmask - 1)) /* > 1 bit set */
1312                         return (-1);
1313                 if (evmask == 0) {
1314                         evmask = 0x01; /* Rev C and later: #instrs */
1315                         pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
1316                 }
1317                 break;
1318         default:
1319                 if (evmask == 0 && pmask != NULL) {
1320                         for (pm = pmask; pm->pm_name; pm++)
1321                                 evmask |= pm->pm_value;
1322                         pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
1323                 }
1324         }
1325
1326         if (pmc_config->pm_caps & PMC_CAP_QUALIFIER)
1327                 pmc_config->pm_md.pm_amd.pm_amd_config =
1328                     AMD_PMC_TO_UNITMASK(evmask);
1329
1330         return (0);
1331 }
1332
1333 #endif
1334
1335 #if defined(__amd64__) || defined(__i386__)
1336
1337 /*
1338  * Intel P4 PMCs
1339  */
1340
1341 static struct pmc_event_alias p4_aliases[] = {
1342         EV_ALIAS("branches",            "p4-branch-retired,mask=mmtp+mmtm"),
1343         EV_ALIAS("branch-mispredicts",  "p4-mispred-branch-retired"),
1344         EV_ALIAS("cycles",              "tsc"),
1345         EV_ALIAS("instructions",
1346             "p4-instr-retired,mask=nbogusntag+nbogustag"),
1347         EV_ALIAS("unhalted-cycles",     "p4-global-power-events"),
1348         EV_ALIAS(NULL, NULL)
1349 };
1350
1351 #define P4_KW_ACTIVE    "active"
1352 #define P4_KW_ACTIVE_ANY "any"
1353 #define P4_KW_ACTIVE_BOTH "both"
1354 #define P4_KW_ACTIVE_NONE "none"
1355 #define P4_KW_ACTIVE_SINGLE "single"
1356 #define P4_KW_BUSREQTYPE "busreqtype"
1357 #define P4_KW_CASCADE   "cascade"
1358 #define P4_KW_EDGE      "edge"
1359 #define P4_KW_INV       "complement"
1360 #define P4_KW_OS        "os"
1361 #define P4_KW_MASK      "mask"
1362 #define P4_KW_PRECISE   "precise"
1363 #define P4_KW_TAG       "tag"
1364 #define P4_KW_THRESHOLD "threshold"
1365 #define P4_KW_USR       "usr"
1366
1367 #define __P4MASK(N,V) PMCMASK(N, (1 << (V)))
1368
1369 static const struct pmc_masks p4_mask_tcdm[] = { /* tc deliver mode */
1370         __P4MASK(dd, 0),
1371         __P4MASK(db, 1),
1372         __P4MASK(di, 2),
1373         __P4MASK(bd, 3),
1374         __P4MASK(bb, 4),
1375         __P4MASK(bi, 5),
1376         __P4MASK(id, 6),
1377         __P4MASK(ib, 7),
1378         NULLMASK
1379 };
1380
1381 static const struct pmc_masks p4_mask_bfr[] = { /* bpu fetch request */
1382         __P4MASK(tcmiss, 0),
1383         NULLMASK,
1384 };
1385
1386 static const struct pmc_masks p4_mask_ir[] = { /* itlb reference */
1387         __P4MASK(hit, 0),
1388         __P4MASK(miss, 1),
1389         __P4MASK(hit-uc, 2),
1390         NULLMASK
1391 };
1392
1393 static const struct pmc_masks p4_mask_memcan[] = { /* memory cancel */
1394         __P4MASK(st-rb-full, 2),
1395         __P4MASK(64k-conf, 3),
1396         NULLMASK
1397 };
1398
1399 static const struct pmc_masks p4_mask_memcomp[] = { /* memory complete */
1400         __P4MASK(lsc, 0),
1401         __P4MASK(ssc, 1),
1402         NULLMASK
1403 };
1404
1405 static const struct pmc_masks p4_mask_lpr[] = { /* load port replay */
1406         __P4MASK(split-ld, 1),
1407         NULLMASK
1408 };
1409
1410 static const struct pmc_masks p4_mask_spr[] = { /* store port replay */
1411         __P4MASK(split-st, 1),
1412         NULLMASK
1413 };
1414
1415 static const struct pmc_masks p4_mask_mlr[] = { /* mob load replay */
1416         __P4MASK(no-sta, 1),
1417         __P4MASK(no-std, 3),
1418         __P4MASK(partial-data, 4),
1419         __P4MASK(unalgn-addr, 5),
1420         NULLMASK
1421 };
1422
1423 static const struct pmc_masks p4_mask_pwt[] = { /* page walk type */
1424         __P4MASK(dtmiss, 0),
1425         __P4MASK(itmiss, 1),
1426         NULLMASK
1427 };
1428
1429 static const struct pmc_masks p4_mask_bcr[] = { /* bsq cache reference */
1430         __P4MASK(rd-2ndl-hits, 0),
1431         __P4MASK(rd-2ndl-hite, 1),
1432         __P4MASK(rd-2ndl-hitm, 2),
1433         __P4MASK(rd-3rdl-hits, 3),
1434         __P4MASK(rd-3rdl-hite, 4),
1435         __P4MASK(rd-3rdl-hitm, 5),
1436         __P4MASK(rd-2ndl-miss, 8),
1437         __P4MASK(rd-3rdl-miss, 9),
1438         __P4MASK(wr-2ndl-miss, 10),
1439         NULLMASK
1440 };
1441
1442 static const struct pmc_masks p4_mask_ia[] = { /* ioq allocation */
1443         __P4MASK(all-read, 5),
1444         __P4MASK(all-write, 6),
1445         __P4MASK(mem-uc, 7),
1446         __P4MASK(mem-wc, 8),
1447         __P4MASK(mem-wt, 9),
1448         __P4MASK(mem-wp, 10),
1449         __P4MASK(mem-wb, 11),
1450         __P4MASK(own, 13),
1451         __P4MASK(other, 14),
1452         __P4MASK(prefetch, 15),
1453         NULLMASK
1454 };
1455
1456 static const struct pmc_masks p4_mask_iae[] = { /* ioq active entries */
1457         __P4MASK(all-read, 5),
1458         __P4MASK(all-write, 6),
1459         __P4MASK(mem-uc, 7),
1460         __P4MASK(mem-wc, 8),
1461         __P4MASK(mem-wt, 9),
1462         __P4MASK(mem-wp, 10),
1463         __P4MASK(mem-wb, 11),
1464         __P4MASK(own, 13),
1465         __P4MASK(other, 14),
1466         __P4MASK(prefetch, 15),
1467         NULLMASK
1468 };
1469
1470 static const struct pmc_masks p4_mask_fda[] = { /* fsb data activity */
1471         __P4MASK(drdy-drv, 0),
1472         __P4MASK(drdy-own, 1),
1473         __P4MASK(drdy-other, 2),
1474         __P4MASK(dbsy-drv, 3),
1475         __P4MASK(dbsy-own, 4),
1476         __P4MASK(dbsy-other, 5),
1477         NULLMASK
1478 };
1479
1480 static const struct pmc_masks p4_mask_ba[] = { /* bsq allocation */
1481         __P4MASK(req-type0, 0),
1482         __P4MASK(req-type1, 1),
1483         __P4MASK(req-len0, 2),
1484         __P4MASK(req-len1, 3),
1485         __P4MASK(req-io-type, 5),
1486         __P4MASK(req-lock-type, 6),
1487         __P4MASK(req-cache-type, 7),
1488         __P4MASK(req-split-type, 8),
1489         __P4MASK(req-dem-type, 9),
1490         __P4MASK(req-ord-type, 10),
1491         __P4MASK(mem-type0, 11),
1492         __P4MASK(mem-type1, 12),
1493         __P4MASK(mem-type2, 13),
1494         NULLMASK
1495 };
1496
1497 static const struct pmc_masks p4_mask_sia[] = { /* sse input assist */
1498         __P4MASK(all, 15),
1499         NULLMASK
1500 };
1501
1502 static const struct pmc_masks p4_mask_psu[] = { /* packed sp uop */
1503         __P4MASK(all, 15),
1504         NULLMASK
1505 };
1506
1507 static const struct pmc_masks p4_mask_pdu[] = { /* packed dp uop */
1508         __P4MASK(all, 15),
1509         NULLMASK
1510 };
1511
1512 static const struct pmc_masks p4_mask_ssu[] = { /* scalar sp uop */
1513         __P4MASK(all, 15),
1514         NULLMASK
1515 };
1516
1517 static const struct pmc_masks p4_mask_sdu[] = { /* scalar dp uop */
1518         __P4MASK(all, 15),
1519         NULLMASK
1520 };
1521
1522 static const struct pmc_masks p4_mask_64bmu[] = { /* 64 bit mmx uop */
1523         __P4MASK(all, 15),
1524         NULLMASK
1525 };
1526
1527 static const struct pmc_masks p4_mask_128bmu[] = { /* 128 bit mmx uop */
1528         __P4MASK(all, 15),
1529         NULLMASK
1530 };
1531
1532 static const struct pmc_masks p4_mask_xfu[] = { /* X87 fp uop */
1533         __P4MASK(all, 15),
1534         NULLMASK
1535 };
1536
1537 static const struct pmc_masks p4_mask_xsmu[] = { /* x87 simd moves uop */
1538         __P4MASK(allp0, 3),
1539         __P4MASK(allp2, 4),
1540         NULLMASK
1541 };
1542
1543 static const struct pmc_masks p4_mask_gpe[] = { /* global power events */
1544         __P4MASK(running, 0),
1545         NULLMASK
1546 };
1547
1548 static const struct pmc_masks p4_mask_tmx[] = { /* TC ms xfer */
1549         __P4MASK(cisc, 0),
1550         NULLMASK
1551 };
1552
1553 static const struct pmc_masks p4_mask_uqw[] = { /* uop queue writes */
1554         __P4MASK(from-tc-build, 0),
1555         __P4MASK(from-tc-deliver, 1),
1556         __P4MASK(from-rom, 2),
1557         NULLMASK
1558 };
1559
1560 static const struct pmc_masks p4_mask_rmbt[] = {
1561         /* retired mispred branch type */
1562         __P4MASK(conditional, 1),
1563         __P4MASK(call, 2),
1564         __P4MASK(return, 3),
1565         __P4MASK(indirect, 4),
1566         NULLMASK
1567 };
1568
1569 static const struct pmc_masks p4_mask_rbt[] = { /* retired branch type */
1570         __P4MASK(conditional, 1),
1571         __P4MASK(call, 2),
1572         __P4MASK(retired, 3),
1573         __P4MASK(indirect, 4),
1574         NULLMASK
1575 };
1576
1577 static const struct pmc_masks p4_mask_rs[] = { /* resource stall */
1578         __P4MASK(sbfull, 5),
1579         NULLMASK
1580 };
1581
1582 static const struct pmc_masks p4_mask_wb[] = { /* WC buffer */
1583         __P4MASK(wcb-evicts, 0),
1584         __P4MASK(wcb-full-evict, 1),
1585         NULLMASK
1586 };
1587
1588 static const struct pmc_masks p4_mask_fee[] = { /* front end event */
1589         __P4MASK(nbogus, 0),
1590         __P4MASK(bogus, 1),
1591         NULLMASK
1592 };
1593
1594 static const struct pmc_masks p4_mask_ee[] = { /* execution event */
1595         __P4MASK(nbogus0, 0),
1596         __P4MASK(nbogus1, 1),
1597         __P4MASK(nbogus2, 2),
1598         __P4MASK(nbogus3, 3),
1599         __P4MASK(bogus0, 4),
1600         __P4MASK(bogus1, 5),
1601         __P4MASK(bogus2, 6),
1602         __P4MASK(bogus3, 7),
1603         NULLMASK
1604 };
1605
1606 static const struct pmc_masks p4_mask_re[] = { /* replay event */
1607         __P4MASK(nbogus, 0),
1608         __P4MASK(bogus, 1),
1609         NULLMASK
1610 };
1611
1612 static const struct pmc_masks p4_mask_insret[] = { /* instr retired */
1613         __P4MASK(nbogusntag, 0),
1614         __P4MASK(nbogustag, 1),
1615         __P4MASK(bogusntag, 2),
1616         __P4MASK(bogustag, 3),
1617         NULLMASK
1618 };
1619
1620 static const struct pmc_masks p4_mask_ur[] = { /* uops retired */
1621         __P4MASK(nbogus, 0),
1622         __P4MASK(bogus, 1),
1623         NULLMASK
1624 };
1625
1626 static const struct pmc_masks p4_mask_ut[] = { /* uop type */
1627         __P4MASK(tagloads, 1),
1628         __P4MASK(tagstores, 2),
1629         NULLMASK
1630 };
1631
1632 static const struct pmc_masks p4_mask_br[] = { /* branch retired */
1633         __P4MASK(mmnp, 0),
1634         __P4MASK(mmnm, 1),
1635         __P4MASK(mmtp, 2),
1636         __P4MASK(mmtm, 3),
1637         NULLMASK
1638 };
1639
1640 static const struct pmc_masks p4_mask_mbr[] = { /* mispred branch retired */
1641         __P4MASK(nbogus, 0),
1642         NULLMASK
1643 };
1644
1645 static const struct pmc_masks p4_mask_xa[] = { /* x87 assist */
1646         __P4MASK(fpsu, 0),
1647         __P4MASK(fpso, 1),
1648         __P4MASK(poao, 2),
1649         __P4MASK(poau, 3),
1650         __P4MASK(prea, 4),
1651         NULLMASK
1652 };
1653
1654 static const struct pmc_masks p4_mask_machclr[] = { /* machine clear */
1655         __P4MASK(clear, 0),
1656         __P4MASK(moclear, 2),
1657         __P4MASK(smclear, 3),
1658         NULLMASK
1659 };
1660
1661 /* P4 event parser */
1662 static int
1663 p4_allocate_pmc(enum pmc_event pe, char *ctrspec,
1664     struct pmc_op_pmcallocate *pmc_config)
1665 {
1666
1667         char    *e, *p, *q;
1668         int     count, has_tag, has_busreqtype, n;
1669         uint32_t cccractivemask;
1670         uint64_t evmask;
1671         const struct pmc_masks *pm, *pmask;
1672
1673         pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
1674         pmc_config->pm_md.pm_p4.pm_p4_cccrconfig =
1675             pmc_config->pm_md.pm_p4.pm_p4_escrconfig = 0;
1676
1677         pmask   = NULL;
1678         evmask  = 0;
1679         cccractivemask = 0x3;
1680         has_tag = has_busreqtype = 0;
1681
1682 #define __P4SETMASK(M) do {                             \
1683         pmask = p4_mask_##M;                            \
1684 } while (0)
1685
1686         switch (pe) {
1687         case PMC_EV_P4_TC_DELIVER_MODE:
1688                 __P4SETMASK(tcdm);
1689                 break;
1690         case PMC_EV_P4_BPU_FETCH_REQUEST:
1691                 __P4SETMASK(bfr);
1692                 break;
1693         case PMC_EV_P4_ITLB_REFERENCE:
1694                 __P4SETMASK(ir);
1695                 break;
1696         case PMC_EV_P4_MEMORY_CANCEL:
1697                 __P4SETMASK(memcan);
1698                 break;
1699         case PMC_EV_P4_MEMORY_COMPLETE:
1700                 __P4SETMASK(memcomp);
1701                 break;
1702         case PMC_EV_P4_LOAD_PORT_REPLAY:
1703                 __P4SETMASK(lpr);
1704                 break;
1705         case PMC_EV_P4_STORE_PORT_REPLAY:
1706                 __P4SETMASK(spr);
1707                 break;
1708         case PMC_EV_P4_MOB_LOAD_REPLAY:
1709                 __P4SETMASK(mlr);
1710                 break;
1711         case PMC_EV_P4_PAGE_WALK_TYPE:
1712                 __P4SETMASK(pwt);
1713                 break;
1714         case PMC_EV_P4_BSQ_CACHE_REFERENCE:
1715                 __P4SETMASK(bcr);
1716                 break;
1717         case PMC_EV_P4_IOQ_ALLOCATION:
1718                 __P4SETMASK(ia);
1719                 has_busreqtype = 1;
1720                 break;
1721         case PMC_EV_P4_IOQ_ACTIVE_ENTRIES:
1722                 __P4SETMASK(iae);
1723                 has_busreqtype = 1;
1724                 break;
1725         case PMC_EV_P4_FSB_DATA_ACTIVITY:
1726                 __P4SETMASK(fda);
1727                 break;
1728         case PMC_EV_P4_BSQ_ALLOCATION:
1729                 __P4SETMASK(ba);
1730                 break;
1731         case PMC_EV_P4_SSE_INPUT_ASSIST:
1732                 __P4SETMASK(sia);
1733                 break;
1734         case PMC_EV_P4_PACKED_SP_UOP:
1735                 __P4SETMASK(psu);
1736                 break;
1737         case PMC_EV_P4_PACKED_DP_UOP:
1738                 __P4SETMASK(pdu);
1739                 break;
1740         case PMC_EV_P4_SCALAR_SP_UOP:
1741                 __P4SETMASK(ssu);
1742                 break;
1743         case PMC_EV_P4_SCALAR_DP_UOP:
1744                 __P4SETMASK(sdu);
1745                 break;
1746         case PMC_EV_P4_64BIT_MMX_UOP:
1747                 __P4SETMASK(64bmu);
1748                 break;
1749         case PMC_EV_P4_128BIT_MMX_UOP:
1750                 __P4SETMASK(128bmu);
1751                 break;
1752         case PMC_EV_P4_X87_FP_UOP:
1753                 __P4SETMASK(xfu);
1754                 break;
1755         case PMC_EV_P4_X87_SIMD_MOVES_UOP:
1756                 __P4SETMASK(xsmu);
1757                 break;
1758         case PMC_EV_P4_GLOBAL_POWER_EVENTS:
1759                 __P4SETMASK(gpe);
1760                 break;
1761         case PMC_EV_P4_TC_MS_XFER:
1762                 __P4SETMASK(tmx);
1763                 break;
1764         case PMC_EV_P4_UOP_QUEUE_WRITES:
1765                 __P4SETMASK(uqw);
1766                 break;
1767         case PMC_EV_P4_RETIRED_MISPRED_BRANCH_TYPE:
1768                 __P4SETMASK(rmbt);
1769                 break;
1770         case PMC_EV_P4_RETIRED_BRANCH_TYPE:
1771                 __P4SETMASK(rbt);
1772                 break;
1773         case PMC_EV_P4_RESOURCE_STALL:
1774                 __P4SETMASK(rs);
1775                 break;
1776         case PMC_EV_P4_WC_BUFFER:
1777                 __P4SETMASK(wb);
1778                 break;
1779         case PMC_EV_P4_BSQ_ACTIVE_ENTRIES:
1780         case PMC_EV_P4_B2B_CYCLES:
1781         case PMC_EV_P4_BNR:
1782         case PMC_EV_P4_SNOOP:
1783         case PMC_EV_P4_RESPONSE:
1784                 break;
1785         case PMC_EV_P4_FRONT_END_EVENT:
1786                 __P4SETMASK(fee);
1787                 break;
1788         case PMC_EV_P4_EXECUTION_EVENT:
1789                 __P4SETMASK(ee);
1790                 break;
1791         case PMC_EV_P4_REPLAY_EVENT:
1792                 __P4SETMASK(re);
1793                 break;
1794         case PMC_EV_P4_INSTR_RETIRED:
1795                 __P4SETMASK(insret);
1796                 break;
1797         case PMC_EV_P4_UOPS_RETIRED:
1798                 __P4SETMASK(ur);
1799                 break;
1800         case PMC_EV_P4_UOP_TYPE:
1801                 __P4SETMASK(ut);
1802                 break;
1803         case PMC_EV_P4_BRANCH_RETIRED:
1804                 __P4SETMASK(br);
1805                 break;
1806         case PMC_EV_P4_MISPRED_BRANCH_RETIRED:
1807                 __P4SETMASK(mbr);
1808                 break;
1809         case PMC_EV_P4_X87_ASSIST:
1810                 __P4SETMASK(xa);
1811                 break;
1812         case PMC_EV_P4_MACHINE_CLEAR:
1813                 __P4SETMASK(machclr);
1814                 break;
1815         default:
1816                 return (-1);
1817         }
1818
1819         /* process additional flags */
1820         while ((p = strsep(&ctrspec, ",")) != NULL) {
1821                 if (KWPREFIXMATCH(p, P4_KW_ACTIVE)) {
1822                         q = strchr(p, '=');
1823                         if (*++q == '\0') /* skip '=' */
1824                                 return (-1);
1825
1826                         if (strcasecmp(q, P4_KW_ACTIVE_NONE) == 0)
1827                                 cccractivemask = 0x0;
1828                         else if (strcasecmp(q, P4_KW_ACTIVE_SINGLE) == 0)
1829                                 cccractivemask = 0x1;
1830                         else if (strcasecmp(q, P4_KW_ACTIVE_BOTH) == 0)
1831                                 cccractivemask = 0x2;
1832                         else if (strcasecmp(q, P4_KW_ACTIVE_ANY) == 0)
1833                                 cccractivemask = 0x3;
1834                         else
1835                                 return (-1);
1836
1837                 } else if (KWPREFIXMATCH(p, P4_KW_BUSREQTYPE)) {
1838                         if (has_busreqtype == 0)
1839                                 return (-1);
1840
1841                         q = strchr(p, '=');
1842                         if (*++q == '\0') /* skip '=' */
1843                                 return (-1);
1844
1845                         count = strtol(q, &e, 0);
1846                         if (e == q || *e != '\0')
1847                                 return (-1);
1848                         evmask = (evmask & ~0x1F) | (count & 0x1F);
1849                 } else if (KWMATCH(p, P4_KW_CASCADE))
1850                         pmc_config->pm_caps |= PMC_CAP_CASCADE;
1851                 else if (KWMATCH(p, P4_KW_EDGE))
1852                         pmc_config->pm_caps |= PMC_CAP_EDGE;
1853                 else if (KWMATCH(p, P4_KW_INV))
1854                         pmc_config->pm_caps |= PMC_CAP_INVERT;
1855                 else if (KWPREFIXMATCH(p, P4_KW_MASK "=")) {
1856                         if ((n = pmc_parse_mask(pmask, p, &evmask)) < 0)
1857                                 return (-1);
1858                         pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
1859                 } else if (KWMATCH(p, P4_KW_OS))
1860                         pmc_config->pm_caps |= PMC_CAP_SYSTEM;
1861                 else if (KWMATCH(p, P4_KW_PRECISE))
1862                         pmc_config->pm_caps |= PMC_CAP_PRECISE;
1863                 else if (KWPREFIXMATCH(p, P4_KW_TAG "=")) {
1864                         if (has_tag == 0)
1865                                 return (-1);
1866
1867                         q = strchr(p, '=');
1868                         if (*++q == '\0') /* skip '=' */
1869                                 return (-1);
1870
1871                         count = strtol(q, &e, 0);
1872                         if (e == q || *e != '\0')
1873                                 return (-1);
1874
1875                         pmc_config->pm_caps |= PMC_CAP_TAGGING;
1876                         pmc_config->pm_md.pm_p4.pm_p4_escrconfig |=
1877                             P4_ESCR_TO_TAG_VALUE(count);
1878                 } else if (KWPREFIXMATCH(p, P4_KW_THRESHOLD "=")) {
1879                         q = strchr(p, '=');
1880                         if (*++q == '\0') /* skip '=' */
1881                                 return (-1);
1882
1883                         count = strtol(q, &e, 0);
1884                         if (e == q || *e != '\0')
1885                                 return (-1);
1886
1887                         pmc_config->pm_caps |= PMC_CAP_THRESHOLD;
1888                         pmc_config->pm_md.pm_p4.pm_p4_cccrconfig &=
1889                             ~P4_CCCR_THRESHOLD_MASK;
1890                         pmc_config->pm_md.pm_p4.pm_p4_cccrconfig |=
1891                             P4_CCCR_TO_THRESHOLD(count);
1892                 } else if (KWMATCH(p, P4_KW_USR))
1893                         pmc_config->pm_caps |= PMC_CAP_USER;
1894                 else
1895                         return (-1);
1896         }
1897
1898         /* other post processing */
1899         if (pe == PMC_EV_P4_IOQ_ALLOCATION ||
1900             pe == PMC_EV_P4_FSB_DATA_ACTIVITY ||
1901             pe == PMC_EV_P4_BSQ_ALLOCATION)
1902                 pmc_config->pm_caps |= PMC_CAP_EDGE;
1903
1904         /* fill in thread activity mask */
1905         pmc_config->pm_md.pm_p4.pm_p4_cccrconfig |=
1906             P4_CCCR_TO_ACTIVE_THREAD(cccractivemask);
1907
1908         if (evmask)
1909                 pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
1910
1911         switch (pe) {
1912         case PMC_EV_P4_FSB_DATA_ACTIVITY:
1913                 if ((evmask & 0x06) == 0x06 ||
1914                     (evmask & 0x18) == 0x18)
1915                         return (-1); /* can't have own+other bits together */
1916                 if (evmask == 0) /* default:drdy-{drv,own}+dbsy{drv,own} */
1917                         evmask = 0x1D;
1918                 break;
1919         case PMC_EV_P4_MACHINE_CLEAR:
1920                 /* only one bit is allowed to be set */
1921                 if ((evmask & (evmask - 1)) != 0)
1922                         return (-1);
1923                 if (evmask == 0) {
1924                         evmask = 0x1;   /* 'CLEAR' */
1925                         pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
1926                 }
1927                 break;
1928         default:
1929                 if (evmask == 0 && pmask) {
1930                         for (pm = pmask; pm->pm_name; pm++)
1931                                 evmask |= pm->pm_value;
1932                         pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
1933                 }
1934         }
1935
1936         pmc_config->pm_md.pm_p4.pm_p4_escrconfig =
1937             P4_ESCR_TO_EVENT_MASK(evmask);
1938
1939         return (0);
1940 }
1941
1942 #endif
1943
1944 #if defined(__i386__)
1945
1946 /*
1947  * Pentium style PMCs
1948  */
1949
1950 static struct pmc_event_alias p5_aliases[] = {
1951         EV_ALIAS("branches",            "p5-taken-branches"),
1952         EV_ALIAS("cycles",              "tsc"),
1953         EV_ALIAS("dc-misses",           "p5-data-read-miss-or-write-miss"),
1954         EV_ALIAS("ic-misses",           "p5-code-cache-miss"),
1955         EV_ALIAS("instructions",        "p5-instructions-executed"),
1956         EV_ALIAS("interrupts",          "p5-hardware-interrupts"),
1957         EV_ALIAS("unhalted-cycles",
1958             "p5-number-of-cycles-not-in-halt-state"),
1959         EV_ALIAS(NULL, NULL)
1960 };
1961
1962 static int
1963 p5_allocate_pmc(enum pmc_event pe, char *ctrspec,
1964     struct pmc_op_pmcallocate *pmc_config)
1965 {
1966         return (-1 || pe || ctrspec || pmc_config); /* shut up gcc */
1967 }
1968
1969 /*
1970  * Pentium Pro style PMCs.  These PMCs are found in Pentium II, Pentium III,
1971  * and Pentium M CPUs.
1972  */
1973
1974 static struct pmc_event_alias p6_aliases[] = {
1975         EV_ALIAS("branches",            "p6-br-inst-retired"),
1976         EV_ALIAS("branch-mispredicts",  "p6-br-miss-pred-retired"),
1977         EV_ALIAS("cycles",              "tsc"),
1978         EV_ALIAS("dc-misses",           "p6-dcu-lines-in"),
1979         EV_ALIAS("ic-misses",           "p6-ifu-fetch-miss"),
1980         EV_ALIAS("instructions",        "p6-inst-retired"),
1981         EV_ALIAS("interrupts",          "p6-hw-int-rx"),
1982         EV_ALIAS("unhalted-cycles",     "p6-cpu-clk-unhalted"),
1983         EV_ALIAS(NULL, NULL)
1984 };
1985
1986 #define P6_KW_CMASK     "cmask"
1987 #define P6_KW_EDGE      "edge"
1988 #define P6_KW_INV       "inv"
1989 #define P6_KW_OS        "os"
1990 #define P6_KW_UMASK     "umask"
1991 #define P6_KW_USR       "usr"
1992
1993 static struct pmc_masks p6_mask_mesi[] = {
1994         PMCMASK(m,      0x01),
1995         PMCMASK(e,      0x02),
1996         PMCMASK(s,      0x04),
1997         PMCMASK(i,      0x08),
1998         NULLMASK
1999 };
2000
2001 static struct pmc_masks p6_mask_mesihw[] = {
2002         PMCMASK(m,      0x01),
2003         PMCMASK(e,      0x02),
2004         PMCMASK(s,      0x04),
2005         PMCMASK(i,      0x08),
2006         PMCMASK(nonhw,  0x00),
2007         PMCMASK(hw,     0x10),
2008         PMCMASK(both,   0x30),
2009         NULLMASK
2010 };
2011
2012 static struct pmc_masks p6_mask_hw[] = {
2013         PMCMASK(nonhw,  0x00),
2014         PMCMASK(hw,     0x10),
2015         PMCMASK(both,   0x30),
2016         NULLMASK
2017 };
2018
2019 static struct pmc_masks p6_mask_any[] = {
2020         PMCMASK(self,   0x00),
2021         PMCMASK(any,    0x20),
2022         NULLMASK
2023 };
2024
2025 static struct pmc_masks p6_mask_ekp[] = {
2026         PMCMASK(nta,    0x00),
2027         PMCMASK(t1,     0x01),
2028         PMCMASK(t2,     0x02),
2029         PMCMASK(wos,    0x03),
2030         NULLMASK
2031 };
2032
2033 static struct pmc_masks p6_mask_pps[] = {
2034         PMCMASK(packed-and-scalar, 0x00),
2035         PMCMASK(scalar, 0x01),
2036         NULLMASK
2037 };
2038
2039 static struct pmc_masks p6_mask_mite[] = {
2040         PMCMASK(packed-multiply,         0x01),
2041         PMCMASK(packed-shift,           0x02),
2042         PMCMASK(pack,                   0x04),
2043         PMCMASK(unpack,                 0x08),
2044         PMCMASK(packed-logical,         0x10),
2045         PMCMASK(packed-arithmetic,      0x20),
2046         NULLMASK
2047 };
2048
2049 static struct pmc_masks p6_mask_fmt[] = {
2050         PMCMASK(mmxtofp,        0x00),
2051         PMCMASK(fptommx,        0x01),
2052         NULLMASK
2053 };
2054
2055 static struct pmc_masks p6_mask_sr[] = {
2056         PMCMASK(es,     0x01),
2057         PMCMASK(ds,     0x02),
2058         PMCMASK(fs,     0x04),
2059         PMCMASK(gs,     0x08),
2060         NULLMASK
2061 };
2062
2063 static struct pmc_masks p6_mask_eet[] = {
2064         PMCMASK(all,    0x00),
2065         PMCMASK(freq,   0x02),
2066         NULLMASK
2067 };
2068
2069 static struct pmc_masks p6_mask_efur[] = {
2070         PMCMASK(all,    0x00),
2071         PMCMASK(loadop, 0x01),
2072         PMCMASK(stdsta, 0x02),
2073         NULLMASK
2074 };
2075
2076 static struct pmc_masks p6_mask_essir[] = {
2077         PMCMASK(sse-packed-single,      0x00),
2078         PMCMASK(sse-packed-single-scalar-single, 0x01),
2079         PMCMASK(sse2-packed-double,     0x02),
2080         PMCMASK(sse2-scalar-double,     0x03),
2081         NULLMASK
2082 };
2083
2084 static struct pmc_masks p6_mask_esscir[] = {
2085         PMCMASK(sse-packed-single,      0x00),
2086         PMCMASK(sse-scalar-single,      0x01),
2087         PMCMASK(sse2-packed-double,     0x02),
2088         PMCMASK(sse2-scalar-double,     0x03),
2089         NULLMASK
2090 };
2091
2092 /* P6 event parser */
2093 static int
2094 p6_allocate_pmc(enum pmc_event pe, char *ctrspec,
2095     struct pmc_op_pmcallocate *pmc_config)
2096 {
2097         char *e, *p, *q;
2098         uint64_t evmask;
2099         int count, n;
2100         const struct pmc_masks *pm, *pmask;
2101
2102         pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
2103         pmc_config->pm_md.pm_ppro.pm_ppro_config = 0;
2104
2105         evmask = 0;
2106
2107 #define P6MASKSET(M)    pmask = p6_mask_ ## M
2108
2109         switch(pe) {
2110         case PMC_EV_P6_L2_IFETCH:       P6MASKSET(mesi); break;
2111         case PMC_EV_P6_L2_LD:           P6MASKSET(mesi); break;
2112         case PMC_EV_P6_L2_ST:           P6MASKSET(mesi); break;
2113         case PMC_EV_P6_L2_RQSTS:        P6MASKSET(mesi); break;
2114         case PMC_EV_P6_BUS_DRDY_CLOCKS:
2115         case PMC_EV_P6_BUS_LOCK_CLOCKS:
2116         case PMC_EV_P6_BUS_TRAN_BRD:
2117         case PMC_EV_P6_BUS_TRAN_RFO:
2118         case PMC_EV_P6_BUS_TRANS_WB:
2119         case PMC_EV_P6_BUS_TRAN_IFETCH:
2120         case PMC_EV_P6_BUS_TRAN_INVAL:
2121         case PMC_EV_P6_BUS_TRAN_PWR:
2122         case PMC_EV_P6_BUS_TRANS_P:
2123         case PMC_EV_P6_BUS_TRANS_IO:
2124         case PMC_EV_P6_BUS_TRAN_DEF:
2125         case PMC_EV_P6_BUS_TRAN_BURST:
2126         case PMC_EV_P6_BUS_TRAN_ANY:
2127         case PMC_EV_P6_BUS_TRAN_MEM:
2128                 P6MASKSET(any); break;
2129         case PMC_EV_P6_EMON_KNI_PREF_DISPATCHED:
2130         case PMC_EV_P6_EMON_KNI_PREF_MISS:
2131                 P6MASKSET(ekp); break;
2132         case PMC_EV_P6_EMON_KNI_INST_RETIRED:
2133         case PMC_EV_P6_EMON_KNI_COMP_INST_RET:
2134                 P6MASKSET(pps); break;
2135         case PMC_EV_P6_MMX_INSTR_TYPE_EXEC:
2136                 P6MASKSET(mite); break;
2137         case PMC_EV_P6_FP_MMX_TRANS:
2138                 P6MASKSET(fmt); break;
2139         case PMC_EV_P6_SEG_RENAME_STALLS:
2140         case PMC_EV_P6_SEG_REG_RENAMES:
2141                 P6MASKSET(sr);  break;
2142         case PMC_EV_P6_EMON_EST_TRANS:
2143                 P6MASKSET(eet); break;
2144         case PMC_EV_P6_EMON_FUSED_UOPS_RET:
2145                 P6MASKSET(efur); break;
2146         case PMC_EV_P6_EMON_SSE_SSE2_INST_RETIRED:
2147                 P6MASKSET(essir); break;
2148         case PMC_EV_P6_EMON_SSE_SSE2_COMP_INST_RETIRED:
2149                 P6MASKSET(esscir); break;
2150         default:
2151                 pmask = NULL;
2152                 break;
2153         }
2154
2155         /* Pentium M PMCs have a few events with different semantics */
2156         if (cpu_info.pm_cputype == PMC_CPU_INTEL_PM) {
2157                 if (pe == PMC_EV_P6_L2_LD ||
2158                     pe == PMC_EV_P6_L2_LINES_IN ||
2159                     pe == PMC_EV_P6_L2_LINES_OUT)
2160                         P6MASKSET(mesihw);
2161                 else if (pe == PMC_EV_P6_L2_M_LINES_OUTM)
2162                         P6MASKSET(hw);
2163         }
2164
2165         /* Parse additional modifiers if present */
2166         while ((p = strsep(&ctrspec, ",")) != NULL) {
2167                 if (KWPREFIXMATCH(p, P6_KW_CMASK "=")) {
2168                         q = strchr(p, '=');
2169                         if (*++q == '\0') /* skip '=' */
2170                                 return (-1);
2171                         count = strtol(q, &e, 0);
2172                         if (e == q || *e != '\0')
2173                                 return (-1);
2174                         pmc_config->pm_caps |= PMC_CAP_THRESHOLD;
2175                         pmc_config->pm_md.pm_ppro.pm_ppro_config |=
2176                             P6_EVSEL_TO_CMASK(count);
2177                 } else if (KWMATCH(p, P6_KW_EDGE)) {
2178                         pmc_config->pm_caps |= PMC_CAP_EDGE;
2179                 } else if (KWMATCH(p, P6_KW_INV)) {
2180                         pmc_config->pm_caps |= PMC_CAP_INVERT;
2181                 } else if (KWMATCH(p, P6_KW_OS)) {
2182                         pmc_config->pm_caps |= PMC_CAP_SYSTEM;
2183                 } else if (KWPREFIXMATCH(p, P6_KW_UMASK "=")) {
2184                         evmask = 0;
2185                         if ((n = pmc_parse_mask(pmask, p, &evmask)) < 0)
2186                                 return (-1);
2187                         if ((pe == PMC_EV_P6_BUS_DRDY_CLOCKS ||
2188                              pe == PMC_EV_P6_BUS_LOCK_CLOCKS ||
2189                              pe == PMC_EV_P6_BUS_TRAN_BRD ||
2190                              pe == PMC_EV_P6_BUS_TRAN_RFO ||
2191                              pe == PMC_EV_P6_BUS_TRAN_IFETCH ||
2192                              pe == PMC_EV_P6_BUS_TRAN_INVAL ||
2193                              pe == PMC_EV_P6_BUS_TRAN_PWR ||
2194                              pe == PMC_EV_P6_BUS_TRAN_DEF ||
2195                              pe == PMC_EV_P6_BUS_TRAN_BURST ||
2196                              pe == PMC_EV_P6_BUS_TRAN_ANY ||
2197                              pe == PMC_EV_P6_BUS_TRAN_MEM ||
2198                              pe == PMC_EV_P6_BUS_TRANS_IO ||
2199                              pe == PMC_EV_P6_BUS_TRANS_P ||
2200                              pe == PMC_EV_P6_BUS_TRANS_WB ||
2201                              pe == PMC_EV_P6_EMON_EST_TRANS ||
2202                              pe == PMC_EV_P6_EMON_FUSED_UOPS_RET ||
2203                              pe == PMC_EV_P6_EMON_KNI_COMP_INST_RET ||
2204                              pe == PMC_EV_P6_EMON_KNI_INST_RETIRED ||
2205                              pe == PMC_EV_P6_EMON_KNI_PREF_DISPATCHED ||
2206                              pe == PMC_EV_P6_EMON_KNI_PREF_MISS ||
2207                              pe == PMC_EV_P6_EMON_SSE_SSE2_COMP_INST_RETIRED ||
2208                              pe == PMC_EV_P6_EMON_SSE_SSE2_INST_RETIRED ||
2209                              pe == PMC_EV_P6_FP_MMX_TRANS)
2210                             && (n > 1)) /* Only one mask keyword is allowed. */
2211                                 return (-1);
2212                         pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
2213                 } else if (KWMATCH(p, P6_KW_USR)) {
2214                         pmc_config->pm_caps |= PMC_CAP_USER;
2215                 } else
2216                         return (-1);
2217         }
2218
2219         /* post processing */
2220         switch (pe) {
2221
2222                 /*
2223                  * The following events default to an evmask of 0
2224                  */
2225
2226                 /* default => 'self' */
2227         case PMC_EV_P6_BUS_DRDY_CLOCKS:
2228         case PMC_EV_P6_BUS_LOCK_CLOCKS:
2229         case PMC_EV_P6_BUS_TRAN_BRD:
2230         case PMC_EV_P6_BUS_TRAN_RFO:
2231         case PMC_EV_P6_BUS_TRANS_WB:
2232         case PMC_EV_P6_BUS_TRAN_IFETCH:
2233         case PMC_EV_P6_BUS_TRAN_INVAL:
2234         case PMC_EV_P6_BUS_TRAN_PWR:
2235         case PMC_EV_P6_BUS_TRANS_P:
2236         case PMC_EV_P6_BUS_TRANS_IO:
2237         case PMC_EV_P6_BUS_TRAN_DEF:
2238         case PMC_EV_P6_BUS_TRAN_BURST:
2239         case PMC_EV_P6_BUS_TRAN_ANY:
2240         case PMC_EV_P6_BUS_TRAN_MEM:
2241
2242                 /* default => 'nta' */
2243         case PMC_EV_P6_EMON_KNI_PREF_DISPATCHED:
2244         case PMC_EV_P6_EMON_KNI_PREF_MISS:
2245
2246                 /* default => 'packed and scalar' */
2247         case PMC_EV_P6_EMON_KNI_INST_RETIRED:
2248         case PMC_EV_P6_EMON_KNI_COMP_INST_RET:
2249
2250                 /* default => 'mmx to fp transitions' */
2251         case PMC_EV_P6_FP_MMX_TRANS:
2252
2253                 /* default => 'SSE Packed Single' */
2254         case PMC_EV_P6_EMON_SSE_SSE2_INST_RETIRED:
2255         case PMC_EV_P6_EMON_SSE_SSE2_COMP_INST_RETIRED:
2256
2257                 /* default => 'all fused micro-ops' */
2258         case PMC_EV_P6_EMON_FUSED_UOPS_RET:
2259
2260                 /* default => 'all transitions' */
2261         case PMC_EV_P6_EMON_EST_TRANS:
2262                 break;
2263
2264         case PMC_EV_P6_MMX_UOPS_EXEC:
2265                 evmask = 0x0F;          /* only value allowed */
2266                 break;
2267
2268         default:
2269                 /*
2270                  * For all other events, set the default event mask
2271                  * to a logical OR of all the allowed event mask bits.
2272                  */
2273                 if (evmask == 0 && pmask) {
2274                         for (pm = pmask; pm->pm_name; pm++)
2275                                 evmask |= pm->pm_value;
2276                         pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
2277                 }
2278
2279                 break;
2280         }
2281
2282         if (pmc_config->pm_caps & PMC_CAP_QUALIFIER)
2283                 pmc_config->pm_md.pm_ppro.pm_ppro_config |=
2284                     P6_EVSEL_TO_UMASK(evmask);
2285
2286         return (0);
2287 }
2288
2289 #endif
2290
2291 #if     defined(__i386__) || defined(__amd64__)
2292 static int
2293 tsc_allocate_pmc(enum pmc_event pe, char *ctrspec,
2294     struct pmc_op_pmcallocate *pmc_config)
2295 {
2296         if (pe != PMC_EV_TSC_TSC)
2297                 return (-1);
2298
2299         /* TSC events must be unqualified. */
2300         if (ctrspec && *ctrspec != '\0')
2301                 return (-1);
2302
2303         pmc_config->pm_md.pm_amd.pm_amd_config = 0;
2304         pmc_config->pm_caps |= PMC_CAP_READ;
2305
2306         return (0);
2307 }
2308 #endif
2309
2310 static struct pmc_event_alias generic_aliases[] = {
2311         EV_ALIAS("instructions",                "SOFT-CLOCK.HARD"),
2312         EV_ALIAS(NULL, NULL)
2313 };
2314
2315 static int
2316 soft_allocate_pmc(enum pmc_event pe, char *ctrspec,
2317     struct pmc_op_pmcallocate *pmc_config)
2318 {
2319         (void)ctrspec;
2320         (void)pmc_config;
2321
2322         if ((int)pe < PMC_EV_SOFT_FIRST || (int)pe > PMC_EV_SOFT_LAST)
2323                 return (-1);
2324
2325         pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
2326         return (0);
2327 }
2328
2329 #if     defined(__XSCALE__)
2330
2331 static struct pmc_event_alias xscale_aliases[] = {
2332         EV_ALIAS("branches",            "BRANCH_RETIRED"),
2333         EV_ALIAS("branch-mispredicts",  "BRANCH_MISPRED"),
2334         EV_ALIAS("dc-misses",           "DC_MISS"),
2335         EV_ALIAS("ic-misses",           "IC_MISS"),
2336         EV_ALIAS("instructions",        "INSTR_RETIRED"),
2337         EV_ALIAS(NULL, NULL)
2338 };
2339 static int
2340 xscale_allocate_pmc(enum pmc_event pe, char *ctrspec __unused,
2341     struct pmc_op_pmcallocate *pmc_config __unused)
2342 {
2343         switch (pe) {
2344         default:
2345                 break;
2346         }
2347
2348         return (0);
2349 }
2350 #endif
2351
2352 #if defined(__mips__)
2353
2354 static struct pmc_event_alias mips24k_aliases[] = {
2355         EV_ALIAS("instructions",        "INSTR_EXECUTED"),
2356         EV_ALIAS("branches",            "BRANCH_COMPLETED"),
2357         EV_ALIAS("branch-mispredicts",  "BRANCH_MISPRED"),
2358         EV_ALIAS(NULL, NULL)
2359 };
2360
2361 static struct pmc_event_alias octeon_aliases[] = {
2362         EV_ALIAS("instructions",        "RET"),
2363         EV_ALIAS("branches",            "BR"),
2364         EV_ALIAS("branch-mispredicts",  "BRMIS"),
2365         EV_ALIAS(NULL, NULL)
2366 };
2367
2368 #define MIPS_KW_OS              "os"
2369 #define MIPS_KW_USR             "usr"
2370 #define MIPS_KW_ANYTHREAD       "anythread"
2371
2372 static int
2373 mips_allocate_pmc(enum pmc_event pe, char *ctrspec __unused,
2374                   struct pmc_op_pmcallocate *pmc_config __unused)
2375 {
2376         char *p;
2377
2378         (void) pe;
2379
2380         pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
2381
2382         while ((p = strsep(&ctrspec, ",")) != NULL) {
2383                 if (KWMATCH(p, MIPS_KW_OS))
2384                         pmc_config->pm_caps |= PMC_CAP_SYSTEM;
2385                 else if (KWMATCH(p, MIPS_KW_USR))
2386                         pmc_config->pm_caps |= PMC_CAP_USER;
2387                 else if (KWMATCH(p, MIPS_KW_ANYTHREAD))
2388                         pmc_config->pm_caps |= (PMC_CAP_USER | PMC_CAP_SYSTEM);
2389                 else
2390                         return (-1);
2391         }
2392
2393         return (0);
2394 }
2395
2396 #endif /* __mips__ */
2397
2398 #if defined(__powerpc__)
2399
2400 static struct pmc_event_alias ppc7450_aliases[] = {
2401         EV_ALIAS("instructions",        "INSTR_COMPLETED"),
2402         EV_ALIAS("branches",            "BRANCHES_COMPLETED"),
2403         EV_ALIAS("branch-mispredicts",  "MISPREDICTED_BRANCHES"),
2404         EV_ALIAS(NULL, NULL)
2405 };
2406
2407 #define PPC7450_KW_OS           "os"
2408 #define PPC7450_KW_USR          "usr"
2409 #define PPC7450_KW_ANYTHREAD    "anythread"
2410
2411 static int
2412 ppc7450_allocate_pmc(enum pmc_event pe, char *ctrspec __unused,
2413                   struct pmc_op_pmcallocate *pmc_config __unused)
2414 {
2415         char *p;
2416
2417         (void) pe;
2418
2419         pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
2420
2421         while ((p = strsep(&ctrspec, ",")) != NULL) {
2422                 if (KWMATCH(p, PPC7450_KW_OS))
2423                         pmc_config->pm_caps |= PMC_CAP_SYSTEM;
2424                 else if (KWMATCH(p, PPC7450_KW_USR))
2425                         pmc_config->pm_caps |= PMC_CAP_USER;
2426                 else if (KWMATCH(p, PPC7450_KW_ANYTHREAD))
2427                         pmc_config->pm_caps |= (PMC_CAP_USER | PMC_CAP_SYSTEM);
2428                 else
2429                         return (-1);
2430         }
2431
2432         return (0);
2433 }
2434 #endif /* __powerpc__ */
2435
2436
2437 /*
2438  * Match an event name `name' with its canonical form.
2439  *
2440  * Matches are case insensitive and spaces, periods, underscores and
2441  * hyphen characters are considered to match each other.
2442  *
2443  * Returns 1 for a match, 0 otherwise.
2444  */
2445
2446 static int
2447 pmc_match_event_name(const char *name, const char *canonicalname)
2448 {
2449         int cc, nc;
2450         const unsigned char *c, *n;
2451
2452         c = (const unsigned char *) canonicalname;
2453         n = (const unsigned char *) name;
2454
2455         for (; (nc = *n) && (cc = *c); n++, c++) {
2456
2457                 if ((nc == ' ' || nc == '_' || nc == '-' || nc == '.') &&
2458                     (cc == ' ' || cc == '_' || cc == '-' || cc == '.'))
2459                         continue;
2460
2461                 if (toupper(nc) == toupper(cc))
2462                         continue;
2463
2464
2465                 return (0);
2466         }
2467
2468         if (*n == '\0' && *c == '\0')
2469                 return (1);
2470
2471         return (0);
2472 }
2473
2474 /*
2475  * Match an event name against all the event named supported by a
2476  * PMC class.
2477  *
2478  * Returns an event descriptor pointer on match or NULL otherwise.
2479  */
2480 static const struct pmc_event_descr *
2481 pmc_match_event_class(const char *name,
2482     const struct pmc_class_descr *pcd)
2483 {
2484         size_t n;
2485         const struct pmc_event_descr *ev;
2486
2487         ev = pcd->pm_evc_event_table;
2488         for (n = 0; n < pcd->pm_evc_event_table_size; n++, ev++)
2489                 if (pmc_match_event_name(name, ev->pm_ev_name))
2490                         return (ev);
2491
2492         return (NULL);
2493 }
2494
2495 static int
2496 pmc_mdep_is_compatible_class(enum pmc_class pc)
2497 {
2498         size_t n;
2499
2500         for (n = 0; n < pmc_mdep_class_list_size; n++)
2501                 if (pmc_mdep_class_list[n] == pc)
2502                         return (1);
2503         return (0);
2504 }
2505
2506 /*
2507  * API entry points
2508  */
2509
2510 int
2511 pmc_allocate(const char *ctrspec, enum pmc_mode mode,
2512     uint32_t flags, int cpu, pmc_id_t *pmcid)
2513 {
2514         size_t n;
2515         int retval;
2516         char *r, *spec_copy;
2517         const char *ctrname;
2518         const struct pmc_event_descr *ev;
2519         const struct pmc_event_alias *alias;
2520         struct pmc_op_pmcallocate pmc_config;
2521         const struct pmc_class_descr *pcd;
2522
2523         spec_copy = NULL;
2524         retval    = -1;
2525
2526         if (mode != PMC_MODE_SS && mode != PMC_MODE_TS &&
2527             mode != PMC_MODE_SC && mode != PMC_MODE_TC) {
2528                 errno = EINVAL;
2529                 goto out;
2530         }
2531
2532         /* replace an event alias with the canonical event specifier */
2533         if (pmc_mdep_event_aliases)
2534                 for (alias = pmc_mdep_event_aliases; alias->pm_alias; alias++)
2535                         if (!strcasecmp(ctrspec, alias->pm_alias)) {
2536                                 spec_copy = strdup(alias->pm_spec);
2537                                 break;
2538                         }
2539
2540         if (spec_copy == NULL)
2541                 spec_copy = strdup(ctrspec);
2542
2543         r = spec_copy;
2544         ctrname = strsep(&r, ",");
2545
2546         /*
2547          * If a explicit class prefix was given by the user, restrict the
2548          * search for the event to the specified PMC class.
2549          */
2550         ev = NULL;
2551         for (n = 0; n < PMC_CLASS_TABLE_SIZE; n++) {
2552                 pcd = pmc_class_table[n];
2553                 if (pmc_mdep_is_compatible_class(pcd->pm_evc_class) &&
2554                     strncasecmp(ctrname, pcd->pm_evc_name,
2555                                 pcd->pm_evc_name_size) == 0) {
2556                         if ((ev = pmc_match_event_class(ctrname +
2557                             pcd->pm_evc_name_size, pcd)) == NULL) {
2558                                 errno = EINVAL;
2559                                 goto out;
2560                         }
2561                         break;
2562                 }
2563         }
2564
2565         /*
2566          * Otherwise, search for this event in all compatible PMC
2567          * classes.
2568          */
2569         for (n = 0; ev == NULL && n < PMC_CLASS_TABLE_SIZE; n++) {
2570                 pcd = pmc_class_table[n];
2571                 if (pmc_mdep_is_compatible_class(pcd->pm_evc_class))
2572                         ev = pmc_match_event_class(ctrname, pcd);
2573         }
2574
2575         if (ev == NULL) {
2576                 errno = EINVAL;
2577                 goto out;
2578         }
2579
2580         bzero(&pmc_config, sizeof(pmc_config));
2581         pmc_config.pm_ev    = ev->pm_ev_code;
2582         pmc_config.pm_class = pcd->pm_evc_class;
2583         pmc_config.pm_cpu   = cpu;
2584         pmc_config.pm_mode  = mode;
2585         pmc_config.pm_flags = flags;
2586
2587         if (PMC_IS_SAMPLING_MODE(mode))
2588                 pmc_config.pm_caps |= PMC_CAP_INTERRUPT;
2589
2590         if (pcd->pm_evc_allocate_pmc(ev->pm_ev_code, r, &pmc_config) < 0) {
2591                 errno = EINVAL;
2592                 goto out;
2593         }
2594
2595         if (PMC_CALL(PMCALLOCATE, &pmc_config) < 0)
2596                 goto out;
2597
2598         *pmcid = pmc_config.pm_pmcid;
2599
2600         retval = 0;
2601
2602  out:
2603         if (spec_copy)
2604                 free(spec_copy);
2605
2606         return (retval);
2607 }
2608
2609 int
2610 pmc_attach(pmc_id_t pmc, pid_t pid)
2611 {
2612         struct pmc_op_pmcattach pmc_attach_args;
2613
2614         pmc_attach_args.pm_pmc = pmc;
2615         pmc_attach_args.pm_pid = pid;
2616
2617         return (PMC_CALL(PMCATTACH, &pmc_attach_args));
2618 }
2619
2620 int
2621 pmc_capabilities(pmc_id_t pmcid, uint32_t *caps)
2622 {
2623         unsigned int i;
2624         enum pmc_class cl;
2625
2626         cl = PMC_ID_TO_CLASS(pmcid);
2627         for (i = 0; i < cpu_info.pm_nclass; i++)
2628                 if (cpu_info.pm_classes[i].pm_class == cl) {
2629                         *caps = cpu_info.pm_classes[i].pm_caps;
2630                         return (0);
2631                 }
2632         errno = EINVAL;
2633         return (-1);
2634 }
2635
2636 int
2637 pmc_configure_logfile(int fd)
2638 {
2639         struct pmc_op_configurelog cla;
2640
2641         cla.pm_logfd = fd;
2642         if (PMC_CALL(CONFIGURELOG, &cla) < 0)
2643                 return (-1);
2644         return (0);
2645 }
2646
2647 int
2648 pmc_cpuinfo(const struct pmc_cpuinfo **pci)
2649 {
2650         if (pmc_syscall == -1) {
2651                 errno = ENXIO;
2652                 return (-1);
2653         }
2654
2655         *pci = &cpu_info;
2656         return (0);
2657 }
2658
2659 int
2660 pmc_detach(pmc_id_t pmc, pid_t pid)
2661 {
2662         struct pmc_op_pmcattach pmc_detach_args;
2663
2664         pmc_detach_args.pm_pmc = pmc;
2665         pmc_detach_args.pm_pid = pid;
2666         return (PMC_CALL(PMCDETACH, &pmc_detach_args));
2667 }
2668
2669 int
2670 pmc_disable(int cpu, int pmc)
2671 {
2672         struct pmc_op_pmcadmin ssa;
2673
2674         ssa.pm_cpu = cpu;
2675         ssa.pm_pmc = pmc;
2676         ssa.pm_state = PMC_STATE_DISABLED;
2677         return (PMC_CALL(PMCADMIN, &ssa));
2678 }
2679
2680 int
2681 pmc_enable(int cpu, int pmc)
2682 {
2683         struct pmc_op_pmcadmin ssa;
2684
2685         ssa.pm_cpu = cpu;
2686         ssa.pm_pmc = pmc;
2687         ssa.pm_state = PMC_STATE_FREE;
2688         return (PMC_CALL(PMCADMIN, &ssa));
2689 }
2690
2691 /*
2692  * Return a list of events known to a given PMC class.  'cl' is the
2693  * PMC class identifier, 'eventnames' is the returned list of 'const
2694  * char *' pointers pointing to the names of the events. 'nevents' is
2695  * the number of event name pointers returned.
2696  *
2697  * The space for 'eventnames' is allocated using malloc(3).  The caller
2698  * is responsible for freeing this space when done.
2699  */
2700 int
2701 pmc_event_names_of_class(enum pmc_class cl, const char ***eventnames,
2702     int *nevents)
2703 {
2704         int count;
2705         const char **names;
2706         const struct pmc_event_descr *ev;
2707
2708         switch (cl)
2709         {
2710         case PMC_CLASS_IAF:
2711                 ev = iaf_event_table;
2712                 count = PMC_EVENT_TABLE_SIZE(iaf);
2713                 break;
2714         case PMC_CLASS_IAP:
2715                 /*
2716                  * Return the most appropriate set of event name
2717                  * spellings for the current CPU.
2718                  */
2719                 switch (cpu_info.pm_cputype) {
2720                 default:
2721                 case PMC_CPU_INTEL_ATOM:
2722                         ev = atom_event_table;
2723                         count = PMC_EVENT_TABLE_SIZE(atom);
2724                         break;
2725                 case PMC_CPU_INTEL_CORE:
2726                         ev = core_event_table;
2727                         count = PMC_EVENT_TABLE_SIZE(core);
2728                         break;
2729                 case PMC_CPU_INTEL_CORE2:
2730                 case PMC_CPU_INTEL_CORE2EXTREME:
2731                         ev = core2_event_table;
2732                         count = PMC_EVENT_TABLE_SIZE(core2);
2733                         break;
2734                 case PMC_CPU_INTEL_COREI7:
2735                         ev = corei7_event_table;
2736                         count = PMC_EVENT_TABLE_SIZE(corei7);
2737                         break;
2738                 case PMC_CPU_INTEL_HASWELL:
2739                         ev = haswell_event_table;
2740                         count = PMC_EVENT_TABLE_SIZE(haswell);
2741                         break;
2742                 case PMC_CPU_INTEL_IVYBRIDGE:
2743                         ev = ivybridge_event_table;
2744                         count = PMC_EVENT_TABLE_SIZE(ivybridge);
2745                         break;
2746                 case PMC_CPU_INTEL_IVYBRIDGE_XEON:
2747                         ev = ivybridge_xeon_event_table;
2748                         count = PMC_EVENT_TABLE_SIZE(ivybridge_xeon);
2749                         break;
2750                 case PMC_CPU_INTEL_SANDYBRIDGE:
2751                         ev = sandybridge_event_table;
2752                         count = PMC_EVENT_TABLE_SIZE(sandybridge);
2753                         break;
2754                 case PMC_CPU_INTEL_SANDYBRIDGE_XEON:
2755                         ev = sandybridge_xeon_event_table;
2756                         count = PMC_EVENT_TABLE_SIZE(sandybridge_xeon);
2757                         break;
2758                 case PMC_CPU_INTEL_WESTMERE:
2759                         ev = westmere_event_table;
2760                         count = PMC_EVENT_TABLE_SIZE(westmere);
2761                         break;
2762                 }
2763                 break;
2764         case PMC_CLASS_UCF:
2765                 ev = ucf_event_table;
2766                 count = PMC_EVENT_TABLE_SIZE(ucf);
2767                 break;
2768         case PMC_CLASS_UCP:
2769                 /*
2770                  * Return the most appropriate set of event name
2771                  * spellings for the current CPU.
2772                  */
2773                 switch (cpu_info.pm_cputype) {
2774                 default:
2775                 case PMC_CPU_INTEL_COREI7:
2776                         ev = corei7uc_event_table;
2777                         count = PMC_EVENT_TABLE_SIZE(corei7uc);
2778                         break;
2779                 case PMC_CPU_INTEL_HASWELL:
2780                         ev = haswelluc_event_table;
2781                         count = PMC_EVENT_TABLE_SIZE(haswelluc);
2782                         break;
2783                 case PMC_CPU_INTEL_SANDYBRIDGE:
2784                         ev = sandybridgeuc_event_table;
2785                         count = PMC_EVENT_TABLE_SIZE(sandybridgeuc);
2786                         break;
2787                 case PMC_CPU_INTEL_WESTMERE:
2788                         ev = westmereuc_event_table;
2789                         count = PMC_EVENT_TABLE_SIZE(westmereuc);
2790                         break;
2791                 }
2792                 break;
2793         case PMC_CLASS_TSC:
2794                 ev = tsc_event_table;
2795                 count = PMC_EVENT_TABLE_SIZE(tsc);
2796                 break;
2797         case PMC_CLASS_K7:
2798                 ev = k7_event_table;
2799                 count = PMC_EVENT_TABLE_SIZE(k7);
2800                 break;
2801         case PMC_CLASS_K8:
2802                 ev = k8_event_table;
2803                 count = PMC_EVENT_TABLE_SIZE(k8);
2804                 break;
2805         case PMC_CLASS_P4:
2806                 ev = p4_event_table;
2807                 count = PMC_EVENT_TABLE_SIZE(p4);
2808                 break;
2809         case PMC_CLASS_P5:
2810                 ev = p5_event_table;
2811                 count = PMC_EVENT_TABLE_SIZE(p5);
2812                 break;
2813         case PMC_CLASS_P6:
2814                 ev = p6_event_table;
2815                 count = PMC_EVENT_TABLE_SIZE(p6);
2816                 break;
2817         case PMC_CLASS_XSCALE:
2818                 ev = xscale_event_table;
2819                 count = PMC_EVENT_TABLE_SIZE(xscale);
2820                 break;
2821         case PMC_CLASS_MIPS24K:
2822                 ev = mips24k_event_table;
2823                 count = PMC_EVENT_TABLE_SIZE(mips24k);
2824                 break;
2825         case PMC_CLASS_OCTEON:
2826                 ev = octeon_event_table;
2827                 count = PMC_EVENT_TABLE_SIZE(octeon);
2828                 break;
2829         case PMC_CLASS_PPC7450:
2830                 ev = ppc7450_event_table;
2831                 count = PMC_EVENT_TABLE_SIZE(ppc7450);
2832                 break;
2833         case PMC_CLASS_SOFT:
2834                 ev = soft_event_table;
2835                 count = soft_event_info.pm_nevent;
2836                 break;
2837         default:
2838                 errno = EINVAL;
2839                 return (-1);
2840         }
2841
2842         if ((names = malloc(count * sizeof(const char *))) == NULL)
2843                 return (-1);
2844
2845         *eventnames = names;
2846         *nevents = count;
2847
2848         for (;count--; ev++, names++)
2849                 *names = ev->pm_ev_name;
2850
2851         return (0);
2852 }
2853
2854 int
2855 pmc_flush_logfile(void)
2856 {
2857         return (PMC_CALL(FLUSHLOG,0));
2858 }
2859
2860 int
2861 pmc_close_logfile(void)
2862 {
2863         return (PMC_CALL(CLOSELOG,0));
2864 }
2865
2866 int
2867 pmc_get_driver_stats(struct pmc_driverstats *ds)
2868 {
2869         struct pmc_op_getdriverstats gms;
2870
2871         if (PMC_CALL(GETDRIVERSTATS, &gms) < 0)
2872                 return (-1);
2873
2874         /* copy out fields in the current userland<->library interface */
2875         ds->pm_intr_ignored    = gms.pm_intr_ignored;
2876         ds->pm_intr_processed  = gms.pm_intr_processed;
2877         ds->pm_intr_bufferfull = gms.pm_intr_bufferfull;
2878         ds->pm_syscalls        = gms.pm_syscalls;
2879         ds->pm_syscall_errors  = gms.pm_syscall_errors;
2880         ds->pm_buffer_requests = gms.pm_buffer_requests;
2881         ds->pm_buffer_requests_failed = gms.pm_buffer_requests_failed;
2882         ds->pm_log_sweeps      = gms.pm_log_sweeps;
2883         return (0);
2884 }
2885
2886 int
2887 pmc_get_msr(pmc_id_t pmc, uint32_t *msr)
2888 {
2889         struct pmc_op_getmsr gm;
2890
2891         gm.pm_pmcid = pmc;
2892         if (PMC_CALL(PMCGETMSR, &gm) < 0)
2893                 return (-1);
2894         *msr = gm.pm_msr;
2895         return (0);
2896 }
2897
2898 int
2899 pmc_init(void)
2900 {
2901         int error, pmc_mod_id;
2902         unsigned int n;
2903         uint32_t abi_version;
2904         struct module_stat pmc_modstat;
2905         struct pmc_op_getcpuinfo op_cpu_info;
2906 #if defined(__amd64__) || defined(__i386__)
2907         int cpu_has_iaf_counters;
2908         unsigned int t;
2909 #endif
2910
2911         if (pmc_syscall != -1) /* already inited */
2912                 return (0);
2913
2914         /* retrieve the system call number from the KLD */
2915         if ((pmc_mod_id = modfind(PMC_MODULE_NAME)) < 0)
2916                 return (-1);
2917
2918         pmc_modstat.version = sizeof(struct module_stat);
2919         if ((error = modstat(pmc_mod_id, &pmc_modstat)) < 0)
2920                 return (-1);
2921
2922         pmc_syscall = pmc_modstat.data.intval;
2923
2924         /* check the kernel module's ABI against our compiled-in version */
2925         abi_version = PMC_VERSION;
2926         if (PMC_CALL(GETMODULEVERSION, &abi_version) < 0)
2927                 return (pmc_syscall = -1);
2928
2929         /* ignore patch & minor numbers for the comparision */
2930         if ((abi_version & 0xFF000000) != (PMC_VERSION & 0xFF000000)) {
2931                 errno  = EPROGMISMATCH;
2932                 return (pmc_syscall = -1);
2933         }
2934
2935         if (PMC_CALL(GETCPUINFO, &op_cpu_info) < 0)
2936                 return (pmc_syscall = -1);
2937
2938         cpu_info.pm_cputype = op_cpu_info.pm_cputype;
2939         cpu_info.pm_ncpu    = op_cpu_info.pm_ncpu;
2940         cpu_info.pm_npmc    = op_cpu_info.pm_npmc;
2941         cpu_info.pm_nclass  = op_cpu_info.pm_nclass;
2942         for (n = 0; n < cpu_info.pm_nclass; n++)
2943                 cpu_info.pm_classes[n] = op_cpu_info.pm_classes[n];
2944
2945         pmc_class_table = malloc(PMC_CLASS_TABLE_SIZE *
2946             sizeof(struct pmc_class_descr *));
2947
2948         if (pmc_class_table == NULL)
2949                 return (-1);
2950
2951         for (n = 0; n < PMC_CLASS_TABLE_SIZE; n++)
2952                 pmc_class_table[n] = NULL;
2953
2954         /*
2955          * Get soft events list.
2956          */
2957         soft_event_info.pm_class = PMC_CLASS_SOFT;
2958         if (PMC_CALL(GETDYNEVENTINFO, &soft_event_info) < 0)
2959                 return (pmc_syscall = -1);
2960
2961         /* Map soft events to static list. */
2962         for (n = 0; n < soft_event_info.pm_nevent; n++) {
2963                 soft_event_table[n].pm_ev_name =
2964                     soft_event_info.pm_events[n].pm_ev_name;
2965                 soft_event_table[n].pm_ev_code =
2966                     soft_event_info.pm_events[n].pm_ev_code;
2967         }
2968         soft_class_table_descr.pm_evc_event_table_size = \
2969             soft_event_info.pm_nevent;
2970         soft_class_table_descr.pm_evc_event_table = \
2971             soft_event_table;
2972
2973         /*
2974          * Fill in the class table.
2975          */
2976         n = 0;
2977
2978         /* Fill soft events information. */
2979         pmc_class_table[n++] = &soft_class_table_descr;
2980 #if defined(__amd64__) || defined(__i386__)
2981         if (cpu_info.pm_cputype != PMC_CPU_GENERIC)
2982                 pmc_class_table[n++] = &tsc_class_table_descr;
2983
2984         /*
2985          * Check if this CPU has fixed function counters.
2986          */
2987         cpu_has_iaf_counters = 0;
2988         for (t = 0; t < cpu_info.pm_nclass; t++)
2989                 if (cpu_info.pm_classes[t].pm_class == PMC_CLASS_IAF &&
2990                     cpu_info.pm_classes[t].pm_num > 0)
2991                         cpu_has_iaf_counters = 1;
2992 #endif
2993
2994 #define PMC_MDEP_INIT(C) do {                                   \
2995                 pmc_mdep_event_aliases    = C##_aliases;        \
2996                 pmc_mdep_class_list  = C##_pmc_classes;         \
2997                 pmc_mdep_class_list_size =                      \
2998                     PMC_TABLE_SIZE(C##_pmc_classes);            \
2999         } while (0)
3000
3001 #define PMC_MDEP_INIT_INTEL_V2(C) do {                                  \
3002                 PMC_MDEP_INIT(C);                                       \
3003                 pmc_class_table[n++] = &iaf_class_table_descr;          \
3004                 if (!cpu_has_iaf_counters)                              \
3005                         pmc_mdep_event_aliases =                        \
3006                                 C##_aliases_without_iaf;                \
3007                 pmc_class_table[n] = &C##_class_table_descr;            \
3008         } while (0)
3009
3010         /* Configure the event name parser. */
3011         switch (cpu_info.pm_cputype) {
3012 #if defined(__i386__)
3013         case PMC_CPU_AMD_K7:
3014                 PMC_MDEP_INIT(k7);
3015                 pmc_class_table[n] = &k7_class_table_descr;
3016                 break;
3017         case PMC_CPU_INTEL_P5:
3018                 PMC_MDEP_INIT(p5);
3019                 pmc_class_table[n]  = &p5_class_table_descr;
3020                 break;
3021         case PMC_CPU_INTEL_P6:          /* P6 ... Pentium M CPUs have */
3022         case PMC_CPU_INTEL_PII:         /* similar PMCs. */
3023         case PMC_CPU_INTEL_PIII:
3024         case PMC_CPU_INTEL_PM:
3025                 PMC_MDEP_INIT(p6);
3026                 pmc_class_table[n] = &p6_class_table_descr;
3027                 break;
3028 #endif
3029 #if defined(__amd64__) || defined(__i386__)
3030         case PMC_CPU_AMD_K8:
3031                 PMC_MDEP_INIT(k8);
3032                 pmc_class_table[n] = &k8_class_table_descr;
3033                 break;
3034         case PMC_CPU_INTEL_ATOM:
3035                 PMC_MDEP_INIT_INTEL_V2(atom);
3036                 break;
3037         case PMC_CPU_INTEL_CORE:
3038                 PMC_MDEP_INIT(core);
3039                 pmc_class_table[n] = &core_class_table_descr;
3040                 break;
3041         case PMC_CPU_INTEL_CORE2:
3042         case PMC_CPU_INTEL_CORE2EXTREME:
3043                 PMC_MDEP_INIT_INTEL_V2(core2);
3044                 break;
3045         case PMC_CPU_INTEL_COREI7:
3046                 pmc_class_table[n++] = &ucf_class_table_descr;
3047                 pmc_class_table[n++] = &corei7uc_class_table_descr;
3048                 PMC_MDEP_INIT_INTEL_V2(corei7);
3049                 break;
3050         case PMC_CPU_INTEL_HASWELL:
3051                 pmc_class_table[n++] = &ucf_class_table_descr;
3052                 pmc_class_table[n++] = &haswelluc_class_table_descr;
3053                 PMC_MDEP_INIT_INTEL_V2(haswell);
3054                 break;
3055         case PMC_CPU_INTEL_IVYBRIDGE:
3056                 PMC_MDEP_INIT_INTEL_V2(ivybridge);
3057                 break;
3058         case PMC_CPU_INTEL_IVYBRIDGE_XEON:
3059                 PMC_MDEP_INIT_INTEL_V2(ivybridge_xeon);
3060                 break;
3061         case PMC_CPU_INTEL_SANDYBRIDGE:
3062                 pmc_class_table[n++] = &ucf_class_table_descr;
3063                 pmc_class_table[n++] = &sandybridgeuc_class_table_descr;
3064                 PMC_MDEP_INIT_INTEL_V2(sandybridge);
3065                 break;
3066         case PMC_CPU_INTEL_SANDYBRIDGE_XEON:
3067                 PMC_MDEP_INIT_INTEL_V2(sandybridge_xeon);
3068                 break;
3069         case PMC_CPU_INTEL_WESTMERE:
3070                 pmc_class_table[n++] = &ucf_class_table_descr;
3071                 pmc_class_table[n++] = &westmereuc_class_table_descr;
3072                 PMC_MDEP_INIT_INTEL_V2(westmere);
3073                 break;
3074         case PMC_CPU_INTEL_PIV:
3075                 PMC_MDEP_INIT(p4);
3076                 pmc_class_table[n] = &p4_class_table_descr;
3077                 break;
3078 #endif
3079         case PMC_CPU_GENERIC:
3080                 PMC_MDEP_INIT(generic);
3081                 break;
3082 #if defined(__XSCALE__)
3083         case PMC_CPU_INTEL_XSCALE:
3084                 PMC_MDEP_INIT(xscale);
3085                 pmc_class_table[n] = &xscale_class_table_descr;
3086                 break;
3087 #endif
3088 #if defined(__mips__)
3089         case PMC_CPU_MIPS_24K:
3090                 PMC_MDEP_INIT(mips24k);
3091                 pmc_class_table[n] = &mips24k_class_table_descr;
3092                 break;
3093         case PMC_CPU_MIPS_OCTEON:
3094                 PMC_MDEP_INIT(octeon);
3095                 pmc_class_table[n] = &octeon_class_table_descr;
3096                 break;
3097 #endif /* __mips__ */
3098 #if defined(__powerpc__)
3099         case PMC_CPU_PPC_7450:
3100                 PMC_MDEP_INIT(ppc7450);
3101                 pmc_class_table[n] = &ppc7450_class_table_descr;
3102                 break;
3103 #endif
3104         default:
3105                 /*
3106                  * Some kind of CPU this version of the library knows nothing
3107                  * about.  This shouldn't happen since the abi version check
3108                  * should have caught this.
3109                  */
3110                 errno = ENXIO;
3111                 return (pmc_syscall = -1);
3112         }
3113
3114         return (0);
3115 }
3116
3117 const char *
3118 pmc_name_of_capability(enum pmc_caps cap)
3119 {
3120         int i;
3121
3122         /*
3123          * 'cap' should have a single bit set and should be in
3124          * range.
3125          */
3126         if ((cap & (cap - 1)) || cap < PMC_CAP_FIRST ||
3127             cap > PMC_CAP_LAST) {
3128                 errno = EINVAL;
3129                 return (NULL);
3130         }
3131
3132         i = ffs(cap);
3133         return (pmc_capability_names[i - 1]);
3134 }
3135
3136 const char *
3137 pmc_name_of_class(enum pmc_class pc)
3138 {
3139         if ((int) pc >= PMC_CLASS_FIRST &&
3140             pc <= PMC_CLASS_LAST)
3141                 return (pmc_class_names[pc]);
3142
3143         errno = EINVAL;
3144         return (NULL);
3145 }
3146
3147 const char *
3148 pmc_name_of_cputype(enum pmc_cputype cp)
3149 {
3150         size_t n;
3151
3152         for (n = 0; n < PMC_TABLE_SIZE(pmc_cputype_names); n++)
3153                 if (cp == pmc_cputype_names[n].pm_cputype)
3154                         return (pmc_cputype_names[n].pm_name);
3155
3156         errno = EINVAL;
3157         return (NULL);
3158 }
3159
3160 const char *
3161 pmc_name_of_disposition(enum pmc_disp pd)
3162 {
3163         if ((int) pd >= PMC_DISP_FIRST &&
3164             pd <= PMC_DISP_LAST)
3165                 return (pmc_disposition_names[pd]);
3166
3167         errno = EINVAL;
3168         return (NULL);
3169 }
3170
3171 const char *
3172 _pmc_name_of_event(enum pmc_event pe, enum pmc_cputype cpu)
3173 {
3174         const struct pmc_event_descr *ev, *evfence;
3175
3176         ev = evfence = NULL;
3177         if (pe >= PMC_EV_IAF_FIRST && pe <= PMC_EV_IAF_LAST) {
3178                 ev = iaf_event_table;
3179                 evfence = iaf_event_table + PMC_EVENT_TABLE_SIZE(iaf);
3180         } else if (pe >= PMC_EV_IAP_FIRST && pe <= PMC_EV_IAP_LAST) {
3181                 switch (cpu) {
3182                 case PMC_CPU_INTEL_ATOM:
3183                         ev = atom_event_table;
3184                         evfence = atom_event_table + PMC_EVENT_TABLE_SIZE(atom);
3185                         break;
3186                 case PMC_CPU_INTEL_CORE:
3187                         ev = core_event_table;
3188                         evfence = core_event_table + PMC_EVENT_TABLE_SIZE(core);
3189                         break;
3190                 case PMC_CPU_INTEL_CORE2:
3191                 case PMC_CPU_INTEL_CORE2EXTREME:
3192                         ev = core2_event_table;
3193                         evfence = core2_event_table + PMC_EVENT_TABLE_SIZE(core2);
3194                         break;
3195                 case PMC_CPU_INTEL_COREI7:
3196                         ev = corei7_event_table;
3197                         evfence = corei7_event_table + PMC_EVENT_TABLE_SIZE(corei7);
3198                         break;
3199                 case PMC_CPU_INTEL_HASWELL:
3200                         ev = haswell_event_table;
3201                         evfence = haswell_event_table + PMC_EVENT_TABLE_SIZE(haswell);
3202                         break;
3203                 case PMC_CPU_INTEL_IVYBRIDGE:
3204                         ev = ivybridge_event_table;
3205                         evfence = ivybridge_event_table + PMC_EVENT_TABLE_SIZE(ivybridge);
3206                         break;
3207                 case PMC_CPU_INTEL_IVYBRIDGE_XEON:
3208                         ev = ivybridge_xeon_event_table;
3209                         evfence = ivybridge_xeon_event_table + PMC_EVENT_TABLE_SIZE(ivybridge_xeon);
3210                         break;
3211                 case PMC_CPU_INTEL_SANDYBRIDGE:
3212                         ev = sandybridge_event_table;
3213                         evfence = sandybridge_event_table + PMC_EVENT_TABLE_SIZE(sandybridge);
3214                         break;
3215                 case PMC_CPU_INTEL_SANDYBRIDGE_XEON:
3216                         ev = sandybridge_xeon_event_table;
3217                         evfence = sandybridge_xeon_event_table + PMC_EVENT_TABLE_SIZE(sandybridge_xeon);
3218                         break;
3219                 case PMC_CPU_INTEL_WESTMERE:
3220                         ev = westmere_event_table;
3221                         evfence = westmere_event_table + PMC_EVENT_TABLE_SIZE(westmere);
3222                         break;
3223                 default:        /* Unknown CPU type. */
3224                         break;
3225                 }
3226         } else if (pe >= PMC_EV_UCF_FIRST && pe <= PMC_EV_UCF_LAST) {
3227                 ev = ucf_event_table;
3228                 evfence = ucf_event_table + PMC_EVENT_TABLE_SIZE(ucf);
3229         } else if (pe >= PMC_EV_UCP_FIRST && pe <= PMC_EV_UCP_LAST) {
3230                 switch (cpu) {
3231                 case PMC_CPU_INTEL_COREI7:
3232                         ev = corei7uc_event_table;
3233                         evfence = corei7uc_event_table + PMC_EVENT_TABLE_SIZE(corei7uc);
3234                         break;
3235                 case PMC_CPU_INTEL_SANDYBRIDGE:
3236                         ev = sandybridgeuc_event_table;
3237                         evfence = sandybridgeuc_event_table + PMC_EVENT_TABLE_SIZE(sandybridgeuc);
3238                         break;
3239                 case PMC_CPU_INTEL_WESTMERE:
3240                         ev = westmereuc_event_table;
3241                         evfence = westmereuc_event_table + PMC_EVENT_TABLE_SIZE(westmereuc);
3242                         break;
3243                 default:        /* Unknown CPU type. */
3244                         break;
3245                 }
3246         } else if (pe >= PMC_EV_K7_FIRST && pe <= PMC_EV_K7_LAST) {
3247                 ev = k7_event_table;
3248                 evfence = k7_event_table + PMC_EVENT_TABLE_SIZE(k7);
3249         } else if (pe >= PMC_EV_K8_FIRST && pe <= PMC_EV_K8_LAST) {
3250                 ev = k8_event_table;
3251                 evfence = k8_event_table + PMC_EVENT_TABLE_SIZE(k8);
3252         } else if (pe >= PMC_EV_P4_FIRST && pe <= PMC_EV_P4_LAST) {
3253                 ev = p4_event_table;
3254                 evfence = p4_event_table + PMC_EVENT_TABLE_SIZE(p4);
3255         } else if (pe >= PMC_EV_P5_FIRST && pe <= PMC_EV_P5_LAST) {
3256                 ev = p5_event_table;
3257                 evfence = p5_event_table + PMC_EVENT_TABLE_SIZE(p5);
3258         } else if (pe >= PMC_EV_P6_FIRST && pe <= PMC_EV_P6_LAST) {
3259                 ev = p6_event_table;
3260                 evfence = p6_event_table + PMC_EVENT_TABLE_SIZE(p6);
3261         } else if (pe >= PMC_EV_XSCALE_FIRST && pe <= PMC_EV_XSCALE_LAST) {
3262                 ev = xscale_event_table;
3263                 evfence = xscale_event_table + PMC_EVENT_TABLE_SIZE(xscale);
3264         } else if (pe >= PMC_EV_MIPS24K_FIRST && pe <= PMC_EV_MIPS24K_LAST) {
3265                 ev = mips24k_event_table;
3266                 evfence = mips24k_event_table + PMC_EVENT_TABLE_SIZE(mips24k);
3267         } else if (pe >= PMC_EV_OCTEON_FIRST && pe <= PMC_EV_OCTEON_LAST) {
3268                 ev = octeon_event_table;
3269                 evfence = octeon_event_table + PMC_EVENT_TABLE_SIZE(octeon);
3270         } else if (pe >= PMC_EV_PPC7450_FIRST && pe <= PMC_EV_PPC7450_LAST) {
3271                 ev = ppc7450_event_table;
3272                 evfence = ppc7450_event_table + PMC_EVENT_TABLE_SIZE(ppc7450);
3273         } else if (pe == PMC_EV_TSC_TSC) {
3274                 ev = tsc_event_table;
3275                 evfence = tsc_event_table + PMC_EVENT_TABLE_SIZE(tsc);
3276         } else if ((int)pe >= PMC_EV_SOFT_FIRST && (int)pe <= PMC_EV_SOFT_LAST) {
3277                 ev = soft_event_table;
3278                 evfence = soft_event_table + soft_event_info.pm_nevent;
3279         }
3280
3281         for (; ev != evfence; ev++)
3282                 if (pe == ev->pm_ev_code)
3283                         return (ev->pm_ev_name);
3284
3285         return (NULL);
3286 }
3287
3288 const char *
3289 pmc_name_of_event(enum pmc_event pe)
3290 {
3291         const char *n;
3292
3293         if ((n = _pmc_name_of_event(pe, cpu_info.pm_cputype)) != NULL)
3294                 return (n);
3295
3296         errno = EINVAL;
3297         return (NULL);
3298 }
3299
3300 const char *
3301 pmc_name_of_mode(enum pmc_mode pm)
3302 {
3303         if ((int) pm >= PMC_MODE_FIRST &&
3304             pm <= PMC_MODE_LAST)
3305                 return (pmc_mode_names[pm]);
3306
3307         errno = EINVAL;
3308         return (NULL);
3309 }
3310
3311 const char *
3312 pmc_name_of_state(enum pmc_state ps)
3313 {
3314         if ((int) ps >= PMC_STATE_FIRST &&
3315             ps <= PMC_STATE_LAST)
3316                 return (pmc_state_names[ps]);
3317
3318         errno = EINVAL;
3319         return (NULL);
3320 }
3321
3322 int
3323 pmc_ncpu(void)
3324 {
3325         if (pmc_syscall == -1) {
3326                 errno = ENXIO;
3327                 return (-1);
3328         }
3329
3330         return (cpu_info.pm_ncpu);
3331 }
3332
3333 int
3334 pmc_npmc(int cpu)
3335 {
3336         if (pmc_syscall == -1) {
3337                 errno = ENXIO;
3338                 return (-1);
3339         }
3340
3341         if (cpu < 0 || cpu >= (int) cpu_info.pm_ncpu) {
3342                 errno = EINVAL;
3343                 return (-1);
3344         }
3345
3346         return (cpu_info.pm_npmc);
3347 }
3348
3349 int
3350 pmc_pmcinfo(int cpu, struct pmc_pmcinfo **ppmci)
3351 {
3352         int nbytes, npmc;
3353         struct pmc_op_getpmcinfo *pmci;
3354
3355         if ((npmc = pmc_npmc(cpu)) < 0)
3356                 return (-1);
3357
3358         nbytes = sizeof(struct pmc_op_getpmcinfo) +
3359             npmc * sizeof(struct pmc_info);
3360
3361         if ((pmci = calloc(1, nbytes)) == NULL)
3362                 return (-1);
3363
3364         pmci->pm_cpu  = cpu;
3365
3366         if (PMC_CALL(GETPMCINFO, pmci) < 0) {
3367                 free(pmci);
3368                 return (-1);
3369         }
3370
3371         /* kernel<->library, library<->userland interfaces are identical */
3372         *ppmci = (struct pmc_pmcinfo *) pmci;
3373         return (0);
3374 }
3375
3376 int
3377 pmc_read(pmc_id_t pmc, pmc_value_t *value)
3378 {
3379         struct pmc_op_pmcrw pmc_read_op;
3380
3381         pmc_read_op.pm_pmcid = pmc;
3382         pmc_read_op.pm_flags = PMC_F_OLDVALUE;
3383         pmc_read_op.pm_value = -1;
3384
3385         if (PMC_CALL(PMCRW, &pmc_read_op) < 0)
3386                 return (-1);
3387
3388         *value = pmc_read_op.pm_value;
3389         return (0);
3390 }
3391
3392 int
3393 pmc_release(pmc_id_t pmc)
3394 {
3395         struct pmc_op_simple    pmc_release_args;
3396
3397         pmc_release_args.pm_pmcid = pmc;
3398         return (PMC_CALL(PMCRELEASE, &pmc_release_args));
3399 }
3400
3401 int
3402 pmc_rw(pmc_id_t pmc, pmc_value_t newvalue, pmc_value_t *oldvaluep)
3403 {
3404         struct pmc_op_pmcrw pmc_rw_op;
3405
3406         pmc_rw_op.pm_pmcid = pmc;
3407         pmc_rw_op.pm_flags = PMC_F_NEWVALUE | PMC_F_OLDVALUE;
3408         pmc_rw_op.pm_value = newvalue;
3409
3410         if (PMC_CALL(PMCRW, &pmc_rw_op) < 0)
3411                 return (-1);
3412
3413         *oldvaluep = pmc_rw_op.pm_value;
3414         return (0);
3415 }
3416
3417 int
3418 pmc_set(pmc_id_t pmc, pmc_value_t value)
3419 {
3420         struct pmc_op_pmcsetcount sc;
3421
3422         sc.pm_pmcid = pmc;
3423         sc.pm_count = value;
3424
3425         if (PMC_CALL(PMCSETCOUNT, &sc) < 0)
3426                 return (-1);
3427         return (0);
3428 }
3429
3430 int
3431 pmc_start(pmc_id_t pmc)
3432 {
3433         struct pmc_op_simple    pmc_start_args;
3434
3435         pmc_start_args.pm_pmcid = pmc;
3436         return (PMC_CALL(PMCSTART, &pmc_start_args));
3437 }
3438
3439 int
3440 pmc_stop(pmc_id_t pmc)
3441 {
3442         struct pmc_op_simple    pmc_stop_args;
3443
3444         pmc_stop_args.pm_pmcid = pmc;
3445         return (PMC_CALL(PMCSTOP, &pmc_stop_args));
3446 }
3447
3448 int
3449 pmc_width(pmc_id_t pmcid, uint32_t *width)
3450 {
3451         unsigned int i;
3452         enum pmc_class cl;
3453
3454         cl = PMC_ID_TO_CLASS(pmcid);
3455         for (i = 0; i < cpu_info.pm_nclass; i++)
3456                 if (cpu_info.pm_classes[i].pm_class == cl) {
3457                         *width = cpu_info.pm_classes[i].pm_width;
3458                         return (0);
3459                 }
3460         errno = EINVAL;
3461         return (-1);
3462 }
3463
3464 int
3465 pmc_write(pmc_id_t pmc, pmc_value_t value)
3466 {
3467         struct pmc_op_pmcrw pmc_write_op;
3468
3469         pmc_write_op.pm_pmcid = pmc;
3470         pmc_write_op.pm_flags = PMC_F_NEWVALUE;
3471         pmc_write_op.pm_value = value;
3472         return (PMC_CALL(PMCRW, &pmc_write_op));
3473 }
3474
3475 int
3476 pmc_writelog(uint32_t userdata)
3477 {
3478         struct pmc_op_writelog wl;
3479
3480         wl.pm_userdata = userdata;
3481         return (PMC_CALL(WRITELOG, &wl));
3482 }