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31 .Nd measurement events for
33 Pentium Pro, P-II, P-III family CPUs
39 Intel P6 PMCs are present in Intel
48 They are documented in
50 .%B "IA-32 Intel(R) Architecture Software Developer's Manual"
51 .%T "Volume 3: System Programming Guide"
52 .%N "Order Number 245472-012"
54 .%Q "Intel Corporation"
57 Some of these events are affected by processor errata described in
59 .%B "Intel(R) Pentium(R) III Processor Specification Update"
60 .%N "Document Number: 244453-054"
62 .%Q "Intel Corporation"
65 These CPUs have two counters, each 40 bits wide.
66 Some events may only be used on specific counters and some events are
67 defined only on specific processor models.
68 These PMCs support the following capabilities:
69 .Bl -column "PMC_CAP_INTERRUPT" "Support"
70 .It Em Capability Ta Em Support
71 .It PMC_CAP_CASCADE Ta \&No
72 .It PMC_CAP_EDGE Ta Yes
73 .It PMC_CAP_INTERRUPT Ta Yes
74 .It PMC_CAP_INVERT Ta Yes
75 .It PMC_CAP_READ Ta Yes
76 .It PMC_CAP_PRECISE Ta \&No
77 .It PMC_CAP_SYSTEM Ta Yes
78 .It PMC_CAP_TAGGING Ta \&No
79 .It PMC_CAP_THRESHOLD Ta Yes
80 .It PMC_CAP_USER Ta Yes
81 .It PMC_CAP_WRITE Ta Yes
84 Event specifiers for Intel P6 PMCs can have the following common
86 .Bl -tag -width indent
87 .It Li cmask= Ns Ar value
88 Configure the PMC to increment only if the number of configured
89 events measured in a cycle is greater than or equal to
92 Configure the PMC to count the number of de-asserted to asserted
93 transitions of the conditions expressed by the other qualifiers.
94 If specified, the counter will increment only once whenever a
95 condition becomes true, irrespective of the number of clocks during
96 which the condition remains true.
98 Invert the sense of comparison when the
100 qualifier is present, making the counter increment when the number of
101 events per cycle is less than the value specified by the
105 Configure the PMC to count events happening at processor privilege
107 .It Li umask= Ns Ar value
108 This qualifier is used to further qualify the event selected (see
111 Configure the PMC to count events occurring at privilege levels 1, 2
119 qualifiers are specified, the default is to enable both.
121 The event specifiers supported by Intel P6 PMCs are:
122 .Bl -tag -width indent
125 Count the number of times a static branch prediction was made by the
126 branch decoder because the BTB did not have a prediction.
127 .It Li p6-br-bac-missp-exec
128 .Pq Event 8AH , Tn "Pentium M"
129 Count the number of branch instructions executed that where
130 mispredicted at the Front End (BAC).
133 Count the number of bogus branches.
134 .It Li p6-br-call-exec
135 .Pq Event 92H , Tn "Pentium M"
136 Count the number of call instructions executed.
137 .It Li p6-br-call-missp-exec
138 .Pq Event 93H , Tn "Pentium M"
139 Count the number of call instructions executed that were mispredicted.
140 .It Li p6-br-cnd-exec
141 .Pq Event 8BH , Tn "Pentium M"
142 Count the number of conditional branch instructions executed.
143 .It Li p6-br-cnd-missp-exec
144 .Pq Event 8CH , Tn "Pentium M"
145 Count the number of conditional branch instructions executed that were
147 .It Li p6-br-ind-call-exec
148 .Pq Event 94H , Tn "Pentium M"
149 Count the number of indirect call instructions executed.
150 .It Li p6-br-ind-exec
151 .Pq Event 8DH , Tn "Pentium M"
152 Count the number of indirect branch instructions executed.
153 .It Li p6-br-ind-missp-exec
154 .Pq Event 8EH , Tn "Pentium M"
155 Count the number of indirect branch instructions executed that were
157 .It Li p6-br-inst-decoded
159 Count the number of branch instructions decoded.
160 .It Li p6-br-inst-exec
161 .Pq Event 88H , Tn "Pentium M"
162 Count the number of branch instructions executed but necessarily retired.
163 .It Li p6-br-inst-retired
165 Count the number of branch instructions retired.
166 .It Li p6-br-miss-pred-retired
168 Count the number of mispredicted branch instructions retired.
169 .It Li p6-br-miss-pred-taken-ret
171 Count the number of taken mispredicted branches retired.
172 .It Li p6-br-missp-exec
173 .Pq Event 89H , Tn "Pentium M"
174 Count the number of branch instructions executed that were
175 mispredicted at execution.
176 .It Li p6-br-ret-bac-missp-exec
177 .Pq Event 91H , Tn "Pentium M"
178 Count the number of return instructions executed that were
179 mispredicted at the Front End (BAC).
180 .It Li p6-br-ret-exec
181 .Pq Event 8FH , Tn "Pentium M"
182 Count the number of return instructions executed.
183 .It Li p6-br-ret-missp-exec
184 .Pq Event 90H , Tn "Pentium M"
185 Count the number of return instructions executed that were
186 mispredicted at execution.
187 .It Li p6-br-taken-retired
189 Count the number of taken branches retired.
192 Count the number of branches for which the BTB did not produce a
194 .It Li p6-bus-bnr-drv
196 Count the number of bus clock cycles during which this processor is
197 driving the BNR# pin.
198 .It Li p6-bus-data-rcv
200 Count the number of bus clock cycles during which this processor is
202 .It Li p6-bus-drdy-clocks Op Li ,umask= Ns Ar qualifier
204 Count the number of clocks during which DRDY# is asserted.
205 An additional qualifier may be specified, and comprises one of the
208 .Bl -tag -width indent -compact
210 Count transactions generated by any agent on the bus.
212 Count transactions generated by this processor.
215 The default is to count operations generated by this processor.
216 .It Li p6-bus-hit-drv
218 Count the number of bus clock cycles during which this processor is
219 driving the HIT# pin.
220 .It Li p6-bus-hitm-drv
222 Count the number of bus clock cycles during which this processor is
223 driving the HITM# pin.
224 .It Li p6-bus-lock-clocks Op Li ,umask= Ns Ar qualifier
226 Count the number of clocks during with LOCK# is asserted on the
228 An additional qualifier may be specified and comprises one of the following
231 .Bl -tag -width indent -compact
233 Count transactions generated by any agent on the bus.
235 Count transactions generated by this processor.
238 The default is to count operations generated by this processor.
239 .It Li p6-bus-req-outstanding
241 Count the number of bus requests outstanding in any given cycle.
242 .It Li p6-bus-snoop-stall
244 Count the number of clock cycles during which the bus is snoop stalled.
245 .It Li p6-bus-tran-any Op Li ,umask= Ns Ar qualifier
247 Count the number of completed bus transactions of any kind.
248 An additional qualifier may be specified and comprises one of the following
251 .Bl -tag -width indent -compact
253 Count transactions generated by any agent on the bus.
255 Count transactions generated by this processor.
258 The default is to count operations generated by this processor.
259 .It Li p6-bus-tran-brd Op Li ,umask= Ns Ar qualifier
261 Count the number of burst read transactions.
262 An additional qualifier may be specified and comprises one of the following
265 .Bl -tag -width indent -compact
267 Count transactions generated by any agent on the bus.
269 Count transactions generated by this processor.
272 The default is to count operations generated by this processor.
273 .It Li p6-bus-tran-burst Op Li ,umask= Ns Ar qualifier
275 Count the number of completed burst transactions.
276 An additional qualifier may be specified and comprises one of the following
279 .Bl -tag -width indent -compact
281 Count transactions generated by any agent on the bus.
283 Count transactions generated by this processor.
286 The default is to count operations generated by this processor.
287 .It Li p6-bus-tran-def Op Li ,umask= Ns Ar qualifier
289 Count the number of completed deferred transactions.
290 An additional qualifier may be specified and comprises one of the following
293 .Bl -tag -width indent -compact
295 Count transactions generated by any agent on the bus.
297 Count transactions generated by this processor.
300 The default is to count operations generated by this processor.
301 .It Li p6-bus-tran-ifetch Op Li ,umask= Ns Ar qualifier
303 Count the number of completed instruction fetch transactions.
304 An additional qualifier may be specified and comprises one of the following
307 .Bl -tag -width indent -compact
309 Count transactions generated by any agent on the bus.
311 Count transactions generated by this processor.
314 The default is to count operations generated by this processor.
315 .It Li p6-bus-tran-inval Op Li ,umask= Ns Ar qualifier
317 Count the number of completed invalidate transactions.
318 An additional qualifier may be specified and comprises one of the following
321 .Bl -tag -width indent -compact
323 Count transactions generated by any agent on the bus.
325 Count transactions generated by this processor.
328 The default is to count operations generated by this processor.
329 .It Li p6-bus-tran-mem Op Li ,umask= Ns Ar qualifier
331 Count the number of completed memory transactions.
332 An additional qualifier may be specified and comprises one of the following
335 .Bl -tag -width indent -compact
337 Count transactions generated by any agent on the bus.
339 Count transactions generated by this processor.
342 The default is to count operations generated by this processor.
343 .It Li p6-bus-tran-pwr Op Li ,umask= Ns Ar qualifier
345 Count the number of completed partial write transactions.
346 An additional qualifier may be specified and comprises one of the following
349 .Bl -tag -width indent -compact
351 Count transactions generated by any agent on the bus.
353 Count transactions generated by this processor.
356 The default is to count operations generated by this processor.
357 .It Li p6-bus-tran-rfo Op Li ,umask= Ns Ar qualifier
359 Count the number of completed read-for-ownership transactions.
360 An additional qualifier may be specified and comprises one of the following
363 .Bl -tag -width indent -compact
365 Count transactions generated by any agent on the bus.
367 Count transactions generated by this processor.
370 The default is to count operations generated by this processor.
371 .It Li p6-bus-trans-io Op Li ,umask= Ns Ar qualifier
373 Count the number of completed I/O transactions.
374 An additional qualifier may be specified and comprises one of the following
377 .Bl -tag -width indent -compact
379 Count transactions generated by any agent on the bus.
381 Count transactions generated by this processor.
384 The default is to count operations generated by this processor.
385 .It Li p6-bus-trans-p Op Li ,umask= Ns Ar qualifier
387 Count the number of completed partial transactions.
388 An additional qualifier may be specified and comprises one of the following
391 .Bl -tag -width indent -compact
393 Count transactions generated by any agent on the bus.
395 Count transactions generated by this processor.
398 The default is to count operations generated by this processor.
399 .It Li p6-bus-trans-wb Op Li ,umask= Ns Ar qualifier
401 Count the number of completed write-back transactions.
402 An additional qualifier may be specified and comprises one of the following
405 .Bl -tag -width indent -compact
407 Count transactions generated by any agent on the bus.
409 Count transactions generated by this processor.
412 The default is to count operations generated by this processor.
413 .It Li p6-cpu-clk-unhalted
415 Count the number of cycles during with the processor was not halted.
418 Count the number of cycles during with the processor was not halted
419 and not in a thermal trip.
420 .It Li p6-cycles-div-busy
422 Count the number of cycles during which the divider is busy and cannot
424 This event is only allocated on counter 0.
425 .It Li p6-cycles-int-pending-and-masked
427 Count the number of processor cycles for which interrupts were
428 disabled and interrupts were pending.
429 .It Li p6-cycles-int-masked
431 Count the number of processor cycles for which interrupts were
433 .It Li p6-data-mem-refs
435 Count all loads and all stores using any memory type, including
437 Each part of a split store is counted separately.
438 .It Li p6-dcu-lines-in
440 Count the total lines allocated in the data cache unit.
441 .It Li p6-dcu-m-lines-in
443 Count the number of M state lines allocated in the data cache unit.
444 .It Li p6-dcu-m-lines-out
446 Count the number of M state lines evicted from the data cache unit.
447 .It Li p6-dcu-miss-outstanding
449 Count the weighted number of cycles while a data cache unit miss is
450 outstanding, incremented by the number of outstanding cache misses at
454 Count the number of integer and floating-point divides including
456 This event is only allocated on counter 1.
457 .It Li p6-emon-esp-uops
458 .Pq Event D7H , Tn "Pentium M"
459 Count the total number of micro-ops.
460 .It Li p6-emon-est-trans Op Li ,umask= Ns Ar qualifier
461 .Pq Event 58H , Tn "Pentium M"
463 .Tn "Enhanced Intel SpeedStep"
465 An additional qualifier may be specified, and can be one of the
468 .Bl -tag -width indent -compact
470 Count all transitions.
472 Count only frequency transitions.
475 The default is to count all transitions.
476 .It Li p6-emon-fused-uops-ret Op Li ,umask= Ns Ar qualifier
477 .Pq Event DAH , Tn "Pentium M"
478 Count the number of retired fused micro-ops.
479 An additional qualifier may be specified, and may be one of the
482 .Bl -tag -width indent -compact
484 Count all fused micro-ops.
486 Count only load and op micro-ops.
488 Count only STD/STA micro-ops.
491 The default is to count all fused micro-ops.
492 .It Li p6-emon-kni-comp-inst-ret
493 .Pq Event D9H , Tn "Pentium III"
494 Count the number of SSE computational instructions retired.
495 An additional qualifier may be specified, and comprises one of the
498 .Bl -tag -width indent -compact
499 .It Li packed-and-scalar
500 Count packed and scalar operations.
502 Count scalar operations only.
505 The default is to count packed and scalar operations.
506 .It Li p6-emon-kni-inst-retired Op Li ,umask= Ns Ar qualifier
507 .Pq Event D8H , Tn "Pentium III"
508 Count the number of SSE instructions retired.
509 An additional qualifier may be specified, and comprises one of the
512 .Bl -tag -width indent -compact
513 .It Li packed-and-scalar
514 Count packed and scalar operations.
516 Count scalar operations only.
519 The default is to count packed and scalar operations.
520 .It Li p6-emon-kni-pref-dispatched Op Li ,umask= Ns Ar qualifier
521 .Pq Event 07H , Tn "Pentium III"
522 Count the number of SSE prefetch or weakly ordered instructions
523 dispatched (including speculative prefetches).
524 An additional qualifier may be specified, and comprises one of the
527 .Bl -tag -width indent -compact
529 Count non-temporal prefetches.
531 Count prefetches to L1.
533 Count prefetches to L2.
535 Count weakly ordered stores.
538 The default is to count non-temporal prefetches.
539 .It Li p6-emon-kni-pref-miss Op Li ,umask= Ns Ar qualifier
540 .Pq Event 4BH , Tn "Pentium III"
541 Count the number of prefetch or weakly ordered instructions that miss
543 An additional qualifier may be specified, and comprises one of the
546 .Bl -tag -width indent -compact
548 Count non-temporal prefetches.
550 Count prefetches to L1.
552 Count prefetches to L2.
554 Count weakly ordered stores.
557 The default is to count non-temporal prefetches.
558 .It Li p6-emon-pref-rqsts-dn
559 .Pq Event F8H , Tn "Pentium M"
560 Count the number of downward prefetches issued.
561 .It Li p6-emon-pref-rqsts-up
562 .Pq Event F0H , Tn "Pentium M"
563 Count the number of upward prefetches issued.
564 .It Li p6-emon-simd-instr-retired
565 .Pq Event CEH , Tn "Pentium M"
566 Count the number of retired
569 .It Li p6-emon-sse-sse2-comp-inst-retired Op Li ,umask= Ns Ar qualifier
570 .Pq Event D9H , Tn "Pentium M"
571 Count the number of computational SSE instructions retired.
572 An additional qualifier may be specified and can be one of the
575 .Bl -tag -width indent -compact
576 .It Li sse-packed-single
577 Count SSE packed-single instructions.
578 .It Li sse-scalar-single
579 Count SSE scalar-single instructions.
580 .It Li sse2-packed-double
581 Count SSE2 packed-double instructions.
582 .It Li sse2-scalar-double
583 Count SSE2 scalar-double instructions.
586 The default is to count SSE packed-single instructions.
587 .It Li p6-emon-sse-sse2-inst-retired Op Li ,umask= Ns Ar qualifier
588 .Pq Event D8H , Tn "Pentium M"
589 Count the number of SSE instructions retired.
590 An additional qualifier can be specified, and can be one of the
593 .Bl -tag -width indent -compact
594 .It Li sse-packed-single
595 Count SSE packed-single instructions.
596 .It Li sse-packed-single-scalar-single
597 Count SSE packed-single and scalar-single instructions.
598 .It Li sse2-packed-double
599 Count SSE2 packed-double instructions.
600 .It Li sse2-scalar-double
601 Count SSE2 scalar-double instructions.
604 The default is to count SSE packed-single instructions.
605 .It Li p6-emon-synch-uops
606 .Pq Event D3H , Tn "Pentium M"
607 Count the number of sync micro-ops.
608 .It Li p6-emon-thermal-trip
609 .Pq Event 59H , Tn "Pentium M"
610 Count the duration or occurrences of thermal trips.
613 qualifier to count occurrences of thermal trips.
614 .It Li p6-emon-unfusion
615 .Pq Event DBH , Tn "Pentium M"
616 Count the number of unfusion events in the reorder buffer.
619 Count the number of computational floating point operations retired.
620 This event is only allocated on counter 0.
623 Count the number of floating point exceptions handled by microcode.
624 This event is only allocated on counter 1.
625 .It Li p6-fp-comps-ops-exe
627 Count the number of computation floating point operations executed.
628 This event is only allocated on counter 0.
629 .It Li p6-fp-mmx-trans Op Li ,umask= Ns Ar qualifier
630 .Pq Event CCH , Tn "Pentium II" , Tn "Pentium III"
631 Count the number of transitions between MMX and floating-point
633 An additional qualifier may be specified, and comprises one of the
636 .Bl -tag -width indent -compact
638 Count transitions from MMX instructions to floating-point instructions.
640 Count transitions from floating-point instructions to MMX instructions.
643 The default is to count MMX to floating-point transitions.
646 Count the number of hardware interrupts received.
649 Count the number of instruction fetches, both cacheable and non-cacheable.
650 .It Li p6-ifu-ifetch-miss
652 Count the number of instruction fetch misses (i.e., those that produce
654 .It Li p6-ifu-mem-stall
656 Count the number of cycles instruction fetch is stalled for any reason.
659 Count the number of cycles the instruction length decoder is stalled.
660 .It Li p6-inst-decoded
662 Count the number of instructions decoded.
663 .It Li p6-inst-retired
665 Count the number of instructions retired.
668 Count the number of instruction TLB misses.
671 Count the number of L2 address strobes.
672 .It Li p6-l2-dbus-busy
674 Count the number of cycles during which the L2 cache data bus was busy.
675 .It Li p6-l2-dbus-busy-rd
677 Count the number of cycles during which the L2 cache data bus was busy
678 transferring read data from L2 to the processor.
679 .It Li p6-l2-ifetch Op Li ,umask= Ns Ar qualifier
681 Count the number of L2 instruction fetches.
682 An additional qualifier may be specified and comprises a list of the following
683 keywords separated by
687 .Bl -tag -width indent -compact
689 Count operations affecting E (exclusive) state lines.
691 Count operations affecting I (invalid) state lines.
693 Count operations affecting M (modified) state lines.
695 Count operations affecting S (shared) state lines.
698 The default is to count operations affecting all (MESI) state lines.
699 .It Li p6-l2-ld Op Li ,umask= Ns Ar qualifier
701 Count the number of L2 data loads.
702 An additional qualifier may be specified and comprises a list of the following
703 keywords separated by
707 .Bl -tag -width indent -compact
710 Count both hardware-prefetched lines and non-hardware-prefetched lines.
712 Count operations affecting E (exclusive) state lines.
715 Count hardware-prefetched lines only.
717 Count operations affecting I (invalid) state lines.
719 Count operations affecting M (modified) state lines.
722 Exclude hardware-prefetched lines.
724 Count operations affecting S (shared) state lines.
727 The default on processors other than
729 processors is to count operations affecting all (MESI) state lines.
732 processors is to count both hardware-prefetched and
733 non-hardware-prefetch operations on all (MESI) state lines.
735 This event is affected by processor errata E53.
736 .It Li p6-l2-lines-in Op Li ,umask= Ns Ar qualifier
738 Count the number of L2 lines allocated.
739 An additional qualifier may be specified and comprises a list of the following
740 keywords separated by
744 .Bl -tag -width indent -compact
747 Count both hardware-prefetched lines and non-hardware-prefetched lines.
749 Count operations affecting E (exclusive) state lines.
752 Count hardware-prefetched lines only.
754 Count operations affecting I (invalid) state lines.
756 Count operations affecting M (modified) state lines.
759 Exclude hardware-prefetched lines.
761 Count operations affecting S (shared) state lines.
764 The default on processors other than
766 processors is to count operations affecting all (MESI) state lines.
769 processors is to count both hardware-prefetched and
770 non-hardware-prefetch operations on all (MESI) state lines.
772 This event is affected by processor errata E45.
773 .It Li p6-l2-lines-out Op Li ,umask= Ns Ar qualifier
775 Count the number of L2 lines evicted.
776 An additional qualifier may be specified and comprises a list of the following
777 keywords separated by
781 .Bl -tag -width indent -compact
784 Count both hardware-prefetched lines and non-hardware-prefetched lines.
786 Count operations affecting E (exclusive) state lines.
789 Count hardware-prefetched lines only.
791 Count operations affecting I (invalid) state lines.
793 Count operations affecting M (modified) state lines.
795 .Pq Tn "Pentium M" only
796 Exclude hardware-prefetched lines.
798 Count operations affecting S (shared) state lines.
801 The default on processors other than
803 processors is to count operations affecting all (MESI) state lines.
806 processors is to count both hardware-prefetched and
807 non-hardware-prefetch operations on all (MESI) state lines.
809 This event is affected by processor errata E45.
810 .It Li p6-l2-m-lines-inm
812 Count the number of modified lines allocated in L2 cache.
813 .It Li p6-l2-m-lines-outm Op Li ,umask= Ns Ar qualifier
815 Count the number of L2 M-state lines evicted.
818 On these processors an additional qualifier may be specified and
819 comprises a list of the following keywords separated by
823 .Bl -tag -width indent -compact
825 Count both hardware-prefetched lines and non-hardware-prefetched lines.
827 Count hardware-prefetched lines only.
829 Exclude hardware-prefetched lines.
832 The default is to count both hardware-prefetched and
833 non-hardware-prefetch operations.
835 This event is affected by processor errata E53.
836 .It Li p6-l2-rqsts Op Li ,umask= Ns Ar qualifier
838 Count the total number of L2 requests.
839 An additional qualifier may be specified and comprises a list of the following
840 keywords separated by
844 .Bl -tag -width indent -compact
846 Count operations affecting E (exclusive) state lines.
848 Count operations affecting I (invalid) state lines.
850 Count operations affecting M (modified) state lines.
852 Count operations affecting S (shared) state lines.
855 The default is to count operations affecting all (MESI) state lines.
858 Count the number of L2 data stores.
859 An additional qualifier may be specified and comprises a list of the following
860 keywords separated by
864 .Bl -tag -width indent -compact
866 Count operations affecting E (exclusive) state lines.
868 Count operations affecting I (invalid) state lines.
870 Count operations affecting M (modified) state lines.
872 Count operations affecting S (shared) state lines.
875 The default is to count operations affecting all (MESI) state lines.
878 Count the number of load operations delayed due to store buffer blocks.
879 .It Li p6-misalign-mem-ref
881 Count the number of misaligned data memory references (crossing a 64
884 .Pq Event CDH , Tn "Pentium II" , Tn "Pentium III"
885 Count the number of MMX assists executed.
886 .It Li p6-mmx-instr-exec
888 .Pq Tn Celeron , Tn "Pentium II"
889 Count the number of MMX instructions executed, except MOVQ and MOVD
890 stores from register to memory.
891 .It Li p6-mmx-instr-ret
892 .Pq Event CEH , Tn "Pentium II"
893 Count the number of MMX instructions retired.
894 .It Li p6-mmx-instr-type-exec Op Li ,umask= Ns Ar qualifier
895 .Pq Event B3H , Tn "Pentium II" , Tn "Pentium III"
896 Count the number of MMX instructions executed.
897 An additional qualifier may be specified and comprises a list of
898 the following keywords separated by
902 .Bl -tag -width indent -compact
904 Count MMX pack operation instructions.
905 .It Li packed-arithmetic
906 Count MMX packed arithmetic instructions.
907 .It Li packed-logical
908 Count MMX packed logical instructions.
909 .It Li packed-multiply
910 Count MMX packed multiply instructions.
912 Count MMX packed shift instructions.
914 Count MMX unpack operation instructions.
917 The default is to count all operations.
918 .It Li p6-mmx-sat-instr-exec
919 .Pq Event B1H , Tn "Pentium II" , Tn "Pentium III"
920 Count the number of MMX saturating instructions executed.
921 .It Li p6-mmx-uops-exec
922 .Pq Event B2H , Tn "Pentium II" , Tn "Pentium III"
923 Count the number of MMX micro-ops executed.
926 Count the number of integer and floating-point multiplies, including
927 speculative multiplies.
928 This event is only allocated on counter 1.
929 .It Li p6-partial-rat-stalls
931 Count the number of cycles or events for partial stalls.
932 .It Li p6-resource-stalls
934 Count the number of cycles there was a resource related stall of any kind.
935 .It Li p6-ret-seg-renames
936 .Pq Event D6H , Tn "Pentium II" , Tn "Pentium III"
937 Count the number of segment register rename events retired.
940 Count the number of cycles the store buffer is draining.
941 .It Li p6-seg-reg-renames Op Li ,umask= Ns Ar qualifier
942 .Pq Event D5H , Tn "Pentium II" , Tn "Pentium III"
943 Count the number of segment register renames.
944 An additional qualifier may be specified, and comprises a list of the
945 following keywords separated by
949 .Bl -tag -width indent -compact
951 Count renames for segment register DS.
953 Count renames for segment register ES.
955 Count renames for segment register FS.
957 Count renames for segment register GS.
960 The default is to count operations affecting all segment registers.
961 .It Li p6-seg-rename-stalls
962 .Pq Event D4H , Tn "Pentium II" , Tn "Pentium III"
963 Count the number of segment register renaming stalls.
964 An additional qualifier may be specified, and comprises a list of the
965 following keywords separated by
969 .Bl -tag -width indent -compact
971 Count stalls for segment register DS.
973 Count stalls for segment register ES.
975 Count stalls for segment register FS.
977 Count stalls for segment register GS.
980 The default is to count operations affecting all the segment registers.
981 .It Li p6-segment-reg-loads
983 Count the number of segment register loads.
984 .It Li p6-uops-retired
986 Count the number of micro-ops retired.
988 .Ss Event Name Aliases
989 The following table shows the mapping between the PMC-independent
992 and the underlying hardware events used.
993 .Bl -column "branch-mispredicts" "Description"
994 .It Em Alias Ta Em Event
995 .It Li branches Ta Li p6-br-inst-retired
996 .It Li branch-mispredicts Ta Li p6-br-miss-pred-retired
997 .It Li dc-misses Ta Li p6-dcu-lines-in
998 .It Li ic-misses Ta Li p6-ifu-fetch-miss
999 .It Li instructions Ta Li p6-inst-retired
1000 .It Li interrupts Ta Li p6-hw-int-rx
1001 .It Li unhalted-cycles Ta Li p6-cpu-clk-unhalted
1020 library first appeared in
1025 library was written by
1027 .Aq jkoshy@FreeBSD.org .
projects / FreeBSD / releng / 10.0.git / blob